module IntXbar(
  input   auto_int_in_14_0,
  input   auto_int_in_13_0,
  input   auto_int_in_12_0,
  input   auto_int_in_12_1,
  input   auto_int_in_12_2,
  input   auto_int_in_12_3,
  input   auto_int_in_11_0,
  input   auto_int_in_11_1,
  input   auto_int_in_11_2,
  input   auto_int_in_11_3,
  input   auto_int_in_10_0,
  input   auto_int_in_10_1,
  input   auto_int_in_10_2,
  input   auto_int_in_10_3,
  input   auto_int_in_9_0,
  input   auto_int_in_9_1,
  input   auto_int_in_9_2,
  input   auto_int_in_9_3,
  input   auto_int_in_9_4,
  input   auto_int_in_9_5,
  input   auto_int_in_9_6,
  input   auto_int_in_9_7,
  input   auto_int_in_9_8,
  input   auto_int_in_9_9,
  input   auto_int_in_9_10,
  input   auto_int_in_9_11,
  input   auto_int_in_9_12,
  input   auto_int_in_9_13,
  input   auto_int_in_9_14,
  input   auto_int_in_9_15,
  input   auto_int_in_9_16,
  input   auto_int_in_9_17,
  input   auto_int_in_9_18,
  input   auto_int_in_9_19,
  input   auto_int_in_9_20,
  input   auto_int_in_9_21,
  input   auto_int_in_9_22,
  input   auto_int_in_9_23,
  input   auto_int_in_9_24,
  input   auto_int_in_9_25,
  input   auto_int_in_9_26,
  input   auto_int_in_9_27,
  input   auto_int_in_9_28,
  input   auto_int_in_9_29,
  input   auto_int_in_9_30,
  input   auto_int_in_9_31,
  input   auto_int_in_8_0,
  input   auto_int_in_7_0,
  input   auto_int_in_6_0,
  input   auto_int_in_5_0,
  input   auto_int_in_4_0,
  input   auto_int_in_3_0,
  input   auto_int_in_2_0,
  input   auto_int_in_1_0,
  input   auto_int_in_0_0,
  input   auto_int_in_0_1,
  output  auto_int_out_0,
  output  auto_int_out_1,
  output  auto_int_out_2,
  output  auto_int_out_3,
  output  auto_int_out_4,
  output  auto_int_out_5,
  output  auto_int_out_6,
  output  auto_int_out_7,
  output  auto_int_out_8,
  output  auto_int_out_9,
  output  auto_int_out_10,
  output  auto_int_out_11,
  output  auto_int_out_12,
  output  auto_int_out_13,
  output  auto_int_out_14,
  output  auto_int_out_15,
  output  auto_int_out_16,
  output  auto_int_out_17,
  output  auto_int_out_18,
  output  auto_int_out_19,
  output  auto_int_out_20,
  output  auto_int_out_21,
  output  auto_int_out_22,
  output  auto_int_out_23,
  output  auto_int_out_24,
  output  auto_int_out_25,
  output  auto_int_out_26,
  output  auto_int_out_27,
  output  auto_int_out_28,
  output  auto_int_out_29,
  output  auto_int_out_30,
  output  auto_int_out_31,
  output  auto_int_out_32,
  output  auto_int_out_33,
  output  auto_int_out_34,
  output  auto_int_out_35,
  output  auto_int_out_36,
  output  auto_int_out_37,
  output  auto_int_out_38,
  output  auto_int_out_39,
  output  auto_int_out_40,
  output  auto_int_out_41,
  output  auto_int_out_42,
  output  auto_int_out_43,
  output  auto_int_out_44,
  output  auto_int_out_45,
  output  auto_int_out_46,
  output  auto_int_out_47,
  output  auto_int_out_48,
  output  auto_int_out_49,
  output  auto_int_out_50,
  output  auto_int_out_51,
  output  auto_int_out_52,
  output  auto_int_out_53,
  output  auto_int_out_54,
  output  auto_int_out_55
);
  assign auto_int_out_0 = auto_int_in_0_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_1 = auto_int_in_0_1; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_2 = auto_int_in_1_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_3 = auto_int_in_2_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_4 = auto_int_in_3_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_5 = auto_int_in_4_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_6 = auto_int_in_5_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_7 = auto_int_in_6_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_8 = auto_int_in_7_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_9 = auto_int_in_8_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_10 = auto_int_in_9_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_11 = auto_int_in_9_1; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_12 = auto_int_in_9_2; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_13 = auto_int_in_9_3; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_14 = auto_int_in_9_4; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_15 = auto_int_in_9_5; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_16 = auto_int_in_9_6; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_17 = auto_int_in_9_7; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_18 = auto_int_in_9_8; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_19 = auto_int_in_9_9; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_20 = auto_int_in_9_10; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_21 = auto_int_in_9_11; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_22 = auto_int_in_9_12; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_23 = auto_int_in_9_13; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_24 = auto_int_in_9_14; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_25 = auto_int_in_9_15; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_26 = auto_int_in_9_16; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_27 = auto_int_in_9_17; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_28 = auto_int_in_9_18; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_29 = auto_int_in_9_19; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_30 = auto_int_in_9_20; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_31 = auto_int_in_9_21; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_32 = auto_int_in_9_22; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_33 = auto_int_in_9_23; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_34 = auto_int_in_9_24; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_35 = auto_int_in_9_25; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_36 = auto_int_in_9_26; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_37 = auto_int_in_9_27; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_38 = auto_int_in_9_28; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_39 = auto_int_in_9_29; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_40 = auto_int_in_9_30; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_41 = auto_int_in_9_31; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_42 = auto_int_in_10_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_43 = auto_int_in_10_1; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_44 = auto_int_in_10_2; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_45 = auto_int_in_10_3; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_46 = auto_int_in_11_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_47 = auto_int_in_11_1; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_48 = auto_int_in_11_2; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_49 = auto_int_in_11_3; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_50 = auto_int_in_12_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_51 = auto_int_in_12_1; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_52 = auto_int_in_12_2; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_53 = auto_int_in_12_3; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_54 = auto_int_in_13_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_55 = auto_int_in_14_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module InterruptBusWrapper(
  input   auto_int_bus_int_in_14_0,
  input   auto_int_bus_int_in_13_0,
  input   auto_int_bus_int_in_12_0,
  input   auto_int_bus_int_in_12_1,
  input   auto_int_bus_int_in_12_2,
  input   auto_int_bus_int_in_12_3,
  input   auto_int_bus_int_in_11_0,
  input   auto_int_bus_int_in_11_1,
  input   auto_int_bus_int_in_11_2,
  input   auto_int_bus_int_in_11_3,
  input   auto_int_bus_int_in_10_0,
  input   auto_int_bus_int_in_10_1,
  input   auto_int_bus_int_in_10_2,
  input   auto_int_bus_int_in_10_3,
  input   auto_int_bus_int_in_9_0,
  input   auto_int_bus_int_in_9_1,
  input   auto_int_bus_int_in_9_2,
  input   auto_int_bus_int_in_9_3,
  input   auto_int_bus_int_in_9_4,
  input   auto_int_bus_int_in_9_5,
  input   auto_int_bus_int_in_9_6,
  input   auto_int_bus_int_in_9_7,
  input   auto_int_bus_int_in_9_8,
  input   auto_int_bus_int_in_9_9,
  input   auto_int_bus_int_in_9_10,
  input   auto_int_bus_int_in_9_11,
  input   auto_int_bus_int_in_9_12,
  input   auto_int_bus_int_in_9_13,
  input   auto_int_bus_int_in_9_14,
  input   auto_int_bus_int_in_9_15,
  input   auto_int_bus_int_in_9_16,
  input   auto_int_bus_int_in_9_17,
  input   auto_int_bus_int_in_9_18,
  input   auto_int_bus_int_in_9_19,
  input   auto_int_bus_int_in_9_20,
  input   auto_int_bus_int_in_9_21,
  input   auto_int_bus_int_in_9_22,
  input   auto_int_bus_int_in_9_23,
  input   auto_int_bus_int_in_9_24,
  input   auto_int_bus_int_in_9_25,
  input   auto_int_bus_int_in_9_26,
  input   auto_int_bus_int_in_9_27,
  input   auto_int_bus_int_in_9_28,
  input   auto_int_bus_int_in_9_29,
  input   auto_int_bus_int_in_9_30,
  input   auto_int_bus_int_in_9_31,
  input   auto_int_bus_int_in_8_0,
  input   auto_int_bus_int_in_7_0,
  input   auto_int_bus_int_in_6_0,
  input   auto_int_bus_int_in_5_0,
  input   auto_int_bus_int_in_4_0,
  input   auto_int_bus_int_in_3_0,
  input   auto_int_bus_int_in_2_0,
  input   auto_int_bus_int_in_1_0,
  input   auto_int_bus_int_in_0_0,
  input   auto_int_bus_int_in_0_1,
  output  auto_int_bus_int_out_0,
  output  auto_int_bus_int_out_1,
  output  auto_int_bus_int_out_2,
  output  auto_int_bus_int_out_3,
  output  auto_int_bus_int_out_4,
  output  auto_int_bus_int_out_5,
  output  auto_int_bus_int_out_6,
  output  auto_int_bus_int_out_7,
  output  auto_int_bus_int_out_8,
  output  auto_int_bus_int_out_9,
  output  auto_int_bus_int_out_10,
  output  auto_int_bus_int_out_11,
  output  auto_int_bus_int_out_12,
  output  auto_int_bus_int_out_13,
  output  auto_int_bus_int_out_14,
  output  auto_int_bus_int_out_15,
  output  auto_int_bus_int_out_16,
  output  auto_int_bus_int_out_17,
  output  auto_int_bus_int_out_18,
  output  auto_int_bus_int_out_19,
  output  auto_int_bus_int_out_20,
  output  auto_int_bus_int_out_21,
  output  auto_int_bus_int_out_22,
  output  auto_int_bus_int_out_23,
  output  auto_int_bus_int_out_24,
  output  auto_int_bus_int_out_25,
  output  auto_int_bus_int_out_26,
  output  auto_int_bus_int_out_27,
  output  auto_int_bus_int_out_28,
  output  auto_int_bus_int_out_29,
  output  auto_int_bus_int_out_30,
  output  auto_int_bus_int_out_31,
  output  auto_int_bus_int_out_32,
  output  auto_int_bus_int_out_33,
  output  auto_int_bus_int_out_34,
  output  auto_int_bus_int_out_35,
  output  auto_int_bus_int_out_36,
  output  auto_int_bus_int_out_37,
  output  auto_int_bus_int_out_38,
  output  auto_int_bus_int_out_39,
  output  auto_int_bus_int_out_40,
  output  auto_int_bus_int_out_41,
  output  auto_int_bus_int_out_42,
  output  auto_int_bus_int_out_43,
  output  auto_int_bus_int_out_44,
  output  auto_int_bus_int_out_45,
  output  auto_int_bus_int_out_46,
  output  auto_int_bus_int_out_47,
  output  auto_int_bus_int_out_48,
  output  auto_int_bus_int_out_49,
  output  auto_int_bus_int_out_50,
  output  auto_int_bus_int_out_51,
  output  auto_int_bus_int_out_52,
  output  auto_int_bus_int_out_53,
  output  auto_int_bus_int_out_54,
  output  auto_int_bus_int_out_55
);
  wire  int_bus_auto_int_in_14_0; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_13_0; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_12_0; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_12_1; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_12_2; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_12_3; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_11_0; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_11_1; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_11_2; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_11_3; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_10_0; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_10_1; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_10_2; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_10_3; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_9_0; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_9_1; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_9_2; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_9_3; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_9_4; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_9_5; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_9_6; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_9_7; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_9_8; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_9_9; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_9_10; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_9_11; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_9_12; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_9_13; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_9_14; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_9_15; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_9_16; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_9_17; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_9_18; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_9_19; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_9_20; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_9_21; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_9_22; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_9_23; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_9_24; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_9_25; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_9_26; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_9_27; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_9_28; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_9_29; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_9_30; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_9_31; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_8_0; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_7_0; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_6_0; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_5_0; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_4_0; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_3_0; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_2_0; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_1_0; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_0_0; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_in_0_1; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_0; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_1; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_2; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_3; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_4; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_5; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_6; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_7; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_8; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_9; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_10; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_11; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_12; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_13; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_14; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_15; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_16; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_17; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_18; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_19; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_20; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_21; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_22; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_23; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_24; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_25; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_26; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_27; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_28; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_29; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_30; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_31; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_32; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_33; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_34; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_35; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_36; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_37; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_38; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_39; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_40; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_41; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_42; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_43; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_44; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_45; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_46; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_47; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_48; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_49; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_50; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_51; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_52; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_53; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_54; // @[InterruptBus.scala 14:27]
  wire  int_bus_auto_int_out_55; // @[InterruptBus.scala 14:27]
  IntXbar int_bus ( // @[InterruptBus.scala 14:27]
    .auto_int_in_14_0(int_bus_auto_int_in_14_0),
    .auto_int_in_13_0(int_bus_auto_int_in_13_0),
    .auto_int_in_12_0(int_bus_auto_int_in_12_0),
    .auto_int_in_12_1(int_bus_auto_int_in_12_1),
    .auto_int_in_12_2(int_bus_auto_int_in_12_2),
    .auto_int_in_12_3(int_bus_auto_int_in_12_3),
    .auto_int_in_11_0(int_bus_auto_int_in_11_0),
    .auto_int_in_11_1(int_bus_auto_int_in_11_1),
    .auto_int_in_11_2(int_bus_auto_int_in_11_2),
    .auto_int_in_11_3(int_bus_auto_int_in_11_3),
    .auto_int_in_10_0(int_bus_auto_int_in_10_0),
    .auto_int_in_10_1(int_bus_auto_int_in_10_1),
    .auto_int_in_10_2(int_bus_auto_int_in_10_2),
    .auto_int_in_10_3(int_bus_auto_int_in_10_3),
    .auto_int_in_9_0(int_bus_auto_int_in_9_0),
    .auto_int_in_9_1(int_bus_auto_int_in_9_1),
    .auto_int_in_9_2(int_bus_auto_int_in_9_2),
    .auto_int_in_9_3(int_bus_auto_int_in_9_3),
    .auto_int_in_9_4(int_bus_auto_int_in_9_4),
    .auto_int_in_9_5(int_bus_auto_int_in_9_5),
    .auto_int_in_9_6(int_bus_auto_int_in_9_6),
    .auto_int_in_9_7(int_bus_auto_int_in_9_7),
    .auto_int_in_9_8(int_bus_auto_int_in_9_8),
    .auto_int_in_9_9(int_bus_auto_int_in_9_9),
    .auto_int_in_9_10(int_bus_auto_int_in_9_10),
    .auto_int_in_9_11(int_bus_auto_int_in_9_11),
    .auto_int_in_9_12(int_bus_auto_int_in_9_12),
    .auto_int_in_9_13(int_bus_auto_int_in_9_13),
    .auto_int_in_9_14(int_bus_auto_int_in_9_14),
    .auto_int_in_9_15(int_bus_auto_int_in_9_15),
    .auto_int_in_9_16(int_bus_auto_int_in_9_16),
    .auto_int_in_9_17(int_bus_auto_int_in_9_17),
    .auto_int_in_9_18(int_bus_auto_int_in_9_18),
    .auto_int_in_9_19(int_bus_auto_int_in_9_19),
    .auto_int_in_9_20(int_bus_auto_int_in_9_20),
    .auto_int_in_9_21(int_bus_auto_int_in_9_21),
    .auto_int_in_9_22(int_bus_auto_int_in_9_22),
    .auto_int_in_9_23(int_bus_auto_int_in_9_23),
    .auto_int_in_9_24(int_bus_auto_int_in_9_24),
    .auto_int_in_9_25(int_bus_auto_int_in_9_25),
    .auto_int_in_9_26(int_bus_auto_int_in_9_26),
    .auto_int_in_9_27(int_bus_auto_int_in_9_27),
    .auto_int_in_9_28(int_bus_auto_int_in_9_28),
    .auto_int_in_9_29(int_bus_auto_int_in_9_29),
    .auto_int_in_9_30(int_bus_auto_int_in_9_30),
    .auto_int_in_9_31(int_bus_auto_int_in_9_31),
    .auto_int_in_8_0(int_bus_auto_int_in_8_0),
    .auto_int_in_7_0(int_bus_auto_int_in_7_0),
    .auto_int_in_6_0(int_bus_auto_int_in_6_0),
    .auto_int_in_5_0(int_bus_auto_int_in_5_0),
    .auto_int_in_4_0(int_bus_auto_int_in_4_0),
    .auto_int_in_3_0(int_bus_auto_int_in_3_0),
    .auto_int_in_2_0(int_bus_auto_int_in_2_0),
    .auto_int_in_1_0(int_bus_auto_int_in_1_0),
    .auto_int_in_0_0(int_bus_auto_int_in_0_0),
    .auto_int_in_0_1(int_bus_auto_int_in_0_1),
    .auto_int_out_0(int_bus_auto_int_out_0),
    .auto_int_out_1(int_bus_auto_int_out_1),
    .auto_int_out_2(int_bus_auto_int_out_2),
    .auto_int_out_3(int_bus_auto_int_out_3),
    .auto_int_out_4(int_bus_auto_int_out_4),
    .auto_int_out_5(int_bus_auto_int_out_5),
    .auto_int_out_6(int_bus_auto_int_out_6),
    .auto_int_out_7(int_bus_auto_int_out_7),
    .auto_int_out_8(int_bus_auto_int_out_8),
    .auto_int_out_9(int_bus_auto_int_out_9),
    .auto_int_out_10(int_bus_auto_int_out_10),
    .auto_int_out_11(int_bus_auto_int_out_11),
    .auto_int_out_12(int_bus_auto_int_out_12),
    .auto_int_out_13(int_bus_auto_int_out_13),
    .auto_int_out_14(int_bus_auto_int_out_14),
    .auto_int_out_15(int_bus_auto_int_out_15),
    .auto_int_out_16(int_bus_auto_int_out_16),
    .auto_int_out_17(int_bus_auto_int_out_17),
    .auto_int_out_18(int_bus_auto_int_out_18),
    .auto_int_out_19(int_bus_auto_int_out_19),
    .auto_int_out_20(int_bus_auto_int_out_20),
    .auto_int_out_21(int_bus_auto_int_out_21),
    .auto_int_out_22(int_bus_auto_int_out_22),
    .auto_int_out_23(int_bus_auto_int_out_23),
    .auto_int_out_24(int_bus_auto_int_out_24),
    .auto_int_out_25(int_bus_auto_int_out_25),
    .auto_int_out_26(int_bus_auto_int_out_26),
    .auto_int_out_27(int_bus_auto_int_out_27),
    .auto_int_out_28(int_bus_auto_int_out_28),
    .auto_int_out_29(int_bus_auto_int_out_29),
    .auto_int_out_30(int_bus_auto_int_out_30),
    .auto_int_out_31(int_bus_auto_int_out_31),
    .auto_int_out_32(int_bus_auto_int_out_32),
    .auto_int_out_33(int_bus_auto_int_out_33),
    .auto_int_out_34(int_bus_auto_int_out_34),
    .auto_int_out_35(int_bus_auto_int_out_35),
    .auto_int_out_36(int_bus_auto_int_out_36),
    .auto_int_out_37(int_bus_auto_int_out_37),
    .auto_int_out_38(int_bus_auto_int_out_38),
    .auto_int_out_39(int_bus_auto_int_out_39),
    .auto_int_out_40(int_bus_auto_int_out_40),
    .auto_int_out_41(int_bus_auto_int_out_41),
    .auto_int_out_42(int_bus_auto_int_out_42),
    .auto_int_out_43(int_bus_auto_int_out_43),
    .auto_int_out_44(int_bus_auto_int_out_44),
    .auto_int_out_45(int_bus_auto_int_out_45),
    .auto_int_out_46(int_bus_auto_int_out_46),
    .auto_int_out_47(int_bus_auto_int_out_47),
    .auto_int_out_48(int_bus_auto_int_out_48),
    .auto_int_out_49(int_bus_auto_int_out_49),
    .auto_int_out_50(int_bus_auto_int_out_50),
    .auto_int_out_51(int_bus_auto_int_out_51),
    .auto_int_out_52(int_bus_auto_int_out_52),
    .auto_int_out_53(int_bus_auto_int_out_53),
    .auto_int_out_54(int_bus_auto_int_out_54),
    .auto_int_out_55(int_bus_auto_int_out_55)
  );
  assign auto_int_bus_int_out_0 = int_bus_auto_int_out_0; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_1 = int_bus_auto_int_out_1; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_2 = int_bus_auto_int_out_2; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_3 = int_bus_auto_int_out_3; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_4 = int_bus_auto_int_out_4; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_5 = int_bus_auto_int_out_5; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_6 = int_bus_auto_int_out_6; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_7 = int_bus_auto_int_out_7; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_8 = int_bus_auto_int_out_8; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_9 = int_bus_auto_int_out_9; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_10 = int_bus_auto_int_out_10; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_11 = int_bus_auto_int_out_11; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_12 = int_bus_auto_int_out_12; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_13 = int_bus_auto_int_out_13; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_14 = int_bus_auto_int_out_14; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_15 = int_bus_auto_int_out_15; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_16 = int_bus_auto_int_out_16; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_17 = int_bus_auto_int_out_17; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_18 = int_bus_auto_int_out_18; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_19 = int_bus_auto_int_out_19; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_20 = int_bus_auto_int_out_20; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_21 = int_bus_auto_int_out_21; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_22 = int_bus_auto_int_out_22; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_23 = int_bus_auto_int_out_23; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_24 = int_bus_auto_int_out_24; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_25 = int_bus_auto_int_out_25; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_26 = int_bus_auto_int_out_26; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_27 = int_bus_auto_int_out_27; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_28 = int_bus_auto_int_out_28; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_29 = int_bus_auto_int_out_29; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_30 = int_bus_auto_int_out_30; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_31 = int_bus_auto_int_out_31; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_32 = int_bus_auto_int_out_32; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_33 = int_bus_auto_int_out_33; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_34 = int_bus_auto_int_out_34; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_35 = int_bus_auto_int_out_35; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_36 = int_bus_auto_int_out_36; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_37 = int_bus_auto_int_out_37; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_38 = int_bus_auto_int_out_38; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_39 = int_bus_auto_int_out_39; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_40 = int_bus_auto_int_out_40; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_41 = int_bus_auto_int_out_41; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_42 = int_bus_auto_int_out_42; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_43 = int_bus_auto_int_out_43; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_44 = int_bus_auto_int_out_44; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_45 = int_bus_auto_int_out_45; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_46 = int_bus_auto_int_out_46; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_47 = int_bus_auto_int_out_47; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_48 = int_bus_auto_int_out_48; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_49 = int_bus_auto_int_out_49; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_50 = int_bus_auto_int_out_50; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_51 = int_bus_auto_int_out_51; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_52 = int_bus_auto_int_out_52; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_53 = int_bus_auto_int_out_53; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_54 = int_bus_auto_int_out_54; // @[LazyModule.scala 311:12]
  assign auto_int_bus_int_out_55 = int_bus_auto_int_out_55; // @[LazyModule.scala 311:12]
  assign int_bus_auto_int_in_14_0 = auto_int_bus_int_in_14_0; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_13_0 = auto_int_bus_int_in_13_0; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_12_0 = auto_int_bus_int_in_12_0; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_12_1 = auto_int_bus_int_in_12_1; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_12_2 = auto_int_bus_int_in_12_2; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_12_3 = auto_int_bus_int_in_12_3; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_11_0 = auto_int_bus_int_in_11_0; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_11_1 = auto_int_bus_int_in_11_1; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_11_2 = auto_int_bus_int_in_11_2; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_11_3 = auto_int_bus_int_in_11_3; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_10_0 = auto_int_bus_int_in_10_0; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_10_1 = auto_int_bus_int_in_10_1; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_10_2 = auto_int_bus_int_in_10_2; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_10_3 = auto_int_bus_int_in_10_3; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_9_0 = auto_int_bus_int_in_9_0; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_9_1 = auto_int_bus_int_in_9_1; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_9_2 = auto_int_bus_int_in_9_2; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_9_3 = auto_int_bus_int_in_9_3; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_9_4 = auto_int_bus_int_in_9_4; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_9_5 = auto_int_bus_int_in_9_5; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_9_6 = auto_int_bus_int_in_9_6; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_9_7 = auto_int_bus_int_in_9_7; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_9_8 = auto_int_bus_int_in_9_8; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_9_9 = auto_int_bus_int_in_9_9; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_9_10 = auto_int_bus_int_in_9_10; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_9_11 = auto_int_bus_int_in_9_11; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_9_12 = auto_int_bus_int_in_9_12; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_9_13 = auto_int_bus_int_in_9_13; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_9_14 = auto_int_bus_int_in_9_14; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_9_15 = auto_int_bus_int_in_9_15; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_9_16 = auto_int_bus_int_in_9_16; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_9_17 = auto_int_bus_int_in_9_17; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_9_18 = auto_int_bus_int_in_9_18; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_9_19 = auto_int_bus_int_in_9_19; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_9_20 = auto_int_bus_int_in_9_20; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_9_21 = auto_int_bus_int_in_9_21; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_9_22 = auto_int_bus_int_in_9_22; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_9_23 = auto_int_bus_int_in_9_23; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_9_24 = auto_int_bus_int_in_9_24; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_9_25 = auto_int_bus_int_in_9_25; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_9_26 = auto_int_bus_int_in_9_26; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_9_27 = auto_int_bus_int_in_9_27; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_9_28 = auto_int_bus_int_in_9_28; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_9_29 = auto_int_bus_int_in_9_29; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_9_30 = auto_int_bus_int_in_9_30; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_9_31 = auto_int_bus_int_in_9_31; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_8_0 = auto_int_bus_int_in_8_0; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_7_0 = auto_int_bus_int_in_7_0; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_6_0 = auto_int_bus_int_in_6_0; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_5_0 = auto_int_bus_int_in_5_0; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_4_0 = auto_int_bus_int_in_4_0; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_3_0 = auto_int_bus_int_in_3_0; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_2_0 = auto_int_bus_int_in_2_0; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_1_0 = auto_int_bus_int_in_1_0; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_0_0 = auto_int_bus_int_in_0_0; // @[LazyModule.scala 309:16]
  assign int_bus_auto_int_in_0_1 = auto_int_bus_int_in_0_1; // @[LazyModule.scala 309:16]
endmodule
module SimpleClockGroupSource(
  input   clock,
  input   reset,
  output  auto_out_member_subsystem_sbus_5_clock,
  output  auto_out_member_subsystem_sbus_5_reset,
  output  auto_out_member_subsystem_sbus_4_clock,
  output  auto_out_member_subsystem_sbus_4_reset,
  output  auto_out_member_subsystem_sbus_3_clock,
  output  auto_out_member_subsystem_sbus_3_reset,
  output  auto_out_member_subsystem_sbus_2_clock,
  output  auto_out_member_subsystem_sbus_2_reset,
  output  auto_out_member_subsystem_sbus_1_clock,
  output  auto_out_member_subsystem_sbus_1_reset,
  output  auto_out_member_subsystem_sbus_0_clock,
  output  auto_out_member_subsystem_sbus_0_reset
);
  assign auto_out_member_subsystem_sbus_5_clock = clock; // @[Nodes.scala 1207:84 ClockGroup.scala 72:17]
  assign auto_out_member_subsystem_sbus_5_reset = reset; // @[Nodes.scala 1207:84 ClockGroup.scala 72:35]
  assign auto_out_member_subsystem_sbus_4_clock = clock; // @[Nodes.scala 1207:84 ClockGroup.scala 72:17]
  assign auto_out_member_subsystem_sbus_4_reset = reset; // @[Nodes.scala 1207:84 ClockGroup.scala 72:35]
  assign auto_out_member_subsystem_sbus_3_clock = clock; // @[Nodes.scala 1207:84 ClockGroup.scala 72:17]
  assign auto_out_member_subsystem_sbus_3_reset = reset; // @[Nodes.scala 1207:84 ClockGroup.scala 72:35]
  assign auto_out_member_subsystem_sbus_2_clock = clock; // @[Nodes.scala 1207:84 ClockGroup.scala 72:17]
  assign auto_out_member_subsystem_sbus_2_reset = reset; // @[Nodes.scala 1207:84 ClockGroup.scala 72:35]
  assign auto_out_member_subsystem_sbus_1_clock = clock; // @[Nodes.scala 1207:84 ClockGroup.scala 72:17]
  assign auto_out_member_subsystem_sbus_1_reset = reset; // @[Nodes.scala 1207:84 ClockGroup.scala 72:35]
  assign auto_out_member_subsystem_sbus_0_clock = clock; // @[Nodes.scala 1207:84 ClockGroup.scala 72:17]
  assign auto_out_member_subsystem_sbus_0_reset = reset; // @[Nodes.scala 1207:84 ClockGroup.scala 72:35]
endmodule
module ClockGroupAggregator(
  input   auto_in_member_subsystem_sbus_5_clock,
  input   auto_in_member_subsystem_sbus_5_reset,
  input   auto_in_member_subsystem_sbus_4_clock,
  input   auto_in_member_subsystem_sbus_4_reset,
  input   auto_in_member_subsystem_sbus_3_clock,
  input   auto_in_member_subsystem_sbus_3_reset,
  input   auto_in_member_subsystem_sbus_2_clock,
  input   auto_in_member_subsystem_sbus_2_reset,
  input   auto_in_member_subsystem_sbus_1_clock,
  input   auto_in_member_subsystem_sbus_1_reset,
  input   auto_in_member_subsystem_sbus_0_clock,
  input   auto_in_member_subsystem_sbus_0_reset,
  output  auto_out_3_member_subsystem_l2_1_clock,
  output  auto_out_3_member_subsystem_l2_1_reset,
  output  auto_out_3_member_subsystem_l2_0_clock,
  output  auto_out_3_member_subsystem_l2_0_reset,
  output  auto_out_2_member_subsystem_fbus_0_clock,
  output  auto_out_2_member_subsystem_fbus_0_reset,
  output  auto_out_1_member_subsystem_cbus_1_clock,
  output  auto_out_1_member_subsystem_cbus_1_reset,
  output  auto_out_1_member_subsystem_cbus_0_clock,
  output  auto_out_1_member_subsystem_cbus_0_reset,
  output  auto_out_0_member_subsystem_sbus_0_clock,
  output  auto_out_0_member_subsystem_sbus_0_reset
);
  assign auto_out_3_member_subsystem_l2_1_clock = auto_in_member_subsystem_sbus_5_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_3_member_subsystem_l2_1_reset = auto_in_member_subsystem_sbus_5_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_3_member_subsystem_l2_0_clock = auto_in_member_subsystem_sbus_4_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_3_member_subsystem_l2_0_reset = auto_in_member_subsystem_sbus_4_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_2_member_subsystem_fbus_0_clock = auto_in_member_subsystem_sbus_3_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_2_member_subsystem_fbus_0_reset = auto_in_member_subsystem_sbus_3_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_member_subsystem_cbus_1_clock = auto_in_member_subsystem_sbus_2_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_member_subsystem_cbus_1_reset = auto_in_member_subsystem_sbus_2_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_member_subsystem_cbus_0_clock = auto_in_member_subsystem_sbus_1_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_member_subsystem_cbus_0_reset = auto_in_member_subsystem_sbus_1_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_0_member_subsystem_sbus_0_clock = auto_in_member_subsystem_sbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_0_member_subsystem_sbus_0_reset = auto_in_member_subsystem_sbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module ClockGroup(
  input   auto_in_member_subsystem_sbus_0_clock,
  input   auto_in_member_subsystem_sbus_0_reset,
  output  auto_out_clock,
  output  auto_out_reset
);
  assign auto_out_clock = auto_in_member_subsystem_sbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_reset = auto_in_member_subsystem_sbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module FixedClockBroadcast(
  input   auto_in_clock,
  input   auto_in_reset,
  output  auto_out_2_clock,
  output  auto_out_2_reset,
  output  auto_out_0_clock,
  output  auto_out_0_reset
);
  assign auto_out_2_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_2_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_0_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_0_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module TLMonitor(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [3:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [30:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_b_ready,
  input         io_in_b_valid,
  input  [1:0]  io_in_b_bits_param,
  input  [30:0] io_in_b_bits_address,
  input         io_in_c_ready,
  input         io_in_c_valid,
  input  [2:0]  io_in_c_bits_opcode,
  input  [2:0]  io_in_c_bits_param,
  input  [3:0]  io_in_c_bits_size,
  input  [1:0]  io_in_c_bits_source,
  input  [30:0] io_in_c_bits_address,
  input         io_in_c_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_param,
  input  [3:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source,
  input  [1:0]  io_in_d_bits_sink,
  input         io_in_d_bits_denied,
  input         io_in_d_bits_corrupt,
  input         io_in_e_valid,
  input  [1:0]  io_in_e_bits_sink
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [31:0] _RAND_33;
  reg [31:0] _RAND_34;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [26:0] _is_aligned_mask_T_1 = 27'hfff << io_in_a_bits_size; // @[package.scala 234:77]
  wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1[11:0]; // @[package.scala 234:46]
  wire [30:0] _GEN_86 = {{19'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [30:0] _is_aligned_T = io_in_a_bits_address & _GEN_86; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 31'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 4'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire [31:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire  _T_35 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42]
  wire  _T_42 = _T_35 & source_ok; // @[Parameters.scala 1160:30]
  wire [31:0] _T_48 = $signed(_T_7) & -32'sh10001000; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_50 = io_in_a_bits_address ^ 31'h3000; // @[Parameters.scala 137:31]
  wire [31:0] _T_51 = {1'b0,$signed(_T_50)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_53 = $signed(_T_51) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _T_54 = $signed(_T_53) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_55 = io_in_a_bits_address ^ 31'h10000; // @[Parameters.scala 137:31]
  wire [31:0] _T_56 = {1'b0,$signed(_T_55)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_58 = $signed(_T_56) & -32'sh10000; // @[Parameters.scala 137:52]
  wire  _T_59 = $signed(_T_58) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_60 = io_in_a_bits_address ^ 31'h2000000; // @[Parameters.scala 137:31]
  wire [31:0] _T_61 = {1'b0,$signed(_T_60)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_63 = $signed(_T_61) & -32'sh10000; // @[Parameters.scala 137:52]
  wire  _T_64 = $signed(_T_63) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_65 = io_in_a_bits_address ^ 31'h8000000; // @[Parameters.scala 137:31]
  wire [31:0] _T_66 = {1'b0,$signed(_T_65)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_68 = $signed(_T_66) & -32'sh4000; // @[Parameters.scala 137:52]
  wire  _T_69 = $signed(_T_68) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_70 = io_in_a_bits_address ^ 31'hc000000; // @[Parameters.scala 137:31]
  wire [31:0] _T_71 = {1'b0,$signed(_T_70)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_73 = $signed(_T_71) & -32'sh4000000; // @[Parameters.scala 137:52]
  wire  _T_74 = $signed(_T_73) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_75 = io_in_a_bits_address ^ 31'h10012000; // @[Parameters.scala 137:31]
  wire [31:0] _T_76 = {1'b0,$signed(_T_75)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_78 = $signed(_T_76) & -32'sh2000; // @[Parameters.scala 137:52]
  wire  _T_79 = $signed(_T_78) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_80 = io_in_a_bits_address ^ 31'h10014000; // @[Parameters.scala 137:31]
  wire [31:0] _T_81 = {1'b0,$signed(_T_80)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_83 = $signed(_T_81) & -32'sh2000; // @[Parameters.scala 137:52]
  wire  _T_84 = $signed(_T_83) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_85 = io_in_a_bits_address ^ 31'h10016000; // @[Parameters.scala 137:31]
  wire [31:0] _T_86 = {1'b0,$signed(_T_85)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_88 = $signed(_T_86) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _T_89 = $signed(_T_88) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_90 = io_in_a_bits_address ^ 31'h10023000; // @[Parameters.scala 137:31]
  wire [31:0] _T_91 = {1'b0,$signed(_T_90)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_93 = $signed(_T_91) & -32'sh11000; // @[Parameters.scala 137:52]
  wire  _T_94 = $signed(_T_93) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_95 = io_in_a_bits_address ^ 31'h10024000; // @[Parameters.scala 137:31]
  wire [31:0] _T_96 = {1'b0,$signed(_T_95)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_98 = $signed(_T_96) & -32'sh12000; // @[Parameters.scala 137:52]
  wire  _T_99 = $signed(_T_98) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_100 = io_in_a_bits_address ^ 31'h10026000; // @[Parameters.scala 137:31]
  wire [31:0] _T_101 = {1'b0,$signed(_T_100)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_103 = $signed(_T_101) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _T_104 = $signed(_T_103) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_105 = io_in_a_bits_address ^ 31'h10043000; // @[Parameters.scala 137:31]
  wire [31:0] _T_106 = {1'b0,$signed(_T_105)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_108 = $signed(_T_106) & -32'sh11000; // @[Parameters.scala 137:52]
  wire  _T_109 = $signed(_T_108) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_110 = io_in_a_bits_address ^ 31'h20000000; // @[Parameters.scala 137:31]
  wire [31:0] _T_111 = {1'b0,$signed(_T_110)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_113 = $signed(_T_111) & -32'sh20000000; // @[Parameters.scala 137:52]
  wire  _T_114 = $signed(_T_113) == 32'sh0; // @[Parameters.scala 137:67]
  wire  _T_130 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42]
  wire [30:0] _T_133 = io_in_a_bits_address ^ 31'h40000000; // @[Parameters.scala 137:31]
  wire [31:0] _T_134 = {1'b0,$signed(_T_133)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_136 = $signed(_T_134) & -32'sh20000000; // @[Parameters.scala 137:52]
  wire  _T_137 = $signed(_T_136) == 32'sh0; // @[Parameters.scala 137:67]
  wire  _T_138 = _T_130 & _T_137; // @[Parameters.scala 670:56]
  wire  _T_141 = _T_42 & _T_138; // @[Monitor.scala 82:72]
  wire  _T_148 = 4'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_149 = _source_ok_T & _T_148; // @[Mux.scala 27:73]
  wire  _T_246 = _T_49 | _T_54 | _T_59 | _T_64 | _T_69 | _T_74 | _T_79 | _T_84 | _T_89 | _T_94 | _T_99 | _T_104 | _T_109
     | _T_114 | _T_137; // @[Parameters.scala 671:42]
  wire  _T_247 = _T_35 & _T_246; // @[Parameters.scala 670:56]
  wire  _T_249 = _T_149 & _T_247; // @[Monitor.scala 83:78]
  wire  _T_263 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_267 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_268 = _T_267 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_272 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_276 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_510 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_523 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_546 = _T_35 & _T_54; // @[Parameters.scala 670:56]
  wire  _T_633 = _T_49 | _T_59 | _T_64 | _T_69 | _T_74 | _T_79 | _T_84 | _T_89 | _T_94 | _T_99 | _T_104 | _T_109 |
    _T_114 | _T_137; // @[Parameters.scala 671:42]
  wire  _T_634 = _T_130 & _T_633; // @[Parameters.scala 670:56]
  wire  _T_636 = _T_546 | _T_634; // @[Parameters.scala 672:30]
  wire  _T_646 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_650 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_658 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_752 = _T_49 | _T_64 | _T_69 | _T_74 | _T_79 | _T_84 | _T_89 | _T_94 | _T_99 | _T_104 | _T_109; // @[Parameters.scala 671:42]
  wire  _T_753 = _T_49 | _T_64 | _T_69 | _T_74 | _T_79 | _T_84 | _T_89 | _T_94 | _T_99 | _T_104 | _T_109 | _T_137; // @[Parameters.scala 671:42]
  wire  _T_754 = _T_130 & _T_753; // @[Parameters.scala 670:56]
  wire  _T_769 = _T_546 | _T_754; // @[Parameters.scala 672:30]
  wire  _T_771 = _T_42 & _T_769; // @[Monitor.scala 115:71]
  wire  _T_789 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire  _T_879 = _T_130 & _T_752; // @[Parameters.scala 670:56]
  wire  _T_900 = _T_546 | _T_879; // @[Parameters.scala 672:30]
  wire  _T_902 = _T_42 & _T_900; // @[Monitor.scala 123:74]
  wire [3:0] _T_916 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_917 = io_in_a_bits_mask & _T_916; // @[Monitor.scala 127:31]
  wire  _T_918 = _T_917 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_922 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_934 = io_in_a_bits_size <= 4'h2; // @[Parameters.scala 92:42]
  wire  _T_1007 = _T_49 | _T_54 | _T_64 | _T_69 | _T_74 | _T_79 | _T_84 | _T_89 | _T_94 | _T_99 | _T_104 | _T_109; // @[Parameters.scala 671:42]
  wire  _T_1008 = _T_934 & _T_1007; // @[Parameters.scala 670:56]
  wire  _T_1030 = _T_42 & _T_1008; // @[Monitor.scala 131:74]
  wire  _T_1040 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_1048 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_1166 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_1174 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_1282 = _T_42 & _T_546; // @[Monitor.scala 147:68]
  wire  _T_1292 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_1304 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  _T_1308 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_1312 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 312:27]
  wire  _T_1316 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
  wire  _T_1320 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
  wire  _T_1324 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
  wire  _T_1328 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_1339 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
  wire  _T_1343 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
  wire  _T_1356 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_1376 = _T_1324 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
  wire  _T_1385 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_1402 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_1420 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire [31:0] _T_1444 = {1'b0,$signed(io_in_b_bits_address)}; // @[Parameters.scala 137:49]
  wire [30:0] _address_ok_T = io_in_b_bits_address ^ 31'h3000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_1 = {1'b0,$signed(_address_ok_T)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_3 = $signed(_address_ok_T_1) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_4 = $signed(_address_ok_T_3) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_5 = io_in_b_bits_address ^ 31'h10013000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_6 = {1'b0,$signed(_address_ok_T_5)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_8 = $signed(_address_ok_T_6) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_9 = $signed(_address_ok_T_8) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_10 = io_in_b_bits_address ^ 31'h10023000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_11 = {1'b0,$signed(_address_ok_T_10)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_13 = $signed(_address_ok_T_11) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_14 = $signed(_address_ok_T_13) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_15 = io_in_b_bits_address ^ 31'h10033000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_16 = {1'b0,$signed(_address_ok_T_15)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_18 = $signed(_address_ok_T_16) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_19 = $signed(_address_ok_T_18) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_20 = io_in_b_bits_address ^ 31'h10043000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_21 = {1'b0,$signed(_address_ok_T_20)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_23 = $signed(_address_ok_T_21) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_24 = $signed(_address_ok_T_23) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_25 = io_in_b_bits_address ^ 31'h10053000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_26 = {1'b0,$signed(_address_ok_T_25)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_28 = $signed(_address_ok_T_26) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_29 = $signed(_address_ok_T_28) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_30 = io_in_b_bits_address ^ 31'h10014000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_31 = {1'b0,$signed(_address_ok_T_30)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_33 = $signed(_address_ok_T_31) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_34 = $signed(_address_ok_T_33) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_35 = io_in_b_bits_address ^ 31'h20000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_36 = {1'b0,$signed(_address_ok_T_35)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_38 = $signed(_address_ok_T_36) & -32'sh20000000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_39 = $signed(_address_ok_T_38) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_40 = io_in_b_bits_address ^ 31'h10034000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_41 = {1'b0,$signed(_address_ok_T_40)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_43 = $signed(_address_ok_T_41) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_44 = $signed(_address_ok_T_43) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_45 = io_in_b_bits_address ^ 31'h10024000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_46 = {1'b0,$signed(_address_ok_T_45)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_48 = $signed(_address_ok_T_46) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_49 = $signed(_address_ok_T_48) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_50 = io_in_b_bits_address ^ 31'h10012000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_51 = {1'b0,$signed(_address_ok_T_50)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_53 = $signed(_address_ok_T_51) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_54 = $signed(_address_ok_T_53) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_55 = io_in_b_bits_address ^ 31'h10015000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_56 = {1'b0,$signed(_address_ok_T_55)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_58 = $signed(_address_ok_T_56) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_59 = $signed(_address_ok_T_58) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_60 = io_in_b_bits_address ^ 31'h10025000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_61 = {1'b0,$signed(_address_ok_T_60)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_63 = $signed(_address_ok_T_61) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_64 = $signed(_address_ok_T_63) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_65 = io_in_b_bits_address ^ 31'h10035000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_66 = {1'b0,$signed(_address_ok_T_65)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_68 = $signed(_address_ok_T_66) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_69 = $signed(_address_ok_T_68) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_70 = io_in_b_bits_address ^ 31'h10016000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_71 = {1'b0,$signed(_address_ok_T_70)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_73 = $signed(_address_ok_T_71) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_74 = $signed(_address_ok_T_73) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_75 = io_in_b_bits_address ^ 31'h10026000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_76 = {1'b0,$signed(_address_ok_T_75)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_78 = $signed(_address_ok_T_76) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_79 = $signed(_address_ok_T_78) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_80 = io_in_b_bits_address ^ 31'hc000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_81 = {1'b0,$signed(_address_ok_T_80)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_83 = $signed(_address_ok_T_81) & -32'sh4000000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_84 = $signed(_address_ok_T_83) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_85 = io_in_b_bits_address ^ 31'h2000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_86 = {1'b0,$signed(_address_ok_T_85)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_88 = $signed(_address_ok_T_86) & -32'sh10000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_89 = $signed(_address_ok_T_88) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _address_ok_T_93 = $signed(_T_1444) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_94 = $signed(_address_ok_T_93) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_95 = io_in_b_bits_address ^ 31'h8000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_96 = {1'b0,$signed(_address_ok_T_95)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_98 = $signed(_address_ok_T_96) & -32'sh4000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_99 = $signed(_address_ok_T_98) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_100 = io_in_b_bits_address ^ 31'h10000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_101 = {1'b0,$signed(_address_ok_T_100)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_103 = $signed(_address_ok_T_101) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_104 = $signed(_address_ok_T_103) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_105 = io_in_b_bits_address ^ 31'h10000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_106 = {1'b0,$signed(_address_ok_T_105)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_108 = $signed(_address_ok_T_106) & -32'sh10000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_109 = $signed(_address_ok_T_108) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_110 = io_in_b_bits_address ^ 31'h40000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_111 = {1'b0,$signed(_address_ok_T_110)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_113 = $signed(_address_ok_T_111) & -32'sh20000000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_114 = $signed(_address_ok_T_113) == 32'sh0; // @[Parameters.scala 137:67]
  wire  address_ok = _address_ok_T_4 | _address_ok_T_9 | _address_ok_T_14 | _address_ok_T_19 | _address_ok_T_24 |
    _address_ok_T_29 | _address_ok_T_34 | _address_ok_T_39 | _address_ok_T_44 | _address_ok_T_49 | _address_ok_T_54 |
    _address_ok_T_59 | _address_ok_T_64 | _address_ok_T_69 | _address_ok_T_74 | _address_ok_T_79 | _address_ok_T_84 |
    _address_ok_T_89 | _address_ok_T_94 | _address_ok_T_99 | _address_ok_T_104 | _address_ok_T_109 | _address_ok_T_114; // @[Parameters.scala 622:64]
  wire [30:0] _is_aligned_T_1 = io_in_b_bits_address & 31'h3f; // @[Edges.scala 20:16]
  wire  is_aligned_1 = _is_aligned_T_1 == 31'h0; // @[Edges.scala 20:24]
  wire [31:0] _T_1487 = $signed(_T_1444) & -32'sh10001000; // @[Parameters.scala 137:52]
  wire  _T_1488 = $signed(_T_1487) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_1517 = $signed(_address_ok_T_51) & -32'sh2000; // @[Parameters.scala 137:52]
  wire  _T_1518 = $signed(_T_1517) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_1522 = $signed(_address_ok_T_31) & -32'sh2000; // @[Parameters.scala 137:52]
  wire  _T_1523 = $signed(_T_1522) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_1532 = $signed(_address_ok_T_11) & -32'sh11000; // @[Parameters.scala 137:52]
  wire  _T_1533 = $signed(_T_1532) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_1537 = $signed(_address_ok_T_46) & -32'sh12000; // @[Parameters.scala 137:52]
  wire  _T_1538 = $signed(_T_1537) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_1547 = $signed(_address_ok_T_21) & -32'sh11000; // @[Parameters.scala 137:52]
  wire  _T_1548 = $signed(_T_1547) == 32'sh0; // @[Parameters.scala 137:67]
  wire  _T_1572 = _T_1488 | _address_ok_T_4 | _address_ok_T_109 | _address_ok_T_89 | _address_ok_T_99 | _address_ok_T_84
     | _T_1518 | _T_1523 | _address_ok_T_74 | _T_1533 | _T_1538 | _address_ok_T_79 | _T_1548 | _address_ok_T_39 |
    _address_ok_T_114; // @[Parameters.scala 671:42]
  wire  _T_1588 = io_in_b_bits_param <= 2'h2; // @[Bundles.scala 102:26]
  wire  _source_ok_T_8 = io_in_c_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_9 = io_in_c_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_10 = io_in_c_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_2 = _source_ok_T_8 | _source_ok_T_9 | _source_ok_T_10; // @[Parameters.scala 1125:46]
  wire [26:0] _is_aligned_mask_T_7 = 27'hfff << io_in_c_bits_size; // @[package.scala 234:77]
  wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_7[11:0]; // @[package.scala 234:46]
  wire [30:0] _GEN_87 = {{19'd0}, is_aligned_mask_2}; // @[Edges.scala 20:16]
  wire [30:0] _is_aligned_T_2 = io_in_c_bits_address & _GEN_87; // @[Edges.scala 20:16]
  wire  is_aligned_2 = _is_aligned_T_2 == 31'h0; // @[Edges.scala 20:24]
  wire [30:0] _address_ok_T_136 = io_in_c_bits_address ^ 31'h3000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_137 = {1'b0,$signed(_address_ok_T_136)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_139 = $signed(_address_ok_T_137) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_140 = $signed(_address_ok_T_139) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_141 = io_in_c_bits_address ^ 31'h10013000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_142 = {1'b0,$signed(_address_ok_T_141)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_144 = $signed(_address_ok_T_142) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_145 = $signed(_address_ok_T_144) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_146 = io_in_c_bits_address ^ 31'h10023000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_147 = {1'b0,$signed(_address_ok_T_146)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_149 = $signed(_address_ok_T_147) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_150 = $signed(_address_ok_T_149) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_151 = io_in_c_bits_address ^ 31'h10033000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_152 = {1'b0,$signed(_address_ok_T_151)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_154 = $signed(_address_ok_T_152) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_155 = $signed(_address_ok_T_154) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_156 = io_in_c_bits_address ^ 31'h10043000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_157 = {1'b0,$signed(_address_ok_T_156)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_159 = $signed(_address_ok_T_157) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_160 = $signed(_address_ok_T_159) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_161 = io_in_c_bits_address ^ 31'h10053000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_162 = {1'b0,$signed(_address_ok_T_161)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_164 = $signed(_address_ok_T_162) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_165 = $signed(_address_ok_T_164) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_166 = io_in_c_bits_address ^ 31'h10014000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_167 = {1'b0,$signed(_address_ok_T_166)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_169 = $signed(_address_ok_T_167) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_170 = $signed(_address_ok_T_169) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_171 = io_in_c_bits_address ^ 31'h20000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_172 = {1'b0,$signed(_address_ok_T_171)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_174 = $signed(_address_ok_T_172) & -32'sh20000000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_175 = $signed(_address_ok_T_174) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_176 = io_in_c_bits_address ^ 31'h10034000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_177 = {1'b0,$signed(_address_ok_T_176)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_179 = $signed(_address_ok_T_177) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_180 = $signed(_address_ok_T_179) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_181 = io_in_c_bits_address ^ 31'h10024000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_182 = {1'b0,$signed(_address_ok_T_181)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_184 = $signed(_address_ok_T_182) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_185 = $signed(_address_ok_T_184) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_186 = io_in_c_bits_address ^ 31'h10012000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_187 = {1'b0,$signed(_address_ok_T_186)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_189 = $signed(_address_ok_T_187) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_190 = $signed(_address_ok_T_189) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_191 = io_in_c_bits_address ^ 31'h10015000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_192 = {1'b0,$signed(_address_ok_T_191)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_194 = $signed(_address_ok_T_192) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_195 = $signed(_address_ok_T_194) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_196 = io_in_c_bits_address ^ 31'h10025000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_197 = {1'b0,$signed(_address_ok_T_196)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_199 = $signed(_address_ok_T_197) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_200 = $signed(_address_ok_T_199) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_201 = io_in_c_bits_address ^ 31'h10035000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_202 = {1'b0,$signed(_address_ok_T_201)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_204 = $signed(_address_ok_T_202) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_205 = $signed(_address_ok_T_204) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_206 = io_in_c_bits_address ^ 31'h10016000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_207 = {1'b0,$signed(_address_ok_T_206)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_209 = $signed(_address_ok_T_207) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_210 = $signed(_address_ok_T_209) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_211 = io_in_c_bits_address ^ 31'h10026000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_212 = {1'b0,$signed(_address_ok_T_211)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_214 = $signed(_address_ok_T_212) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_215 = $signed(_address_ok_T_214) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_216 = io_in_c_bits_address ^ 31'hc000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_217 = {1'b0,$signed(_address_ok_T_216)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_219 = $signed(_address_ok_T_217) & -32'sh4000000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_220 = $signed(_address_ok_T_219) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_221 = io_in_c_bits_address ^ 31'h2000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_222 = {1'b0,$signed(_address_ok_T_221)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_224 = $signed(_address_ok_T_222) & -32'sh10000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_225 = $signed(_address_ok_T_224) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _address_ok_T_227 = {1'b0,$signed(io_in_c_bits_address)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_229 = $signed(_address_ok_T_227) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_230 = $signed(_address_ok_T_229) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_231 = io_in_c_bits_address ^ 31'h8000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_232 = {1'b0,$signed(_address_ok_T_231)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_234 = $signed(_address_ok_T_232) & -32'sh4000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_235 = $signed(_address_ok_T_234) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_236 = io_in_c_bits_address ^ 31'h10000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_237 = {1'b0,$signed(_address_ok_T_236)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_239 = $signed(_address_ok_T_237) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_240 = $signed(_address_ok_T_239) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_241 = io_in_c_bits_address ^ 31'h10000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_242 = {1'b0,$signed(_address_ok_T_241)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_244 = $signed(_address_ok_T_242) & -32'sh10000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_245 = $signed(_address_ok_T_244) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_246 = io_in_c_bits_address ^ 31'h40000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_247 = {1'b0,$signed(_address_ok_T_246)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_249 = $signed(_address_ok_T_247) & -32'sh20000000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_250 = $signed(_address_ok_T_249) == 32'sh0; // @[Parameters.scala 137:67]
  wire  address_ok_1 = _address_ok_T_140 | _address_ok_T_145 | _address_ok_T_150 | _address_ok_T_155 | _address_ok_T_160
     | _address_ok_T_165 | _address_ok_T_170 | _address_ok_T_175 | _address_ok_T_180 | _address_ok_T_185 |
    _address_ok_T_190 | _address_ok_T_195 | _address_ok_T_200 | _address_ok_T_205 | _address_ok_T_210 |
    _address_ok_T_215 | _address_ok_T_220 | _address_ok_T_225 | _address_ok_T_230 | _address_ok_T_235 |
    _address_ok_T_240 | _address_ok_T_245 | _address_ok_T_250; // @[Parameters.scala 622:64]
  wire  _T_2341 = io_in_c_bits_opcode == 3'h4; // @[Monitor.scala 242:25]
  wire  _T_2348 = io_in_c_bits_size >= 4'h2; // @[Monitor.scala 245:30]
  wire  _T_2355 = io_in_c_bits_param <= 3'h5; // @[Bundles.scala 120:29]
  wire  _T_2359 = ~io_in_c_bits_corrupt; // @[Monitor.scala 248:18]
  wire  _T_2363 = io_in_c_bits_opcode == 3'h5; // @[Monitor.scala 251:25]
  wire  _T_2381 = io_in_c_bits_opcode == 3'h6; // @[Monitor.scala 259:25]
  wire  _T_2383 = io_in_c_bits_size <= 4'hc; // @[Parameters.scala 92:42]
  wire  _T_2390 = _T_2383 & source_ok_2; // @[Parameters.scala 1160:30]
  wire [31:0] _T_2396 = $signed(_address_ok_T_227) & -32'sh10001000; // @[Parameters.scala 137:52]
  wire  _T_2397 = $signed(_T_2396) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_2426 = $signed(_address_ok_T_187) & -32'sh2000; // @[Parameters.scala 137:52]
  wire  _T_2427 = $signed(_T_2426) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_2431 = $signed(_address_ok_T_167) & -32'sh2000; // @[Parameters.scala 137:52]
  wire  _T_2432 = $signed(_T_2431) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_2441 = $signed(_address_ok_T_147) & -32'sh11000; // @[Parameters.scala 137:52]
  wire  _T_2442 = $signed(_T_2441) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_2446 = $signed(_address_ok_T_182) & -32'sh12000; // @[Parameters.scala 137:52]
  wire  _T_2447 = $signed(_T_2446) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_2456 = $signed(_address_ok_T_157) & -32'sh11000; // @[Parameters.scala 137:52]
  wire  _T_2457 = $signed(_T_2456) == 32'sh0; // @[Parameters.scala 137:67]
  wire  _T_2478 = io_in_c_bits_size <= 4'h6; // @[Parameters.scala 92:42]
  wire  _T_2486 = _T_2478 & _address_ok_T_250; // @[Parameters.scala 670:56]
  wire  _T_2489 = _T_2390 & _T_2486; // @[Monitor.scala 260:78]
  wire  _T_2496 = 4'h6 == io_in_c_bits_size; // @[Parameters.scala 91:48]
  wire  _T_2497 = _source_ok_T_8 & _T_2496; // @[Mux.scala 27:73]
  wire  _T_2594 = _T_2397 | _address_ok_T_140 | _address_ok_T_245 | _address_ok_T_225 | _address_ok_T_235 |
    _address_ok_T_220 | _T_2427 | _T_2432 | _address_ok_T_210 | _T_2442 | _T_2447 | _address_ok_T_215 | _T_2457 |
    _address_ok_T_175 | _address_ok_T_250; // @[Parameters.scala 671:42]
  wire  _T_2595 = _T_2383 & _T_2594; // @[Parameters.scala 670:56]
  wire  _T_2597 = _T_2497 & _T_2595; // @[Monitor.scala 261:78]
  wire  _T_2619 = io_in_c_bits_opcode == 3'h7; // @[Monitor.scala 269:25]
  wire  _T_2853 = io_in_c_bits_opcode == 3'h0; // @[Monitor.scala 278:25]
  wire  _T_2863 = io_in_c_bits_param == 3'h0; // @[Monitor.scala 282:31]
  wire  _T_2871 = io_in_c_bits_opcode == 3'h1; // @[Monitor.scala 286:25]
  wire  _T_2885 = io_in_c_bits_opcode == 3'h2; // @[Monitor.scala 293:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [9:0] a_first_beats1_decode = is_aligned_mask[11:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [9:0] a_first_counter; // @[Edges.scala 228:27]
  wire [9:0] a_first_counter1 = a_first_counter - 10'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 10'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [3:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [30:0] address; // @[Monitor.scala 388:22]
  wire  _T_2907 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_2908 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_2912 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_2916 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_2920 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_2924 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [26:0] _d_first_beats1_decode_T_1 = 27'hfff << io_in_d_bits_size; // @[package.scala 234:77]
  wire [11:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
  wire [9:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[11:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [9:0] d_first_counter; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1 = d_first_counter - 10'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 10'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] param_1; // @[Monitor.scala 536:22]
  reg [3:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  reg [1:0] sink; // @[Monitor.scala 539:22]
  reg  denied; // @[Monitor.scala 540:22]
  wire  _T_2931 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_2932 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_2936 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
  wire  _T_2940 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_2944 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  wire  _T_2948 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
  wire  _T_2952 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
  wire  b_first_done = io_in_b_ready & io_in_b_valid; // @[Decoupled.scala 50:35]
  reg [9:0] b_first_counter; // @[Edges.scala 228:27]
  wire [9:0] b_first_counter1 = b_first_counter - 10'h1; // @[Edges.scala 229:28]
  wire  b_first = b_first_counter == 10'h0; // @[Edges.scala 230:25]
  reg [1:0] param_2; // @[Monitor.scala 408:22]
  reg [30:0] address_1; // @[Monitor.scala 411:22]
  wire  _T_2959 = io_in_b_valid & ~b_first; // @[Monitor.scala 412:19]
  wire  _T_2964 = io_in_b_bits_param == param_2; // @[Monitor.scala 414:32]
  wire  _T_2976 = io_in_b_bits_address == address_1; // @[Monitor.scala 417:32]
  wire  _c_first_T = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala 50:35]
  wire [9:0] c_first_beats1_decode = is_aligned_mask_2[11:2]; // @[Edges.scala 219:59]
  wire  c_first_beats1_opdata = io_in_c_bits_opcode[0]; // @[Edges.scala 101:36]
  reg [9:0] c_first_counter; // @[Edges.scala 228:27]
  wire [9:0] c_first_counter1 = c_first_counter - 10'h1; // @[Edges.scala 229:28]
  wire  c_first = c_first_counter == 10'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_3; // @[Monitor.scala 512:22]
  reg [2:0] param_3; // @[Monitor.scala 513:22]
  reg [3:0] size_3; // @[Monitor.scala 514:22]
  reg [1:0] source_3; // @[Monitor.scala 515:22]
  reg [30:0] address_2; // @[Monitor.scala 516:22]
  wire  _T_2983 = io_in_c_valid & ~c_first; // @[Monitor.scala 517:19]
  wire  _T_2984 = io_in_c_bits_opcode == opcode_3; // @[Monitor.scala 518:32]
  wire  _T_2988 = io_in_c_bits_param == param_3; // @[Monitor.scala 519:32]
  wire  _T_2992 = io_in_c_bits_size == size_3; // @[Monitor.scala 520:32]
  wire  _T_2996 = io_in_c_bits_source == source_3; // @[Monitor.scala 521:32]
  wire  _T_3000 = io_in_c_bits_address == address_2; // @[Monitor.scala 522:32]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [23:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [9:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [9:0] a_first_counter1_1 = a_first_counter_1 - 10'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 10'h0; // @[Edges.scala 230:25]
  reg [9:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1_1 = d_first_counter_1 - 10'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 10'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_88 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_88}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_89 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_89 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [4:0] _a_size_lookup_T = {io_in_d_bits_source, 3'h0}; // @[Monitor.scala 638:65]
  wire [23:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _a_size_lookup_T_5 = 16'h100 - 16'h1; // @[Monitor.scala 609:57]
  wire [23:0] _GEN_91 = {{8'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 638:91]
  wire [23:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_91; // @[Monitor.scala 638:91]
  wire [23:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[23:1]}; // @[Monitor.scala 638:144]
  wire  _T_3006 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _GEN_27 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_3009 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [4:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 5'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_93 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_93}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [4:0] _a_sizes_set_T = {io_in_a_bits_source, 3'h0}; // @[Monitor.scala 657:77]
  wire [4:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala 652:72 655:28]
  wire [35:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [35:0] _a_sizes_set_T_1 = _GEN_2 << _a_sizes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_3011 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_3013 = ~_T_3011[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_28 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_31 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [35:0] _GEN_32 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 36'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_3017 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_3019 = ~_T_1308; // @[Monitor.scala 671:74]
  wire  _T_3020 = io_in_d_valid & d_first_1 & ~_T_1308; // @[Monitor.scala 671:71]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _GEN_33 = io_in_d_valid & d_first_1 & ~_T_1308 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 671:90 672:22]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [46:0] _GEN_4 = {{31'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 678:74]
  wire [46:0] _d_sizes_clr_T_5 = _GEN_4 << _a_size_lookup_T; // @[Monitor.scala 678:74]
  wire [3:0] _GEN_34 = _d_first_T & d_first_1 & _T_3019 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_35 = _d_first_T & d_first_1 & _T_3019 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire [46:0] _GEN_36 = _d_first_T & d_first_1 & _T_3019 ? _d_sizes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 678:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_3006 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_3030 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_3032 = _T_3030[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_39 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_40 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_39; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_41 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_40; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_42 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_41; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_43 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_42; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_44 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_43; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_51 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_42; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_52 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_51; // @[Monitor.scala 686:{39,39}]
  wire  _T_3037 = io_in_d_bits_opcode == _GEN_52; // @[Monitor.scala 686:39]
  wire  _T_3038 = io_in_d_bits_opcode == _GEN_44 | _T_3037; // @[Monitor.scala 685:77]
  wire  _T_3042 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_55 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_56 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_55; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_57 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_56; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_58 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_57; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_59 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_58; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_60 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_59; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_67 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_58; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_68 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_67; // @[Monitor.scala 690:{38,38}]
  wire  _T_3049 = io_in_d_bits_opcode == _GEN_68; // @[Monitor.scala 690:38]
  wire  _T_3050 = io_in_d_bits_opcode == _GEN_60 | _T_3049; // @[Monitor.scala 689:72]
  wire [7:0] a_size_lookup = _a_size_lookup_T_7[7:0];
  wire [7:0] _GEN_95 = {{4'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_3054 = _GEN_95 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_3064 = _T_3017 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_3019; // @[Monitor.scala 694:116]
  wire  _T_3065 = ~io_in_d_ready; // @[Monitor.scala 695:15]
  wire  _T_3066 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set_wo_ready = _GEN_27[2:0];
  wire [2:0] d_clr_wo_ready = _GEN_33[2:0];
  wire  _T_3073 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire [2:0] a_set = _GEN_28[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_34[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_31[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_35[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [23:0] a_sizes_set = _GEN_32[23:0];
  wire [23:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [23:0] d_sizes_clr = _GEN_36[23:0];
  wire [23:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala 704:56]
  wire [23:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_3082 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [2:0] inflight_1; // @[Monitor.scala 723:35]
  reg [23:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [9:0] c_first_counter_1; // @[Edges.scala 228:27]
  wire [9:0] c_first_counter1_1 = c_first_counter_1 - 10'h1; // @[Edges.scala 229:28]
  wire  c_first_1 = c_first_counter_1 == 10'h0; // @[Edges.scala 230:25]
  reg [9:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1_2 = d_first_counter_2 - 10'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 10'h0; // @[Edges.scala 230:25]
  wire [23:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_size_lookup_T; // @[Monitor.scala 747:42]
  wire [23:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_91; // @[Monitor.scala 747:93]
  wire [23:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[23:1]}; // @[Monitor.scala 747:146]
  wire  _T_3092 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala 67:40]
  wire  _T_3093 = io_in_c_valid & c_first_1 & _T_3092; // @[Monitor.scala 756:37]
  wire [3:0] _c_set_wo_ready_T = 4'h1 << io_in_c_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _GEN_72 = io_in_c_valid & c_first_1 & _T_3092 ? _c_set_wo_ready_T : 4'h0; // @[Monitor.scala 756:71 757:22]
  wire  _T_3099 = _c_first_T & c_first_1 & _T_3092; // @[Monitor.scala 760:38]
  wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size, 1'h0}; // @[Monitor.scala 763:51]
  wire [4:0] _c_sizes_set_interm_T_1 = _c_sizes_set_interm_T | 5'h1; // @[Monitor.scala 763:59]
  wire [4:0] _c_sizes_set_T = {io_in_c_bits_source, 3'h0}; // @[Monitor.scala 765:77]
  wire [4:0] c_sizes_set_interm = _c_first_T & c_first_1 & _T_3092 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala 760:72 763:28]
  wire [35:0] _GEN_5 = {{31'd0}, c_sizes_set_interm}; // @[Monitor.scala 765:52]
  wire [35:0] _c_sizes_set_T_1 = _GEN_5 << _c_sizes_set_T; // @[Monitor.scala 765:52]
  wire [2:0] _T_3100 = inflight_1 >> io_in_c_bits_source; // @[Monitor.scala 766:26]
  wire  _T_3102 = ~_T_3100[0]; // @[Monitor.scala 766:17]
  wire [3:0] _GEN_73 = _c_first_T & c_first_1 & _T_3092 ? _c_set_wo_ready_T : 4'h0; // @[Monitor.scala 760:72 761:28]
  wire [35:0] _GEN_77 = _c_first_T & c_first_1 & _T_3092 ? _c_sizes_set_T_1 : 36'h0; // @[Monitor.scala 760:72 765:28]
  wire  _T_3106 = io_in_d_valid & d_first_2; // @[Monitor.scala 779:26]
  wire  _T_3108 = io_in_d_valid & d_first_2 & _T_1308; // @[Monitor.scala 779:71]
  wire [3:0] _GEN_78 = io_in_d_valid & d_first_2 & _T_1308 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 779:89 780:22]
  wire [3:0] _GEN_79 = _d_first_T & d_first_2 & _T_1308 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 783:90 784:21]
  wire [46:0] _GEN_81 = _d_first_T & d_first_2 & _T_1308 ? _d_sizes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 786:21]
  wire  _same_cycle_resp_T_8 = io_in_c_bits_source == io_in_d_bits_source; // @[Monitor.scala 790:113]
  wire  same_cycle_resp_1 = _T_3093 & io_in_c_bits_source == io_in_d_bits_source; // @[Monitor.scala 790:88]
  wire [2:0] _T_3116 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire  _T_3118 = _T_3116[0] | same_cycle_resp_1; // @[Monitor.scala 791:49]
  wire  _T_3122 = io_in_d_bits_size == io_in_c_bits_size; // @[Monitor.scala 793:36]
  wire [7:0] c_size_lookup = _c_size_lookup_T_7[7:0];
  wire  _T_3126 = _GEN_95 == c_size_lookup; // @[Monitor.scala 795:36]
  wire  _T_3135 = _T_3106 & c_first_1 & io_in_c_valid & _same_cycle_resp_T_8 & _T_1308; // @[Monitor.scala 799:116]
  wire  _T_3137 = _T_3065 | io_in_c_ready; // @[Monitor.scala 800:32]
  wire [2:0] c_set_wo_ready = _GEN_72[2:0];
  wire  _T_3141 = |c_set_wo_ready; // @[Monitor.scala 804:28]
  wire [2:0] d_clr_wo_ready_1 = _GEN_78[2:0];
  wire  _T_3142 = c_set_wo_ready != d_clr_wo_ready_1; // @[Monitor.scala 805:31]
  wire [2:0] c_set = _GEN_73[2:0];
  wire [2:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala 809:35]
  wire [2:0] d_clr_1 = _GEN_79[2:0];
  wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [2:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [23:0] c_sizes_set = _GEN_77[23:0];
  wire [23:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala 811:41]
  wire [23:0] d_sizes_clr_1 = _GEN_81[23:0];
  wire [23:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
  wire [23:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_3151 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  reg [3:0] inflight_2; // @[Monitor.scala 823:27]
  reg [9:0] d_first_counter_3; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1_3 = d_first_counter_3 - 10'h1; // @[Edges.scala 229:28]
  wire  d_first_3 = d_first_counter_3 == 10'h0; // @[Edges.scala 230:25]
  wire  _T_3163 = io_in_d_bits_opcode[2] & ~io_in_d_bits_opcode[1]; // @[Edges.scala 70:40]
  wire  _T_3164 = _d_first_T & d_first_3 & _T_3163; // @[Monitor.scala 829:38]
  wire [3:0] _d_set_T = 4'h1 << io_in_d_bits_sink; // @[OneHot.scala 57:35]
  wire [3:0] _T_3165 = inflight_2 >> io_in_d_bits_sink; // @[Monitor.scala 831:23]
  wire  _T_3167 = ~_T_3165[0]; // @[Monitor.scala 831:14]
  wire [3:0] d_set = _d_first_T & d_first_3 & _T_3163 ? _d_set_T : 4'h0; // @[Monitor.scala 829:72 830:13]
  wire [3:0] _e_clr_T = 4'h1 << io_in_e_bits_sink; // @[OneHot.scala 57:35]
  wire [3:0] _T_3174 = d_set | inflight_2; // @[Monitor.scala 837:24]
  wire [3:0] _T_3175 = _T_3174 >> io_in_e_bits_sink; // @[Monitor.scala 837:35]
  wire [3:0] e_clr = io_in_e_valid ? _e_clr_T : 4'h0; // @[Monitor.scala 835:73 836:13]
  wire [3:0] _inflight_T_6 = inflight_2 | d_set; // @[Monitor.scala 842:27]
  wire [3:0] _inflight_T_7 = ~e_clr; // @[Monitor.scala 842:38]
  wire [3:0] _inflight_T_8 = _inflight_T_6 & _inflight_T_7; // @[Monitor.scala 842:36]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 10'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 10'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 10'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      b_first_counter <= 10'h0; // @[Edges.scala 228:27]
    end else if (b_first_done) begin // @[Edges.scala 234:17]
      if (b_first) begin // @[Edges.scala 235:21]
        b_first_counter <= 10'h0;
      end else begin
        b_first_counter <= b_first_counter1;
      end
    end
    if (b_first_done & b_first) begin // @[Monitor.scala 419:32]
      param_2 <= io_in_b_bits_param; // @[Monitor.scala 421:15]
    end
    if (b_first_done & b_first) begin // @[Monitor.scala 419:32]
      address_1 <= io_in_b_bits_address; // @[Monitor.scala 424:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      c_first_counter <= 10'h0; // @[Edges.scala 228:27]
    end else if (_c_first_T) begin // @[Edges.scala 234:17]
      if (c_first) begin // @[Edges.scala 235:21]
        if (c_first_beats1_opdata) begin // @[Edges.scala 220:14]
          c_first_counter <= c_first_beats1_decode;
        end else begin
          c_first_counter <= 10'h0;
        end
      end else begin
        c_first_counter <= c_first_counter1;
      end
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      opcode_3 <= io_in_c_bits_opcode; // @[Monitor.scala 525:15]
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      param_3 <= io_in_c_bits_param; // @[Monitor.scala 526:15]
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      size_3 <= io_in_c_bits_size; // @[Monitor.scala 527:15]
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      source_3 <= io_in_c_bits_source; // @[Monitor.scala 528:15]
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      address_2 <= io_in_c_bits_address; // @[Monitor.scala 529:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 24'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 10'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 10'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 3'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 24'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      c_first_counter_1 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_c_first_T) begin // @[Edges.scala 234:17]
      if (c_first_1) begin // @[Edges.scala 235:21]
        if (c_first_beats1_opdata) begin // @[Edges.scala 220:14]
          c_first_counter_1 <= c_first_beats1_decode;
        end else begin
          c_first_counter_1 <= 10'h0;
        end
      end else begin
        c_first_counter_1 <= c_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 10'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_c_first_T | _d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    if (reset) begin // @[Monitor.scala 823:27]
      inflight_2 <= 4'h0; // @[Monitor.scala 823:27]
    end else begin
      inflight_2 <= _inflight_T_8; // @[Monitor.scala 842:14]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_3 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_3) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_3 <= d_first_beats1_decode;
        end else begin
          d_first_counter_3 <= 10'h0;
        end
      end else begin
        d_first_counter_3 <= d_first_counter1_3;
      end
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_141 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_141) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_249 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_249) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_263 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_263) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_268 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_268) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_272 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_272) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_141 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_T_141) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_249 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_T_249) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_263 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_T_263) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_510 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_T_510) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_268 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_T_268) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_272 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_T_272) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_42 & (io_in_a_valid & _T_523 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_523 & ~reset & ~_T_42) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_636 & (io_in_a_valid & _T_523 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_523 & ~reset & ~_T_636) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_523 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_523 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_523 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_523 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_646 & (io_in_a_valid & _T_523 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_523 & ~reset & ~_T_646) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_650 & (io_in_a_valid & _T_523 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_523 & ~reset & ~_T_650) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_272 & (io_in_a_valid & _T_523 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_523 & ~reset & ~_T_272) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_771 & (io_in_a_valid & _T_658 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_658 & ~reset & ~_T_771) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_658 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_658 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_658 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_658 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_646 & (io_in_a_valid & _T_658 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_658 & ~reset & ~_T_646) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_650 & (io_in_a_valid & _T_658 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_658 & ~reset & ~_T_650) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_902 & (io_in_a_valid & _T_789 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_789 & ~reset & ~_T_902) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_789 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_789 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_789 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_789 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_646 & (io_in_a_valid & _T_789 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_789 & ~reset & ~_T_646) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_918 & (io_in_a_valid & _T_789 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_789 & ~reset & ~_T_918) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1030 & (io_in_a_valid & _T_922 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_922 & ~reset & ~_T_1030) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_922 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_922 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_922 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_922 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1040 & (io_in_a_valid & _T_922 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_922 & ~reset & ~_T_1040) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_650 & (io_in_a_valid & _T_922 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_922 & ~reset & ~_T_650) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1030 & (io_in_a_valid & _T_1048 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1048 & ~reset & ~_T_1030) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_1048 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1048 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_1048 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1048 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1166 & (io_in_a_valid & _T_1048 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1048 & ~reset & ~_T_1166) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_650 & (io_in_a_valid & _T_1048 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1048 & ~reset & ~_T_650) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1282 & (io_in_a_valid & _T_1174 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1174 & ~reset & ~_T_1282) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_1174 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1174 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_1174 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1174 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1292 & (io_in_a_valid & _T_1174 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1174 & ~reset & ~_T_1292) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_650 & (io_in_a_valid & _T_1174 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1174 & ~reset & ~_T_650) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_272 & (io_in_a_valid & _T_1174 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1174 & ~reset & ~_T_272) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1304 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_1304) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1308 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1308 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1312 & (io_in_d_valid & _T_1308 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1308 & _T_2 & ~_T_1312) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1316 & (io_in_d_valid & _T_1308 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1308 & _T_2 & ~_T_1316) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1320 & (io_in_d_valid & _T_1308 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1308 & _T_2 & ~_T_1320) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1324 & (io_in_d_valid & _T_1308 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1308 & _T_2 & ~_T_1324) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is denied (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1328 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1328 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1312 & (io_in_d_valid & _T_1328 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1328 & _T_2 & ~_T_1312) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1339 & (io_in_d_valid & _T_1328 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1328 & _T_2 & ~_T_1339) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid cap param (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1343 & (io_in_d_valid & _T_1328 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1328 & _T_2 & ~_T_1343) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries toN param (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1320 & (io_in_d_valid & _T_1328 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1328 & _T_2 & ~_T_1320) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is corrupt (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1356 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1356 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1312 & (io_in_d_valid & _T_1356 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1356 & _T_2 & ~_T_1312) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1339 & (io_in_d_valid & _T_1356 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1356 & _T_2 & ~_T_1339) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1343 & (io_in_d_valid & _T_1356 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1356 & _T_2 & ~_T_1343) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries toN param (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1376 & (io_in_d_valid & _T_1356 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1356 & _T_2 & ~_T_1376) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1385 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1385 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1316 & (io_in_d_valid & _T_1385 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1385 & _T_2 & ~_T_1316) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid param (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1320 & (io_in_d_valid & _T_1385 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1385 & _T_2 & ~_T_1320) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is corrupt (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1402 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1402 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1316 & (io_in_d_valid & _T_1402 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1402 & _T_2 & ~_T_1316) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1376 & (io_in_d_valid & _T_1402 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1402 & _T_2 & ~_T_1376) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1420 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1420 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1316 & (io_in_d_valid & _T_1420 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1420 & _T_2 & ~_T_1316) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid param (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1320 & (io_in_d_valid & _T_1420 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1420 & _T_2 & ~_T_1320) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is corrupt (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1572 & (io_in_b_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2 & ~_T_1572) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~address_ok & (io_in_b_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2 & ~address_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Probe carries unmanaged address (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_1 & (io_in_b_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2 & ~is_aligned_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Probe address not aligned to size (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1588 & (io_in_b_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2 & ~_T_1588) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Probe carries invalid cap param (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~address_ok_1 & (io_in_c_valid & _T_2341 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2341 & ~reset & ~address_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_2 & (io_in_c_valid & _T_2341 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2341 & ~reset & ~source_ok_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2348 & (io_in_c_valid & _T_2341 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2341 & ~reset & ~_T_2348) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_2341 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2341 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2355 & (io_in_c_valid & _T_2341 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2341 & ~reset & ~_T_2355) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2359 & (io_in_c_valid & _T_2341 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2341 & ~reset & ~_T_2359) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck is corrupt (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~address_ok_1 & (io_in_c_valid & _T_2363 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2363 & ~reset & ~address_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_2 & (io_in_c_valid & _T_2363 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2363 & ~reset & ~source_ok_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2348 & (io_in_c_valid & _T_2363 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2363 & ~reset & ~_T_2348) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_2363 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2363 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2355 & (io_in_c_valid & _T_2363 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2363 & ~reset & ~_T_2355) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2489 & (io_in_c_valid & _T_2381 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2381 & ~reset & ~_T_2489) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2597 & (io_in_c_valid & _T_2381 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2381 & ~reset & ~_T_2597) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_2 & (io_in_c_valid & _T_2381 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2381 & ~reset & ~source_ok_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release carries invalid source ID (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2348 & (io_in_c_valid & _T_2381 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2381 & ~reset & ~_T_2348) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release smaller than a beat (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_2381 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2381 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release address not aligned to size (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2355 & (io_in_c_valid & _T_2381 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2381 & ~reset & ~_T_2355) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release carries invalid report param (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2359 & (io_in_c_valid & _T_2381 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2381 & ~reset & ~_T_2359) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release is corrupt (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2489 & (io_in_c_valid & _T_2619 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2619 & ~reset & ~_T_2489) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2597 & (io_in_c_valid & _T_2619 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2619 & ~reset & ~_T_2597) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_2 & (io_in_c_valid & _T_2619 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2619 & ~reset & ~source_ok_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2348 & (io_in_c_valid & _T_2619 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2619 & ~reset & ~_T_2348) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_2619 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2619 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2355 & (io_in_c_valid & _T_2619 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2619 & ~reset & ~_T_2355) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~address_ok_1 & (io_in_c_valid & _T_2853 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2853 & ~reset & ~address_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_2 & (io_in_c_valid & _T_2853 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2853 & ~reset & ~source_ok_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_2853 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2853 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2863 & (io_in_c_valid & _T_2853 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2853 & ~reset & ~_T_2863) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck carries invalid param (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2359 & (io_in_c_valid & _T_2853 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2853 & ~reset & ~_T_2359) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck is corrupt (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~address_ok_1 & (io_in_c_valid & _T_2871 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2871 & ~reset & ~address_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_2 & (io_in_c_valid & _T_2871 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2871 & ~reset & ~source_ok_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_2871 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2871 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2863 & (io_in_c_valid & _T_2871 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2871 & ~reset & ~_T_2863) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~address_ok_1 & (io_in_c_valid & _T_2885 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2885 & ~reset & ~address_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_2 & (io_in_c_valid & _T_2885 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2885 & ~reset & ~source_ok_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_2885 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2885 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck address not aligned to size (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2863 & (io_in_c_valid & _T_2885 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2885 & ~reset & ~_T_2863) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck carries invalid param (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2359 & (io_in_c_valid & _T_2885 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2885 & ~reset & ~_T_2359) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck is corrupt (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2908 & (_T_2907 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2907 & ~reset & ~_T_2908) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2912 & (_T_2907 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2907 & ~reset & ~_T_2912) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2916 & (_T_2907 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2907 & ~reset & ~_T_2916) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2920 & (_T_2907 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2907 & ~reset & ~_T_2920) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2924 & (_T_2907 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2907 & ~reset & ~_T_2924) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2932 & (_T_2931 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2931 & _T_2 & ~_T_2932) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2936 & (_T_2931 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2931 & _T_2 & ~_T_2936) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel param changed within multibeat operation (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2940 & (_T_2931 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2931 & _T_2 & ~_T_2940) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2944 & (_T_2931 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2931 & _T_2 & ~_T_2944) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2948 & (_T_2931 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2931 & _T_2 & ~_T_2948) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel sink changed with multibeat operation (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2952 & (_T_2931 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2931 & _T_2 & ~_T_2952) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel denied changed with multibeat operation (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2964 & (_T_2959 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2959 & ~reset & ~_T_2964) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel param changed within multibeat operation (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2976 & (_T_2959 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2959 & ~reset & ~_T_2976) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2984 & (_T_2983 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2983 & ~reset & ~_T_2984) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2988 & (_T_2983 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2983 & ~reset & ~_T_2988) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel param changed within multibeat operation (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2992 & (_T_2983 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2983 & ~reset & ~_T_2992) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel size changed within multibeat operation (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2996 & (_T_2983 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2983 & ~reset & ~_T_2996) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel source changed within multibeat operation (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3000 & (_T_2983 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2983 & ~reset & ~_T_3000) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel address changed with multibeat operation (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3013 & (_T_3009 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3009 & ~reset & ~_T_3013) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3032 & (_T_3020 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3020 & _T_2 & ~_T_3032) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3038 & (_T_3020 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3020 & same_cycle_resp & _T_2 & ~_T_3038) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3042 & (_T_3020 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3020 & same_cycle_resp & _T_2 & ~_T_3042) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3050 & (_T_3020 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3020 & ~same_cycle_resp & _T_2 & ~_T_3050) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3054 & (_T_3020 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3020 & ~same_cycle_resp & _T_2 & ~_T_3054) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3066 & (_T_3064 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3064 & _T_2 & ~_T_3066) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3073 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_3073) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3082 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_3082) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3102 & (_T_3099 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3099 & ~reset & ~_T_3102) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel re-used a source ID (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3118 & (_T_3108 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3108 & _T_2 & ~_T_3118) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3122 & (_T_3108 & same_cycle_resp_1 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3108 & same_cycle_resp_1 & _T_2 & ~_T_3122) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3126 & (_T_3108 & ~same_cycle_resp_1 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3108 & ~same_cycle_resp_1 & _T_2 & ~_T_3126) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3137 & (_T_3135 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3135 & _T_2 & ~_T_3137) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3142 & (_T_3141 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3141 & _T_2 & ~_T_3142) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' and 'D' concurrent, despite minlatency 1 (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3151 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_3151) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3167 & (_T_3164 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3164 & _T_2 & ~_T_3167) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel re-used a sink ID (connected at SystemBus.scala:41:55)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3175[0] & (io_in_e_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_e_valid & ~reset & ~_T_3175[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at SystemBus.scala:41:55)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[9:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[30:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[9:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  param_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  size_1 = _RAND_9[3:0];
  _RAND_10 = {1{`RANDOM}};
  source_1 = _RAND_10[1:0];
  _RAND_11 = {1{`RANDOM}};
  sink = _RAND_11[1:0];
  _RAND_12 = {1{`RANDOM}};
  denied = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  b_first_counter = _RAND_13[9:0];
  _RAND_14 = {1{`RANDOM}};
  param_2 = _RAND_14[1:0];
  _RAND_15 = {1{`RANDOM}};
  address_1 = _RAND_15[30:0];
  _RAND_16 = {1{`RANDOM}};
  c_first_counter = _RAND_16[9:0];
  _RAND_17 = {1{`RANDOM}};
  opcode_3 = _RAND_17[2:0];
  _RAND_18 = {1{`RANDOM}};
  param_3 = _RAND_18[2:0];
  _RAND_19 = {1{`RANDOM}};
  size_3 = _RAND_19[3:0];
  _RAND_20 = {1{`RANDOM}};
  source_3 = _RAND_20[1:0];
  _RAND_21 = {1{`RANDOM}};
  address_2 = _RAND_21[30:0];
  _RAND_22 = {1{`RANDOM}};
  inflight = _RAND_22[2:0];
  _RAND_23 = {1{`RANDOM}};
  inflight_opcodes = _RAND_23[11:0];
  _RAND_24 = {1{`RANDOM}};
  inflight_sizes = _RAND_24[23:0];
  _RAND_25 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_25[9:0];
  _RAND_26 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_26[9:0];
  _RAND_27 = {1{`RANDOM}};
  watchdog = _RAND_27[31:0];
  _RAND_28 = {1{`RANDOM}};
  inflight_1 = _RAND_28[2:0];
  _RAND_29 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_29[23:0];
  _RAND_30 = {1{`RANDOM}};
  c_first_counter_1 = _RAND_30[9:0];
  _RAND_31 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_31[9:0];
  _RAND_32 = {1{`RANDOM}};
  watchdog_1 = _RAND_32[31:0];
  _RAND_33 = {1{`RANDOM}};
  inflight_2 = _RAND_33[3:0];
  _RAND_34 = {1{`RANDOM}};
  d_first_counter_3 = _RAND_34[9:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLXbar(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [3:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [30:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_b_ready,
  output        auto_in_b_valid,
  output [1:0]  auto_in_b_bits_param,
  output [30:0] auto_in_b_bits_address,
  output        auto_in_c_ready,
  input         auto_in_c_valid,
  input  [2:0]  auto_in_c_bits_opcode,
  input  [2:0]  auto_in_c_bits_param,
  input  [3:0]  auto_in_c_bits_size,
  input  [1:0]  auto_in_c_bits_source,
  input  [30:0] auto_in_c_bits_address,
  input  [31:0] auto_in_c_bits_data,
  input         auto_in_c_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [1:0]  auto_in_d_bits_param,
  output [3:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output [1:0]  auto_in_d_bits_sink,
  output        auto_in_d_bits_denied,
  output [31:0] auto_in_d_bits_data,
  output        auto_in_d_bits_corrupt,
  input         auto_in_e_valid,
  input  [1:0]  auto_in_e_bits_sink,
  input         auto_out_1_a_ready,
  output        auto_out_1_a_valid,
  output [2:0]  auto_out_1_a_bits_opcode,
  output [2:0]  auto_out_1_a_bits_param,
  output [2:0]  auto_out_1_a_bits_size,
  output [1:0]  auto_out_1_a_bits_source,
  output [30:0] auto_out_1_a_bits_address,
  output [3:0]  auto_out_1_a_bits_mask,
  output [31:0] auto_out_1_a_bits_data,
  output        auto_out_1_a_bits_corrupt,
  output        auto_out_1_b_ready,
  input         auto_out_1_b_valid,
  input  [1:0]  auto_out_1_b_bits_param,
  input  [30:0] auto_out_1_b_bits_address,
  input         auto_out_1_c_ready,
  output        auto_out_1_c_valid,
  output [2:0]  auto_out_1_c_bits_opcode,
  output [2:0]  auto_out_1_c_bits_param,
  output [2:0]  auto_out_1_c_bits_size,
  output [1:0]  auto_out_1_c_bits_source,
  output [30:0] auto_out_1_c_bits_address,
  output [31:0] auto_out_1_c_bits_data,
  output        auto_out_1_c_bits_corrupt,
  output        auto_out_1_d_ready,
  input         auto_out_1_d_valid,
  input  [2:0]  auto_out_1_d_bits_opcode,
  input  [1:0]  auto_out_1_d_bits_param,
  input  [2:0]  auto_out_1_d_bits_size,
  input  [1:0]  auto_out_1_d_bits_source,
  input  [1:0]  auto_out_1_d_bits_sink,
  input  [31:0] auto_out_1_d_bits_data,
  output        auto_out_1_e_valid,
  output [1:0]  auto_out_1_e_bits_sink,
  input         auto_out_0_a_ready,
  output        auto_out_0_a_valid,
  output [2:0]  auto_out_0_a_bits_opcode,
  output [2:0]  auto_out_0_a_bits_param,
  output [3:0]  auto_out_0_a_bits_size,
  output [1:0]  auto_out_0_a_bits_source,
  output [29:0] auto_out_0_a_bits_address,
  output [3:0]  auto_out_0_a_bits_mask,
  output [31:0] auto_out_0_a_bits_data,
  output        auto_out_0_a_bits_corrupt,
  output        auto_out_0_d_ready,
  input         auto_out_0_d_valid,
  input  [2:0]  auto_out_0_d_bits_opcode,
  input  [1:0]  auto_out_0_d_bits_param,
  input  [3:0]  auto_out_0_d_bits_size,
  input  [1:0]  auto_out_0_d_bits_source,
  input         auto_out_0_d_bits_sink,
  input         auto_out_0_d_bits_denied,
  input  [31:0] auto_out_0_d_bits_data,
  input         auto_out_0_d_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [30:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_b_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_b_valid; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_b_bits_param; // @[Nodes.scala 24:25]
  wire [30:0] monitor_io_in_b_bits_address; // @[Nodes.scala 24:25]
  wire  monitor_io_in_c_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_c_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_c_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_c_bits_param; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_c_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_c_bits_source; // @[Nodes.scala 24:25]
  wire [30:0] monitor_io_in_c_bits_address; // @[Nodes.scala 24:25]
  wire  monitor_io_in_c_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_e_valid; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_e_bits_sink; // @[Nodes.scala 24:25]
  reg [9:0] beatsLeft; // @[Arbiter.scala 87:30]
  wire  idle = beatsLeft == 10'h0; // @[Arbiter.scala 88:28]
  wire [1:0] readys_valid = {auto_out_1_d_valid,auto_out_0_d_valid}; // @[Cat.scala 31:58]
  reg [1:0] readys_mask; // @[Arbiter.scala 23:23]
  wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala 24:30]
  wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala 24:28]
  wire [3:0] readys_filter = {_readys_filter_T_1,auto_out_1_d_valid,auto_out_0_d_valid}; // @[Cat.scala 31:58]
  wire [3:0] _GEN_1 = {{1'd0}, readys_filter[3:1]}; // @[package.scala 253:43]
  wire [3:0] _readys_unready_T_1 = readys_filter | _GEN_1; // @[package.scala 253:43]
  wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala 25:66]
  wire [3:0] _GEN_2 = {{1'd0}, _readys_unready_T_1[3:1]}; // @[Arbiter.scala 25:58]
  wire [3:0] readys_unready = _GEN_2 | _readys_unready_T_4; // @[Arbiter.scala 25:58]
  wire [1:0] _readys_readys_T_2 = readys_unready[3:2] & readys_unready[1:0]; // @[Arbiter.scala 26:39]
  wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala 26:18]
  wire  readys_0 = readys_readys[0]; // @[Arbiter.scala 95:86]
  wire  earlyWinner_0 = readys_0 & auto_out_0_d_valid; // @[Arbiter.scala 97:79]
  reg  state_0; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_0 = idle ? earlyWinner_0 : state_0; // @[Arbiter.scala 117:30]
  wire [1:0] _T_37 = muxStateEarly_0 ? auto_out_0_d_bits_source : 2'h0; // @[Mux.scala 27:73]
  wire  readys_1 = readys_readys[1]; // @[Arbiter.scala 95:86]
  wire  earlyWinner_1 = readys_1 & auto_out_1_d_valid; // @[Arbiter.scala 97:79]
  reg  state_1; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_1 = idle ? earlyWinner_1 : state_1; // @[Arbiter.scala 117:30]
  wire [1:0] _T_38 = muxStateEarly_1 ? auto_out_1_d_bits_source : 2'h0; // @[Mux.scala 27:73]
  wire [31:0] _requestAIO_T_1 = {1'b0,$signed(auto_in_a_bits_address)}; // @[Parameters.scala 137:49]
  wire [31:0] _requestAIO_T_3 = $signed(_requestAIO_T_1) & 32'sh40000000; // @[Parameters.scala 137:52]
  wire  requestAIO_0_0 = $signed(_requestAIO_T_3) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _requestAIO_T_5 = auto_in_a_bits_address ^ 31'h40000000; // @[Parameters.scala 137:31]
  wire [31:0] _requestAIO_T_6 = {1'b0,$signed(_requestAIO_T_5)}; // @[Parameters.scala 137:49]
  wire [31:0] _requestAIO_T_8 = $signed(_requestAIO_T_6) & 32'sh40000000; // @[Parameters.scala 137:52]
  wire  requestAIO_0_1 = $signed(_requestAIO_T_8) == 32'sh0; // @[Parameters.scala 137:67]
  wire [26:0] _beatsDO_decode_T_1 = 27'hfff << auto_out_0_d_bits_size; // @[package.scala 234:77]
  wire [11:0] _beatsDO_decode_T_3 = ~_beatsDO_decode_T_1[11:0]; // @[package.scala 234:46]
  wire [9:0] beatsDO_decode = _beatsDO_decode_T_3[11:2]; // @[Edges.scala 219:59]
  wire  beatsDO_opdata = auto_out_0_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire [9:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 10'h0; // @[Edges.scala 220:14]
  wire [3:0] out_1_1_d_bits_size = {{1'd0}, auto_out_1_d_bits_size}; // @[BundleMap.scala 247:19 Xbar.scala 288:19]
  wire [20:0] _beatsDO_decode_T_5 = 21'h3f << out_1_1_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _beatsDO_decode_T_7 = ~_beatsDO_decode_T_5[5:0]; // @[package.scala 234:46]
  wire [3:0] beatsDO_decode_1 = _beatsDO_decode_T_7[5:2]; // @[Edges.scala 219:59]
  wire  beatsDO_opdata_1 = auto_out_1_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire [3:0] beatsDO_1 = beatsDO_opdata_1 ? beatsDO_decode_1 : 4'h0; // @[Edges.scala 220:14]
  wire  latch = idle & auto_in_d_ready; // @[Arbiter.scala 89:24]
  wire  _readys_T_3 = ~reset; // @[Arbiter.scala 22:12]
  wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala 28:29]
  wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala 244:48]
  wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_1[1:0]; // @[package.scala 244:43]
  wire  _prefixOR_T = earlyWinner_0 | earlyWinner_1; // @[Arbiter.scala 104:53]
  wire  _T_11 = auto_out_0_d_valid | auto_out_1_d_valid; // @[Arbiter.scala 107:36]
  wire  _T_12 = ~(auto_out_0_d_valid | auto_out_1_d_valid); // @[Arbiter.scala 107:15]
  wire [9:0] maskedBeats_0 = earlyWinner_0 ? beatsDO_0 : 10'h0; // @[Arbiter.scala 111:73]
  wire [3:0] maskedBeats_1 = earlyWinner_1 ? beatsDO_1 : 4'h0; // @[Arbiter.scala 111:73]
  wire [9:0] _GEN_3 = {{6'd0}, maskedBeats_1}; // @[Arbiter.scala 112:44]
  wire [9:0] initBeats = maskedBeats_0 | _GEN_3; // @[Arbiter.scala 112:44]
  wire  _sink_ACancel_earlyValid_T_3 = state_0 & auto_out_0_d_valid | state_1 & auto_out_1_d_valid; // @[Mux.scala 27:73]
  wire  sink_ACancel_5_earlyValid = idle ? _T_11 : _sink_ACancel_earlyValid_T_3; // @[Arbiter.scala 125:29]
  wire  _beatsLeft_T_2 = auto_in_d_ready & sink_ACancel_5_earlyValid; // @[ReadyValidCancel.scala 49:33]
  wire [9:0] _GEN_4 = {{9'd0}, _beatsLeft_T_2}; // @[Arbiter.scala 113:52]
  wire [9:0] _beatsLeft_T_4 = beatsLeft - _GEN_4; // @[Arbiter.scala 113:52]
  wire  allowed_0 = idle ? readys_0 : state_0; // @[Arbiter.scala 121:24]
  wire  allowed_1 = idle ? readys_1 : state_1; // @[Arbiter.scala 121:24]
  wire [31:0] _T_28 = muxStateEarly_0 ? auto_out_0_d_bits_data : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_29 = muxStateEarly_1 ? auto_out_1_d_bits_data : 32'h0; // @[Mux.scala 27:73]
  wire [1:0] out_1_0_d_bits_sink = {{1'd0}, auto_out_0_d_bits_sink}; // @[Xbar.scala 288:19 323:28]
  wire [1:0] _T_34 = muxStateEarly_0 ? out_1_0_d_bits_sink : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_35 = muxStateEarly_1 ? auto_out_1_d_bits_sink : 2'h0; // @[Mux.scala 27:73]
  wire [3:0] _T_40 = muxStateEarly_0 ? auto_out_0_d_bits_size : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _T_41 = muxStateEarly_1 ? out_1_1_d_bits_size : 4'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_43 = muxStateEarly_0 ? auto_out_0_d_bits_param : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_44 = muxStateEarly_1 ? auto_out_1_d_bits_param : 2'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_46 = muxStateEarly_0 ? auto_out_0_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_47 = muxStateEarly_1 ? auto_out_1_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  TLMonitor monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_b_ready(monitor_io_in_b_ready),
    .io_in_b_valid(monitor_io_in_b_valid),
    .io_in_b_bits_param(monitor_io_in_b_bits_param),
    .io_in_b_bits_address(monitor_io_in_b_bits_address),
    .io_in_c_ready(monitor_io_in_c_ready),
    .io_in_c_valid(monitor_io_in_c_valid),
    .io_in_c_bits_opcode(monitor_io_in_c_bits_opcode),
    .io_in_c_bits_param(monitor_io_in_c_bits_param),
    .io_in_c_bits_size(monitor_io_in_c_bits_size),
    .io_in_c_bits_source(monitor_io_in_c_bits_source),
    .io_in_c_bits_address(monitor_io_in_c_bits_address),
    .io_in_c_bits_corrupt(monitor_io_in_c_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_param(monitor_io_in_d_bits_param),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source),
    .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
    .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
    .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt),
    .io_in_e_valid(monitor_io_in_e_valid),
    .io_in_e_bits_sink(monitor_io_in_e_bits_sink)
  );
  assign auto_in_a_ready = requestAIO_0_0 & auto_out_0_a_ready | requestAIO_0_1 & auto_out_1_a_ready; // @[Mux.scala 27:73]
  assign auto_in_b_valid = auto_out_1_b_valid; // @[ReadyValidCancel.scala 21:38]
  assign auto_in_b_bits_param = auto_out_1_b_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_b_bits_address = auto_out_1_b_bits_address; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_c_ready = auto_out_1_c_ready; // @[Mux.scala 27:73]
  assign auto_in_d_valid = idle ? _T_11 : _sink_ACancel_earlyValid_T_3; // @[Arbiter.scala 125:29]
  assign auto_in_d_bits_opcode = _T_46 | _T_47; // @[Mux.scala 27:73]
  assign auto_in_d_bits_param = _T_43 | _T_44; // @[Mux.scala 27:73]
  assign auto_in_d_bits_size = _T_40 | _T_41; // @[Mux.scala 27:73]
  assign auto_in_d_bits_source = _T_37 | _T_38; // @[Mux.scala 27:73]
  assign auto_in_d_bits_sink = _T_34 | _T_35; // @[Mux.scala 27:73]
  assign auto_in_d_bits_denied = muxStateEarly_0 & auto_out_0_d_bits_denied; // @[Mux.scala 27:73]
  assign auto_in_d_bits_data = _T_28 | _T_29; // @[Mux.scala 27:73]
  assign auto_in_d_bits_corrupt = muxStateEarly_0 & auto_out_0_d_bits_corrupt; // @[Mux.scala 27:73]
  assign auto_out_1_a_valid = auto_in_a_valid & requestAIO_0_1; // @[Xbar.scala 428:50]
  assign auto_out_1_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_a_bits_size = auto_in_a_bits_size[2:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
  assign auto_out_1_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
  assign auto_out_1_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_b_ready = auto_in_b_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_c_valid = auto_in_c_valid; // @[ReadyValidCancel.scala 21:38]
  assign auto_out_1_c_bits_opcode = auto_in_c_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_c_bits_param = auto_in_c_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_c_bits_size = auto_in_c_bits_size[2:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
  assign auto_out_1_c_bits_source = auto_in_c_bits_source; // @[Xbar.scala 259:55]
  assign auto_out_1_c_bits_address = auto_in_c_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_c_bits_data = auto_in_c_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_c_bits_corrupt = auto_in_c_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_d_ready = auto_in_d_ready & allowed_1; // @[Arbiter.scala 123:31]
  assign auto_out_1_e_valid = auto_in_e_valid; // @[ReadyValidCancel.scala 21:38]
  assign auto_out_1_e_bits_sink = auto_in_e_bits_sink; // @[Xbar.scala 228:69]
  assign auto_out_0_a_valid = auto_in_a_valid & requestAIO_0_0; // @[Xbar.scala 428:50]
  assign auto_out_0_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_0_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_0_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_0_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
  assign auto_out_0_a_bits_address = auto_in_a_bits_address[29:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
  assign auto_out_0_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_0_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_0_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_0_d_ready = auto_in_d_ready & allowed_0; // @[Arbiter.scala 123:31]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = requestAIO_0_0 & auto_out_0_a_ready | requestAIO_0_1 & auto_out_1_a_ready; // @[Mux.scala 27:73]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_b_ready = auto_in_b_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_b_valid = auto_out_1_b_valid; // @[ReadyValidCancel.scala 21:38]
  assign monitor_io_in_b_bits_param = auto_out_1_b_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_b_bits_address = auto_out_1_b_bits_address; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_c_ready = auto_out_1_c_ready; // @[Mux.scala 27:73]
  assign monitor_io_in_c_valid = auto_in_c_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_opcode = auto_in_c_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_param = auto_in_c_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_size = auto_in_c_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_source = auto_in_c_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_address = auto_in_c_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_corrupt = auto_in_c_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = idle ? _T_11 : _sink_ACancel_earlyValid_T_3; // @[Arbiter.scala 125:29]
  assign monitor_io_in_d_bits_opcode = _T_46 | _T_47; // @[Mux.scala 27:73]
  assign monitor_io_in_d_bits_param = _T_43 | _T_44; // @[Mux.scala 27:73]
  assign monitor_io_in_d_bits_size = _T_40 | _T_41; // @[Mux.scala 27:73]
  assign monitor_io_in_d_bits_source = _T_37 | _T_38; // @[Mux.scala 27:73]
  assign monitor_io_in_d_bits_sink = _T_34 | _T_35; // @[Mux.scala 27:73]
  assign monitor_io_in_d_bits_denied = muxStateEarly_0 & auto_out_0_d_bits_denied; // @[Mux.scala 27:73]
  assign monitor_io_in_d_bits_corrupt = muxStateEarly_0 & auto_out_0_d_bits_corrupt; // @[Mux.scala 27:73]
  assign monitor_io_in_e_valid = auto_in_e_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_e_bits_sink = auto_in_e_bits_sink; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  always @(posedge clock) begin
    if (reset) begin // @[Arbiter.scala 87:30]
      beatsLeft <= 10'h0; // @[Arbiter.scala 87:30]
    end else if (latch) begin // @[Arbiter.scala 113:23]
      beatsLeft <= initBeats;
    end else begin
      beatsLeft <= _beatsLeft_T_4;
    end
    if (reset) begin // @[Arbiter.scala 23:23]
      readys_mask <= 2'h3; // @[Arbiter.scala 23:23]
    end else if (latch & |readys_valid) begin // @[Arbiter.scala 27:32]
      readys_mask <= _readys_mask_T_3; // @[Arbiter.scala 28:12]
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_0 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_0 <= earlyWinner_0;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_1 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_1 <= earlyWinner_1;
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~earlyWinner_0 | ~earlyWinner_1) & _readys_T_3) begin
          $fatal; // @[Arbiter.scala 105:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_readys_T_3 & ~(~earlyWinner_0 | ~earlyWinner_1)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:105 assert((prefixOR zip earlyWinner) map { case (p,w) => !p || !w } reduce {_ && _})\n"
            ); // @[Arbiter.scala 105:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(auto_out_0_d_valid | auto_out_1_d_valid) | _prefixOR_T) & _readys_T_3) begin
          $fatal; // @[Arbiter.scala 107:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_readys_T_3 & ~(~(auto_out_0_d_valid | auto_out_1_d_valid) | _prefixOR_T)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:107 assert (!earlyValids.reduce(_||_) || earlyWinner.reduce(_||_))\n"
            ); // @[Arbiter.scala 107:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_12 | _T_11) & _readys_T_3) begin
          $fatal; // @[Arbiter.scala 108:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_readys_T_3 & ~(_T_12 | _T_11)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:108 assert (!validQuals .reduce(_||_) || validQuals .reduce(_||_))\n"
            ); // @[Arbiter.scala 108:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  beatsLeft = _RAND_0[9:0];
  _RAND_1 = {1{`RANDOM}};
  readys_mask = _RAND_1[1:0];
  _RAND_2 = {1{`RANDOM}};
  state_0 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  state_1 = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLMonitor_1(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [3:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [30:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_b_ready,
  input         io_in_b_valid,
  input  [1:0]  io_in_b_bits_param,
  input  [30:0] io_in_b_bits_address,
  input         io_in_c_ready,
  input         io_in_c_valid,
  input  [2:0]  io_in_c_bits_opcode,
  input  [2:0]  io_in_c_bits_param,
  input  [3:0]  io_in_c_bits_size,
  input  [1:0]  io_in_c_bits_source,
  input  [30:0] io_in_c_bits_address,
  input         io_in_c_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_param,
  input  [3:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source,
  input  [1:0]  io_in_d_bits_sink,
  input         io_in_d_bits_denied,
  input         io_in_d_bits_corrupt,
  input         io_in_e_valid,
  input  [1:0]  io_in_e_bits_sink
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [31:0] _RAND_33;
  reg [31:0] _RAND_34;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [26:0] _is_aligned_mask_T_1 = 27'hfff << io_in_a_bits_size; // @[package.scala 234:77]
  wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1[11:0]; // @[package.scala 234:46]
  wire [30:0] _GEN_86 = {{19'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [30:0] _is_aligned_T = io_in_a_bits_address & _GEN_86; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 31'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 4'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire [31:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire  _T_35 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42]
  wire  _T_42 = _T_35 & source_ok; // @[Parameters.scala 1160:30]
  wire [31:0] _T_48 = $signed(_T_7) & -32'sh10001000; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_50 = io_in_a_bits_address ^ 31'h3000; // @[Parameters.scala 137:31]
  wire [31:0] _T_51 = {1'b0,$signed(_T_50)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_53 = $signed(_T_51) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _T_54 = $signed(_T_53) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_55 = io_in_a_bits_address ^ 31'h10000; // @[Parameters.scala 137:31]
  wire [31:0] _T_56 = {1'b0,$signed(_T_55)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_58 = $signed(_T_56) & -32'sh10000; // @[Parameters.scala 137:52]
  wire  _T_59 = $signed(_T_58) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_60 = io_in_a_bits_address ^ 31'h2000000; // @[Parameters.scala 137:31]
  wire [31:0] _T_61 = {1'b0,$signed(_T_60)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_63 = $signed(_T_61) & -32'sh10000; // @[Parameters.scala 137:52]
  wire  _T_64 = $signed(_T_63) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_65 = io_in_a_bits_address ^ 31'h8000000; // @[Parameters.scala 137:31]
  wire [31:0] _T_66 = {1'b0,$signed(_T_65)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_68 = $signed(_T_66) & -32'sh4000; // @[Parameters.scala 137:52]
  wire  _T_69 = $signed(_T_68) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_70 = io_in_a_bits_address ^ 31'hc000000; // @[Parameters.scala 137:31]
  wire [31:0] _T_71 = {1'b0,$signed(_T_70)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_73 = $signed(_T_71) & -32'sh4000000; // @[Parameters.scala 137:52]
  wire  _T_74 = $signed(_T_73) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_75 = io_in_a_bits_address ^ 31'h10012000; // @[Parameters.scala 137:31]
  wire [31:0] _T_76 = {1'b0,$signed(_T_75)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_78 = $signed(_T_76) & -32'sh2000; // @[Parameters.scala 137:52]
  wire  _T_79 = $signed(_T_78) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_80 = io_in_a_bits_address ^ 31'h10014000; // @[Parameters.scala 137:31]
  wire [31:0] _T_81 = {1'b0,$signed(_T_80)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_83 = $signed(_T_81) & -32'sh2000; // @[Parameters.scala 137:52]
  wire  _T_84 = $signed(_T_83) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_85 = io_in_a_bits_address ^ 31'h10016000; // @[Parameters.scala 137:31]
  wire [31:0] _T_86 = {1'b0,$signed(_T_85)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_88 = $signed(_T_86) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _T_89 = $signed(_T_88) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_90 = io_in_a_bits_address ^ 31'h10023000; // @[Parameters.scala 137:31]
  wire [31:0] _T_91 = {1'b0,$signed(_T_90)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_93 = $signed(_T_91) & -32'sh11000; // @[Parameters.scala 137:52]
  wire  _T_94 = $signed(_T_93) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_95 = io_in_a_bits_address ^ 31'h10024000; // @[Parameters.scala 137:31]
  wire [31:0] _T_96 = {1'b0,$signed(_T_95)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_98 = $signed(_T_96) & -32'sh12000; // @[Parameters.scala 137:52]
  wire  _T_99 = $signed(_T_98) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_100 = io_in_a_bits_address ^ 31'h10026000; // @[Parameters.scala 137:31]
  wire [31:0] _T_101 = {1'b0,$signed(_T_100)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_103 = $signed(_T_101) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _T_104 = $signed(_T_103) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_105 = io_in_a_bits_address ^ 31'h10043000; // @[Parameters.scala 137:31]
  wire [31:0] _T_106 = {1'b0,$signed(_T_105)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_108 = $signed(_T_106) & -32'sh11000; // @[Parameters.scala 137:52]
  wire  _T_109 = $signed(_T_108) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_110 = io_in_a_bits_address ^ 31'h20000000; // @[Parameters.scala 137:31]
  wire [31:0] _T_111 = {1'b0,$signed(_T_110)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_113 = $signed(_T_111) & -32'sh20000000; // @[Parameters.scala 137:52]
  wire  _T_114 = $signed(_T_113) == 32'sh0; // @[Parameters.scala 137:67]
  wire  _T_130 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42]
  wire [30:0] _T_133 = io_in_a_bits_address ^ 31'h40000000; // @[Parameters.scala 137:31]
  wire [31:0] _T_134 = {1'b0,$signed(_T_133)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_136 = $signed(_T_134) & -32'sh20000000; // @[Parameters.scala 137:52]
  wire  _T_137 = $signed(_T_136) == 32'sh0; // @[Parameters.scala 137:67]
  wire  _T_138 = _T_130 & _T_137; // @[Parameters.scala 670:56]
  wire  _T_141 = _T_42 & _T_138; // @[Monitor.scala 82:72]
  wire  _T_148 = 4'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_149 = _source_ok_T & _T_148; // @[Mux.scala 27:73]
  wire  _T_246 = _T_49 | _T_54 | _T_59 | _T_64 | _T_69 | _T_74 | _T_79 | _T_84 | _T_89 | _T_94 | _T_99 | _T_104 | _T_109
     | _T_114 | _T_137; // @[Parameters.scala 671:42]
  wire  _T_247 = _T_35 & _T_246; // @[Parameters.scala 670:56]
  wire  _T_249 = _T_149 & _T_247; // @[Monitor.scala 83:78]
  wire  _T_263 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_267 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_268 = _T_267 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_272 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_276 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_510 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_523 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_546 = _T_35 & _T_54; // @[Parameters.scala 670:56]
  wire  _T_633 = _T_49 | _T_59 | _T_64 | _T_69 | _T_74 | _T_79 | _T_84 | _T_89 | _T_94 | _T_99 | _T_104 | _T_109 |
    _T_114 | _T_137; // @[Parameters.scala 671:42]
  wire  _T_634 = _T_130 & _T_633; // @[Parameters.scala 670:56]
  wire  _T_636 = _T_546 | _T_634; // @[Parameters.scala 672:30]
  wire  _T_646 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_650 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_658 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_752 = _T_49 | _T_64 | _T_69 | _T_74 | _T_79 | _T_84 | _T_89 | _T_94 | _T_99 | _T_104 | _T_109; // @[Parameters.scala 671:42]
  wire  _T_753 = _T_49 | _T_64 | _T_69 | _T_74 | _T_79 | _T_84 | _T_89 | _T_94 | _T_99 | _T_104 | _T_109 | _T_137; // @[Parameters.scala 671:42]
  wire  _T_754 = _T_130 & _T_753; // @[Parameters.scala 670:56]
  wire  _T_769 = _T_546 | _T_754; // @[Parameters.scala 672:30]
  wire  _T_771 = _T_42 & _T_769; // @[Monitor.scala 115:71]
  wire  _T_789 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire  _T_879 = _T_130 & _T_752; // @[Parameters.scala 670:56]
  wire  _T_900 = _T_546 | _T_879; // @[Parameters.scala 672:30]
  wire  _T_902 = _T_42 & _T_900; // @[Monitor.scala 123:74]
  wire [3:0] _T_916 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_917 = io_in_a_bits_mask & _T_916; // @[Monitor.scala 127:31]
  wire  _T_918 = _T_917 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_922 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_934 = io_in_a_bits_size <= 4'h2; // @[Parameters.scala 92:42]
  wire  _T_1007 = _T_49 | _T_54 | _T_64 | _T_69 | _T_74 | _T_79 | _T_84 | _T_89 | _T_94 | _T_99 | _T_104 | _T_109; // @[Parameters.scala 671:42]
  wire  _T_1008 = _T_934 & _T_1007; // @[Parameters.scala 670:56]
  wire  _T_1030 = _T_42 & _T_1008; // @[Monitor.scala 131:74]
  wire  _T_1040 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_1048 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_1166 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_1174 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_1282 = _T_42 & _T_546; // @[Monitor.scala 147:68]
  wire  _T_1292 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_1304 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  _T_1308 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_1312 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 312:27]
  wire  _T_1316 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
  wire  _T_1320 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
  wire  _T_1324 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
  wire  _T_1328 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_1339 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
  wire  _T_1343 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
  wire  _T_1356 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_1376 = _T_1324 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
  wire  _T_1385 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_1402 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_1420 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire [31:0] _T_1444 = {1'b0,$signed(io_in_b_bits_address)}; // @[Parameters.scala 137:49]
  wire [30:0] _address_ok_T = io_in_b_bits_address ^ 31'h3000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_1 = {1'b0,$signed(_address_ok_T)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_3 = $signed(_address_ok_T_1) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_4 = $signed(_address_ok_T_3) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_5 = io_in_b_bits_address ^ 31'h10013000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_6 = {1'b0,$signed(_address_ok_T_5)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_8 = $signed(_address_ok_T_6) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_9 = $signed(_address_ok_T_8) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_10 = io_in_b_bits_address ^ 31'h10023000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_11 = {1'b0,$signed(_address_ok_T_10)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_13 = $signed(_address_ok_T_11) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_14 = $signed(_address_ok_T_13) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_15 = io_in_b_bits_address ^ 31'h10033000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_16 = {1'b0,$signed(_address_ok_T_15)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_18 = $signed(_address_ok_T_16) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_19 = $signed(_address_ok_T_18) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_20 = io_in_b_bits_address ^ 31'h10043000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_21 = {1'b0,$signed(_address_ok_T_20)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_23 = $signed(_address_ok_T_21) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_24 = $signed(_address_ok_T_23) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_25 = io_in_b_bits_address ^ 31'h10053000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_26 = {1'b0,$signed(_address_ok_T_25)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_28 = $signed(_address_ok_T_26) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_29 = $signed(_address_ok_T_28) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_30 = io_in_b_bits_address ^ 31'h10014000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_31 = {1'b0,$signed(_address_ok_T_30)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_33 = $signed(_address_ok_T_31) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_34 = $signed(_address_ok_T_33) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_35 = io_in_b_bits_address ^ 31'h20000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_36 = {1'b0,$signed(_address_ok_T_35)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_38 = $signed(_address_ok_T_36) & -32'sh20000000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_39 = $signed(_address_ok_T_38) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_40 = io_in_b_bits_address ^ 31'h10034000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_41 = {1'b0,$signed(_address_ok_T_40)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_43 = $signed(_address_ok_T_41) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_44 = $signed(_address_ok_T_43) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_45 = io_in_b_bits_address ^ 31'h10024000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_46 = {1'b0,$signed(_address_ok_T_45)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_48 = $signed(_address_ok_T_46) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_49 = $signed(_address_ok_T_48) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_50 = io_in_b_bits_address ^ 31'h10012000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_51 = {1'b0,$signed(_address_ok_T_50)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_53 = $signed(_address_ok_T_51) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_54 = $signed(_address_ok_T_53) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_55 = io_in_b_bits_address ^ 31'h10015000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_56 = {1'b0,$signed(_address_ok_T_55)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_58 = $signed(_address_ok_T_56) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_59 = $signed(_address_ok_T_58) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_60 = io_in_b_bits_address ^ 31'h10025000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_61 = {1'b0,$signed(_address_ok_T_60)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_63 = $signed(_address_ok_T_61) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_64 = $signed(_address_ok_T_63) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_65 = io_in_b_bits_address ^ 31'h10035000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_66 = {1'b0,$signed(_address_ok_T_65)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_68 = $signed(_address_ok_T_66) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_69 = $signed(_address_ok_T_68) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_70 = io_in_b_bits_address ^ 31'h10016000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_71 = {1'b0,$signed(_address_ok_T_70)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_73 = $signed(_address_ok_T_71) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_74 = $signed(_address_ok_T_73) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_75 = io_in_b_bits_address ^ 31'h10026000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_76 = {1'b0,$signed(_address_ok_T_75)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_78 = $signed(_address_ok_T_76) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_79 = $signed(_address_ok_T_78) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_80 = io_in_b_bits_address ^ 31'hc000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_81 = {1'b0,$signed(_address_ok_T_80)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_83 = $signed(_address_ok_T_81) & -32'sh4000000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_84 = $signed(_address_ok_T_83) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_85 = io_in_b_bits_address ^ 31'h2000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_86 = {1'b0,$signed(_address_ok_T_85)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_88 = $signed(_address_ok_T_86) & -32'sh10000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_89 = $signed(_address_ok_T_88) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _address_ok_T_93 = $signed(_T_1444) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_94 = $signed(_address_ok_T_93) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_95 = io_in_b_bits_address ^ 31'h8000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_96 = {1'b0,$signed(_address_ok_T_95)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_98 = $signed(_address_ok_T_96) & -32'sh4000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_99 = $signed(_address_ok_T_98) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_100 = io_in_b_bits_address ^ 31'h10000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_101 = {1'b0,$signed(_address_ok_T_100)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_103 = $signed(_address_ok_T_101) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_104 = $signed(_address_ok_T_103) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_105 = io_in_b_bits_address ^ 31'h10000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_106 = {1'b0,$signed(_address_ok_T_105)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_108 = $signed(_address_ok_T_106) & -32'sh10000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_109 = $signed(_address_ok_T_108) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_110 = io_in_b_bits_address ^ 31'h40000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_111 = {1'b0,$signed(_address_ok_T_110)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_113 = $signed(_address_ok_T_111) & -32'sh20000000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_114 = $signed(_address_ok_T_113) == 32'sh0; // @[Parameters.scala 137:67]
  wire  address_ok = _address_ok_T_4 | _address_ok_T_9 | _address_ok_T_14 | _address_ok_T_19 | _address_ok_T_24 |
    _address_ok_T_29 | _address_ok_T_34 | _address_ok_T_39 | _address_ok_T_44 | _address_ok_T_49 | _address_ok_T_54 |
    _address_ok_T_59 | _address_ok_T_64 | _address_ok_T_69 | _address_ok_T_74 | _address_ok_T_79 | _address_ok_T_84 |
    _address_ok_T_89 | _address_ok_T_94 | _address_ok_T_99 | _address_ok_T_104 | _address_ok_T_109 | _address_ok_T_114; // @[Parameters.scala 622:64]
  wire [30:0] _is_aligned_T_1 = io_in_b_bits_address & 31'h3f; // @[Edges.scala 20:16]
  wire  is_aligned_1 = _is_aligned_T_1 == 31'h0; // @[Edges.scala 20:24]
  wire [31:0] _T_1487 = $signed(_T_1444) & -32'sh10001000; // @[Parameters.scala 137:52]
  wire  _T_1488 = $signed(_T_1487) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_1517 = $signed(_address_ok_T_51) & -32'sh2000; // @[Parameters.scala 137:52]
  wire  _T_1518 = $signed(_T_1517) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_1522 = $signed(_address_ok_T_31) & -32'sh2000; // @[Parameters.scala 137:52]
  wire  _T_1523 = $signed(_T_1522) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_1532 = $signed(_address_ok_T_11) & -32'sh11000; // @[Parameters.scala 137:52]
  wire  _T_1533 = $signed(_T_1532) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_1537 = $signed(_address_ok_T_46) & -32'sh12000; // @[Parameters.scala 137:52]
  wire  _T_1538 = $signed(_T_1537) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_1547 = $signed(_address_ok_T_21) & -32'sh11000; // @[Parameters.scala 137:52]
  wire  _T_1548 = $signed(_T_1547) == 32'sh0; // @[Parameters.scala 137:67]
  wire  _T_1572 = _T_1488 | _address_ok_T_4 | _address_ok_T_109 | _address_ok_T_89 | _address_ok_T_99 | _address_ok_T_84
     | _T_1518 | _T_1523 | _address_ok_T_74 | _T_1533 | _T_1538 | _address_ok_T_79 | _T_1548 | _address_ok_T_39 |
    _address_ok_T_114; // @[Parameters.scala 671:42]
  wire  _T_1588 = io_in_b_bits_param <= 2'h2; // @[Bundles.scala 102:26]
  wire  _source_ok_T_8 = io_in_c_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_9 = io_in_c_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_10 = io_in_c_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_2 = _source_ok_T_8 | _source_ok_T_9 | _source_ok_T_10; // @[Parameters.scala 1125:46]
  wire [26:0] _is_aligned_mask_T_7 = 27'hfff << io_in_c_bits_size; // @[package.scala 234:77]
  wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_7[11:0]; // @[package.scala 234:46]
  wire [30:0] _GEN_87 = {{19'd0}, is_aligned_mask_2}; // @[Edges.scala 20:16]
  wire [30:0] _is_aligned_T_2 = io_in_c_bits_address & _GEN_87; // @[Edges.scala 20:16]
  wire  is_aligned_2 = _is_aligned_T_2 == 31'h0; // @[Edges.scala 20:24]
  wire [30:0] _address_ok_T_136 = io_in_c_bits_address ^ 31'h3000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_137 = {1'b0,$signed(_address_ok_T_136)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_139 = $signed(_address_ok_T_137) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_140 = $signed(_address_ok_T_139) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_141 = io_in_c_bits_address ^ 31'h10013000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_142 = {1'b0,$signed(_address_ok_T_141)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_144 = $signed(_address_ok_T_142) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_145 = $signed(_address_ok_T_144) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_146 = io_in_c_bits_address ^ 31'h10023000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_147 = {1'b0,$signed(_address_ok_T_146)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_149 = $signed(_address_ok_T_147) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_150 = $signed(_address_ok_T_149) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_151 = io_in_c_bits_address ^ 31'h10033000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_152 = {1'b0,$signed(_address_ok_T_151)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_154 = $signed(_address_ok_T_152) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_155 = $signed(_address_ok_T_154) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_156 = io_in_c_bits_address ^ 31'h10043000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_157 = {1'b0,$signed(_address_ok_T_156)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_159 = $signed(_address_ok_T_157) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_160 = $signed(_address_ok_T_159) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_161 = io_in_c_bits_address ^ 31'h10053000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_162 = {1'b0,$signed(_address_ok_T_161)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_164 = $signed(_address_ok_T_162) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_165 = $signed(_address_ok_T_164) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_166 = io_in_c_bits_address ^ 31'h10014000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_167 = {1'b0,$signed(_address_ok_T_166)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_169 = $signed(_address_ok_T_167) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_170 = $signed(_address_ok_T_169) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_171 = io_in_c_bits_address ^ 31'h20000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_172 = {1'b0,$signed(_address_ok_T_171)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_174 = $signed(_address_ok_T_172) & -32'sh20000000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_175 = $signed(_address_ok_T_174) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_176 = io_in_c_bits_address ^ 31'h10034000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_177 = {1'b0,$signed(_address_ok_T_176)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_179 = $signed(_address_ok_T_177) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_180 = $signed(_address_ok_T_179) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_181 = io_in_c_bits_address ^ 31'h10024000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_182 = {1'b0,$signed(_address_ok_T_181)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_184 = $signed(_address_ok_T_182) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_185 = $signed(_address_ok_T_184) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_186 = io_in_c_bits_address ^ 31'h10012000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_187 = {1'b0,$signed(_address_ok_T_186)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_189 = $signed(_address_ok_T_187) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_190 = $signed(_address_ok_T_189) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_191 = io_in_c_bits_address ^ 31'h10015000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_192 = {1'b0,$signed(_address_ok_T_191)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_194 = $signed(_address_ok_T_192) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_195 = $signed(_address_ok_T_194) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_196 = io_in_c_bits_address ^ 31'h10025000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_197 = {1'b0,$signed(_address_ok_T_196)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_199 = $signed(_address_ok_T_197) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_200 = $signed(_address_ok_T_199) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_201 = io_in_c_bits_address ^ 31'h10035000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_202 = {1'b0,$signed(_address_ok_T_201)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_204 = $signed(_address_ok_T_202) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_205 = $signed(_address_ok_T_204) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_206 = io_in_c_bits_address ^ 31'h10016000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_207 = {1'b0,$signed(_address_ok_T_206)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_209 = $signed(_address_ok_T_207) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_210 = $signed(_address_ok_T_209) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_211 = io_in_c_bits_address ^ 31'h10026000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_212 = {1'b0,$signed(_address_ok_T_211)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_214 = $signed(_address_ok_T_212) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_215 = $signed(_address_ok_T_214) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_216 = io_in_c_bits_address ^ 31'hc000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_217 = {1'b0,$signed(_address_ok_T_216)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_219 = $signed(_address_ok_T_217) & -32'sh4000000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_220 = $signed(_address_ok_T_219) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_221 = io_in_c_bits_address ^ 31'h2000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_222 = {1'b0,$signed(_address_ok_T_221)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_224 = $signed(_address_ok_T_222) & -32'sh10000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_225 = $signed(_address_ok_T_224) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _address_ok_T_227 = {1'b0,$signed(io_in_c_bits_address)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_229 = $signed(_address_ok_T_227) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_230 = $signed(_address_ok_T_229) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_231 = io_in_c_bits_address ^ 31'h8000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_232 = {1'b0,$signed(_address_ok_T_231)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_234 = $signed(_address_ok_T_232) & -32'sh4000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_235 = $signed(_address_ok_T_234) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_236 = io_in_c_bits_address ^ 31'h10000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_237 = {1'b0,$signed(_address_ok_T_236)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_239 = $signed(_address_ok_T_237) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_240 = $signed(_address_ok_T_239) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_241 = io_in_c_bits_address ^ 31'h10000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_242 = {1'b0,$signed(_address_ok_T_241)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_244 = $signed(_address_ok_T_242) & -32'sh10000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_245 = $signed(_address_ok_T_244) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_246 = io_in_c_bits_address ^ 31'h40000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_247 = {1'b0,$signed(_address_ok_T_246)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_249 = $signed(_address_ok_T_247) & -32'sh20000000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_250 = $signed(_address_ok_T_249) == 32'sh0; // @[Parameters.scala 137:67]
  wire  address_ok_1 = _address_ok_T_140 | _address_ok_T_145 | _address_ok_T_150 | _address_ok_T_155 | _address_ok_T_160
     | _address_ok_T_165 | _address_ok_T_170 | _address_ok_T_175 | _address_ok_T_180 | _address_ok_T_185 |
    _address_ok_T_190 | _address_ok_T_195 | _address_ok_T_200 | _address_ok_T_205 | _address_ok_T_210 |
    _address_ok_T_215 | _address_ok_T_220 | _address_ok_T_225 | _address_ok_T_230 | _address_ok_T_235 |
    _address_ok_T_240 | _address_ok_T_245 | _address_ok_T_250; // @[Parameters.scala 622:64]
  wire  _T_2341 = io_in_c_bits_opcode == 3'h4; // @[Monitor.scala 242:25]
  wire  _T_2348 = io_in_c_bits_size >= 4'h2; // @[Monitor.scala 245:30]
  wire  _T_2355 = io_in_c_bits_param <= 3'h5; // @[Bundles.scala 120:29]
  wire  _T_2359 = ~io_in_c_bits_corrupt; // @[Monitor.scala 248:18]
  wire  _T_2363 = io_in_c_bits_opcode == 3'h5; // @[Monitor.scala 251:25]
  wire  _T_2381 = io_in_c_bits_opcode == 3'h6; // @[Monitor.scala 259:25]
  wire  _T_2383 = io_in_c_bits_size <= 4'hc; // @[Parameters.scala 92:42]
  wire  _T_2390 = _T_2383 & source_ok_2; // @[Parameters.scala 1160:30]
  wire [31:0] _T_2396 = $signed(_address_ok_T_227) & -32'sh10001000; // @[Parameters.scala 137:52]
  wire  _T_2397 = $signed(_T_2396) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_2426 = $signed(_address_ok_T_187) & -32'sh2000; // @[Parameters.scala 137:52]
  wire  _T_2427 = $signed(_T_2426) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_2431 = $signed(_address_ok_T_167) & -32'sh2000; // @[Parameters.scala 137:52]
  wire  _T_2432 = $signed(_T_2431) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_2441 = $signed(_address_ok_T_147) & -32'sh11000; // @[Parameters.scala 137:52]
  wire  _T_2442 = $signed(_T_2441) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_2446 = $signed(_address_ok_T_182) & -32'sh12000; // @[Parameters.scala 137:52]
  wire  _T_2447 = $signed(_T_2446) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_2456 = $signed(_address_ok_T_157) & -32'sh11000; // @[Parameters.scala 137:52]
  wire  _T_2457 = $signed(_T_2456) == 32'sh0; // @[Parameters.scala 137:67]
  wire  _T_2478 = io_in_c_bits_size <= 4'h6; // @[Parameters.scala 92:42]
  wire  _T_2486 = _T_2478 & _address_ok_T_250; // @[Parameters.scala 670:56]
  wire  _T_2489 = _T_2390 & _T_2486; // @[Monitor.scala 260:78]
  wire  _T_2496 = 4'h6 == io_in_c_bits_size; // @[Parameters.scala 91:48]
  wire  _T_2497 = _source_ok_T_8 & _T_2496; // @[Mux.scala 27:73]
  wire  _T_2594 = _T_2397 | _address_ok_T_140 | _address_ok_T_245 | _address_ok_T_225 | _address_ok_T_235 |
    _address_ok_T_220 | _T_2427 | _T_2432 | _address_ok_T_210 | _T_2442 | _T_2447 | _address_ok_T_215 | _T_2457 |
    _address_ok_T_175 | _address_ok_T_250; // @[Parameters.scala 671:42]
  wire  _T_2595 = _T_2383 & _T_2594; // @[Parameters.scala 670:56]
  wire  _T_2597 = _T_2497 & _T_2595; // @[Monitor.scala 261:78]
  wire  _T_2619 = io_in_c_bits_opcode == 3'h7; // @[Monitor.scala 269:25]
  wire  _T_2853 = io_in_c_bits_opcode == 3'h0; // @[Monitor.scala 278:25]
  wire  _T_2863 = io_in_c_bits_param == 3'h0; // @[Monitor.scala 282:31]
  wire  _T_2871 = io_in_c_bits_opcode == 3'h1; // @[Monitor.scala 286:25]
  wire  _T_2885 = io_in_c_bits_opcode == 3'h2; // @[Monitor.scala 293:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [9:0] a_first_beats1_decode = is_aligned_mask[11:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [9:0] a_first_counter; // @[Edges.scala 228:27]
  wire [9:0] a_first_counter1 = a_first_counter - 10'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 10'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [3:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [30:0] address; // @[Monitor.scala 388:22]
  wire  _T_2907 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_2908 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_2912 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_2916 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_2920 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_2924 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [26:0] _d_first_beats1_decode_T_1 = 27'hfff << io_in_d_bits_size; // @[package.scala 234:77]
  wire [11:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
  wire [9:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[11:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [9:0] d_first_counter; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1 = d_first_counter - 10'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 10'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] param_1; // @[Monitor.scala 536:22]
  reg [3:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  reg [1:0] sink; // @[Monitor.scala 539:22]
  reg  denied; // @[Monitor.scala 540:22]
  wire  _T_2931 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_2932 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_2936 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
  wire  _T_2940 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_2944 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  wire  _T_2948 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
  wire  _T_2952 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
  wire  b_first_done = io_in_b_ready & io_in_b_valid; // @[Decoupled.scala 50:35]
  reg [9:0] b_first_counter; // @[Edges.scala 228:27]
  wire [9:0] b_first_counter1 = b_first_counter - 10'h1; // @[Edges.scala 229:28]
  wire  b_first = b_first_counter == 10'h0; // @[Edges.scala 230:25]
  reg [1:0] param_2; // @[Monitor.scala 408:22]
  reg [30:0] address_1; // @[Monitor.scala 411:22]
  wire  _T_2959 = io_in_b_valid & ~b_first; // @[Monitor.scala 412:19]
  wire  _T_2964 = io_in_b_bits_param == param_2; // @[Monitor.scala 414:32]
  wire  _T_2976 = io_in_b_bits_address == address_1; // @[Monitor.scala 417:32]
  wire  _c_first_T = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala 50:35]
  wire [9:0] c_first_beats1_decode = is_aligned_mask_2[11:2]; // @[Edges.scala 219:59]
  wire  c_first_beats1_opdata = io_in_c_bits_opcode[0]; // @[Edges.scala 101:36]
  reg [9:0] c_first_counter; // @[Edges.scala 228:27]
  wire [9:0] c_first_counter1 = c_first_counter - 10'h1; // @[Edges.scala 229:28]
  wire  c_first = c_first_counter == 10'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_3; // @[Monitor.scala 512:22]
  reg [2:0] param_3; // @[Monitor.scala 513:22]
  reg [3:0] size_3; // @[Monitor.scala 514:22]
  reg [1:0] source_3; // @[Monitor.scala 515:22]
  reg [30:0] address_2; // @[Monitor.scala 516:22]
  wire  _T_2983 = io_in_c_valid & ~c_first; // @[Monitor.scala 517:19]
  wire  _T_2984 = io_in_c_bits_opcode == opcode_3; // @[Monitor.scala 518:32]
  wire  _T_2988 = io_in_c_bits_param == param_3; // @[Monitor.scala 519:32]
  wire  _T_2992 = io_in_c_bits_size == size_3; // @[Monitor.scala 520:32]
  wire  _T_2996 = io_in_c_bits_source == source_3; // @[Monitor.scala 521:32]
  wire  _T_3000 = io_in_c_bits_address == address_2; // @[Monitor.scala 522:32]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [23:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [9:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [9:0] a_first_counter1_1 = a_first_counter_1 - 10'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 10'h0; // @[Edges.scala 230:25]
  reg [9:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1_1 = d_first_counter_1 - 10'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 10'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_88 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_88}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_89 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_89 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [4:0] _a_size_lookup_T = {io_in_d_bits_source, 3'h0}; // @[Monitor.scala 638:65]
  wire [23:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _a_size_lookup_T_5 = 16'h100 - 16'h1; // @[Monitor.scala 609:57]
  wire [23:0] _GEN_91 = {{8'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 638:91]
  wire [23:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_91; // @[Monitor.scala 638:91]
  wire [23:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[23:1]}; // @[Monitor.scala 638:144]
  wire  _T_3006 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _GEN_27 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_3009 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [4:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 5'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_93 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_93}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [4:0] _a_sizes_set_T = {io_in_a_bits_source, 3'h0}; // @[Monitor.scala 657:77]
  wire [4:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala 652:72 655:28]
  wire [35:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [35:0] _a_sizes_set_T_1 = _GEN_2 << _a_sizes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_3011 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_3013 = ~_T_3011[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_28 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_31 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [35:0] _GEN_32 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 36'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_3017 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_3019 = ~_T_1308; // @[Monitor.scala 671:74]
  wire  _T_3020 = io_in_d_valid & d_first_1 & ~_T_1308; // @[Monitor.scala 671:71]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _GEN_33 = io_in_d_valid & d_first_1 & ~_T_1308 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 671:90 672:22]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [46:0] _GEN_4 = {{31'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 678:74]
  wire [46:0] _d_sizes_clr_T_5 = _GEN_4 << _a_size_lookup_T; // @[Monitor.scala 678:74]
  wire [3:0] _GEN_34 = _d_first_T & d_first_1 & _T_3019 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_35 = _d_first_T & d_first_1 & _T_3019 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire [46:0] _GEN_36 = _d_first_T & d_first_1 & _T_3019 ? _d_sizes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 678:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_3006 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_3030 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_3032 = _T_3030[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_39 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_40 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_39; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_41 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_40; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_42 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_41; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_43 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_42; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_44 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_43; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_51 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_42; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_52 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_51; // @[Monitor.scala 686:{39,39}]
  wire  _T_3037 = io_in_d_bits_opcode == _GEN_52; // @[Monitor.scala 686:39]
  wire  _T_3038 = io_in_d_bits_opcode == _GEN_44 | _T_3037; // @[Monitor.scala 685:77]
  wire  _T_3042 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_55 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_56 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_55; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_57 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_56; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_58 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_57; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_59 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_58; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_60 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_59; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_67 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_58; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_68 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_67; // @[Monitor.scala 690:{38,38}]
  wire  _T_3049 = io_in_d_bits_opcode == _GEN_68; // @[Monitor.scala 690:38]
  wire  _T_3050 = io_in_d_bits_opcode == _GEN_60 | _T_3049; // @[Monitor.scala 689:72]
  wire [7:0] a_size_lookup = _a_size_lookup_T_7[7:0];
  wire [7:0] _GEN_95 = {{4'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_3054 = _GEN_95 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_3064 = _T_3017 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_3019; // @[Monitor.scala 694:116]
  wire  _T_3065 = ~io_in_d_ready; // @[Monitor.scala 695:15]
  wire  _T_3066 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set_wo_ready = _GEN_27[2:0];
  wire [2:0] d_clr_wo_ready = _GEN_33[2:0];
  wire  _T_3073 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire [2:0] a_set = _GEN_28[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_34[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_31[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_35[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [23:0] a_sizes_set = _GEN_32[23:0];
  wire [23:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [23:0] d_sizes_clr = _GEN_36[23:0];
  wire [23:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala 704:56]
  wire [23:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_3082 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [2:0] inflight_1; // @[Monitor.scala 723:35]
  reg [23:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [9:0] c_first_counter_1; // @[Edges.scala 228:27]
  wire [9:0] c_first_counter1_1 = c_first_counter_1 - 10'h1; // @[Edges.scala 229:28]
  wire  c_first_1 = c_first_counter_1 == 10'h0; // @[Edges.scala 230:25]
  reg [9:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1_2 = d_first_counter_2 - 10'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 10'h0; // @[Edges.scala 230:25]
  wire [23:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_size_lookup_T; // @[Monitor.scala 747:42]
  wire [23:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_91; // @[Monitor.scala 747:93]
  wire [23:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[23:1]}; // @[Monitor.scala 747:146]
  wire  _T_3092 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala 67:40]
  wire  _T_3093 = io_in_c_valid & c_first_1 & _T_3092; // @[Monitor.scala 756:37]
  wire [3:0] _c_set_wo_ready_T = 4'h1 << io_in_c_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _GEN_72 = io_in_c_valid & c_first_1 & _T_3092 ? _c_set_wo_ready_T : 4'h0; // @[Monitor.scala 756:71 757:22]
  wire  _T_3099 = _c_first_T & c_first_1 & _T_3092; // @[Monitor.scala 760:38]
  wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size, 1'h0}; // @[Monitor.scala 763:51]
  wire [4:0] _c_sizes_set_interm_T_1 = _c_sizes_set_interm_T | 5'h1; // @[Monitor.scala 763:59]
  wire [4:0] _c_sizes_set_T = {io_in_c_bits_source, 3'h0}; // @[Monitor.scala 765:77]
  wire [4:0] c_sizes_set_interm = _c_first_T & c_first_1 & _T_3092 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala 760:72 763:28]
  wire [35:0] _GEN_5 = {{31'd0}, c_sizes_set_interm}; // @[Monitor.scala 765:52]
  wire [35:0] _c_sizes_set_T_1 = _GEN_5 << _c_sizes_set_T; // @[Monitor.scala 765:52]
  wire [2:0] _T_3100 = inflight_1 >> io_in_c_bits_source; // @[Monitor.scala 766:26]
  wire  _T_3102 = ~_T_3100[0]; // @[Monitor.scala 766:17]
  wire [3:0] _GEN_73 = _c_first_T & c_first_1 & _T_3092 ? _c_set_wo_ready_T : 4'h0; // @[Monitor.scala 760:72 761:28]
  wire [35:0] _GEN_77 = _c_first_T & c_first_1 & _T_3092 ? _c_sizes_set_T_1 : 36'h0; // @[Monitor.scala 760:72 765:28]
  wire  _T_3106 = io_in_d_valid & d_first_2; // @[Monitor.scala 779:26]
  wire  _T_3108 = io_in_d_valid & d_first_2 & _T_1308; // @[Monitor.scala 779:71]
  wire [3:0] _GEN_78 = io_in_d_valid & d_first_2 & _T_1308 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 779:89 780:22]
  wire [3:0] _GEN_79 = _d_first_T & d_first_2 & _T_1308 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 783:90 784:21]
  wire [46:0] _GEN_81 = _d_first_T & d_first_2 & _T_1308 ? _d_sizes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 786:21]
  wire  _same_cycle_resp_T_8 = io_in_c_bits_source == io_in_d_bits_source; // @[Monitor.scala 790:113]
  wire  same_cycle_resp_1 = _T_3093 & io_in_c_bits_source == io_in_d_bits_source; // @[Monitor.scala 790:88]
  wire [2:0] _T_3116 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire  _T_3118 = _T_3116[0] | same_cycle_resp_1; // @[Monitor.scala 791:49]
  wire  _T_3122 = io_in_d_bits_size == io_in_c_bits_size; // @[Monitor.scala 793:36]
  wire [7:0] c_size_lookup = _c_size_lookup_T_7[7:0];
  wire  _T_3126 = _GEN_95 == c_size_lookup; // @[Monitor.scala 795:36]
  wire  _T_3135 = _T_3106 & c_first_1 & io_in_c_valid & _same_cycle_resp_T_8 & _T_1308; // @[Monitor.scala 799:116]
  wire  _T_3137 = _T_3065 | io_in_c_ready; // @[Monitor.scala 800:32]
  wire [2:0] c_set_wo_ready = _GEN_72[2:0];
  wire  _T_3141 = |c_set_wo_ready; // @[Monitor.scala 804:28]
  wire [2:0] d_clr_wo_ready_1 = _GEN_78[2:0];
  wire  _T_3142 = c_set_wo_ready != d_clr_wo_ready_1; // @[Monitor.scala 805:31]
  wire [2:0] c_set = _GEN_73[2:0];
  wire [2:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala 809:35]
  wire [2:0] d_clr_1 = _GEN_79[2:0];
  wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [2:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [23:0] c_sizes_set = _GEN_77[23:0];
  wire [23:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala 811:41]
  wire [23:0] d_sizes_clr_1 = _GEN_81[23:0];
  wire [23:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
  wire [23:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_3151 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  reg [3:0] inflight_2; // @[Monitor.scala 823:27]
  reg [9:0] d_first_counter_3; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1_3 = d_first_counter_3 - 10'h1; // @[Edges.scala 229:28]
  wire  d_first_3 = d_first_counter_3 == 10'h0; // @[Edges.scala 230:25]
  wire  _T_3163 = io_in_d_bits_opcode[2] & ~io_in_d_bits_opcode[1]; // @[Edges.scala 70:40]
  wire  _T_3164 = _d_first_T & d_first_3 & _T_3163; // @[Monitor.scala 829:38]
  wire [3:0] _d_set_T = 4'h1 << io_in_d_bits_sink; // @[OneHot.scala 57:35]
  wire [3:0] _T_3165 = inflight_2 >> io_in_d_bits_sink; // @[Monitor.scala 831:23]
  wire  _T_3167 = ~_T_3165[0]; // @[Monitor.scala 831:14]
  wire [3:0] d_set = _d_first_T & d_first_3 & _T_3163 ? _d_set_T : 4'h0; // @[Monitor.scala 829:72 830:13]
  wire [3:0] _e_clr_T = 4'h1 << io_in_e_bits_sink; // @[OneHot.scala 57:35]
  wire [3:0] _T_3174 = d_set | inflight_2; // @[Monitor.scala 837:24]
  wire [3:0] _T_3175 = _T_3174 >> io_in_e_bits_sink; // @[Monitor.scala 837:35]
  wire [3:0] e_clr = io_in_e_valid ? _e_clr_T : 4'h0; // @[Monitor.scala 835:73 836:13]
  wire [3:0] _inflight_T_6 = inflight_2 | d_set; // @[Monitor.scala 842:27]
  wire [3:0] _inflight_T_7 = ~e_clr; // @[Monitor.scala 842:38]
  wire [3:0] _inflight_T_8 = _inflight_T_6 & _inflight_T_7; // @[Monitor.scala 842:36]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 10'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 10'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 10'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      b_first_counter <= 10'h0; // @[Edges.scala 228:27]
    end else if (b_first_done) begin // @[Edges.scala 234:17]
      if (b_first) begin // @[Edges.scala 235:21]
        b_first_counter <= 10'h0;
      end else begin
        b_first_counter <= b_first_counter1;
      end
    end
    if (b_first_done & b_first) begin // @[Monitor.scala 419:32]
      param_2 <= io_in_b_bits_param; // @[Monitor.scala 421:15]
    end
    if (b_first_done & b_first) begin // @[Monitor.scala 419:32]
      address_1 <= io_in_b_bits_address; // @[Monitor.scala 424:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      c_first_counter <= 10'h0; // @[Edges.scala 228:27]
    end else if (_c_first_T) begin // @[Edges.scala 234:17]
      if (c_first) begin // @[Edges.scala 235:21]
        if (c_first_beats1_opdata) begin // @[Edges.scala 220:14]
          c_first_counter <= c_first_beats1_decode;
        end else begin
          c_first_counter <= 10'h0;
        end
      end else begin
        c_first_counter <= c_first_counter1;
      end
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      opcode_3 <= io_in_c_bits_opcode; // @[Monitor.scala 525:15]
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      param_3 <= io_in_c_bits_param; // @[Monitor.scala 526:15]
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      size_3 <= io_in_c_bits_size; // @[Monitor.scala 527:15]
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      source_3 <= io_in_c_bits_source; // @[Monitor.scala 528:15]
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      address_2 <= io_in_c_bits_address; // @[Monitor.scala 529:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 24'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 10'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 10'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 3'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 24'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      c_first_counter_1 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_c_first_T) begin // @[Edges.scala 234:17]
      if (c_first_1) begin // @[Edges.scala 235:21]
        if (c_first_beats1_opdata) begin // @[Edges.scala 220:14]
          c_first_counter_1 <= c_first_beats1_decode;
        end else begin
          c_first_counter_1 <= 10'h0;
        end
      end else begin
        c_first_counter_1 <= c_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 10'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_c_first_T | _d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    if (reset) begin // @[Monitor.scala 823:27]
      inflight_2 <= 4'h0; // @[Monitor.scala 823:27]
    end else begin
      inflight_2 <= _inflight_T_8; // @[Monitor.scala 842:14]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_3 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_3) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_3 <= d_first_beats1_decode;
        end else begin
          d_first_counter_3 <= 10'h0;
        end
      end else begin
        d_first_counter_3 <= d_first_counter1_3;
      end
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_141 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_141) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_249 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_249) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_263 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_263) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_268 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_268) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_272 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_272) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_141 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_T_141) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_249 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_T_249) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_263 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_T_263) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_510 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_T_510) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_268 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_T_268) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_272 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_T_272) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_42 & (io_in_a_valid & _T_523 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_523 & ~reset & ~_T_42) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_636 & (io_in_a_valid & _T_523 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_523 & ~reset & ~_T_636) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_523 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_523 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_523 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_523 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_646 & (io_in_a_valid & _T_523 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_523 & ~reset & ~_T_646) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_650 & (io_in_a_valid & _T_523 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_523 & ~reset & ~_T_650) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_272 & (io_in_a_valid & _T_523 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_523 & ~reset & ~_T_272) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_771 & (io_in_a_valid & _T_658 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_658 & ~reset & ~_T_771) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_658 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_658 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_658 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_658 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_646 & (io_in_a_valid & _T_658 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_658 & ~reset & ~_T_646) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_650 & (io_in_a_valid & _T_658 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_658 & ~reset & ~_T_650) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_902 & (io_in_a_valid & _T_789 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_789 & ~reset & ~_T_902) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_789 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_789 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_789 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_789 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_646 & (io_in_a_valid & _T_789 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_789 & ~reset & ~_T_646) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_918 & (io_in_a_valid & _T_789 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_789 & ~reset & ~_T_918) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1030 & (io_in_a_valid & _T_922 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_922 & ~reset & ~_T_1030) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_922 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_922 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_922 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_922 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1040 & (io_in_a_valid & _T_922 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_922 & ~reset & ~_T_1040) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_650 & (io_in_a_valid & _T_922 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_922 & ~reset & ~_T_650) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1030 & (io_in_a_valid & _T_1048 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1048 & ~reset & ~_T_1030) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_1048 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1048 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_1048 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1048 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1166 & (io_in_a_valid & _T_1048 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1048 & ~reset & ~_T_1166) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_650 & (io_in_a_valid & _T_1048 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1048 & ~reset & ~_T_650) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1282 & (io_in_a_valid & _T_1174 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1174 & ~reset & ~_T_1282) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_1174 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1174 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_1174 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1174 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1292 & (io_in_a_valid & _T_1174 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1174 & ~reset & ~_T_1292) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_650 & (io_in_a_valid & _T_1174 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1174 & ~reset & ~_T_650) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_272 & (io_in_a_valid & _T_1174 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1174 & ~reset & ~_T_272) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1304 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_1304) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1308 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1308 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1312 & (io_in_d_valid & _T_1308 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1308 & _T_2 & ~_T_1312) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1316 & (io_in_d_valid & _T_1308 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1308 & _T_2 & ~_T_1316) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1320 & (io_in_d_valid & _T_1308 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1308 & _T_2 & ~_T_1320) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1324 & (io_in_d_valid & _T_1308 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1308 & _T_2 & ~_T_1324) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is denied (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1328 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1328 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1312 & (io_in_d_valid & _T_1328 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1328 & _T_2 & ~_T_1312) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1339 & (io_in_d_valid & _T_1328 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1328 & _T_2 & ~_T_1339) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid cap param (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1343 & (io_in_d_valid & _T_1328 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1328 & _T_2 & ~_T_1343) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries toN param (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1320 & (io_in_d_valid & _T_1328 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1328 & _T_2 & ~_T_1320) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is corrupt (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1356 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1356 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1312 & (io_in_d_valid & _T_1356 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1356 & _T_2 & ~_T_1312) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1339 & (io_in_d_valid & _T_1356 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1356 & _T_2 & ~_T_1339) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1343 & (io_in_d_valid & _T_1356 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1356 & _T_2 & ~_T_1343) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries toN param (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1376 & (io_in_d_valid & _T_1356 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1356 & _T_2 & ~_T_1376) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1385 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1385 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1316 & (io_in_d_valid & _T_1385 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1385 & _T_2 & ~_T_1316) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid param (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1320 & (io_in_d_valid & _T_1385 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1385 & _T_2 & ~_T_1320) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is corrupt (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1402 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1402 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1316 & (io_in_d_valid & _T_1402 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1402 & _T_2 & ~_T_1316) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1376 & (io_in_d_valid & _T_1402 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1402 & _T_2 & ~_T_1376) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1420 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1420 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1316 & (io_in_d_valid & _T_1420 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1420 & _T_2 & ~_T_1316) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid param (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1320 & (io_in_d_valid & _T_1420 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1420 & _T_2 & ~_T_1320) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is corrupt (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1572 & (io_in_b_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2 & ~_T_1572) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~address_ok & (io_in_b_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2 & ~address_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Probe carries unmanaged address (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_1 & (io_in_b_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2 & ~is_aligned_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Probe address not aligned to size (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1588 & (io_in_b_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2 & ~_T_1588) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Probe carries invalid cap param (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~address_ok_1 & (io_in_c_valid & _T_2341 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2341 & ~reset & ~address_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_2 & (io_in_c_valid & _T_2341 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2341 & ~reset & ~source_ok_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2348 & (io_in_c_valid & _T_2341 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2341 & ~reset & ~_T_2348) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_2341 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2341 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2355 & (io_in_c_valid & _T_2341 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2341 & ~reset & ~_T_2355) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2359 & (io_in_c_valid & _T_2341 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2341 & ~reset & ~_T_2359) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck is corrupt (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~address_ok_1 & (io_in_c_valid & _T_2363 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2363 & ~reset & ~address_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_2 & (io_in_c_valid & _T_2363 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2363 & ~reset & ~source_ok_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2348 & (io_in_c_valid & _T_2363 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2363 & ~reset & ~_T_2348) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_2363 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2363 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2355 & (io_in_c_valid & _T_2363 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2363 & ~reset & ~_T_2355) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2489 & (io_in_c_valid & _T_2381 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2381 & ~reset & ~_T_2489) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2597 & (io_in_c_valid & _T_2381 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2381 & ~reset & ~_T_2597) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_2 & (io_in_c_valid & _T_2381 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2381 & ~reset & ~source_ok_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release carries invalid source ID (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2348 & (io_in_c_valid & _T_2381 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2381 & ~reset & ~_T_2348) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release smaller than a beat (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_2381 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2381 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release address not aligned to size (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2355 & (io_in_c_valid & _T_2381 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2381 & ~reset & ~_T_2355) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release carries invalid report param (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2359 & (io_in_c_valid & _T_2381 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2381 & ~reset & ~_T_2359) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release is corrupt (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2489 & (io_in_c_valid & _T_2619 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2619 & ~reset & ~_T_2489) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2597 & (io_in_c_valid & _T_2619 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2619 & ~reset & ~_T_2597) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_2 & (io_in_c_valid & _T_2619 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2619 & ~reset & ~source_ok_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2348 & (io_in_c_valid & _T_2619 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2619 & ~reset & ~_T_2348) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_2619 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2619 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2355 & (io_in_c_valid & _T_2619 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2619 & ~reset & ~_T_2355) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~address_ok_1 & (io_in_c_valid & _T_2853 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2853 & ~reset & ~address_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_2 & (io_in_c_valid & _T_2853 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2853 & ~reset & ~source_ok_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_2853 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2853 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2863 & (io_in_c_valid & _T_2853 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2853 & ~reset & ~_T_2863) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck carries invalid param (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2359 & (io_in_c_valid & _T_2853 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2853 & ~reset & ~_T_2359) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck is corrupt (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~address_ok_1 & (io_in_c_valid & _T_2871 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2871 & ~reset & ~address_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_2 & (io_in_c_valid & _T_2871 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2871 & ~reset & ~source_ok_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_2871 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2871 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2863 & (io_in_c_valid & _T_2871 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2871 & ~reset & ~_T_2863) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~address_ok_1 & (io_in_c_valid & _T_2885 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2885 & ~reset & ~address_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_2 & (io_in_c_valid & _T_2885 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2885 & ~reset & ~source_ok_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_2885 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2885 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck address not aligned to size (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2863 & (io_in_c_valid & _T_2885 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2885 & ~reset & ~_T_2863) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck carries invalid param (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2359 & (io_in_c_valid & _T_2885 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2885 & ~reset & ~_T_2359) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck is corrupt (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2908 & (_T_2907 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2907 & ~reset & ~_T_2908) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2912 & (_T_2907 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2907 & ~reset & ~_T_2912) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2916 & (_T_2907 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2907 & ~reset & ~_T_2916) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2920 & (_T_2907 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2907 & ~reset & ~_T_2920) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2924 & (_T_2907 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2907 & ~reset & ~_T_2924) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2932 & (_T_2931 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2931 & _T_2 & ~_T_2932) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2936 & (_T_2931 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2931 & _T_2 & ~_T_2936) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel param changed within multibeat operation (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2940 & (_T_2931 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2931 & _T_2 & ~_T_2940) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2944 & (_T_2931 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2931 & _T_2 & ~_T_2944) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2948 & (_T_2931 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2931 & _T_2 & ~_T_2948) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel sink changed with multibeat operation (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2952 & (_T_2931 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2931 & _T_2 & ~_T_2952) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel denied changed with multibeat operation (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2964 & (_T_2959 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2959 & ~reset & ~_T_2964) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel param changed within multibeat operation (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2976 & (_T_2959 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2959 & ~reset & ~_T_2976) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2984 & (_T_2983 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2983 & ~reset & ~_T_2984) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2988 & (_T_2983 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2983 & ~reset & ~_T_2988) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel param changed within multibeat operation (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2992 & (_T_2983 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2983 & ~reset & ~_T_2992) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel size changed within multibeat operation (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2996 & (_T_2983 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2983 & ~reset & ~_T_2996) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel source changed within multibeat operation (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3000 & (_T_2983 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2983 & ~reset & ~_T_3000) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel address changed with multibeat operation (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3013 & (_T_3009 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3009 & ~reset & ~_T_3013) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3032 & (_T_3020 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3020 & _T_2 & ~_T_3032) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3038 & (_T_3020 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3020 & same_cycle_resp & _T_2 & ~_T_3038) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3042 & (_T_3020 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3020 & same_cycle_resp & _T_2 & ~_T_3042) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3050 & (_T_3020 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3020 & ~same_cycle_resp & _T_2 & ~_T_3050) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3054 & (_T_3020 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3020 & ~same_cycle_resp & _T_2 & ~_T_3054) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3066 & (_T_3064 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3064 & _T_2 & ~_T_3066) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3073 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_3073) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3082 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_3082) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3102 & (_T_3099 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3099 & ~reset & ~_T_3102) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel re-used a source ID (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3118 & (_T_3108 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3108 & _T_2 & ~_T_3118) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3122 & (_T_3108 & same_cycle_resp_1 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3108 & same_cycle_resp_1 & _T_2 & ~_T_3122) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3126 & (_T_3108 & ~same_cycle_resp_1 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3108 & ~same_cycle_resp_1 & _T_2 & ~_T_3126) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3137 & (_T_3135 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3135 & _T_2 & ~_T_3137) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3142 & (_T_3141 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3141 & _T_2 & ~_T_3142) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' and 'D' concurrent, despite minlatency 1 (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3151 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_3151) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3167 & (_T_3164 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3164 & _T_2 & ~_T_3167) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel re-used a sink ID (connected at SystemBus.scala:41:96)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3175[0] & (io_in_e_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_e_valid & ~reset & ~_T_3175[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at SystemBus.scala:41:96)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[9:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[30:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[9:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  param_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  size_1 = _RAND_9[3:0];
  _RAND_10 = {1{`RANDOM}};
  source_1 = _RAND_10[1:0];
  _RAND_11 = {1{`RANDOM}};
  sink = _RAND_11[1:0];
  _RAND_12 = {1{`RANDOM}};
  denied = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  b_first_counter = _RAND_13[9:0];
  _RAND_14 = {1{`RANDOM}};
  param_2 = _RAND_14[1:0];
  _RAND_15 = {1{`RANDOM}};
  address_1 = _RAND_15[30:0];
  _RAND_16 = {1{`RANDOM}};
  c_first_counter = _RAND_16[9:0];
  _RAND_17 = {1{`RANDOM}};
  opcode_3 = _RAND_17[2:0];
  _RAND_18 = {1{`RANDOM}};
  param_3 = _RAND_18[2:0];
  _RAND_19 = {1{`RANDOM}};
  size_3 = _RAND_19[3:0];
  _RAND_20 = {1{`RANDOM}};
  source_3 = _RAND_20[1:0];
  _RAND_21 = {1{`RANDOM}};
  address_2 = _RAND_21[30:0];
  _RAND_22 = {1{`RANDOM}};
  inflight = _RAND_22[2:0];
  _RAND_23 = {1{`RANDOM}};
  inflight_opcodes = _RAND_23[11:0];
  _RAND_24 = {1{`RANDOM}};
  inflight_sizes = _RAND_24[23:0];
  _RAND_25 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_25[9:0];
  _RAND_26 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_26[9:0];
  _RAND_27 = {1{`RANDOM}};
  watchdog = _RAND_27[31:0];
  _RAND_28 = {1{`RANDOM}};
  inflight_1 = _RAND_28[2:0];
  _RAND_29 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_29[23:0];
  _RAND_30 = {1{`RANDOM}};
  c_first_counter_1 = _RAND_30[9:0];
  _RAND_31 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_31[9:0];
  _RAND_32 = {1{`RANDOM}};
  watchdog_1 = _RAND_32[31:0];
  _RAND_33 = {1{`RANDOM}};
  inflight_2 = _RAND_33[3:0];
  _RAND_34 = {1{`RANDOM}};
  d_first_counter_3 = _RAND_34[9:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLFIFOFixer(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [3:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [30:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_b_ready,
  output        auto_in_b_valid,
  output [1:0]  auto_in_b_bits_param,
  output [30:0] auto_in_b_bits_address,
  output        auto_in_c_ready,
  input         auto_in_c_valid,
  input  [2:0]  auto_in_c_bits_opcode,
  input  [2:0]  auto_in_c_bits_param,
  input  [3:0]  auto_in_c_bits_size,
  input  [1:0]  auto_in_c_bits_source,
  input  [30:0] auto_in_c_bits_address,
  input  [31:0] auto_in_c_bits_data,
  input         auto_in_c_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [1:0]  auto_in_d_bits_param,
  output [3:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output [1:0]  auto_in_d_bits_sink,
  output        auto_in_d_bits_denied,
  output [31:0] auto_in_d_bits_data,
  output        auto_in_d_bits_corrupt,
  input         auto_in_e_valid,
  input  [1:0]  auto_in_e_bits_sink,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [3:0]  auto_out_a_bits_size,
  output [1:0]  auto_out_a_bits_source,
  output [30:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_b_ready,
  input         auto_out_b_valid,
  input  [1:0]  auto_out_b_bits_param,
  input  [30:0] auto_out_b_bits_address,
  input         auto_out_c_ready,
  output        auto_out_c_valid,
  output [2:0]  auto_out_c_bits_opcode,
  output [2:0]  auto_out_c_bits_param,
  output [3:0]  auto_out_c_bits_size,
  output [1:0]  auto_out_c_bits_source,
  output [30:0] auto_out_c_bits_address,
  output [31:0] auto_out_c_bits_data,
  output        auto_out_c_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_param,
  input  [3:0]  auto_out_d_bits_size,
  input  [1:0]  auto_out_d_bits_source,
  input  [1:0]  auto_out_d_bits_sink,
  input         auto_out_d_bits_denied,
  input  [31:0] auto_out_d_bits_data,
  input         auto_out_d_bits_corrupt,
  output        auto_out_e_valid,
  output [1:0]  auto_out_e_bits_sink
);
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [30:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_b_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_b_valid; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_b_bits_param; // @[Nodes.scala 24:25]
  wire [30:0] monitor_io_in_b_bits_address; // @[Nodes.scala 24:25]
  wire  monitor_io_in_c_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_c_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_c_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_c_bits_param; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_c_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_c_bits_source; // @[Nodes.scala 24:25]
  wire [30:0] monitor_io_in_c_bits_address; // @[Nodes.scala 24:25]
  wire  monitor_io_in_c_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_e_valid; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_e_bits_sink; // @[Nodes.scala 24:25]
  TLMonitor_1 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_b_ready(monitor_io_in_b_ready),
    .io_in_b_valid(monitor_io_in_b_valid),
    .io_in_b_bits_param(monitor_io_in_b_bits_param),
    .io_in_b_bits_address(monitor_io_in_b_bits_address),
    .io_in_c_ready(monitor_io_in_c_ready),
    .io_in_c_valid(monitor_io_in_c_valid),
    .io_in_c_bits_opcode(monitor_io_in_c_bits_opcode),
    .io_in_c_bits_param(monitor_io_in_c_bits_param),
    .io_in_c_bits_size(monitor_io_in_c_bits_size),
    .io_in_c_bits_source(monitor_io_in_c_bits_source),
    .io_in_c_bits_address(monitor_io_in_c_bits_address),
    .io_in_c_bits_corrupt(monitor_io_in_c_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_param(monitor_io_in_d_bits_param),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source),
    .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
    .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
    .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt),
    .io_in_e_valid(monitor_io_in_e_valid),
    .io_in_e_bits_sink(monitor_io_in_e_bits_sink)
  );
  assign auto_in_a_ready = auto_out_a_ready; // @[FIFOFixer.scala 88:33]
  assign auto_in_b_valid = auto_out_b_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_b_bits_param = auto_out_b_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_b_bits_address = auto_out_b_bits_address; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_c_ready = auto_out_c_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = auto_in_a_valid; // @[FIFOFixer.scala 87:33]
  assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_b_ready = auto_in_b_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_valid = auto_in_c_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_bits_opcode = auto_in_c_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_bits_param = auto_in_c_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_bits_size = auto_in_c_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_bits_source = auto_in_c_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_bits_address = auto_in_c_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_bits_data = auto_in_c_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_bits_corrupt = auto_in_c_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_e_valid = auto_in_e_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_e_bits_sink = auto_in_e_bits_sink; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = auto_out_a_ready; // @[FIFOFixer.scala 88:33]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_b_ready = auto_in_b_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_b_valid = auto_out_b_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_b_bits_param = auto_out_b_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_b_bits_address = auto_out_b_bits_address; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_c_ready = auto_out_c_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_c_valid = auto_in_c_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_opcode = auto_in_c_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_param = auto_in_c_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_size = auto_in_c_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_source = auto_in_c_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_address = auto_in_c_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_corrupt = auto_in_c_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_e_valid = auto_in_e_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_e_bits_sink = auto_in_e_bits_sink; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module TLWidthWidget(
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [3:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [29:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [1:0]  auto_in_d_bits_param,
  output [3:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output        auto_in_d_bits_sink,
  output        auto_in_d_bits_denied,
  output [31:0] auto_in_d_bits_data,
  output        auto_in_d_bits_corrupt,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [3:0]  auto_out_a_bits_size,
  output [1:0]  auto_out_a_bits_source,
  output [29:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_param,
  input  [3:0]  auto_out_d_bits_size,
  input  [1:0]  auto_out_d_bits_source,
  input         auto_out_d_bits_sink,
  input         auto_out_d_bits_denied,
  input  [31:0] auto_out_d_bits_data,
  input         auto_out_d_bits_corrupt
);
  assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module TLInterconnectCoupler(
  output        auto_widget_in_a_ready,
  input         auto_widget_in_a_valid,
  input  [2:0]  auto_widget_in_a_bits_opcode,
  input  [2:0]  auto_widget_in_a_bits_param,
  input  [3:0]  auto_widget_in_a_bits_size,
  input  [1:0]  auto_widget_in_a_bits_source,
  input  [29:0] auto_widget_in_a_bits_address,
  input  [3:0]  auto_widget_in_a_bits_mask,
  input  [31:0] auto_widget_in_a_bits_data,
  input         auto_widget_in_a_bits_corrupt,
  input         auto_widget_in_d_ready,
  output        auto_widget_in_d_valid,
  output [2:0]  auto_widget_in_d_bits_opcode,
  output [1:0]  auto_widget_in_d_bits_param,
  output [3:0]  auto_widget_in_d_bits_size,
  output [1:0]  auto_widget_in_d_bits_source,
  output        auto_widget_in_d_bits_sink,
  output        auto_widget_in_d_bits_denied,
  output [31:0] auto_widget_in_d_bits_data,
  output        auto_widget_in_d_bits_corrupt,
  input         auto_bus_xing_out_a_ready,
  output        auto_bus_xing_out_a_valid,
  output [2:0]  auto_bus_xing_out_a_bits_opcode,
  output [2:0]  auto_bus_xing_out_a_bits_param,
  output [3:0]  auto_bus_xing_out_a_bits_size,
  output [1:0]  auto_bus_xing_out_a_bits_source,
  output [29:0] auto_bus_xing_out_a_bits_address,
  output [3:0]  auto_bus_xing_out_a_bits_mask,
  output [31:0] auto_bus_xing_out_a_bits_data,
  output        auto_bus_xing_out_a_bits_corrupt,
  output        auto_bus_xing_out_d_ready,
  input         auto_bus_xing_out_d_valid,
  input  [2:0]  auto_bus_xing_out_d_bits_opcode,
  input  [1:0]  auto_bus_xing_out_d_bits_param,
  input  [3:0]  auto_bus_xing_out_d_bits_size,
  input  [1:0]  auto_bus_xing_out_d_bits_source,
  input         auto_bus_xing_out_d_bits_sink,
  input         auto_bus_xing_out_d_bits_denied,
  input  [31:0] auto_bus_xing_out_d_bits_data,
  input         auto_bus_xing_out_d_bits_corrupt
);
  wire  widget_auto_in_a_ready; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_a_valid; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_a_bits_opcode; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_a_bits_param; // @[WidthWidget.scala 219:28]
  wire [3:0] widget_auto_in_a_bits_size; // @[WidthWidget.scala 219:28]
  wire [1:0] widget_auto_in_a_bits_source; // @[WidthWidget.scala 219:28]
  wire [29:0] widget_auto_in_a_bits_address; // @[WidthWidget.scala 219:28]
  wire [3:0] widget_auto_in_a_bits_mask; // @[WidthWidget.scala 219:28]
  wire [31:0] widget_auto_in_a_bits_data; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_a_bits_corrupt; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_d_ready; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_d_valid; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_d_bits_opcode; // @[WidthWidget.scala 219:28]
  wire [1:0] widget_auto_in_d_bits_param; // @[WidthWidget.scala 219:28]
  wire [3:0] widget_auto_in_d_bits_size; // @[WidthWidget.scala 219:28]
  wire [1:0] widget_auto_in_d_bits_source; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_d_bits_sink; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_d_bits_denied; // @[WidthWidget.scala 219:28]
  wire [31:0] widget_auto_in_d_bits_data; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_d_bits_corrupt; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_a_ready; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_a_valid; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_a_bits_opcode; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_a_bits_param; // @[WidthWidget.scala 219:28]
  wire [3:0] widget_auto_out_a_bits_size; // @[WidthWidget.scala 219:28]
  wire [1:0] widget_auto_out_a_bits_source; // @[WidthWidget.scala 219:28]
  wire [29:0] widget_auto_out_a_bits_address; // @[WidthWidget.scala 219:28]
  wire [3:0] widget_auto_out_a_bits_mask; // @[WidthWidget.scala 219:28]
  wire [31:0] widget_auto_out_a_bits_data; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_a_bits_corrupt; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_d_ready; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_d_valid; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_d_bits_opcode; // @[WidthWidget.scala 219:28]
  wire [1:0] widget_auto_out_d_bits_param; // @[WidthWidget.scala 219:28]
  wire [3:0] widget_auto_out_d_bits_size; // @[WidthWidget.scala 219:28]
  wire [1:0] widget_auto_out_d_bits_source; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_d_bits_sink; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_d_bits_denied; // @[WidthWidget.scala 219:28]
  wire [31:0] widget_auto_out_d_bits_data; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_d_bits_corrupt; // @[WidthWidget.scala 219:28]
  TLWidthWidget widget ( // @[WidthWidget.scala 219:28]
    .auto_in_a_ready(widget_auto_in_a_ready),
    .auto_in_a_valid(widget_auto_in_a_valid),
    .auto_in_a_bits_opcode(widget_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(widget_auto_in_a_bits_param),
    .auto_in_a_bits_size(widget_auto_in_a_bits_size),
    .auto_in_a_bits_source(widget_auto_in_a_bits_source),
    .auto_in_a_bits_address(widget_auto_in_a_bits_address),
    .auto_in_a_bits_mask(widget_auto_in_a_bits_mask),
    .auto_in_a_bits_data(widget_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(widget_auto_in_a_bits_corrupt),
    .auto_in_d_ready(widget_auto_in_d_ready),
    .auto_in_d_valid(widget_auto_in_d_valid),
    .auto_in_d_bits_opcode(widget_auto_in_d_bits_opcode),
    .auto_in_d_bits_param(widget_auto_in_d_bits_param),
    .auto_in_d_bits_size(widget_auto_in_d_bits_size),
    .auto_in_d_bits_source(widget_auto_in_d_bits_source),
    .auto_in_d_bits_sink(widget_auto_in_d_bits_sink),
    .auto_in_d_bits_denied(widget_auto_in_d_bits_denied),
    .auto_in_d_bits_data(widget_auto_in_d_bits_data),
    .auto_in_d_bits_corrupt(widget_auto_in_d_bits_corrupt),
    .auto_out_a_ready(widget_auto_out_a_ready),
    .auto_out_a_valid(widget_auto_out_a_valid),
    .auto_out_a_bits_opcode(widget_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(widget_auto_out_a_bits_param),
    .auto_out_a_bits_size(widget_auto_out_a_bits_size),
    .auto_out_a_bits_source(widget_auto_out_a_bits_source),
    .auto_out_a_bits_address(widget_auto_out_a_bits_address),
    .auto_out_a_bits_mask(widget_auto_out_a_bits_mask),
    .auto_out_a_bits_data(widget_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(widget_auto_out_a_bits_corrupt),
    .auto_out_d_ready(widget_auto_out_d_ready),
    .auto_out_d_valid(widget_auto_out_d_valid),
    .auto_out_d_bits_opcode(widget_auto_out_d_bits_opcode),
    .auto_out_d_bits_param(widget_auto_out_d_bits_param),
    .auto_out_d_bits_size(widget_auto_out_d_bits_size),
    .auto_out_d_bits_source(widget_auto_out_d_bits_source),
    .auto_out_d_bits_sink(widget_auto_out_d_bits_sink),
    .auto_out_d_bits_denied(widget_auto_out_d_bits_denied),
    .auto_out_d_bits_data(widget_auto_out_d_bits_data),
    .auto_out_d_bits_corrupt(widget_auto_out_d_bits_corrupt)
  );
  assign auto_widget_in_a_ready = widget_auto_in_a_ready; // @[LazyModule.scala 309:16]
  assign auto_widget_in_d_valid = widget_auto_in_d_valid; // @[LazyModule.scala 309:16]
  assign auto_widget_in_d_bits_opcode = widget_auto_in_d_bits_opcode; // @[LazyModule.scala 309:16]
  assign auto_widget_in_d_bits_param = widget_auto_in_d_bits_param; // @[LazyModule.scala 309:16]
  assign auto_widget_in_d_bits_size = widget_auto_in_d_bits_size; // @[LazyModule.scala 309:16]
  assign auto_widget_in_d_bits_source = widget_auto_in_d_bits_source; // @[LazyModule.scala 309:16]
  assign auto_widget_in_d_bits_sink = widget_auto_in_d_bits_sink; // @[LazyModule.scala 309:16]
  assign auto_widget_in_d_bits_denied = widget_auto_in_d_bits_denied; // @[LazyModule.scala 309:16]
  assign auto_widget_in_d_bits_data = widget_auto_in_d_bits_data; // @[LazyModule.scala 309:16]
  assign auto_widget_in_d_bits_corrupt = widget_auto_in_d_bits_corrupt; // @[LazyModule.scala 309:16]
  assign auto_bus_xing_out_a_valid = widget_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_bus_xing_out_a_bits_opcode = widget_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_bus_xing_out_a_bits_param = widget_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_bus_xing_out_a_bits_size = widget_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_bus_xing_out_a_bits_source = widget_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_bus_xing_out_a_bits_address = widget_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_bus_xing_out_a_bits_mask = widget_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_bus_xing_out_a_bits_data = widget_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_bus_xing_out_a_bits_corrupt = widget_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_bus_xing_out_d_ready = widget_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign widget_auto_in_a_valid = auto_widget_in_a_valid; // @[LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_opcode = auto_widget_in_a_bits_opcode; // @[LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_param = auto_widget_in_a_bits_param; // @[LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_size = auto_widget_in_a_bits_size; // @[LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_source = auto_widget_in_a_bits_source; // @[LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_address = auto_widget_in_a_bits_address; // @[LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_mask = auto_widget_in_a_bits_mask; // @[LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_data = auto_widget_in_a_bits_data; // @[LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_corrupt = auto_widget_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
  assign widget_auto_in_d_ready = auto_widget_in_d_ready; // @[LazyModule.scala 309:16]
  assign widget_auto_out_a_ready = auto_bus_xing_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign widget_auto_out_d_valid = auto_bus_xing_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign widget_auto_out_d_bits_opcode = auto_bus_xing_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign widget_auto_out_d_bits_param = auto_bus_xing_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign widget_auto_out_d_bits_size = auto_bus_xing_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign widget_auto_out_d_bits_source = auto_bus_xing_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign widget_auto_out_d_bits_sink = auto_bus_xing_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign widget_auto_out_d_bits_denied = auto_bus_xing_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign widget_auto_out_d_bits_data = auto_bus_xing_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign widget_auto_out_d_bits_corrupt = auto_bus_xing_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
endmodule
module TLWidthWidget_2(
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [30:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_b_ready,
  output        auto_in_b_valid,
  output [1:0]  auto_in_b_bits_param,
  output [30:0] auto_in_b_bits_address,
  output        auto_in_c_ready,
  input         auto_in_c_valid,
  input  [2:0]  auto_in_c_bits_opcode,
  input  [2:0]  auto_in_c_bits_param,
  input  [2:0]  auto_in_c_bits_size,
  input  [1:0]  auto_in_c_bits_source,
  input  [30:0] auto_in_c_bits_address,
  input  [31:0] auto_in_c_bits_data,
  input         auto_in_c_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [1:0]  auto_in_d_bits_param,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output [1:0]  auto_in_d_bits_sink,
  output [31:0] auto_in_d_bits_data,
  input         auto_in_e_valid,
  input  [1:0]  auto_in_e_bits_sink,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [2:0]  auto_out_a_bits_size,
  output [1:0]  auto_out_a_bits_source,
  output [30:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_b_ready,
  input         auto_out_b_valid,
  input  [1:0]  auto_out_b_bits_param,
  input  [30:0] auto_out_b_bits_address,
  input         auto_out_c_ready,
  output        auto_out_c_valid,
  output [2:0]  auto_out_c_bits_opcode,
  output [2:0]  auto_out_c_bits_param,
  output [2:0]  auto_out_c_bits_size,
  output [1:0]  auto_out_c_bits_source,
  output [30:0] auto_out_c_bits_address,
  output [31:0] auto_out_c_bits_data,
  output        auto_out_c_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_param,
  input  [2:0]  auto_out_d_bits_size,
  input  [1:0]  auto_out_d_bits_source,
  input  [1:0]  auto_out_d_bits_sink,
  input  [31:0] auto_out_d_bits_data,
  output        auto_out_e_valid,
  output [1:0]  auto_out_e_bits_sink
);
  assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_b_valid = auto_out_b_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_b_bits_param = auto_out_b_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_b_bits_address = auto_out_b_bits_address; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_c_ready = auto_out_c_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_b_ready = auto_in_b_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_valid = auto_in_c_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_bits_opcode = auto_in_c_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_bits_param = auto_in_c_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_bits_size = auto_in_c_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_bits_source = auto_in_c_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_bits_address = auto_in_c_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_bits_data = auto_in_c_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_bits_corrupt = auto_in_c_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_e_valid = auto_in_e_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_e_bits_sink = auto_in_e_bits_sink; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module TLInterconnectCoupler_2(
  output        auto_widget_in_a_ready,
  input         auto_widget_in_a_valid,
  input  [2:0]  auto_widget_in_a_bits_opcode,
  input  [2:0]  auto_widget_in_a_bits_param,
  input  [2:0]  auto_widget_in_a_bits_size,
  input  [1:0]  auto_widget_in_a_bits_source,
  input  [30:0] auto_widget_in_a_bits_address,
  input  [3:0]  auto_widget_in_a_bits_mask,
  input  [31:0] auto_widget_in_a_bits_data,
  input         auto_widget_in_a_bits_corrupt,
  input         auto_widget_in_b_ready,
  output        auto_widget_in_b_valid,
  output [1:0]  auto_widget_in_b_bits_param,
  output [30:0] auto_widget_in_b_bits_address,
  output        auto_widget_in_c_ready,
  input         auto_widget_in_c_valid,
  input  [2:0]  auto_widget_in_c_bits_opcode,
  input  [2:0]  auto_widget_in_c_bits_param,
  input  [2:0]  auto_widget_in_c_bits_size,
  input  [1:0]  auto_widget_in_c_bits_source,
  input  [30:0] auto_widget_in_c_bits_address,
  input  [31:0] auto_widget_in_c_bits_data,
  input         auto_widget_in_c_bits_corrupt,
  input         auto_widget_in_d_ready,
  output        auto_widget_in_d_valid,
  output [2:0]  auto_widget_in_d_bits_opcode,
  output [1:0]  auto_widget_in_d_bits_param,
  output [2:0]  auto_widget_in_d_bits_size,
  output [1:0]  auto_widget_in_d_bits_source,
  output [1:0]  auto_widget_in_d_bits_sink,
  output [31:0] auto_widget_in_d_bits_data,
  input         auto_widget_in_e_valid,
  input  [1:0]  auto_widget_in_e_bits_sink,
  input         auto_widget_out_a_ready,
  output        auto_widget_out_a_valid,
  output [2:0]  auto_widget_out_a_bits_opcode,
  output [2:0]  auto_widget_out_a_bits_param,
  output [2:0]  auto_widget_out_a_bits_size,
  output [1:0]  auto_widget_out_a_bits_source,
  output [30:0] auto_widget_out_a_bits_address,
  output [3:0]  auto_widget_out_a_bits_mask,
  output [31:0] auto_widget_out_a_bits_data,
  output        auto_widget_out_a_bits_corrupt,
  output        auto_widget_out_b_ready,
  input         auto_widget_out_b_valid,
  input  [1:0]  auto_widget_out_b_bits_param,
  input  [30:0] auto_widget_out_b_bits_address,
  input         auto_widget_out_c_ready,
  output        auto_widget_out_c_valid,
  output [2:0]  auto_widget_out_c_bits_opcode,
  output [2:0]  auto_widget_out_c_bits_param,
  output [2:0]  auto_widget_out_c_bits_size,
  output [1:0]  auto_widget_out_c_bits_source,
  output [30:0] auto_widget_out_c_bits_address,
  output [31:0] auto_widget_out_c_bits_data,
  output        auto_widget_out_c_bits_corrupt,
  output        auto_widget_out_d_ready,
  input         auto_widget_out_d_valid,
  input  [2:0]  auto_widget_out_d_bits_opcode,
  input  [1:0]  auto_widget_out_d_bits_param,
  input  [2:0]  auto_widget_out_d_bits_size,
  input  [1:0]  auto_widget_out_d_bits_source,
  input  [1:0]  auto_widget_out_d_bits_sink,
  input  [31:0] auto_widget_out_d_bits_data,
  output        auto_widget_out_e_valid,
  output [1:0]  auto_widget_out_e_bits_sink
);
  wire  widget_auto_in_a_ready; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_a_valid; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_a_bits_opcode; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_a_bits_param; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_a_bits_size; // @[WidthWidget.scala 219:28]
  wire [1:0] widget_auto_in_a_bits_source; // @[WidthWidget.scala 219:28]
  wire [30:0] widget_auto_in_a_bits_address; // @[WidthWidget.scala 219:28]
  wire [3:0] widget_auto_in_a_bits_mask; // @[WidthWidget.scala 219:28]
  wire [31:0] widget_auto_in_a_bits_data; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_a_bits_corrupt; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_b_ready; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_b_valid; // @[WidthWidget.scala 219:28]
  wire [1:0] widget_auto_in_b_bits_param; // @[WidthWidget.scala 219:28]
  wire [30:0] widget_auto_in_b_bits_address; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_c_ready; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_c_valid; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_c_bits_opcode; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_c_bits_param; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_c_bits_size; // @[WidthWidget.scala 219:28]
  wire [1:0] widget_auto_in_c_bits_source; // @[WidthWidget.scala 219:28]
  wire [30:0] widget_auto_in_c_bits_address; // @[WidthWidget.scala 219:28]
  wire [31:0] widget_auto_in_c_bits_data; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_c_bits_corrupt; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_d_ready; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_d_valid; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_d_bits_opcode; // @[WidthWidget.scala 219:28]
  wire [1:0] widget_auto_in_d_bits_param; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_d_bits_size; // @[WidthWidget.scala 219:28]
  wire [1:0] widget_auto_in_d_bits_source; // @[WidthWidget.scala 219:28]
  wire [1:0] widget_auto_in_d_bits_sink; // @[WidthWidget.scala 219:28]
  wire [31:0] widget_auto_in_d_bits_data; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_e_valid; // @[WidthWidget.scala 219:28]
  wire [1:0] widget_auto_in_e_bits_sink; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_a_ready; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_a_valid; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_a_bits_opcode; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_a_bits_param; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_a_bits_size; // @[WidthWidget.scala 219:28]
  wire [1:0] widget_auto_out_a_bits_source; // @[WidthWidget.scala 219:28]
  wire [30:0] widget_auto_out_a_bits_address; // @[WidthWidget.scala 219:28]
  wire [3:0] widget_auto_out_a_bits_mask; // @[WidthWidget.scala 219:28]
  wire [31:0] widget_auto_out_a_bits_data; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_a_bits_corrupt; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_b_ready; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_b_valid; // @[WidthWidget.scala 219:28]
  wire [1:0] widget_auto_out_b_bits_param; // @[WidthWidget.scala 219:28]
  wire [30:0] widget_auto_out_b_bits_address; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_c_ready; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_c_valid; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_c_bits_opcode; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_c_bits_param; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_c_bits_size; // @[WidthWidget.scala 219:28]
  wire [1:0] widget_auto_out_c_bits_source; // @[WidthWidget.scala 219:28]
  wire [30:0] widget_auto_out_c_bits_address; // @[WidthWidget.scala 219:28]
  wire [31:0] widget_auto_out_c_bits_data; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_c_bits_corrupt; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_d_ready; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_d_valid; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_d_bits_opcode; // @[WidthWidget.scala 219:28]
  wire [1:0] widget_auto_out_d_bits_param; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_d_bits_size; // @[WidthWidget.scala 219:28]
  wire [1:0] widget_auto_out_d_bits_source; // @[WidthWidget.scala 219:28]
  wire [1:0] widget_auto_out_d_bits_sink; // @[WidthWidget.scala 219:28]
  wire [31:0] widget_auto_out_d_bits_data; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_e_valid; // @[WidthWidget.scala 219:28]
  wire [1:0] widget_auto_out_e_bits_sink; // @[WidthWidget.scala 219:28]
  TLWidthWidget_2 widget ( // @[WidthWidget.scala 219:28]
    .auto_in_a_ready(widget_auto_in_a_ready),
    .auto_in_a_valid(widget_auto_in_a_valid),
    .auto_in_a_bits_opcode(widget_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(widget_auto_in_a_bits_param),
    .auto_in_a_bits_size(widget_auto_in_a_bits_size),
    .auto_in_a_bits_source(widget_auto_in_a_bits_source),
    .auto_in_a_bits_address(widget_auto_in_a_bits_address),
    .auto_in_a_bits_mask(widget_auto_in_a_bits_mask),
    .auto_in_a_bits_data(widget_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(widget_auto_in_a_bits_corrupt),
    .auto_in_b_ready(widget_auto_in_b_ready),
    .auto_in_b_valid(widget_auto_in_b_valid),
    .auto_in_b_bits_param(widget_auto_in_b_bits_param),
    .auto_in_b_bits_address(widget_auto_in_b_bits_address),
    .auto_in_c_ready(widget_auto_in_c_ready),
    .auto_in_c_valid(widget_auto_in_c_valid),
    .auto_in_c_bits_opcode(widget_auto_in_c_bits_opcode),
    .auto_in_c_bits_param(widget_auto_in_c_bits_param),
    .auto_in_c_bits_size(widget_auto_in_c_bits_size),
    .auto_in_c_bits_source(widget_auto_in_c_bits_source),
    .auto_in_c_bits_address(widget_auto_in_c_bits_address),
    .auto_in_c_bits_data(widget_auto_in_c_bits_data),
    .auto_in_c_bits_corrupt(widget_auto_in_c_bits_corrupt),
    .auto_in_d_ready(widget_auto_in_d_ready),
    .auto_in_d_valid(widget_auto_in_d_valid),
    .auto_in_d_bits_opcode(widget_auto_in_d_bits_opcode),
    .auto_in_d_bits_param(widget_auto_in_d_bits_param),
    .auto_in_d_bits_size(widget_auto_in_d_bits_size),
    .auto_in_d_bits_source(widget_auto_in_d_bits_source),
    .auto_in_d_bits_sink(widget_auto_in_d_bits_sink),
    .auto_in_d_bits_data(widget_auto_in_d_bits_data),
    .auto_in_e_valid(widget_auto_in_e_valid),
    .auto_in_e_bits_sink(widget_auto_in_e_bits_sink),
    .auto_out_a_ready(widget_auto_out_a_ready),
    .auto_out_a_valid(widget_auto_out_a_valid),
    .auto_out_a_bits_opcode(widget_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(widget_auto_out_a_bits_param),
    .auto_out_a_bits_size(widget_auto_out_a_bits_size),
    .auto_out_a_bits_source(widget_auto_out_a_bits_source),
    .auto_out_a_bits_address(widget_auto_out_a_bits_address),
    .auto_out_a_bits_mask(widget_auto_out_a_bits_mask),
    .auto_out_a_bits_data(widget_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(widget_auto_out_a_bits_corrupt),
    .auto_out_b_ready(widget_auto_out_b_ready),
    .auto_out_b_valid(widget_auto_out_b_valid),
    .auto_out_b_bits_param(widget_auto_out_b_bits_param),
    .auto_out_b_bits_address(widget_auto_out_b_bits_address),
    .auto_out_c_ready(widget_auto_out_c_ready),
    .auto_out_c_valid(widget_auto_out_c_valid),
    .auto_out_c_bits_opcode(widget_auto_out_c_bits_opcode),
    .auto_out_c_bits_param(widget_auto_out_c_bits_param),
    .auto_out_c_bits_size(widget_auto_out_c_bits_size),
    .auto_out_c_bits_source(widget_auto_out_c_bits_source),
    .auto_out_c_bits_address(widget_auto_out_c_bits_address),
    .auto_out_c_bits_data(widget_auto_out_c_bits_data),
    .auto_out_c_bits_corrupt(widget_auto_out_c_bits_corrupt),
    .auto_out_d_ready(widget_auto_out_d_ready),
    .auto_out_d_valid(widget_auto_out_d_valid),
    .auto_out_d_bits_opcode(widget_auto_out_d_bits_opcode),
    .auto_out_d_bits_param(widget_auto_out_d_bits_param),
    .auto_out_d_bits_size(widget_auto_out_d_bits_size),
    .auto_out_d_bits_source(widget_auto_out_d_bits_source),
    .auto_out_d_bits_sink(widget_auto_out_d_bits_sink),
    .auto_out_d_bits_data(widget_auto_out_d_bits_data),
    .auto_out_e_valid(widget_auto_out_e_valid),
    .auto_out_e_bits_sink(widget_auto_out_e_bits_sink)
  );
  assign auto_widget_in_a_ready = widget_auto_in_a_ready; // @[LazyModule.scala 309:16]
  assign auto_widget_in_b_valid = widget_auto_in_b_valid; // @[LazyModule.scala 309:16]
  assign auto_widget_in_b_bits_param = widget_auto_in_b_bits_param; // @[LazyModule.scala 309:16]
  assign auto_widget_in_b_bits_address = widget_auto_in_b_bits_address; // @[LazyModule.scala 309:16]
  assign auto_widget_in_c_ready = widget_auto_in_c_ready; // @[LazyModule.scala 309:16]
  assign auto_widget_in_d_valid = widget_auto_in_d_valid; // @[LazyModule.scala 309:16]
  assign auto_widget_in_d_bits_opcode = widget_auto_in_d_bits_opcode; // @[LazyModule.scala 309:16]
  assign auto_widget_in_d_bits_param = widget_auto_in_d_bits_param; // @[LazyModule.scala 309:16]
  assign auto_widget_in_d_bits_size = widget_auto_in_d_bits_size; // @[LazyModule.scala 309:16]
  assign auto_widget_in_d_bits_source = widget_auto_in_d_bits_source; // @[LazyModule.scala 309:16]
  assign auto_widget_in_d_bits_sink = widget_auto_in_d_bits_sink; // @[LazyModule.scala 309:16]
  assign auto_widget_in_d_bits_data = widget_auto_in_d_bits_data; // @[LazyModule.scala 309:16]
  assign auto_widget_out_a_valid = widget_auto_out_a_valid; // @[LazyModule.scala 311:12]
  assign auto_widget_out_a_bits_opcode = widget_auto_out_a_bits_opcode; // @[LazyModule.scala 311:12]
  assign auto_widget_out_a_bits_param = widget_auto_out_a_bits_param; // @[LazyModule.scala 311:12]
  assign auto_widget_out_a_bits_size = widget_auto_out_a_bits_size; // @[LazyModule.scala 311:12]
  assign auto_widget_out_a_bits_source = widget_auto_out_a_bits_source; // @[LazyModule.scala 311:12]
  assign auto_widget_out_a_bits_address = widget_auto_out_a_bits_address; // @[LazyModule.scala 311:12]
  assign auto_widget_out_a_bits_mask = widget_auto_out_a_bits_mask; // @[LazyModule.scala 311:12]
  assign auto_widget_out_a_bits_data = widget_auto_out_a_bits_data; // @[LazyModule.scala 311:12]
  assign auto_widget_out_a_bits_corrupt = widget_auto_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
  assign auto_widget_out_b_ready = widget_auto_out_b_ready; // @[LazyModule.scala 311:12]
  assign auto_widget_out_c_valid = widget_auto_out_c_valid; // @[LazyModule.scala 311:12]
  assign auto_widget_out_c_bits_opcode = widget_auto_out_c_bits_opcode; // @[LazyModule.scala 311:12]
  assign auto_widget_out_c_bits_param = widget_auto_out_c_bits_param; // @[LazyModule.scala 311:12]
  assign auto_widget_out_c_bits_size = widget_auto_out_c_bits_size; // @[LazyModule.scala 311:12]
  assign auto_widget_out_c_bits_source = widget_auto_out_c_bits_source; // @[LazyModule.scala 311:12]
  assign auto_widget_out_c_bits_address = widget_auto_out_c_bits_address; // @[LazyModule.scala 311:12]
  assign auto_widget_out_c_bits_data = widget_auto_out_c_bits_data; // @[LazyModule.scala 311:12]
  assign auto_widget_out_c_bits_corrupt = widget_auto_out_c_bits_corrupt; // @[LazyModule.scala 311:12]
  assign auto_widget_out_d_ready = widget_auto_out_d_ready; // @[LazyModule.scala 311:12]
  assign auto_widget_out_e_valid = widget_auto_out_e_valid; // @[LazyModule.scala 311:12]
  assign auto_widget_out_e_bits_sink = widget_auto_out_e_bits_sink; // @[LazyModule.scala 311:12]
  assign widget_auto_in_a_valid = auto_widget_in_a_valid; // @[LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_opcode = auto_widget_in_a_bits_opcode; // @[LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_param = auto_widget_in_a_bits_param; // @[LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_size = auto_widget_in_a_bits_size; // @[LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_source = auto_widget_in_a_bits_source; // @[LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_address = auto_widget_in_a_bits_address; // @[LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_mask = auto_widget_in_a_bits_mask; // @[LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_data = auto_widget_in_a_bits_data; // @[LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_corrupt = auto_widget_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
  assign widget_auto_in_b_ready = auto_widget_in_b_ready; // @[LazyModule.scala 309:16]
  assign widget_auto_in_c_valid = auto_widget_in_c_valid; // @[LazyModule.scala 309:16]
  assign widget_auto_in_c_bits_opcode = auto_widget_in_c_bits_opcode; // @[LazyModule.scala 309:16]
  assign widget_auto_in_c_bits_param = auto_widget_in_c_bits_param; // @[LazyModule.scala 309:16]
  assign widget_auto_in_c_bits_size = auto_widget_in_c_bits_size; // @[LazyModule.scala 309:16]
  assign widget_auto_in_c_bits_source = auto_widget_in_c_bits_source; // @[LazyModule.scala 309:16]
  assign widget_auto_in_c_bits_address = auto_widget_in_c_bits_address; // @[LazyModule.scala 309:16]
  assign widget_auto_in_c_bits_data = auto_widget_in_c_bits_data; // @[LazyModule.scala 309:16]
  assign widget_auto_in_c_bits_corrupt = auto_widget_in_c_bits_corrupt; // @[LazyModule.scala 309:16]
  assign widget_auto_in_d_ready = auto_widget_in_d_ready; // @[LazyModule.scala 309:16]
  assign widget_auto_in_e_valid = auto_widget_in_e_valid; // @[LazyModule.scala 309:16]
  assign widget_auto_in_e_bits_sink = auto_widget_in_e_bits_sink; // @[LazyModule.scala 309:16]
  assign widget_auto_out_a_ready = auto_widget_out_a_ready; // @[LazyModule.scala 311:12]
  assign widget_auto_out_b_valid = auto_widget_out_b_valid; // @[LazyModule.scala 311:12]
  assign widget_auto_out_b_bits_param = auto_widget_out_b_bits_param; // @[LazyModule.scala 311:12]
  assign widget_auto_out_b_bits_address = auto_widget_out_b_bits_address; // @[LazyModule.scala 311:12]
  assign widget_auto_out_c_ready = auto_widget_out_c_ready; // @[LazyModule.scala 311:12]
  assign widget_auto_out_d_valid = auto_widget_out_d_valid; // @[LazyModule.scala 311:12]
  assign widget_auto_out_d_bits_opcode = auto_widget_out_d_bits_opcode; // @[LazyModule.scala 311:12]
  assign widget_auto_out_d_bits_param = auto_widget_out_d_bits_param; // @[LazyModule.scala 311:12]
  assign widget_auto_out_d_bits_size = auto_widget_out_d_bits_size; // @[LazyModule.scala 311:12]
  assign widget_auto_out_d_bits_source = auto_widget_out_d_bits_source; // @[LazyModule.scala 311:12]
  assign widget_auto_out_d_bits_sink = auto_widget_out_d_bits_sink; // @[LazyModule.scala 311:12]
  assign widget_auto_out_d_bits_data = auto_widget_out_d_bits_data; // @[LazyModule.scala 311:12]
endmodule
module TLInterconnectCoupler_3(
  output        auto_tl_master_clock_xing_in_a_ready,
  input         auto_tl_master_clock_xing_in_a_valid,
  input  [2:0]  auto_tl_master_clock_xing_in_a_bits_opcode,
  input  [2:0]  auto_tl_master_clock_xing_in_a_bits_param,
  input  [3:0]  auto_tl_master_clock_xing_in_a_bits_size,
  input  [1:0]  auto_tl_master_clock_xing_in_a_bits_source,
  input  [30:0] auto_tl_master_clock_xing_in_a_bits_address,
  input  [3:0]  auto_tl_master_clock_xing_in_a_bits_mask,
  input  [31:0] auto_tl_master_clock_xing_in_a_bits_data,
  input         auto_tl_master_clock_xing_in_a_bits_corrupt,
  input         auto_tl_master_clock_xing_in_b_ready,
  output        auto_tl_master_clock_xing_in_b_valid,
  output [1:0]  auto_tl_master_clock_xing_in_b_bits_param,
  output [30:0] auto_tl_master_clock_xing_in_b_bits_address,
  output        auto_tl_master_clock_xing_in_c_ready,
  input         auto_tl_master_clock_xing_in_c_valid,
  input  [2:0]  auto_tl_master_clock_xing_in_c_bits_opcode,
  input  [2:0]  auto_tl_master_clock_xing_in_c_bits_param,
  input  [3:0]  auto_tl_master_clock_xing_in_c_bits_size,
  input  [1:0]  auto_tl_master_clock_xing_in_c_bits_source,
  input  [30:0] auto_tl_master_clock_xing_in_c_bits_address,
  input  [31:0] auto_tl_master_clock_xing_in_c_bits_data,
  input         auto_tl_master_clock_xing_in_c_bits_corrupt,
  input         auto_tl_master_clock_xing_in_d_ready,
  output        auto_tl_master_clock_xing_in_d_valid,
  output [2:0]  auto_tl_master_clock_xing_in_d_bits_opcode,
  output [1:0]  auto_tl_master_clock_xing_in_d_bits_param,
  output [3:0]  auto_tl_master_clock_xing_in_d_bits_size,
  output [1:0]  auto_tl_master_clock_xing_in_d_bits_source,
  output [1:0]  auto_tl_master_clock_xing_in_d_bits_sink,
  output        auto_tl_master_clock_xing_in_d_bits_denied,
  output [31:0] auto_tl_master_clock_xing_in_d_bits_data,
  output        auto_tl_master_clock_xing_in_d_bits_corrupt,
  input         auto_tl_master_clock_xing_in_e_valid,
  input  [1:0]  auto_tl_master_clock_xing_in_e_bits_sink,
  input         auto_tl_out_a_ready,
  output        auto_tl_out_a_valid,
  output [2:0]  auto_tl_out_a_bits_opcode,
  output [2:0]  auto_tl_out_a_bits_param,
  output [3:0]  auto_tl_out_a_bits_size,
  output [1:0]  auto_tl_out_a_bits_source,
  output [30:0] auto_tl_out_a_bits_address,
  output [3:0]  auto_tl_out_a_bits_mask,
  output [31:0] auto_tl_out_a_bits_data,
  output        auto_tl_out_a_bits_corrupt,
  output        auto_tl_out_b_ready,
  input         auto_tl_out_b_valid,
  input  [1:0]  auto_tl_out_b_bits_param,
  input  [30:0] auto_tl_out_b_bits_address,
  input         auto_tl_out_c_ready,
  output        auto_tl_out_c_valid,
  output [2:0]  auto_tl_out_c_bits_opcode,
  output [2:0]  auto_tl_out_c_bits_param,
  output [3:0]  auto_tl_out_c_bits_size,
  output [1:0]  auto_tl_out_c_bits_source,
  output [30:0] auto_tl_out_c_bits_address,
  output [31:0] auto_tl_out_c_bits_data,
  output        auto_tl_out_c_bits_corrupt,
  output        auto_tl_out_d_ready,
  input         auto_tl_out_d_valid,
  input  [2:0]  auto_tl_out_d_bits_opcode,
  input  [1:0]  auto_tl_out_d_bits_param,
  input  [3:0]  auto_tl_out_d_bits_size,
  input  [1:0]  auto_tl_out_d_bits_source,
  input  [1:0]  auto_tl_out_d_bits_sink,
  input         auto_tl_out_d_bits_denied,
  input  [31:0] auto_tl_out_d_bits_data,
  input         auto_tl_out_d_bits_corrupt,
  output        auto_tl_out_e_valid,
  output [1:0]  auto_tl_out_e_bits_sink
);
  assign auto_tl_master_clock_xing_in_a_ready = auto_tl_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_tl_master_clock_xing_in_b_valid = auto_tl_out_b_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_tl_master_clock_xing_in_b_bits_param = auto_tl_out_b_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_tl_master_clock_xing_in_b_bits_address = auto_tl_out_b_bits_address; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_tl_master_clock_xing_in_c_ready = auto_tl_out_c_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_tl_master_clock_xing_in_d_valid = auto_tl_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_tl_master_clock_xing_in_d_bits_opcode = auto_tl_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_tl_master_clock_xing_in_d_bits_param = auto_tl_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_tl_master_clock_xing_in_d_bits_size = auto_tl_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_tl_master_clock_xing_in_d_bits_source = auto_tl_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_tl_master_clock_xing_in_d_bits_sink = auto_tl_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_tl_master_clock_xing_in_d_bits_denied = auto_tl_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_tl_master_clock_xing_in_d_bits_data = auto_tl_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_tl_master_clock_xing_in_d_bits_corrupt = auto_tl_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_tl_out_a_valid = auto_tl_master_clock_xing_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_tl_out_a_bits_opcode = auto_tl_master_clock_xing_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_tl_out_a_bits_param = auto_tl_master_clock_xing_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_tl_out_a_bits_size = auto_tl_master_clock_xing_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_tl_out_a_bits_source = auto_tl_master_clock_xing_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_tl_out_a_bits_address = auto_tl_master_clock_xing_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_tl_out_a_bits_mask = auto_tl_master_clock_xing_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_tl_out_a_bits_data = auto_tl_master_clock_xing_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_tl_out_a_bits_corrupt = auto_tl_master_clock_xing_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_tl_out_b_ready = auto_tl_master_clock_xing_in_b_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_tl_out_c_valid = auto_tl_master_clock_xing_in_c_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_tl_out_c_bits_opcode = auto_tl_master_clock_xing_in_c_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_tl_out_c_bits_param = auto_tl_master_clock_xing_in_c_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_tl_out_c_bits_size = auto_tl_master_clock_xing_in_c_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_tl_out_c_bits_source = auto_tl_master_clock_xing_in_c_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_tl_out_c_bits_address = auto_tl_master_clock_xing_in_c_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_tl_out_c_bits_data = auto_tl_master_clock_xing_in_c_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_tl_out_c_bits_corrupt = auto_tl_master_clock_xing_in_c_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_tl_out_d_ready = auto_tl_master_clock_xing_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_tl_out_e_valid = auto_tl_master_clock_xing_in_e_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_tl_out_e_bits_sink = auto_tl_master_clock_xing_in_e_bits_sink; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module SystemBus(
  output        auto_coupler_from_tile_tl_master_clock_xing_in_a_ready,
  input         auto_coupler_from_tile_tl_master_clock_xing_in_a_valid,
  input  [2:0]  auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_opcode,
  input  [2:0]  auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_param,
  input  [3:0]  auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_size,
  input  [1:0]  auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_source,
  input  [30:0] auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_address,
  input  [3:0]  auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_mask,
  input  [31:0] auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_data,
  input         auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_corrupt,
  input         auto_coupler_from_tile_tl_master_clock_xing_in_b_ready,
  output        auto_coupler_from_tile_tl_master_clock_xing_in_b_valid,
  output [1:0]  auto_coupler_from_tile_tl_master_clock_xing_in_b_bits_param,
  output [30:0] auto_coupler_from_tile_tl_master_clock_xing_in_b_bits_address,
  output        auto_coupler_from_tile_tl_master_clock_xing_in_c_ready,
  input         auto_coupler_from_tile_tl_master_clock_xing_in_c_valid,
  input  [2:0]  auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_opcode,
  input  [2:0]  auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_param,
  input  [3:0]  auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_size,
  input  [1:0]  auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_source,
  input  [30:0] auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_address,
  input  [31:0] auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_data,
  input         auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_corrupt,
  input         auto_coupler_from_tile_tl_master_clock_xing_in_d_ready,
  output        auto_coupler_from_tile_tl_master_clock_xing_in_d_valid,
  output [2:0]  auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_opcode,
  output [1:0]  auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_param,
  output [3:0]  auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_size,
  output [1:0]  auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_source,
  output [1:0]  auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_sink,
  output        auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_denied,
  output [31:0] auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_data,
  output        auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_corrupt,
  input         auto_coupler_from_tile_tl_master_clock_xing_in_e_valid,
  input  [1:0]  auto_coupler_from_tile_tl_master_clock_xing_in_e_bits_sink,
  input         auto_coupler_to_bus_named_subsystem_l2_widget_out_a_ready,
  output        auto_coupler_to_bus_named_subsystem_l2_widget_out_a_valid,
  output [2:0]  auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_opcode,
  output [2:0]  auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_param,
  output [2:0]  auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_size,
  output [1:0]  auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_source,
  output [30:0] auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_address,
  output [3:0]  auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_mask,
  output [31:0] auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_data,
  output        auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_corrupt,
  output        auto_coupler_to_bus_named_subsystem_l2_widget_out_b_ready,
  input         auto_coupler_to_bus_named_subsystem_l2_widget_out_b_valid,
  input  [1:0]  auto_coupler_to_bus_named_subsystem_l2_widget_out_b_bits_param,
  input  [30:0] auto_coupler_to_bus_named_subsystem_l2_widget_out_b_bits_address,
  input         auto_coupler_to_bus_named_subsystem_l2_widget_out_c_ready,
  output        auto_coupler_to_bus_named_subsystem_l2_widget_out_c_valid,
  output [2:0]  auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_opcode,
  output [2:0]  auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_param,
  output [2:0]  auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_size,
  output [1:0]  auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_source,
  output [30:0] auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_address,
  output [31:0] auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_data,
  output        auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_corrupt,
  output        auto_coupler_to_bus_named_subsystem_l2_widget_out_d_ready,
  input         auto_coupler_to_bus_named_subsystem_l2_widget_out_d_valid,
  input  [2:0]  auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_opcode,
  input  [1:0]  auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_param,
  input  [2:0]  auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_size,
  input  [1:0]  auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_source,
  input  [1:0]  auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_sink,
  input  [31:0] auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_data,
  output        auto_coupler_to_bus_named_subsystem_l2_widget_out_e_valid,
  output [1:0]  auto_coupler_to_bus_named_subsystem_l2_widget_out_e_bits_sink,
  input         auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_ready,
  output        auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_valid,
  output [2:0]  auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_opcode,
  output [2:0]  auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_param,
  output [3:0]  auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_size,
  output [1:0]  auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_source,
  output [29:0] auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_address,
  output [3:0]  auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_mask,
  output [31:0] auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_data,
  output        auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_corrupt,
  output        auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_ready,
  input         auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_valid,
  input  [2:0]  auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_opcode,
  input  [1:0]  auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_param,
  input  [3:0]  auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_size,
  input  [1:0]  auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_source,
  input         auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_sink,
  input         auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_denied,
  input  [31:0] auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_data,
  input         auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_corrupt,
  output        auto_fixedClockNode_out_1_clock,
  output        auto_fixedClockNode_out_1_reset,
  input         auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_5_clock,
  input         auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_5_reset,
  input         auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_4_clock,
  input         auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_4_reset,
  input         auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_3_clock,
  input         auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_3_reset,
  input         auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_2_clock,
  input         auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_2_reset,
  input         auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_1_clock,
  input         auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_1_reset,
  input         auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_0_clock,
  input         auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_0_reset,
  output        auto_subsystem_sbus_clock_groups_out_2_member_subsystem_l2_1_clock,
  output        auto_subsystem_sbus_clock_groups_out_2_member_subsystem_l2_1_reset,
  output        auto_subsystem_sbus_clock_groups_out_2_member_subsystem_l2_0_clock,
  output        auto_subsystem_sbus_clock_groups_out_2_member_subsystem_l2_0_reset,
  output        auto_subsystem_sbus_clock_groups_out_1_member_subsystem_fbus_0_clock,
  output        auto_subsystem_sbus_clock_groups_out_1_member_subsystem_fbus_0_reset,
  output        auto_subsystem_sbus_clock_groups_out_0_member_subsystem_cbus_1_clock,
  output        auto_subsystem_sbus_clock_groups_out_0_member_subsystem_cbus_1_reset,
  output        auto_subsystem_sbus_clock_groups_out_0_member_subsystem_cbus_0_clock,
  output        auto_subsystem_sbus_clock_groups_out_0_member_subsystem_cbus_0_reset
);
  wire  subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_5_clock; // @[BusWrapper.scala 40:48]
  wire  subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_5_reset; // @[BusWrapper.scala 40:48]
  wire  subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_4_clock; // @[BusWrapper.scala 40:48]
  wire  subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_4_reset; // @[BusWrapper.scala 40:48]
  wire  subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_3_clock; // @[BusWrapper.scala 40:48]
  wire  subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_3_reset; // @[BusWrapper.scala 40:48]
  wire  subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_2_clock; // @[BusWrapper.scala 40:48]
  wire  subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_2_reset; // @[BusWrapper.scala 40:48]
  wire  subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_1_clock; // @[BusWrapper.scala 40:48]
  wire  subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_1_reset; // @[BusWrapper.scala 40:48]
  wire  subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_0_clock; // @[BusWrapper.scala 40:48]
  wire  subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_0_reset; // @[BusWrapper.scala 40:48]
  wire  subsystem_sbus_clock_groups_auto_out_3_member_subsystem_l2_1_clock; // @[BusWrapper.scala 40:48]
  wire  subsystem_sbus_clock_groups_auto_out_3_member_subsystem_l2_1_reset; // @[BusWrapper.scala 40:48]
  wire  subsystem_sbus_clock_groups_auto_out_3_member_subsystem_l2_0_clock; // @[BusWrapper.scala 40:48]
  wire  subsystem_sbus_clock_groups_auto_out_3_member_subsystem_l2_0_reset; // @[BusWrapper.scala 40:48]
  wire  subsystem_sbus_clock_groups_auto_out_2_member_subsystem_fbus_0_clock; // @[BusWrapper.scala 40:48]
  wire  subsystem_sbus_clock_groups_auto_out_2_member_subsystem_fbus_0_reset; // @[BusWrapper.scala 40:48]
  wire  subsystem_sbus_clock_groups_auto_out_1_member_subsystem_cbus_1_clock; // @[BusWrapper.scala 40:48]
  wire  subsystem_sbus_clock_groups_auto_out_1_member_subsystem_cbus_1_reset; // @[BusWrapper.scala 40:48]
  wire  subsystem_sbus_clock_groups_auto_out_1_member_subsystem_cbus_0_clock; // @[BusWrapper.scala 40:48]
  wire  subsystem_sbus_clock_groups_auto_out_1_member_subsystem_cbus_0_reset; // @[BusWrapper.scala 40:48]
  wire  subsystem_sbus_clock_groups_auto_out_0_member_subsystem_sbus_0_clock; // @[BusWrapper.scala 40:48]
  wire  subsystem_sbus_clock_groups_auto_out_0_member_subsystem_sbus_0_reset; // @[BusWrapper.scala 40:48]
  wire  clockGroup_auto_in_member_subsystem_sbus_0_clock; // @[BusWrapper.scala 41:38]
  wire  clockGroup_auto_in_member_subsystem_sbus_0_reset; // @[BusWrapper.scala 41:38]
  wire  clockGroup_auto_out_clock; // @[BusWrapper.scala 41:38]
  wire  clockGroup_auto_out_reset; // @[BusWrapper.scala 41:38]
  wire  fixedClockNode_auto_in_clock; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_in_reset; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_2_clock; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_2_reset; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_0_clock; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_0_reset; // @[ClockGroup.scala 106:107]
  wire  system_bus_xbar_clock; // @[SystemBus.scala 40:43]
  wire  system_bus_xbar_reset; // @[SystemBus.scala 40:43]
  wire  system_bus_xbar_auto_in_a_ready; // @[SystemBus.scala 40:43]
  wire  system_bus_xbar_auto_in_a_valid; // @[SystemBus.scala 40:43]
  wire [2:0] system_bus_xbar_auto_in_a_bits_opcode; // @[SystemBus.scala 40:43]
  wire [2:0] system_bus_xbar_auto_in_a_bits_param; // @[SystemBus.scala 40:43]
  wire [3:0] system_bus_xbar_auto_in_a_bits_size; // @[SystemBus.scala 40:43]
  wire [1:0] system_bus_xbar_auto_in_a_bits_source; // @[SystemBus.scala 40:43]
  wire [30:0] system_bus_xbar_auto_in_a_bits_address; // @[SystemBus.scala 40:43]
  wire [3:0] system_bus_xbar_auto_in_a_bits_mask; // @[SystemBus.scala 40:43]
  wire [31:0] system_bus_xbar_auto_in_a_bits_data; // @[SystemBus.scala 40:43]
  wire  system_bus_xbar_auto_in_a_bits_corrupt; // @[SystemBus.scala 40:43]
  wire  system_bus_xbar_auto_in_b_ready; // @[SystemBus.scala 40:43]
  wire  system_bus_xbar_auto_in_b_valid; // @[SystemBus.scala 40:43]
  wire [1:0] system_bus_xbar_auto_in_b_bits_param; // @[SystemBus.scala 40:43]
  wire [30:0] system_bus_xbar_auto_in_b_bits_address; // @[SystemBus.scala 40:43]
  wire  system_bus_xbar_auto_in_c_ready; // @[SystemBus.scala 40:43]
  wire  system_bus_xbar_auto_in_c_valid; // @[SystemBus.scala 40:43]
  wire [2:0] system_bus_xbar_auto_in_c_bits_opcode; // @[SystemBus.scala 40:43]
  wire [2:0] system_bus_xbar_auto_in_c_bits_param; // @[SystemBus.scala 40:43]
  wire [3:0] system_bus_xbar_auto_in_c_bits_size; // @[SystemBus.scala 40:43]
  wire [1:0] system_bus_xbar_auto_in_c_bits_source; // @[SystemBus.scala 40:43]
  wire [30:0] system_bus_xbar_auto_in_c_bits_address; // @[SystemBus.scala 40:43]
  wire [31:0] system_bus_xbar_auto_in_c_bits_data; // @[SystemBus.scala 40:43]
  wire  system_bus_xbar_auto_in_c_bits_corrupt; // @[SystemBus.scala 40:43]
  wire  system_bus_xbar_auto_in_d_ready; // @[SystemBus.scala 40:43]
  wire  system_bus_xbar_auto_in_d_valid; // @[SystemBus.scala 40:43]
  wire [2:0] system_bus_xbar_auto_in_d_bits_opcode; // @[SystemBus.scala 40:43]
  wire [1:0] system_bus_xbar_auto_in_d_bits_param; // @[SystemBus.scala 40:43]
  wire [3:0] system_bus_xbar_auto_in_d_bits_size; // @[SystemBus.scala 40:43]
  wire [1:0] system_bus_xbar_auto_in_d_bits_source; // @[SystemBus.scala 40:43]
  wire [1:0] system_bus_xbar_auto_in_d_bits_sink; // @[SystemBus.scala 40:43]
  wire  system_bus_xbar_auto_in_d_bits_denied; // @[SystemBus.scala 40:43]
  wire [31:0] system_bus_xbar_auto_in_d_bits_data; // @[SystemBus.scala 40:43]
  wire  system_bus_xbar_auto_in_d_bits_corrupt; // @[SystemBus.scala 40:43]
  wire  system_bus_xbar_auto_in_e_valid; // @[SystemBus.scala 40:43]
  wire [1:0] system_bus_xbar_auto_in_e_bits_sink; // @[SystemBus.scala 40:43]
  wire  system_bus_xbar_auto_out_1_a_ready; // @[SystemBus.scala 40:43]
  wire  system_bus_xbar_auto_out_1_a_valid; // @[SystemBus.scala 40:43]
  wire [2:0] system_bus_xbar_auto_out_1_a_bits_opcode; // @[SystemBus.scala 40:43]
  wire [2:0] system_bus_xbar_auto_out_1_a_bits_param; // @[SystemBus.scala 40:43]
  wire [2:0] system_bus_xbar_auto_out_1_a_bits_size; // @[SystemBus.scala 40:43]
  wire [1:0] system_bus_xbar_auto_out_1_a_bits_source; // @[SystemBus.scala 40:43]
  wire [30:0] system_bus_xbar_auto_out_1_a_bits_address; // @[SystemBus.scala 40:43]
  wire [3:0] system_bus_xbar_auto_out_1_a_bits_mask; // @[SystemBus.scala 40:43]
  wire [31:0] system_bus_xbar_auto_out_1_a_bits_data; // @[SystemBus.scala 40:43]
  wire  system_bus_xbar_auto_out_1_a_bits_corrupt; // @[SystemBus.scala 40:43]
  wire  system_bus_xbar_auto_out_1_b_ready; // @[SystemBus.scala 40:43]
  wire  system_bus_xbar_auto_out_1_b_valid; // @[SystemBus.scala 40:43]
  wire [1:0] system_bus_xbar_auto_out_1_b_bits_param; // @[SystemBus.scala 40:43]
  wire [30:0] system_bus_xbar_auto_out_1_b_bits_address; // @[SystemBus.scala 40:43]
  wire  system_bus_xbar_auto_out_1_c_ready; // @[SystemBus.scala 40:43]
  wire  system_bus_xbar_auto_out_1_c_valid; // @[SystemBus.scala 40:43]
  wire [2:0] system_bus_xbar_auto_out_1_c_bits_opcode; // @[SystemBus.scala 40:43]
  wire [2:0] system_bus_xbar_auto_out_1_c_bits_param; // @[SystemBus.scala 40:43]
  wire [2:0] system_bus_xbar_auto_out_1_c_bits_size; // @[SystemBus.scala 40:43]
  wire [1:0] system_bus_xbar_auto_out_1_c_bits_source; // @[SystemBus.scala 40:43]
  wire [30:0] system_bus_xbar_auto_out_1_c_bits_address; // @[SystemBus.scala 40:43]
  wire [31:0] system_bus_xbar_auto_out_1_c_bits_data; // @[SystemBus.scala 40:43]
  wire  system_bus_xbar_auto_out_1_c_bits_corrupt; // @[SystemBus.scala 40:43]
  wire  system_bus_xbar_auto_out_1_d_ready; // @[SystemBus.scala 40:43]
  wire  system_bus_xbar_auto_out_1_d_valid; // @[SystemBus.scala 40:43]
  wire [2:0] system_bus_xbar_auto_out_1_d_bits_opcode; // @[SystemBus.scala 40:43]
  wire [1:0] system_bus_xbar_auto_out_1_d_bits_param; // @[SystemBus.scala 40:43]
  wire [2:0] system_bus_xbar_auto_out_1_d_bits_size; // @[SystemBus.scala 40:43]
  wire [1:0] system_bus_xbar_auto_out_1_d_bits_source; // @[SystemBus.scala 40:43]
  wire [1:0] system_bus_xbar_auto_out_1_d_bits_sink; // @[SystemBus.scala 40:43]
  wire [31:0] system_bus_xbar_auto_out_1_d_bits_data; // @[SystemBus.scala 40:43]
  wire  system_bus_xbar_auto_out_1_e_valid; // @[SystemBus.scala 40:43]
  wire [1:0] system_bus_xbar_auto_out_1_e_bits_sink; // @[SystemBus.scala 40:43]
  wire  system_bus_xbar_auto_out_0_a_ready; // @[SystemBus.scala 40:43]
  wire  system_bus_xbar_auto_out_0_a_valid; // @[SystemBus.scala 40:43]
  wire [2:0] system_bus_xbar_auto_out_0_a_bits_opcode; // @[SystemBus.scala 40:43]
  wire [2:0] system_bus_xbar_auto_out_0_a_bits_param; // @[SystemBus.scala 40:43]
  wire [3:0] system_bus_xbar_auto_out_0_a_bits_size; // @[SystemBus.scala 40:43]
  wire [1:0] system_bus_xbar_auto_out_0_a_bits_source; // @[SystemBus.scala 40:43]
  wire [29:0] system_bus_xbar_auto_out_0_a_bits_address; // @[SystemBus.scala 40:43]
  wire [3:0] system_bus_xbar_auto_out_0_a_bits_mask; // @[SystemBus.scala 40:43]
  wire [31:0] system_bus_xbar_auto_out_0_a_bits_data; // @[SystemBus.scala 40:43]
  wire  system_bus_xbar_auto_out_0_a_bits_corrupt; // @[SystemBus.scala 40:43]
  wire  system_bus_xbar_auto_out_0_d_ready; // @[SystemBus.scala 40:43]
  wire  system_bus_xbar_auto_out_0_d_valid; // @[SystemBus.scala 40:43]
  wire [2:0] system_bus_xbar_auto_out_0_d_bits_opcode; // @[SystemBus.scala 40:43]
  wire [1:0] system_bus_xbar_auto_out_0_d_bits_param; // @[SystemBus.scala 40:43]
  wire [3:0] system_bus_xbar_auto_out_0_d_bits_size; // @[SystemBus.scala 40:43]
  wire [1:0] system_bus_xbar_auto_out_0_d_bits_source; // @[SystemBus.scala 40:43]
  wire  system_bus_xbar_auto_out_0_d_bits_sink; // @[SystemBus.scala 40:43]
  wire  system_bus_xbar_auto_out_0_d_bits_denied; // @[SystemBus.scala 40:43]
  wire [31:0] system_bus_xbar_auto_out_0_d_bits_data; // @[SystemBus.scala 40:43]
  wire  system_bus_xbar_auto_out_0_d_bits_corrupt; // @[SystemBus.scala 40:43]
  wire  fixer_clock; // @[FIFOFixer.scala 144:27]
  wire  fixer_reset; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_in_a_ready; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_in_a_valid; // @[FIFOFixer.scala 144:27]
  wire [2:0] fixer_auto_in_a_bits_opcode; // @[FIFOFixer.scala 144:27]
  wire [2:0] fixer_auto_in_a_bits_param; // @[FIFOFixer.scala 144:27]
  wire [3:0] fixer_auto_in_a_bits_size; // @[FIFOFixer.scala 144:27]
  wire [1:0] fixer_auto_in_a_bits_source; // @[FIFOFixer.scala 144:27]
  wire [30:0] fixer_auto_in_a_bits_address; // @[FIFOFixer.scala 144:27]
  wire [3:0] fixer_auto_in_a_bits_mask; // @[FIFOFixer.scala 144:27]
  wire [31:0] fixer_auto_in_a_bits_data; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_in_a_bits_corrupt; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_in_b_ready; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_in_b_valid; // @[FIFOFixer.scala 144:27]
  wire [1:0] fixer_auto_in_b_bits_param; // @[FIFOFixer.scala 144:27]
  wire [30:0] fixer_auto_in_b_bits_address; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_in_c_ready; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_in_c_valid; // @[FIFOFixer.scala 144:27]
  wire [2:0] fixer_auto_in_c_bits_opcode; // @[FIFOFixer.scala 144:27]
  wire [2:0] fixer_auto_in_c_bits_param; // @[FIFOFixer.scala 144:27]
  wire [3:0] fixer_auto_in_c_bits_size; // @[FIFOFixer.scala 144:27]
  wire [1:0] fixer_auto_in_c_bits_source; // @[FIFOFixer.scala 144:27]
  wire [30:0] fixer_auto_in_c_bits_address; // @[FIFOFixer.scala 144:27]
  wire [31:0] fixer_auto_in_c_bits_data; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_in_c_bits_corrupt; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_in_d_ready; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_in_d_valid; // @[FIFOFixer.scala 144:27]
  wire [2:0] fixer_auto_in_d_bits_opcode; // @[FIFOFixer.scala 144:27]
  wire [1:0] fixer_auto_in_d_bits_param; // @[FIFOFixer.scala 144:27]
  wire [3:0] fixer_auto_in_d_bits_size; // @[FIFOFixer.scala 144:27]
  wire [1:0] fixer_auto_in_d_bits_source; // @[FIFOFixer.scala 144:27]
  wire [1:0] fixer_auto_in_d_bits_sink; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_in_d_bits_denied; // @[FIFOFixer.scala 144:27]
  wire [31:0] fixer_auto_in_d_bits_data; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_in_d_bits_corrupt; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_in_e_valid; // @[FIFOFixer.scala 144:27]
  wire [1:0] fixer_auto_in_e_bits_sink; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_out_a_ready; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_out_a_valid; // @[FIFOFixer.scala 144:27]
  wire [2:0] fixer_auto_out_a_bits_opcode; // @[FIFOFixer.scala 144:27]
  wire [2:0] fixer_auto_out_a_bits_param; // @[FIFOFixer.scala 144:27]
  wire [3:0] fixer_auto_out_a_bits_size; // @[FIFOFixer.scala 144:27]
  wire [1:0] fixer_auto_out_a_bits_source; // @[FIFOFixer.scala 144:27]
  wire [30:0] fixer_auto_out_a_bits_address; // @[FIFOFixer.scala 144:27]
  wire [3:0] fixer_auto_out_a_bits_mask; // @[FIFOFixer.scala 144:27]
  wire [31:0] fixer_auto_out_a_bits_data; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_out_a_bits_corrupt; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_out_b_ready; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_out_b_valid; // @[FIFOFixer.scala 144:27]
  wire [1:0] fixer_auto_out_b_bits_param; // @[FIFOFixer.scala 144:27]
  wire [30:0] fixer_auto_out_b_bits_address; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_out_c_ready; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_out_c_valid; // @[FIFOFixer.scala 144:27]
  wire [2:0] fixer_auto_out_c_bits_opcode; // @[FIFOFixer.scala 144:27]
  wire [2:0] fixer_auto_out_c_bits_param; // @[FIFOFixer.scala 144:27]
  wire [3:0] fixer_auto_out_c_bits_size; // @[FIFOFixer.scala 144:27]
  wire [1:0] fixer_auto_out_c_bits_source; // @[FIFOFixer.scala 144:27]
  wire [30:0] fixer_auto_out_c_bits_address; // @[FIFOFixer.scala 144:27]
  wire [31:0] fixer_auto_out_c_bits_data; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_out_c_bits_corrupt; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_out_d_ready; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_out_d_valid; // @[FIFOFixer.scala 144:27]
  wire [2:0] fixer_auto_out_d_bits_opcode; // @[FIFOFixer.scala 144:27]
  wire [1:0] fixer_auto_out_d_bits_param; // @[FIFOFixer.scala 144:27]
  wire [3:0] fixer_auto_out_d_bits_size; // @[FIFOFixer.scala 144:27]
  wire [1:0] fixer_auto_out_d_bits_source; // @[FIFOFixer.scala 144:27]
  wire [1:0] fixer_auto_out_d_bits_sink; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_out_d_bits_denied; // @[FIFOFixer.scala 144:27]
  wire [31:0] fixer_auto_out_d_bits_data; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_out_d_bits_corrupt; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_out_e_valid; // @[FIFOFixer.scala 144:27]
  wire [1:0] fixer_auto_out_e_bits_sink; // @[FIFOFixer.scala 144:27]
  wire  coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_param; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_source; // @[LazyModule.scala 432:27]
  wire [29:0] coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_param; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_source; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_sink; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_denied; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_param; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_source; // @[LazyModule.scala 432:27]
  wire [29:0] coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_param; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_source; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_sink; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_denied; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_l2_auto_widget_in_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_l2_auto_widget_in_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_l2_auto_widget_in_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_l2_auto_widget_in_a_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_l2_auto_widget_in_a_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_bus_named_subsystem_l2_auto_widget_in_a_bits_source; // @[LazyModule.scala 432:27]
  wire [30:0] coupler_to_bus_named_subsystem_l2_auto_widget_in_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_bus_named_subsystem_l2_auto_widget_in_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_bus_named_subsystem_l2_auto_widget_in_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_l2_auto_widget_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_l2_auto_widget_in_b_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_l2_auto_widget_in_b_valid; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_bus_named_subsystem_l2_auto_widget_in_b_bits_param; // @[LazyModule.scala 432:27]
  wire [30:0] coupler_to_bus_named_subsystem_l2_auto_widget_in_b_bits_address; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_l2_auto_widget_in_c_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_l2_auto_widget_in_c_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_l2_auto_widget_in_c_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_l2_auto_widget_in_c_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_l2_auto_widget_in_c_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_bus_named_subsystem_l2_auto_widget_in_c_bits_source; // @[LazyModule.scala 432:27]
  wire [30:0] coupler_to_bus_named_subsystem_l2_auto_widget_in_c_bits_address; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_bus_named_subsystem_l2_auto_widget_in_c_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_l2_auto_widget_in_c_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_l2_auto_widget_in_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_l2_auto_widget_in_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_l2_auto_widget_in_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_bus_named_subsystem_l2_auto_widget_in_d_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_l2_auto_widget_in_d_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_bus_named_subsystem_l2_auto_widget_in_d_bits_source; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_bus_named_subsystem_l2_auto_widget_in_d_bits_sink; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_bus_named_subsystem_l2_auto_widget_in_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_l2_auto_widget_in_e_valid; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_bus_named_subsystem_l2_auto_widget_in_e_bits_sink; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_l2_auto_widget_out_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_l2_auto_widget_out_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_l2_auto_widget_out_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_l2_auto_widget_out_a_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_l2_auto_widget_out_a_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_bus_named_subsystem_l2_auto_widget_out_a_bits_source; // @[LazyModule.scala 432:27]
  wire [30:0] coupler_to_bus_named_subsystem_l2_auto_widget_out_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_bus_named_subsystem_l2_auto_widget_out_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_bus_named_subsystem_l2_auto_widget_out_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_l2_auto_widget_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_l2_auto_widget_out_b_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_l2_auto_widget_out_b_valid; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_bus_named_subsystem_l2_auto_widget_out_b_bits_param; // @[LazyModule.scala 432:27]
  wire [30:0] coupler_to_bus_named_subsystem_l2_auto_widget_out_b_bits_address; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_l2_auto_widget_out_c_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_l2_auto_widget_out_c_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_l2_auto_widget_out_c_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_l2_auto_widget_out_c_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_l2_auto_widget_out_c_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_bus_named_subsystem_l2_auto_widget_out_c_bits_source; // @[LazyModule.scala 432:27]
  wire [30:0] coupler_to_bus_named_subsystem_l2_auto_widget_out_c_bits_address; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_bus_named_subsystem_l2_auto_widget_out_c_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_l2_auto_widget_out_c_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_l2_auto_widget_out_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_l2_auto_widget_out_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_l2_auto_widget_out_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_bus_named_subsystem_l2_auto_widget_out_d_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_l2_auto_widget_out_d_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_bus_named_subsystem_l2_auto_widget_out_d_bits_source; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_bus_named_subsystem_l2_auto_widget_out_d_bits_sink; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_bus_named_subsystem_l2_auto_widget_out_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_l2_auto_widget_out_e_valid; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_bus_named_subsystem_l2_auto_widget_out_e_bits_sink; // @[LazyModule.scala 432:27]
  wire  coupler_from_tile_auto_tl_master_clock_xing_in_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_from_tile_auto_tl_master_clock_xing_in_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_param; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_source; // @[LazyModule.scala 432:27]
  wire [30:0] coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_from_tile_auto_tl_master_clock_xing_in_b_ready; // @[LazyModule.scala 432:27]
  wire  coupler_from_tile_auto_tl_master_clock_xing_in_b_valid; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_from_tile_auto_tl_master_clock_xing_in_b_bits_param; // @[LazyModule.scala 432:27]
  wire [30:0] coupler_from_tile_auto_tl_master_clock_xing_in_b_bits_address; // @[LazyModule.scala 432:27]
  wire  coupler_from_tile_auto_tl_master_clock_xing_in_c_ready; // @[LazyModule.scala 432:27]
  wire  coupler_from_tile_auto_tl_master_clock_xing_in_c_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_from_tile_auto_tl_master_clock_xing_in_c_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_from_tile_auto_tl_master_clock_xing_in_c_bits_param; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_from_tile_auto_tl_master_clock_xing_in_c_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_from_tile_auto_tl_master_clock_xing_in_c_bits_source; // @[LazyModule.scala 432:27]
  wire [30:0] coupler_from_tile_auto_tl_master_clock_xing_in_c_bits_address; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_from_tile_auto_tl_master_clock_xing_in_c_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_from_tile_auto_tl_master_clock_xing_in_c_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_from_tile_auto_tl_master_clock_xing_in_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_from_tile_auto_tl_master_clock_xing_in_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_param; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_source; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_sink; // @[LazyModule.scala 432:27]
  wire  coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_denied; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_from_tile_auto_tl_master_clock_xing_in_e_valid; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_from_tile_auto_tl_master_clock_xing_in_e_bits_sink; // @[LazyModule.scala 432:27]
  wire  coupler_from_tile_auto_tl_out_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_from_tile_auto_tl_out_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_from_tile_auto_tl_out_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_from_tile_auto_tl_out_a_bits_param; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_from_tile_auto_tl_out_a_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_from_tile_auto_tl_out_a_bits_source; // @[LazyModule.scala 432:27]
  wire [30:0] coupler_from_tile_auto_tl_out_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_from_tile_auto_tl_out_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_from_tile_auto_tl_out_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_from_tile_auto_tl_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_from_tile_auto_tl_out_b_ready; // @[LazyModule.scala 432:27]
  wire  coupler_from_tile_auto_tl_out_b_valid; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_from_tile_auto_tl_out_b_bits_param; // @[LazyModule.scala 432:27]
  wire [30:0] coupler_from_tile_auto_tl_out_b_bits_address; // @[LazyModule.scala 432:27]
  wire  coupler_from_tile_auto_tl_out_c_ready; // @[LazyModule.scala 432:27]
  wire  coupler_from_tile_auto_tl_out_c_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_from_tile_auto_tl_out_c_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_from_tile_auto_tl_out_c_bits_param; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_from_tile_auto_tl_out_c_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_from_tile_auto_tl_out_c_bits_source; // @[LazyModule.scala 432:27]
  wire [30:0] coupler_from_tile_auto_tl_out_c_bits_address; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_from_tile_auto_tl_out_c_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_from_tile_auto_tl_out_c_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_from_tile_auto_tl_out_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_from_tile_auto_tl_out_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_from_tile_auto_tl_out_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_from_tile_auto_tl_out_d_bits_param; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_from_tile_auto_tl_out_d_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_from_tile_auto_tl_out_d_bits_source; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_from_tile_auto_tl_out_d_bits_sink; // @[LazyModule.scala 432:27]
  wire  coupler_from_tile_auto_tl_out_d_bits_denied; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_from_tile_auto_tl_out_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_from_tile_auto_tl_out_d_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_from_tile_auto_tl_out_e_valid; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_from_tile_auto_tl_out_e_bits_sink; // @[LazyModule.scala 432:27]
  ClockGroupAggregator subsystem_sbus_clock_groups ( // @[BusWrapper.scala 40:48]
    .auto_in_member_subsystem_sbus_5_clock(subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_5_clock),
    .auto_in_member_subsystem_sbus_5_reset(subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_5_reset),
    .auto_in_member_subsystem_sbus_4_clock(subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_4_clock),
    .auto_in_member_subsystem_sbus_4_reset(subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_4_reset),
    .auto_in_member_subsystem_sbus_3_clock(subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_3_clock),
    .auto_in_member_subsystem_sbus_3_reset(subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_3_reset),
    .auto_in_member_subsystem_sbus_2_clock(subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_2_clock),
    .auto_in_member_subsystem_sbus_2_reset(subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_2_reset),
    .auto_in_member_subsystem_sbus_1_clock(subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_1_clock),
    .auto_in_member_subsystem_sbus_1_reset(subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_1_reset),
    .auto_in_member_subsystem_sbus_0_clock(subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_0_clock),
    .auto_in_member_subsystem_sbus_0_reset(subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_0_reset),
    .auto_out_3_member_subsystem_l2_1_clock(subsystem_sbus_clock_groups_auto_out_3_member_subsystem_l2_1_clock),
    .auto_out_3_member_subsystem_l2_1_reset(subsystem_sbus_clock_groups_auto_out_3_member_subsystem_l2_1_reset),
    .auto_out_3_member_subsystem_l2_0_clock(subsystem_sbus_clock_groups_auto_out_3_member_subsystem_l2_0_clock),
    .auto_out_3_member_subsystem_l2_0_reset(subsystem_sbus_clock_groups_auto_out_3_member_subsystem_l2_0_reset),
    .auto_out_2_member_subsystem_fbus_0_clock(subsystem_sbus_clock_groups_auto_out_2_member_subsystem_fbus_0_clock),
    .auto_out_2_member_subsystem_fbus_0_reset(subsystem_sbus_clock_groups_auto_out_2_member_subsystem_fbus_0_reset),
    .auto_out_1_member_subsystem_cbus_1_clock(subsystem_sbus_clock_groups_auto_out_1_member_subsystem_cbus_1_clock),
    .auto_out_1_member_subsystem_cbus_1_reset(subsystem_sbus_clock_groups_auto_out_1_member_subsystem_cbus_1_reset),
    .auto_out_1_member_subsystem_cbus_0_clock(subsystem_sbus_clock_groups_auto_out_1_member_subsystem_cbus_0_clock),
    .auto_out_1_member_subsystem_cbus_0_reset(subsystem_sbus_clock_groups_auto_out_1_member_subsystem_cbus_0_reset),
    .auto_out_0_member_subsystem_sbus_0_clock(subsystem_sbus_clock_groups_auto_out_0_member_subsystem_sbus_0_clock),
    .auto_out_0_member_subsystem_sbus_0_reset(subsystem_sbus_clock_groups_auto_out_0_member_subsystem_sbus_0_reset)
  );
  ClockGroup clockGroup ( // @[BusWrapper.scala 41:38]
    .auto_in_member_subsystem_sbus_0_clock(clockGroup_auto_in_member_subsystem_sbus_0_clock),
    .auto_in_member_subsystem_sbus_0_reset(clockGroup_auto_in_member_subsystem_sbus_0_reset),
    .auto_out_clock(clockGroup_auto_out_clock),
    .auto_out_reset(clockGroup_auto_out_reset)
  );
  FixedClockBroadcast fixedClockNode ( // @[ClockGroup.scala 106:107]
    .auto_in_clock(fixedClockNode_auto_in_clock),
    .auto_in_reset(fixedClockNode_auto_in_reset),
    .auto_out_2_clock(fixedClockNode_auto_out_2_clock),
    .auto_out_2_reset(fixedClockNode_auto_out_2_reset),
    .auto_out_0_clock(fixedClockNode_auto_out_0_clock),
    .auto_out_0_reset(fixedClockNode_auto_out_0_reset)
  );
  TLXbar system_bus_xbar ( // @[SystemBus.scala 40:43]
    .clock(system_bus_xbar_clock),
    .reset(system_bus_xbar_reset),
    .auto_in_a_ready(system_bus_xbar_auto_in_a_ready),
    .auto_in_a_valid(system_bus_xbar_auto_in_a_valid),
    .auto_in_a_bits_opcode(system_bus_xbar_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(system_bus_xbar_auto_in_a_bits_param),
    .auto_in_a_bits_size(system_bus_xbar_auto_in_a_bits_size),
    .auto_in_a_bits_source(system_bus_xbar_auto_in_a_bits_source),
    .auto_in_a_bits_address(system_bus_xbar_auto_in_a_bits_address),
    .auto_in_a_bits_mask(system_bus_xbar_auto_in_a_bits_mask),
    .auto_in_a_bits_data(system_bus_xbar_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(system_bus_xbar_auto_in_a_bits_corrupt),
    .auto_in_b_ready(system_bus_xbar_auto_in_b_ready),
    .auto_in_b_valid(system_bus_xbar_auto_in_b_valid),
    .auto_in_b_bits_param(system_bus_xbar_auto_in_b_bits_param),
    .auto_in_b_bits_address(system_bus_xbar_auto_in_b_bits_address),
    .auto_in_c_ready(system_bus_xbar_auto_in_c_ready),
    .auto_in_c_valid(system_bus_xbar_auto_in_c_valid),
    .auto_in_c_bits_opcode(system_bus_xbar_auto_in_c_bits_opcode),
    .auto_in_c_bits_param(system_bus_xbar_auto_in_c_bits_param),
    .auto_in_c_bits_size(system_bus_xbar_auto_in_c_bits_size),
    .auto_in_c_bits_source(system_bus_xbar_auto_in_c_bits_source),
    .auto_in_c_bits_address(system_bus_xbar_auto_in_c_bits_address),
    .auto_in_c_bits_data(system_bus_xbar_auto_in_c_bits_data),
    .auto_in_c_bits_corrupt(system_bus_xbar_auto_in_c_bits_corrupt),
    .auto_in_d_ready(system_bus_xbar_auto_in_d_ready),
    .auto_in_d_valid(system_bus_xbar_auto_in_d_valid),
    .auto_in_d_bits_opcode(system_bus_xbar_auto_in_d_bits_opcode),
    .auto_in_d_bits_param(system_bus_xbar_auto_in_d_bits_param),
    .auto_in_d_bits_size(system_bus_xbar_auto_in_d_bits_size),
    .auto_in_d_bits_source(system_bus_xbar_auto_in_d_bits_source),
    .auto_in_d_bits_sink(system_bus_xbar_auto_in_d_bits_sink),
    .auto_in_d_bits_denied(system_bus_xbar_auto_in_d_bits_denied),
    .auto_in_d_bits_data(system_bus_xbar_auto_in_d_bits_data),
    .auto_in_d_bits_corrupt(system_bus_xbar_auto_in_d_bits_corrupt),
    .auto_in_e_valid(system_bus_xbar_auto_in_e_valid),
    .auto_in_e_bits_sink(system_bus_xbar_auto_in_e_bits_sink),
    .auto_out_1_a_ready(system_bus_xbar_auto_out_1_a_ready),
    .auto_out_1_a_valid(system_bus_xbar_auto_out_1_a_valid),
    .auto_out_1_a_bits_opcode(system_bus_xbar_auto_out_1_a_bits_opcode),
    .auto_out_1_a_bits_param(system_bus_xbar_auto_out_1_a_bits_param),
    .auto_out_1_a_bits_size(system_bus_xbar_auto_out_1_a_bits_size),
    .auto_out_1_a_bits_source(system_bus_xbar_auto_out_1_a_bits_source),
    .auto_out_1_a_bits_address(system_bus_xbar_auto_out_1_a_bits_address),
    .auto_out_1_a_bits_mask(system_bus_xbar_auto_out_1_a_bits_mask),
    .auto_out_1_a_bits_data(system_bus_xbar_auto_out_1_a_bits_data),
    .auto_out_1_a_bits_corrupt(system_bus_xbar_auto_out_1_a_bits_corrupt),
    .auto_out_1_b_ready(system_bus_xbar_auto_out_1_b_ready),
    .auto_out_1_b_valid(system_bus_xbar_auto_out_1_b_valid),
    .auto_out_1_b_bits_param(system_bus_xbar_auto_out_1_b_bits_param),
    .auto_out_1_b_bits_address(system_bus_xbar_auto_out_1_b_bits_address),
    .auto_out_1_c_ready(system_bus_xbar_auto_out_1_c_ready),
    .auto_out_1_c_valid(system_bus_xbar_auto_out_1_c_valid),
    .auto_out_1_c_bits_opcode(system_bus_xbar_auto_out_1_c_bits_opcode),
    .auto_out_1_c_bits_param(system_bus_xbar_auto_out_1_c_bits_param),
    .auto_out_1_c_bits_size(system_bus_xbar_auto_out_1_c_bits_size),
    .auto_out_1_c_bits_source(system_bus_xbar_auto_out_1_c_bits_source),
    .auto_out_1_c_bits_address(system_bus_xbar_auto_out_1_c_bits_address),
    .auto_out_1_c_bits_data(system_bus_xbar_auto_out_1_c_bits_data),
    .auto_out_1_c_bits_corrupt(system_bus_xbar_auto_out_1_c_bits_corrupt),
    .auto_out_1_d_ready(system_bus_xbar_auto_out_1_d_ready),
    .auto_out_1_d_valid(system_bus_xbar_auto_out_1_d_valid),
    .auto_out_1_d_bits_opcode(system_bus_xbar_auto_out_1_d_bits_opcode),
    .auto_out_1_d_bits_param(system_bus_xbar_auto_out_1_d_bits_param),
    .auto_out_1_d_bits_size(system_bus_xbar_auto_out_1_d_bits_size),
    .auto_out_1_d_bits_source(system_bus_xbar_auto_out_1_d_bits_source),
    .auto_out_1_d_bits_sink(system_bus_xbar_auto_out_1_d_bits_sink),
    .auto_out_1_d_bits_data(system_bus_xbar_auto_out_1_d_bits_data),
    .auto_out_1_e_valid(system_bus_xbar_auto_out_1_e_valid),
    .auto_out_1_e_bits_sink(system_bus_xbar_auto_out_1_e_bits_sink),
    .auto_out_0_a_ready(system_bus_xbar_auto_out_0_a_ready),
    .auto_out_0_a_valid(system_bus_xbar_auto_out_0_a_valid),
    .auto_out_0_a_bits_opcode(system_bus_xbar_auto_out_0_a_bits_opcode),
    .auto_out_0_a_bits_param(system_bus_xbar_auto_out_0_a_bits_param),
    .auto_out_0_a_bits_size(system_bus_xbar_auto_out_0_a_bits_size),
    .auto_out_0_a_bits_source(system_bus_xbar_auto_out_0_a_bits_source),
    .auto_out_0_a_bits_address(system_bus_xbar_auto_out_0_a_bits_address),
    .auto_out_0_a_bits_mask(system_bus_xbar_auto_out_0_a_bits_mask),
    .auto_out_0_a_bits_data(system_bus_xbar_auto_out_0_a_bits_data),
    .auto_out_0_a_bits_corrupt(system_bus_xbar_auto_out_0_a_bits_corrupt),
    .auto_out_0_d_ready(system_bus_xbar_auto_out_0_d_ready),
    .auto_out_0_d_valid(system_bus_xbar_auto_out_0_d_valid),
    .auto_out_0_d_bits_opcode(system_bus_xbar_auto_out_0_d_bits_opcode),
    .auto_out_0_d_bits_param(system_bus_xbar_auto_out_0_d_bits_param),
    .auto_out_0_d_bits_size(system_bus_xbar_auto_out_0_d_bits_size),
    .auto_out_0_d_bits_source(system_bus_xbar_auto_out_0_d_bits_source),
    .auto_out_0_d_bits_sink(system_bus_xbar_auto_out_0_d_bits_sink),
    .auto_out_0_d_bits_denied(system_bus_xbar_auto_out_0_d_bits_denied),
    .auto_out_0_d_bits_data(system_bus_xbar_auto_out_0_d_bits_data),
    .auto_out_0_d_bits_corrupt(system_bus_xbar_auto_out_0_d_bits_corrupt)
  );
  TLFIFOFixer fixer ( // @[FIFOFixer.scala 144:27]
    .clock(fixer_clock),
    .reset(fixer_reset),
    .auto_in_a_ready(fixer_auto_in_a_ready),
    .auto_in_a_valid(fixer_auto_in_a_valid),
    .auto_in_a_bits_opcode(fixer_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(fixer_auto_in_a_bits_param),
    .auto_in_a_bits_size(fixer_auto_in_a_bits_size),
    .auto_in_a_bits_source(fixer_auto_in_a_bits_source),
    .auto_in_a_bits_address(fixer_auto_in_a_bits_address),
    .auto_in_a_bits_mask(fixer_auto_in_a_bits_mask),
    .auto_in_a_bits_data(fixer_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(fixer_auto_in_a_bits_corrupt),
    .auto_in_b_ready(fixer_auto_in_b_ready),
    .auto_in_b_valid(fixer_auto_in_b_valid),
    .auto_in_b_bits_param(fixer_auto_in_b_bits_param),
    .auto_in_b_bits_address(fixer_auto_in_b_bits_address),
    .auto_in_c_ready(fixer_auto_in_c_ready),
    .auto_in_c_valid(fixer_auto_in_c_valid),
    .auto_in_c_bits_opcode(fixer_auto_in_c_bits_opcode),
    .auto_in_c_bits_param(fixer_auto_in_c_bits_param),
    .auto_in_c_bits_size(fixer_auto_in_c_bits_size),
    .auto_in_c_bits_source(fixer_auto_in_c_bits_source),
    .auto_in_c_bits_address(fixer_auto_in_c_bits_address),
    .auto_in_c_bits_data(fixer_auto_in_c_bits_data),
    .auto_in_c_bits_corrupt(fixer_auto_in_c_bits_corrupt),
    .auto_in_d_ready(fixer_auto_in_d_ready),
    .auto_in_d_valid(fixer_auto_in_d_valid),
    .auto_in_d_bits_opcode(fixer_auto_in_d_bits_opcode),
    .auto_in_d_bits_param(fixer_auto_in_d_bits_param),
    .auto_in_d_bits_size(fixer_auto_in_d_bits_size),
    .auto_in_d_bits_source(fixer_auto_in_d_bits_source),
    .auto_in_d_bits_sink(fixer_auto_in_d_bits_sink),
    .auto_in_d_bits_denied(fixer_auto_in_d_bits_denied),
    .auto_in_d_bits_data(fixer_auto_in_d_bits_data),
    .auto_in_d_bits_corrupt(fixer_auto_in_d_bits_corrupt),
    .auto_in_e_valid(fixer_auto_in_e_valid),
    .auto_in_e_bits_sink(fixer_auto_in_e_bits_sink),
    .auto_out_a_ready(fixer_auto_out_a_ready),
    .auto_out_a_valid(fixer_auto_out_a_valid),
    .auto_out_a_bits_opcode(fixer_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(fixer_auto_out_a_bits_param),
    .auto_out_a_bits_size(fixer_auto_out_a_bits_size),
    .auto_out_a_bits_source(fixer_auto_out_a_bits_source),
    .auto_out_a_bits_address(fixer_auto_out_a_bits_address),
    .auto_out_a_bits_mask(fixer_auto_out_a_bits_mask),
    .auto_out_a_bits_data(fixer_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(fixer_auto_out_a_bits_corrupt),
    .auto_out_b_ready(fixer_auto_out_b_ready),
    .auto_out_b_valid(fixer_auto_out_b_valid),
    .auto_out_b_bits_param(fixer_auto_out_b_bits_param),
    .auto_out_b_bits_address(fixer_auto_out_b_bits_address),
    .auto_out_c_ready(fixer_auto_out_c_ready),
    .auto_out_c_valid(fixer_auto_out_c_valid),
    .auto_out_c_bits_opcode(fixer_auto_out_c_bits_opcode),
    .auto_out_c_bits_param(fixer_auto_out_c_bits_param),
    .auto_out_c_bits_size(fixer_auto_out_c_bits_size),
    .auto_out_c_bits_source(fixer_auto_out_c_bits_source),
    .auto_out_c_bits_address(fixer_auto_out_c_bits_address),
    .auto_out_c_bits_data(fixer_auto_out_c_bits_data),
    .auto_out_c_bits_corrupt(fixer_auto_out_c_bits_corrupt),
    .auto_out_d_ready(fixer_auto_out_d_ready),
    .auto_out_d_valid(fixer_auto_out_d_valid),
    .auto_out_d_bits_opcode(fixer_auto_out_d_bits_opcode),
    .auto_out_d_bits_param(fixer_auto_out_d_bits_param),
    .auto_out_d_bits_size(fixer_auto_out_d_bits_size),
    .auto_out_d_bits_source(fixer_auto_out_d_bits_source),
    .auto_out_d_bits_sink(fixer_auto_out_d_bits_sink),
    .auto_out_d_bits_denied(fixer_auto_out_d_bits_denied),
    .auto_out_d_bits_data(fixer_auto_out_d_bits_data),
    .auto_out_d_bits_corrupt(fixer_auto_out_d_bits_corrupt),
    .auto_out_e_valid(fixer_auto_out_e_valid),
    .auto_out_e_bits_sink(fixer_auto_out_e_bits_sink)
  );
  TLInterconnectCoupler coupler_to_bus_named_subsystem_cbus ( // @[LazyModule.scala 432:27]
    .auto_widget_in_a_ready(coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_ready),
    .auto_widget_in_a_valid(coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_valid),
    .auto_widget_in_a_bits_opcode(coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_opcode),
    .auto_widget_in_a_bits_param(coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_param),
    .auto_widget_in_a_bits_size(coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_size),
    .auto_widget_in_a_bits_source(coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_source),
    .auto_widget_in_a_bits_address(coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_address),
    .auto_widget_in_a_bits_mask(coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_mask),
    .auto_widget_in_a_bits_data(coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_data),
    .auto_widget_in_a_bits_corrupt(coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_corrupt),
    .auto_widget_in_d_ready(coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_ready),
    .auto_widget_in_d_valid(coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_valid),
    .auto_widget_in_d_bits_opcode(coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_opcode),
    .auto_widget_in_d_bits_param(coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_param),
    .auto_widget_in_d_bits_size(coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_size),
    .auto_widget_in_d_bits_source(coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_source),
    .auto_widget_in_d_bits_sink(coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_sink),
    .auto_widget_in_d_bits_denied(coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_denied),
    .auto_widget_in_d_bits_data(coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_data),
    .auto_widget_in_d_bits_corrupt(coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_corrupt),
    .auto_bus_xing_out_a_ready(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_ready),
    .auto_bus_xing_out_a_valid(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_valid),
    .auto_bus_xing_out_a_bits_opcode(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_opcode),
    .auto_bus_xing_out_a_bits_param(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_param),
    .auto_bus_xing_out_a_bits_size(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_size),
    .auto_bus_xing_out_a_bits_source(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_source),
    .auto_bus_xing_out_a_bits_address(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_address),
    .auto_bus_xing_out_a_bits_mask(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_mask),
    .auto_bus_xing_out_a_bits_data(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_data),
    .auto_bus_xing_out_a_bits_corrupt(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_corrupt),
    .auto_bus_xing_out_d_ready(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_ready),
    .auto_bus_xing_out_d_valid(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_valid),
    .auto_bus_xing_out_d_bits_opcode(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_opcode),
    .auto_bus_xing_out_d_bits_param(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_param),
    .auto_bus_xing_out_d_bits_size(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_size),
    .auto_bus_xing_out_d_bits_source(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_source),
    .auto_bus_xing_out_d_bits_sink(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_sink),
    .auto_bus_xing_out_d_bits_denied(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_denied),
    .auto_bus_xing_out_d_bits_data(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_data),
    .auto_bus_xing_out_d_bits_corrupt(coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_corrupt)
  );
  TLInterconnectCoupler_2 coupler_to_bus_named_subsystem_l2 ( // @[LazyModule.scala 432:27]
    .auto_widget_in_a_ready(coupler_to_bus_named_subsystem_l2_auto_widget_in_a_ready),
    .auto_widget_in_a_valid(coupler_to_bus_named_subsystem_l2_auto_widget_in_a_valid),
    .auto_widget_in_a_bits_opcode(coupler_to_bus_named_subsystem_l2_auto_widget_in_a_bits_opcode),
    .auto_widget_in_a_bits_param(coupler_to_bus_named_subsystem_l2_auto_widget_in_a_bits_param),
    .auto_widget_in_a_bits_size(coupler_to_bus_named_subsystem_l2_auto_widget_in_a_bits_size),
    .auto_widget_in_a_bits_source(coupler_to_bus_named_subsystem_l2_auto_widget_in_a_bits_source),
    .auto_widget_in_a_bits_address(coupler_to_bus_named_subsystem_l2_auto_widget_in_a_bits_address),
    .auto_widget_in_a_bits_mask(coupler_to_bus_named_subsystem_l2_auto_widget_in_a_bits_mask),
    .auto_widget_in_a_bits_data(coupler_to_bus_named_subsystem_l2_auto_widget_in_a_bits_data),
    .auto_widget_in_a_bits_corrupt(coupler_to_bus_named_subsystem_l2_auto_widget_in_a_bits_corrupt),
    .auto_widget_in_b_ready(coupler_to_bus_named_subsystem_l2_auto_widget_in_b_ready),
    .auto_widget_in_b_valid(coupler_to_bus_named_subsystem_l2_auto_widget_in_b_valid),
    .auto_widget_in_b_bits_param(coupler_to_bus_named_subsystem_l2_auto_widget_in_b_bits_param),
    .auto_widget_in_b_bits_address(coupler_to_bus_named_subsystem_l2_auto_widget_in_b_bits_address),
    .auto_widget_in_c_ready(coupler_to_bus_named_subsystem_l2_auto_widget_in_c_ready),
    .auto_widget_in_c_valid(coupler_to_bus_named_subsystem_l2_auto_widget_in_c_valid),
    .auto_widget_in_c_bits_opcode(coupler_to_bus_named_subsystem_l2_auto_widget_in_c_bits_opcode),
    .auto_widget_in_c_bits_param(coupler_to_bus_named_subsystem_l2_auto_widget_in_c_bits_param),
    .auto_widget_in_c_bits_size(coupler_to_bus_named_subsystem_l2_auto_widget_in_c_bits_size),
    .auto_widget_in_c_bits_source(coupler_to_bus_named_subsystem_l2_auto_widget_in_c_bits_source),
    .auto_widget_in_c_bits_address(coupler_to_bus_named_subsystem_l2_auto_widget_in_c_bits_address),
    .auto_widget_in_c_bits_data(coupler_to_bus_named_subsystem_l2_auto_widget_in_c_bits_data),
    .auto_widget_in_c_bits_corrupt(coupler_to_bus_named_subsystem_l2_auto_widget_in_c_bits_corrupt),
    .auto_widget_in_d_ready(coupler_to_bus_named_subsystem_l2_auto_widget_in_d_ready),
    .auto_widget_in_d_valid(coupler_to_bus_named_subsystem_l2_auto_widget_in_d_valid),
    .auto_widget_in_d_bits_opcode(coupler_to_bus_named_subsystem_l2_auto_widget_in_d_bits_opcode),
    .auto_widget_in_d_bits_param(coupler_to_bus_named_subsystem_l2_auto_widget_in_d_bits_param),
    .auto_widget_in_d_bits_size(coupler_to_bus_named_subsystem_l2_auto_widget_in_d_bits_size),
    .auto_widget_in_d_bits_source(coupler_to_bus_named_subsystem_l2_auto_widget_in_d_bits_source),
    .auto_widget_in_d_bits_sink(coupler_to_bus_named_subsystem_l2_auto_widget_in_d_bits_sink),
    .auto_widget_in_d_bits_data(coupler_to_bus_named_subsystem_l2_auto_widget_in_d_bits_data),
    .auto_widget_in_e_valid(coupler_to_bus_named_subsystem_l2_auto_widget_in_e_valid),
    .auto_widget_in_e_bits_sink(coupler_to_bus_named_subsystem_l2_auto_widget_in_e_bits_sink),
    .auto_widget_out_a_ready(coupler_to_bus_named_subsystem_l2_auto_widget_out_a_ready),
    .auto_widget_out_a_valid(coupler_to_bus_named_subsystem_l2_auto_widget_out_a_valid),
    .auto_widget_out_a_bits_opcode(coupler_to_bus_named_subsystem_l2_auto_widget_out_a_bits_opcode),
    .auto_widget_out_a_bits_param(coupler_to_bus_named_subsystem_l2_auto_widget_out_a_bits_param),
    .auto_widget_out_a_bits_size(coupler_to_bus_named_subsystem_l2_auto_widget_out_a_bits_size),
    .auto_widget_out_a_bits_source(coupler_to_bus_named_subsystem_l2_auto_widget_out_a_bits_source),
    .auto_widget_out_a_bits_address(coupler_to_bus_named_subsystem_l2_auto_widget_out_a_bits_address),
    .auto_widget_out_a_bits_mask(coupler_to_bus_named_subsystem_l2_auto_widget_out_a_bits_mask),
    .auto_widget_out_a_bits_data(coupler_to_bus_named_subsystem_l2_auto_widget_out_a_bits_data),
    .auto_widget_out_a_bits_corrupt(coupler_to_bus_named_subsystem_l2_auto_widget_out_a_bits_corrupt),
    .auto_widget_out_b_ready(coupler_to_bus_named_subsystem_l2_auto_widget_out_b_ready),
    .auto_widget_out_b_valid(coupler_to_bus_named_subsystem_l2_auto_widget_out_b_valid),
    .auto_widget_out_b_bits_param(coupler_to_bus_named_subsystem_l2_auto_widget_out_b_bits_param),
    .auto_widget_out_b_bits_address(coupler_to_bus_named_subsystem_l2_auto_widget_out_b_bits_address),
    .auto_widget_out_c_ready(coupler_to_bus_named_subsystem_l2_auto_widget_out_c_ready),
    .auto_widget_out_c_valid(coupler_to_bus_named_subsystem_l2_auto_widget_out_c_valid),
    .auto_widget_out_c_bits_opcode(coupler_to_bus_named_subsystem_l2_auto_widget_out_c_bits_opcode),
    .auto_widget_out_c_bits_param(coupler_to_bus_named_subsystem_l2_auto_widget_out_c_bits_param),
    .auto_widget_out_c_bits_size(coupler_to_bus_named_subsystem_l2_auto_widget_out_c_bits_size),
    .auto_widget_out_c_bits_source(coupler_to_bus_named_subsystem_l2_auto_widget_out_c_bits_source),
    .auto_widget_out_c_bits_address(coupler_to_bus_named_subsystem_l2_auto_widget_out_c_bits_address),
    .auto_widget_out_c_bits_data(coupler_to_bus_named_subsystem_l2_auto_widget_out_c_bits_data),
    .auto_widget_out_c_bits_corrupt(coupler_to_bus_named_subsystem_l2_auto_widget_out_c_bits_corrupt),
    .auto_widget_out_d_ready(coupler_to_bus_named_subsystem_l2_auto_widget_out_d_ready),
    .auto_widget_out_d_valid(coupler_to_bus_named_subsystem_l2_auto_widget_out_d_valid),
    .auto_widget_out_d_bits_opcode(coupler_to_bus_named_subsystem_l2_auto_widget_out_d_bits_opcode),
    .auto_widget_out_d_bits_param(coupler_to_bus_named_subsystem_l2_auto_widget_out_d_bits_param),
    .auto_widget_out_d_bits_size(coupler_to_bus_named_subsystem_l2_auto_widget_out_d_bits_size),
    .auto_widget_out_d_bits_source(coupler_to_bus_named_subsystem_l2_auto_widget_out_d_bits_source),
    .auto_widget_out_d_bits_sink(coupler_to_bus_named_subsystem_l2_auto_widget_out_d_bits_sink),
    .auto_widget_out_d_bits_data(coupler_to_bus_named_subsystem_l2_auto_widget_out_d_bits_data),
    .auto_widget_out_e_valid(coupler_to_bus_named_subsystem_l2_auto_widget_out_e_valid),
    .auto_widget_out_e_bits_sink(coupler_to_bus_named_subsystem_l2_auto_widget_out_e_bits_sink)
  );
  TLInterconnectCoupler_3 coupler_from_tile ( // @[LazyModule.scala 432:27]
    .auto_tl_master_clock_xing_in_a_ready(coupler_from_tile_auto_tl_master_clock_xing_in_a_ready),
    .auto_tl_master_clock_xing_in_a_valid(coupler_from_tile_auto_tl_master_clock_xing_in_a_valid),
    .auto_tl_master_clock_xing_in_a_bits_opcode(coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_opcode),
    .auto_tl_master_clock_xing_in_a_bits_param(coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_param),
    .auto_tl_master_clock_xing_in_a_bits_size(coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_size),
    .auto_tl_master_clock_xing_in_a_bits_source(coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_source),
    .auto_tl_master_clock_xing_in_a_bits_address(coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_address),
    .auto_tl_master_clock_xing_in_a_bits_mask(coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_mask),
    .auto_tl_master_clock_xing_in_a_bits_data(coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_data),
    .auto_tl_master_clock_xing_in_a_bits_corrupt(coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_corrupt),
    .auto_tl_master_clock_xing_in_b_ready(coupler_from_tile_auto_tl_master_clock_xing_in_b_ready),
    .auto_tl_master_clock_xing_in_b_valid(coupler_from_tile_auto_tl_master_clock_xing_in_b_valid),
    .auto_tl_master_clock_xing_in_b_bits_param(coupler_from_tile_auto_tl_master_clock_xing_in_b_bits_param),
    .auto_tl_master_clock_xing_in_b_bits_address(coupler_from_tile_auto_tl_master_clock_xing_in_b_bits_address),
    .auto_tl_master_clock_xing_in_c_ready(coupler_from_tile_auto_tl_master_clock_xing_in_c_ready),
    .auto_tl_master_clock_xing_in_c_valid(coupler_from_tile_auto_tl_master_clock_xing_in_c_valid),
    .auto_tl_master_clock_xing_in_c_bits_opcode(coupler_from_tile_auto_tl_master_clock_xing_in_c_bits_opcode),
    .auto_tl_master_clock_xing_in_c_bits_param(coupler_from_tile_auto_tl_master_clock_xing_in_c_bits_param),
    .auto_tl_master_clock_xing_in_c_bits_size(coupler_from_tile_auto_tl_master_clock_xing_in_c_bits_size),
    .auto_tl_master_clock_xing_in_c_bits_source(coupler_from_tile_auto_tl_master_clock_xing_in_c_bits_source),
    .auto_tl_master_clock_xing_in_c_bits_address(coupler_from_tile_auto_tl_master_clock_xing_in_c_bits_address),
    .auto_tl_master_clock_xing_in_c_bits_data(coupler_from_tile_auto_tl_master_clock_xing_in_c_bits_data),
    .auto_tl_master_clock_xing_in_c_bits_corrupt(coupler_from_tile_auto_tl_master_clock_xing_in_c_bits_corrupt),
    .auto_tl_master_clock_xing_in_d_ready(coupler_from_tile_auto_tl_master_clock_xing_in_d_ready),
    .auto_tl_master_clock_xing_in_d_valid(coupler_from_tile_auto_tl_master_clock_xing_in_d_valid),
    .auto_tl_master_clock_xing_in_d_bits_opcode(coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_opcode),
    .auto_tl_master_clock_xing_in_d_bits_param(coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_param),
    .auto_tl_master_clock_xing_in_d_bits_size(coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_size),
    .auto_tl_master_clock_xing_in_d_bits_source(coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_source),
    .auto_tl_master_clock_xing_in_d_bits_sink(coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_sink),
    .auto_tl_master_clock_xing_in_d_bits_denied(coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_denied),
    .auto_tl_master_clock_xing_in_d_bits_data(coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_data),
    .auto_tl_master_clock_xing_in_d_bits_corrupt(coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_corrupt),
    .auto_tl_master_clock_xing_in_e_valid(coupler_from_tile_auto_tl_master_clock_xing_in_e_valid),
    .auto_tl_master_clock_xing_in_e_bits_sink(coupler_from_tile_auto_tl_master_clock_xing_in_e_bits_sink),
    .auto_tl_out_a_ready(coupler_from_tile_auto_tl_out_a_ready),
    .auto_tl_out_a_valid(coupler_from_tile_auto_tl_out_a_valid),
    .auto_tl_out_a_bits_opcode(coupler_from_tile_auto_tl_out_a_bits_opcode),
    .auto_tl_out_a_bits_param(coupler_from_tile_auto_tl_out_a_bits_param),
    .auto_tl_out_a_bits_size(coupler_from_tile_auto_tl_out_a_bits_size),
    .auto_tl_out_a_bits_source(coupler_from_tile_auto_tl_out_a_bits_source),
    .auto_tl_out_a_bits_address(coupler_from_tile_auto_tl_out_a_bits_address),
    .auto_tl_out_a_bits_mask(coupler_from_tile_auto_tl_out_a_bits_mask),
    .auto_tl_out_a_bits_data(coupler_from_tile_auto_tl_out_a_bits_data),
    .auto_tl_out_a_bits_corrupt(coupler_from_tile_auto_tl_out_a_bits_corrupt),
    .auto_tl_out_b_ready(coupler_from_tile_auto_tl_out_b_ready),
    .auto_tl_out_b_valid(coupler_from_tile_auto_tl_out_b_valid),
    .auto_tl_out_b_bits_param(coupler_from_tile_auto_tl_out_b_bits_param),
    .auto_tl_out_b_bits_address(coupler_from_tile_auto_tl_out_b_bits_address),
    .auto_tl_out_c_ready(coupler_from_tile_auto_tl_out_c_ready),
    .auto_tl_out_c_valid(coupler_from_tile_auto_tl_out_c_valid),
    .auto_tl_out_c_bits_opcode(coupler_from_tile_auto_tl_out_c_bits_opcode),
    .auto_tl_out_c_bits_param(coupler_from_tile_auto_tl_out_c_bits_param),
    .auto_tl_out_c_bits_size(coupler_from_tile_auto_tl_out_c_bits_size),
    .auto_tl_out_c_bits_source(coupler_from_tile_auto_tl_out_c_bits_source),
    .auto_tl_out_c_bits_address(coupler_from_tile_auto_tl_out_c_bits_address),
    .auto_tl_out_c_bits_data(coupler_from_tile_auto_tl_out_c_bits_data),
    .auto_tl_out_c_bits_corrupt(coupler_from_tile_auto_tl_out_c_bits_corrupt),
    .auto_tl_out_d_ready(coupler_from_tile_auto_tl_out_d_ready),
    .auto_tl_out_d_valid(coupler_from_tile_auto_tl_out_d_valid),
    .auto_tl_out_d_bits_opcode(coupler_from_tile_auto_tl_out_d_bits_opcode),
    .auto_tl_out_d_bits_param(coupler_from_tile_auto_tl_out_d_bits_param),
    .auto_tl_out_d_bits_size(coupler_from_tile_auto_tl_out_d_bits_size),
    .auto_tl_out_d_bits_source(coupler_from_tile_auto_tl_out_d_bits_source),
    .auto_tl_out_d_bits_sink(coupler_from_tile_auto_tl_out_d_bits_sink),
    .auto_tl_out_d_bits_denied(coupler_from_tile_auto_tl_out_d_bits_denied),
    .auto_tl_out_d_bits_data(coupler_from_tile_auto_tl_out_d_bits_data),
    .auto_tl_out_d_bits_corrupt(coupler_from_tile_auto_tl_out_d_bits_corrupt),
    .auto_tl_out_e_valid(coupler_from_tile_auto_tl_out_e_valid),
    .auto_tl_out_e_bits_sink(coupler_from_tile_auto_tl_out_e_bits_sink)
  );
  assign auto_coupler_from_tile_tl_master_clock_xing_in_a_ready = coupler_from_tile_auto_tl_master_clock_xing_in_a_ready
    ; // @[LazyModule.scala 309:16]
  assign auto_coupler_from_tile_tl_master_clock_xing_in_b_valid = coupler_from_tile_auto_tl_master_clock_xing_in_b_valid
    ; // @[LazyModule.scala 309:16]
  assign auto_coupler_from_tile_tl_master_clock_xing_in_b_bits_param =
    coupler_from_tile_auto_tl_master_clock_xing_in_b_bits_param; // @[LazyModule.scala 309:16]
  assign auto_coupler_from_tile_tl_master_clock_xing_in_b_bits_address =
    coupler_from_tile_auto_tl_master_clock_xing_in_b_bits_address; // @[LazyModule.scala 309:16]
  assign auto_coupler_from_tile_tl_master_clock_xing_in_c_ready = coupler_from_tile_auto_tl_master_clock_xing_in_c_ready
    ; // @[LazyModule.scala 309:16]
  assign auto_coupler_from_tile_tl_master_clock_xing_in_d_valid = coupler_from_tile_auto_tl_master_clock_xing_in_d_valid
    ; // @[LazyModule.scala 309:16]
  assign auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_opcode =
    coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_opcode; // @[LazyModule.scala 309:16]
  assign auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_param =
    coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_param; // @[LazyModule.scala 309:16]
  assign auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_size =
    coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_size; // @[LazyModule.scala 309:16]
  assign auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_source =
    coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_source; // @[LazyModule.scala 309:16]
  assign auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_sink =
    coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_sink; // @[LazyModule.scala 309:16]
  assign auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_denied =
    coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_denied; // @[LazyModule.scala 309:16]
  assign auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_data =
    coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_data; // @[LazyModule.scala 309:16]
  assign auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_corrupt =
    coupler_from_tile_auto_tl_master_clock_xing_in_d_bits_corrupt; // @[LazyModule.scala 309:16]
  assign auto_coupler_to_bus_named_subsystem_l2_widget_out_a_valid =
    coupler_to_bus_named_subsystem_l2_auto_widget_out_a_valid; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_opcode =
    coupler_to_bus_named_subsystem_l2_auto_widget_out_a_bits_opcode; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_param =
    coupler_to_bus_named_subsystem_l2_auto_widget_out_a_bits_param; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_size =
    coupler_to_bus_named_subsystem_l2_auto_widget_out_a_bits_size; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_source =
    coupler_to_bus_named_subsystem_l2_auto_widget_out_a_bits_source; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_address =
    coupler_to_bus_named_subsystem_l2_auto_widget_out_a_bits_address; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_mask =
    coupler_to_bus_named_subsystem_l2_auto_widget_out_a_bits_mask; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_data =
    coupler_to_bus_named_subsystem_l2_auto_widget_out_a_bits_data; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_corrupt =
    coupler_to_bus_named_subsystem_l2_auto_widget_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_l2_widget_out_b_ready =
    coupler_to_bus_named_subsystem_l2_auto_widget_out_b_ready; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_l2_widget_out_c_valid =
    coupler_to_bus_named_subsystem_l2_auto_widget_out_c_valid; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_opcode =
    coupler_to_bus_named_subsystem_l2_auto_widget_out_c_bits_opcode; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_param =
    coupler_to_bus_named_subsystem_l2_auto_widget_out_c_bits_param; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_size =
    coupler_to_bus_named_subsystem_l2_auto_widget_out_c_bits_size; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_source =
    coupler_to_bus_named_subsystem_l2_auto_widget_out_c_bits_source; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_address =
    coupler_to_bus_named_subsystem_l2_auto_widget_out_c_bits_address; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_data =
    coupler_to_bus_named_subsystem_l2_auto_widget_out_c_bits_data; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_corrupt =
    coupler_to_bus_named_subsystem_l2_auto_widget_out_c_bits_corrupt; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_l2_widget_out_d_ready =
    coupler_to_bus_named_subsystem_l2_auto_widget_out_d_ready; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_l2_widget_out_e_valid =
    coupler_to_bus_named_subsystem_l2_auto_widget_out_e_valid; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_l2_widget_out_e_bits_sink =
    coupler_to_bus_named_subsystem_l2_auto_widget_out_e_bits_sink; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_valid =
    coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_valid; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_opcode =
    coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_opcode; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_param =
    coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_param; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_size =
    coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_size; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_source =
    coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_source; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_address =
    coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_address; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_mask =
    coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_mask; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_data =
    coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_data; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_corrupt =
    coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_ready =
    coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_ready; // @[LazyModule.scala 311:12]
  assign auto_fixedClockNode_out_1_clock = fixedClockNode_auto_out_2_clock; // @[LazyModule.scala 311:12]
  assign auto_fixedClockNode_out_1_reset = fixedClockNode_auto_out_2_reset; // @[LazyModule.scala 311:12]
  assign auto_subsystem_sbus_clock_groups_out_2_member_subsystem_l2_1_clock =
    subsystem_sbus_clock_groups_auto_out_3_member_subsystem_l2_1_clock; // @[LazyModule.scala 311:12]
  assign auto_subsystem_sbus_clock_groups_out_2_member_subsystem_l2_1_reset =
    subsystem_sbus_clock_groups_auto_out_3_member_subsystem_l2_1_reset; // @[LazyModule.scala 311:12]
  assign auto_subsystem_sbus_clock_groups_out_2_member_subsystem_l2_0_clock =
    subsystem_sbus_clock_groups_auto_out_3_member_subsystem_l2_0_clock; // @[LazyModule.scala 311:12]
  assign auto_subsystem_sbus_clock_groups_out_2_member_subsystem_l2_0_reset =
    subsystem_sbus_clock_groups_auto_out_3_member_subsystem_l2_0_reset; // @[LazyModule.scala 311:12]
  assign auto_subsystem_sbus_clock_groups_out_1_member_subsystem_fbus_0_clock =
    subsystem_sbus_clock_groups_auto_out_2_member_subsystem_fbus_0_clock; // @[LazyModule.scala 311:12]
  assign auto_subsystem_sbus_clock_groups_out_1_member_subsystem_fbus_0_reset =
    subsystem_sbus_clock_groups_auto_out_2_member_subsystem_fbus_0_reset; // @[LazyModule.scala 311:12]
  assign auto_subsystem_sbus_clock_groups_out_0_member_subsystem_cbus_1_clock =
    subsystem_sbus_clock_groups_auto_out_1_member_subsystem_cbus_1_clock; // @[LazyModule.scala 311:12]
  assign auto_subsystem_sbus_clock_groups_out_0_member_subsystem_cbus_1_reset =
    subsystem_sbus_clock_groups_auto_out_1_member_subsystem_cbus_1_reset; // @[LazyModule.scala 311:12]
  assign auto_subsystem_sbus_clock_groups_out_0_member_subsystem_cbus_0_clock =
    subsystem_sbus_clock_groups_auto_out_1_member_subsystem_cbus_0_clock; // @[LazyModule.scala 311:12]
  assign auto_subsystem_sbus_clock_groups_out_0_member_subsystem_cbus_0_reset =
    subsystem_sbus_clock_groups_auto_out_1_member_subsystem_cbus_0_reset; // @[LazyModule.scala 311:12]
  assign subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_5_clock =
    auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_5_clock; // @[LazyModule.scala 309:16]
  assign subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_5_reset =
    auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_5_reset; // @[LazyModule.scala 309:16]
  assign subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_4_clock =
    auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_4_clock; // @[LazyModule.scala 309:16]
  assign subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_4_reset =
    auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_4_reset; // @[LazyModule.scala 309:16]
  assign subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_3_clock =
    auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_3_clock; // @[LazyModule.scala 309:16]
  assign subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_3_reset =
    auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_3_reset; // @[LazyModule.scala 309:16]
  assign subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_2_clock =
    auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_2_clock; // @[LazyModule.scala 309:16]
  assign subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_2_reset =
    auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_2_reset; // @[LazyModule.scala 309:16]
  assign subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_1_clock =
    auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_1_clock; // @[LazyModule.scala 309:16]
  assign subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_1_reset =
    auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_1_reset; // @[LazyModule.scala 309:16]
  assign subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_0_clock =
    auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_0_clock; // @[LazyModule.scala 309:16]
  assign subsystem_sbus_clock_groups_auto_in_member_subsystem_sbus_0_reset =
    auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_0_reset; // @[LazyModule.scala 309:16]
  assign clockGroup_auto_in_member_subsystem_sbus_0_clock =
    subsystem_sbus_clock_groups_auto_out_0_member_subsystem_sbus_0_clock; // @[LazyModule.scala 298:16]
  assign clockGroup_auto_in_member_subsystem_sbus_0_reset =
    subsystem_sbus_clock_groups_auto_out_0_member_subsystem_sbus_0_reset; // @[LazyModule.scala 298:16]
  assign fixedClockNode_auto_in_clock = clockGroup_auto_out_clock; // @[LazyModule.scala 298:16]
  assign fixedClockNode_auto_in_reset = clockGroup_auto_out_reset; // @[LazyModule.scala 298:16]
  assign system_bus_xbar_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign system_bus_xbar_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign system_bus_xbar_auto_in_a_valid = fixer_auto_out_a_valid; // @[LazyModule.scala 296:16]
  assign system_bus_xbar_auto_in_a_bits_opcode = fixer_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign system_bus_xbar_auto_in_a_bits_param = fixer_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
  assign system_bus_xbar_auto_in_a_bits_size = fixer_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign system_bus_xbar_auto_in_a_bits_source = fixer_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign system_bus_xbar_auto_in_a_bits_address = fixer_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign system_bus_xbar_auto_in_a_bits_mask = fixer_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign system_bus_xbar_auto_in_a_bits_data = fixer_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign system_bus_xbar_auto_in_a_bits_corrupt = fixer_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
  assign system_bus_xbar_auto_in_b_ready = fixer_auto_out_b_ready; // @[LazyModule.scala 296:16]
  assign system_bus_xbar_auto_in_c_valid = fixer_auto_out_c_valid; // @[LazyModule.scala 296:16]
  assign system_bus_xbar_auto_in_c_bits_opcode = fixer_auto_out_c_bits_opcode; // @[LazyModule.scala 296:16]
  assign system_bus_xbar_auto_in_c_bits_param = fixer_auto_out_c_bits_param; // @[LazyModule.scala 296:16]
  assign system_bus_xbar_auto_in_c_bits_size = fixer_auto_out_c_bits_size; // @[LazyModule.scala 296:16]
  assign system_bus_xbar_auto_in_c_bits_source = fixer_auto_out_c_bits_source; // @[LazyModule.scala 296:16]
  assign system_bus_xbar_auto_in_c_bits_address = fixer_auto_out_c_bits_address; // @[LazyModule.scala 296:16]
  assign system_bus_xbar_auto_in_c_bits_data = fixer_auto_out_c_bits_data; // @[LazyModule.scala 296:16]
  assign system_bus_xbar_auto_in_c_bits_corrupt = fixer_auto_out_c_bits_corrupt; // @[LazyModule.scala 296:16]
  assign system_bus_xbar_auto_in_d_ready = fixer_auto_out_d_ready; // @[LazyModule.scala 296:16]
  assign system_bus_xbar_auto_in_e_valid = fixer_auto_out_e_valid; // @[LazyModule.scala 296:16]
  assign system_bus_xbar_auto_in_e_bits_sink = fixer_auto_out_e_bits_sink; // @[LazyModule.scala 296:16]
  assign system_bus_xbar_auto_out_1_a_ready = coupler_to_bus_named_subsystem_l2_auto_widget_in_a_ready; // @[LazyModule.scala 298:16]
  assign system_bus_xbar_auto_out_1_b_valid = coupler_to_bus_named_subsystem_l2_auto_widget_in_b_valid; // @[LazyModule.scala 298:16]
  assign system_bus_xbar_auto_out_1_b_bits_param = coupler_to_bus_named_subsystem_l2_auto_widget_in_b_bits_param; // @[LazyModule.scala 298:16]
  assign system_bus_xbar_auto_out_1_b_bits_address = coupler_to_bus_named_subsystem_l2_auto_widget_in_b_bits_address; // @[LazyModule.scala 298:16]
  assign system_bus_xbar_auto_out_1_c_ready = coupler_to_bus_named_subsystem_l2_auto_widget_in_c_ready; // @[LazyModule.scala 298:16]
  assign system_bus_xbar_auto_out_1_d_valid = coupler_to_bus_named_subsystem_l2_auto_widget_in_d_valid; // @[LazyModule.scala 298:16]
  assign system_bus_xbar_auto_out_1_d_bits_opcode = coupler_to_bus_named_subsystem_l2_auto_widget_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign system_bus_xbar_auto_out_1_d_bits_param = coupler_to_bus_named_subsystem_l2_auto_widget_in_d_bits_param; // @[LazyModule.scala 298:16]
  assign system_bus_xbar_auto_out_1_d_bits_size = coupler_to_bus_named_subsystem_l2_auto_widget_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign system_bus_xbar_auto_out_1_d_bits_source = coupler_to_bus_named_subsystem_l2_auto_widget_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign system_bus_xbar_auto_out_1_d_bits_sink = coupler_to_bus_named_subsystem_l2_auto_widget_in_d_bits_sink; // @[LazyModule.scala 298:16]
  assign system_bus_xbar_auto_out_1_d_bits_data = coupler_to_bus_named_subsystem_l2_auto_widget_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign system_bus_xbar_auto_out_0_a_ready = coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_ready; // @[LazyModule.scala 298:16]
  assign system_bus_xbar_auto_out_0_d_valid = coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_valid; // @[LazyModule.scala 298:16]
  assign system_bus_xbar_auto_out_0_d_bits_opcode = coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign system_bus_xbar_auto_out_0_d_bits_param = coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_param; // @[LazyModule.scala 298:16]
  assign system_bus_xbar_auto_out_0_d_bits_size = coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign system_bus_xbar_auto_out_0_d_bits_source = coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign system_bus_xbar_auto_out_0_d_bits_sink = coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_sink; // @[LazyModule.scala 298:16]
  assign system_bus_xbar_auto_out_0_d_bits_denied = coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_denied; // @[LazyModule.scala 298:16]
  assign system_bus_xbar_auto_out_0_d_bits_data = coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign system_bus_xbar_auto_out_0_d_bits_corrupt = coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_bits_corrupt; // @[LazyModule.scala 298:16]
  assign fixer_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign fixer_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign fixer_auto_in_a_valid = coupler_from_tile_auto_tl_out_a_valid; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_opcode = coupler_from_tile_auto_tl_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_param = coupler_from_tile_auto_tl_out_a_bits_param; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_size = coupler_from_tile_auto_tl_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_source = coupler_from_tile_auto_tl_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_address = coupler_from_tile_auto_tl_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_mask = coupler_from_tile_auto_tl_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_data = coupler_from_tile_auto_tl_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_corrupt = coupler_from_tile_auto_tl_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_b_ready = coupler_from_tile_auto_tl_out_b_ready; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_c_valid = coupler_from_tile_auto_tl_out_c_valid; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_c_bits_opcode = coupler_from_tile_auto_tl_out_c_bits_opcode; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_c_bits_param = coupler_from_tile_auto_tl_out_c_bits_param; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_c_bits_size = coupler_from_tile_auto_tl_out_c_bits_size; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_c_bits_source = coupler_from_tile_auto_tl_out_c_bits_source; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_c_bits_address = coupler_from_tile_auto_tl_out_c_bits_address; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_c_bits_data = coupler_from_tile_auto_tl_out_c_bits_data; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_c_bits_corrupt = coupler_from_tile_auto_tl_out_c_bits_corrupt; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_d_ready = coupler_from_tile_auto_tl_out_d_ready; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_e_valid = coupler_from_tile_auto_tl_out_e_valid; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_e_bits_sink = coupler_from_tile_auto_tl_out_e_bits_sink; // @[LazyModule.scala 296:16]
  assign fixer_auto_out_a_ready = system_bus_xbar_auto_in_a_ready; // @[LazyModule.scala 296:16]
  assign fixer_auto_out_b_valid = system_bus_xbar_auto_in_b_valid; // @[LazyModule.scala 296:16]
  assign fixer_auto_out_b_bits_param = system_bus_xbar_auto_in_b_bits_param; // @[LazyModule.scala 296:16]
  assign fixer_auto_out_b_bits_address = system_bus_xbar_auto_in_b_bits_address; // @[LazyModule.scala 296:16]
  assign fixer_auto_out_c_ready = system_bus_xbar_auto_in_c_ready; // @[LazyModule.scala 296:16]
  assign fixer_auto_out_d_valid = system_bus_xbar_auto_in_d_valid; // @[LazyModule.scala 296:16]
  assign fixer_auto_out_d_bits_opcode = system_bus_xbar_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign fixer_auto_out_d_bits_param = system_bus_xbar_auto_in_d_bits_param; // @[LazyModule.scala 296:16]
  assign fixer_auto_out_d_bits_size = system_bus_xbar_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
  assign fixer_auto_out_d_bits_source = system_bus_xbar_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
  assign fixer_auto_out_d_bits_sink = system_bus_xbar_auto_in_d_bits_sink; // @[LazyModule.scala 296:16]
  assign fixer_auto_out_d_bits_denied = system_bus_xbar_auto_in_d_bits_denied; // @[LazyModule.scala 296:16]
  assign fixer_auto_out_d_bits_data = system_bus_xbar_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
  assign fixer_auto_out_d_bits_corrupt = system_bus_xbar_auto_in_d_bits_corrupt; // @[LazyModule.scala 296:16]
  assign coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_valid = system_bus_xbar_auto_out_0_a_valid; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_opcode = system_bus_xbar_auto_out_0_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_param = system_bus_xbar_auto_out_0_a_bits_param; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_size = system_bus_xbar_auto_out_0_a_bits_size; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_source = system_bus_xbar_auto_out_0_a_bits_source; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_address = system_bus_xbar_auto_out_0_a_bits_address; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_mask = system_bus_xbar_auto_out_0_a_bits_mask; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_data = system_bus_xbar_auto_out_0_a_bits_data; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_cbus_auto_widget_in_a_bits_corrupt = system_bus_xbar_auto_out_0_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_cbus_auto_widget_in_d_ready = system_bus_xbar_auto_out_0_d_ready; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_a_ready =
    auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_ready; // @[LazyModule.scala 311:12]
  assign coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_valid =
    auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_valid; // @[LazyModule.scala 311:12]
  assign coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_opcode =
    auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_opcode; // @[LazyModule.scala 311:12]
  assign coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_param =
    auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_param; // @[LazyModule.scala 311:12]
  assign coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_size =
    auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_size; // @[LazyModule.scala 311:12]
  assign coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_source =
    auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_source; // @[LazyModule.scala 311:12]
  assign coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_sink =
    auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_sink; // @[LazyModule.scala 311:12]
  assign coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_denied =
    auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_denied; // @[LazyModule.scala 311:12]
  assign coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_data =
    auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_data; // @[LazyModule.scala 311:12]
  assign coupler_to_bus_named_subsystem_cbus_auto_bus_xing_out_d_bits_corrupt =
    auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_corrupt; // @[LazyModule.scala 311:12]
  assign coupler_to_bus_named_subsystem_l2_auto_widget_in_a_valid = system_bus_xbar_auto_out_1_a_valid; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_l2_auto_widget_in_a_bits_opcode = system_bus_xbar_auto_out_1_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_l2_auto_widget_in_a_bits_param = system_bus_xbar_auto_out_1_a_bits_param; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_l2_auto_widget_in_a_bits_size = system_bus_xbar_auto_out_1_a_bits_size; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_l2_auto_widget_in_a_bits_source = system_bus_xbar_auto_out_1_a_bits_source; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_l2_auto_widget_in_a_bits_address = system_bus_xbar_auto_out_1_a_bits_address; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_l2_auto_widget_in_a_bits_mask = system_bus_xbar_auto_out_1_a_bits_mask; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_l2_auto_widget_in_a_bits_data = system_bus_xbar_auto_out_1_a_bits_data; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_l2_auto_widget_in_a_bits_corrupt = system_bus_xbar_auto_out_1_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_l2_auto_widget_in_b_ready = system_bus_xbar_auto_out_1_b_ready; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_l2_auto_widget_in_c_valid = system_bus_xbar_auto_out_1_c_valid; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_l2_auto_widget_in_c_bits_opcode = system_bus_xbar_auto_out_1_c_bits_opcode; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_l2_auto_widget_in_c_bits_param = system_bus_xbar_auto_out_1_c_bits_param; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_l2_auto_widget_in_c_bits_size = system_bus_xbar_auto_out_1_c_bits_size; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_l2_auto_widget_in_c_bits_source = system_bus_xbar_auto_out_1_c_bits_source; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_l2_auto_widget_in_c_bits_address = system_bus_xbar_auto_out_1_c_bits_address; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_l2_auto_widget_in_c_bits_data = system_bus_xbar_auto_out_1_c_bits_data; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_l2_auto_widget_in_c_bits_corrupt = system_bus_xbar_auto_out_1_c_bits_corrupt; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_l2_auto_widget_in_d_ready = system_bus_xbar_auto_out_1_d_ready; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_l2_auto_widget_in_e_valid = system_bus_xbar_auto_out_1_e_valid; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_l2_auto_widget_in_e_bits_sink = system_bus_xbar_auto_out_1_e_bits_sink; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_l2_auto_widget_out_a_ready =
    auto_coupler_to_bus_named_subsystem_l2_widget_out_a_ready; // @[LazyModule.scala 311:12]
  assign coupler_to_bus_named_subsystem_l2_auto_widget_out_b_valid =
    auto_coupler_to_bus_named_subsystem_l2_widget_out_b_valid; // @[LazyModule.scala 311:12]
  assign coupler_to_bus_named_subsystem_l2_auto_widget_out_b_bits_param =
    auto_coupler_to_bus_named_subsystem_l2_widget_out_b_bits_param; // @[LazyModule.scala 311:12]
  assign coupler_to_bus_named_subsystem_l2_auto_widget_out_b_bits_address =
    auto_coupler_to_bus_named_subsystem_l2_widget_out_b_bits_address; // @[LazyModule.scala 311:12]
  assign coupler_to_bus_named_subsystem_l2_auto_widget_out_c_ready =
    auto_coupler_to_bus_named_subsystem_l2_widget_out_c_ready; // @[LazyModule.scala 311:12]
  assign coupler_to_bus_named_subsystem_l2_auto_widget_out_d_valid =
    auto_coupler_to_bus_named_subsystem_l2_widget_out_d_valid; // @[LazyModule.scala 311:12]
  assign coupler_to_bus_named_subsystem_l2_auto_widget_out_d_bits_opcode =
    auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_opcode; // @[LazyModule.scala 311:12]
  assign coupler_to_bus_named_subsystem_l2_auto_widget_out_d_bits_param =
    auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_param; // @[LazyModule.scala 311:12]
  assign coupler_to_bus_named_subsystem_l2_auto_widget_out_d_bits_size =
    auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_size; // @[LazyModule.scala 311:12]
  assign coupler_to_bus_named_subsystem_l2_auto_widget_out_d_bits_source =
    auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_source; // @[LazyModule.scala 311:12]
  assign coupler_to_bus_named_subsystem_l2_auto_widget_out_d_bits_sink =
    auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_sink; // @[LazyModule.scala 311:12]
  assign coupler_to_bus_named_subsystem_l2_auto_widget_out_d_bits_data =
    auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_data; // @[LazyModule.scala 311:12]
  assign coupler_from_tile_auto_tl_master_clock_xing_in_a_valid = auto_coupler_from_tile_tl_master_clock_xing_in_a_valid
    ; // @[LazyModule.scala 309:16]
  assign coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_opcode =
    auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_opcode; // @[LazyModule.scala 309:16]
  assign coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_param =
    auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_param; // @[LazyModule.scala 309:16]
  assign coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_size =
    auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_size; // @[LazyModule.scala 309:16]
  assign coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_source =
    auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_source; // @[LazyModule.scala 309:16]
  assign coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_address =
    auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_address; // @[LazyModule.scala 309:16]
  assign coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_mask =
    auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_mask; // @[LazyModule.scala 309:16]
  assign coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_data =
    auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_data; // @[LazyModule.scala 309:16]
  assign coupler_from_tile_auto_tl_master_clock_xing_in_a_bits_corrupt =
    auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
  assign coupler_from_tile_auto_tl_master_clock_xing_in_b_ready = auto_coupler_from_tile_tl_master_clock_xing_in_b_ready
    ; // @[LazyModule.scala 309:16]
  assign coupler_from_tile_auto_tl_master_clock_xing_in_c_valid = auto_coupler_from_tile_tl_master_clock_xing_in_c_valid
    ; // @[LazyModule.scala 309:16]
  assign coupler_from_tile_auto_tl_master_clock_xing_in_c_bits_opcode =
    auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_opcode; // @[LazyModule.scala 309:16]
  assign coupler_from_tile_auto_tl_master_clock_xing_in_c_bits_param =
    auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_param; // @[LazyModule.scala 309:16]
  assign coupler_from_tile_auto_tl_master_clock_xing_in_c_bits_size =
    auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_size; // @[LazyModule.scala 309:16]
  assign coupler_from_tile_auto_tl_master_clock_xing_in_c_bits_source =
    auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_source; // @[LazyModule.scala 309:16]
  assign coupler_from_tile_auto_tl_master_clock_xing_in_c_bits_address =
    auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_address; // @[LazyModule.scala 309:16]
  assign coupler_from_tile_auto_tl_master_clock_xing_in_c_bits_data =
    auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_data; // @[LazyModule.scala 309:16]
  assign coupler_from_tile_auto_tl_master_clock_xing_in_c_bits_corrupt =
    auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_corrupt; // @[LazyModule.scala 309:16]
  assign coupler_from_tile_auto_tl_master_clock_xing_in_d_ready = auto_coupler_from_tile_tl_master_clock_xing_in_d_ready
    ; // @[LazyModule.scala 309:16]
  assign coupler_from_tile_auto_tl_master_clock_xing_in_e_valid = auto_coupler_from_tile_tl_master_clock_xing_in_e_valid
    ; // @[LazyModule.scala 309:16]
  assign coupler_from_tile_auto_tl_master_clock_xing_in_e_bits_sink =
    auto_coupler_from_tile_tl_master_clock_xing_in_e_bits_sink; // @[LazyModule.scala 309:16]
  assign coupler_from_tile_auto_tl_out_a_ready = fixer_auto_in_a_ready; // @[LazyModule.scala 296:16]
  assign coupler_from_tile_auto_tl_out_b_valid = fixer_auto_in_b_valid; // @[LazyModule.scala 296:16]
  assign coupler_from_tile_auto_tl_out_b_bits_param = fixer_auto_in_b_bits_param; // @[LazyModule.scala 296:16]
  assign coupler_from_tile_auto_tl_out_b_bits_address = fixer_auto_in_b_bits_address; // @[LazyModule.scala 296:16]
  assign coupler_from_tile_auto_tl_out_c_ready = fixer_auto_in_c_ready; // @[LazyModule.scala 296:16]
  assign coupler_from_tile_auto_tl_out_d_valid = fixer_auto_in_d_valid; // @[LazyModule.scala 296:16]
  assign coupler_from_tile_auto_tl_out_d_bits_opcode = fixer_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign coupler_from_tile_auto_tl_out_d_bits_param = fixer_auto_in_d_bits_param; // @[LazyModule.scala 296:16]
  assign coupler_from_tile_auto_tl_out_d_bits_size = fixer_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
  assign coupler_from_tile_auto_tl_out_d_bits_source = fixer_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
  assign coupler_from_tile_auto_tl_out_d_bits_sink = fixer_auto_in_d_bits_sink; // @[LazyModule.scala 296:16]
  assign coupler_from_tile_auto_tl_out_d_bits_denied = fixer_auto_in_d_bits_denied; // @[LazyModule.scala 296:16]
  assign coupler_from_tile_auto_tl_out_d_bits_data = fixer_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
  assign coupler_from_tile_auto_tl_out_d_bits_corrupt = fixer_auto_in_d_bits_corrupt; // @[LazyModule.scala 296:16]
endmodule
module ClockGroupAggregator_1(
  input   auto_in_member_subsystem_pbus_0_clock,
  input   auto_in_member_subsystem_pbus_0_reset,
  output  auto_out_member_subsystem_pbus_0_clock,
  output  auto_out_member_subsystem_pbus_0_reset
);
  assign auto_out_member_subsystem_pbus_0_clock = auto_in_member_subsystem_pbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_member_subsystem_pbus_0_reset = auto_in_member_subsystem_pbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module ClockGroup_1(
  input   auto_in_member_subsystem_pbus_0_clock,
  input   auto_in_member_subsystem_pbus_0_reset,
  output  auto_out_clock,
  output  auto_out_reset
);
  assign auto_out_clock = auto_in_member_subsystem_pbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_reset = auto_in_member_subsystem_pbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module FixedClockBroadcast_1(
  input   auto_in_clock,
  input   auto_in_reset,
  output  auto_out_14_clock,
  output  auto_out_14_reset,
  output  auto_out_13_clock,
  output  auto_out_13_reset,
  output  auto_out_12_clock,
  output  auto_out_12_reset,
  output  auto_out_11_clock,
  output  auto_out_11_reset,
  output  auto_out_10_clock,
  output  auto_out_10_reset,
  output  auto_out_9_clock,
  output  auto_out_9_reset,
  output  auto_out_8_clock,
  output  auto_out_8_reset,
  output  auto_out_7_clock,
  output  auto_out_7_reset,
  output  auto_out_6_clock,
  output  auto_out_6_reset,
  output  auto_out_5_clock,
  output  auto_out_5_reset,
  output  auto_out_4_clock,
  output  auto_out_4_reset,
  output  auto_out_3_clock,
  output  auto_out_3_reset,
  output  auto_out_2_clock,
  output  auto_out_2_reset,
  output  auto_out_1_clock,
  output  auto_out_1_reset,
  output  auto_out_0_clock,
  output  auto_out_0_reset
);
  assign auto_out_14_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_14_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_13_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_13_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_12_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_12_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_11_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_11_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_10_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_10_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_9_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_9_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_8_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_8_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_7_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_7_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_6_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_6_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_5_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_5_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_4_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_4_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_3_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_3_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_2_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_2_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_0_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_0_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module TLMonitor_2(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [29:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [2:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
  wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
  wire [29:0] _GEN_71 = {{24'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [29:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 30'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [29:0] _T_45 = io_in_a_bits_address ^ 30'h10012000; // @[Parameters.scala 137:31]
  wire [30:0] _T_46 = {1'b0,$signed(_T_45)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_48 = $signed(_T_46) & -31'sh2000; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_50 = io_in_a_bits_address ^ 30'h10014000; // @[Parameters.scala 137:31]
  wire [30:0] _T_51 = {1'b0,$signed(_T_50)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_53 = $signed(_T_51) & -31'sh2000; // @[Parameters.scala 137:52]
  wire  _T_54 = $signed(_T_53) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_55 = io_in_a_bits_address ^ 30'h10016000; // @[Parameters.scala 137:31]
  wire [30:0] _T_56 = {1'b0,$signed(_T_55)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_58 = $signed(_T_56) & -31'sh1000; // @[Parameters.scala 137:52]
  wire  _T_59 = $signed(_T_58) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_60 = io_in_a_bits_address ^ 30'h10023000; // @[Parameters.scala 137:31]
  wire [30:0] _T_61 = {1'b0,$signed(_T_60)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_63 = $signed(_T_61) & -31'sh11000; // @[Parameters.scala 137:52]
  wire  _T_64 = $signed(_T_63) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_65 = io_in_a_bits_address ^ 30'h10024000; // @[Parameters.scala 137:31]
  wire [30:0] _T_66 = {1'b0,$signed(_T_65)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_68 = $signed(_T_66) & -31'sh12000; // @[Parameters.scala 137:52]
  wire  _T_69 = $signed(_T_68) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_70 = io_in_a_bits_address ^ 30'h10026000; // @[Parameters.scala 137:31]
  wire [30:0] _T_71 = {1'b0,$signed(_T_70)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_73 = $signed(_T_71) & -31'sh1000; // @[Parameters.scala 137:52]
  wire  _T_74 = $signed(_T_73) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_75 = io_in_a_bits_address ^ 30'h10043000; // @[Parameters.scala 137:31]
  wire [30:0] _T_76 = {1'b0,$signed(_T_75)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_78 = $signed(_T_76) & -31'sh11000; // @[Parameters.scala 137:52]
  wire  _T_79 = $signed(_T_78) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_80 = io_in_a_bits_address ^ 30'h20000000; // @[Parameters.scala 137:31]
  wire [30:0] _T_81 = {1'b0,$signed(_T_80)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_83 = $signed(_T_81) & -31'sh20000000; // @[Parameters.scala 137:52]
  wire  _T_84 = $signed(_T_83) == 31'sh0; // @[Parameters.scala 137:67]
  wire  _T_90 = _T_49 | _T_54 | _T_59 | _T_64 | _T_69 | _T_74 | _T_79; // @[Parameters.scala 671:42]
  wire  _T_91 = _T_49 | _T_54 | _T_59 | _T_64 | _T_69 | _T_74 | _T_79 | _T_84; // @[Parameters.scala 671:42]
  wire  _T_101 = 3'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_102 = _source_ok_T & _T_101; // @[Mux.scala 27:73]
  wire  _T_160 = _T_102 & _T_91; // @[Monitor.scala 83:78]
  wire  _T_174 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_178 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_179 = _T_178 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_183 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_187 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_332 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_345 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_360 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
  wire  _T_410 = _T_360 & _T_91; // @[Parameters.scala 670:56]
  wire  _T_421 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_425 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_433 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_489 = _T_360 & _T_90; // @[Parameters.scala 670:56]
  wire  _T_499 = source_ok & _T_489; // @[Monitor.scala 115:71]
  wire  _T_517 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_597 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_598 = io_in_a_bits_mask & _T_597; // @[Monitor.scala 127:31]
  wire  _T_599 = _T_598 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_603 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_674 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_682 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_753 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_761 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_832 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_844 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  _T_848 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_852 = io_in_d_bits_size >= 3'h2; // @[Monitor.scala 312:27]
  wire  _T_868 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_896 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_925 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_942 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_960 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [3:0] a_first_beats1_decode = is_aligned_mask[5:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] a_first_counter; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1 = a_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [29:0] address; // @[Monitor.scala 388:22]
  wire  _T_990 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_991 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_995 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_999 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_1003 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_1007 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
  wire [3:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [3:0] d_first_counter; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1 = d_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_1014 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_1015 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_1023 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_1027 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [11:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [3:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1_1 = a_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  reg [3:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_1 = d_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [11:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _GEN_76 = {{4'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_76 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_1041 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_1044 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [34:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [34:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_1046 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_1048 = ~_T_1046[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [34:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_1052 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_1054 = ~_T_848; // @[Monitor.scala 671:74]
  wire  _T_1055 = io_in_d_valid & d_first_1 & ~_T_848; // @[Monitor.scala 671:71]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [3:0] _GEN_22 = _d_first_T & d_first_1 & _T_1054 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_23 = _d_first_T & d_first_1 & _T_1054 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_1041 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_1065 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_1067 = _T_1065[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_1072 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_1073 = io_in_d_bits_opcode == _GEN_32 | _T_1072; // @[Monitor.scala 685:77]
  wire  _T_1077 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_1084 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_1085 = io_in_d_bits_opcode == _GEN_48 | _T_1084; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_1089 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_1099 = _T_1052 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_1054; // @[Monitor.scala 694:116]
  wire  _T_1101 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set = _GEN_16[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_22[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_19[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_23[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [11:0] a_sizes_set = _GEN_20[11:0];
  wire [11:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [11:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_1110 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [2:0] inflight_1; // @[Monitor.scala 723:35]
  reg [11:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [3:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_2 = d_first_counter_2 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 4'h0; // @[Edges.scala 230:25]
  wire [11:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [15:0] _GEN_87 = {{4'd0}, _c_size_lookup_T_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_87 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_1136 = io_in_d_valid & d_first_2 & _T_848; // @[Monitor.scala 779:71]
  wire [3:0] _GEN_67 = _d_first_T & d_first_2 & _T_848 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 783:90 784:21]
  wire [46:0] _GEN_68 = _d_first_T & d_first_2 & _T_848 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 785:21]
  wire [2:0] _T_1144 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_1154 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [2:0] d_clr_1 = _GEN_67[2:0];
  wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [2:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [11:0] d_opcodes_clr_1 = _GEN_68[11:0];
  wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [11:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_1174 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 4'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 4'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 12'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 4'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 4'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 3'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 12'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 4'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_160 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_160) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_174 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_174) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_179 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_179) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_160 & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~_T_160) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_174 & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~_T_174) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_332 & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~_T_332) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_179 & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~_T_179) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_410 & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~_T_410) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_421 & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~_T_421) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_425 & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~_T_425) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_499 & (io_in_a_valid & _T_433 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_433 & ~reset & ~_T_499) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_433 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_433 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_433 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_433 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_421 & (io_in_a_valid & _T_433 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_433 & ~reset & ~_T_421) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_425 & (io_in_a_valid & _T_433 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_433 & ~reset & ~_T_425) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_499 & (io_in_a_valid & _T_517 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_517 & ~reset & ~_T_499) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_517 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_517 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_517 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_517 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_421 & (io_in_a_valid & _T_517 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_517 & ~reset & ~_T_421) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_599 & (io_in_a_valid & _T_517 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_517 & ~reset & ~_T_599) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_603 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_603 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_603 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_603 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_603 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_603 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_674 & (io_in_a_valid & _T_603 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_603 & ~reset & ~_T_674) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_425 & (io_in_a_valid & _T_603 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_603 & ~reset & ~_T_425) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_682 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_682 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_682 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_682 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_682 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_682 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_753 & (io_in_a_valid & _T_682 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_682 & ~reset & ~_T_753) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_425 & (io_in_a_valid & _T_682 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_682 & ~reset & ~_T_425) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_761 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_761 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_761 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_761 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_761 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_761 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_832 & (io_in_a_valid & _T_761 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_761 & ~reset & ~_T_832) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_425 & (io_in_a_valid & _T_761 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_761 & ~reset & ~_T_425) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_761 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_761 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_844 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_844) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_848 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_848 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_852 & (io_in_d_valid & _T_848 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_848 & _T_2 & ~_T_852) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_868 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_868 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_868 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_868 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_852 & (io_in_d_valid & _T_868 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_868 & _T_2 & ~_T_852) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_896 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_896 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_896 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_896 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_852 & (io_in_d_valid & _T_896 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_896 & _T_2 & ~_T_852) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_925 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_925 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_942 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_942 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_960 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_960 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_991 & (_T_990 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_990 & ~reset & ~_T_991) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_995 & (_T_990 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_990 & ~reset & ~_T_995) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_999 & (_T_990 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_990 & ~reset & ~_T_999) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1003 & (_T_990 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_990 & ~reset & ~_T_1003) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1007 & (_T_990 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_990 & ~reset & ~_T_1007) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1015 & (_T_1014 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1014 & _T_2 & ~_T_1015) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1023 & (_T_1014 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1014 & _T_2 & ~_T_1023) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1027 & (_T_1014 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1014 & _T_2 & ~_T_1027) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1048 & (_T_1044 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1044 & ~reset & ~_T_1048) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1067 & (_T_1055 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1055 & _T_2 & ~_T_1067) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1073 & (_T_1055 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1055 & same_cycle_resp & _T_2 & ~_T_1073) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1077 & (_T_1055 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1055 & same_cycle_resp & _T_2 & ~_T_1077) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1085 & (_T_1055 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1055 & ~same_cycle_resp & _T_2 & ~_T_1085) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1089 & (_T_1055 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1055 & ~same_cycle_resp & _T_2 & ~_T_1089) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1101 & (_T_1099 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1099 & _T_2 & ~_T_1101) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1110 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_1110) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1144[0] & (_T_1136 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1136 & _T_2 & ~_T_1144[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1154 & (_T_1136 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1136 & _T_2 & ~_T_1154) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1174 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_1174) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[29:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[2:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[1:0];
  _RAND_10 = {1{`RANDOM}};
  inflight = _RAND_10[2:0];
  _RAND_11 = {1{`RANDOM}};
  inflight_opcodes = _RAND_11[11:0];
  _RAND_12 = {1{`RANDOM}};
  inflight_sizes = _RAND_12[11:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[3:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[3:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  inflight_1 = _RAND_16[2:0];
  _RAND_17 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_17[11:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[3:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLFIFOFixer_1(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [29:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output [31:0] auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [2:0]  auto_out_a_bits_size,
  output [1:0]  auto_out_a_bits_source,
  output [29:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [2:0]  auto_out_d_bits_size,
  input  [1:0]  auto_out_d_bits_source,
  input  [31:0] auto_out_d_bits_data
);
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [29:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  TLMonitor_2 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  assign auto_in_a_ready = auto_out_a_ready; // @[FIFOFixer.scala 88:33]
  assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = auto_in_a_valid; // @[FIFOFixer.scala 87:33]
  assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = auto_out_a_ready; // @[FIFOFixer.scala 88:33]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
endmodule
module TLXbar_1(
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [29:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [1:0]  auto_in_d_bits_param,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output        auto_in_d_bits_sink,
  output        auto_in_d_bits_denied,
  output [31:0] auto_in_d_bits_data,
  output        auto_in_d_bits_corrupt,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [2:0]  auto_out_a_bits_size,
  output [1:0]  auto_out_a_bits_source,
  output [29:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_param,
  input  [2:0]  auto_out_d_bits_size,
  input  [1:0]  auto_out_d_bits_source,
  input         auto_out_d_bits_sink,
  input         auto_out_d_bits_denied,
  input  [31:0] auto_out_d_bits_data,
  input         auto_out_d_bits_corrupt
);
  assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_valid = auto_out_d_valid; // @[ReadyValidCancel.scala 21:38]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Xbar.scala 228:69]
  assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[Xbar.scala 323:53]
  assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = auto_in_a_valid; // @[ReadyValidCancel.scala 21:38]
  assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
  assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module TLMonitor_3(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [29:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [2:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
  wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
  wire [29:0] _GEN_71 = {{24'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [29:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 30'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [29:0] _T_45 = io_in_a_bits_address ^ 30'h10012000; // @[Parameters.scala 137:31]
  wire [30:0] _T_46 = {1'b0,$signed(_T_45)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_48 = $signed(_T_46) & -31'sh2000; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_50 = io_in_a_bits_address ^ 30'h10014000; // @[Parameters.scala 137:31]
  wire [30:0] _T_51 = {1'b0,$signed(_T_50)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_53 = $signed(_T_51) & -31'sh2000; // @[Parameters.scala 137:52]
  wire  _T_54 = $signed(_T_53) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_55 = io_in_a_bits_address ^ 30'h10016000; // @[Parameters.scala 137:31]
  wire [30:0] _T_56 = {1'b0,$signed(_T_55)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_58 = $signed(_T_56) & -31'sh1000; // @[Parameters.scala 137:52]
  wire  _T_59 = $signed(_T_58) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_60 = io_in_a_bits_address ^ 30'h10023000; // @[Parameters.scala 137:31]
  wire [30:0] _T_61 = {1'b0,$signed(_T_60)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_63 = $signed(_T_61) & -31'sh11000; // @[Parameters.scala 137:52]
  wire  _T_64 = $signed(_T_63) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_65 = io_in_a_bits_address ^ 30'h10024000; // @[Parameters.scala 137:31]
  wire [30:0] _T_66 = {1'b0,$signed(_T_65)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_68 = $signed(_T_66) & -31'sh12000; // @[Parameters.scala 137:52]
  wire  _T_69 = $signed(_T_68) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_70 = io_in_a_bits_address ^ 30'h10026000; // @[Parameters.scala 137:31]
  wire [30:0] _T_71 = {1'b0,$signed(_T_70)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_73 = $signed(_T_71) & -31'sh1000; // @[Parameters.scala 137:52]
  wire  _T_74 = $signed(_T_73) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_75 = io_in_a_bits_address ^ 30'h10043000; // @[Parameters.scala 137:31]
  wire [30:0] _T_76 = {1'b0,$signed(_T_75)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_78 = $signed(_T_76) & -31'sh11000; // @[Parameters.scala 137:52]
  wire  _T_79 = $signed(_T_78) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_80 = io_in_a_bits_address ^ 30'h20000000; // @[Parameters.scala 137:31]
  wire [30:0] _T_81 = {1'b0,$signed(_T_80)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_83 = $signed(_T_81) & -31'sh20000000; // @[Parameters.scala 137:52]
  wire  _T_84 = $signed(_T_83) == 31'sh0; // @[Parameters.scala 137:67]
  wire  _T_90 = _T_49 | _T_54 | _T_59 | _T_64 | _T_69 | _T_74 | _T_79; // @[Parameters.scala 671:42]
  wire  _T_91 = _T_49 | _T_54 | _T_59 | _T_64 | _T_69 | _T_74 | _T_79 | _T_84; // @[Parameters.scala 671:42]
  wire  _T_101 = 3'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_102 = _source_ok_T & _T_101; // @[Mux.scala 27:73]
  wire  _T_160 = _T_102 & _T_91; // @[Monitor.scala 83:78]
  wire  _T_174 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_178 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_179 = _T_178 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_183 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_187 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_332 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_345 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_360 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
  wire  _T_410 = _T_360 & _T_91; // @[Parameters.scala 670:56]
  wire  _T_421 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_425 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_433 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_489 = _T_360 & _T_90; // @[Parameters.scala 670:56]
  wire  _T_499 = source_ok & _T_489; // @[Monitor.scala 115:71]
  wire  _T_517 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_597 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_598 = io_in_a_bits_mask & _T_597; // @[Monitor.scala 127:31]
  wire  _T_599 = _T_598 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_603 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_674 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_682 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_753 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_761 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_832 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_844 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  _T_848 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_852 = io_in_d_bits_size >= 3'h2; // @[Monitor.scala 312:27]
  wire  _T_868 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_896 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_925 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_942 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_960 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [3:0] a_first_beats1_decode = is_aligned_mask[5:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] a_first_counter; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1 = a_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [29:0] address; // @[Monitor.scala 388:22]
  wire  _T_990 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_991 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_995 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_999 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_1003 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_1007 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
  wire [3:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [3:0] d_first_counter; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1 = d_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_1014 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_1015 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_1023 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_1027 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [11:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [3:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1_1 = a_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  reg [3:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_1 = d_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [11:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _GEN_76 = {{4'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_76 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_1041 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_1044 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [34:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [34:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_1046 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_1048 = ~_T_1046[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [34:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_1052 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_1054 = ~_T_848; // @[Monitor.scala 671:74]
  wire  _T_1055 = io_in_d_valid & d_first_1 & ~_T_848; // @[Monitor.scala 671:71]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [3:0] _GEN_22 = _d_first_T & d_first_1 & _T_1054 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_23 = _d_first_T & d_first_1 & _T_1054 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_1041 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_1065 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_1067 = _T_1065[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_1072 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_1073 = io_in_d_bits_opcode == _GEN_32 | _T_1072; // @[Monitor.scala 685:77]
  wire  _T_1077 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_1084 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_1085 = io_in_d_bits_opcode == _GEN_48 | _T_1084; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_1089 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_1099 = _T_1052 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_1054; // @[Monitor.scala 694:116]
  wire  _T_1101 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set = _GEN_16[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_22[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_19[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_23[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [11:0] a_sizes_set = _GEN_20[11:0];
  wire [11:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [11:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_1110 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [2:0] inflight_1; // @[Monitor.scala 723:35]
  reg [11:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [3:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_2 = d_first_counter_2 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 4'h0; // @[Edges.scala 230:25]
  wire [11:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [15:0] _GEN_87 = {{4'd0}, _c_size_lookup_T_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_87 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_1136 = io_in_d_valid & d_first_2 & _T_848; // @[Monitor.scala 779:71]
  wire [3:0] _GEN_67 = _d_first_T & d_first_2 & _T_848 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 783:90 784:21]
  wire [46:0] _GEN_68 = _d_first_T & d_first_2 & _T_848 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 785:21]
  wire [2:0] _T_1144 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_1154 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [2:0] d_clr_1 = _GEN_67[2:0];
  wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [2:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [11:0] d_opcodes_clr_1 = _GEN_68[11:0];
  wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [11:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_1174 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 4'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 4'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 12'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 4'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 4'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 3'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 12'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 4'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_160 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_160) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_174 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_174) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_179 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_179) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_160 & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~_T_160) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_174 & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~_T_174) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_332 & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~_T_332) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_179 & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~_T_179) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_410 & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~_T_410) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_421 & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~_T_421) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_425 & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~_T_425) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_499 & (io_in_a_valid & _T_433 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_433 & ~reset & ~_T_499) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_433 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_433 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_433 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_433 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_421 & (io_in_a_valid & _T_433 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_433 & ~reset & ~_T_421) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_425 & (io_in_a_valid & _T_433 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_433 & ~reset & ~_T_425) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_499 & (io_in_a_valid & _T_517 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_517 & ~reset & ~_T_499) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_517 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_517 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_517 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_517 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_421 & (io_in_a_valid & _T_517 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_517 & ~reset & ~_T_421) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_599 & (io_in_a_valid & _T_517 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_517 & ~reset & ~_T_599) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_603 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_603 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_603 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_603 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_603 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_603 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_674 & (io_in_a_valid & _T_603 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_603 & ~reset & ~_T_674) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_425 & (io_in_a_valid & _T_603 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_603 & ~reset & ~_T_425) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_682 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_682 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_682 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_682 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_682 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_682 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_753 & (io_in_a_valid & _T_682 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_682 & ~reset & ~_T_753) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_425 & (io_in_a_valid & _T_682 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_682 & ~reset & ~_T_425) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_761 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_761 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_761 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_761 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_761 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_761 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_832 & (io_in_a_valid & _T_761 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_761 & ~reset & ~_T_832) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_425 & (io_in_a_valid & _T_761 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_761 & ~reset & ~_T_425) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_761 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_761 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_844 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_844) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_848 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_848 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_852 & (io_in_d_valid & _T_848 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_848 & _T_2 & ~_T_852) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_868 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_868 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_868 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_868 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_852 & (io_in_d_valid & _T_868 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_868 & _T_2 & ~_T_852) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_896 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_896 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_896 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_896 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_852 & (io_in_d_valid & _T_896 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_896 & _T_2 & ~_T_852) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_925 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_925 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_942 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_942 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_960 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_960 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_991 & (_T_990 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_990 & ~reset & ~_T_991) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_995 & (_T_990 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_990 & ~reset & ~_T_995) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_999 & (_T_990 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_990 & ~reset & ~_T_999) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1003 & (_T_990 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_990 & ~reset & ~_T_1003) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1007 & (_T_990 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_990 & ~reset & ~_T_1007) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1015 & (_T_1014 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1014 & _T_2 & ~_T_1015) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1023 & (_T_1014 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1014 & _T_2 & ~_T_1023) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1027 & (_T_1014 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1014 & _T_2 & ~_T_1027) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1048 & (_T_1044 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1044 & ~reset & ~_T_1048) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1067 & (_T_1055 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1055 & _T_2 & ~_T_1067) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1073 & (_T_1055 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1055 & same_cycle_resp & _T_2 & ~_T_1073) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1077 & (_T_1055 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1055 & same_cycle_resp & _T_2 & ~_T_1077) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1085 & (_T_1055 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1055 & ~same_cycle_resp & _T_2 & ~_T_1085) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1089 & (_T_1055 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1055 & ~same_cycle_resp & _T_2 & ~_T_1089) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1101 & (_T_1099 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1099 & _T_2 & ~_T_1101) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1110 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_1110) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1144[0] & (_T_1136 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1136 & _T_2 & ~_T_1144[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1154 & (_T_1136 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1136 & _T_2 & ~_T_1154) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1174 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_1174) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[29:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[2:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[1:0];
  _RAND_10 = {1{`RANDOM}};
  inflight = _RAND_10[2:0];
  _RAND_11 = {1{`RANDOM}};
  inflight_opcodes = _RAND_11[11:0];
  _RAND_12 = {1{`RANDOM}};
  inflight_sizes = _RAND_12[11:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[3:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[3:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  inflight_1 = _RAND_16[2:0];
  _RAND_17 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_17[11:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[3:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLXbar_2(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [29:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output [31:0] auto_in_d_bits_data,
  input         auto_out_14_a_ready,
  output        auto_out_14_a_valid,
  output [2:0]  auto_out_14_a_bits_opcode,
  output [2:0]  auto_out_14_a_bits_param,
  output [2:0]  auto_out_14_a_bits_size,
  output [1:0]  auto_out_14_a_bits_source,
  output [28:0] auto_out_14_a_bits_address,
  output [3:0]  auto_out_14_a_bits_mask,
  output [31:0] auto_out_14_a_bits_data,
  output        auto_out_14_a_bits_corrupt,
  output        auto_out_14_d_ready,
  input         auto_out_14_d_valid,
  input  [2:0]  auto_out_14_d_bits_opcode,
  input  [2:0]  auto_out_14_d_bits_size,
  input  [1:0]  auto_out_14_d_bits_source,
  input  [31:0] auto_out_14_d_bits_data,
  input         auto_out_13_a_ready,
  output        auto_out_13_a_valid,
  output [2:0]  auto_out_13_a_bits_opcode,
  output [2:0]  auto_out_13_a_bits_param,
  output [2:0]  auto_out_13_a_bits_size,
  output [1:0]  auto_out_13_a_bits_source,
  output [28:0] auto_out_13_a_bits_address,
  output [3:0]  auto_out_13_a_bits_mask,
  output [31:0] auto_out_13_a_bits_data,
  output        auto_out_13_a_bits_corrupt,
  output        auto_out_13_d_ready,
  input         auto_out_13_d_valid,
  input  [2:0]  auto_out_13_d_bits_opcode,
  input  [2:0]  auto_out_13_d_bits_size,
  input  [1:0]  auto_out_13_d_bits_source,
  input  [31:0] auto_out_13_d_bits_data,
  input         auto_out_12_a_ready,
  output        auto_out_12_a_valid,
  output [2:0]  auto_out_12_a_bits_opcode,
  output [2:0]  auto_out_12_a_bits_param,
  output [2:0]  auto_out_12_a_bits_size,
  output [1:0]  auto_out_12_a_bits_source,
  output [28:0] auto_out_12_a_bits_address,
  output [3:0]  auto_out_12_a_bits_mask,
  output [31:0] auto_out_12_a_bits_data,
  output        auto_out_12_a_bits_corrupt,
  output        auto_out_12_d_ready,
  input         auto_out_12_d_valid,
  input  [2:0]  auto_out_12_d_bits_opcode,
  input  [2:0]  auto_out_12_d_bits_size,
  input  [1:0]  auto_out_12_d_bits_source,
  input  [31:0] auto_out_12_d_bits_data,
  input         auto_out_11_a_ready,
  output        auto_out_11_a_valid,
  output [2:0]  auto_out_11_a_bits_opcode,
  output [2:0]  auto_out_11_a_bits_param,
  output [2:0]  auto_out_11_a_bits_size,
  output [1:0]  auto_out_11_a_bits_source,
  output [28:0] auto_out_11_a_bits_address,
  output [3:0]  auto_out_11_a_bits_mask,
  output [31:0] auto_out_11_a_bits_data,
  output        auto_out_11_a_bits_corrupt,
  output        auto_out_11_d_ready,
  input         auto_out_11_d_valid,
  input  [2:0]  auto_out_11_d_bits_opcode,
  input  [2:0]  auto_out_11_d_bits_size,
  input  [1:0]  auto_out_11_d_bits_source,
  input  [31:0] auto_out_11_d_bits_data,
  input         auto_out_10_a_ready,
  output        auto_out_10_a_valid,
  output [2:0]  auto_out_10_a_bits_opcode,
  output [2:0]  auto_out_10_a_bits_param,
  output [2:0]  auto_out_10_a_bits_size,
  output [1:0]  auto_out_10_a_bits_source,
  output [28:0] auto_out_10_a_bits_address,
  output [3:0]  auto_out_10_a_bits_mask,
  output [31:0] auto_out_10_a_bits_data,
  output        auto_out_10_a_bits_corrupt,
  output        auto_out_10_d_ready,
  input         auto_out_10_d_valid,
  input  [2:0]  auto_out_10_d_bits_opcode,
  input  [2:0]  auto_out_10_d_bits_size,
  input  [1:0]  auto_out_10_d_bits_source,
  input  [31:0] auto_out_10_d_bits_data,
  input         auto_out_9_a_ready,
  output        auto_out_9_a_valid,
  output [2:0]  auto_out_9_a_bits_opcode,
  output [2:0]  auto_out_9_a_bits_param,
  output [2:0]  auto_out_9_a_bits_size,
  output [1:0]  auto_out_9_a_bits_source,
  output [28:0] auto_out_9_a_bits_address,
  output [3:0]  auto_out_9_a_bits_mask,
  output [31:0] auto_out_9_a_bits_data,
  output        auto_out_9_a_bits_corrupt,
  output        auto_out_9_d_ready,
  input         auto_out_9_d_valid,
  input  [2:0]  auto_out_9_d_bits_opcode,
  input  [2:0]  auto_out_9_d_bits_size,
  input  [1:0]  auto_out_9_d_bits_source,
  input  [31:0] auto_out_9_d_bits_data,
  input         auto_out_8_a_ready,
  output        auto_out_8_a_valid,
  output [2:0]  auto_out_8_a_bits_opcode,
  output [2:0]  auto_out_8_a_bits_param,
  output [2:0]  auto_out_8_a_bits_size,
  output [1:0]  auto_out_8_a_bits_source,
  output [28:0] auto_out_8_a_bits_address,
  output [3:0]  auto_out_8_a_bits_mask,
  output [31:0] auto_out_8_a_bits_data,
  output        auto_out_8_a_bits_corrupt,
  output        auto_out_8_d_ready,
  input         auto_out_8_d_valid,
  input  [2:0]  auto_out_8_d_bits_opcode,
  input  [2:0]  auto_out_8_d_bits_size,
  input  [1:0]  auto_out_8_d_bits_source,
  input  [31:0] auto_out_8_d_bits_data,
  input         auto_out_7_a_ready,
  output        auto_out_7_a_valid,
  output [2:0]  auto_out_7_a_bits_opcode,
  output [2:0]  auto_out_7_a_bits_param,
  output [2:0]  auto_out_7_a_bits_size,
  output [1:0]  auto_out_7_a_bits_source,
  output [28:0] auto_out_7_a_bits_address,
  output [3:0]  auto_out_7_a_bits_mask,
  output [31:0] auto_out_7_a_bits_data,
  output        auto_out_7_a_bits_corrupt,
  output        auto_out_7_d_ready,
  input         auto_out_7_d_valid,
  input  [2:0]  auto_out_7_d_bits_opcode,
  input  [2:0]  auto_out_7_d_bits_size,
  input  [1:0]  auto_out_7_d_bits_source,
  input  [31:0] auto_out_7_d_bits_data,
  input         auto_out_6_a_ready,
  output        auto_out_6_a_valid,
  output [2:0]  auto_out_6_a_bits_opcode,
  output [2:0]  auto_out_6_a_bits_param,
  output [2:0]  auto_out_6_a_bits_size,
  output [1:0]  auto_out_6_a_bits_source,
  output [29:0] auto_out_6_a_bits_address,
  output [3:0]  auto_out_6_a_bits_mask,
  output        auto_out_6_a_bits_corrupt,
  output        auto_out_6_d_ready,
  input         auto_out_6_d_valid,
  input  [2:0]  auto_out_6_d_bits_size,
  input  [1:0]  auto_out_6_d_bits_source,
  input  [31:0] auto_out_6_d_bits_data,
  input         auto_out_5_a_ready,
  output        auto_out_5_a_valid,
  output [2:0]  auto_out_5_a_bits_opcode,
  output [2:0]  auto_out_5_a_bits_param,
  output [2:0]  auto_out_5_a_bits_size,
  output [1:0]  auto_out_5_a_bits_source,
  output [28:0] auto_out_5_a_bits_address,
  output [3:0]  auto_out_5_a_bits_mask,
  output [31:0] auto_out_5_a_bits_data,
  output        auto_out_5_a_bits_corrupt,
  output        auto_out_5_d_ready,
  input         auto_out_5_d_valid,
  input  [2:0]  auto_out_5_d_bits_opcode,
  input  [2:0]  auto_out_5_d_bits_size,
  input  [1:0]  auto_out_5_d_bits_source,
  input  [31:0] auto_out_5_d_bits_data,
  input         auto_out_4_a_ready,
  output        auto_out_4_a_valid,
  output [2:0]  auto_out_4_a_bits_opcode,
  output [2:0]  auto_out_4_a_bits_param,
  output [2:0]  auto_out_4_a_bits_size,
  output [1:0]  auto_out_4_a_bits_source,
  output [28:0] auto_out_4_a_bits_address,
  output [3:0]  auto_out_4_a_bits_mask,
  output [31:0] auto_out_4_a_bits_data,
  output        auto_out_4_a_bits_corrupt,
  output        auto_out_4_d_ready,
  input         auto_out_4_d_valid,
  input  [2:0]  auto_out_4_d_bits_opcode,
  input  [2:0]  auto_out_4_d_bits_size,
  input  [1:0]  auto_out_4_d_bits_source,
  input  [31:0] auto_out_4_d_bits_data,
  input         auto_out_3_a_ready,
  output        auto_out_3_a_valid,
  output [2:0]  auto_out_3_a_bits_opcode,
  output [2:0]  auto_out_3_a_bits_param,
  output [2:0]  auto_out_3_a_bits_size,
  output [1:0]  auto_out_3_a_bits_source,
  output [28:0] auto_out_3_a_bits_address,
  output [3:0]  auto_out_3_a_bits_mask,
  output [31:0] auto_out_3_a_bits_data,
  output        auto_out_3_a_bits_corrupt,
  output        auto_out_3_d_ready,
  input         auto_out_3_d_valid,
  input  [2:0]  auto_out_3_d_bits_opcode,
  input  [2:0]  auto_out_3_d_bits_size,
  input  [1:0]  auto_out_3_d_bits_source,
  input  [31:0] auto_out_3_d_bits_data,
  input         auto_out_2_a_ready,
  output        auto_out_2_a_valid,
  output [2:0]  auto_out_2_a_bits_opcode,
  output [2:0]  auto_out_2_a_bits_param,
  output [2:0]  auto_out_2_a_bits_size,
  output [1:0]  auto_out_2_a_bits_source,
  output [28:0] auto_out_2_a_bits_address,
  output [3:0]  auto_out_2_a_bits_mask,
  output [31:0] auto_out_2_a_bits_data,
  output        auto_out_2_a_bits_corrupt,
  output        auto_out_2_d_ready,
  input         auto_out_2_d_valid,
  input  [2:0]  auto_out_2_d_bits_opcode,
  input  [2:0]  auto_out_2_d_bits_size,
  input  [1:0]  auto_out_2_d_bits_source,
  input  [31:0] auto_out_2_d_bits_data,
  input         auto_out_1_a_ready,
  output        auto_out_1_a_valid,
  output [2:0]  auto_out_1_a_bits_opcode,
  output [2:0]  auto_out_1_a_bits_param,
  output [2:0]  auto_out_1_a_bits_size,
  output [1:0]  auto_out_1_a_bits_source,
  output [28:0] auto_out_1_a_bits_address,
  output [3:0]  auto_out_1_a_bits_mask,
  output [31:0] auto_out_1_a_bits_data,
  output        auto_out_1_a_bits_corrupt,
  output        auto_out_1_d_ready,
  input         auto_out_1_d_valid,
  input  [2:0]  auto_out_1_d_bits_opcode,
  input  [2:0]  auto_out_1_d_bits_size,
  input  [1:0]  auto_out_1_d_bits_source,
  input  [31:0] auto_out_1_d_bits_data,
  input         auto_out_0_a_ready,
  output        auto_out_0_a_valid,
  output [2:0]  auto_out_0_a_bits_opcode,
  output [2:0]  auto_out_0_a_bits_param,
  output [2:0]  auto_out_0_a_bits_size,
  output [1:0]  auto_out_0_a_bits_source,
  output [28:0] auto_out_0_a_bits_address,
  output [3:0]  auto_out_0_a_bits_mask,
  output [31:0] auto_out_0_a_bits_data,
  output        auto_out_0_a_bits_corrupt,
  output        auto_out_0_d_ready,
  input         auto_out_0_d_valid,
  input  [2:0]  auto_out_0_d_bits_opcode,
  input  [2:0]  auto_out_0_d_bits_size,
  input  [1:0]  auto_out_0_d_bits_source,
  input  [31:0] auto_out_0_d_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [29:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  reg [3:0] beatsLeft; // @[Arbiter.scala 87:30]
  wire  idle = beatsLeft == 4'h0; // @[Arbiter.scala 88:28]
  wire [6:0] readys_lo = {auto_out_6_d_valid,auto_out_5_d_valid,auto_out_4_d_valid,auto_out_3_d_valid,auto_out_2_d_valid
    ,auto_out_1_d_valid,auto_out_0_d_valid}; // @[Cat.scala 31:58]
  wire [14:0] readys_valid = {auto_out_14_d_valid,auto_out_13_d_valid,auto_out_12_d_valid,auto_out_11_d_valid,
    auto_out_10_d_valid,auto_out_9_d_valid,auto_out_8_d_valid,auto_out_7_d_valid,readys_lo}; // @[Cat.scala 31:58]
  reg [14:0] readys_mask; // @[Arbiter.scala 23:23]
  wire [14:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala 24:30]
  wire [14:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala 24:28]
  wire [29:0] readys_filter = {_readys_filter_T_1,auto_out_14_d_valid,auto_out_13_d_valid,auto_out_12_d_valid,
    auto_out_11_d_valid,auto_out_10_d_valid,auto_out_9_d_valid,auto_out_8_d_valid,auto_out_7_d_valid,readys_lo}; // @[Cat.scala 31:58]
  wire [29:0] _GEN_1 = {{1'd0}, readys_filter[29:1]}; // @[package.scala 253:43]
  wire [29:0] _readys_unready_T_1 = readys_filter | _GEN_1; // @[package.scala 253:43]
  wire [29:0] _GEN_2 = {{2'd0}, _readys_unready_T_1[29:2]}; // @[package.scala 253:43]
  wire [29:0] _readys_unready_T_3 = _readys_unready_T_1 | _GEN_2; // @[package.scala 253:43]
  wire [29:0] _GEN_3 = {{4'd0}, _readys_unready_T_3[29:4]}; // @[package.scala 253:43]
  wire [29:0] _readys_unready_T_5 = _readys_unready_T_3 | _GEN_3; // @[package.scala 253:43]
  wire [29:0] _GEN_4 = {{8'd0}, _readys_unready_T_5[29:8]}; // @[package.scala 253:43]
  wire [29:0] _readys_unready_T_7 = _readys_unready_T_5 | _GEN_4; // @[package.scala 253:43]
  wire [29:0] _readys_unready_T_10 = {readys_mask, 15'h0}; // @[Arbiter.scala 25:66]
  wire [29:0] _GEN_5 = {{1'd0}, _readys_unready_T_7[29:1]}; // @[Arbiter.scala 25:58]
  wire [29:0] readys_unready = _GEN_5 | _readys_unready_T_10; // @[Arbiter.scala 25:58]
  wire [14:0] _readys_readys_T_2 = readys_unready[29:15] & readys_unready[14:0]; // @[Arbiter.scala 26:39]
  wire [14:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala 26:18]
  wire  readys_0 = readys_readys[0]; // @[Arbiter.scala 95:86]
  wire  earlyWinner_0 = readys_0 & auto_out_0_d_valid; // @[Arbiter.scala 97:79]
  reg  state_0; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_0 = idle ? earlyWinner_0 : state_0; // @[Arbiter.scala 117:30]
  wire [1:0] _T_244 = muxStateEarly_0 ? auto_out_0_d_bits_source : 2'h0; // @[Mux.scala 27:73]
  wire  readys_1 = readys_readys[1]; // @[Arbiter.scala 95:86]
  wire  earlyWinner_1 = readys_1 & auto_out_1_d_valid; // @[Arbiter.scala 97:79]
  reg  state_1; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_1 = idle ? earlyWinner_1 : state_1; // @[Arbiter.scala 117:30]
  wire [1:0] _T_245 = muxStateEarly_1 ? auto_out_1_d_bits_source : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_259 = _T_244 | _T_245; // @[Mux.scala 27:73]
  wire  readys_2 = readys_readys[2]; // @[Arbiter.scala 95:86]
  wire  earlyWinner_2 = readys_2 & auto_out_2_d_valid; // @[Arbiter.scala 97:79]
  reg  state_2; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_2 = idle ? earlyWinner_2 : state_2; // @[Arbiter.scala 117:30]
  wire [1:0] _T_246 = muxStateEarly_2 ? auto_out_2_d_bits_source : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_260 = _T_259 | _T_246; // @[Mux.scala 27:73]
  wire  readys_3 = readys_readys[3]; // @[Arbiter.scala 95:86]
  wire  earlyWinner_3 = readys_3 & auto_out_3_d_valid; // @[Arbiter.scala 97:79]
  reg  state_3; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_3 = idle ? earlyWinner_3 : state_3; // @[Arbiter.scala 117:30]
  wire [1:0] _T_247 = muxStateEarly_3 ? auto_out_3_d_bits_source : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_261 = _T_260 | _T_247; // @[Mux.scala 27:73]
  wire  readys_4 = readys_readys[4]; // @[Arbiter.scala 95:86]
  wire  earlyWinner_4 = readys_4 & auto_out_4_d_valid; // @[Arbiter.scala 97:79]
  reg  state_4; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_4 = idle ? earlyWinner_4 : state_4; // @[Arbiter.scala 117:30]
  wire [1:0] _T_248 = muxStateEarly_4 ? auto_out_4_d_bits_source : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_262 = _T_261 | _T_248; // @[Mux.scala 27:73]
  wire  readys_5 = readys_readys[5]; // @[Arbiter.scala 95:86]
  wire  earlyWinner_5 = readys_5 & auto_out_5_d_valid; // @[Arbiter.scala 97:79]
  reg  state_5; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_5 = idle ? earlyWinner_5 : state_5; // @[Arbiter.scala 117:30]
  wire [1:0] _T_249 = muxStateEarly_5 ? auto_out_5_d_bits_source : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_263 = _T_262 | _T_249; // @[Mux.scala 27:73]
  wire  readys_6 = readys_readys[6]; // @[Arbiter.scala 95:86]
  wire  earlyWinner_6 = readys_6 & auto_out_6_d_valid; // @[Arbiter.scala 97:79]
  reg  state_6; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_6 = idle ? earlyWinner_6 : state_6; // @[Arbiter.scala 117:30]
  wire [1:0] _T_250 = muxStateEarly_6 ? auto_out_6_d_bits_source : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_264 = _T_263 | _T_250; // @[Mux.scala 27:73]
  wire  readys_7 = readys_readys[7]; // @[Arbiter.scala 95:86]
  wire  earlyWinner_7 = readys_7 & auto_out_7_d_valid; // @[Arbiter.scala 97:79]
  reg  state_7; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_7 = idle ? earlyWinner_7 : state_7; // @[Arbiter.scala 117:30]
  wire [1:0] _T_251 = muxStateEarly_7 ? auto_out_7_d_bits_source : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_265 = _T_264 | _T_251; // @[Mux.scala 27:73]
  wire  readys_8 = readys_readys[8]; // @[Arbiter.scala 95:86]
  wire  earlyWinner_8 = readys_8 & auto_out_8_d_valid; // @[Arbiter.scala 97:79]
  reg  state_8; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_8 = idle ? earlyWinner_8 : state_8; // @[Arbiter.scala 117:30]
  wire [1:0] _T_252 = muxStateEarly_8 ? auto_out_8_d_bits_source : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_266 = _T_265 | _T_252; // @[Mux.scala 27:73]
  wire  readys_9 = readys_readys[9]; // @[Arbiter.scala 95:86]
  wire  earlyWinner_9 = readys_9 & auto_out_9_d_valid; // @[Arbiter.scala 97:79]
  reg  state_9; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_9 = idle ? earlyWinner_9 : state_9; // @[Arbiter.scala 117:30]
  wire [1:0] _T_253 = muxStateEarly_9 ? auto_out_9_d_bits_source : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_267 = _T_266 | _T_253; // @[Mux.scala 27:73]
  wire  readys_10 = readys_readys[10]; // @[Arbiter.scala 95:86]
  wire  earlyWinner_10 = readys_10 & auto_out_10_d_valid; // @[Arbiter.scala 97:79]
  reg  state_10; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_10 = idle ? earlyWinner_10 : state_10; // @[Arbiter.scala 117:30]
  wire [1:0] _T_254 = muxStateEarly_10 ? auto_out_10_d_bits_source : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_268 = _T_267 | _T_254; // @[Mux.scala 27:73]
  wire  readys_11 = readys_readys[11]; // @[Arbiter.scala 95:86]
  wire  earlyWinner_11 = readys_11 & auto_out_11_d_valid; // @[Arbiter.scala 97:79]
  reg  state_11; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_11 = idle ? earlyWinner_11 : state_11; // @[Arbiter.scala 117:30]
  wire [1:0] _T_255 = muxStateEarly_11 ? auto_out_11_d_bits_source : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_269 = _T_268 | _T_255; // @[Mux.scala 27:73]
  wire  readys_12 = readys_readys[12]; // @[Arbiter.scala 95:86]
  wire  earlyWinner_12 = readys_12 & auto_out_12_d_valid; // @[Arbiter.scala 97:79]
  reg  state_12; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_12 = idle ? earlyWinner_12 : state_12; // @[Arbiter.scala 117:30]
  wire [1:0] _T_256 = muxStateEarly_12 ? auto_out_12_d_bits_source : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_270 = _T_269 | _T_256; // @[Mux.scala 27:73]
  wire  readys_13 = readys_readys[13]; // @[Arbiter.scala 95:86]
  wire  earlyWinner_13 = readys_13 & auto_out_13_d_valid; // @[Arbiter.scala 97:79]
  reg  state_13; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_13 = idle ? earlyWinner_13 : state_13; // @[Arbiter.scala 117:30]
  wire [1:0] _T_257 = muxStateEarly_13 ? auto_out_13_d_bits_source : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_271 = _T_270 | _T_257; // @[Mux.scala 27:73]
  wire  readys_14 = readys_readys[14]; // @[Arbiter.scala 95:86]
  wire  earlyWinner_14 = readys_14 & auto_out_14_d_valid; // @[Arbiter.scala 97:79]
  reg  state_14; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_14 = idle ? earlyWinner_14 : state_14; // @[Arbiter.scala 117:30]
  wire [1:0] _T_258 = muxStateEarly_14 ? auto_out_14_d_bits_source : 2'h0; // @[Mux.scala 27:73]
  wire [29:0] _requestAIO_T = auto_in_a_bits_address ^ 30'h13000; // @[Parameters.scala 137:31]
  wire [30:0] _requestAIO_T_1 = {1'b0,$signed(_requestAIO_T)}; // @[Parameters.scala 137:49]
  wire [30:0] _requestAIO_T_3 = $signed(_requestAIO_T_1) & 31'sh20077000; // @[Parameters.scala 137:52]
  wire  requestAIO_0_0 = $signed(_requestAIO_T_3) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _requestAIO_T_5 = auto_in_a_bits_address ^ 30'h23000; // @[Parameters.scala 137:31]
  wire [30:0] _requestAIO_T_6 = {1'b0,$signed(_requestAIO_T_5)}; // @[Parameters.scala 137:49]
  wire [30:0] _requestAIO_T_8 = $signed(_requestAIO_T_6) & 31'sh20077000; // @[Parameters.scala 137:52]
  wire  requestAIO_0_1 = $signed(_requestAIO_T_8) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _requestAIO_T_10 = auto_in_a_bits_address ^ 30'h33000; // @[Parameters.scala 137:31]
  wire [30:0] _requestAIO_T_11 = {1'b0,$signed(_requestAIO_T_10)}; // @[Parameters.scala 137:49]
  wire [30:0] _requestAIO_T_13 = $signed(_requestAIO_T_11) & 31'sh20077000; // @[Parameters.scala 137:52]
  wire  requestAIO_0_2 = $signed(_requestAIO_T_13) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _requestAIO_T_15 = auto_in_a_bits_address ^ 30'h43000; // @[Parameters.scala 137:31]
  wire [30:0] _requestAIO_T_16 = {1'b0,$signed(_requestAIO_T_15)}; // @[Parameters.scala 137:49]
  wire [30:0] _requestAIO_T_18 = $signed(_requestAIO_T_16) & 31'sh20077000; // @[Parameters.scala 137:52]
  wire  requestAIO_0_3 = $signed(_requestAIO_T_18) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _requestAIO_T_20 = auto_in_a_bits_address ^ 30'h53000; // @[Parameters.scala 137:31]
  wire [30:0] _requestAIO_T_21 = {1'b0,$signed(_requestAIO_T_20)}; // @[Parameters.scala 137:49]
  wire [30:0] _requestAIO_T_23 = $signed(_requestAIO_T_21) & 31'sh20077000; // @[Parameters.scala 137:52]
  wire  requestAIO_0_4 = $signed(_requestAIO_T_23) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _requestAIO_T_25 = auto_in_a_bits_address ^ 30'h14000; // @[Parameters.scala 137:31]
  wire [30:0] _requestAIO_T_26 = {1'b0,$signed(_requestAIO_T_25)}; // @[Parameters.scala 137:49]
  wire [30:0] _requestAIO_T_28 = $signed(_requestAIO_T_26) & 31'sh20077000; // @[Parameters.scala 137:52]
  wire  requestAIO_0_5 = $signed(_requestAIO_T_28) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _requestAIO_T_30 = auto_in_a_bits_address ^ 30'h20000000; // @[Parameters.scala 137:31]
  wire [30:0] _requestAIO_T_31 = {1'b0,$signed(_requestAIO_T_30)}; // @[Parameters.scala 137:49]
  wire [30:0] _requestAIO_T_33 = $signed(_requestAIO_T_31) & 31'sh20000000; // @[Parameters.scala 137:52]
  wire  requestAIO_0_6 = $signed(_requestAIO_T_33) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _requestAIO_T_35 = auto_in_a_bits_address ^ 30'h34000; // @[Parameters.scala 137:31]
  wire [30:0] _requestAIO_T_36 = {1'b0,$signed(_requestAIO_T_35)}; // @[Parameters.scala 137:49]
  wire [30:0] _requestAIO_T_38 = $signed(_requestAIO_T_36) & 31'sh20077000; // @[Parameters.scala 137:52]
  wire  requestAIO_0_7 = $signed(_requestAIO_T_38) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _requestAIO_T_40 = auto_in_a_bits_address ^ 30'h24000; // @[Parameters.scala 137:31]
  wire [30:0] _requestAIO_T_41 = {1'b0,$signed(_requestAIO_T_40)}; // @[Parameters.scala 137:49]
  wire [30:0] _requestAIO_T_43 = $signed(_requestAIO_T_41) & 31'sh20077000; // @[Parameters.scala 137:52]
  wire  requestAIO_0_8 = $signed(_requestAIO_T_43) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _requestAIO_T_45 = auto_in_a_bits_address ^ 30'h12000; // @[Parameters.scala 137:31]
  wire [30:0] _requestAIO_T_46 = {1'b0,$signed(_requestAIO_T_45)}; // @[Parameters.scala 137:49]
  wire [30:0] _requestAIO_T_48 = $signed(_requestAIO_T_46) & 31'sh20077000; // @[Parameters.scala 137:52]
  wire  requestAIO_0_9 = $signed(_requestAIO_T_48) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _requestAIO_T_50 = auto_in_a_bits_address ^ 30'h15000; // @[Parameters.scala 137:31]
  wire [30:0] _requestAIO_T_51 = {1'b0,$signed(_requestAIO_T_50)}; // @[Parameters.scala 137:49]
  wire [30:0] _requestAIO_T_53 = $signed(_requestAIO_T_51) & 31'sh20077000; // @[Parameters.scala 137:52]
  wire  requestAIO_0_10 = $signed(_requestAIO_T_53) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _requestAIO_T_55 = auto_in_a_bits_address ^ 30'h25000; // @[Parameters.scala 137:31]
  wire [30:0] _requestAIO_T_56 = {1'b0,$signed(_requestAIO_T_55)}; // @[Parameters.scala 137:49]
  wire [30:0] _requestAIO_T_58 = $signed(_requestAIO_T_56) & 31'sh20077000; // @[Parameters.scala 137:52]
  wire  requestAIO_0_11 = $signed(_requestAIO_T_58) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _requestAIO_T_60 = auto_in_a_bits_address ^ 30'h35000; // @[Parameters.scala 137:31]
  wire [30:0] _requestAIO_T_61 = {1'b0,$signed(_requestAIO_T_60)}; // @[Parameters.scala 137:49]
  wire [30:0] _requestAIO_T_63 = $signed(_requestAIO_T_61) & 31'sh20077000; // @[Parameters.scala 137:52]
  wire  requestAIO_0_12 = $signed(_requestAIO_T_63) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _requestAIO_T_65 = auto_in_a_bits_address ^ 30'h16000; // @[Parameters.scala 137:31]
  wire [30:0] _requestAIO_T_66 = {1'b0,$signed(_requestAIO_T_65)}; // @[Parameters.scala 137:49]
  wire [30:0] _requestAIO_T_68 = $signed(_requestAIO_T_66) & 31'sh20077000; // @[Parameters.scala 137:52]
  wire  requestAIO_0_13 = $signed(_requestAIO_T_68) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _requestAIO_T_70 = auto_in_a_bits_address ^ 30'h26000; // @[Parameters.scala 137:31]
  wire [30:0] _requestAIO_T_71 = {1'b0,$signed(_requestAIO_T_70)}; // @[Parameters.scala 137:49]
  wire [30:0] _requestAIO_T_73 = $signed(_requestAIO_T_71) & 31'sh20077000; // @[Parameters.scala 137:52]
  wire  requestAIO_0_14 = $signed(_requestAIO_T_73) == 31'sh0; // @[Parameters.scala 137:67]
  wire [12:0] _beatsDO_decode_T_1 = 13'h3f << auto_out_0_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _beatsDO_decode_T_3 = ~_beatsDO_decode_T_1[5:0]; // @[package.scala 234:46]
  wire [3:0] beatsDO_decode = _beatsDO_decode_T_3[5:2]; // @[Edges.scala 219:59]
  wire  beatsDO_opdata = auto_out_0_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire [3:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 4'h0; // @[Edges.scala 220:14]
  wire [12:0] _beatsDO_decode_T_5 = 13'h3f << auto_out_1_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _beatsDO_decode_T_7 = ~_beatsDO_decode_T_5[5:0]; // @[package.scala 234:46]
  wire [3:0] beatsDO_decode_1 = _beatsDO_decode_T_7[5:2]; // @[Edges.scala 219:59]
  wire  beatsDO_opdata_1 = auto_out_1_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire [3:0] beatsDO_1 = beatsDO_opdata_1 ? beatsDO_decode_1 : 4'h0; // @[Edges.scala 220:14]
  wire [12:0] _beatsDO_decode_T_9 = 13'h3f << auto_out_2_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _beatsDO_decode_T_11 = ~_beatsDO_decode_T_9[5:0]; // @[package.scala 234:46]
  wire [3:0] beatsDO_decode_2 = _beatsDO_decode_T_11[5:2]; // @[Edges.scala 219:59]
  wire  beatsDO_opdata_2 = auto_out_2_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire [3:0] beatsDO_2 = beatsDO_opdata_2 ? beatsDO_decode_2 : 4'h0; // @[Edges.scala 220:14]
  wire [12:0] _beatsDO_decode_T_13 = 13'h3f << auto_out_3_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _beatsDO_decode_T_15 = ~_beatsDO_decode_T_13[5:0]; // @[package.scala 234:46]
  wire [3:0] beatsDO_decode_3 = _beatsDO_decode_T_15[5:2]; // @[Edges.scala 219:59]
  wire  beatsDO_opdata_3 = auto_out_3_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire [3:0] beatsDO_3 = beatsDO_opdata_3 ? beatsDO_decode_3 : 4'h0; // @[Edges.scala 220:14]
  wire [12:0] _beatsDO_decode_T_17 = 13'h3f << auto_out_4_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _beatsDO_decode_T_19 = ~_beatsDO_decode_T_17[5:0]; // @[package.scala 234:46]
  wire [3:0] beatsDO_decode_4 = _beatsDO_decode_T_19[5:2]; // @[Edges.scala 219:59]
  wire  beatsDO_opdata_4 = auto_out_4_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire [3:0] beatsDO_4 = beatsDO_opdata_4 ? beatsDO_decode_4 : 4'h0; // @[Edges.scala 220:14]
  wire [12:0] _beatsDO_decode_T_21 = 13'h3f << auto_out_5_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _beatsDO_decode_T_23 = ~_beatsDO_decode_T_21[5:0]; // @[package.scala 234:46]
  wire [3:0] beatsDO_decode_5 = _beatsDO_decode_T_23[5:2]; // @[Edges.scala 219:59]
  wire  beatsDO_opdata_5 = auto_out_5_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire [3:0] beatsDO_5 = beatsDO_opdata_5 ? beatsDO_decode_5 : 4'h0; // @[Edges.scala 220:14]
  wire [12:0] _beatsDO_decode_T_25 = 13'h3f << auto_out_6_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _beatsDO_decode_T_27 = ~_beatsDO_decode_T_25[5:0]; // @[package.scala 234:46]
  wire [3:0] beatsDO_decode_6 = _beatsDO_decode_T_27[5:2]; // @[Edges.scala 219:59]
  wire [12:0] _beatsDO_decode_T_29 = 13'h3f << auto_out_7_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _beatsDO_decode_T_31 = ~_beatsDO_decode_T_29[5:0]; // @[package.scala 234:46]
  wire [3:0] beatsDO_decode_7 = _beatsDO_decode_T_31[5:2]; // @[Edges.scala 219:59]
  wire  beatsDO_opdata_7 = auto_out_7_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire [3:0] beatsDO_7 = beatsDO_opdata_7 ? beatsDO_decode_7 : 4'h0; // @[Edges.scala 220:14]
  wire [12:0] _beatsDO_decode_T_33 = 13'h3f << auto_out_8_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _beatsDO_decode_T_35 = ~_beatsDO_decode_T_33[5:0]; // @[package.scala 234:46]
  wire [3:0] beatsDO_decode_8 = _beatsDO_decode_T_35[5:2]; // @[Edges.scala 219:59]
  wire  beatsDO_opdata_8 = auto_out_8_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire [3:0] beatsDO_8 = beatsDO_opdata_8 ? beatsDO_decode_8 : 4'h0; // @[Edges.scala 220:14]
  wire [12:0] _beatsDO_decode_T_37 = 13'h3f << auto_out_9_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _beatsDO_decode_T_39 = ~_beatsDO_decode_T_37[5:0]; // @[package.scala 234:46]
  wire [3:0] beatsDO_decode_9 = _beatsDO_decode_T_39[5:2]; // @[Edges.scala 219:59]
  wire  beatsDO_opdata_9 = auto_out_9_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire [3:0] beatsDO_9 = beatsDO_opdata_9 ? beatsDO_decode_9 : 4'h0; // @[Edges.scala 220:14]
  wire [12:0] _beatsDO_decode_T_41 = 13'h3f << auto_out_10_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _beatsDO_decode_T_43 = ~_beatsDO_decode_T_41[5:0]; // @[package.scala 234:46]
  wire [3:0] beatsDO_decode_10 = _beatsDO_decode_T_43[5:2]; // @[Edges.scala 219:59]
  wire  beatsDO_opdata_10 = auto_out_10_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire [3:0] beatsDO_10 = beatsDO_opdata_10 ? beatsDO_decode_10 : 4'h0; // @[Edges.scala 220:14]
  wire [12:0] _beatsDO_decode_T_45 = 13'h3f << auto_out_11_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _beatsDO_decode_T_47 = ~_beatsDO_decode_T_45[5:0]; // @[package.scala 234:46]
  wire [3:0] beatsDO_decode_11 = _beatsDO_decode_T_47[5:2]; // @[Edges.scala 219:59]
  wire  beatsDO_opdata_11 = auto_out_11_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire [3:0] beatsDO_11 = beatsDO_opdata_11 ? beatsDO_decode_11 : 4'h0; // @[Edges.scala 220:14]
  wire [12:0] _beatsDO_decode_T_49 = 13'h3f << auto_out_12_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _beatsDO_decode_T_51 = ~_beatsDO_decode_T_49[5:0]; // @[package.scala 234:46]
  wire [3:0] beatsDO_decode_12 = _beatsDO_decode_T_51[5:2]; // @[Edges.scala 219:59]
  wire  beatsDO_opdata_12 = auto_out_12_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire [3:0] beatsDO_12 = beatsDO_opdata_12 ? beatsDO_decode_12 : 4'h0; // @[Edges.scala 220:14]
  wire [12:0] _beatsDO_decode_T_53 = 13'h3f << auto_out_13_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _beatsDO_decode_T_55 = ~_beatsDO_decode_T_53[5:0]; // @[package.scala 234:46]
  wire [3:0] beatsDO_decode_13 = _beatsDO_decode_T_55[5:2]; // @[Edges.scala 219:59]
  wire  beatsDO_opdata_13 = auto_out_13_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire [3:0] beatsDO_13 = beatsDO_opdata_13 ? beatsDO_decode_13 : 4'h0; // @[Edges.scala 220:14]
  wire [12:0] _beatsDO_decode_T_57 = 13'h3f << auto_out_14_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _beatsDO_decode_T_59 = ~_beatsDO_decode_T_57[5:0]; // @[package.scala 234:46]
  wire [3:0] beatsDO_decode_14 = _beatsDO_decode_T_59[5:2]; // @[Edges.scala 219:59]
  wire  beatsDO_opdata_14 = auto_out_14_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire [3:0] beatsDO_14 = beatsDO_opdata_14 ? beatsDO_decode_14 : 4'h0; // @[Edges.scala 220:14]
  wire  latch = idle & auto_in_d_ready; // @[Arbiter.scala 89:24]
  wire  _readys_T_3 = ~reset; // @[Arbiter.scala 22:12]
  wire [14:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala 28:29]
  wire [15:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala 244:48]
  wire [14:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_1[14:0]; // @[package.scala 244:43]
  wire [16:0] _readys_mask_T_4 = {_readys_mask_T_3, 2'h0}; // @[package.scala 244:48]
  wire [14:0] _readys_mask_T_6 = _readys_mask_T_3 | _readys_mask_T_4[14:0]; // @[package.scala 244:43]
  wire [18:0] _readys_mask_T_7 = {_readys_mask_T_6, 4'h0}; // @[package.scala 244:48]
  wire [14:0] _readys_mask_T_9 = _readys_mask_T_6 | _readys_mask_T_7[14:0]; // @[package.scala 244:43]
  wire [22:0] _readys_mask_T_10 = {_readys_mask_T_9, 8'h0}; // @[package.scala 244:48]
  wire [14:0] _readys_mask_T_12 = _readys_mask_T_9 | _readys_mask_T_10[14:0]; // @[package.scala 244:43]
  wire  prefixOR_2 = earlyWinner_0 | earlyWinner_1; // @[Arbiter.scala 104:53]
  wire  prefixOR_3 = prefixOR_2 | earlyWinner_2; // @[Arbiter.scala 104:53]
  wire  prefixOR_4 = prefixOR_3 | earlyWinner_3; // @[Arbiter.scala 104:53]
  wire  prefixOR_5 = prefixOR_4 | earlyWinner_4; // @[Arbiter.scala 104:53]
  wire  prefixOR_6 = prefixOR_5 | earlyWinner_5; // @[Arbiter.scala 104:53]
  wire  prefixOR_7 = prefixOR_6 | earlyWinner_6; // @[Arbiter.scala 104:53]
  wire  prefixOR_8 = prefixOR_7 | earlyWinner_7; // @[Arbiter.scala 104:53]
  wire  prefixOR_9 = prefixOR_8 | earlyWinner_8; // @[Arbiter.scala 104:53]
  wire  prefixOR_10 = prefixOR_9 | earlyWinner_9; // @[Arbiter.scala 104:53]
  wire  prefixOR_11 = prefixOR_10 | earlyWinner_10; // @[Arbiter.scala 104:53]
  wire  prefixOR_12 = prefixOR_11 | earlyWinner_11; // @[Arbiter.scala 104:53]
  wire  prefixOR_13 = prefixOR_12 | earlyWinner_12; // @[Arbiter.scala 104:53]
  wire  prefixOR_14 = prefixOR_13 | earlyWinner_13; // @[Arbiter.scala 104:53]
  wire  _prefixOR_T = prefixOR_14 | earlyWinner_14; // @[Arbiter.scala 104:53]
  wire  _T_26 = ~prefixOR_8 | ~earlyWinner_8; // @[Arbiter.scala 105:64]
  wire  _T_29 = ~prefixOR_9 | ~earlyWinner_9; // @[Arbiter.scala 105:64]
  wire  _T_32 = ~prefixOR_10 | ~earlyWinner_10; // @[Arbiter.scala 105:64]
  wire  _T_54 = (~earlyWinner_0 | ~earlyWinner_1) & (~prefixOR_2 | ~earlyWinner_2) & (~prefixOR_3 | ~earlyWinner_3) & (~
    prefixOR_4 | ~earlyWinner_4) & (~prefixOR_5 | ~earlyWinner_5) & (~prefixOR_6 | ~earlyWinner_6) & (~prefixOR_7 | ~
    earlyWinner_7) & _T_26 & _T_29 & _T_32; // @[Arbiter.scala 105:82]
  wire  _T_75 = auto_out_0_d_valid | auto_out_1_d_valid | auto_out_2_d_valid | auto_out_3_d_valid | auto_out_4_d_valid
     | auto_out_5_d_valid | auto_out_6_d_valid | auto_out_7_d_valid | auto_out_8_d_valid | auto_out_9_d_valid |
    auto_out_10_d_valid | auto_out_11_d_valid | auto_out_12_d_valid | auto_out_13_d_valid | auto_out_14_d_valid; // @[Arbiter.scala 107:36]
  wire  _T_76 = ~(auto_out_0_d_valid | auto_out_1_d_valid | auto_out_2_d_valid | auto_out_3_d_valid | auto_out_4_d_valid
     | auto_out_5_d_valid | auto_out_6_d_valid | auto_out_7_d_valid | auto_out_8_d_valid | auto_out_9_d_valid |
    auto_out_10_d_valid | auto_out_11_d_valid | auto_out_12_d_valid | auto_out_13_d_valid | auto_out_14_d_valid); // @[Arbiter.scala 107:15]
  wire [3:0] maskedBeats_0 = earlyWinner_0 ? beatsDO_0 : 4'h0; // @[Arbiter.scala 111:73]
  wire [3:0] maskedBeats_1 = earlyWinner_1 ? beatsDO_1 : 4'h0; // @[Arbiter.scala 111:73]
  wire [3:0] maskedBeats_2 = earlyWinner_2 ? beatsDO_2 : 4'h0; // @[Arbiter.scala 111:73]
  wire [3:0] maskedBeats_3 = earlyWinner_3 ? beatsDO_3 : 4'h0; // @[Arbiter.scala 111:73]
  wire [3:0] maskedBeats_4 = earlyWinner_4 ? beatsDO_4 : 4'h0; // @[Arbiter.scala 111:73]
  wire [3:0] maskedBeats_5 = earlyWinner_5 ? beatsDO_5 : 4'h0; // @[Arbiter.scala 111:73]
  wire [3:0] maskedBeats_6 = earlyWinner_6 ? beatsDO_decode_6 : 4'h0; // @[Arbiter.scala 111:73]
  wire [3:0] maskedBeats_7 = earlyWinner_7 ? beatsDO_7 : 4'h0; // @[Arbiter.scala 111:73]
  wire [3:0] maskedBeats_8 = earlyWinner_8 ? beatsDO_8 : 4'h0; // @[Arbiter.scala 111:73]
  wire [3:0] maskedBeats_9 = earlyWinner_9 ? beatsDO_9 : 4'h0; // @[Arbiter.scala 111:73]
  wire [3:0] maskedBeats_10 = earlyWinner_10 ? beatsDO_10 : 4'h0; // @[Arbiter.scala 111:73]
  wire [3:0] maskedBeats_11 = earlyWinner_11 ? beatsDO_11 : 4'h0; // @[Arbiter.scala 111:73]
  wire [3:0] maskedBeats_12 = earlyWinner_12 ? beatsDO_12 : 4'h0; // @[Arbiter.scala 111:73]
  wire [3:0] maskedBeats_13 = earlyWinner_13 ? beatsDO_13 : 4'h0; // @[Arbiter.scala 111:73]
  wire [3:0] maskedBeats_14 = earlyWinner_14 ? beatsDO_14 : 4'h0; // @[Arbiter.scala 111:73]
  wire [3:0] _initBeats_T = maskedBeats_0 | maskedBeats_1; // @[Arbiter.scala 112:44]
  wire [3:0] _initBeats_T_1 = _initBeats_T | maskedBeats_2; // @[Arbiter.scala 112:44]
  wire [3:0] _initBeats_T_2 = _initBeats_T_1 | maskedBeats_3; // @[Arbiter.scala 112:44]
  wire [3:0] _initBeats_T_3 = _initBeats_T_2 | maskedBeats_4; // @[Arbiter.scala 112:44]
  wire [3:0] _initBeats_T_4 = _initBeats_T_3 | maskedBeats_5; // @[Arbiter.scala 112:44]
  wire [3:0] _initBeats_T_5 = _initBeats_T_4 | maskedBeats_6; // @[Arbiter.scala 112:44]
  wire [3:0] _initBeats_T_6 = _initBeats_T_5 | maskedBeats_7; // @[Arbiter.scala 112:44]
  wire [3:0] _initBeats_T_7 = _initBeats_T_6 | maskedBeats_8; // @[Arbiter.scala 112:44]
  wire [3:0] _initBeats_T_8 = _initBeats_T_7 | maskedBeats_9; // @[Arbiter.scala 112:44]
  wire [3:0] _initBeats_T_9 = _initBeats_T_8 | maskedBeats_10; // @[Arbiter.scala 112:44]
  wire [3:0] _initBeats_T_10 = _initBeats_T_9 | maskedBeats_11; // @[Arbiter.scala 112:44]
  wire [3:0] _initBeats_T_11 = _initBeats_T_10 | maskedBeats_12; // @[Arbiter.scala 112:44]
  wire [3:0] _initBeats_T_12 = _initBeats_T_11 | maskedBeats_13; // @[Arbiter.scala 112:44]
  wire [3:0] initBeats = _initBeats_T_12 | maskedBeats_14; // @[Arbiter.scala 112:44]
  wire  _sink_ACancel_earlyValid_T_42 = state_0 & auto_out_0_d_valid | state_1 & auto_out_1_d_valid | state_2 &
    auto_out_2_d_valid | state_3 & auto_out_3_d_valid | state_4 & auto_out_4_d_valid | state_5 & auto_out_5_d_valid |
    state_6 & auto_out_6_d_valid | state_7 & auto_out_7_d_valid | state_8 & auto_out_8_d_valid | state_9 &
    auto_out_9_d_valid | state_10 & auto_out_10_d_valid | state_11 & auto_out_11_d_valid | state_12 &
    auto_out_12_d_valid | state_13 & auto_out_13_d_valid | state_14 & auto_out_14_d_valid; // @[Mux.scala 27:73]
  wire  sink_ACancel_31_earlyValid = idle ? _T_75 : _sink_ACancel_earlyValid_T_42; // @[Arbiter.scala 125:29]
  wire  _beatsLeft_T_2 = auto_in_d_ready & sink_ACancel_31_earlyValid; // @[ReadyValidCancel.scala 49:33]
  wire [3:0] _GEN_6 = {{3'd0}, _beatsLeft_T_2}; // @[Arbiter.scala 113:52]
  wire [3:0] _beatsLeft_T_4 = beatsLeft - _GEN_6; // @[Arbiter.scala 113:52]
  wire  allowed_0 = idle ? readys_0 : state_0; // @[Arbiter.scala 121:24]
  wire  allowed_1 = idle ? readys_1 : state_1; // @[Arbiter.scala 121:24]
  wire  allowed_2 = idle ? readys_2 : state_2; // @[Arbiter.scala 121:24]
  wire  allowed_3 = idle ? readys_3 : state_3; // @[Arbiter.scala 121:24]
  wire  allowed_4 = idle ? readys_4 : state_4; // @[Arbiter.scala 121:24]
  wire  allowed_5 = idle ? readys_5 : state_5; // @[Arbiter.scala 121:24]
  wire  allowed_6 = idle ? readys_6 : state_6; // @[Arbiter.scala 121:24]
  wire  allowed_7 = idle ? readys_7 : state_7; // @[Arbiter.scala 121:24]
  wire  allowed_8 = idle ? readys_8 : state_8; // @[Arbiter.scala 121:24]
  wire  allowed_9 = idle ? readys_9 : state_9; // @[Arbiter.scala 121:24]
  wire  allowed_10 = idle ? readys_10 : state_10; // @[Arbiter.scala 121:24]
  wire  allowed_11 = idle ? readys_11 : state_11; // @[Arbiter.scala 121:24]
  wire  allowed_12 = idle ? readys_12 : state_12; // @[Arbiter.scala 121:24]
  wire  allowed_13 = idle ? readys_13 : state_13; // @[Arbiter.scala 121:24]
  wire  allowed_14 = idle ? readys_14 : state_14; // @[Arbiter.scala 121:24]
  wire [31:0] _T_157 = muxStateEarly_0 ? auto_out_0_d_bits_data : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_158 = muxStateEarly_1 ? auto_out_1_d_bits_data : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_159 = muxStateEarly_2 ? auto_out_2_d_bits_data : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_160 = muxStateEarly_3 ? auto_out_3_d_bits_data : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_161 = muxStateEarly_4 ? auto_out_4_d_bits_data : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_162 = muxStateEarly_5 ? auto_out_5_d_bits_data : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_163 = muxStateEarly_6 ? auto_out_6_d_bits_data : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_164 = muxStateEarly_7 ? auto_out_7_d_bits_data : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_165 = muxStateEarly_8 ? auto_out_8_d_bits_data : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_166 = muxStateEarly_9 ? auto_out_9_d_bits_data : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_167 = muxStateEarly_10 ? auto_out_10_d_bits_data : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_168 = muxStateEarly_11 ? auto_out_11_d_bits_data : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_169 = muxStateEarly_12 ? auto_out_12_d_bits_data : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_170 = muxStateEarly_13 ? auto_out_13_d_bits_data : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_171 = muxStateEarly_14 ? auto_out_14_d_bits_data : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_172 = _T_157 | _T_158; // @[Mux.scala 27:73]
  wire [31:0] _T_173 = _T_172 | _T_159; // @[Mux.scala 27:73]
  wire [31:0] _T_174 = _T_173 | _T_160; // @[Mux.scala 27:73]
  wire [31:0] _T_175 = _T_174 | _T_161; // @[Mux.scala 27:73]
  wire [31:0] _T_176 = _T_175 | _T_162; // @[Mux.scala 27:73]
  wire [31:0] _T_177 = _T_176 | _T_163; // @[Mux.scala 27:73]
  wire [31:0] _T_178 = _T_177 | _T_164; // @[Mux.scala 27:73]
  wire [31:0] _T_179 = _T_178 | _T_165; // @[Mux.scala 27:73]
  wire [31:0] _T_180 = _T_179 | _T_166; // @[Mux.scala 27:73]
  wire [31:0] _T_181 = _T_180 | _T_167; // @[Mux.scala 27:73]
  wire [31:0] _T_182 = _T_181 | _T_168; // @[Mux.scala 27:73]
  wire [31:0] _T_183 = _T_182 | _T_169; // @[Mux.scala 27:73]
  wire [31:0] _T_184 = _T_183 | _T_170; // @[Mux.scala 27:73]
  wire [2:0] _T_273 = muxStateEarly_0 ? auto_out_0_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_274 = muxStateEarly_1 ? auto_out_1_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_275 = muxStateEarly_2 ? auto_out_2_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_276 = muxStateEarly_3 ? auto_out_3_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_277 = muxStateEarly_4 ? auto_out_4_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_278 = muxStateEarly_5 ? auto_out_5_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_279 = muxStateEarly_6 ? auto_out_6_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_280 = muxStateEarly_7 ? auto_out_7_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_281 = muxStateEarly_8 ? auto_out_8_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_282 = muxStateEarly_9 ? auto_out_9_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_283 = muxStateEarly_10 ? auto_out_10_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_284 = muxStateEarly_11 ? auto_out_11_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_285 = muxStateEarly_12 ? auto_out_12_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_286 = muxStateEarly_13 ? auto_out_13_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_287 = muxStateEarly_14 ? auto_out_14_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_288 = _T_273 | _T_274; // @[Mux.scala 27:73]
  wire [2:0] _T_289 = _T_288 | _T_275; // @[Mux.scala 27:73]
  wire [2:0] _T_290 = _T_289 | _T_276; // @[Mux.scala 27:73]
  wire [2:0] _T_291 = _T_290 | _T_277; // @[Mux.scala 27:73]
  wire [2:0] _T_292 = _T_291 | _T_278; // @[Mux.scala 27:73]
  wire [2:0] _T_293 = _T_292 | _T_279; // @[Mux.scala 27:73]
  wire [2:0] _T_294 = _T_293 | _T_280; // @[Mux.scala 27:73]
  wire [2:0] _T_295 = _T_294 | _T_281; // @[Mux.scala 27:73]
  wire [2:0] _T_296 = _T_295 | _T_282; // @[Mux.scala 27:73]
  wire [2:0] _T_297 = _T_296 | _T_283; // @[Mux.scala 27:73]
  wire [2:0] _T_298 = _T_297 | _T_284; // @[Mux.scala 27:73]
  wire [2:0] _T_299 = _T_298 | _T_285; // @[Mux.scala 27:73]
  wire [2:0] _T_300 = _T_299 | _T_286; // @[Mux.scala 27:73]
  wire [2:0] _T_331 = muxStateEarly_0 ? auto_out_0_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_332 = muxStateEarly_1 ? auto_out_1_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_333 = muxStateEarly_2 ? auto_out_2_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_334 = muxStateEarly_3 ? auto_out_3_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_335 = muxStateEarly_4 ? auto_out_4_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_336 = muxStateEarly_5 ? auto_out_5_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_337 = muxStateEarly_6 ? 3'h1 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_338 = muxStateEarly_7 ? auto_out_7_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_339 = muxStateEarly_8 ? auto_out_8_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_340 = muxStateEarly_9 ? auto_out_9_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_341 = muxStateEarly_10 ? auto_out_10_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_342 = muxStateEarly_11 ? auto_out_11_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_343 = muxStateEarly_12 ? auto_out_12_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_344 = muxStateEarly_13 ? auto_out_13_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_345 = muxStateEarly_14 ? auto_out_14_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_346 = _T_331 | _T_332; // @[Mux.scala 27:73]
  wire [2:0] _T_347 = _T_346 | _T_333; // @[Mux.scala 27:73]
  wire [2:0] _T_348 = _T_347 | _T_334; // @[Mux.scala 27:73]
  wire [2:0] _T_349 = _T_348 | _T_335; // @[Mux.scala 27:73]
  wire [2:0] _T_350 = _T_349 | _T_336; // @[Mux.scala 27:73]
  wire [2:0] _T_351 = _T_350 | _T_337; // @[Mux.scala 27:73]
  wire [2:0] _T_352 = _T_351 | _T_338; // @[Mux.scala 27:73]
  wire [2:0] _T_353 = _T_352 | _T_339; // @[Mux.scala 27:73]
  wire [2:0] _T_354 = _T_353 | _T_340; // @[Mux.scala 27:73]
  wire [2:0] _T_355 = _T_354 | _T_341; // @[Mux.scala 27:73]
  wire [2:0] _T_356 = _T_355 | _T_342; // @[Mux.scala 27:73]
  wire [2:0] _T_357 = _T_356 | _T_343; // @[Mux.scala 27:73]
  wire [2:0] _T_358 = _T_357 | _T_344; // @[Mux.scala 27:73]
  TLMonitor_3 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  assign auto_in_a_ready = requestAIO_0_0 & auto_out_0_a_ready | requestAIO_0_1 & auto_out_1_a_ready | requestAIO_0_2 &
    auto_out_2_a_ready | requestAIO_0_3 & auto_out_3_a_ready | requestAIO_0_4 & auto_out_4_a_ready | requestAIO_0_5 &
    auto_out_5_a_ready | requestAIO_0_6 & auto_out_6_a_ready | requestAIO_0_7 & auto_out_7_a_ready | requestAIO_0_8 &
    auto_out_8_a_ready | requestAIO_0_9 & auto_out_9_a_ready | requestAIO_0_10 & auto_out_10_a_ready | requestAIO_0_11
     & auto_out_11_a_ready | requestAIO_0_12 & auto_out_12_a_ready | requestAIO_0_13 & auto_out_13_a_ready |
    requestAIO_0_14 & auto_out_14_a_ready; // @[Mux.scala 27:73]
  assign auto_in_d_valid = idle ? _T_75 : _sink_ACancel_earlyValid_T_42; // @[Arbiter.scala 125:29]
  assign auto_in_d_bits_opcode = _T_358 | _T_345; // @[Mux.scala 27:73]
  assign auto_in_d_bits_size = _T_300 | _T_287; // @[Mux.scala 27:73]
  assign auto_in_d_bits_source = _T_271 | _T_258; // @[Mux.scala 27:73]
  assign auto_in_d_bits_data = _T_184 | _T_171; // @[Mux.scala 27:73]
  assign auto_out_14_a_valid = auto_in_a_valid & requestAIO_0_14; // @[Xbar.scala 428:50]
  assign auto_out_14_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_14_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_14_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_14_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
  assign auto_out_14_a_bits_address = auto_in_a_bits_address[28:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
  assign auto_out_14_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_14_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_14_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_14_d_ready = auto_in_d_ready & allowed_14; // @[Arbiter.scala 123:31]
  assign auto_out_13_a_valid = auto_in_a_valid & requestAIO_0_13; // @[Xbar.scala 428:50]
  assign auto_out_13_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_13_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_13_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_13_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
  assign auto_out_13_a_bits_address = auto_in_a_bits_address[28:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
  assign auto_out_13_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_13_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_13_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_13_d_ready = auto_in_d_ready & allowed_13; // @[Arbiter.scala 123:31]
  assign auto_out_12_a_valid = auto_in_a_valid & requestAIO_0_12; // @[Xbar.scala 428:50]
  assign auto_out_12_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_12_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_12_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_12_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
  assign auto_out_12_a_bits_address = auto_in_a_bits_address[28:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
  assign auto_out_12_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_12_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_12_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_12_d_ready = auto_in_d_ready & allowed_12; // @[Arbiter.scala 123:31]
  assign auto_out_11_a_valid = auto_in_a_valid & requestAIO_0_11; // @[Xbar.scala 428:50]
  assign auto_out_11_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_11_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_11_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_11_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
  assign auto_out_11_a_bits_address = auto_in_a_bits_address[28:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
  assign auto_out_11_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_11_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_11_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_11_d_ready = auto_in_d_ready & allowed_11; // @[Arbiter.scala 123:31]
  assign auto_out_10_a_valid = auto_in_a_valid & requestAIO_0_10; // @[Xbar.scala 428:50]
  assign auto_out_10_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_10_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_10_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_10_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
  assign auto_out_10_a_bits_address = auto_in_a_bits_address[28:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
  assign auto_out_10_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_10_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_10_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_10_d_ready = auto_in_d_ready & allowed_10; // @[Arbiter.scala 123:31]
  assign auto_out_9_a_valid = auto_in_a_valid & requestAIO_0_9; // @[Xbar.scala 428:50]
  assign auto_out_9_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_9_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_9_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_9_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
  assign auto_out_9_a_bits_address = auto_in_a_bits_address[28:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
  assign auto_out_9_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_9_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_9_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_9_d_ready = auto_in_d_ready & allowed_9; // @[Arbiter.scala 123:31]
  assign auto_out_8_a_valid = auto_in_a_valid & requestAIO_0_8; // @[Xbar.scala 428:50]
  assign auto_out_8_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_8_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_8_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_8_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
  assign auto_out_8_a_bits_address = auto_in_a_bits_address[28:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
  assign auto_out_8_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_8_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_8_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_8_d_ready = auto_in_d_ready & allowed_8; // @[Arbiter.scala 123:31]
  assign auto_out_7_a_valid = auto_in_a_valid & requestAIO_0_7; // @[Xbar.scala 428:50]
  assign auto_out_7_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_7_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_7_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_7_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
  assign auto_out_7_a_bits_address = auto_in_a_bits_address[28:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
  assign auto_out_7_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_7_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_7_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_7_d_ready = auto_in_d_ready & allowed_7; // @[Arbiter.scala 123:31]
  assign auto_out_6_a_valid = auto_in_a_valid & requestAIO_0_6; // @[Xbar.scala 428:50]
  assign auto_out_6_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_6_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_6_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_6_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
  assign auto_out_6_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_6_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_6_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_6_d_ready = auto_in_d_ready & allowed_6; // @[Arbiter.scala 123:31]
  assign auto_out_5_a_valid = auto_in_a_valid & requestAIO_0_5; // @[Xbar.scala 428:50]
  assign auto_out_5_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_5_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_5_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_5_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
  assign auto_out_5_a_bits_address = auto_in_a_bits_address[28:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
  assign auto_out_5_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_5_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_5_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_5_d_ready = auto_in_d_ready & allowed_5; // @[Arbiter.scala 123:31]
  assign auto_out_4_a_valid = auto_in_a_valid & requestAIO_0_4; // @[Xbar.scala 428:50]
  assign auto_out_4_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_4_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_4_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_4_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
  assign auto_out_4_a_bits_address = auto_in_a_bits_address[28:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
  assign auto_out_4_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_4_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_4_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_4_d_ready = auto_in_d_ready & allowed_4; // @[Arbiter.scala 123:31]
  assign auto_out_3_a_valid = auto_in_a_valid & requestAIO_0_3; // @[Xbar.scala 428:50]
  assign auto_out_3_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_3_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_3_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_3_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
  assign auto_out_3_a_bits_address = auto_in_a_bits_address[28:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
  assign auto_out_3_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_3_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_3_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_3_d_ready = auto_in_d_ready & allowed_3; // @[Arbiter.scala 123:31]
  assign auto_out_2_a_valid = auto_in_a_valid & requestAIO_0_2; // @[Xbar.scala 428:50]
  assign auto_out_2_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_2_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_2_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_2_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
  assign auto_out_2_a_bits_address = auto_in_a_bits_address[28:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
  assign auto_out_2_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_2_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_2_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_2_d_ready = auto_in_d_ready & allowed_2; // @[Arbiter.scala 123:31]
  assign auto_out_1_a_valid = auto_in_a_valid & requestAIO_0_1; // @[Xbar.scala 428:50]
  assign auto_out_1_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
  assign auto_out_1_a_bits_address = auto_in_a_bits_address[28:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
  assign auto_out_1_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_d_ready = auto_in_d_ready & allowed_1; // @[Arbiter.scala 123:31]
  assign auto_out_0_a_valid = auto_in_a_valid & requestAIO_0_0; // @[Xbar.scala 428:50]
  assign auto_out_0_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_0_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_0_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_0_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
  assign auto_out_0_a_bits_address = auto_in_a_bits_address[28:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
  assign auto_out_0_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_0_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_0_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_0_d_ready = auto_in_d_ready & allowed_0; // @[Arbiter.scala 123:31]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = requestAIO_0_0 & auto_out_0_a_ready | requestAIO_0_1 & auto_out_1_a_ready |
    requestAIO_0_2 & auto_out_2_a_ready | requestAIO_0_3 & auto_out_3_a_ready | requestAIO_0_4 & auto_out_4_a_ready |
    requestAIO_0_5 & auto_out_5_a_ready | requestAIO_0_6 & auto_out_6_a_ready | requestAIO_0_7 & auto_out_7_a_ready |
    requestAIO_0_8 & auto_out_8_a_ready | requestAIO_0_9 & auto_out_9_a_ready | requestAIO_0_10 & auto_out_10_a_ready |
    requestAIO_0_11 & auto_out_11_a_ready | requestAIO_0_12 & auto_out_12_a_ready | requestAIO_0_13 &
    auto_out_13_a_ready | requestAIO_0_14 & auto_out_14_a_ready; // @[Mux.scala 27:73]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = idle ? _T_75 : _sink_ACancel_earlyValid_T_42; // @[Arbiter.scala 125:29]
  assign monitor_io_in_d_bits_opcode = _T_358 | _T_345; // @[Mux.scala 27:73]
  assign monitor_io_in_d_bits_size = _T_300 | _T_287; // @[Mux.scala 27:73]
  assign monitor_io_in_d_bits_source = _T_271 | _T_258; // @[Mux.scala 27:73]
  always @(posedge clock) begin
    if (reset) begin // @[Arbiter.scala 87:30]
      beatsLeft <= 4'h0; // @[Arbiter.scala 87:30]
    end else if (latch) begin // @[Arbiter.scala 113:23]
      beatsLeft <= initBeats;
    end else begin
      beatsLeft <= _beatsLeft_T_4;
    end
    if (reset) begin // @[Arbiter.scala 23:23]
      readys_mask <= 15'h7fff; // @[Arbiter.scala 23:23]
    end else if (latch & |readys_valid) begin // @[Arbiter.scala 27:32]
      readys_mask <= _readys_mask_T_12; // @[Arbiter.scala 28:12]
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_0 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_0 <= earlyWinner_0;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_1 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_1 <= earlyWinner_1;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_2 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_2 <= earlyWinner_2;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_3 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_3 <= earlyWinner_3;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_4 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_4 <= earlyWinner_4;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_5 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_5 <= earlyWinner_5;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_6 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_6 <= earlyWinner_6;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_7 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_7 <= earlyWinner_7;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_8 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_8 <= earlyWinner_8;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_9 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_9 <= earlyWinner_9;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_10 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_10 <= earlyWinner_10;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_11 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_11 <= earlyWinner_11;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_12 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_12 <= earlyWinner_12;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_13 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_13 <= earlyWinner_13;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_14 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_14 <= earlyWinner_14;
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_54 & (~prefixOR_11 | ~earlyWinner_11) & (~prefixOR_12 | ~earlyWinner_12) & (~prefixOR_13 | ~
          earlyWinner_13) & (~prefixOR_14 | ~earlyWinner_14)) & _readys_T_3) begin
          $fatal; // @[Arbiter.scala 105:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_readys_T_3 & ~(_T_54 & (~prefixOR_11 | ~earlyWinner_11) & (~prefixOR_12 | ~earlyWinner_12) & (~prefixOR_13
           | ~earlyWinner_13) & (~prefixOR_14 | ~earlyWinner_14))) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:105 assert((prefixOR zip earlyWinner) map { case (p,w) => !p || !w } reduce {_ && _})\n"
            ); // @[Arbiter.scala 105:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(auto_out_0_d_valid | auto_out_1_d_valid | auto_out_2_d_valid | auto_out_3_d_valid | auto_out_4_d_valid
           | auto_out_5_d_valid | auto_out_6_d_valid | auto_out_7_d_valid | auto_out_8_d_valid | auto_out_9_d_valid |
          auto_out_10_d_valid | auto_out_11_d_valid | auto_out_12_d_valid | auto_out_13_d_valid | auto_out_14_d_valid)
           | _prefixOR_T) & _readys_T_3) begin
          $fatal; // @[Arbiter.scala 107:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_readys_T_3 & ~(~(auto_out_0_d_valid | auto_out_1_d_valid | auto_out_2_d_valid | auto_out_3_d_valid |
          auto_out_4_d_valid | auto_out_5_d_valid | auto_out_6_d_valid | auto_out_7_d_valid | auto_out_8_d_valid |
          auto_out_9_d_valid | auto_out_10_d_valid | auto_out_11_d_valid | auto_out_12_d_valid | auto_out_13_d_valid |
          auto_out_14_d_valid) | _prefixOR_T)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:107 assert (!earlyValids.reduce(_||_) || earlyWinner.reduce(_||_))\n"
            ); // @[Arbiter.scala 107:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_76 | _T_75) & _readys_T_3) begin
          $fatal; // @[Arbiter.scala 108:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_readys_T_3 & ~(_T_76 | _T_75)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:108 assert (!validQuals .reduce(_||_) || validQuals .reduce(_||_))\n"
            ); // @[Arbiter.scala 108:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  beatsLeft = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  readys_mask = _RAND_1[14:0];
  _RAND_2 = {1{`RANDOM}};
  state_0 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  state_1 = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  state_2 = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  state_3 = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  state_4 = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  state_5 = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  state_6 = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  state_7 = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  state_8 = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  state_9 = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  state_10 = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  state_11 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  state_12 = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  state_13 = _RAND_15[0:0];
  _RAND_16 = {1{`RANDOM}};
  state_14 = _RAND_16[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLMonitor_4(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [29:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_param,
  input  [2:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source,
  input         io_in_d_bits_sink,
  input         io_in_d_bits_denied,
  input         io_in_d_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
  wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
  wire [29:0] _GEN_71 = {{24'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [29:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 30'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [29:0] _T_45 = io_in_a_bits_address ^ 30'h10012000; // @[Parameters.scala 137:31]
  wire [30:0] _T_46 = {1'b0,$signed(_T_45)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_48 = $signed(_T_46) & -31'sh2000; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_50 = io_in_a_bits_address ^ 30'h10014000; // @[Parameters.scala 137:31]
  wire [30:0] _T_51 = {1'b0,$signed(_T_50)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_53 = $signed(_T_51) & -31'sh2000; // @[Parameters.scala 137:52]
  wire  _T_54 = $signed(_T_53) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_55 = io_in_a_bits_address ^ 30'h10016000; // @[Parameters.scala 137:31]
  wire [30:0] _T_56 = {1'b0,$signed(_T_55)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_58 = $signed(_T_56) & -31'sh1000; // @[Parameters.scala 137:52]
  wire  _T_59 = $signed(_T_58) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_60 = io_in_a_bits_address ^ 30'h10023000; // @[Parameters.scala 137:31]
  wire [30:0] _T_61 = {1'b0,$signed(_T_60)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_63 = $signed(_T_61) & -31'sh11000; // @[Parameters.scala 137:52]
  wire  _T_64 = $signed(_T_63) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_65 = io_in_a_bits_address ^ 30'h10024000; // @[Parameters.scala 137:31]
  wire [30:0] _T_66 = {1'b0,$signed(_T_65)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_68 = $signed(_T_66) & -31'sh12000; // @[Parameters.scala 137:52]
  wire  _T_69 = $signed(_T_68) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_70 = io_in_a_bits_address ^ 30'h10026000; // @[Parameters.scala 137:31]
  wire [30:0] _T_71 = {1'b0,$signed(_T_70)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_73 = $signed(_T_71) & -31'sh1000; // @[Parameters.scala 137:52]
  wire  _T_74 = $signed(_T_73) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_75 = io_in_a_bits_address ^ 30'h10043000; // @[Parameters.scala 137:31]
  wire [30:0] _T_76 = {1'b0,$signed(_T_75)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_78 = $signed(_T_76) & -31'sh11000; // @[Parameters.scala 137:52]
  wire  _T_79 = $signed(_T_78) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_80 = io_in_a_bits_address ^ 30'h20000000; // @[Parameters.scala 137:31]
  wire [30:0] _T_81 = {1'b0,$signed(_T_80)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_83 = $signed(_T_81) & -31'sh20000000; // @[Parameters.scala 137:52]
  wire  _T_84 = $signed(_T_83) == 31'sh0; // @[Parameters.scala 137:67]
  wire  _T_90 = _T_49 | _T_54 | _T_59 | _T_64 | _T_69 | _T_74 | _T_79; // @[Parameters.scala 671:42]
  wire  _T_91 = _T_49 | _T_54 | _T_59 | _T_64 | _T_69 | _T_74 | _T_79 | _T_84; // @[Parameters.scala 671:42]
  wire  _T_101 = 3'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_102 = _source_ok_T & _T_101; // @[Mux.scala 27:73]
  wire  _T_160 = _T_102 & _T_91; // @[Monitor.scala 83:78]
  wire  _T_174 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_178 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_179 = _T_178 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_183 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_187 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_332 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_345 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_360 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
  wire  _T_410 = _T_360 & _T_91; // @[Parameters.scala 670:56]
  wire  _T_421 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_425 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_433 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_489 = _T_360 & _T_90; // @[Parameters.scala 670:56]
  wire  _T_499 = source_ok & _T_489; // @[Monitor.scala 115:71]
  wire  _T_517 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_597 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_598 = io_in_a_bits_mask & _T_597; // @[Monitor.scala 127:31]
  wire  _T_599 = _T_598 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_603 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_674 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_682 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_753 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_761 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_832 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_844 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  _T_848 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_852 = io_in_d_bits_size >= 3'h2; // @[Monitor.scala 312:27]
  wire  _T_856 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
  wire  _T_860 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
  wire  _T_864 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
  wire  _T_868 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_879 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
  wire  _T_883 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
  wire  _T_896 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_916 = _T_864 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
  wire  _T_925 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_942 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_960 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [3:0] a_first_beats1_decode = is_aligned_mask[5:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] a_first_counter; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1 = a_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [29:0] address; // @[Monitor.scala 388:22]
  wire  _T_990 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_991 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_995 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_999 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_1003 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_1007 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
  wire [3:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [3:0] d_first_counter; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1 = d_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] param_1; // @[Monitor.scala 536:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  reg  sink; // @[Monitor.scala 539:22]
  reg  denied; // @[Monitor.scala 540:22]
  wire  _T_1014 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_1015 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_1019 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
  wire  _T_1023 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_1027 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  wire  _T_1031 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
  wire  _T_1035 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [11:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [3:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1_1 = a_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  reg [3:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_1 = d_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [11:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _GEN_76 = {{4'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_76 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_1041 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_1044 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [34:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [34:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_1046 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_1048 = ~_T_1046[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [34:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_1052 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_1054 = ~_T_848; // @[Monitor.scala 671:74]
  wire  _T_1055 = io_in_d_valid & d_first_1 & ~_T_848; // @[Monitor.scala 671:71]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_848 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 671:90 672:22]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [3:0] _GEN_22 = _d_first_T & d_first_1 & _T_1054 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_23 = _d_first_T & d_first_1 & _T_1054 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_1041 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_1065 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_1067 = _T_1065[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_1072 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_1073 = io_in_d_bits_opcode == _GEN_32 | _T_1072; // @[Monitor.scala 685:77]
  wire  _T_1077 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_1084 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_1085 = io_in_d_bits_opcode == _GEN_48 | _T_1084; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_1089 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_1099 = _T_1052 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_1054; // @[Monitor.scala 694:116]
  wire  _T_1101 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set_wo_ready = _GEN_15[2:0];
  wire [2:0] d_clr_wo_ready = _GEN_21[2:0];
  wire  _T_1108 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire [2:0] a_set = _GEN_16[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_22[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_19[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_23[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [11:0] a_sizes_set = _GEN_20[11:0];
  wire [11:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [11:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_1117 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [2:0] inflight_1; // @[Monitor.scala 723:35]
  reg [11:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [3:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_2 = d_first_counter_2 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 4'h0; // @[Edges.scala 230:25]
  wire [11:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [15:0] _GEN_87 = {{4'd0}, _c_size_lookup_T_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_87 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_1143 = io_in_d_valid & d_first_2 & _T_848; // @[Monitor.scala 779:71]
  wire [3:0] _GEN_67 = _d_first_T & d_first_2 & _T_848 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 783:90 784:21]
  wire [46:0] _GEN_68 = _d_first_T & d_first_2 & _T_848 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 785:21]
  wire [2:0] _T_1151 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_1161 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [2:0] d_clr_1 = _GEN_67[2:0];
  wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [2:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [11:0] d_opcodes_clr_1 = _GEN_68[11:0];
  wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [11:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_1186 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 4'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 4'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 12'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 4'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 4'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 3'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 12'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 4'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_160 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_160) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_174 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_174) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_179 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_179) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_160 & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~_T_160) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_174 & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~_T_174) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_332 & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~_T_332) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_179 & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~_T_179) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_410 & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~_T_410) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_421 & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~_T_421) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_425 & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~_T_425) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_499 & (io_in_a_valid & _T_433 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_433 & ~reset & ~_T_499) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_433 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_433 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_433 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_433 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_421 & (io_in_a_valid & _T_433 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_433 & ~reset & ~_T_421) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_425 & (io_in_a_valid & _T_433 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_433 & ~reset & ~_T_425) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_499 & (io_in_a_valid & _T_517 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_517 & ~reset & ~_T_499) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_517 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_517 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_517 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_517 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_421 & (io_in_a_valid & _T_517 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_517 & ~reset & ~_T_421) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_599 & (io_in_a_valid & _T_517 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_517 & ~reset & ~_T_599) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_603 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_603 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_603 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_603 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_603 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_603 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_674 & (io_in_a_valid & _T_603 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_603 & ~reset & ~_T_674) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_425 & (io_in_a_valid & _T_603 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_603 & ~reset & ~_T_425) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_682 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_682 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_682 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_682 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_682 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_682 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_753 & (io_in_a_valid & _T_682 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_682 & ~reset & ~_T_753) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_425 & (io_in_a_valid & _T_682 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_682 & ~reset & ~_T_425) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_761 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_761 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_761 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_761 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_761 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_761 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_832 & (io_in_a_valid & _T_761 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_761 & ~reset & ~_T_832) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_425 & (io_in_a_valid & _T_761 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_761 & ~reset & ~_T_425) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_761 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_761 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_844 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_844) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_848 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_848 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_852 & (io_in_d_valid & _T_848 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_848 & _T_2 & ~_T_852) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_856 & (io_in_d_valid & _T_848 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_848 & _T_2 & ~_T_856) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_860 & (io_in_d_valid & _T_848 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_848 & _T_2 & ~_T_860) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_864 & (io_in_d_valid & _T_848 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_848 & _T_2 & ~_T_864) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is denied (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_868 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_868 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_868 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_868 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_852 & (io_in_d_valid & _T_868 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_868 & _T_2 & ~_T_852) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_879 & (io_in_d_valid & _T_868 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_868 & _T_2 & ~_T_879) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid cap param (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_883 & (io_in_d_valid & _T_868 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_868 & _T_2 & ~_T_883) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries toN param (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_860 & (io_in_d_valid & _T_868 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_868 & _T_2 & ~_T_860) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is corrupt (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_864 & (io_in_d_valid & _T_868 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_868 & _T_2 & ~_T_864) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is denied (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_896 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_896 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_896 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_896 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_852 & (io_in_d_valid & _T_896 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_896 & _T_2 & ~_T_852) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_879 & (io_in_d_valid & _T_896 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_896 & _T_2 & ~_T_879) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_883 & (io_in_d_valid & _T_896 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_896 & _T_2 & ~_T_883) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries toN param (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_916 & (io_in_d_valid & _T_896 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_896 & _T_2 & ~_T_916) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_864 & (io_in_d_valid & _T_896 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_896 & _T_2 & ~_T_864) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_925 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_925 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_856 & (io_in_d_valid & _T_925 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_925 & _T_2 & ~_T_856) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid param (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_860 & (io_in_d_valid & _T_925 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_925 & _T_2 & ~_T_860) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is corrupt (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_864 & (io_in_d_valid & _T_925 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_925 & _T_2 & ~_T_864) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is denied (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_942 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_942 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_856 & (io_in_d_valid & _T_942 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_942 & _T_2 & ~_T_856) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_916 & (io_in_d_valid & _T_942 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_942 & _T_2 & ~_T_916) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_864 & (io_in_d_valid & _T_942 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_942 & _T_2 & ~_T_864) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_960 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_960 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_856 & (io_in_d_valid & _T_960 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_960 & _T_2 & ~_T_856) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid param (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_860 & (io_in_d_valid & _T_960 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_960 & _T_2 & ~_T_860) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is corrupt (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_864 & (io_in_d_valid & _T_960 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_960 & _T_2 & ~_T_864) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is denied (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_991 & (_T_990 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_990 & ~reset & ~_T_991) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_995 & (_T_990 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_990 & ~reset & ~_T_995) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_999 & (_T_990 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_990 & ~reset & ~_T_999) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1003 & (_T_990 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_990 & ~reset & ~_T_1003) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1007 & (_T_990 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_990 & ~reset & ~_T_1007) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1015 & (_T_1014 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1014 & _T_2 & ~_T_1015) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1019 & (_T_1014 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1014 & _T_2 & ~_T_1019) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel param changed within multibeat operation (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1023 & (_T_1014 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1014 & _T_2 & ~_T_1023) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1027 & (_T_1014 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1014 & _T_2 & ~_T_1027) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1031 & (_T_1014 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1014 & _T_2 & ~_T_1031) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel sink changed with multibeat operation (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1035 & (_T_1014 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1014 & _T_2 & ~_T_1035) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel denied changed with multibeat operation (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1048 & (_T_1044 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1044 & ~reset & ~_T_1048) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1067 & (_T_1055 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1055 & _T_2 & ~_T_1067) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1073 & (_T_1055 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1055 & same_cycle_resp & _T_2 & ~_T_1073) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1077 & (_T_1055 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1055 & same_cycle_resp & _T_2 & ~_T_1077) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1085 & (_T_1055 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1055 & ~same_cycle_resp & _T_2 & ~_T_1085) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1089 & (_T_1055 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1055 & ~same_cycle_resp & _T_2 & ~_T_1089) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1101 & (_T_1099 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1099 & _T_2 & ~_T_1101) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1108 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_1108) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1117 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_1117) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1151[0] & (_T_1143 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1143 & _T_2 & ~_T_1151[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1161 & (_T_1143 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1143 & _T_2 & ~_T_1161) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1186 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_1186) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[29:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  param_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  size_1 = _RAND_9[2:0];
  _RAND_10 = {1{`RANDOM}};
  source_1 = _RAND_10[1:0];
  _RAND_11 = {1{`RANDOM}};
  sink = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  denied = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  inflight = _RAND_13[2:0];
  _RAND_14 = {1{`RANDOM}};
  inflight_opcodes = _RAND_14[11:0];
  _RAND_15 = {1{`RANDOM}};
  inflight_sizes = _RAND_15[11:0];
  _RAND_16 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_16[3:0];
  _RAND_17 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_17[3:0];
  _RAND_18 = {1{`RANDOM}};
  watchdog = _RAND_18[31:0];
  _RAND_19 = {1{`RANDOM}};
  inflight_1 = _RAND_19[2:0];
  _RAND_20 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_20[11:0];
  _RAND_21 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_21[3:0];
  _RAND_22 = {1{`RANDOM}};
  watchdog_1 = _RAND_22[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [2:0]  io_enq_bits_opcode,
  input  [2:0]  io_enq_bits_param,
  input  [2:0]  io_enq_bits_size,
  input  [1:0]  io_enq_bits_source,
  input  [29:0] io_enq_bits_address,
  input  [3:0]  io_enq_bits_mask,
  input  [31:0] io_enq_bits_data,
  input         io_enq_bits_corrupt,
  input         io_deq_ready,
  output        io_deq_valid,
  output [2:0]  io_deq_bits_opcode,
  output [2:0]  io_deq_bits_param,
  output [2:0]  io_deq_bits_size,
  output [1:0]  io_deq_bits_source,
  output [29:0] io_deq_bits_address,
  output [3:0]  io_deq_bits_mask,
  output [31:0] io_deq_bits_data,
  output        io_deq_bits_corrupt
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
`endif // RANDOMIZE_REG_INIT
  reg [2:0] ram_opcode [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_opcode_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_opcode_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [2:0] ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_en; // @[Decoupled.scala 259:95]
  reg [2:0] ram_param [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_param_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_param_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [2:0] ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_param_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_param_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_param_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_param_MPORT_en; // @[Decoupled.scala 259:95]
  reg [2:0] ram_size [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [2:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_size_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_en; // @[Decoupled.scala 259:95]
  reg [1:0] ram_source [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [1:0] ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [1:0] ram_source_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_en; // @[Decoupled.scala 259:95]
  reg [29:0] ram_address [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_address_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_address_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [29:0] ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [29:0] ram_address_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_address_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_address_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_address_MPORT_en; // @[Decoupled.scala 259:95]
  reg [3:0] ram_mask [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_mask_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_mask_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [3:0] ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [3:0] ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_mask_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_mask_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_mask_MPORT_en; // @[Decoupled.scala 259:95]
  reg [31:0] ram_data [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_data_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_data_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [31:0] ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [31:0] ram_data_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_data_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_data_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_data_MPORT_en; // @[Decoupled.scala 259:95]
  reg  ram_corrupt [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_en; // @[Decoupled.scala 259:95]
  reg  value; // @[Counter.scala 62:40]
  reg  value_1; // @[Counter.scala 62:40]
  reg  maybe_full; // @[Decoupled.scala 262:27]
  wire  ptr_match = value == value_1; // @[Decoupled.scala 263:33]
  wire  empty = ptr_match & ~maybe_full; // @[Decoupled.scala 264:25]
  wire  full = ptr_match & maybe_full; // @[Decoupled.scala 265:24]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
  wire  do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
  assign ram_opcode_io_deq_bits_MPORT_en = 1'h1;
  assign ram_opcode_io_deq_bits_MPORT_addr = value_1;
  assign ram_opcode_io_deq_bits_MPORT_data = ram_opcode[ram_opcode_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_opcode_MPORT_data = io_enq_bits_opcode;
  assign ram_opcode_MPORT_addr = value;
  assign ram_opcode_MPORT_mask = 1'h1;
  assign ram_opcode_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_param_io_deq_bits_MPORT_en = 1'h1;
  assign ram_param_io_deq_bits_MPORT_addr = value_1;
  assign ram_param_io_deq_bits_MPORT_data = ram_param[ram_param_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_param_MPORT_data = io_enq_bits_param;
  assign ram_param_MPORT_addr = value;
  assign ram_param_MPORT_mask = 1'h1;
  assign ram_param_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_size_io_deq_bits_MPORT_en = 1'h1;
  assign ram_size_io_deq_bits_MPORT_addr = value_1;
  assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_size_MPORT_data = io_enq_bits_size;
  assign ram_size_MPORT_addr = value;
  assign ram_size_MPORT_mask = 1'h1;
  assign ram_size_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_source_io_deq_bits_MPORT_en = 1'h1;
  assign ram_source_io_deq_bits_MPORT_addr = value_1;
  assign ram_source_io_deq_bits_MPORT_data = ram_source[ram_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_source_MPORT_data = io_enq_bits_source;
  assign ram_source_MPORT_addr = value;
  assign ram_source_MPORT_mask = 1'h1;
  assign ram_source_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_address_io_deq_bits_MPORT_en = 1'h1;
  assign ram_address_io_deq_bits_MPORT_addr = value_1;
  assign ram_address_io_deq_bits_MPORT_data = ram_address[ram_address_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_address_MPORT_data = io_enq_bits_address;
  assign ram_address_MPORT_addr = value;
  assign ram_address_MPORT_mask = 1'h1;
  assign ram_address_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_mask_io_deq_bits_MPORT_en = 1'h1;
  assign ram_mask_io_deq_bits_MPORT_addr = value_1;
  assign ram_mask_io_deq_bits_MPORT_data = ram_mask[ram_mask_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_mask_MPORT_data = io_enq_bits_mask;
  assign ram_mask_MPORT_addr = value;
  assign ram_mask_MPORT_mask = 1'h1;
  assign ram_mask_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_data_io_deq_bits_MPORT_en = 1'h1;
  assign ram_data_io_deq_bits_MPORT_addr = value_1;
  assign ram_data_io_deq_bits_MPORT_data = ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_data_MPORT_data = io_enq_bits_data;
  assign ram_data_MPORT_addr = value;
  assign ram_data_MPORT_mask = 1'h1;
  assign ram_data_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_corrupt_io_deq_bits_MPORT_en = 1'h1;
  assign ram_corrupt_io_deq_bits_MPORT_addr = value_1;
  assign ram_corrupt_io_deq_bits_MPORT_data = ram_corrupt[ram_corrupt_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_corrupt_MPORT_data = io_enq_bits_corrupt;
  assign ram_corrupt_MPORT_addr = value;
  assign ram_corrupt_MPORT_mask = 1'h1;
  assign ram_corrupt_MPORT_en = io_enq_ready & io_enq_valid;
  assign io_enq_ready = ~full; // @[Decoupled.scala 289:19]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 288:19]
  assign io_deq_bits_opcode = ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_param = ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_size = ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_source = ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_address = ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_mask = ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_data = ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_corrupt = ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  always @(posedge clock) begin
    if (ram_opcode_MPORT_en & ram_opcode_MPORT_mask) begin
      ram_opcode[ram_opcode_MPORT_addr] <= ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_param_MPORT_en & ram_param_MPORT_mask) begin
      ram_param[ram_param_MPORT_addr] <= ram_param_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
      ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_source_MPORT_en & ram_source_MPORT_mask) begin
      ram_source[ram_source_MPORT_addr] <= ram_source_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_address_MPORT_en & ram_address_MPORT_mask) begin
      ram_address[ram_address_MPORT_addr] <= ram_address_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_mask_MPORT_en & ram_mask_MPORT_mask) begin
      ram_mask[ram_mask_MPORT_addr] <= ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_data_MPORT_en & ram_data_MPORT_mask) begin
      ram_data[ram_data_MPORT_addr] <= ram_data_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_corrupt_MPORT_en & ram_corrupt_MPORT_mask) begin
      ram_corrupt[ram_corrupt_MPORT_addr] <= ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (reset) begin // @[Counter.scala 62:40]
      value <= 1'h0; // @[Counter.scala 62:40]
    end else if (do_enq) begin // @[Decoupled.scala 272:16]
      value <= value + 1'h1; // @[Counter.scala 78:15]
    end
    if (reset) begin // @[Counter.scala 62:40]
      value_1 <= 1'h0; // @[Counter.scala 62:40]
    end else if (do_deq) begin // @[Decoupled.scala 276:16]
      value_1 <= value_1 + 1'h1; // @[Counter.scala 78:15]
    end
    if (reset) begin // @[Decoupled.scala 262:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 262:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 279:27]
      maybe_full <= do_enq; // @[Decoupled.scala 280:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_opcode[initvar] = _RAND_0[2:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_param[initvar] = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_size[initvar] = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_source[initvar] = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_address[initvar] = _RAND_4[29:0];
  _RAND_5 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_mask[initvar] = _RAND_5[3:0];
  _RAND_6 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_data[initvar] = _RAND_6[31:0];
  _RAND_7 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_corrupt[initvar] = _RAND_7[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_8 = {1{`RANDOM}};
  value = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  value_1 = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  maybe_full = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_1(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [2:0]  io_enq_bits_opcode,
  input  [1:0]  io_enq_bits_param,
  input  [2:0]  io_enq_bits_size,
  input  [1:0]  io_enq_bits_source,
  input         io_enq_bits_sink,
  input         io_enq_bits_denied,
  input  [31:0] io_enq_bits_data,
  input         io_enq_bits_corrupt,
  input         io_deq_ready,
  output        io_deq_valid,
  output [2:0]  io_deq_bits_opcode,
  output [1:0]  io_deq_bits_param,
  output [2:0]  io_deq_bits_size,
  output [1:0]  io_deq_bits_source,
  output        io_deq_bits_sink,
  output        io_deq_bits_denied,
  output [31:0] io_deq_bits_data,
  output        io_deq_bits_corrupt
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
`endif // RANDOMIZE_REG_INIT
  reg [2:0] ram_opcode [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_opcode_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_opcode_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [2:0] ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_en; // @[Decoupled.scala 259:95]
  reg [1:0] ram_param [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_param_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_param_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [1:0] ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [1:0] ram_param_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_param_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_param_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_param_MPORT_en; // @[Decoupled.scala 259:95]
  reg [2:0] ram_size [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [2:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_size_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_en; // @[Decoupled.scala 259:95]
  reg [1:0] ram_source [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [1:0] ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [1:0] ram_source_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_en; // @[Decoupled.scala 259:95]
  reg  ram_sink [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_sink_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_sink_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_sink_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_sink_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_sink_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_sink_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_sink_MPORT_en; // @[Decoupled.scala 259:95]
  reg  ram_denied [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_denied_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_denied_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_denied_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_denied_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_denied_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_denied_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_denied_MPORT_en; // @[Decoupled.scala 259:95]
  reg [31:0] ram_data [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_data_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_data_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [31:0] ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [31:0] ram_data_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_data_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_data_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_data_MPORT_en; // @[Decoupled.scala 259:95]
  reg  ram_corrupt [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_en; // @[Decoupled.scala 259:95]
  reg  value; // @[Counter.scala 62:40]
  reg  value_1; // @[Counter.scala 62:40]
  reg  maybe_full; // @[Decoupled.scala 262:27]
  wire  ptr_match = value == value_1; // @[Decoupled.scala 263:33]
  wire  empty = ptr_match & ~maybe_full; // @[Decoupled.scala 264:25]
  wire  full = ptr_match & maybe_full; // @[Decoupled.scala 265:24]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
  wire  do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
  assign ram_opcode_io_deq_bits_MPORT_en = 1'h1;
  assign ram_opcode_io_deq_bits_MPORT_addr = value_1;
  assign ram_opcode_io_deq_bits_MPORT_data = ram_opcode[ram_opcode_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_opcode_MPORT_data = io_enq_bits_opcode;
  assign ram_opcode_MPORT_addr = value;
  assign ram_opcode_MPORT_mask = 1'h1;
  assign ram_opcode_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_param_io_deq_bits_MPORT_en = 1'h1;
  assign ram_param_io_deq_bits_MPORT_addr = value_1;
  assign ram_param_io_deq_bits_MPORT_data = ram_param[ram_param_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_param_MPORT_data = io_enq_bits_param;
  assign ram_param_MPORT_addr = value;
  assign ram_param_MPORT_mask = 1'h1;
  assign ram_param_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_size_io_deq_bits_MPORT_en = 1'h1;
  assign ram_size_io_deq_bits_MPORT_addr = value_1;
  assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_size_MPORT_data = io_enq_bits_size;
  assign ram_size_MPORT_addr = value;
  assign ram_size_MPORT_mask = 1'h1;
  assign ram_size_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_source_io_deq_bits_MPORT_en = 1'h1;
  assign ram_source_io_deq_bits_MPORT_addr = value_1;
  assign ram_source_io_deq_bits_MPORT_data = ram_source[ram_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_source_MPORT_data = io_enq_bits_source;
  assign ram_source_MPORT_addr = value;
  assign ram_source_MPORT_mask = 1'h1;
  assign ram_source_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_sink_io_deq_bits_MPORT_en = 1'h1;
  assign ram_sink_io_deq_bits_MPORT_addr = value_1;
  assign ram_sink_io_deq_bits_MPORT_data = ram_sink[ram_sink_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_sink_MPORT_data = io_enq_bits_sink;
  assign ram_sink_MPORT_addr = value;
  assign ram_sink_MPORT_mask = 1'h1;
  assign ram_sink_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_denied_io_deq_bits_MPORT_en = 1'h1;
  assign ram_denied_io_deq_bits_MPORT_addr = value_1;
  assign ram_denied_io_deq_bits_MPORT_data = ram_denied[ram_denied_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_denied_MPORT_data = io_enq_bits_denied;
  assign ram_denied_MPORT_addr = value;
  assign ram_denied_MPORT_mask = 1'h1;
  assign ram_denied_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_data_io_deq_bits_MPORT_en = 1'h1;
  assign ram_data_io_deq_bits_MPORT_addr = value_1;
  assign ram_data_io_deq_bits_MPORT_data = ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_data_MPORT_data = io_enq_bits_data;
  assign ram_data_MPORT_addr = value;
  assign ram_data_MPORT_mask = 1'h1;
  assign ram_data_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_corrupt_io_deq_bits_MPORT_en = 1'h1;
  assign ram_corrupt_io_deq_bits_MPORT_addr = value_1;
  assign ram_corrupt_io_deq_bits_MPORT_data = ram_corrupt[ram_corrupt_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_corrupt_MPORT_data = io_enq_bits_corrupt;
  assign ram_corrupt_MPORT_addr = value;
  assign ram_corrupt_MPORT_mask = 1'h1;
  assign ram_corrupt_MPORT_en = io_enq_ready & io_enq_valid;
  assign io_enq_ready = ~full; // @[Decoupled.scala 289:19]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 288:19]
  assign io_deq_bits_opcode = ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_param = ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_size = ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_source = ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_sink = ram_sink_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_denied = ram_denied_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_data = ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_corrupt = ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  always @(posedge clock) begin
    if (ram_opcode_MPORT_en & ram_opcode_MPORT_mask) begin
      ram_opcode[ram_opcode_MPORT_addr] <= ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_param_MPORT_en & ram_param_MPORT_mask) begin
      ram_param[ram_param_MPORT_addr] <= ram_param_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
      ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_source_MPORT_en & ram_source_MPORT_mask) begin
      ram_source[ram_source_MPORT_addr] <= ram_source_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_sink_MPORT_en & ram_sink_MPORT_mask) begin
      ram_sink[ram_sink_MPORT_addr] <= ram_sink_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_denied_MPORT_en & ram_denied_MPORT_mask) begin
      ram_denied[ram_denied_MPORT_addr] <= ram_denied_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_data_MPORT_en & ram_data_MPORT_mask) begin
      ram_data[ram_data_MPORT_addr] <= ram_data_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_corrupt_MPORT_en & ram_corrupt_MPORT_mask) begin
      ram_corrupt[ram_corrupt_MPORT_addr] <= ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (reset) begin // @[Counter.scala 62:40]
      value <= 1'h0; // @[Counter.scala 62:40]
    end else if (do_enq) begin // @[Decoupled.scala 272:16]
      value <= value + 1'h1; // @[Counter.scala 78:15]
    end
    if (reset) begin // @[Counter.scala 62:40]
      value_1 <= 1'h0; // @[Counter.scala 62:40]
    end else if (do_deq) begin // @[Decoupled.scala 276:16]
      value_1 <= value_1 + 1'h1; // @[Counter.scala 78:15]
    end
    if (reset) begin // @[Decoupled.scala 262:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 262:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 279:27]
      maybe_full <= do_enq; // @[Decoupled.scala 280:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_opcode[initvar] = _RAND_0[2:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_param[initvar] = _RAND_1[1:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_size[initvar] = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_source[initvar] = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_sink[initvar] = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_denied[initvar] = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_data[initvar] = _RAND_6[31:0];
  _RAND_7 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_corrupt[initvar] = _RAND_7[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_8 = {1{`RANDOM}};
  value = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  value_1 = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  maybe_full = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLBuffer(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [29:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [1:0]  auto_in_d_bits_param,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output        auto_in_d_bits_sink,
  output        auto_in_d_bits_denied,
  output [31:0] auto_in_d_bits_data,
  output        auto_in_d_bits_corrupt,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [2:0]  auto_out_a_bits_size,
  output [1:0]  auto_out_a_bits_source,
  output [29:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [2:0]  auto_out_d_bits_size,
  input  [1:0]  auto_out_d_bits_source,
  input  [31:0] auto_out_d_bits_data
);
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [29:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
  wire  bundleOut_0_a_q_clock; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_reset; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_enq_ready; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_enq_valid; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
  wire [1:0] bundleOut_0_a_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
  wire [29:0] bundleOut_0_a_q_io_enq_bits_address; // @[Decoupled.scala 361:21]
  wire [3:0] bundleOut_0_a_q_io_enq_bits_mask; // @[Decoupled.scala 361:21]
  wire [31:0] bundleOut_0_a_q_io_enq_bits_data; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_enq_bits_corrupt; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_deq_ready; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_deq_valid; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
  wire [1:0] bundleOut_0_a_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
  wire [29:0] bundleOut_0_a_q_io_deq_bits_address; // @[Decoupled.scala 361:21]
  wire [3:0] bundleOut_0_a_q_io_deq_bits_mask; // @[Decoupled.scala 361:21]
  wire [31:0] bundleOut_0_a_q_io_deq_bits_data; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_clock; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_reset; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_enq_ready; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_enq_valid; // @[Decoupled.scala 361:21]
  wire [2:0] bundleIn_0_d_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
  wire [1:0] bundleIn_0_d_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
  wire [2:0] bundleIn_0_d_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
  wire [1:0] bundleIn_0_d_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_enq_bits_sink; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_enq_bits_denied; // @[Decoupled.scala 361:21]
  wire [31:0] bundleIn_0_d_q_io_enq_bits_data; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_enq_bits_corrupt; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_deq_ready; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_deq_valid; // @[Decoupled.scala 361:21]
  wire [2:0] bundleIn_0_d_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
  wire [1:0] bundleIn_0_d_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
  wire [2:0] bundleIn_0_d_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
  wire [1:0] bundleIn_0_d_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_deq_bits_sink; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_deq_bits_denied; // @[Decoupled.scala 361:21]
  wire [31:0] bundleIn_0_d_q_io_deq_bits_data; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
  TLMonitor_4 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_param(monitor_io_in_d_bits_param),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source),
    .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
    .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
    .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
  );
  Queue bundleOut_0_a_q ( // @[Decoupled.scala 361:21]
    .clock(bundleOut_0_a_q_clock),
    .reset(bundleOut_0_a_q_reset),
    .io_enq_ready(bundleOut_0_a_q_io_enq_ready),
    .io_enq_valid(bundleOut_0_a_q_io_enq_valid),
    .io_enq_bits_opcode(bundleOut_0_a_q_io_enq_bits_opcode),
    .io_enq_bits_param(bundleOut_0_a_q_io_enq_bits_param),
    .io_enq_bits_size(bundleOut_0_a_q_io_enq_bits_size),
    .io_enq_bits_source(bundleOut_0_a_q_io_enq_bits_source),
    .io_enq_bits_address(bundleOut_0_a_q_io_enq_bits_address),
    .io_enq_bits_mask(bundleOut_0_a_q_io_enq_bits_mask),
    .io_enq_bits_data(bundleOut_0_a_q_io_enq_bits_data),
    .io_enq_bits_corrupt(bundleOut_0_a_q_io_enq_bits_corrupt),
    .io_deq_ready(bundleOut_0_a_q_io_deq_ready),
    .io_deq_valid(bundleOut_0_a_q_io_deq_valid),
    .io_deq_bits_opcode(bundleOut_0_a_q_io_deq_bits_opcode),
    .io_deq_bits_param(bundleOut_0_a_q_io_deq_bits_param),
    .io_deq_bits_size(bundleOut_0_a_q_io_deq_bits_size),
    .io_deq_bits_source(bundleOut_0_a_q_io_deq_bits_source),
    .io_deq_bits_address(bundleOut_0_a_q_io_deq_bits_address),
    .io_deq_bits_mask(bundleOut_0_a_q_io_deq_bits_mask),
    .io_deq_bits_data(bundleOut_0_a_q_io_deq_bits_data),
    .io_deq_bits_corrupt(bundleOut_0_a_q_io_deq_bits_corrupt)
  );
  Queue_1 bundleIn_0_d_q ( // @[Decoupled.scala 361:21]
    .clock(bundleIn_0_d_q_clock),
    .reset(bundleIn_0_d_q_reset),
    .io_enq_ready(bundleIn_0_d_q_io_enq_ready),
    .io_enq_valid(bundleIn_0_d_q_io_enq_valid),
    .io_enq_bits_opcode(bundleIn_0_d_q_io_enq_bits_opcode),
    .io_enq_bits_param(bundleIn_0_d_q_io_enq_bits_param),
    .io_enq_bits_size(bundleIn_0_d_q_io_enq_bits_size),
    .io_enq_bits_source(bundleIn_0_d_q_io_enq_bits_source),
    .io_enq_bits_sink(bundleIn_0_d_q_io_enq_bits_sink),
    .io_enq_bits_denied(bundleIn_0_d_q_io_enq_bits_denied),
    .io_enq_bits_data(bundleIn_0_d_q_io_enq_bits_data),
    .io_enq_bits_corrupt(bundleIn_0_d_q_io_enq_bits_corrupt),
    .io_deq_ready(bundleIn_0_d_q_io_deq_ready),
    .io_deq_valid(bundleIn_0_d_q_io_deq_valid),
    .io_deq_bits_opcode(bundleIn_0_d_q_io_deq_bits_opcode),
    .io_deq_bits_param(bundleIn_0_d_q_io_deq_bits_param),
    .io_deq_bits_size(bundleIn_0_d_q_io_deq_bits_size),
    .io_deq_bits_source(bundleIn_0_d_q_io_deq_bits_source),
    .io_deq_bits_sink(bundleIn_0_d_q_io_deq_bits_sink),
    .io_deq_bits_denied(bundleIn_0_d_q_io_deq_bits_denied),
    .io_deq_bits_data(bundleIn_0_d_q_io_deq_bits_data),
    .io_deq_bits_corrupt(bundleIn_0_d_q_io_deq_bits_corrupt)
  );
  assign auto_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
  assign auto_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_param = bundleIn_0_d_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_source = bundleIn_0_d_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_sink = bundleIn_0_d_q_io_deq_bits_sink; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_denied = bundleIn_0_d_q_io_deq_bits_denied; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_data = bundleIn_0_d_q_io_deq_bits_data; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_corrupt = bundleIn_0_d_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_out_a_valid = bundleOut_0_a_q_io_deq_valid; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_opcode = bundleOut_0_a_q_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_param = bundleOut_0_a_q_io_deq_bits_param; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_size = bundleOut_0_a_q_io_deq_bits_size; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_source = bundleOut_0_a_q_io_deq_bits_source; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_address = bundleOut_0_a_q_io_deq_bits_address; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_mask = bundleOut_0_a_q_io_deq_bits_mask; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_data = bundleOut_0_a_q_io_deq_bits_data; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_corrupt = bundleOut_0_a_q_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_d_ready = bundleIn_0_d_q_io_enq_ready; // @[Nodes.scala 1207:84 Decoupled.scala 365:17]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_param = bundleIn_0_d_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_source = bundleIn_0_d_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_sink = bundleIn_0_d_q_io_deq_bits_sink; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_denied = bundleIn_0_d_q_io_deq_bits_denied; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_corrupt = bundleIn_0_d_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign bundleOut_0_a_q_clock = clock;
  assign bundleOut_0_a_q_reset = reset;
  assign bundleOut_0_a_q_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_clock = clock;
  assign bundleIn_0_d_q_reset = reset;
  assign bundleIn_0_d_q_io_enq_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_param = 2'h0; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_sink = 1'h0; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_denied = 1'h0; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_corrupt = 1'h0; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_deq_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module TLMonitor_5(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [29:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_param,
  input  [2:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source,
  input         io_in_d_bits_sink,
  input         io_in_d_bits_denied,
  input         io_in_d_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
  wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
  wire [29:0] _GEN_71 = {{24'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [29:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 30'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [29:0] _T_45 = io_in_a_bits_address ^ 30'h10012000; // @[Parameters.scala 137:31]
  wire [30:0] _T_46 = {1'b0,$signed(_T_45)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_48 = $signed(_T_46) & -31'sh2000; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_50 = io_in_a_bits_address ^ 30'h10014000; // @[Parameters.scala 137:31]
  wire [30:0] _T_51 = {1'b0,$signed(_T_50)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_53 = $signed(_T_51) & -31'sh2000; // @[Parameters.scala 137:52]
  wire  _T_54 = $signed(_T_53) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_55 = io_in_a_bits_address ^ 30'h10016000; // @[Parameters.scala 137:31]
  wire [30:0] _T_56 = {1'b0,$signed(_T_55)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_58 = $signed(_T_56) & -31'sh1000; // @[Parameters.scala 137:52]
  wire  _T_59 = $signed(_T_58) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_60 = io_in_a_bits_address ^ 30'h10023000; // @[Parameters.scala 137:31]
  wire [30:0] _T_61 = {1'b0,$signed(_T_60)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_63 = $signed(_T_61) & -31'sh11000; // @[Parameters.scala 137:52]
  wire  _T_64 = $signed(_T_63) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_65 = io_in_a_bits_address ^ 30'h10024000; // @[Parameters.scala 137:31]
  wire [30:0] _T_66 = {1'b0,$signed(_T_65)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_68 = $signed(_T_66) & -31'sh12000; // @[Parameters.scala 137:52]
  wire  _T_69 = $signed(_T_68) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_70 = io_in_a_bits_address ^ 30'h10026000; // @[Parameters.scala 137:31]
  wire [30:0] _T_71 = {1'b0,$signed(_T_70)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_73 = $signed(_T_71) & -31'sh1000; // @[Parameters.scala 137:52]
  wire  _T_74 = $signed(_T_73) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_75 = io_in_a_bits_address ^ 30'h10043000; // @[Parameters.scala 137:31]
  wire [30:0] _T_76 = {1'b0,$signed(_T_75)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_78 = $signed(_T_76) & -31'sh11000; // @[Parameters.scala 137:52]
  wire  _T_79 = $signed(_T_78) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_80 = io_in_a_bits_address ^ 30'h20000000; // @[Parameters.scala 137:31]
  wire [30:0] _T_81 = {1'b0,$signed(_T_80)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_83 = $signed(_T_81) & -31'sh20000000; // @[Parameters.scala 137:52]
  wire  _T_84 = $signed(_T_83) == 31'sh0; // @[Parameters.scala 137:67]
  wire  _T_90 = _T_49 | _T_54 | _T_59 | _T_64 | _T_69 | _T_74 | _T_79; // @[Parameters.scala 671:42]
  wire  _T_91 = _T_49 | _T_54 | _T_59 | _T_64 | _T_69 | _T_74 | _T_79 | _T_84; // @[Parameters.scala 671:42]
  wire  _T_101 = 3'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_102 = _source_ok_T & _T_101; // @[Mux.scala 27:73]
  wire  _T_160 = _T_102 & _T_91; // @[Monitor.scala 83:78]
  wire  _T_174 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_178 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_179 = _T_178 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_183 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_187 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_332 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_345 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_360 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
  wire  _T_410 = _T_360 & _T_91; // @[Parameters.scala 670:56]
  wire  _T_421 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_425 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_433 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_489 = _T_360 & _T_90; // @[Parameters.scala 670:56]
  wire  _T_499 = source_ok & _T_489; // @[Monitor.scala 115:71]
  wire  _T_517 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_597 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_598 = io_in_a_bits_mask & _T_597; // @[Monitor.scala 127:31]
  wire  _T_599 = _T_598 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_603 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_615 = io_in_a_bits_size <= 3'h2; // @[Parameters.scala 92:42]
  wire  _T_659 = _T_615 & _T_90; // @[Parameters.scala 670:56]
  wire  _T_669 = source_ok & _T_659; // @[Monitor.scala 131:74]
  wire  _T_679 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_687 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_763 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_771 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_842 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_854 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  _T_858 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_862 = io_in_d_bits_size >= 3'h2; // @[Monitor.scala 312:27]
  wire  _T_866 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
  wire  _T_870 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
  wire  _T_874 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
  wire  _T_878 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_889 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
  wire  _T_893 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
  wire  _T_906 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_926 = _T_874 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
  wire  _T_935 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_952 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_970 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [3:0] a_first_beats1_decode = is_aligned_mask[5:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] a_first_counter; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1 = a_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [29:0] address; // @[Monitor.scala 388:22]
  wire  _T_1000 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_1001 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_1005 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_1009 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_1013 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_1017 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
  wire [3:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [3:0] d_first_counter; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1 = d_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] param_1; // @[Monitor.scala 536:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  reg  sink; // @[Monitor.scala 539:22]
  reg  denied; // @[Monitor.scala 540:22]
  wire  _T_1024 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_1025 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_1029 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
  wire  _T_1033 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_1037 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  wire  _T_1041 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
  wire  _T_1045 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [11:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [3:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1_1 = a_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  reg [3:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_1 = d_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [11:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _GEN_76 = {{4'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_76 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_1051 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_1054 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [34:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [34:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_1056 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_1058 = ~_T_1056[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [34:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_1062 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_1064 = ~_T_858; // @[Monitor.scala 671:74]
  wire  _T_1065 = io_in_d_valid & d_first_1 & ~_T_858; // @[Monitor.scala 671:71]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_858 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 671:90 672:22]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [3:0] _GEN_22 = _d_first_T & d_first_1 & _T_1064 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_23 = _d_first_T & d_first_1 & _T_1064 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_1051 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_1075 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_1077 = _T_1075[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_1082 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_1083 = io_in_d_bits_opcode == _GEN_32 | _T_1082; // @[Monitor.scala 685:77]
  wire  _T_1087 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_1094 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_1095 = io_in_d_bits_opcode == _GEN_48 | _T_1094; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_1099 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_1109 = _T_1062 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_1064; // @[Monitor.scala 694:116]
  wire  _T_1111 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set_wo_ready = _GEN_15[2:0];
  wire [2:0] d_clr_wo_ready = _GEN_21[2:0];
  wire  _T_1118 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire [2:0] a_set = _GEN_16[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_22[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_19[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_23[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [11:0] a_sizes_set = _GEN_20[11:0];
  wire [11:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [11:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_1127 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [2:0] inflight_1; // @[Monitor.scala 723:35]
  reg [11:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [3:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_2 = d_first_counter_2 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 4'h0; // @[Edges.scala 230:25]
  wire [11:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [15:0] _GEN_87 = {{4'd0}, _c_size_lookup_T_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_87 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_1153 = io_in_d_valid & d_first_2 & _T_858; // @[Monitor.scala 779:71]
  wire [3:0] _GEN_67 = _d_first_T & d_first_2 & _T_858 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 783:90 784:21]
  wire [46:0] _GEN_68 = _d_first_T & d_first_2 & _T_858 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 785:21]
  wire [2:0] _T_1161 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_1171 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [2:0] d_clr_1 = _GEN_67[2:0];
  wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [2:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [11:0] d_opcodes_clr_1 = _GEN_68[11:0];
  wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [11:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_1196 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 4'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 4'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 12'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 4'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 4'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 3'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 12'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 4'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_160 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_160) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_174 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_174) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_179 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_179) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_160 & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~_T_160) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_174 & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~_T_174) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_332 & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~_T_332) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_179 & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~_T_179) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_410 & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~_T_410) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_421 & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~_T_421) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_425 & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~_T_425) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_499 & (io_in_a_valid & _T_433 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_433 & ~reset & ~_T_499) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_433 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_433 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_433 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_433 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_421 & (io_in_a_valid & _T_433 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_433 & ~reset & ~_T_421) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_425 & (io_in_a_valid & _T_433 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_433 & ~reset & ~_T_425) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_499 & (io_in_a_valid & _T_517 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_517 & ~reset & ~_T_499) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_517 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_517 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_517 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_517 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_421 & (io_in_a_valid & _T_517 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_517 & ~reset & ~_T_421) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_599 & (io_in_a_valid & _T_517 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_517 & ~reset & ~_T_599) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_669 & (io_in_a_valid & _T_603 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_603 & ~reset & ~_T_669) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_603 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_603 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_603 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_603 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_679 & (io_in_a_valid & _T_603 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_603 & ~reset & ~_T_679) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_425 & (io_in_a_valid & _T_603 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_603 & ~reset & ~_T_425) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_669 & (io_in_a_valid & _T_687 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_687 & ~reset & ~_T_669) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_687 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_687 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_687 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_687 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_763 & (io_in_a_valid & _T_687 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_687 & ~reset & ~_T_763) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_425 & (io_in_a_valid & _T_687 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_687 & ~reset & ~_T_425) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_771 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_771 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_771 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_771 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_771 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_771 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_842 & (io_in_a_valid & _T_771 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_771 & ~reset & ~_T_842) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_425 & (io_in_a_valid & _T_771 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_771 & ~reset & ~_T_425) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_771 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_771 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_854 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_854) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_858 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_858 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_862 & (io_in_d_valid & _T_858 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_858 & _T_2 & ~_T_862) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_866 & (io_in_d_valid & _T_858 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_858 & _T_2 & ~_T_866) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_870 & (io_in_d_valid & _T_858 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_858 & _T_2 & ~_T_870) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_874 & (io_in_d_valid & _T_858 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_858 & _T_2 & ~_T_874) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is denied (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_878 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_878 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_878 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_878 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_862 & (io_in_d_valid & _T_878 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_878 & _T_2 & ~_T_862) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_889 & (io_in_d_valid & _T_878 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_878 & _T_2 & ~_T_889) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid cap param (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_893 & (io_in_d_valid & _T_878 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_878 & _T_2 & ~_T_893) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries toN param (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_870 & (io_in_d_valid & _T_878 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_878 & _T_2 & ~_T_870) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is corrupt (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_874 & (io_in_d_valid & _T_878 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_878 & _T_2 & ~_T_874) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is denied (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_906 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_906 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_906 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_906 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_862 & (io_in_d_valid & _T_906 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_906 & _T_2 & ~_T_862) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_889 & (io_in_d_valid & _T_906 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_906 & _T_2 & ~_T_889) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_893 & (io_in_d_valid & _T_906 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_906 & _T_2 & ~_T_893) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries toN param (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_926 & (io_in_d_valid & _T_906 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_906 & _T_2 & ~_T_926) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_874 & (io_in_d_valid & _T_906 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_906 & _T_2 & ~_T_874) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_935 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_935 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_866 & (io_in_d_valid & _T_935 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_935 & _T_2 & ~_T_866) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid param (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_870 & (io_in_d_valid & _T_935 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_935 & _T_2 & ~_T_870) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is corrupt (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_874 & (io_in_d_valid & _T_935 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_935 & _T_2 & ~_T_874) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is denied (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_952 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_952 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_866 & (io_in_d_valid & _T_952 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_952 & _T_2 & ~_T_866) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_926 & (io_in_d_valid & _T_952 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_952 & _T_2 & ~_T_926) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_874 & (io_in_d_valid & _T_952 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_952 & _T_2 & ~_T_874) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_970 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_970 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_866 & (io_in_d_valid & _T_970 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_970 & _T_2 & ~_T_866) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid param (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_870 & (io_in_d_valid & _T_970 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_970 & _T_2 & ~_T_870) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is corrupt (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_874 & (io_in_d_valid & _T_970 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_970 & _T_2 & ~_T_874) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is denied (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1001 & (_T_1000 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1000 & ~reset & ~_T_1001) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1005 & (_T_1000 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1000 & ~reset & ~_T_1005) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1009 & (_T_1000 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1000 & ~reset & ~_T_1009) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1013 & (_T_1000 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1000 & ~reset & ~_T_1013) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1017 & (_T_1000 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1000 & ~reset & ~_T_1017) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1025 & (_T_1024 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1024 & _T_2 & ~_T_1025) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1029 & (_T_1024 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1024 & _T_2 & ~_T_1029) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel param changed within multibeat operation (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1033 & (_T_1024 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1024 & _T_2 & ~_T_1033) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1037 & (_T_1024 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1024 & _T_2 & ~_T_1037) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1041 & (_T_1024 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1024 & _T_2 & ~_T_1041) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel sink changed with multibeat operation (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1045 & (_T_1024 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1024 & _T_2 & ~_T_1045) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel denied changed with multibeat operation (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1058 & (_T_1054 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1054 & ~reset & ~_T_1058) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1077 & (_T_1065 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1065 & _T_2 & ~_T_1077) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1083 & (_T_1065 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1065 & same_cycle_resp & _T_2 & ~_T_1083) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1087 & (_T_1065 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1065 & same_cycle_resp & _T_2 & ~_T_1087) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1095 & (_T_1065 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1065 & ~same_cycle_resp & _T_2 & ~_T_1095) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1099 & (_T_1065 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1065 & ~same_cycle_resp & _T_2 & ~_T_1099) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1111 & (_T_1109 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1109 & _T_2 & ~_T_1111) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1118 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_1118) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1127 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_1127) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1161[0] & (_T_1153 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1153 & _T_2 & ~_T_1161[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1171 & (_T_1153 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1153 & _T_2 & ~_T_1171) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1196 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_1196) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[29:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  param_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  size_1 = _RAND_9[2:0];
  _RAND_10 = {1{`RANDOM}};
  source_1 = _RAND_10[1:0];
  _RAND_11 = {1{`RANDOM}};
  sink = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  denied = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  inflight = _RAND_13[2:0];
  _RAND_14 = {1{`RANDOM}};
  inflight_opcodes = _RAND_14[11:0];
  _RAND_15 = {1{`RANDOM}};
  inflight_sizes = _RAND_15[11:0];
  _RAND_16 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_16[3:0];
  _RAND_17 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_17[3:0];
  _RAND_18 = {1{`RANDOM}};
  watchdog = _RAND_18[31:0];
  _RAND_19 = {1{`RANDOM}};
  inflight_1 = _RAND_19[2:0];
  _RAND_20 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_20[11:0];
  _RAND_21 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_21[3:0];
  _RAND_22 = {1{`RANDOM}};
  watchdog_1 = _RAND_22[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLAtomicAutomata(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [29:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [1:0]  auto_in_d_bits_param,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output        auto_in_d_bits_sink,
  output        auto_in_d_bits_denied,
  output [31:0] auto_in_d_bits_data,
  output        auto_in_d_bits_corrupt,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [2:0]  auto_out_a_bits_size,
  output [1:0]  auto_out_a_bits_source,
  output [29:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_param,
  input  [2:0]  auto_out_d_bits_size,
  input  [1:0]  auto_out_d_bits_source,
  input         auto_out_d_bits_sink,
  input         auto_out_d_bits_denied,
  input  [31:0] auto_out_d_bits_data,
  input         auto_out_d_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [29:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
  reg [1:0] cam_s_0_state; // @[AtomicAutomata.scala 76:28]
  reg [2:0] cam_a_0_bits_opcode; // @[AtomicAutomata.scala 77:24]
  reg [2:0] cam_a_0_bits_param; // @[AtomicAutomata.scala 77:24]
  reg [2:0] cam_a_0_bits_size; // @[AtomicAutomata.scala 77:24]
  reg [1:0] cam_a_0_bits_source; // @[AtomicAutomata.scala 77:24]
  reg [29:0] cam_a_0_bits_address; // @[AtomicAutomata.scala 77:24]
  reg [3:0] cam_a_0_bits_mask; // @[AtomicAutomata.scala 77:24]
  reg [31:0] cam_a_0_bits_data; // @[AtomicAutomata.scala 77:24]
  reg  cam_a_0_bits_corrupt; // @[AtomicAutomata.scala 77:24]
  reg [3:0] cam_a_0_lut; // @[AtomicAutomata.scala 77:24]
  reg [31:0] cam_d_0_data; // @[AtomicAutomata.scala 78:24]
  reg  cam_d_0_denied; // @[AtomicAutomata.scala 78:24]
  reg  cam_d_0_corrupt; // @[AtomicAutomata.scala 78:24]
  wire  cam_free_0 = cam_s_0_state == 2'h0; // @[AtomicAutomata.scala 80:44]
  wire  cam_amo_0 = cam_s_0_state == 2'h2; // @[AtomicAutomata.scala 81:44]
  wire  cam_abusy_0 = cam_s_0_state == 2'h3 | cam_amo_0; // @[AtomicAutomata.scala 82:57]
  wire  cam_dmatch_0 = cam_s_0_state != 2'h0; // @[AtomicAutomata.scala 83:49]
  wire  a_isLogical = auto_in_a_bits_opcode == 3'h3; // @[AtomicAutomata.scala 90:47]
  wire  a_isArithmetic = auto_in_a_bits_opcode == 3'h2; // @[AtomicAutomata.scala 91:47]
  wire  _a_isSupported_T = a_isArithmetic ? 1'h0 : 1'h1; // @[AtomicAutomata.scala 92:63]
  wire  a_isSupported = a_isLogical ? 1'h0 : _a_isSupported_T; // @[AtomicAutomata.scala 92:32]
  wire [1:0] indexes_0 = {cam_a_0_bits_data[0],cam_d_0_data[0]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_1 = {cam_a_0_bits_data[1],cam_d_0_data[1]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_2 = {cam_a_0_bits_data[2],cam_d_0_data[2]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_3 = {cam_a_0_bits_data[3],cam_d_0_data[3]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_4 = {cam_a_0_bits_data[4],cam_d_0_data[4]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_5 = {cam_a_0_bits_data[5],cam_d_0_data[5]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_6 = {cam_a_0_bits_data[6],cam_d_0_data[6]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_7 = {cam_a_0_bits_data[7],cam_d_0_data[7]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_8 = {cam_a_0_bits_data[8],cam_d_0_data[8]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_9 = {cam_a_0_bits_data[9],cam_d_0_data[9]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_10 = {cam_a_0_bits_data[10],cam_d_0_data[10]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_11 = {cam_a_0_bits_data[11],cam_d_0_data[11]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_12 = {cam_a_0_bits_data[12],cam_d_0_data[12]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_13 = {cam_a_0_bits_data[13],cam_d_0_data[13]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_14 = {cam_a_0_bits_data[14],cam_d_0_data[14]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_15 = {cam_a_0_bits_data[15],cam_d_0_data[15]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_16 = {cam_a_0_bits_data[16],cam_d_0_data[16]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_17 = {cam_a_0_bits_data[17],cam_d_0_data[17]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_18 = {cam_a_0_bits_data[18],cam_d_0_data[18]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_19 = {cam_a_0_bits_data[19],cam_d_0_data[19]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_20 = {cam_a_0_bits_data[20],cam_d_0_data[20]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_21 = {cam_a_0_bits_data[21],cam_d_0_data[21]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_22 = {cam_a_0_bits_data[22],cam_d_0_data[22]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_23 = {cam_a_0_bits_data[23],cam_d_0_data[23]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_24 = {cam_a_0_bits_data[24],cam_d_0_data[24]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_25 = {cam_a_0_bits_data[25],cam_d_0_data[25]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_26 = {cam_a_0_bits_data[26],cam_d_0_data[26]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_27 = {cam_a_0_bits_data[27],cam_d_0_data[27]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_28 = {cam_a_0_bits_data[28],cam_d_0_data[28]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_29 = {cam_a_0_bits_data[29],cam_d_0_data[29]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_30 = {cam_a_0_bits_data[30],cam_d_0_data[30]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_31 = {cam_a_0_bits_data[31],cam_d_0_data[31]}; // @[Cat.scala 31:58]
  wire [3:0] _logic_out_T = cam_a_0_lut >> indexes_0; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_2 = cam_a_0_lut >> indexes_1; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_4 = cam_a_0_lut >> indexes_2; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_6 = cam_a_0_lut >> indexes_3; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_8 = cam_a_0_lut >> indexes_4; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_10 = cam_a_0_lut >> indexes_5; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_12 = cam_a_0_lut >> indexes_6; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_14 = cam_a_0_lut >> indexes_7; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_16 = cam_a_0_lut >> indexes_8; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_18 = cam_a_0_lut >> indexes_9; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_20 = cam_a_0_lut >> indexes_10; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_22 = cam_a_0_lut >> indexes_11; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_24 = cam_a_0_lut >> indexes_12; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_26 = cam_a_0_lut >> indexes_13; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_28 = cam_a_0_lut >> indexes_14; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_30 = cam_a_0_lut >> indexes_15; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_32 = cam_a_0_lut >> indexes_16; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_34 = cam_a_0_lut >> indexes_17; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_36 = cam_a_0_lut >> indexes_18; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_38 = cam_a_0_lut >> indexes_19; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_40 = cam_a_0_lut >> indexes_20; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_42 = cam_a_0_lut >> indexes_21; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_44 = cam_a_0_lut >> indexes_22; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_46 = cam_a_0_lut >> indexes_23; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_48 = cam_a_0_lut >> indexes_24; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_50 = cam_a_0_lut >> indexes_25; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_52 = cam_a_0_lut >> indexes_26; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_54 = cam_a_0_lut >> indexes_27; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_56 = cam_a_0_lut >> indexes_28; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_58 = cam_a_0_lut >> indexes_29; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_60 = cam_a_0_lut >> indexes_30; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_62 = cam_a_0_lut >> indexes_31; // @[AtomicAutomata.scala 114:57]
  wire [7:0] logic_out_lo_lo = {_logic_out_T_14[0],_logic_out_T_12[0],_logic_out_T_10[0],_logic_out_T_8[0],
    _logic_out_T_6[0],_logic_out_T_4[0],_logic_out_T_2[0],_logic_out_T[0]}; // @[Cat.scala 31:58]
  wire [15:0] logic_out_lo = {_logic_out_T_30[0],_logic_out_T_28[0],_logic_out_T_26[0],_logic_out_T_24[0],
    _logic_out_T_22[0],_logic_out_T_20[0],_logic_out_T_18[0],_logic_out_T_16[0],logic_out_lo_lo}; // @[Cat.scala 31:58]
  wire [7:0] logic_out_hi_lo = {_logic_out_T_46[0],_logic_out_T_44[0],_logic_out_T_42[0],_logic_out_T_40[0],
    _logic_out_T_38[0],_logic_out_T_36[0],_logic_out_T_34[0],_logic_out_T_32[0]}; // @[Cat.scala 31:58]
  wire [31:0] logic_out = {_logic_out_T_62[0],_logic_out_T_60[0],_logic_out_T_58[0],_logic_out_T_56[0],_logic_out_T_54[0
    ],_logic_out_T_52[0],_logic_out_T_50[0],_logic_out_T_48[0],logic_out_hi_lo,logic_out_lo}; // @[Cat.scala 31:58]
  wire  unsigned_ = cam_a_0_bits_param[1]; // @[AtomicAutomata.scala 117:42]
  wire  take_max = cam_a_0_bits_param[0]; // @[AtomicAutomata.scala 118:42]
  wire  adder = cam_a_0_bits_param[2]; // @[AtomicAutomata.scala 119:39]
  wire [3:0] _signSel_T = ~cam_a_0_bits_mask; // @[AtomicAutomata.scala 121:25]
  wire [3:0] _GEN_39 = {{1'd0}, cam_a_0_bits_mask[3:1]}; // @[AtomicAutomata.scala 121:31]
  wire [3:0] _signSel_T_2 = _signSel_T | _GEN_39; // @[AtomicAutomata.scala 121:31]
  wire [3:0] signSel = ~_signSel_T_2; // @[AtomicAutomata.scala 121:23]
  wire [3:0] signbits_a = {cam_a_0_bits_data[31],cam_a_0_bits_data[23],cam_a_0_bits_data[15],cam_a_0_bits_data[7]}; // @[Cat.scala 31:58]
  wire [3:0] signbits_d = {cam_d_0_data[31],cam_d_0_data[23],cam_d_0_data[15],cam_d_0_data[7]}; // @[Cat.scala 31:58]
  wire [3:0] _signbit_a_T = signbits_a & signSel; // @[AtomicAutomata.scala 125:38]
  wire [4:0] _signbit_a_T_1 = {_signbit_a_T, 1'h0}; // @[AtomicAutomata.scala 125:49]
  wire [3:0] signbit_a = _signbit_a_T_1[3:0]; // @[AtomicAutomata.scala 125:54]
  wire [3:0] _signbit_d_T = signbits_d & signSel; // @[AtomicAutomata.scala 126:38]
  wire [4:0] _signbit_d_T_1 = {_signbit_d_T, 1'h0}; // @[AtomicAutomata.scala 126:49]
  wire [3:0] signbit_d = _signbit_d_T_1[3:0]; // @[AtomicAutomata.scala 126:54]
  wire [4:0] _signext_a_T = {signbit_a, 1'h0}; // @[package.scala 244:48]
  wire [3:0] _signext_a_T_2 = signbit_a | _signext_a_T[3:0]; // @[package.scala 244:43]
  wire [5:0] _signext_a_T_3 = {_signext_a_T_2, 2'h0}; // @[package.scala 244:48]
  wire [3:0] _signext_a_T_5 = _signext_a_T_2 | _signext_a_T_3[3:0]; // @[package.scala 244:43]
  wire [7:0] _signext_a_T_12 = _signext_a_T_5[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _signext_a_T_14 = _signext_a_T_5[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _signext_a_T_16 = _signext_a_T_5[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _signext_a_T_18 = _signext_a_T_5[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [31:0] signext_a = {_signext_a_T_18,_signext_a_T_16,_signext_a_T_14,_signext_a_T_12}; // @[Cat.scala 31:58]
  wire [4:0] _signext_d_T = {signbit_d, 1'h0}; // @[package.scala 244:48]
  wire [3:0] _signext_d_T_2 = signbit_d | _signext_d_T[3:0]; // @[package.scala 244:43]
  wire [5:0] _signext_d_T_3 = {_signext_d_T_2, 2'h0}; // @[package.scala 244:48]
  wire [3:0] _signext_d_T_5 = _signext_d_T_2 | _signext_d_T_3[3:0]; // @[package.scala 244:43]
  wire [7:0] _signext_d_T_12 = _signext_d_T_5[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _signext_d_T_14 = _signext_d_T_5[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _signext_d_T_16 = _signext_d_T_5[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _signext_d_T_18 = _signext_d_T_5[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [31:0] signext_d = {_signext_d_T_18,_signext_d_T_16,_signext_d_T_14,_signext_d_T_12}; // @[Cat.scala 31:58]
  wire [7:0] _wide_mask_T_5 = cam_a_0_bits_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _wide_mask_T_7 = cam_a_0_bits_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _wide_mask_T_9 = cam_a_0_bits_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _wide_mask_T_11 = cam_a_0_bits_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [31:0] wide_mask = {_wide_mask_T_11,_wide_mask_T_9,_wide_mask_T_7,_wide_mask_T_5}; // @[Cat.scala 31:58]
  wire [31:0] _a_a_ext_T = cam_a_0_bits_data & wide_mask; // @[AtomicAutomata.scala 131:28]
  wire [31:0] a_a_ext = _a_a_ext_T | signext_a; // @[AtomicAutomata.scala 131:41]
  wire [31:0] _a_d_ext_T = cam_d_0_data & wide_mask; // @[AtomicAutomata.scala 132:28]
  wire [31:0] a_d_ext = _a_d_ext_T | signext_d; // @[AtomicAutomata.scala 132:41]
  wire [31:0] _a_d_inv_T = ~a_d_ext; // @[AtomicAutomata.scala 133:43]
  wire [31:0] a_d_inv = adder ? a_d_ext : _a_d_inv_T; // @[AtomicAutomata.scala 133:26]
  wire [31:0] adder_out = a_a_ext + a_d_inv; // @[AtomicAutomata.scala 134:33]
  wire  a_bigger_uneq = unsigned_ == a_a_ext[31]; // @[AtomicAutomata.scala 136:38]
  wire  a_bigger = a_a_ext[31] == a_d_ext[31] ? ~adder_out[31] : a_bigger_uneq; // @[AtomicAutomata.scala 137:27]
  wire  pick_a = take_max == a_bigger; // @[AtomicAutomata.scala 138:31]
  wire [31:0] _arith_out_T = pick_a ? cam_a_0_bits_data : cam_d_0_data; // @[AtomicAutomata.scala 139:50]
  wire [31:0] arith_out = adder ? adder_out : _arith_out_T; // @[AtomicAutomata.scala 139:28]
  wire [31:0] amo_data = cam_a_0_bits_opcode[0] ? logic_out : arith_out; // @[AtomicAutomata.scala 145:14]
  wire  a_allow = ~cam_abusy_0 & (a_isSupported | cam_free_0); // @[AtomicAutomata.scala 149:35]
  reg [3:0] beatsLeft; // @[Arbiter.scala 87:30]
  wire  idle = beatsLeft == 4'h0; // @[Arbiter.scala 88:28]
  wire  source_i_valid = auto_in_a_valid & a_allow; // @[AtomicAutomata.scala 151:38]
  wire [1:0] _readys_T = {source_i_valid,cam_amo_0}; // @[Cat.scala 31:58]
  wire [2:0] _readys_T_1 = {_readys_T, 1'h0}; // @[package.scala 244:48]
  wire [1:0] _readys_T_3 = _readys_T | _readys_T_1[1:0]; // @[package.scala 244:43]
  wire [2:0] _readys_T_5 = {_readys_T_3, 1'h0}; // @[Arbiter.scala 16:78]
  wire [1:0] _readys_T_7 = ~_readys_T_5[1:0]; // @[Arbiter.scala 16:61]
  wire  readys_1 = _readys_T_7[1]; // @[Arbiter.scala 95:86]
  reg  state_1; // @[Arbiter.scala 116:26]
  wire  allowed_1 = idle ? readys_1 : state_1; // @[Arbiter.scala 121:24]
  wire  out_1_ready = auto_out_a_ready & allowed_1; // @[Arbiter.scala 123:31]
  wire  _T = ~a_isSupported; // @[AtomicAutomata.scala 153:15]
  wire [2:0] source_i_bits_opcode = ~a_isSupported ? 3'h4 : auto_in_a_bits_opcode; // @[AtomicAutomata.scala 152:24 153:31 154:32]
  wire [2:0] source_i_bits_param = ~a_isSupported ? 3'h0 : auto_in_a_bits_param; // @[AtomicAutomata.scala 152:24 153:31 155:32]
  wire  source_c_bits_a_corrupt = cam_a_0_bits_corrupt | cam_d_0_corrupt; // @[AtomicAutomata.scala 166:45]
  wire  source_c_bits_a_mask_sizeOH_shiftAmount = cam_a_0_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _source_c_bits_a_mask_sizeOH_T_1 = 2'h1 << source_c_bits_a_mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] source_c_bits_a_mask_sizeOH = _source_c_bits_a_mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _source_c_bits_a_mask_T = cam_a_0_bits_size >= 3'h2; // @[Misc.scala 205:21]
  wire  source_c_bits_a_mask_size = source_c_bits_a_mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  source_c_bits_a_mask_bit = cam_a_0_bits_address[1]; // @[Misc.scala 209:26]
  wire  source_c_bits_a_mask_nbit = ~source_c_bits_a_mask_bit; // @[Misc.scala 210:20]
  wire  source_c_bits_a_mask_acc = _source_c_bits_a_mask_T | source_c_bits_a_mask_size & source_c_bits_a_mask_nbit; // @[Misc.scala 214:29]
  wire  source_c_bits_a_mask_acc_1 = _source_c_bits_a_mask_T | source_c_bits_a_mask_size & source_c_bits_a_mask_bit; // @[Misc.scala 214:29]
  wire  source_c_bits_a_mask_size_1 = source_c_bits_a_mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  source_c_bits_a_mask_bit_1 = cam_a_0_bits_address[0]; // @[Misc.scala 209:26]
  wire  source_c_bits_a_mask_nbit_1 = ~source_c_bits_a_mask_bit_1; // @[Misc.scala 210:20]
  wire  source_c_bits_a_mask_eq_2 = source_c_bits_a_mask_nbit & source_c_bits_a_mask_nbit_1; // @[Misc.scala 213:27]
  wire  source_c_bits_a_mask_acc_2 = source_c_bits_a_mask_acc | source_c_bits_a_mask_size_1 & source_c_bits_a_mask_eq_2; // @[Misc.scala 214:29]
  wire  source_c_bits_a_mask_eq_3 = source_c_bits_a_mask_nbit & source_c_bits_a_mask_bit_1; // @[Misc.scala 213:27]
  wire  source_c_bits_a_mask_acc_3 = source_c_bits_a_mask_acc | source_c_bits_a_mask_size_1 & source_c_bits_a_mask_eq_3; // @[Misc.scala 214:29]
  wire  source_c_bits_a_mask_eq_4 = source_c_bits_a_mask_bit & source_c_bits_a_mask_nbit_1; // @[Misc.scala 213:27]
  wire  source_c_bits_a_mask_acc_4 = source_c_bits_a_mask_acc_1 | source_c_bits_a_mask_size_1 &
    source_c_bits_a_mask_eq_4; // @[Misc.scala 214:29]
  wire  source_c_bits_a_mask_eq_5 = source_c_bits_a_mask_bit & source_c_bits_a_mask_bit_1; // @[Misc.scala 213:27]
  wire  source_c_bits_a_mask_acc_5 = source_c_bits_a_mask_acc_1 | source_c_bits_a_mask_size_1 &
    source_c_bits_a_mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] source_c_bits_a_mask = {source_c_bits_a_mask_acc_5,source_c_bits_a_mask_acc_4,source_c_bits_a_mask_acc_3,
    source_c_bits_a_mask_acc_2}; // @[Cat.scala 31:58]
  wire [12:0] _decode_T_1 = 13'h3f << auto_in_a_bits_size; // @[package.scala 234:77]
  wire [5:0] _decode_T_3 = ~_decode_T_1[5:0]; // @[package.scala 234:46]
  wire [3:0] decode = _decode_T_3[5:2]; // @[Edges.scala 219:59]
  wire  opdata = ~auto_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  wire  latch = idle & auto_out_a_ready; // @[Arbiter.scala 89:24]
  wire  readys_0 = _readys_T_7[0]; // @[Arbiter.scala 95:86]
  wire  earlyWinner_0 = readys_0 & cam_amo_0; // @[Arbiter.scala 97:79]
  wire  earlyWinner_1 = readys_1 & source_i_valid; // @[Arbiter.scala 97:79]
  wire  _prefixOR_T = earlyWinner_0 | earlyWinner_1; // @[Arbiter.scala 104:53]
  wire  _T_10 = ~reset; // @[Arbiter.scala 105:13]
  wire  _T_12 = cam_amo_0 | source_i_valid; // @[Arbiter.scala 107:36]
  wire  _T_13 = ~(cam_amo_0 | source_i_valid); // @[Arbiter.scala 107:15]
  reg  state_0; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_0 = idle ? earlyWinner_0 : state_0; // @[Arbiter.scala 117:30]
  wire  muxStateEarly_1 = idle ? earlyWinner_1 : state_1; // @[Arbiter.scala 117:30]
  wire  _sink_ACancel_earlyValid_T_3 = state_0 & cam_amo_0 | state_1 & source_i_valid; // @[Mux.scala 27:73]
  wire  sink_ACancel_earlyValid = idle ? _T_12 : _sink_ACancel_earlyValid_T_3; // @[Arbiter.scala 125:29]
  wire  _beatsLeft_T_2 = auto_out_a_ready & sink_ACancel_earlyValid; // @[ReadyValidCancel.scala 49:33]
  wire [3:0] _GEN_40 = {{3'd0}, _beatsLeft_T_2}; // @[Arbiter.scala 113:52]
  wire [3:0] _beatsLeft_T_4 = beatsLeft - _GEN_40; // @[Arbiter.scala 113:52]
  wire  allowed_0 = idle ? readys_0 : state_0; // @[Arbiter.scala 121:24]
  wire  out_ready = auto_out_a_ready & allowed_0; // @[Arbiter.scala 123:31]
  wire [31:0] _T_29 = muxStateEarly_0 ? amo_data : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_30 = muxStateEarly_1 ? auto_in_a_bits_data : 32'h0; // @[Mux.scala 27:73]
  wire [3:0] _T_32 = muxStateEarly_0 ? source_c_bits_a_mask : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _T_33 = muxStateEarly_1 ? auto_in_a_bits_mask : 4'h0; // @[Mux.scala 27:73]
  wire [29:0] _T_35 = muxStateEarly_0 ? cam_a_0_bits_address : 30'h0; // @[Mux.scala 27:73]
  wire [29:0] _T_36 = muxStateEarly_1 ? auto_in_a_bits_address : 30'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_38 = muxStateEarly_0 ? cam_a_0_bits_source : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_39 = muxStateEarly_1 ? auto_in_a_bits_source : 2'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_41 = muxStateEarly_0 ? cam_a_0_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_42 = muxStateEarly_1 ? auto_in_a_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire  _T_50 = out_1_ready & source_i_valid; // @[Decoupled.scala 50:35]
  wire [2:0] _GEN_41 = {{1'd0}, auto_in_a_bits_param[1:0]}; // @[Mux.scala 81:61]
  wire [3:0] _cam_a_0_lut_T_2 = 3'h1 == _GEN_41 ? 4'he : 4'h8; // @[Mux.scala 81:58]
  wire [1:0] _GEN_12 = cam_free_0 ? 2'h3 : cam_s_0_state; // @[AtomicAutomata.scala 187:23 188:23 76:28]
  wire [1:0] _GEN_23 = _T_50 & _T ? _GEN_12 : cam_s_0_state; // @[AtomicAutomata.scala 174:50 76:28]
  wire  _T_53 = out_ready & cam_amo_0; // @[Decoupled.scala 50:35]
  wire [1:0] _GEN_24 = cam_amo_0 ? 2'h1 : _GEN_23; // @[AtomicAutomata.scala 196:23 197:23]
  wire [1:0] _GEN_25 = _T_53 ? _GEN_24 : _GEN_23; // @[AtomicAutomata.scala 194:32]
  reg [3:0] d_first_counter; // @[Edges.scala 228:27]
  wire  d_first = d_first_counter == 4'h0; // @[Edges.scala 230:25]
  wire  d_ackd = auto_out_d_bits_opcode == 3'h1; // @[AtomicAutomata.scala 213:40]
  wire  d_cam_sel_raw_0 = cam_a_0_bits_source == auto_out_d_bits_source; // @[AtomicAutomata.scala 204:53]
  wire  d_cam_sel_match_0 = d_cam_sel_raw_0 & cam_dmatch_0; // @[AtomicAutomata.scala 205:83]
  wire  d_drop = d_first & d_ackd & d_cam_sel_match_0; // @[AtomicAutomata.scala 232:40]
  wire  bundleOut_0_d_ready = auto_in_d_ready | d_drop; // @[AtomicAutomata.scala 236:35]
  wire  _d_first_T = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
  wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << auto_out_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
  wire [3:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire [3:0] d_first_counter1 = d_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  d_ack = auto_out_d_bits_opcode == 3'h0; // @[AtomicAutomata.scala 214:40]
  wire  d_replace = d_first & d_ack & d_cam_sel_match_0; // @[AtomicAutomata.scala 233:42]
  TLMonitor_5 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_param(monitor_io_in_d_bits_param),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source),
    .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
    .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
    .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
  );
  assign auto_in_a_ready = out_1_ready & a_allow; // @[AtomicAutomata.scala 150:38]
  assign auto_in_d_valid = auto_out_d_valid & ~d_drop; // @[AtomicAutomata.scala 235:35]
  assign auto_in_d_bits_opcode = d_replace ? 3'h1 : auto_out_d_bits_opcode; // @[AtomicAutomata.scala 238:19 239:26 240:28]
  assign auto_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_denied = d_replace ? cam_d_0_denied | auto_out_d_bits_denied : auto_out_d_bits_denied; // @[AtomicAutomata.scala 238:19 239:26 243:29]
  assign auto_in_d_bits_data = d_replace ? cam_d_0_data : auto_out_d_bits_data; // @[AtomicAutomata.scala 238:19 239:26 241:26]
  assign auto_in_d_bits_corrupt = d_replace ? cam_d_0_corrupt | auto_out_d_bits_denied : auto_out_d_bits_corrupt; // @[AtomicAutomata.scala 238:19 239:26 242:29]
  assign auto_out_a_valid = idle ? _T_12 : _sink_ACancel_earlyValid_T_3; // @[Arbiter.scala 125:29]
  assign auto_out_a_bits_opcode = muxStateEarly_1 ? source_i_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  assign auto_out_a_bits_param = muxStateEarly_1 ? source_i_bits_param : 3'h0; // @[Mux.scala 27:73]
  assign auto_out_a_bits_size = _T_41 | _T_42; // @[Mux.scala 27:73]
  assign auto_out_a_bits_source = _T_38 | _T_39; // @[Mux.scala 27:73]
  assign auto_out_a_bits_address = _T_35 | _T_36; // @[Mux.scala 27:73]
  assign auto_out_a_bits_mask = _T_32 | _T_33; // @[Mux.scala 27:73]
  assign auto_out_a_bits_data = _T_29 | _T_30; // @[Mux.scala 27:73]
  assign auto_out_a_bits_corrupt = muxStateEarly_0 & source_c_bits_a_corrupt | muxStateEarly_1 & auto_in_a_bits_corrupt; // @[Mux.scala 27:73]
  assign auto_out_d_ready = auto_in_d_ready | d_drop; // @[AtomicAutomata.scala 236:35]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = out_1_ready & a_allow; // @[AtomicAutomata.scala 150:38]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid & ~d_drop; // @[AtomicAutomata.scala 235:35]
  assign monitor_io_in_d_bits_opcode = d_replace ? 3'h1 : auto_out_d_bits_opcode; // @[AtomicAutomata.scala 238:19 239:26 240:28]
  assign monitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_denied = d_replace ? cam_d_0_denied | auto_out_d_bits_denied : auto_out_d_bits_denied; // @[AtomicAutomata.scala 238:19 239:26 243:29]
  assign monitor_io_in_d_bits_corrupt = d_replace ? cam_d_0_corrupt | auto_out_d_bits_denied : auto_out_d_bits_corrupt; // @[AtomicAutomata.scala 238:19 239:26 242:29]
  always @(posedge clock) begin
    if (reset) begin // @[AtomicAutomata.scala 76:28]
      cam_s_0_state <= 2'h0; // @[AtomicAutomata.scala 76:28]
    end else if (_d_first_T & d_first) begin // @[AtomicAutomata.scala 216:40]
      if (d_cam_sel_match_0) begin // @[AtomicAutomata.scala 225:23]
        if (d_ackd) begin // @[AtomicAutomata.scala 227:29]
          cam_s_0_state <= 2'h2;
        end else begin
          cam_s_0_state <= 2'h0;
        end
      end else begin
        cam_s_0_state <= _GEN_25;
      end
    end else begin
      cam_s_0_state <= _GEN_25;
    end
    if (_T_50 & _T) begin // @[AtomicAutomata.scala 174:50]
      if (cam_free_0) begin // @[AtomicAutomata.scala 176:23]
        cam_a_0_bits_opcode <= auto_in_a_bits_opcode; // @[AtomicAutomata.scala 178:24]
      end
    end
    if (_T_50 & _T) begin // @[AtomicAutomata.scala 174:50]
      if (cam_free_0) begin // @[AtomicAutomata.scala 176:23]
        cam_a_0_bits_param <= auto_in_a_bits_param; // @[AtomicAutomata.scala 178:24]
      end
    end
    if (_T_50 & _T) begin // @[AtomicAutomata.scala 174:50]
      if (cam_free_0) begin // @[AtomicAutomata.scala 176:23]
        cam_a_0_bits_size <= auto_in_a_bits_size; // @[AtomicAutomata.scala 178:24]
      end
    end
    if (_T_50 & _T) begin // @[AtomicAutomata.scala 174:50]
      if (cam_free_0) begin // @[AtomicAutomata.scala 176:23]
        cam_a_0_bits_source <= auto_in_a_bits_source; // @[AtomicAutomata.scala 178:24]
      end
    end
    if (_T_50 & _T) begin // @[AtomicAutomata.scala 174:50]
      if (cam_free_0) begin // @[AtomicAutomata.scala 176:23]
        cam_a_0_bits_address <= auto_in_a_bits_address; // @[AtomicAutomata.scala 178:24]
      end
    end
    if (_T_50 & _T) begin // @[AtomicAutomata.scala 174:50]
      if (cam_free_0) begin // @[AtomicAutomata.scala 176:23]
        cam_a_0_bits_mask <= auto_in_a_bits_mask; // @[AtomicAutomata.scala 178:24]
      end
    end
    if (_T_50 & _T) begin // @[AtomicAutomata.scala 174:50]
      if (cam_free_0) begin // @[AtomicAutomata.scala 176:23]
        cam_a_0_bits_data <= auto_in_a_bits_data; // @[AtomicAutomata.scala 178:24]
      end
    end
    if (_T_50 & _T) begin // @[AtomicAutomata.scala 174:50]
      if (cam_free_0) begin // @[AtomicAutomata.scala 176:23]
        cam_a_0_bits_corrupt <= auto_in_a_bits_corrupt; // @[AtomicAutomata.scala 178:24]
      end
    end
    if (_T_50 & _T) begin // @[AtomicAutomata.scala 174:50]
      if (cam_free_0) begin // @[AtomicAutomata.scala 176:23]
        if (3'h3 == _GEN_41) begin // @[Mux.scala 81:58]
          cam_a_0_lut <= 4'hc;
        end else if (3'h0 == _GEN_41) begin // @[Mux.scala 81:58]
          cam_a_0_lut <= 4'h6;
        end else begin
          cam_a_0_lut <= _cam_a_0_lut_T_2;
        end
      end
    end
    if (_d_first_T & d_first) begin // @[AtomicAutomata.scala 216:40]
      if (d_cam_sel_match_0 & d_ackd) begin // @[AtomicAutomata.scala 218:33]
        cam_d_0_data <= auto_out_d_bits_data; // @[AtomicAutomata.scala 219:22]
      end
    end
    if (_d_first_T & d_first) begin // @[AtomicAutomata.scala 216:40]
      if (d_cam_sel_match_0 & d_ackd) begin // @[AtomicAutomata.scala 218:33]
        cam_d_0_denied <= auto_out_d_bits_denied; // @[AtomicAutomata.scala 220:24]
      end
    end
    if (_d_first_T & d_first) begin // @[AtomicAutomata.scala 216:40]
      if (d_cam_sel_match_0 & d_ackd) begin // @[AtomicAutomata.scala 218:33]
        cam_d_0_corrupt <= auto_out_d_bits_corrupt; // @[AtomicAutomata.scala 221:25]
      end
    end
    if (reset) begin // @[Arbiter.scala 87:30]
      beatsLeft <= 4'h0; // @[Arbiter.scala 87:30]
    end else if (latch) begin // @[Arbiter.scala 113:23]
      if (earlyWinner_1) begin // @[Arbiter.scala 111:73]
        if (opdata) begin // @[Edges.scala 220:14]
          beatsLeft <= decode;
        end else begin
          beatsLeft <= 4'h0;
        end
      end else begin
        beatsLeft <= 4'h0;
      end
    end else begin
      beatsLeft <= _beatsLeft_T_4;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_1 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_1 <= earlyWinner_1;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_0 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_0 <= earlyWinner_0;
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 4'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~earlyWinner_0 | ~earlyWinner_1) & ~reset) begin
          $fatal; // @[Arbiter.scala 105:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~earlyWinner_0 | ~earlyWinner_1)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:105 assert((prefixOR zip earlyWinner) map { case (p,w) => !p || !w } reduce {_ && _})\n"
            ); // @[Arbiter.scala 105:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(cam_amo_0 | source_i_valid) | _prefixOR_T) & _T_10) begin
          $fatal; // @[Arbiter.scala 107:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_10 & ~(~(cam_amo_0 | source_i_valid) | _prefixOR_T)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:107 assert (!earlyValids.reduce(_||_) || earlyWinner.reduce(_||_))\n"
            ); // @[Arbiter.scala 107:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_13 | _T_12) & _T_10) begin
          $fatal; // @[Arbiter.scala 108:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_10 & ~(_T_13 | _T_12)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:108 assert (!validQuals .reduce(_||_) || validQuals .reduce(_||_))\n"
            ); // @[Arbiter.scala 108:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  cam_s_0_state = _RAND_0[1:0];
  _RAND_1 = {1{`RANDOM}};
  cam_a_0_bits_opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  cam_a_0_bits_param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  cam_a_0_bits_size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  cam_a_0_bits_source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  cam_a_0_bits_address = _RAND_5[29:0];
  _RAND_6 = {1{`RANDOM}};
  cam_a_0_bits_mask = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  cam_a_0_bits_data = _RAND_7[31:0];
  _RAND_8 = {1{`RANDOM}};
  cam_a_0_bits_corrupt = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  cam_a_0_lut = _RAND_9[3:0];
  _RAND_10 = {1{`RANDOM}};
  cam_d_0_data = _RAND_10[31:0];
  _RAND_11 = {1{`RANDOM}};
  cam_d_0_denied = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  cam_d_0_corrupt = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  beatsLeft = _RAND_13[3:0];
  _RAND_14 = {1{`RANDOM}};
  state_1 = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  state_0 = _RAND_15[0:0];
  _RAND_16 = {1{`RANDOM}};
  d_first_counter = _RAND_16[3:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLMonitor_6(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [29:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_param,
  input  [2:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source,
  input         io_in_d_bits_sink,
  input         io_in_d_bits_denied,
  input         io_in_d_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
  wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
  wire [29:0] _GEN_71 = {{24'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [29:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 30'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [29:0] _T_45 = io_in_a_bits_address ^ 30'h10012000; // @[Parameters.scala 137:31]
  wire [30:0] _T_46 = {1'b0,$signed(_T_45)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_48 = $signed(_T_46) & -31'sh2000; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_50 = io_in_a_bits_address ^ 30'h10014000; // @[Parameters.scala 137:31]
  wire [30:0] _T_51 = {1'b0,$signed(_T_50)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_53 = $signed(_T_51) & -31'sh2000; // @[Parameters.scala 137:52]
  wire  _T_54 = $signed(_T_53) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_55 = io_in_a_bits_address ^ 30'h10016000; // @[Parameters.scala 137:31]
  wire [30:0] _T_56 = {1'b0,$signed(_T_55)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_58 = $signed(_T_56) & -31'sh1000; // @[Parameters.scala 137:52]
  wire  _T_59 = $signed(_T_58) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_60 = io_in_a_bits_address ^ 30'h10023000; // @[Parameters.scala 137:31]
  wire [30:0] _T_61 = {1'b0,$signed(_T_60)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_63 = $signed(_T_61) & -31'sh11000; // @[Parameters.scala 137:52]
  wire  _T_64 = $signed(_T_63) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_65 = io_in_a_bits_address ^ 30'h10024000; // @[Parameters.scala 137:31]
  wire [30:0] _T_66 = {1'b0,$signed(_T_65)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_68 = $signed(_T_66) & -31'sh12000; // @[Parameters.scala 137:52]
  wire  _T_69 = $signed(_T_68) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_70 = io_in_a_bits_address ^ 30'h10026000; // @[Parameters.scala 137:31]
  wire [30:0] _T_71 = {1'b0,$signed(_T_70)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_73 = $signed(_T_71) & -31'sh1000; // @[Parameters.scala 137:52]
  wire  _T_74 = $signed(_T_73) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_75 = io_in_a_bits_address ^ 30'h10043000; // @[Parameters.scala 137:31]
  wire [30:0] _T_76 = {1'b0,$signed(_T_75)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_78 = $signed(_T_76) & -31'sh11000; // @[Parameters.scala 137:52]
  wire  _T_79 = $signed(_T_78) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_80 = io_in_a_bits_address ^ 30'h20000000; // @[Parameters.scala 137:31]
  wire [30:0] _T_81 = {1'b0,$signed(_T_80)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_83 = $signed(_T_81) & -31'sh20000000; // @[Parameters.scala 137:52]
  wire  _T_84 = $signed(_T_83) == 31'sh0; // @[Parameters.scala 137:67]
  wire  _T_90 = _T_49 | _T_54 | _T_59 | _T_64 | _T_69 | _T_74 | _T_79; // @[Parameters.scala 671:42]
  wire  _T_91 = _T_49 | _T_54 | _T_59 | _T_64 | _T_69 | _T_74 | _T_79 | _T_84; // @[Parameters.scala 671:42]
  wire  _T_101 = 3'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_102 = _source_ok_T & _T_101; // @[Mux.scala 27:73]
  wire  _T_160 = _T_102 & _T_91; // @[Monitor.scala 83:78]
  wire  _T_174 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_178 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_179 = _T_178 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_183 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_187 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_332 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_345 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_360 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
  wire  _T_410 = _T_360 & _T_91; // @[Parameters.scala 670:56]
  wire  _T_421 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_425 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_433 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_489 = _T_360 & _T_90; // @[Parameters.scala 670:56]
  wire  _T_499 = source_ok & _T_489; // @[Monitor.scala 115:71]
  wire  _T_517 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_597 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_598 = io_in_a_bits_mask & _T_597; // @[Monitor.scala 127:31]
  wire  _T_599 = _T_598 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_603 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_615 = io_in_a_bits_size <= 3'h2; // @[Parameters.scala 92:42]
  wire  _T_659 = _T_615 & _T_90; // @[Parameters.scala 670:56]
  wire  _T_669 = source_ok & _T_659; // @[Monitor.scala 131:74]
  wire  _T_679 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_687 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_763 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_771 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_842 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_854 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  _T_858 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_862 = io_in_d_bits_size >= 3'h2; // @[Monitor.scala 312:27]
  wire  _T_866 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
  wire  _T_870 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
  wire  _T_874 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
  wire  _T_878 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_889 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
  wire  _T_893 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
  wire  _T_906 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_926 = _T_874 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
  wire  _T_935 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_952 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_970 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [3:0] a_first_beats1_decode = is_aligned_mask[5:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] a_first_counter; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1 = a_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [29:0] address; // @[Monitor.scala 388:22]
  wire  _T_1000 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_1001 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_1005 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_1009 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_1013 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_1017 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
  wire [3:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [3:0] d_first_counter; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1 = d_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] param_1; // @[Monitor.scala 536:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  reg  sink; // @[Monitor.scala 539:22]
  reg  denied; // @[Monitor.scala 540:22]
  wire  _T_1024 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_1025 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_1029 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
  wire  _T_1033 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_1037 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  wire  _T_1041 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
  wire  _T_1045 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [11:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [3:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1_1 = a_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  reg [3:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_1 = d_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [11:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _GEN_76 = {{4'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_76 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_1051 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_1054 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [34:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [34:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_1056 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_1058 = ~_T_1056[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [34:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_1062 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_1064 = ~_T_858; // @[Monitor.scala 671:74]
  wire  _T_1065 = io_in_d_valid & d_first_1 & ~_T_858; // @[Monitor.scala 671:71]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_858 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 671:90 672:22]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [3:0] _GEN_22 = _d_first_T & d_first_1 & _T_1064 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_23 = _d_first_T & d_first_1 & _T_1064 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_1051 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_1075 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_1077 = _T_1075[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_1082 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_1083 = io_in_d_bits_opcode == _GEN_32 | _T_1082; // @[Monitor.scala 685:77]
  wire  _T_1087 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_1094 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_1095 = io_in_d_bits_opcode == _GEN_48 | _T_1094; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_1099 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_1109 = _T_1062 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_1064; // @[Monitor.scala 694:116]
  wire  _T_1111 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set_wo_ready = _GEN_15[2:0];
  wire [2:0] d_clr_wo_ready = _GEN_21[2:0];
  wire  _T_1118 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire [2:0] a_set = _GEN_16[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_22[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_19[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_23[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [11:0] a_sizes_set = _GEN_20[11:0];
  wire [11:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [11:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_1127 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [2:0] inflight_1; // @[Monitor.scala 723:35]
  reg [11:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [3:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_2 = d_first_counter_2 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 4'h0; // @[Edges.scala 230:25]
  wire [11:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [15:0] _GEN_87 = {{4'd0}, _c_size_lookup_T_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_87 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_1153 = io_in_d_valid & d_first_2 & _T_858; // @[Monitor.scala 779:71]
  wire [3:0] _GEN_67 = _d_first_T & d_first_2 & _T_858 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 783:90 784:21]
  wire [46:0] _GEN_68 = _d_first_T & d_first_2 & _T_858 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 785:21]
  wire [2:0] _T_1161 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_1171 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [2:0] d_clr_1 = _GEN_67[2:0];
  wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [2:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [11:0] d_opcodes_clr_1 = _GEN_68[11:0];
  wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [11:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_1196 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 4'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 4'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 12'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 4'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 4'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 3'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 12'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 4'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_160 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_160) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_174 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_174) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_179 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_179) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_160 & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~_T_160) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_174 & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~_T_174) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_332 & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~_T_332) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_179 & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~_T_179) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_187 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_187 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_410 & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~_T_410) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_421 & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~_T_421) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_425 & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~_T_425) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_499 & (io_in_a_valid & _T_433 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_433 & ~reset & ~_T_499) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_433 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_433 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_433 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_433 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_421 & (io_in_a_valid & _T_433 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_433 & ~reset & ~_T_421) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_425 & (io_in_a_valid & _T_433 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_433 & ~reset & ~_T_425) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_499 & (io_in_a_valid & _T_517 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_517 & ~reset & ~_T_499) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_517 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_517 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_517 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_517 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_421 & (io_in_a_valid & _T_517 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_517 & ~reset & ~_T_421) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_599 & (io_in_a_valid & _T_517 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_517 & ~reset & ~_T_599) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_669 & (io_in_a_valid & _T_603 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_603 & ~reset & ~_T_669) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_603 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_603 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_603 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_603 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_679 & (io_in_a_valid & _T_603 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_603 & ~reset & ~_T_679) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_425 & (io_in_a_valid & _T_603 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_603 & ~reset & ~_T_425) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_669 & (io_in_a_valid & _T_687 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_687 & ~reset & ~_T_669) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_687 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_687 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_687 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_687 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_763 & (io_in_a_valid & _T_687 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_687 & ~reset & ~_T_763) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_425 & (io_in_a_valid & _T_687 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_687 & ~reset & ~_T_425) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_771 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_771 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_771 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_771 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_771 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_771 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_842 & (io_in_a_valid & _T_771 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_771 & ~reset & ~_T_842) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_425 & (io_in_a_valid & _T_771 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_771 & ~reset & ~_T_425) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_771 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_771 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_854 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_854) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_858 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_858 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_862 & (io_in_d_valid & _T_858 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_858 & _T_2 & ~_T_862) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_866 & (io_in_d_valid & _T_858 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_858 & _T_2 & ~_T_866) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_870 & (io_in_d_valid & _T_858 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_858 & _T_2 & ~_T_870) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_874 & (io_in_d_valid & _T_858 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_858 & _T_2 & ~_T_874) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is denied (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_878 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_878 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_878 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_878 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_862 & (io_in_d_valid & _T_878 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_878 & _T_2 & ~_T_862) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_889 & (io_in_d_valid & _T_878 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_878 & _T_2 & ~_T_889) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid cap param (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_893 & (io_in_d_valid & _T_878 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_878 & _T_2 & ~_T_893) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries toN param (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_870 & (io_in_d_valid & _T_878 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_878 & _T_2 & ~_T_870) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is corrupt (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_874 & (io_in_d_valid & _T_878 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_878 & _T_2 & ~_T_874) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is denied (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_906 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_906 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_906 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_906 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_862 & (io_in_d_valid & _T_906 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_906 & _T_2 & ~_T_862) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_889 & (io_in_d_valid & _T_906 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_906 & _T_2 & ~_T_889) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_893 & (io_in_d_valid & _T_906 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_906 & _T_2 & ~_T_893) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries toN param (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_926 & (io_in_d_valid & _T_906 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_906 & _T_2 & ~_T_926) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_874 & (io_in_d_valid & _T_906 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_906 & _T_2 & ~_T_874) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_935 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_935 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_866 & (io_in_d_valid & _T_935 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_935 & _T_2 & ~_T_866) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid param (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_870 & (io_in_d_valid & _T_935 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_935 & _T_2 & ~_T_870) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is corrupt (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_874 & (io_in_d_valid & _T_935 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_935 & _T_2 & ~_T_874) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is denied (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_952 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_952 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_866 & (io_in_d_valid & _T_952 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_952 & _T_2 & ~_T_866) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_926 & (io_in_d_valid & _T_952 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_952 & _T_2 & ~_T_926) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_874 & (io_in_d_valid & _T_952 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_952 & _T_2 & ~_T_874) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_970 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_970 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_866 & (io_in_d_valid & _T_970 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_970 & _T_2 & ~_T_866) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid param (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_870 & (io_in_d_valid & _T_970 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_970 & _T_2 & ~_T_870) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is corrupt (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_874 & (io_in_d_valid & _T_970 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_970 & _T_2 & ~_T_874) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is denied (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1001 & (_T_1000 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1000 & ~reset & ~_T_1001) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1005 & (_T_1000 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1000 & ~reset & ~_T_1005) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1009 & (_T_1000 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1000 & ~reset & ~_T_1009) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1013 & (_T_1000 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1000 & ~reset & ~_T_1013) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1017 & (_T_1000 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1000 & ~reset & ~_T_1017) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1025 & (_T_1024 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1024 & _T_2 & ~_T_1025) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1029 & (_T_1024 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1024 & _T_2 & ~_T_1029) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1033 & (_T_1024 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1024 & _T_2 & ~_T_1033) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1037 & (_T_1024 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1024 & _T_2 & ~_T_1037) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1041 & (_T_1024 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1024 & _T_2 & ~_T_1041) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel sink changed with multibeat operation (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1045 & (_T_1024 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1024 & _T_2 & ~_T_1045) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel denied changed with multibeat operation (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1058 & (_T_1054 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1054 & ~reset & ~_T_1058) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1077 & (_T_1065 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1065 & _T_2 & ~_T_1077) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1083 & (_T_1065 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1065 & same_cycle_resp & _T_2 & ~_T_1083) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1087 & (_T_1065 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1065 & same_cycle_resp & _T_2 & ~_T_1087) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1095 & (_T_1065 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1065 & ~same_cycle_resp & _T_2 & ~_T_1095) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1099 & (_T_1065 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1065 & ~same_cycle_resp & _T_2 & ~_T_1099) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1111 & (_T_1109 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1109 & _T_2 & ~_T_1111) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1118 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_1118) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 4 (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1127 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_1127) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1161[0] & (_T_1153 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1153 & _T_2 & ~_T_1161[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1171 & (_T_1153 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1153 & _T_2 & ~_T_1171) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1196 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_1196) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:44)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[29:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  param_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  size_1 = _RAND_9[2:0];
  _RAND_10 = {1{`RANDOM}};
  source_1 = _RAND_10[1:0];
  _RAND_11 = {1{`RANDOM}};
  sink = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  denied = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  inflight = _RAND_13[2:0];
  _RAND_14 = {1{`RANDOM}};
  inflight_opcodes = _RAND_14[11:0];
  _RAND_15 = {1{`RANDOM}};
  inflight_sizes = _RAND_15[11:0];
  _RAND_16 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_16[3:0];
  _RAND_17 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_17[3:0];
  _RAND_18 = {1{`RANDOM}};
  watchdog = _RAND_18[31:0];
  _RAND_19 = {1{`RANDOM}};
  inflight_1 = _RAND_19[2:0];
  _RAND_20 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_20[11:0];
  _RAND_21 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_21[3:0];
  _RAND_22 = {1{`RANDOM}};
  watchdog_1 = _RAND_22[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLBuffer_1(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [29:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [1:0]  auto_in_d_bits_param,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output        auto_in_d_bits_sink,
  output        auto_in_d_bits_denied,
  output [31:0] auto_in_d_bits_data,
  output        auto_in_d_bits_corrupt,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [2:0]  auto_out_a_bits_size,
  output [1:0]  auto_out_a_bits_source,
  output [29:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_param,
  input  [2:0]  auto_out_d_bits_size,
  input  [1:0]  auto_out_d_bits_source,
  input         auto_out_d_bits_sink,
  input         auto_out_d_bits_denied,
  input  [31:0] auto_out_d_bits_data,
  input         auto_out_d_bits_corrupt
);
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [29:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
  wire  bundleOut_0_a_q_clock; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_reset; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_enq_ready; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_enq_valid; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
  wire [1:0] bundleOut_0_a_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
  wire [29:0] bundleOut_0_a_q_io_enq_bits_address; // @[Decoupled.scala 361:21]
  wire [3:0] bundleOut_0_a_q_io_enq_bits_mask; // @[Decoupled.scala 361:21]
  wire [31:0] bundleOut_0_a_q_io_enq_bits_data; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_enq_bits_corrupt; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_deq_ready; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_deq_valid; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
  wire [1:0] bundleOut_0_a_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
  wire [29:0] bundleOut_0_a_q_io_deq_bits_address; // @[Decoupled.scala 361:21]
  wire [3:0] bundleOut_0_a_q_io_deq_bits_mask; // @[Decoupled.scala 361:21]
  wire [31:0] bundleOut_0_a_q_io_deq_bits_data; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_clock; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_reset; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_enq_ready; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_enq_valid; // @[Decoupled.scala 361:21]
  wire [2:0] bundleIn_0_d_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
  wire [1:0] bundleIn_0_d_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
  wire [2:0] bundleIn_0_d_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
  wire [1:0] bundleIn_0_d_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_enq_bits_sink; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_enq_bits_denied; // @[Decoupled.scala 361:21]
  wire [31:0] bundleIn_0_d_q_io_enq_bits_data; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_enq_bits_corrupt; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_deq_ready; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_deq_valid; // @[Decoupled.scala 361:21]
  wire [2:0] bundleIn_0_d_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
  wire [1:0] bundleIn_0_d_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
  wire [2:0] bundleIn_0_d_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
  wire [1:0] bundleIn_0_d_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_deq_bits_sink; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_deq_bits_denied; // @[Decoupled.scala 361:21]
  wire [31:0] bundleIn_0_d_q_io_deq_bits_data; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
  TLMonitor_6 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_param(monitor_io_in_d_bits_param),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source),
    .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
    .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
    .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
  );
  Queue bundleOut_0_a_q ( // @[Decoupled.scala 361:21]
    .clock(bundleOut_0_a_q_clock),
    .reset(bundleOut_0_a_q_reset),
    .io_enq_ready(bundleOut_0_a_q_io_enq_ready),
    .io_enq_valid(bundleOut_0_a_q_io_enq_valid),
    .io_enq_bits_opcode(bundleOut_0_a_q_io_enq_bits_opcode),
    .io_enq_bits_param(bundleOut_0_a_q_io_enq_bits_param),
    .io_enq_bits_size(bundleOut_0_a_q_io_enq_bits_size),
    .io_enq_bits_source(bundleOut_0_a_q_io_enq_bits_source),
    .io_enq_bits_address(bundleOut_0_a_q_io_enq_bits_address),
    .io_enq_bits_mask(bundleOut_0_a_q_io_enq_bits_mask),
    .io_enq_bits_data(bundleOut_0_a_q_io_enq_bits_data),
    .io_enq_bits_corrupt(bundleOut_0_a_q_io_enq_bits_corrupt),
    .io_deq_ready(bundleOut_0_a_q_io_deq_ready),
    .io_deq_valid(bundleOut_0_a_q_io_deq_valid),
    .io_deq_bits_opcode(bundleOut_0_a_q_io_deq_bits_opcode),
    .io_deq_bits_param(bundleOut_0_a_q_io_deq_bits_param),
    .io_deq_bits_size(bundleOut_0_a_q_io_deq_bits_size),
    .io_deq_bits_source(bundleOut_0_a_q_io_deq_bits_source),
    .io_deq_bits_address(bundleOut_0_a_q_io_deq_bits_address),
    .io_deq_bits_mask(bundleOut_0_a_q_io_deq_bits_mask),
    .io_deq_bits_data(bundleOut_0_a_q_io_deq_bits_data),
    .io_deq_bits_corrupt(bundleOut_0_a_q_io_deq_bits_corrupt)
  );
  Queue_1 bundleIn_0_d_q ( // @[Decoupled.scala 361:21]
    .clock(bundleIn_0_d_q_clock),
    .reset(bundleIn_0_d_q_reset),
    .io_enq_ready(bundleIn_0_d_q_io_enq_ready),
    .io_enq_valid(bundleIn_0_d_q_io_enq_valid),
    .io_enq_bits_opcode(bundleIn_0_d_q_io_enq_bits_opcode),
    .io_enq_bits_param(bundleIn_0_d_q_io_enq_bits_param),
    .io_enq_bits_size(bundleIn_0_d_q_io_enq_bits_size),
    .io_enq_bits_source(bundleIn_0_d_q_io_enq_bits_source),
    .io_enq_bits_sink(bundleIn_0_d_q_io_enq_bits_sink),
    .io_enq_bits_denied(bundleIn_0_d_q_io_enq_bits_denied),
    .io_enq_bits_data(bundleIn_0_d_q_io_enq_bits_data),
    .io_enq_bits_corrupt(bundleIn_0_d_q_io_enq_bits_corrupt),
    .io_deq_ready(bundleIn_0_d_q_io_deq_ready),
    .io_deq_valid(bundleIn_0_d_q_io_deq_valid),
    .io_deq_bits_opcode(bundleIn_0_d_q_io_deq_bits_opcode),
    .io_deq_bits_param(bundleIn_0_d_q_io_deq_bits_param),
    .io_deq_bits_size(bundleIn_0_d_q_io_deq_bits_size),
    .io_deq_bits_source(bundleIn_0_d_q_io_deq_bits_source),
    .io_deq_bits_sink(bundleIn_0_d_q_io_deq_bits_sink),
    .io_deq_bits_denied(bundleIn_0_d_q_io_deq_bits_denied),
    .io_deq_bits_data(bundleIn_0_d_q_io_deq_bits_data),
    .io_deq_bits_corrupt(bundleIn_0_d_q_io_deq_bits_corrupt)
  );
  assign auto_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
  assign auto_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_param = bundleIn_0_d_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_source = bundleIn_0_d_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_sink = bundleIn_0_d_q_io_deq_bits_sink; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_denied = bundleIn_0_d_q_io_deq_bits_denied; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_data = bundleIn_0_d_q_io_deq_bits_data; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_corrupt = bundleIn_0_d_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_out_a_valid = bundleOut_0_a_q_io_deq_valid; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_opcode = bundleOut_0_a_q_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_param = bundleOut_0_a_q_io_deq_bits_param; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_size = bundleOut_0_a_q_io_deq_bits_size; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_source = bundleOut_0_a_q_io_deq_bits_source; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_address = bundleOut_0_a_q_io_deq_bits_address; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_mask = bundleOut_0_a_q_io_deq_bits_mask; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_data = bundleOut_0_a_q_io_deq_bits_data; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_corrupt = bundleOut_0_a_q_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_d_ready = bundleIn_0_d_q_io_enq_ready; // @[Nodes.scala 1207:84 Decoupled.scala 365:17]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_param = bundleIn_0_d_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_source = bundleIn_0_d_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_sink = bundleIn_0_d_q_io_deq_bits_sink; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_denied = bundleIn_0_d_q_io_deq_bits_denied; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_corrupt = bundleIn_0_d_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign bundleOut_0_a_q_clock = clock;
  assign bundleOut_0_a_q_reset = reset;
  assign bundleOut_0_a_q_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_clock = clock;
  assign bundleIn_0_d_q_reset = reset;
  assign bundleIn_0_d_q_io_enq_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_deq_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module TLMonitor_7(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [28:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [2:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
  wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
  wire [28:0] _GEN_71 = {{23'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [28:0] _T_45 = io_in_a_bits_address ^ 29'h10013000; // @[Parameters.scala 137:31]
  wire [29:0] _T_46 = {1'b0,$signed(_T_45)}; // @[Parameters.scala 137:49]
  wire [29:0] _T_48 = $signed(_T_46) & -30'sh1000; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 30'sh0; // @[Parameters.scala 137:67]
  wire  _T_59 = 3'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_60 = _source_ok_T & _T_59; // @[Mux.scala 27:73]
  wire  _T_76 = _T_60 & _T_49; // @[Monitor.scala 83:78]
  wire  _T_90 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_94 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_95 = _T_94 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_99 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_103 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_164 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_177 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_192 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
  wire  _T_200 = _T_192 & _T_49; // @[Parameters.scala 670:56]
  wire  _T_211 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_215 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_223 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_245 = source_ok & _T_200; // @[Monitor.scala 115:71]
  wire  _T_263 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_299 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_300 = io_in_a_bits_mask & _T_299; // @[Monitor.scala 127:31]
  wire  _T_301 = _T_300 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_305 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_334 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_342 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_371 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_379 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_408 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_420 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  _T_424 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_428 = io_in_d_bits_size >= 3'h2; // @[Monitor.scala 312:27]
  wire  _T_444 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_472 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_501 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_518 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_536 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [3:0] a_first_beats1_decode = is_aligned_mask[5:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] a_first_counter; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1 = a_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [28:0] address; // @[Monitor.scala 388:22]
  wire  _T_566 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_567 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_571 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_575 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_579 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_583 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
  wire [3:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [3:0] d_first_counter; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1 = d_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_590 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_591 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_599 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_603 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [11:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [3:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1_1 = a_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  reg [3:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_1 = d_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [11:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _GEN_76 = {{4'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_76 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_617 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_620 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [34:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [34:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_622 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_624 = ~_T_622[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [34:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_628 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_630 = ~_T_424; // @[Monitor.scala 671:74]
  wire  _T_631 = io_in_d_valid & d_first_1 & ~_T_424; // @[Monitor.scala 671:71]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [3:0] _GEN_22 = _d_first_T & d_first_1 & _T_630 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_23 = _d_first_T & d_first_1 & _T_630 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_617 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_641 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_643 = _T_641[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_648 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_649 = io_in_d_bits_opcode == _GEN_32 | _T_648; // @[Monitor.scala 685:77]
  wire  _T_653 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_660 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_661 = io_in_d_bits_opcode == _GEN_48 | _T_660; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_665 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_675 = _T_628 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_630; // @[Monitor.scala 694:116]
  wire  _T_677 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set = _GEN_16[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_22[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_19[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_23[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [11:0] a_sizes_set = _GEN_20[11:0];
  wire [11:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [11:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_686 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [2:0] inflight_1; // @[Monitor.scala 723:35]
  reg [11:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [3:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_2 = d_first_counter_2 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 4'h0; // @[Edges.scala 230:25]
  wire [11:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [15:0] _GEN_87 = {{4'd0}, _c_size_lookup_T_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_87 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_712 = io_in_d_valid & d_first_2 & _T_424; // @[Monitor.scala 779:71]
  wire [3:0] _GEN_67 = _d_first_T & d_first_2 & _T_424 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 783:90 784:21]
  wire [46:0] _GEN_68 = _d_first_T & d_first_2 & _T_424 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 785:21]
  wire [2:0] _T_720 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_730 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [2:0] d_clr_1 = _GEN_67[2:0];
  wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [2:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [11:0] d_opcodes_clr_1 = _GEN_68[11:0];
  wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [11:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_750 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 4'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 4'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 12'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 4'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 4'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 3'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 12'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 4'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_164 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_164) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_200 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_200) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_301 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_301) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_334 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_334) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_371 & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~_T_371) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_408 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_408) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_420 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_420) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_501 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_501 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_518 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_518 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_536 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_536 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_567 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_567) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_571 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_571) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_575 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_575) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_579 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_579) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_583 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_583) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_591 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_591) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_599 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_599) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_603 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_603) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_624 & (_T_620 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_620 & ~reset & ~_T_624) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_643 & (_T_631 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & _T_2 & ~_T_643) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_649 & (_T_631 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & same_cycle_resp & _T_2 & ~_T_649) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_653 & (_T_631 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & same_cycle_resp & _T_2 & ~_T_653) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_661 & (_T_631 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & ~same_cycle_resp & _T_2 & ~_T_661) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_665 & (_T_631 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & ~same_cycle_resp & _T_2 & ~_T_665) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_677 & (_T_675 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_675 & _T_2 & ~_T_677) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_686 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_686) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_720[0] & (_T_712 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_712 & _T_2 & ~_T_720[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_730 & (_T_712 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_712 & _T_2 & ~_T_730) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_750 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_750) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[28:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[2:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[1:0];
  _RAND_10 = {1{`RANDOM}};
  inflight = _RAND_10[2:0];
  _RAND_11 = {1{`RANDOM}};
  inflight_opcodes = _RAND_11[11:0];
  _RAND_12 = {1{`RANDOM}};
  inflight_sizes = _RAND_12[11:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[3:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[3:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  inflight_1 = _RAND_16[2:0];
  _RAND_17 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_17[11:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[3:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Repeater(
  input         clock,
  input         reset,
  input         io_repeat,
  output        io_full,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [2:0]  io_enq_bits_opcode,
  input  [2:0]  io_enq_bits_param,
  input  [2:0]  io_enq_bits_size,
  input  [1:0]  io_enq_bits_source,
  input  [28:0] io_enq_bits_address,
  input  [3:0]  io_enq_bits_mask,
  input         io_enq_bits_corrupt,
  input         io_deq_ready,
  output        io_deq_valid,
  output [2:0]  io_deq_bits_opcode,
  output [2:0]  io_deq_bits_param,
  output [2:0]  io_deq_bits_size,
  output [1:0]  io_deq_bits_source,
  output [28:0] io_deq_bits_address,
  output [3:0]  io_deq_bits_mask,
  output        io_deq_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
`endif // RANDOMIZE_REG_INIT
  reg  full; // @[Repeater.scala 19:21]
  reg [2:0] saved_opcode; // @[Repeater.scala 20:18]
  reg [2:0] saved_param; // @[Repeater.scala 20:18]
  reg [2:0] saved_size; // @[Repeater.scala 20:18]
  reg [1:0] saved_source; // @[Repeater.scala 20:18]
  reg [28:0] saved_address; // @[Repeater.scala 20:18]
  reg [3:0] saved_mask; // @[Repeater.scala 20:18]
  reg  saved_corrupt; // @[Repeater.scala 20:18]
  wire  _T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
  wire  _GEN_0 = _T & io_repeat | full; // @[Repeater.scala 19:21 28:{38,45}]
  wire  _T_2 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
  assign io_full = full; // @[Repeater.scala 26:11]
  assign io_enq_ready = io_deq_ready & ~full; // @[Repeater.scala 24:32]
  assign io_deq_valid = io_enq_valid | full; // @[Repeater.scala 23:32]
  assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode; // @[Repeater.scala 25:21]
  assign io_deq_bits_param = full ? saved_param : io_enq_bits_param; // @[Repeater.scala 25:21]
  assign io_deq_bits_size = full ? saved_size : io_enq_bits_size; // @[Repeater.scala 25:21]
  assign io_deq_bits_source = full ? saved_source : io_enq_bits_source; // @[Repeater.scala 25:21]
  assign io_deq_bits_address = full ? saved_address : io_enq_bits_address; // @[Repeater.scala 25:21]
  assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask; // @[Repeater.scala 25:21]
  assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt; // @[Repeater.scala 25:21]
  always @(posedge clock) begin
    if (reset) begin // @[Repeater.scala 19:21]
      full <= 1'h0; // @[Repeater.scala 19:21]
    end else if (_T_2 & ~io_repeat) begin // @[Repeater.scala 29:38]
      full <= 1'h0; // @[Repeater.scala 29:45]
    end else begin
      full <= _GEN_0;
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_opcode <= io_enq_bits_opcode; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_param <= io_enq_bits_param; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_size <= io_enq_bits_size; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_source <= io_enq_bits_source; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_address <= io_enq_bits_address; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_mask <= io_enq_bits_mask; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_corrupt <= io_enq_bits_corrupt; // @[Repeater.scala 28:62]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  full = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  saved_opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  saved_param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  saved_size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  saved_source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  saved_address = _RAND_5[28:0];
  _RAND_6 = {1{`RANDOM}};
  saved_mask = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  saved_corrupt = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLFragmenter(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [28:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output [31:0] auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [1:0]  auto_out_a_bits_size,
  output [6:0]  auto_out_a_bits_source,
  output [28:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_size,
  input  [6:0]  auto_out_d_bits_source,
  input  [31:0] auto_out_d_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  repeater_clock; // @[Fragmenter.scala 262:30]
  wire  repeater_reset; // @[Fragmenter.scala 262:30]
  wire  repeater_io_repeat; // @[Fragmenter.scala 262:30]
  wire  repeater_io_full; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
  wire [28:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
  wire [28:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
  reg [3:0] acknum; // @[Fragmenter.scala 189:29]
  reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
  reg  dToggle; // @[Fragmenter.scala 191:30]
  wire [3:0] dFragnum = auto_out_d_bits_source[3:0]; // @[Fragmenter.scala 192:41]
  wire  dFirst = acknum == 4'h0; // @[Fragmenter.scala 193:29]
  wire  dLast = dFragnum == 4'h0; // @[Fragmenter.scala 194:30]
  wire [3:0] _dsizeOH_T = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 64:12]
  wire [2:0] dsizeOH = _dsizeOH_T[2:0]; // @[OneHot.scala 64:27]
  wire [4:0] _dsizeOH1_T_1 = 5'h3 << auto_out_d_bits_size; // @[package.scala 234:77]
  wire [1:0] dsizeOH1 = ~_dsizeOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  dHasData = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  _T_5 = ~reset; // @[Fragmenter.scala 202:16]
  wire  ack_decrement = dHasData | dsizeOH[2]; // @[Fragmenter.scala 204:32]
  wire [5:0] _dFirst_size_T = {dFragnum, 2'h0}; // @[Fragmenter.scala 206:47]
  wire [5:0] _GEN_7 = {{4'd0}, dsizeOH1}; // @[Fragmenter.scala 206:69]
  wire [5:0] _dFirst_size_T_1 = _dFirst_size_T | _GEN_7; // @[Fragmenter.scala 206:69]
  wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala 232:35]
  wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
  wire [6:0] _dFirst_size_T_4 = {1'h0,_dFirst_size_T_1}; // @[Cat.scala 31:58]
  wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
  wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
  wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
  wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
  wire [3:0] _GEN_8 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
  wire [3:0] _dFirst_size_T_8 = _GEN_8 | dFirst_size_lo; // @[OneHot.scala 32:28]
  wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
  wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
  wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
  wire  drop = ~dHasData & ~dLast; // @[Fragmenter.scala 222:30]
  wire  bundleOut_0_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  wire  _T_7 = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
  wire [3:0] _GEN_9 = {{3'd0}, ack_decrement}; // @[Fragmenter.scala 209:55]
  wire [3:0] _acknum_T_1 = acknum - _GEN_9; // @[Fragmenter.scala 209:55]
  wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h2 ? 3'h2 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
  wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
  wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
  wire [8:0] _aFragOH1_T_1 = 9'h3 << aFrag; // @[package.scala 234:77]
  wire [1:0] aFragOH1 = ~_aFragOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  aHasData = ~repeater_io_deq_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] gennum; // @[Fragmenter.scala 291:29]
  wire  aFirst = gennum == 4'h0; // @[Fragmenter.scala 292:29]
  wire [3:0] _old_gennum1_T_2 = gennum - 4'h1; // @[Fragmenter.scala 293:79]
  wire [3:0] old_gennum1 = aFirst ? aOrigOH1[5:2] : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
  wire [3:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
  wire [3:0] new_gennum = ~_new_gennum_T; // @[Fragmenter.scala 294:26]
  reg  aToggle_r; // @[Reg.scala 16:16]
  wire  _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
  wire  aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
  wire  bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  wire  _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
  wire  _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala 302:31]
  wire [5:0] _bundleOut_0_a_bits_address_T = {old_gennum1, 2'h0}; // @[Fragmenter.scala 304:65]
  wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
  wire [5:0] _bundleOut_0_a_bits_address_T_2 = _bundleOut_0_a_bits_address_T | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
  wire [5:0] _GEN_10 = {{4'd0}, aFragOH1}; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_10; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_4 = _bundleOut_0_a_bits_address_T_3 | 6'h3; // @[Fragmenter.scala 304:111]
  wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_4; // @[Fragmenter.scala 304:51]
  wire [28:0] _GEN_11 = {{23'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
  wire [2:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aToggle}; // @[Cat.scala 31:58]
  wire  _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
  TLMonitor_7 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  Repeater repeater ( // @[Fragmenter.scala 262:30]
    .clock(repeater_clock),
    .reset(repeater_reset),
    .io_repeat(repeater_io_repeat),
    .io_full(repeater_io_full),
    .io_enq_ready(repeater_io_enq_ready),
    .io_enq_valid(repeater_io_enq_valid),
    .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
    .io_enq_bits_param(repeater_io_enq_bits_param),
    .io_enq_bits_size(repeater_io_enq_bits_size),
    .io_enq_bits_source(repeater_io_enq_bits_source),
    .io_enq_bits_address(repeater_io_enq_bits_address),
    .io_enq_bits_mask(repeater_io_enq_bits_mask),
    .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
    .io_deq_ready(repeater_io_deq_ready),
    .io_deq_valid(repeater_io_deq_valid),
    .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
    .io_deq_bits_param(repeater_io_deq_bits_param),
    .io_deq_bits_size(repeater_io_deq_bits_size),
    .io_deq_bits_source(repeater_io_deq_bits_source),
    .io_deq_bits_address(repeater_io_deq_bits_address),
    .io_deq_bits_mask(repeater_io_deq_bits_mask),
    .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
  );
  assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign auto_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign auto_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_size = aFrag[1:0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
  assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,new_gennum}; // @[Cat.scala 31:58]
  assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_11; // @[Fragmenter.scala 304:49]
  assign auto_out_a_bits_mask = repeater_io_full ? 4'hf : auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = repeater_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign repeater_clock = clock;
  assign repeater_reset = reset;
  assign repeater_io_repeat = ~aHasData & new_gennum != 4'h0; // @[Fragmenter.scala 302:41]
  assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  always @(posedge clock) begin
    if (reset) begin // @[Fragmenter.scala 189:29]
      acknum <= 4'h0; // @[Fragmenter.scala 189:29]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 209:24]
        acknum <= dFragnum;
      end else begin
        acknum <= _acknum_T_1;
      end
    end
    if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
      end
    end
    if (reset) begin // @[Fragmenter.scala 191:30]
      dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dToggle <= auto_out_d_bits_source[4]; // @[Fragmenter.scala 212:21]
      end
    end
    if (reset) begin // @[Fragmenter.scala 291:29]
      gennum <= 4'h0; // @[Fragmenter.scala 291:29]
    end else if (_T_8) begin // @[Fragmenter.scala 300:29]
      gennum <= new_gennum; // @[Fragmenter.scala 300:38]
    end
    if (aFirst) begin // @[Reg.scala 17:18]
      aToggle_r <= dToggle; // @[Reg.scala 17:22]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~repeater_io_full | _repeater_io_repeat_T) & _T_5) begin
          $fatal; // @[Fragmenter.scala 309:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(~repeater_io_full | _repeater_io_repeat_T)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Fragmenter.scala:309 assert (!repeater.io.full || !aHasData)\n"
            ); // @[Fragmenter.scala 309:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_9 | repeater_io_deq_bits_mask == 4'hf) & _T_5) begin
          $fatal; // @[Fragmenter.scala 312:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask == 4'hf)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
            ); // @[Fragmenter.scala 312:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  acknum = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  dOrig = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  dToggle = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  gennum = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  aToggle_r = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLInterconnectCoupler_4(
  input         clock,
  input         reset,
  input         auto_control_xing_out_a_ready,
  output        auto_control_xing_out_a_valid,
  output [2:0]  auto_control_xing_out_a_bits_opcode,
  output [2:0]  auto_control_xing_out_a_bits_param,
  output [1:0]  auto_control_xing_out_a_bits_size,
  output [6:0]  auto_control_xing_out_a_bits_source,
  output [28:0] auto_control_xing_out_a_bits_address,
  output [3:0]  auto_control_xing_out_a_bits_mask,
  output [31:0] auto_control_xing_out_a_bits_data,
  output        auto_control_xing_out_a_bits_corrupt,
  output        auto_control_xing_out_d_ready,
  input         auto_control_xing_out_d_valid,
  input  [2:0]  auto_control_xing_out_d_bits_opcode,
  input  [1:0]  auto_control_xing_out_d_bits_size,
  input  [6:0]  auto_control_xing_out_d_bits_source,
  input  [31:0] auto_control_xing_out_d_bits_data,
  output        auto_tl_in_a_ready,
  input         auto_tl_in_a_valid,
  input  [2:0]  auto_tl_in_a_bits_opcode,
  input  [2:0]  auto_tl_in_a_bits_param,
  input  [2:0]  auto_tl_in_a_bits_size,
  input  [1:0]  auto_tl_in_a_bits_source,
  input  [28:0] auto_tl_in_a_bits_address,
  input  [3:0]  auto_tl_in_a_bits_mask,
  input  [31:0] auto_tl_in_a_bits_data,
  input         auto_tl_in_a_bits_corrupt,
  input         auto_tl_in_d_ready,
  output        auto_tl_in_d_valid,
  output [2:0]  auto_tl_in_d_bits_opcode,
  output [2:0]  auto_tl_in_d_bits_size,
  output [1:0]  auto_tl_in_d_bits_source,
  output [31:0] auto_tl_in_d_bits_data
);
  wire  fragmenter_clock; // @[Fragmenter.scala 333:34]
  wire  fragmenter_reset; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [28:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [28:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
  TLFragmenter fragmenter ( // @[Fragmenter.scala 333:34]
    .clock(fragmenter_clock),
    .reset(fragmenter_reset),
    .auto_in_a_ready(fragmenter_auto_in_a_ready),
    .auto_in_a_valid(fragmenter_auto_in_a_valid),
    .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
    .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
    .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
    .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
    .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
    .auto_in_a_bits_data(fragmenter_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
    .auto_in_d_ready(fragmenter_auto_in_d_ready),
    .auto_in_d_valid(fragmenter_auto_in_d_valid),
    .auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
    .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
    .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
    .auto_out_a_ready(fragmenter_auto_out_a_ready),
    .auto_out_a_valid(fragmenter_auto_out_a_valid),
    .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
    .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
    .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
    .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
    .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
    .auto_out_a_bits_data(fragmenter_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
    .auto_out_d_ready(fragmenter_auto_out_d_ready),
    .auto_out_d_valid(fragmenter_auto_out_d_valid),
    .auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
    .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
    .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
  );
  assign auto_control_xing_out_a_valid = fragmenter_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_data = fragmenter_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_d_ready = fragmenter_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_in_a_ready = fragmenter_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_valid = fragmenter_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_size = fragmenter_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_source = fragmenter_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_data = fragmenter_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign fragmenter_clock = clock;
  assign fragmenter_reset = reset;
  assign fragmenter_auto_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_data = auto_tl_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_out_a_ready = auto_control_xing_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_valid = auto_control_xing_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_opcode = auto_control_xing_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_size = auto_control_xing_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_source = auto_control_xing_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_data = auto_control_xing_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
endmodule
module TLMonitor_8(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [28:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [2:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
  wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
  wire [28:0] _GEN_71 = {{23'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [28:0] _T_45 = io_in_a_bits_address ^ 29'h10023000; // @[Parameters.scala 137:31]
  wire [29:0] _T_46 = {1'b0,$signed(_T_45)}; // @[Parameters.scala 137:49]
  wire [29:0] _T_48 = $signed(_T_46) & -30'sh1000; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 30'sh0; // @[Parameters.scala 137:67]
  wire  _T_59 = 3'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_60 = _source_ok_T & _T_59; // @[Mux.scala 27:73]
  wire  _T_76 = _T_60 & _T_49; // @[Monitor.scala 83:78]
  wire  _T_90 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_94 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_95 = _T_94 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_99 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_103 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_164 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_177 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_192 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
  wire  _T_200 = _T_192 & _T_49; // @[Parameters.scala 670:56]
  wire  _T_211 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_215 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_223 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_245 = source_ok & _T_200; // @[Monitor.scala 115:71]
  wire  _T_263 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_299 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_300 = io_in_a_bits_mask & _T_299; // @[Monitor.scala 127:31]
  wire  _T_301 = _T_300 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_305 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_334 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_342 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_371 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_379 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_408 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_420 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  _T_424 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_428 = io_in_d_bits_size >= 3'h2; // @[Monitor.scala 312:27]
  wire  _T_444 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_472 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_501 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_518 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_536 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [3:0] a_first_beats1_decode = is_aligned_mask[5:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] a_first_counter; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1 = a_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [28:0] address; // @[Monitor.scala 388:22]
  wire  _T_566 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_567 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_571 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_575 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_579 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_583 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
  wire [3:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [3:0] d_first_counter; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1 = d_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_590 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_591 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_599 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_603 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [11:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [3:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1_1 = a_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  reg [3:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_1 = d_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [11:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _GEN_76 = {{4'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_76 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_617 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_620 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [34:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [34:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_622 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_624 = ~_T_622[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [34:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_628 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_630 = ~_T_424; // @[Monitor.scala 671:74]
  wire  _T_631 = io_in_d_valid & d_first_1 & ~_T_424; // @[Monitor.scala 671:71]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [3:0] _GEN_22 = _d_first_T & d_first_1 & _T_630 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_23 = _d_first_T & d_first_1 & _T_630 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_617 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_641 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_643 = _T_641[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_648 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_649 = io_in_d_bits_opcode == _GEN_32 | _T_648; // @[Monitor.scala 685:77]
  wire  _T_653 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_660 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_661 = io_in_d_bits_opcode == _GEN_48 | _T_660; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_665 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_675 = _T_628 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_630; // @[Monitor.scala 694:116]
  wire  _T_677 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set = _GEN_16[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_22[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_19[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_23[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [11:0] a_sizes_set = _GEN_20[11:0];
  wire [11:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [11:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_686 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [2:0] inflight_1; // @[Monitor.scala 723:35]
  reg [11:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [3:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_2 = d_first_counter_2 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 4'h0; // @[Edges.scala 230:25]
  wire [11:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [15:0] _GEN_87 = {{4'd0}, _c_size_lookup_T_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_87 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_712 = io_in_d_valid & d_first_2 & _T_424; // @[Monitor.scala 779:71]
  wire [3:0] _GEN_67 = _d_first_T & d_first_2 & _T_424 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 783:90 784:21]
  wire [46:0] _GEN_68 = _d_first_T & d_first_2 & _T_424 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 785:21]
  wire [2:0] _T_720 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_730 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [2:0] d_clr_1 = _GEN_67[2:0];
  wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [2:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [11:0] d_opcodes_clr_1 = _GEN_68[11:0];
  wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [11:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_750 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 4'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 4'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 12'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 4'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 4'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 3'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 12'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 4'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_164 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_164) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_200 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_200) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_301 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_301) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_334 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_334) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_371 & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~_T_371) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_408 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_408) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_420 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_420) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_501 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_501 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_518 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_518 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_536 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_536 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_567 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_567) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_571 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_571) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_575 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_575) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_579 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_579) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_583 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_583) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_591 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_591) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_599 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_599) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_603 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_603) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_624 & (_T_620 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_620 & ~reset & ~_T_624) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_643 & (_T_631 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & _T_2 & ~_T_643) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_649 & (_T_631 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & same_cycle_resp & _T_2 & ~_T_649) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_653 & (_T_631 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & same_cycle_resp & _T_2 & ~_T_653) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_661 & (_T_631 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & ~same_cycle_resp & _T_2 & ~_T_661) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_665 & (_T_631 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & ~same_cycle_resp & _T_2 & ~_T_665) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_677 & (_T_675 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_675 & _T_2 & ~_T_677) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_686 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_686) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_720[0] & (_T_712 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_712 & _T_2 & ~_T_720[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_730 & (_T_712 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_712 & _T_2 & ~_T_730) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_750 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_750) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[28:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[2:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[1:0];
  _RAND_10 = {1{`RANDOM}};
  inflight = _RAND_10[2:0];
  _RAND_11 = {1{`RANDOM}};
  inflight_opcodes = _RAND_11[11:0];
  _RAND_12 = {1{`RANDOM}};
  inflight_sizes = _RAND_12[11:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[3:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[3:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  inflight_1 = _RAND_16[2:0];
  _RAND_17 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_17[11:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[3:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLFragmenter_1(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [28:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output [31:0] auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [1:0]  auto_out_a_bits_size,
  output [6:0]  auto_out_a_bits_source,
  output [28:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_size,
  input  [6:0]  auto_out_d_bits_source,
  input  [31:0] auto_out_d_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  repeater_clock; // @[Fragmenter.scala 262:30]
  wire  repeater_reset; // @[Fragmenter.scala 262:30]
  wire  repeater_io_repeat; // @[Fragmenter.scala 262:30]
  wire  repeater_io_full; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
  wire [28:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
  wire [28:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
  reg [3:0] acknum; // @[Fragmenter.scala 189:29]
  reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
  reg  dToggle; // @[Fragmenter.scala 191:30]
  wire [3:0] dFragnum = auto_out_d_bits_source[3:0]; // @[Fragmenter.scala 192:41]
  wire  dFirst = acknum == 4'h0; // @[Fragmenter.scala 193:29]
  wire  dLast = dFragnum == 4'h0; // @[Fragmenter.scala 194:30]
  wire [3:0] _dsizeOH_T = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 64:12]
  wire [2:0] dsizeOH = _dsizeOH_T[2:0]; // @[OneHot.scala 64:27]
  wire [4:0] _dsizeOH1_T_1 = 5'h3 << auto_out_d_bits_size; // @[package.scala 234:77]
  wire [1:0] dsizeOH1 = ~_dsizeOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  dHasData = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  _T_5 = ~reset; // @[Fragmenter.scala 202:16]
  wire  ack_decrement = dHasData | dsizeOH[2]; // @[Fragmenter.scala 204:32]
  wire [5:0] _dFirst_size_T = {dFragnum, 2'h0}; // @[Fragmenter.scala 206:47]
  wire [5:0] _GEN_7 = {{4'd0}, dsizeOH1}; // @[Fragmenter.scala 206:69]
  wire [5:0] _dFirst_size_T_1 = _dFirst_size_T | _GEN_7; // @[Fragmenter.scala 206:69]
  wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala 232:35]
  wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
  wire [6:0] _dFirst_size_T_4 = {1'h0,_dFirst_size_T_1}; // @[Cat.scala 31:58]
  wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
  wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
  wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
  wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
  wire [3:0] _GEN_8 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
  wire [3:0] _dFirst_size_T_8 = _GEN_8 | dFirst_size_lo; // @[OneHot.scala 32:28]
  wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
  wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
  wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
  wire  drop = ~dHasData & ~dLast; // @[Fragmenter.scala 222:30]
  wire  bundleOut_0_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  wire  _T_7 = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
  wire [3:0] _GEN_9 = {{3'd0}, ack_decrement}; // @[Fragmenter.scala 209:55]
  wire [3:0] _acknum_T_1 = acknum - _GEN_9; // @[Fragmenter.scala 209:55]
  wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h2 ? 3'h2 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
  wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
  wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
  wire [8:0] _aFragOH1_T_1 = 9'h3 << aFrag; // @[package.scala 234:77]
  wire [1:0] aFragOH1 = ~_aFragOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  aHasData = ~repeater_io_deq_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] gennum; // @[Fragmenter.scala 291:29]
  wire  aFirst = gennum == 4'h0; // @[Fragmenter.scala 292:29]
  wire [3:0] _old_gennum1_T_2 = gennum - 4'h1; // @[Fragmenter.scala 293:79]
  wire [3:0] old_gennum1 = aFirst ? aOrigOH1[5:2] : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
  wire [3:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
  wire [3:0] new_gennum = ~_new_gennum_T; // @[Fragmenter.scala 294:26]
  reg  aToggle_r; // @[Reg.scala 16:16]
  wire  _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
  wire  aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
  wire  bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  wire  _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
  wire  _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala 302:31]
  wire [5:0] _bundleOut_0_a_bits_address_T = {old_gennum1, 2'h0}; // @[Fragmenter.scala 304:65]
  wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
  wire [5:0] _bundleOut_0_a_bits_address_T_2 = _bundleOut_0_a_bits_address_T | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
  wire [5:0] _GEN_10 = {{4'd0}, aFragOH1}; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_10; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_4 = _bundleOut_0_a_bits_address_T_3 | 6'h3; // @[Fragmenter.scala 304:111]
  wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_4; // @[Fragmenter.scala 304:51]
  wire [28:0] _GEN_11 = {{23'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
  wire [2:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aToggle}; // @[Cat.scala 31:58]
  wire  _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
  TLMonitor_8 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  Repeater repeater ( // @[Fragmenter.scala 262:30]
    .clock(repeater_clock),
    .reset(repeater_reset),
    .io_repeat(repeater_io_repeat),
    .io_full(repeater_io_full),
    .io_enq_ready(repeater_io_enq_ready),
    .io_enq_valid(repeater_io_enq_valid),
    .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
    .io_enq_bits_param(repeater_io_enq_bits_param),
    .io_enq_bits_size(repeater_io_enq_bits_size),
    .io_enq_bits_source(repeater_io_enq_bits_source),
    .io_enq_bits_address(repeater_io_enq_bits_address),
    .io_enq_bits_mask(repeater_io_enq_bits_mask),
    .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
    .io_deq_ready(repeater_io_deq_ready),
    .io_deq_valid(repeater_io_deq_valid),
    .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
    .io_deq_bits_param(repeater_io_deq_bits_param),
    .io_deq_bits_size(repeater_io_deq_bits_size),
    .io_deq_bits_source(repeater_io_deq_bits_source),
    .io_deq_bits_address(repeater_io_deq_bits_address),
    .io_deq_bits_mask(repeater_io_deq_bits_mask),
    .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
  );
  assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign auto_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign auto_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_size = aFrag[1:0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
  assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,new_gennum}; // @[Cat.scala 31:58]
  assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_11; // @[Fragmenter.scala 304:49]
  assign auto_out_a_bits_mask = repeater_io_full ? 4'hf : auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = repeater_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign repeater_clock = clock;
  assign repeater_reset = reset;
  assign repeater_io_repeat = ~aHasData & new_gennum != 4'h0; // @[Fragmenter.scala 302:41]
  assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  always @(posedge clock) begin
    if (reset) begin // @[Fragmenter.scala 189:29]
      acknum <= 4'h0; // @[Fragmenter.scala 189:29]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 209:24]
        acknum <= dFragnum;
      end else begin
        acknum <= _acknum_T_1;
      end
    end
    if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
      end
    end
    if (reset) begin // @[Fragmenter.scala 191:30]
      dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dToggle <= auto_out_d_bits_source[4]; // @[Fragmenter.scala 212:21]
      end
    end
    if (reset) begin // @[Fragmenter.scala 291:29]
      gennum <= 4'h0; // @[Fragmenter.scala 291:29]
    end else if (_T_8) begin // @[Fragmenter.scala 300:29]
      gennum <= new_gennum; // @[Fragmenter.scala 300:38]
    end
    if (aFirst) begin // @[Reg.scala 17:18]
      aToggle_r <= dToggle; // @[Reg.scala 17:22]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~repeater_io_full | _repeater_io_repeat_T) & _T_5) begin
          $fatal; // @[Fragmenter.scala 309:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(~repeater_io_full | _repeater_io_repeat_T)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Fragmenter.scala:309 assert (!repeater.io.full || !aHasData)\n"
            ); // @[Fragmenter.scala 309:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_9 | repeater_io_deq_bits_mask == 4'hf) & _T_5) begin
          $fatal; // @[Fragmenter.scala 312:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask == 4'hf)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
            ); // @[Fragmenter.scala 312:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  acknum = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  dOrig = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  dToggle = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  gennum = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  aToggle_r = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLInterconnectCoupler_5(
  input         clock,
  input         reset,
  input         auto_control_xing_out_a_ready,
  output        auto_control_xing_out_a_valid,
  output [2:0]  auto_control_xing_out_a_bits_opcode,
  output [2:0]  auto_control_xing_out_a_bits_param,
  output [1:0]  auto_control_xing_out_a_bits_size,
  output [6:0]  auto_control_xing_out_a_bits_source,
  output [28:0] auto_control_xing_out_a_bits_address,
  output [3:0]  auto_control_xing_out_a_bits_mask,
  output [31:0] auto_control_xing_out_a_bits_data,
  output        auto_control_xing_out_a_bits_corrupt,
  output        auto_control_xing_out_d_ready,
  input         auto_control_xing_out_d_valid,
  input  [2:0]  auto_control_xing_out_d_bits_opcode,
  input  [1:0]  auto_control_xing_out_d_bits_size,
  input  [6:0]  auto_control_xing_out_d_bits_source,
  input  [31:0] auto_control_xing_out_d_bits_data,
  output        auto_tl_in_a_ready,
  input         auto_tl_in_a_valid,
  input  [2:0]  auto_tl_in_a_bits_opcode,
  input  [2:0]  auto_tl_in_a_bits_param,
  input  [2:0]  auto_tl_in_a_bits_size,
  input  [1:0]  auto_tl_in_a_bits_source,
  input  [28:0] auto_tl_in_a_bits_address,
  input  [3:0]  auto_tl_in_a_bits_mask,
  input  [31:0] auto_tl_in_a_bits_data,
  input         auto_tl_in_a_bits_corrupt,
  input         auto_tl_in_d_ready,
  output        auto_tl_in_d_valid,
  output [2:0]  auto_tl_in_d_bits_opcode,
  output [2:0]  auto_tl_in_d_bits_size,
  output [1:0]  auto_tl_in_d_bits_source,
  output [31:0] auto_tl_in_d_bits_data
);
  wire  fragmenter_clock; // @[Fragmenter.scala 333:34]
  wire  fragmenter_reset; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [28:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [28:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
  TLFragmenter_1 fragmenter ( // @[Fragmenter.scala 333:34]
    .clock(fragmenter_clock),
    .reset(fragmenter_reset),
    .auto_in_a_ready(fragmenter_auto_in_a_ready),
    .auto_in_a_valid(fragmenter_auto_in_a_valid),
    .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
    .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
    .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
    .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
    .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
    .auto_in_a_bits_data(fragmenter_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
    .auto_in_d_ready(fragmenter_auto_in_d_ready),
    .auto_in_d_valid(fragmenter_auto_in_d_valid),
    .auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
    .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
    .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
    .auto_out_a_ready(fragmenter_auto_out_a_ready),
    .auto_out_a_valid(fragmenter_auto_out_a_valid),
    .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
    .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
    .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
    .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
    .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
    .auto_out_a_bits_data(fragmenter_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
    .auto_out_d_ready(fragmenter_auto_out_d_ready),
    .auto_out_d_valid(fragmenter_auto_out_d_valid),
    .auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
    .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
    .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
  );
  assign auto_control_xing_out_a_valid = fragmenter_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_data = fragmenter_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_d_ready = fragmenter_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_in_a_ready = fragmenter_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_valid = fragmenter_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_size = fragmenter_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_source = fragmenter_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_data = fragmenter_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign fragmenter_clock = clock;
  assign fragmenter_reset = reset;
  assign fragmenter_auto_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_data = auto_tl_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_out_a_ready = auto_control_xing_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_valid = auto_control_xing_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_opcode = auto_control_xing_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_size = auto_control_xing_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_source = auto_control_xing_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_data = auto_control_xing_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
endmodule
module TLMonitor_9(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [28:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [2:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
  wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
  wire [28:0] _GEN_71 = {{23'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [28:0] _T_45 = io_in_a_bits_address ^ 29'h10033000; // @[Parameters.scala 137:31]
  wire [29:0] _T_46 = {1'b0,$signed(_T_45)}; // @[Parameters.scala 137:49]
  wire [29:0] _T_48 = $signed(_T_46) & -30'sh1000; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 30'sh0; // @[Parameters.scala 137:67]
  wire  _T_59 = 3'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_60 = _source_ok_T & _T_59; // @[Mux.scala 27:73]
  wire  _T_76 = _T_60 & _T_49; // @[Monitor.scala 83:78]
  wire  _T_90 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_94 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_95 = _T_94 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_99 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_103 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_164 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_177 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_192 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
  wire  _T_200 = _T_192 & _T_49; // @[Parameters.scala 670:56]
  wire  _T_211 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_215 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_223 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_245 = source_ok & _T_200; // @[Monitor.scala 115:71]
  wire  _T_263 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_299 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_300 = io_in_a_bits_mask & _T_299; // @[Monitor.scala 127:31]
  wire  _T_301 = _T_300 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_305 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_334 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_342 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_371 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_379 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_408 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_420 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  _T_424 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_428 = io_in_d_bits_size >= 3'h2; // @[Monitor.scala 312:27]
  wire  _T_444 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_472 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_501 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_518 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_536 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [3:0] a_first_beats1_decode = is_aligned_mask[5:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] a_first_counter; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1 = a_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [28:0] address; // @[Monitor.scala 388:22]
  wire  _T_566 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_567 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_571 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_575 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_579 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_583 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
  wire [3:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [3:0] d_first_counter; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1 = d_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_590 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_591 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_599 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_603 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [11:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [3:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1_1 = a_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  reg [3:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_1 = d_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [11:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _GEN_76 = {{4'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_76 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_617 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_620 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [34:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [34:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_622 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_624 = ~_T_622[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [34:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_628 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_630 = ~_T_424; // @[Monitor.scala 671:74]
  wire  _T_631 = io_in_d_valid & d_first_1 & ~_T_424; // @[Monitor.scala 671:71]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [3:0] _GEN_22 = _d_first_T & d_first_1 & _T_630 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_23 = _d_first_T & d_first_1 & _T_630 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_617 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_641 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_643 = _T_641[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_648 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_649 = io_in_d_bits_opcode == _GEN_32 | _T_648; // @[Monitor.scala 685:77]
  wire  _T_653 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_660 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_661 = io_in_d_bits_opcode == _GEN_48 | _T_660; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_665 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_675 = _T_628 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_630; // @[Monitor.scala 694:116]
  wire  _T_677 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set = _GEN_16[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_22[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_19[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_23[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [11:0] a_sizes_set = _GEN_20[11:0];
  wire [11:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [11:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_686 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [2:0] inflight_1; // @[Monitor.scala 723:35]
  reg [11:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [3:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_2 = d_first_counter_2 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 4'h0; // @[Edges.scala 230:25]
  wire [11:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [15:0] _GEN_87 = {{4'd0}, _c_size_lookup_T_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_87 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_712 = io_in_d_valid & d_first_2 & _T_424; // @[Monitor.scala 779:71]
  wire [3:0] _GEN_67 = _d_first_T & d_first_2 & _T_424 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 783:90 784:21]
  wire [46:0] _GEN_68 = _d_first_T & d_first_2 & _T_424 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 785:21]
  wire [2:0] _T_720 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_730 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [2:0] d_clr_1 = _GEN_67[2:0];
  wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [2:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [11:0] d_opcodes_clr_1 = _GEN_68[11:0];
  wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [11:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_750 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 4'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 4'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 12'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 4'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 4'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 3'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 12'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 4'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_164 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_164) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_200 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_200) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_301 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_301) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_334 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_334) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_371 & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~_T_371) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_408 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_408) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_420 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_420) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_501 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_501 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_518 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_518 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_536 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_536 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_567 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_567) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_571 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_571) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_575 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_575) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_579 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_579) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_583 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_583) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_591 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_591) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_599 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_599) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_603 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_603) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_624 & (_T_620 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_620 & ~reset & ~_T_624) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_643 & (_T_631 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & _T_2 & ~_T_643) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_649 & (_T_631 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & same_cycle_resp & _T_2 & ~_T_649) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_653 & (_T_631 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & same_cycle_resp & _T_2 & ~_T_653) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_661 & (_T_631 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & ~same_cycle_resp & _T_2 & ~_T_661) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_665 & (_T_631 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & ~same_cycle_resp & _T_2 & ~_T_665) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_677 & (_T_675 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_675 & _T_2 & ~_T_677) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_686 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_686) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_720[0] & (_T_712 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_712 & _T_2 & ~_T_720[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_730 & (_T_712 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_712 & _T_2 & ~_T_730) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_750 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_750) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[28:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[2:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[1:0];
  _RAND_10 = {1{`RANDOM}};
  inflight = _RAND_10[2:0];
  _RAND_11 = {1{`RANDOM}};
  inflight_opcodes = _RAND_11[11:0];
  _RAND_12 = {1{`RANDOM}};
  inflight_sizes = _RAND_12[11:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[3:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[3:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  inflight_1 = _RAND_16[2:0];
  _RAND_17 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_17[11:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[3:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLFragmenter_2(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [28:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output [31:0] auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [1:0]  auto_out_a_bits_size,
  output [6:0]  auto_out_a_bits_source,
  output [28:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_size,
  input  [6:0]  auto_out_d_bits_source,
  input  [31:0] auto_out_d_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  repeater_clock; // @[Fragmenter.scala 262:30]
  wire  repeater_reset; // @[Fragmenter.scala 262:30]
  wire  repeater_io_repeat; // @[Fragmenter.scala 262:30]
  wire  repeater_io_full; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
  wire [28:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
  wire [28:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
  reg [3:0] acknum; // @[Fragmenter.scala 189:29]
  reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
  reg  dToggle; // @[Fragmenter.scala 191:30]
  wire [3:0] dFragnum = auto_out_d_bits_source[3:0]; // @[Fragmenter.scala 192:41]
  wire  dFirst = acknum == 4'h0; // @[Fragmenter.scala 193:29]
  wire  dLast = dFragnum == 4'h0; // @[Fragmenter.scala 194:30]
  wire [3:0] _dsizeOH_T = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 64:12]
  wire [2:0] dsizeOH = _dsizeOH_T[2:0]; // @[OneHot.scala 64:27]
  wire [4:0] _dsizeOH1_T_1 = 5'h3 << auto_out_d_bits_size; // @[package.scala 234:77]
  wire [1:0] dsizeOH1 = ~_dsizeOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  dHasData = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  _T_5 = ~reset; // @[Fragmenter.scala 202:16]
  wire  ack_decrement = dHasData | dsizeOH[2]; // @[Fragmenter.scala 204:32]
  wire [5:0] _dFirst_size_T = {dFragnum, 2'h0}; // @[Fragmenter.scala 206:47]
  wire [5:0] _GEN_7 = {{4'd0}, dsizeOH1}; // @[Fragmenter.scala 206:69]
  wire [5:0] _dFirst_size_T_1 = _dFirst_size_T | _GEN_7; // @[Fragmenter.scala 206:69]
  wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala 232:35]
  wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
  wire [6:0] _dFirst_size_T_4 = {1'h0,_dFirst_size_T_1}; // @[Cat.scala 31:58]
  wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
  wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
  wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
  wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
  wire [3:0] _GEN_8 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
  wire [3:0] _dFirst_size_T_8 = _GEN_8 | dFirst_size_lo; // @[OneHot.scala 32:28]
  wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
  wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
  wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
  wire  drop = ~dHasData & ~dLast; // @[Fragmenter.scala 222:30]
  wire  bundleOut_0_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  wire  _T_7 = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
  wire [3:0] _GEN_9 = {{3'd0}, ack_decrement}; // @[Fragmenter.scala 209:55]
  wire [3:0] _acknum_T_1 = acknum - _GEN_9; // @[Fragmenter.scala 209:55]
  wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h2 ? 3'h2 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
  wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
  wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
  wire [8:0] _aFragOH1_T_1 = 9'h3 << aFrag; // @[package.scala 234:77]
  wire [1:0] aFragOH1 = ~_aFragOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  aHasData = ~repeater_io_deq_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] gennum; // @[Fragmenter.scala 291:29]
  wire  aFirst = gennum == 4'h0; // @[Fragmenter.scala 292:29]
  wire [3:0] _old_gennum1_T_2 = gennum - 4'h1; // @[Fragmenter.scala 293:79]
  wire [3:0] old_gennum1 = aFirst ? aOrigOH1[5:2] : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
  wire [3:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
  wire [3:0] new_gennum = ~_new_gennum_T; // @[Fragmenter.scala 294:26]
  reg  aToggle_r; // @[Reg.scala 16:16]
  wire  _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
  wire  aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
  wire  bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  wire  _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
  wire  _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala 302:31]
  wire [5:0] _bundleOut_0_a_bits_address_T = {old_gennum1, 2'h0}; // @[Fragmenter.scala 304:65]
  wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
  wire [5:0] _bundleOut_0_a_bits_address_T_2 = _bundleOut_0_a_bits_address_T | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
  wire [5:0] _GEN_10 = {{4'd0}, aFragOH1}; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_10; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_4 = _bundleOut_0_a_bits_address_T_3 | 6'h3; // @[Fragmenter.scala 304:111]
  wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_4; // @[Fragmenter.scala 304:51]
  wire [28:0] _GEN_11 = {{23'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
  wire [2:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aToggle}; // @[Cat.scala 31:58]
  wire  _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
  TLMonitor_9 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  Repeater repeater ( // @[Fragmenter.scala 262:30]
    .clock(repeater_clock),
    .reset(repeater_reset),
    .io_repeat(repeater_io_repeat),
    .io_full(repeater_io_full),
    .io_enq_ready(repeater_io_enq_ready),
    .io_enq_valid(repeater_io_enq_valid),
    .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
    .io_enq_bits_param(repeater_io_enq_bits_param),
    .io_enq_bits_size(repeater_io_enq_bits_size),
    .io_enq_bits_source(repeater_io_enq_bits_source),
    .io_enq_bits_address(repeater_io_enq_bits_address),
    .io_enq_bits_mask(repeater_io_enq_bits_mask),
    .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
    .io_deq_ready(repeater_io_deq_ready),
    .io_deq_valid(repeater_io_deq_valid),
    .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
    .io_deq_bits_param(repeater_io_deq_bits_param),
    .io_deq_bits_size(repeater_io_deq_bits_size),
    .io_deq_bits_source(repeater_io_deq_bits_source),
    .io_deq_bits_address(repeater_io_deq_bits_address),
    .io_deq_bits_mask(repeater_io_deq_bits_mask),
    .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
  );
  assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign auto_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign auto_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_size = aFrag[1:0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
  assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,new_gennum}; // @[Cat.scala 31:58]
  assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_11; // @[Fragmenter.scala 304:49]
  assign auto_out_a_bits_mask = repeater_io_full ? 4'hf : auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = repeater_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign repeater_clock = clock;
  assign repeater_reset = reset;
  assign repeater_io_repeat = ~aHasData & new_gennum != 4'h0; // @[Fragmenter.scala 302:41]
  assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  always @(posedge clock) begin
    if (reset) begin // @[Fragmenter.scala 189:29]
      acknum <= 4'h0; // @[Fragmenter.scala 189:29]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 209:24]
        acknum <= dFragnum;
      end else begin
        acknum <= _acknum_T_1;
      end
    end
    if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
      end
    end
    if (reset) begin // @[Fragmenter.scala 191:30]
      dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dToggle <= auto_out_d_bits_source[4]; // @[Fragmenter.scala 212:21]
      end
    end
    if (reset) begin // @[Fragmenter.scala 291:29]
      gennum <= 4'h0; // @[Fragmenter.scala 291:29]
    end else if (_T_8) begin // @[Fragmenter.scala 300:29]
      gennum <= new_gennum; // @[Fragmenter.scala 300:38]
    end
    if (aFirst) begin // @[Reg.scala 17:18]
      aToggle_r <= dToggle; // @[Reg.scala 17:22]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~repeater_io_full | _repeater_io_repeat_T) & _T_5) begin
          $fatal; // @[Fragmenter.scala 309:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(~repeater_io_full | _repeater_io_repeat_T)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Fragmenter.scala:309 assert (!repeater.io.full || !aHasData)\n"
            ); // @[Fragmenter.scala 309:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_9 | repeater_io_deq_bits_mask == 4'hf) & _T_5) begin
          $fatal; // @[Fragmenter.scala 312:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask == 4'hf)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
            ); // @[Fragmenter.scala 312:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  acknum = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  dOrig = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  dToggle = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  gennum = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  aToggle_r = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLInterconnectCoupler_6(
  input         clock,
  input         reset,
  input         auto_control_xing_out_a_ready,
  output        auto_control_xing_out_a_valid,
  output [2:0]  auto_control_xing_out_a_bits_opcode,
  output [2:0]  auto_control_xing_out_a_bits_param,
  output [1:0]  auto_control_xing_out_a_bits_size,
  output [6:0]  auto_control_xing_out_a_bits_source,
  output [28:0] auto_control_xing_out_a_bits_address,
  output [3:0]  auto_control_xing_out_a_bits_mask,
  output [31:0] auto_control_xing_out_a_bits_data,
  output        auto_control_xing_out_a_bits_corrupt,
  output        auto_control_xing_out_d_ready,
  input         auto_control_xing_out_d_valid,
  input  [2:0]  auto_control_xing_out_d_bits_opcode,
  input  [1:0]  auto_control_xing_out_d_bits_size,
  input  [6:0]  auto_control_xing_out_d_bits_source,
  input  [31:0] auto_control_xing_out_d_bits_data,
  output        auto_tl_in_a_ready,
  input         auto_tl_in_a_valid,
  input  [2:0]  auto_tl_in_a_bits_opcode,
  input  [2:0]  auto_tl_in_a_bits_param,
  input  [2:0]  auto_tl_in_a_bits_size,
  input  [1:0]  auto_tl_in_a_bits_source,
  input  [28:0] auto_tl_in_a_bits_address,
  input  [3:0]  auto_tl_in_a_bits_mask,
  input  [31:0] auto_tl_in_a_bits_data,
  input         auto_tl_in_a_bits_corrupt,
  input         auto_tl_in_d_ready,
  output        auto_tl_in_d_valid,
  output [2:0]  auto_tl_in_d_bits_opcode,
  output [2:0]  auto_tl_in_d_bits_size,
  output [1:0]  auto_tl_in_d_bits_source,
  output [31:0] auto_tl_in_d_bits_data
);
  wire  fragmenter_clock; // @[Fragmenter.scala 333:34]
  wire  fragmenter_reset; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [28:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [28:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
  TLFragmenter_2 fragmenter ( // @[Fragmenter.scala 333:34]
    .clock(fragmenter_clock),
    .reset(fragmenter_reset),
    .auto_in_a_ready(fragmenter_auto_in_a_ready),
    .auto_in_a_valid(fragmenter_auto_in_a_valid),
    .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
    .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
    .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
    .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
    .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
    .auto_in_a_bits_data(fragmenter_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
    .auto_in_d_ready(fragmenter_auto_in_d_ready),
    .auto_in_d_valid(fragmenter_auto_in_d_valid),
    .auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
    .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
    .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
    .auto_out_a_ready(fragmenter_auto_out_a_ready),
    .auto_out_a_valid(fragmenter_auto_out_a_valid),
    .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
    .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
    .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
    .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
    .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
    .auto_out_a_bits_data(fragmenter_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
    .auto_out_d_ready(fragmenter_auto_out_d_ready),
    .auto_out_d_valid(fragmenter_auto_out_d_valid),
    .auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
    .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
    .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
  );
  assign auto_control_xing_out_a_valid = fragmenter_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_data = fragmenter_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_d_ready = fragmenter_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_in_a_ready = fragmenter_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_valid = fragmenter_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_size = fragmenter_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_source = fragmenter_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_data = fragmenter_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign fragmenter_clock = clock;
  assign fragmenter_reset = reset;
  assign fragmenter_auto_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_data = auto_tl_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_out_a_ready = auto_control_xing_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_valid = auto_control_xing_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_opcode = auto_control_xing_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_size = auto_control_xing_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_source = auto_control_xing_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_data = auto_control_xing_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
endmodule
module TLMonitor_10(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [28:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [2:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
  wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
  wire [28:0] _GEN_71 = {{23'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [28:0] _T_45 = io_in_a_bits_address ^ 29'h10043000; // @[Parameters.scala 137:31]
  wire [29:0] _T_46 = {1'b0,$signed(_T_45)}; // @[Parameters.scala 137:49]
  wire [29:0] _T_48 = $signed(_T_46) & -30'sh1000; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 30'sh0; // @[Parameters.scala 137:67]
  wire  _T_59 = 3'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_60 = _source_ok_T & _T_59; // @[Mux.scala 27:73]
  wire  _T_76 = _T_60 & _T_49; // @[Monitor.scala 83:78]
  wire  _T_90 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_94 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_95 = _T_94 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_99 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_103 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_164 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_177 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_192 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
  wire  _T_200 = _T_192 & _T_49; // @[Parameters.scala 670:56]
  wire  _T_211 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_215 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_223 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_245 = source_ok & _T_200; // @[Monitor.scala 115:71]
  wire  _T_263 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_299 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_300 = io_in_a_bits_mask & _T_299; // @[Monitor.scala 127:31]
  wire  _T_301 = _T_300 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_305 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_334 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_342 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_371 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_379 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_408 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_420 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  _T_424 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_428 = io_in_d_bits_size >= 3'h2; // @[Monitor.scala 312:27]
  wire  _T_444 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_472 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_501 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_518 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_536 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [3:0] a_first_beats1_decode = is_aligned_mask[5:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] a_first_counter; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1 = a_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [28:0] address; // @[Monitor.scala 388:22]
  wire  _T_566 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_567 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_571 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_575 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_579 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_583 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
  wire [3:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [3:0] d_first_counter; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1 = d_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_590 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_591 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_599 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_603 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [11:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [3:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1_1 = a_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  reg [3:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_1 = d_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [11:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _GEN_76 = {{4'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_76 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_617 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_620 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [34:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [34:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_622 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_624 = ~_T_622[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [34:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_628 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_630 = ~_T_424; // @[Monitor.scala 671:74]
  wire  _T_631 = io_in_d_valid & d_first_1 & ~_T_424; // @[Monitor.scala 671:71]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [3:0] _GEN_22 = _d_first_T & d_first_1 & _T_630 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_23 = _d_first_T & d_first_1 & _T_630 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_617 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_641 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_643 = _T_641[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_648 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_649 = io_in_d_bits_opcode == _GEN_32 | _T_648; // @[Monitor.scala 685:77]
  wire  _T_653 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_660 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_661 = io_in_d_bits_opcode == _GEN_48 | _T_660; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_665 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_675 = _T_628 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_630; // @[Monitor.scala 694:116]
  wire  _T_677 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set = _GEN_16[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_22[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_19[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_23[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [11:0] a_sizes_set = _GEN_20[11:0];
  wire [11:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [11:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_686 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [2:0] inflight_1; // @[Monitor.scala 723:35]
  reg [11:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [3:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_2 = d_first_counter_2 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 4'h0; // @[Edges.scala 230:25]
  wire [11:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [15:0] _GEN_87 = {{4'd0}, _c_size_lookup_T_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_87 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_712 = io_in_d_valid & d_first_2 & _T_424; // @[Monitor.scala 779:71]
  wire [3:0] _GEN_67 = _d_first_T & d_first_2 & _T_424 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 783:90 784:21]
  wire [46:0] _GEN_68 = _d_first_T & d_first_2 & _T_424 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 785:21]
  wire [2:0] _T_720 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_730 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [2:0] d_clr_1 = _GEN_67[2:0];
  wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [2:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [11:0] d_opcodes_clr_1 = _GEN_68[11:0];
  wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [11:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_750 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 4'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 4'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 12'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 4'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 4'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 3'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 12'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 4'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_164 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_164) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_200 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_200) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_301 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_301) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_334 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_334) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_371 & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~_T_371) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_408 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_408) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_420 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_420) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_501 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_501 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_518 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_518 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_536 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_536 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_567 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_567) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_571 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_571) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_575 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_575) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_579 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_579) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_583 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_583) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_591 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_591) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_599 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_599) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_603 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_603) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_624 & (_T_620 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_620 & ~reset & ~_T_624) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_643 & (_T_631 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & _T_2 & ~_T_643) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_649 & (_T_631 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & same_cycle_resp & _T_2 & ~_T_649) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_653 & (_T_631 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & same_cycle_resp & _T_2 & ~_T_653) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_661 & (_T_631 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & ~same_cycle_resp & _T_2 & ~_T_661) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_665 & (_T_631 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & ~same_cycle_resp & _T_2 & ~_T_665) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_677 & (_T_675 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_675 & _T_2 & ~_T_677) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_686 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_686) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_720[0] & (_T_712 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_712 & _T_2 & ~_T_720[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_730 & (_T_712 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_712 & _T_2 & ~_T_730) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_750 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_750) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[28:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[2:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[1:0];
  _RAND_10 = {1{`RANDOM}};
  inflight = _RAND_10[2:0];
  _RAND_11 = {1{`RANDOM}};
  inflight_opcodes = _RAND_11[11:0];
  _RAND_12 = {1{`RANDOM}};
  inflight_sizes = _RAND_12[11:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[3:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[3:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  inflight_1 = _RAND_16[2:0];
  _RAND_17 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_17[11:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[3:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLFragmenter_3(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [28:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output [31:0] auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [1:0]  auto_out_a_bits_size,
  output [6:0]  auto_out_a_bits_source,
  output [28:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_size,
  input  [6:0]  auto_out_d_bits_source,
  input  [31:0] auto_out_d_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  repeater_clock; // @[Fragmenter.scala 262:30]
  wire  repeater_reset; // @[Fragmenter.scala 262:30]
  wire  repeater_io_repeat; // @[Fragmenter.scala 262:30]
  wire  repeater_io_full; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
  wire [28:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
  wire [28:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
  reg [3:0] acknum; // @[Fragmenter.scala 189:29]
  reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
  reg  dToggle; // @[Fragmenter.scala 191:30]
  wire [3:0] dFragnum = auto_out_d_bits_source[3:0]; // @[Fragmenter.scala 192:41]
  wire  dFirst = acknum == 4'h0; // @[Fragmenter.scala 193:29]
  wire  dLast = dFragnum == 4'h0; // @[Fragmenter.scala 194:30]
  wire [3:0] _dsizeOH_T = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 64:12]
  wire [2:0] dsizeOH = _dsizeOH_T[2:0]; // @[OneHot.scala 64:27]
  wire [4:0] _dsizeOH1_T_1 = 5'h3 << auto_out_d_bits_size; // @[package.scala 234:77]
  wire [1:0] dsizeOH1 = ~_dsizeOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  dHasData = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  _T_5 = ~reset; // @[Fragmenter.scala 202:16]
  wire  ack_decrement = dHasData | dsizeOH[2]; // @[Fragmenter.scala 204:32]
  wire [5:0] _dFirst_size_T = {dFragnum, 2'h0}; // @[Fragmenter.scala 206:47]
  wire [5:0] _GEN_7 = {{4'd0}, dsizeOH1}; // @[Fragmenter.scala 206:69]
  wire [5:0] _dFirst_size_T_1 = _dFirst_size_T | _GEN_7; // @[Fragmenter.scala 206:69]
  wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala 232:35]
  wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
  wire [6:0] _dFirst_size_T_4 = {1'h0,_dFirst_size_T_1}; // @[Cat.scala 31:58]
  wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
  wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
  wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
  wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
  wire [3:0] _GEN_8 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
  wire [3:0] _dFirst_size_T_8 = _GEN_8 | dFirst_size_lo; // @[OneHot.scala 32:28]
  wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
  wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
  wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
  wire  drop = ~dHasData & ~dLast; // @[Fragmenter.scala 222:30]
  wire  bundleOut_0_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  wire  _T_7 = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
  wire [3:0] _GEN_9 = {{3'd0}, ack_decrement}; // @[Fragmenter.scala 209:55]
  wire [3:0] _acknum_T_1 = acknum - _GEN_9; // @[Fragmenter.scala 209:55]
  wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h2 ? 3'h2 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
  wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
  wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
  wire [8:0] _aFragOH1_T_1 = 9'h3 << aFrag; // @[package.scala 234:77]
  wire [1:0] aFragOH1 = ~_aFragOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  aHasData = ~repeater_io_deq_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] gennum; // @[Fragmenter.scala 291:29]
  wire  aFirst = gennum == 4'h0; // @[Fragmenter.scala 292:29]
  wire [3:0] _old_gennum1_T_2 = gennum - 4'h1; // @[Fragmenter.scala 293:79]
  wire [3:0] old_gennum1 = aFirst ? aOrigOH1[5:2] : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
  wire [3:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
  wire [3:0] new_gennum = ~_new_gennum_T; // @[Fragmenter.scala 294:26]
  reg  aToggle_r; // @[Reg.scala 16:16]
  wire  _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
  wire  aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
  wire  bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  wire  _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
  wire  _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala 302:31]
  wire [5:0] _bundleOut_0_a_bits_address_T = {old_gennum1, 2'h0}; // @[Fragmenter.scala 304:65]
  wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
  wire [5:0] _bundleOut_0_a_bits_address_T_2 = _bundleOut_0_a_bits_address_T | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
  wire [5:0] _GEN_10 = {{4'd0}, aFragOH1}; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_10; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_4 = _bundleOut_0_a_bits_address_T_3 | 6'h3; // @[Fragmenter.scala 304:111]
  wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_4; // @[Fragmenter.scala 304:51]
  wire [28:0] _GEN_11 = {{23'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
  wire [2:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aToggle}; // @[Cat.scala 31:58]
  wire  _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
  TLMonitor_10 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  Repeater repeater ( // @[Fragmenter.scala 262:30]
    .clock(repeater_clock),
    .reset(repeater_reset),
    .io_repeat(repeater_io_repeat),
    .io_full(repeater_io_full),
    .io_enq_ready(repeater_io_enq_ready),
    .io_enq_valid(repeater_io_enq_valid),
    .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
    .io_enq_bits_param(repeater_io_enq_bits_param),
    .io_enq_bits_size(repeater_io_enq_bits_size),
    .io_enq_bits_source(repeater_io_enq_bits_source),
    .io_enq_bits_address(repeater_io_enq_bits_address),
    .io_enq_bits_mask(repeater_io_enq_bits_mask),
    .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
    .io_deq_ready(repeater_io_deq_ready),
    .io_deq_valid(repeater_io_deq_valid),
    .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
    .io_deq_bits_param(repeater_io_deq_bits_param),
    .io_deq_bits_size(repeater_io_deq_bits_size),
    .io_deq_bits_source(repeater_io_deq_bits_source),
    .io_deq_bits_address(repeater_io_deq_bits_address),
    .io_deq_bits_mask(repeater_io_deq_bits_mask),
    .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
  );
  assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign auto_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign auto_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_size = aFrag[1:0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
  assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,new_gennum}; // @[Cat.scala 31:58]
  assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_11; // @[Fragmenter.scala 304:49]
  assign auto_out_a_bits_mask = repeater_io_full ? 4'hf : auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = repeater_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign repeater_clock = clock;
  assign repeater_reset = reset;
  assign repeater_io_repeat = ~aHasData & new_gennum != 4'h0; // @[Fragmenter.scala 302:41]
  assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  always @(posedge clock) begin
    if (reset) begin // @[Fragmenter.scala 189:29]
      acknum <= 4'h0; // @[Fragmenter.scala 189:29]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 209:24]
        acknum <= dFragnum;
      end else begin
        acknum <= _acknum_T_1;
      end
    end
    if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
      end
    end
    if (reset) begin // @[Fragmenter.scala 191:30]
      dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dToggle <= auto_out_d_bits_source[4]; // @[Fragmenter.scala 212:21]
      end
    end
    if (reset) begin // @[Fragmenter.scala 291:29]
      gennum <= 4'h0; // @[Fragmenter.scala 291:29]
    end else if (_T_8) begin // @[Fragmenter.scala 300:29]
      gennum <= new_gennum; // @[Fragmenter.scala 300:38]
    end
    if (aFirst) begin // @[Reg.scala 17:18]
      aToggle_r <= dToggle; // @[Reg.scala 17:22]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~repeater_io_full | _repeater_io_repeat_T) & _T_5) begin
          $fatal; // @[Fragmenter.scala 309:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(~repeater_io_full | _repeater_io_repeat_T)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Fragmenter.scala:309 assert (!repeater.io.full || !aHasData)\n"
            ); // @[Fragmenter.scala 309:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_9 | repeater_io_deq_bits_mask == 4'hf) & _T_5) begin
          $fatal; // @[Fragmenter.scala 312:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask == 4'hf)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
            ); // @[Fragmenter.scala 312:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  acknum = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  dOrig = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  dToggle = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  gennum = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  aToggle_r = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLInterconnectCoupler_7(
  input         clock,
  input         reset,
  input         auto_control_xing_out_a_ready,
  output        auto_control_xing_out_a_valid,
  output [2:0]  auto_control_xing_out_a_bits_opcode,
  output [2:0]  auto_control_xing_out_a_bits_param,
  output [1:0]  auto_control_xing_out_a_bits_size,
  output [6:0]  auto_control_xing_out_a_bits_source,
  output [28:0] auto_control_xing_out_a_bits_address,
  output [3:0]  auto_control_xing_out_a_bits_mask,
  output [31:0] auto_control_xing_out_a_bits_data,
  output        auto_control_xing_out_a_bits_corrupt,
  output        auto_control_xing_out_d_ready,
  input         auto_control_xing_out_d_valid,
  input  [2:0]  auto_control_xing_out_d_bits_opcode,
  input  [1:0]  auto_control_xing_out_d_bits_size,
  input  [6:0]  auto_control_xing_out_d_bits_source,
  input  [31:0] auto_control_xing_out_d_bits_data,
  output        auto_tl_in_a_ready,
  input         auto_tl_in_a_valid,
  input  [2:0]  auto_tl_in_a_bits_opcode,
  input  [2:0]  auto_tl_in_a_bits_param,
  input  [2:0]  auto_tl_in_a_bits_size,
  input  [1:0]  auto_tl_in_a_bits_source,
  input  [28:0] auto_tl_in_a_bits_address,
  input  [3:0]  auto_tl_in_a_bits_mask,
  input  [31:0] auto_tl_in_a_bits_data,
  input         auto_tl_in_a_bits_corrupt,
  input         auto_tl_in_d_ready,
  output        auto_tl_in_d_valid,
  output [2:0]  auto_tl_in_d_bits_opcode,
  output [2:0]  auto_tl_in_d_bits_size,
  output [1:0]  auto_tl_in_d_bits_source,
  output [31:0] auto_tl_in_d_bits_data
);
  wire  fragmenter_clock; // @[Fragmenter.scala 333:34]
  wire  fragmenter_reset; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [28:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [28:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
  TLFragmenter_3 fragmenter ( // @[Fragmenter.scala 333:34]
    .clock(fragmenter_clock),
    .reset(fragmenter_reset),
    .auto_in_a_ready(fragmenter_auto_in_a_ready),
    .auto_in_a_valid(fragmenter_auto_in_a_valid),
    .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
    .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
    .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
    .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
    .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
    .auto_in_a_bits_data(fragmenter_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
    .auto_in_d_ready(fragmenter_auto_in_d_ready),
    .auto_in_d_valid(fragmenter_auto_in_d_valid),
    .auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
    .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
    .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
    .auto_out_a_ready(fragmenter_auto_out_a_ready),
    .auto_out_a_valid(fragmenter_auto_out_a_valid),
    .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
    .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
    .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
    .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
    .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
    .auto_out_a_bits_data(fragmenter_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
    .auto_out_d_ready(fragmenter_auto_out_d_ready),
    .auto_out_d_valid(fragmenter_auto_out_d_valid),
    .auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
    .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
    .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
  );
  assign auto_control_xing_out_a_valid = fragmenter_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_data = fragmenter_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_d_ready = fragmenter_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_in_a_ready = fragmenter_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_valid = fragmenter_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_size = fragmenter_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_source = fragmenter_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_data = fragmenter_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign fragmenter_clock = clock;
  assign fragmenter_reset = reset;
  assign fragmenter_auto_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_data = auto_tl_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_out_a_ready = auto_control_xing_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_valid = auto_control_xing_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_opcode = auto_control_xing_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_size = auto_control_xing_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_source = auto_control_xing_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_data = auto_control_xing_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
endmodule
module TLMonitor_11(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [28:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [2:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
  wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
  wire [28:0] _GEN_71 = {{23'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [28:0] _T_45 = io_in_a_bits_address ^ 29'h10053000; // @[Parameters.scala 137:31]
  wire [29:0] _T_46 = {1'b0,$signed(_T_45)}; // @[Parameters.scala 137:49]
  wire [29:0] _T_48 = $signed(_T_46) & -30'sh1000; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 30'sh0; // @[Parameters.scala 137:67]
  wire  _T_59 = 3'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_60 = _source_ok_T & _T_59; // @[Mux.scala 27:73]
  wire  _T_76 = _T_60 & _T_49; // @[Monitor.scala 83:78]
  wire  _T_90 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_94 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_95 = _T_94 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_99 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_103 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_164 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_177 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_192 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
  wire  _T_200 = _T_192 & _T_49; // @[Parameters.scala 670:56]
  wire  _T_211 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_215 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_223 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_245 = source_ok & _T_200; // @[Monitor.scala 115:71]
  wire  _T_263 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_299 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_300 = io_in_a_bits_mask & _T_299; // @[Monitor.scala 127:31]
  wire  _T_301 = _T_300 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_305 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_334 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_342 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_371 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_379 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_408 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_420 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  _T_424 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_428 = io_in_d_bits_size >= 3'h2; // @[Monitor.scala 312:27]
  wire  _T_444 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_472 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_501 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_518 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_536 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [3:0] a_first_beats1_decode = is_aligned_mask[5:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] a_first_counter; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1 = a_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [28:0] address; // @[Monitor.scala 388:22]
  wire  _T_566 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_567 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_571 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_575 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_579 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_583 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
  wire [3:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [3:0] d_first_counter; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1 = d_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_590 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_591 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_599 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_603 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [11:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [3:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1_1 = a_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  reg [3:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_1 = d_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [11:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _GEN_76 = {{4'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_76 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_617 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_620 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [34:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [34:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_622 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_624 = ~_T_622[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [34:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_628 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_630 = ~_T_424; // @[Monitor.scala 671:74]
  wire  _T_631 = io_in_d_valid & d_first_1 & ~_T_424; // @[Monitor.scala 671:71]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [3:0] _GEN_22 = _d_first_T & d_first_1 & _T_630 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_23 = _d_first_T & d_first_1 & _T_630 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_617 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_641 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_643 = _T_641[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_648 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_649 = io_in_d_bits_opcode == _GEN_32 | _T_648; // @[Monitor.scala 685:77]
  wire  _T_653 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_660 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_661 = io_in_d_bits_opcode == _GEN_48 | _T_660; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_665 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_675 = _T_628 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_630; // @[Monitor.scala 694:116]
  wire  _T_677 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set = _GEN_16[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_22[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_19[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_23[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [11:0] a_sizes_set = _GEN_20[11:0];
  wire [11:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [11:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_686 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [2:0] inflight_1; // @[Monitor.scala 723:35]
  reg [11:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [3:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_2 = d_first_counter_2 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 4'h0; // @[Edges.scala 230:25]
  wire [11:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [15:0] _GEN_87 = {{4'd0}, _c_size_lookup_T_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_87 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_712 = io_in_d_valid & d_first_2 & _T_424; // @[Monitor.scala 779:71]
  wire [3:0] _GEN_67 = _d_first_T & d_first_2 & _T_424 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 783:90 784:21]
  wire [46:0] _GEN_68 = _d_first_T & d_first_2 & _T_424 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 785:21]
  wire [2:0] _T_720 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_730 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [2:0] d_clr_1 = _GEN_67[2:0];
  wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [2:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [11:0] d_opcodes_clr_1 = _GEN_68[11:0];
  wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [11:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_750 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 4'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 4'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 12'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 4'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 4'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 3'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 12'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 4'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_164 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_164) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_200 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_200) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_301 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_301) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_334 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_334) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_371 & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~_T_371) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_408 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_408) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_420 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_420) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_501 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_501 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_518 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_518 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_536 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_536 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_567 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_567) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_571 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_571) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_575 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_575) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_579 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_579) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_583 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_583) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_591 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_591) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_599 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_599) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_603 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_603) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_624 & (_T_620 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_620 & ~reset & ~_T_624) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_643 & (_T_631 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & _T_2 & ~_T_643) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_649 & (_T_631 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & same_cycle_resp & _T_2 & ~_T_649) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_653 & (_T_631 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & same_cycle_resp & _T_2 & ~_T_653) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_661 & (_T_631 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & ~same_cycle_resp & _T_2 & ~_T_661) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_665 & (_T_631 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & ~same_cycle_resp & _T_2 & ~_T_665) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_677 & (_T_675 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_675 & _T_2 & ~_T_677) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_686 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_686) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_720[0] & (_T_712 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_712 & _T_2 & ~_T_720[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_730 & (_T_712 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_712 & _T_2 & ~_T_730) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at UART.scala:268:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_750 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_750) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at UART.scala:268:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[28:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[2:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[1:0];
  _RAND_10 = {1{`RANDOM}};
  inflight = _RAND_10[2:0];
  _RAND_11 = {1{`RANDOM}};
  inflight_opcodes = _RAND_11[11:0];
  _RAND_12 = {1{`RANDOM}};
  inflight_sizes = _RAND_12[11:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[3:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[3:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  inflight_1 = _RAND_16[2:0];
  _RAND_17 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_17[11:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[3:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLFragmenter_4(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [28:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output [31:0] auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [1:0]  auto_out_a_bits_size,
  output [6:0]  auto_out_a_bits_source,
  output [28:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_size,
  input  [6:0]  auto_out_d_bits_source,
  input  [31:0] auto_out_d_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  repeater_clock; // @[Fragmenter.scala 262:30]
  wire  repeater_reset; // @[Fragmenter.scala 262:30]
  wire  repeater_io_repeat; // @[Fragmenter.scala 262:30]
  wire  repeater_io_full; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
  wire [28:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
  wire [28:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
  reg [3:0] acknum; // @[Fragmenter.scala 189:29]
  reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
  reg  dToggle; // @[Fragmenter.scala 191:30]
  wire [3:0] dFragnum = auto_out_d_bits_source[3:0]; // @[Fragmenter.scala 192:41]
  wire  dFirst = acknum == 4'h0; // @[Fragmenter.scala 193:29]
  wire  dLast = dFragnum == 4'h0; // @[Fragmenter.scala 194:30]
  wire [3:0] _dsizeOH_T = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 64:12]
  wire [2:0] dsizeOH = _dsizeOH_T[2:0]; // @[OneHot.scala 64:27]
  wire [4:0] _dsizeOH1_T_1 = 5'h3 << auto_out_d_bits_size; // @[package.scala 234:77]
  wire [1:0] dsizeOH1 = ~_dsizeOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  dHasData = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  _T_5 = ~reset; // @[Fragmenter.scala 202:16]
  wire  ack_decrement = dHasData | dsizeOH[2]; // @[Fragmenter.scala 204:32]
  wire [5:0] _dFirst_size_T = {dFragnum, 2'h0}; // @[Fragmenter.scala 206:47]
  wire [5:0] _GEN_7 = {{4'd0}, dsizeOH1}; // @[Fragmenter.scala 206:69]
  wire [5:0] _dFirst_size_T_1 = _dFirst_size_T | _GEN_7; // @[Fragmenter.scala 206:69]
  wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala 232:35]
  wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
  wire [6:0] _dFirst_size_T_4 = {1'h0,_dFirst_size_T_1}; // @[Cat.scala 31:58]
  wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
  wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
  wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
  wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
  wire [3:0] _GEN_8 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
  wire [3:0] _dFirst_size_T_8 = _GEN_8 | dFirst_size_lo; // @[OneHot.scala 32:28]
  wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
  wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
  wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
  wire  drop = ~dHasData & ~dLast; // @[Fragmenter.scala 222:30]
  wire  bundleOut_0_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  wire  _T_7 = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
  wire [3:0] _GEN_9 = {{3'd0}, ack_decrement}; // @[Fragmenter.scala 209:55]
  wire [3:0] _acknum_T_1 = acknum - _GEN_9; // @[Fragmenter.scala 209:55]
  wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h2 ? 3'h2 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
  wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
  wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
  wire [8:0] _aFragOH1_T_1 = 9'h3 << aFrag; // @[package.scala 234:77]
  wire [1:0] aFragOH1 = ~_aFragOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  aHasData = ~repeater_io_deq_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] gennum; // @[Fragmenter.scala 291:29]
  wire  aFirst = gennum == 4'h0; // @[Fragmenter.scala 292:29]
  wire [3:0] _old_gennum1_T_2 = gennum - 4'h1; // @[Fragmenter.scala 293:79]
  wire [3:0] old_gennum1 = aFirst ? aOrigOH1[5:2] : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
  wire [3:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
  wire [3:0] new_gennum = ~_new_gennum_T; // @[Fragmenter.scala 294:26]
  reg  aToggle_r; // @[Reg.scala 16:16]
  wire  _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
  wire  aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
  wire  bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  wire  _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
  wire  _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala 302:31]
  wire [5:0] _bundleOut_0_a_bits_address_T = {old_gennum1, 2'h0}; // @[Fragmenter.scala 304:65]
  wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
  wire [5:0] _bundleOut_0_a_bits_address_T_2 = _bundleOut_0_a_bits_address_T | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
  wire [5:0] _GEN_10 = {{4'd0}, aFragOH1}; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_10; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_4 = _bundleOut_0_a_bits_address_T_3 | 6'h3; // @[Fragmenter.scala 304:111]
  wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_4; // @[Fragmenter.scala 304:51]
  wire [28:0] _GEN_11 = {{23'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
  wire [2:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aToggle}; // @[Cat.scala 31:58]
  wire  _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
  TLMonitor_11 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  Repeater repeater ( // @[Fragmenter.scala 262:30]
    .clock(repeater_clock),
    .reset(repeater_reset),
    .io_repeat(repeater_io_repeat),
    .io_full(repeater_io_full),
    .io_enq_ready(repeater_io_enq_ready),
    .io_enq_valid(repeater_io_enq_valid),
    .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
    .io_enq_bits_param(repeater_io_enq_bits_param),
    .io_enq_bits_size(repeater_io_enq_bits_size),
    .io_enq_bits_source(repeater_io_enq_bits_source),
    .io_enq_bits_address(repeater_io_enq_bits_address),
    .io_enq_bits_mask(repeater_io_enq_bits_mask),
    .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
    .io_deq_ready(repeater_io_deq_ready),
    .io_deq_valid(repeater_io_deq_valid),
    .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
    .io_deq_bits_param(repeater_io_deq_bits_param),
    .io_deq_bits_size(repeater_io_deq_bits_size),
    .io_deq_bits_source(repeater_io_deq_bits_source),
    .io_deq_bits_address(repeater_io_deq_bits_address),
    .io_deq_bits_mask(repeater_io_deq_bits_mask),
    .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
  );
  assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign auto_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign auto_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_size = aFrag[1:0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
  assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,new_gennum}; // @[Cat.scala 31:58]
  assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_11; // @[Fragmenter.scala 304:49]
  assign auto_out_a_bits_mask = repeater_io_full ? 4'hf : auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = repeater_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign repeater_clock = clock;
  assign repeater_reset = reset;
  assign repeater_io_repeat = ~aHasData & new_gennum != 4'h0; // @[Fragmenter.scala 302:41]
  assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  always @(posedge clock) begin
    if (reset) begin // @[Fragmenter.scala 189:29]
      acknum <= 4'h0; // @[Fragmenter.scala 189:29]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 209:24]
        acknum <= dFragnum;
      end else begin
        acknum <= _acknum_T_1;
      end
    end
    if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
      end
    end
    if (reset) begin // @[Fragmenter.scala 191:30]
      dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dToggle <= auto_out_d_bits_source[4]; // @[Fragmenter.scala 212:21]
      end
    end
    if (reset) begin // @[Fragmenter.scala 291:29]
      gennum <= 4'h0; // @[Fragmenter.scala 291:29]
    end else if (_T_8) begin // @[Fragmenter.scala 300:29]
      gennum <= new_gennum; // @[Fragmenter.scala 300:38]
    end
    if (aFirst) begin // @[Reg.scala 17:18]
      aToggle_r <= dToggle; // @[Reg.scala 17:22]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~repeater_io_full | _repeater_io_repeat_T) & _T_5) begin
          $fatal; // @[Fragmenter.scala 309:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(~repeater_io_full | _repeater_io_repeat_T)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Fragmenter.scala:309 assert (!repeater.io.full || !aHasData)\n"
            ); // @[Fragmenter.scala 309:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_9 | repeater_io_deq_bits_mask == 4'hf) & _T_5) begin
          $fatal; // @[Fragmenter.scala 312:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask == 4'hf)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
            ); // @[Fragmenter.scala 312:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  acknum = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  dOrig = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  dToggle = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  gennum = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  aToggle_r = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLInterconnectCoupler_8(
  input         clock,
  input         reset,
  input         auto_control_xing_out_a_ready,
  output        auto_control_xing_out_a_valid,
  output [2:0]  auto_control_xing_out_a_bits_opcode,
  output [2:0]  auto_control_xing_out_a_bits_param,
  output [1:0]  auto_control_xing_out_a_bits_size,
  output [6:0]  auto_control_xing_out_a_bits_source,
  output [28:0] auto_control_xing_out_a_bits_address,
  output [3:0]  auto_control_xing_out_a_bits_mask,
  output [31:0] auto_control_xing_out_a_bits_data,
  output        auto_control_xing_out_a_bits_corrupt,
  output        auto_control_xing_out_d_ready,
  input         auto_control_xing_out_d_valid,
  input  [2:0]  auto_control_xing_out_d_bits_opcode,
  input  [1:0]  auto_control_xing_out_d_bits_size,
  input  [6:0]  auto_control_xing_out_d_bits_source,
  input  [31:0] auto_control_xing_out_d_bits_data,
  output        auto_tl_in_a_ready,
  input         auto_tl_in_a_valid,
  input  [2:0]  auto_tl_in_a_bits_opcode,
  input  [2:0]  auto_tl_in_a_bits_param,
  input  [2:0]  auto_tl_in_a_bits_size,
  input  [1:0]  auto_tl_in_a_bits_source,
  input  [28:0] auto_tl_in_a_bits_address,
  input  [3:0]  auto_tl_in_a_bits_mask,
  input  [31:0] auto_tl_in_a_bits_data,
  input         auto_tl_in_a_bits_corrupt,
  input         auto_tl_in_d_ready,
  output        auto_tl_in_d_valid,
  output [2:0]  auto_tl_in_d_bits_opcode,
  output [2:0]  auto_tl_in_d_bits_size,
  output [1:0]  auto_tl_in_d_bits_source,
  output [31:0] auto_tl_in_d_bits_data
);
  wire  fragmenter_clock; // @[Fragmenter.scala 333:34]
  wire  fragmenter_reset; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [28:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [28:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
  TLFragmenter_4 fragmenter ( // @[Fragmenter.scala 333:34]
    .clock(fragmenter_clock),
    .reset(fragmenter_reset),
    .auto_in_a_ready(fragmenter_auto_in_a_ready),
    .auto_in_a_valid(fragmenter_auto_in_a_valid),
    .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
    .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
    .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
    .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
    .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
    .auto_in_a_bits_data(fragmenter_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
    .auto_in_d_ready(fragmenter_auto_in_d_ready),
    .auto_in_d_valid(fragmenter_auto_in_d_valid),
    .auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
    .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
    .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
    .auto_out_a_ready(fragmenter_auto_out_a_ready),
    .auto_out_a_valid(fragmenter_auto_out_a_valid),
    .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
    .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
    .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
    .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
    .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
    .auto_out_a_bits_data(fragmenter_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
    .auto_out_d_ready(fragmenter_auto_out_d_ready),
    .auto_out_d_valid(fragmenter_auto_out_d_valid),
    .auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
    .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
    .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
  );
  assign auto_control_xing_out_a_valid = fragmenter_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_data = fragmenter_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_d_ready = fragmenter_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_in_a_ready = fragmenter_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_valid = fragmenter_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_size = fragmenter_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_source = fragmenter_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_data = fragmenter_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign fragmenter_clock = clock;
  assign fragmenter_reset = reset;
  assign fragmenter_auto_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_data = auto_tl_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_out_a_ready = auto_control_xing_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_valid = auto_control_xing_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_opcode = auto_control_xing_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_size = auto_control_xing_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_source = auto_control_xing_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_data = auto_control_xing_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
endmodule
module TLMonitor_12(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [28:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [2:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
  wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
  wire [28:0] _GEN_71 = {{23'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [28:0] _T_45 = io_in_a_bits_address ^ 29'h10014000; // @[Parameters.scala 137:31]
  wire [29:0] _T_46 = {1'b0,$signed(_T_45)}; // @[Parameters.scala 137:49]
  wire [29:0] _T_48 = $signed(_T_46) & -30'sh1000; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 30'sh0; // @[Parameters.scala 137:67]
  wire  _T_59 = 3'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_60 = _source_ok_T & _T_59; // @[Mux.scala 27:73]
  wire  _T_76 = _T_60 & _T_49; // @[Monitor.scala 83:78]
  wire  _T_90 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_94 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_95 = _T_94 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_99 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_103 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_164 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_177 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_192 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
  wire  _T_200 = _T_192 & _T_49; // @[Parameters.scala 670:56]
  wire  _T_211 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_215 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_223 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_245 = source_ok & _T_200; // @[Monitor.scala 115:71]
  wire  _T_263 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_299 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_300 = io_in_a_bits_mask & _T_299; // @[Monitor.scala 127:31]
  wire  _T_301 = _T_300 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_305 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_334 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_342 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_371 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_379 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_408 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_420 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  _T_424 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_428 = io_in_d_bits_size >= 3'h2; // @[Monitor.scala 312:27]
  wire  _T_444 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_472 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_501 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_518 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_536 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [3:0] a_first_beats1_decode = is_aligned_mask[5:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] a_first_counter; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1 = a_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [28:0] address; // @[Monitor.scala 388:22]
  wire  _T_566 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_567 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_571 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_575 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_579 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_583 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
  wire [3:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [3:0] d_first_counter; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1 = d_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_590 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_591 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_599 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_603 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [11:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [3:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1_1 = a_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  reg [3:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_1 = d_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [11:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _GEN_76 = {{4'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_76 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_617 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_620 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [34:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [34:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_622 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_624 = ~_T_622[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [34:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_628 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_630 = ~_T_424; // @[Monitor.scala 671:74]
  wire  _T_631 = io_in_d_valid & d_first_1 & ~_T_424; // @[Monitor.scala 671:71]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [3:0] _GEN_22 = _d_first_T & d_first_1 & _T_630 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_23 = _d_first_T & d_first_1 & _T_630 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_617 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_641 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_643 = _T_641[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_648 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_649 = io_in_d_bits_opcode == _GEN_32 | _T_648; // @[Monitor.scala 685:77]
  wire  _T_653 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_660 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_661 = io_in_d_bits_opcode == _GEN_48 | _T_660; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_665 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_675 = _T_628 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_630; // @[Monitor.scala 694:116]
  wire  _T_677 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set = _GEN_16[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_22[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_19[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_23[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [11:0] a_sizes_set = _GEN_20[11:0];
  wire [11:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [11:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_686 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [2:0] inflight_1; // @[Monitor.scala 723:35]
  reg [11:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [3:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_2 = d_first_counter_2 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 4'h0; // @[Edges.scala 230:25]
  wire [11:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [15:0] _GEN_87 = {{4'd0}, _c_size_lookup_T_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_87 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_712 = io_in_d_valid & d_first_2 & _T_424; // @[Monitor.scala 779:71]
  wire [3:0] _GEN_67 = _d_first_T & d_first_2 & _T_424 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 783:90 784:21]
  wire [46:0] _GEN_68 = _d_first_T & d_first_2 & _T_424 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 785:21]
  wire [2:0] _T_720 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_730 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [2:0] d_clr_1 = _GEN_67[2:0];
  wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [2:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [11:0] d_opcodes_clr_1 = _GEN_68[11:0];
  wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [11:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_750 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 4'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 4'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 12'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 4'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 4'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 3'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 12'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 4'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_164 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_164) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_200 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_200) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_301 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_301) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_334 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_334) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_371 & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~_T_371) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_408 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_408) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_420 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_420) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at SPI.scala:118:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at SPI.scala:118:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at SPI.scala:118:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at SPI.scala:118:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at SPI.scala:118:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at SPI.scala:118:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at SPI.scala:118:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at SPI.scala:118:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at SPI.scala:118:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_501 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_501 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at SPI.scala:118:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_518 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_518 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at SPI.scala:118:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_536 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_536 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at SPI.scala:118:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_567 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_567) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_571 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_571) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_575 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_575) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_579 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_579) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_583 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_583) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_591 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_591) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at SPI.scala:118:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_599 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_599) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at SPI.scala:118:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_603 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_603) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at SPI.scala:118:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_624 & (_T_620 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_620 & ~reset & ~_T_624) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_643 & (_T_631 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & _T_2 & ~_T_643) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SPI.scala:118:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_649 & (_T_631 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & same_cycle_resp & _T_2 & ~_T_649) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at SPI.scala:118:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_653 & (_T_631 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & same_cycle_resp & _T_2 & ~_T_653) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:118:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_661 & (_T_631 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & ~same_cycle_resp & _T_2 & ~_T_661) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at SPI.scala:118:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_665 & (_T_631 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & ~same_cycle_resp & _T_2 & ~_T_665) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:118:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_677 & (_T_675 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_675 & _T_2 & ~_T_677) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_686 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_686) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_720[0] & (_T_712 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_712 & _T_2 & ~_T_720[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SPI.scala:118:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_730 & (_T_712 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_712 & _T_2 & ~_T_730) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:118:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_750 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_750) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at SPI.scala:118:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[28:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[2:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[1:0];
  _RAND_10 = {1{`RANDOM}};
  inflight = _RAND_10[2:0];
  _RAND_11 = {1{`RANDOM}};
  inflight_opcodes = _RAND_11[11:0];
  _RAND_12 = {1{`RANDOM}};
  inflight_sizes = _RAND_12[11:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[3:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[3:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  inflight_1 = _RAND_16[2:0];
  _RAND_17 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_17[11:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[3:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLFragmenter_5(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [28:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output [31:0] auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [1:0]  auto_out_a_bits_size,
  output [6:0]  auto_out_a_bits_source,
  output [28:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_size,
  input  [6:0]  auto_out_d_bits_source,
  input  [31:0] auto_out_d_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  repeater_clock; // @[Fragmenter.scala 262:30]
  wire  repeater_reset; // @[Fragmenter.scala 262:30]
  wire  repeater_io_repeat; // @[Fragmenter.scala 262:30]
  wire  repeater_io_full; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
  wire [28:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
  wire [28:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
  reg [3:0] acknum; // @[Fragmenter.scala 189:29]
  reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
  reg  dToggle; // @[Fragmenter.scala 191:30]
  wire [3:0] dFragnum = auto_out_d_bits_source[3:0]; // @[Fragmenter.scala 192:41]
  wire  dFirst = acknum == 4'h0; // @[Fragmenter.scala 193:29]
  wire  dLast = dFragnum == 4'h0; // @[Fragmenter.scala 194:30]
  wire [3:0] _dsizeOH_T = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 64:12]
  wire [2:0] dsizeOH = _dsizeOH_T[2:0]; // @[OneHot.scala 64:27]
  wire [4:0] _dsizeOH1_T_1 = 5'h3 << auto_out_d_bits_size; // @[package.scala 234:77]
  wire [1:0] dsizeOH1 = ~_dsizeOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  dHasData = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  _T_5 = ~reset; // @[Fragmenter.scala 202:16]
  wire  ack_decrement = dHasData | dsizeOH[2]; // @[Fragmenter.scala 204:32]
  wire [5:0] _dFirst_size_T = {dFragnum, 2'h0}; // @[Fragmenter.scala 206:47]
  wire [5:0] _GEN_7 = {{4'd0}, dsizeOH1}; // @[Fragmenter.scala 206:69]
  wire [5:0] _dFirst_size_T_1 = _dFirst_size_T | _GEN_7; // @[Fragmenter.scala 206:69]
  wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala 232:35]
  wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
  wire [6:0] _dFirst_size_T_4 = {1'h0,_dFirst_size_T_1}; // @[Cat.scala 31:58]
  wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
  wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
  wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
  wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
  wire [3:0] _GEN_8 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
  wire [3:0] _dFirst_size_T_8 = _GEN_8 | dFirst_size_lo; // @[OneHot.scala 32:28]
  wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
  wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
  wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
  wire  drop = ~dHasData & ~dLast; // @[Fragmenter.scala 222:30]
  wire  bundleOut_0_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  wire  _T_7 = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
  wire [3:0] _GEN_9 = {{3'd0}, ack_decrement}; // @[Fragmenter.scala 209:55]
  wire [3:0] _acknum_T_1 = acknum - _GEN_9; // @[Fragmenter.scala 209:55]
  wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h2 ? 3'h2 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
  wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
  wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
  wire [8:0] _aFragOH1_T_1 = 9'h3 << aFrag; // @[package.scala 234:77]
  wire [1:0] aFragOH1 = ~_aFragOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  aHasData = ~repeater_io_deq_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] gennum; // @[Fragmenter.scala 291:29]
  wire  aFirst = gennum == 4'h0; // @[Fragmenter.scala 292:29]
  wire [3:0] _old_gennum1_T_2 = gennum - 4'h1; // @[Fragmenter.scala 293:79]
  wire [3:0] old_gennum1 = aFirst ? aOrigOH1[5:2] : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
  wire [3:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
  wire [3:0] new_gennum = ~_new_gennum_T; // @[Fragmenter.scala 294:26]
  reg  aToggle_r; // @[Reg.scala 16:16]
  wire  _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
  wire  aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
  wire  bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  wire  _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
  wire  _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala 302:31]
  wire [5:0] _bundleOut_0_a_bits_address_T = {old_gennum1, 2'h0}; // @[Fragmenter.scala 304:65]
  wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
  wire [5:0] _bundleOut_0_a_bits_address_T_2 = _bundleOut_0_a_bits_address_T | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
  wire [5:0] _GEN_10 = {{4'd0}, aFragOH1}; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_10; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_4 = _bundleOut_0_a_bits_address_T_3 | 6'h3; // @[Fragmenter.scala 304:111]
  wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_4; // @[Fragmenter.scala 304:51]
  wire [28:0] _GEN_11 = {{23'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
  wire [2:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aToggle}; // @[Cat.scala 31:58]
  wire  _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
  TLMonitor_12 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  Repeater repeater ( // @[Fragmenter.scala 262:30]
    .clock(repeater_clock),
    .reset(repeater_reset),
    .io_repeat(repeater_io_repeat),
    .io_full(repeater_io_full),
    .io_enq_ready(repeater_io_enq_ready),
    .io_enq_valid(repeater_io_enq_valid),
    .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
    .io_enq_bits_param(repeater_io_enq_bits_param),
    .io_enq_bits_size(repeater_io_enq_bits_size),
    .io_enq_bits_source(repeater_io_enq_bits_source),
    .io_enq_bits_address(repeater_io_enq_bits_address),
    .io_enq_bits_mask(repeater_io_enq_bits_mask),
    .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
    .io_deq_ready(repeater_io_deq_ready),
    .io_deq_valid(repeater_io_deq_valid),
    .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
    .io_deq_bits_param(repeater_io_deq_bits_param),
    .io_deq_bits_size(repeater_io_deq_bits_size),
    .io_deq_bits_source(repeater_io_deq_bits_source),
    .io_deq_bits_address(repeater_io_deq_bits_address),
    .io_deq_bits_mask(repeater_io_deq_bits_mask),
    .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
  );
  assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign auto_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign auto_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_size = aFrag[1:0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
  assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,new_gennum}; // @[Cat.scala 31:58]
  assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_11; // @[Fragmenter.scala 304:49]
  assign auto_out_a_bits_mask = repeater_io_full ? 4'hf : auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = repeater_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign repeater_clock = clock;
  assign repeater_reset = reset;
  assign repeater_io_repeat = ~aHasData & new_gennum != 4'h0; // @[Fragmenter.scala 302:41]
  assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  always @(posedge clock) begin
    if (reset) begin // @[Fragmenter.scala 189:29]
      acknum <= 4'h0; // @[Fragmenter.scala 189:29]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 209:24]
        acknum <= dFragnum;
      end else begin
        acknum <= _acknum_T_1;
      end
    end
    if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
      end
    end
    if (reset) begin // @[Fragmenter.scala 191:30]
      dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dToggle <= auto_out_d_bits_source[4]; // @[Fragmenter.scala 212:21]
      end
    end
    if (reset) begin // @[Fragmenter.scala 291:29]
      gennum <= 4'h0; // @[Fragmenter.scala 291:29]
    end else if (_T_8) begin // @[Fragmenter.scala 300:29]
      gennum <= new_gennum; // @[Fragmenter.scala 300:38]
    end
    if (aFirst) begin // @[Reg.scala 17:18]
      aToggle_r <= dToggle; // @[Reg.scala 17:22]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~repeater_io_full | _repeater_io_repeat_T) & _T_5) begin
          $fatal; // @[Fragmenter.scala 309:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(~repeater_io_full | _repeater_io_repeat_T)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Fragmenter.scala:309 assert (!repeater.io.full || !aHasData)\n"
            ); // @[Fragmenter.scala 309:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_9 | repeater_io_deq_bits_mask == 4'hf) & _T_5) begin
          $fatal; // @[Fragmenter.scala 312:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask == 4'hf)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
            ); // @[Fragmenter.scala 312:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  acknum = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  dOrig = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  dToggle = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  gennum = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  aToggle_r = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLInterconnectCoupler_9(
  input         clock,
  input         reset,
  input         auto_control_xing_out_a_ready,
  output        auto_control_xing_out_a_valid,
  output [2:0]  auto_control_xing_out_a_bits_opcode,
  output [2:0]  auto_control_xing_out_a_bits_param,
  output [1:0]  auto_control_xing_out_a_bits_size,
  output [6:0]  auto_control_xing_out_a_bits_source,
  output [28:0] auto_control_xing_out_a_bits_address,
  output [3:0]  auto_control_xing_out_a_bits_mask,
  output [31:0] auto_control_xing_out_a_bits_data,
  output        auto_control_xing_out_a_bits_corrupt,
  output        auto_control_xing_out_d_ready,
  input         auto_control_xing_out_d_valid,
  input  [2:0]  auto_control_xing_out_d_bits_opcode,
  input  [1:0]  auto_control_xing_out_d_bits_size,
  input  [6:0]  auto_control_xing_out_d_bits_source,
  input  [31:0] auto_control_xing_out_d_bits_data,
  output        auto_tl_in_a_ready,
  input         auto_tl_in_a_valid,
  input  [2:0]  auto_tl_in_a_bits_opcode,
  input  [2:0]  auto_tl_in_a_bits_param,
  input  [2:0]  auto_tl_in_a_bits_size,
  input  [1:0]  auto_tl_in_a_bits_source,
  input  [28:0] auto_tl_in_a_bits_address,
  input  [3:0]  auto_tl_in_a_bits_mask,
  input  [31:0] auto_tl_in_a_bits_data,
  input         auto_tl_in_a_bits_corrupt,
  input         auto_tl_in_d_ready,
  output        auto_tl_in_d_valid,
  output [2:0]  auto_tl_in_d_bits_opcode,
  output [2:0]  auto_tl_in_d_bits_size,
  output [1:0]  auto_tl_in_d_bits_source,
  output [31:0] auto_tl_in_d_bits_data
);
  wire  fragmenter_clock; // @[Fragmenter.scala 333:34]
  wire  fragmenter_reset; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [28:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [28:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
  TLFragmenter_5 fragmenter ( // @[Fragmenter.scala 333:34]
    .clock(fragmenter_clock),
    .reset(fragmenter_reset),
    .auto_in_a_ready(fragmenter_auto_in_a_ready),
    .auto_in_a_valid(fragmenter_auto_in_a_valid),
    .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
    .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
    .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
    .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
    .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
    .auto_in_a_bits_data(fragmenter_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
    .auto_in_d_ready(fragmenter_auto_in_d_ready),
    .auto_in_d_valid(fragmenter_auto_in_d_valid),
    .auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
    .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
    .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
    .auto_out_a_ready(fragmenter_auto_out_a_ready),
    .auto_out_a_valid(fragmenter_auto_out_a_valid),
    .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
    .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
    .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
    .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
    .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
    .auto_out_a_bits_data(fragmenter_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
    .auto_out_d_ready(fragmenter_auto_out_d_ready),
    .auto_out_d_valid(fragmenter_auto_out_d_valid),
    .auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
    .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
    .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
  );
  assign auto_control_xing_out_a_valid = fragmenter_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_data = fragmenter_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_d_ready = fragmenter_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_in_a_ready = fragmenter_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_valid = fragmenter_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_size = fragmenter_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_source = fragmenter_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_data = fragmenter_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign fragmenter_clock = clock;
  assign fragmenter_reset = reset;
  assign fragmenter_auto_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_data = auto_tl_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_out_a_ready = auto_control_xing_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_valid = auto_control_xing_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_opcode = auto_control_xing_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_size = auto_control_xing_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_source = auto_control_xing_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_data = auto_control_xing_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
endmodule
module TLMonitor_13(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [29:0] io_in_a_bits_address,
  input         io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
  wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
  wire [29:0] _GEN_71 = {{24'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [29:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 30'h0; // @[Edges.scala 20:24]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [29:0] _T_45 = io_in_a_bits_address ^ 30'h20000000; // @[Parameters.scala 137:31]
  wire [30:0] _T_46 = {1'b0,$signed(_T_45)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_48 = $signed(_T_46) & -31'sh20000000; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 31'sh0; // @[Parameters.scala 137:67]
  wire  _T_59 = 3'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_60 = _source_ok_T & _T_59; // @[Mux.scala 27:73]
  wire  _T_76 = _T_60 & _T_49; // @[Monitor.scala 83:78]
  wire  _T_90 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire  _T_94 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_95 = ~(~io_in_a_bits_mask); // @[Monitor.scala 88:31]
  wire  _T_99 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_103 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_164 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_177 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_192 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
  wire  _T_200 = _T_192 & _T_49; // @[Parameters.scala 670:56]
  wire  _T_211 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_223 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_260 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire  _T_299 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_328 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_336 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_365 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_373 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_402 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  reg [5:0] a_first_counter; // @[Edges.scala 228:27]
  wire [5:0] a_first_counter1 = a_first_counter - 6'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 6'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [29:0] address; // @[Monitor.scala 388:22]
  wire  _T_560 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_561 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_565 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_569 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_573 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_577 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
  wire [5:0] d_first_beats1_decode = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
  reg [5:0] d_first_counter; // @[Edges.scala 228:27]
  wire [5:0] d_first_counter1 = d_first_counter - 6'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 6'h0; // @[Edges.scala 230:25]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_584 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_593 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_597 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [11:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [5:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [5:0] a_first_counter1_1 = a_first_counter_1 - 6'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 6'h0; // @[Edges.scala 230:25]
  reg [5:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [5:0] d_first_counter1_1 = d_first_counter_1 - 6'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 6'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [11:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _GEN_76 = {{4'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_76 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_611 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_614 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [34:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [34:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_616 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_618 = ~_T_616[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [34:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_622 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [3:0] _GEN_22 = _d_first_T & d_first_1 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_23 = _d_first_T & d_first_1 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_611 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_635 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_637 = _T_635[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_642 = 3'h1 == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_643 = 3'h1 == _GEN_32 | _T_642; // @[Monitor.scala 685:77]
  wire  _T_647 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_654 = 3'h1 == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_655 = 3'h1 == _GEN_48 | _T_654; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_659 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_667 = _T_622 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2; // @[Monitor.scala 694:65]
  wire  _T_671 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set = _GEN_16[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_22[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_19[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_23[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [11:0] a_sizes_set = _GEN_20[11:0];
  wire [11:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [11:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_680 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 6'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 6'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 6'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= d_first_beats1_decode;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 12'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 6'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 6'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 6'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= d_first_beats1_decode;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (a_first_done | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_164 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_164) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_200 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_200) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_94 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & _T_94) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_94 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & _T_94) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_260 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_260 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_260 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_260 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_260 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_260 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_260 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_260 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_299 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_299 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_299 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_299 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_299 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_299 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_328 & (io_in_a_valid & _T_299 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_299 & ~reset & ~_T_328) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_94 & (io_in_a_valid & _T_299 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_299 & ~reset & _T_94) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_336 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_336 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_336 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_336 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_336 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_336 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_365 & (io_in_a_valid & _T_336 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_336 & ~reset & ~_T_365) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_94 & (io_in_a_valid & _T_336 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_336 & ~reset & _T_94) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_373 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_373 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_373 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_373 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_373 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_373 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_402 & (io_in_a_valid & _T_373 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_373 & ~reset & ~_T_402) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_94 & (io_in_a_valid & _T_373 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_373 & ~reset & _T_94) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_373 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_373 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at SPI.scala:131:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_561 & (_T_560 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_560 & ~reset & ~_T_561) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_565 & (_T_560 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_560 & ~reset & ~_T_565) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_569 & (_T_560 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_560 & ~reset & ~_T_569) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_573 & (_T_560 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_560 & ~reset & ~_T_573) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_577 & (_T_560 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_560 & ~reset & ~_T_577) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_593 & (_T_584 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_584 & _T_2 & ~_T_593) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at SPI.scala:131:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_597 & (_T_584 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_584 & _T_2 & ~_T_597) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at SPI.scala:131:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_618 & (_T_614 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_614 & ~reset & ~_T_618) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_637 & (_T_622 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_622 & _T_2 & ~_T_637) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SPI.scala:131:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_643 & (_T_622 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_622 & same_cycle_resp & _T_2 & ~_T_643) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at SPI.scala:131:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_647 & (_T_622 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_622 & same_cycle_resp & _T_2 & ~_T_647) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:131:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_655 & (_T_622 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_622 & ~same_cycle_resp & _T_2 & ~_T_655) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at SPI.scala:131:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_659 & (_T_622 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_622 & ~same_cycle_resp & _T_2 & ~_T_659) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:131:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_671 & (_T_667 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_667 & _T_2 & ~_T_671) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_680 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_680) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at SPI.scala:131:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[5:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[29:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[5:0];
  _RAND_7 = {1{`RANDOM}};
  size_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  source_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  inflight = _RAND_9[2:0];
  _RAND_10 = {1{`RANDOM}};
  inflight_opcodes = _RAND_10[11:0];
  _RAND_11 = {1{`RANDOM}};
  inflight_sizes = _RAND_11[11:0];
  _RAND_12 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_12[5:0];
  _RAND_13 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_13[5:0];
  _RAND_14 = {1{`RANDOM}};
  watchdog = _RAND_14[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Repeater_6(
  input         clock,
  input         reset,
  input         io_repeat,
  output        io_full,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [2:0]  io_enq_bits_opcode,
  input  [2:0]  io_enq_bits_param,
  input  [2:0]  io_enq_bits_size,
  input  [1:0]  io_enq_bits_source,
  input  [29:0] io_enq_bits_address,
  input         io_enq_bits_mask,
  input         io_enq_bits_corrupt,
  input         io_deq_ready,
  output        io_deq_valid,
  output [2:0]  io_deq_bits_opcode,
  output [2:0]  io_deq_bits_param,
  output [2:0]  io_deq_bits_size,
  output [1:0]  io_deq_bits_source,
  output [29:0] io_deq_bits_address,
  output        io_deq_bits_mask,
  output        io_deq_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
`endif // RANDOMIZE_REG_INIT
  reg  full; // @[Repeater.scala 19:21]
  reg [2:0] saved_opcode; // @[Repeater.scala 20:18]
  reg [2:0] saved_param; // @[Repeater.scala 20:18]
  reg [2:0] saved_size; // @[Repeater.scala 20:18]
  reg [1:0] saved_source; // @[Repeater.scala 20:18]
  reg [29:0] saved_address; // @[Repeater.scala 20:18]
  reg  saved_mask; // @[Repeater.scala 20:18]
  reg  saved_corrupt; // @[Repeater.scala 20:18]
  wire  _T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
  wire  _GEN_0 = _T & io_repeat | full; // @[Repeater.scala 19:21 28:{38,45}]
  wire  _T_2 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
  assign io_full = full; // @[Repeater.scala 26:11]
  assign io_enq_ready = io_deq_ready & ~full; // @[Repeater.scala 24:32]
  assign io_deq_valid = io_enq_valid | full; // @[Repeater.scala 23:32]
  assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode; // @[Repeater.scala 25:21]
  assign io_deq_bits_param = full ? saved_param : io_enq_bits_param; // @[Repeater.scala 25:21]
  assign io_deq_bits_size = full ? saved_size : io_enq_bits_size; // @[Repeater.scala 25:21]
  assign io_deq_bits_source = full ? saved_source : io_enq_bits_source; // @[Repeater.scala 25:21]
  assign io_deq_bits_address = full ? saved_address : io_enq_bits_address; // @[Repeater.scala 25:21]
  assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask; // @[Repeater.scala 25:21]
  assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt; // @[Repeater.scala 25:21]
  always @(posedge clock) begin
    if (reset) begin // @[Repeater.scala 19:21]
      full <= 1'h0; // @[Repeater.scala 19:21]
    end else if (_T_2 & ~io_repeat) begin // @[Repeater.scala 29:38]
      full <= 1'h0; // @[Repeater.scala 29:45]
    end else begin
      full <= _GEN_0;
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_opcode <= io_enq_bits_opcode; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_param <= io_enq_bits_param; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_size <= io_enq_bits_size; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_source <= io_enq_bits_source; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_address <= io_enq_bits_address; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_mask <= io_enq_bits_mask; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_corrupt <= io_enq_bits_corrupt; // @[Repeater.scala 28:62]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  full = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  saved_opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  saved_param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  saved_size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  saved_source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  saved_address = _RAND_5[29:0];
  _RAND_6 = {1{`RANDOM}};
  saved_mask = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  saved_corrupt = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLFragmenter_6(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [29:0] auto_in_a_bits_address,
  input         auto_in_a_bits_mask,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output [7:0]  auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output        auto_out_a_bits_size,
  output [8:0]  auto_out_a_bits_source,
  output [29:0] auto_out_a_bits_address,
  output        auto_out_a_bits_mask,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input         auto_out_d_bits_size,
  input  [8:0]  auto_out_d_bits_source,
  input  [7:0]  auto_out_d_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [29:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  repeater_clock; // @[Fragmenter.scala 262:30]
  wire  repeater_reset; // @[Fragmenter.scala 262:30]
  wire  repeater_io_repeat; // @[Fragmenter.scala 262:30]
  wire  repeater_io_full; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
  wire [29:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
  wire [29:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
  reg [5:0] acknum; // @[Fragmenter.scala 189:29]
  reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
  reg  dToggle; // @[Fragmenter.scala 191:30]
  wire [5:0] dFragnum = auto_out_d_bits_source[5:0]; // @[Fragmenter.scala 192:41]
  wire  dFirst = acknum == 6'h0; // @[Fragmenter.scala 193:29]
  wire [1:0] _dsizeOH1_T_1 = 2'h1 << auto_out_d_bits_size; // @[package.scala 234:77]
  wire  dsizeOH1 = ~_dsizeOH1_T_1[0]; // @[package.scala 234:46]
  wire [5:0] _GEN_7 = {{5'd0}, dsizeOH1}; // @[Fragmenter.scala 202:50]
  wire [5:0] _T_1 = dFragnum & _GEN_7; // @[Fragmenter.scala 202:50]
  wire  _T_5 = ~reset; // @[Fragmenter.scala 202:16]
  wire [5:0] dFirst_acknum = dFragnum | _GEN_7; // @[Fragmenter.scala 203:45]
  wire [6:0] _dFirst_size_T_2 = {dFirst_acknum, 1'h0}; // @[package.scala 232:35]
  wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
  wire [6:0] _dFirst_size_T_4 = {1'h0,dFirst_acknum}; // @[Cat.scala 31:58]
  wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
  wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
  wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
  wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
  wire [3:0] _GEN_10 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
  wire [3:0] _dFirst_size_T_8 = _GEN_10 | dFirst_size_lo; // @[OneHot.scala 32:28]
  wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
  wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
  wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
  wire  _T_7 = auto_in_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
  wire [5:0] _acknum_T_1 = acknum - 6'h1; // @[Fragmenter.scala 209:55]
  wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h0 ? 3'h0 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
  wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
  wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
  wire [7:0] _aFragOH1_T_1 = 8'h1 << aFrag; // @[package.scala 234:77]
  wire  aFragOH1 = ~_aFragOH1_T_1[0]; // @[package.scala 234:46]
  reg [5:0] gennum; // @[Fragmenter.scala 291:29]
  wire  aFirst = gennum == 6'h0; // @[Fragmenter.scala 292:29]
  wire [5:0] _old_gennum1_T_2 = gennum - 6'h1; // @[Fragmenter.scala 293:79]
  wire [5:0] old_gennum1 = aFirst ? aOrigOH1 : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
  wire [5:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
  wire [5:0] _GEN_11 = {{5'd0}, aFragOH1}; // @[Fragmenter.scala 294:41]
  wire [5:0] _new_gennum_T_2 = _new_gennum_T | _GEN_11; // @[Fragmenter.scala 294:41]
  wire [5:0] new_gennum = ~_new_gennum_T_2; // @[Fragmenter.scala 294:26]
  reg  aToggle_r; // @[Reg.scala 16:16]
  wire  _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
  wire  aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
  wire  bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  wire  _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
  wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
  wire [5:0] _bundleOut_0_a_bits_address_T_2 = old_gennum1 | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
  wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_11; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_3; // @[Fragmenter.scala 304:51]
  wire [29:0] _GEN_14 = {{24'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
  wire [2:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aToggle}; // @[Cat.scala 31:58]
  wire  _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
  TLMonitor_13 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  Repeater_6 repeater ( // @[Fragmenter.scala 262:30]
    .clock(repeater_clock),
    .reset(repeater_reset),
    .io_repeat(repeater_io_repeat),
    .io_full(repeater_io_full),
    .io_enq_ready(repeater_io_enq_ready),
    .io_enq_valid(repeater_io_enq_valid),
    .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
    .io_enq_bits_param(repeater_io_enq_bits_param),
    .io_enq_bits_size(repeater_io_enq_bits_size),
    .io_enq_bits_source(repeater_io_enq_bits_source),
    .io_enq_bits_address(repeater_io_enq_bits_address),
    .io_enq_bits_mask(repeater_io_enq_bits_mask),
    .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
    .io_deq_ready(repeater_io_deq_ready),
    .io_deq_valid(repeater_io_deq_valid),
    .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
    .io_deq_bits_param(repeater_io_deq_bits_param),
    .io_deq_bits_size(repeater_io_deq_bits_size),
    .io_deq_bits_source(repeater_io_deq_bits_source),
    .io_deq_bits_address(repeater_io_deq_bits_address),
    .io_deq_bits_mask(repeater_io_deq_bits_mask),
    .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
  );
  assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign auto_in_d_valid = auto_out_d_valid; // @[Fragmenter.scala 224:36]
  assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign auto_in_d_bits_source = auto_out_d_bits_source[8:7]; // @[Fragmenter.scala 226:47]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_size = aFrag[0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
  assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,new_gennum}; // @[Cat.scala 31:58]
  assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_14; // @[Fragmenter.scala 304:49]
  assign auto_out_a_bits_mask = repeater_io_full | auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
  assign auto_out_a_bits_corrupt = repeater_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_d_ready = auto_in_d_ready; // @[Fragmenter.scala 223:35]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid; // @[Fragmenter.scala 224:36]
  assign monitor_io_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source[8:7]; // @[Fragmenter.scala 226:47]
  assign repeater_clock = clock;
  assign repeater_reset = reset;
  assign repeater_io_repeat = new_gennum != 6'h0; // @[Fragmenter.scala 302:53]
  assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  always @(posedge clock) begin
    if (reset) begin // @[Fragmenter.scala 189:29]
      acknum <= 6'h0; // @[Fragmenter.scala 189:29]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 209:24]
        acknum <= dFirst_acknum;
      end else begin
        acknum <= _acknum_T_1;
      end
    end
    if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
      end
    end
    if (reset) begin // @[Fragmenter.scala 191:30]
      dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dToggle <= auto_out_d_bits_source[6]; // @[Fragmenter.scala 212:21]
      end
    end
    if (reset) begin // @[Fragmenter.scala 291:29]
      gennum <= 6'h0; // @[Fragmenter.scala 291:29]
    end else if (_T_8) begin // @[Fragmenter.scala 300:29]
      gennum <= new_gennum; // @[Fragmenter.scala 300:38]
    end
    if (aFirst) begin // @[Reg.scala 17:18]
      aToggle_r <= dToggle; // @[Reg.scala 17:22]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~auto_out_d_valid | _T_1 == 6'h0) & ~reset) begin
          $fatal; // @[Fragmenter.scala 202:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~auto_out_d_valid | _T_1 == 6'h0)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Fragmenter.scala:202 assert (!out.d.valid || (acknum_fragment & acknum_size) === UInt(0))\n"
            ); // @[Fragmenter.scala 202:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_9 | repeater_io_deq_bits_mask) & _T_5) begin
          $fatal; // @[Fragmenter.scala 312:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
            ); // @[Fragmenter.scala 312:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  acknum = _RAND_0[5:0];
  _RAND_1 = {1{`RANDOM}};
  dOrig = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  dToggle = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  gennum = _RAND_3[5:0];
  _RAND_4 = {1{`RANDOM}};
  aToggle_r = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLMonitor_14(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [29:0] io_in_a_bits_address,
  input         io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
  wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
  wire [29:0] _GEN_71 = {{24'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [29:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 30'h0; // @[Edges.scala 20:24]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [29:0] _T_45 = io_in_a_bits_address ^ 30'h20000000; // @[Parameters.scala 137:31]
  wire [30:0] _T_46 = {1'b0,$signed(_T_45)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_48 = $signed(_T_46) & -31'sh20000000; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 31'sh0; // @[Parameters.scala 137:67]
  wire  _T_59 = 3'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_60 = _source_ok_T & _T_59; // @[Mux.scala 27:73]
  wire  _T_76 = _T_60 & _T_49; // @[Monitor.scala 83:78]
  wire  _T_90 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire  _T_94 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_95 = ~(~io_in_a_bits_mask); // @[Monitor.scala 88:31]
  wire  _T_99 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_103 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_164 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_177 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_192 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
  wire  _T_200 = _T_192 & _T_49; // @[Parameters.scala 670:56]
  wire  _T_211 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_223 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_260 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire  _T_299 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_328 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_336 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_365 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_373 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_402 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  reg [5:0] a_first_counter; // @[Edges.scala 228:27]
  wire [5:0] a_first_counter1 = a_first_counter - 6'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 6'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [29:0] address; // @[Monitor.scala 388:22]
  wire  _T_560 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_561 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_565 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_569 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_573 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_577 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
  wire [5:0] d_first_beats1_decode = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
  reg [5:0] d_first_counter; // @[Edges.scala 228:27]
  wire [5:0] d_first_counter1 = d_first_counter - 6'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 6'h0; // @[Edges.scala 230:25]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_584 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_593 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_597 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [11:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [5:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [5:0] a_first_counter1_1 = a_first_counter_1 - 6'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 6'h0; // @[Edges.scala 230:25]
  reg [5:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [5:0] d_first_counter1_1 = d_first_counter_1 - 6'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 6'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [11:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _GEN_76 = {{4'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_76 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_611 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_614 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [34:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [34:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_616 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_618 = ~_T_616[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [34:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_622 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _GEN_21 = io_in_d_valid & d_first_1 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 671:90 672:22]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [3:0] _GEN_22 = _d_first_T & d_first_1 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_23 = _d_first_T & d_first_1 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_611 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_635 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_637 = _T_635[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_642 = 3'h1 == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_643 = 3'h1 == _GEN_32 | _T_642; // @[Monitor.scala 685:77]
  wire  _T_647 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_654 = 3'h1 == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_655 = 3'h1 == _GEN_48 | _T_654; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_659 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_667 = _T_622 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2; // @[Monitor.scala 694:65]
  wire  _T_671 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set_wo_ready = _GEN_15[2:0];
  wire [2:0] d_clr_wo_ready = _GEN_21[2:0];
  wire  _T_678 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire [2:0] a_set = _GEN_16[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_22[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_19[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_23[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [11:0] a_sizes_set = _GEN_20[11:0];
  wire [11:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [11:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_687 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 6'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 6'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 6'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= d_first_beats1_decode;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 12'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 6'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 6'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 6'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= d_first_beats1_decode;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (a_first_done | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_164 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_164) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_200 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_200) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_94 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & _T_94) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_94 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & _T_94) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_260 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_260 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_260 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_260 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_260 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_260 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_260 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_260 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_299 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_299 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_299 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_299 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_299 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_299 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_328 & (io_in_a_valid & _T_299 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_299 & ~reset & ~_T_328) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_94 & (io_in_a_valid & _T_299 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_299 & ~reset & _T_94) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_336 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_336 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_336 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_336 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_336 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_336 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_365 & (io_in_a_valid & _T_336 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_336 & ~reset & ~_T_365) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_94 & (io_in_a_valid & _T_336 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_336 & ~reset & _T_94) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_373 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_373 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_373 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_373 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_373 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_373 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_402 & (io_in_a_valid & _T_373 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_373 & ~reset & ~_T_402) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_94 & (io_in_a_valid & _T_373 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_373 & ~reset & _T_94) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_373 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_373 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at SPI.scala:132:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_561 & (_T_560 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_560 & ~reset & ~_T_561) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_565 & (_T_560 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_560 & ~reset & ~_T_565) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_569 & (_T_560 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_560 & ~reset & ~_T_569) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_573 & (_T_560 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_560 & ~reset & ~_T_573) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_577 & (_T_560 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_560 & ~reset & ~_T_577) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_593 & (_T_584 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_584 & _T_2 & ~_T_593) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at SPI.scala:132:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_597 & (_T_584 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_584 & _T_2 & ~_T_597) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at SPI.scala:132:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_618 & (_T_614 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_614 & ~reset & ~_T_618) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_637 & (_T_622 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_622 & _T_2 & ~_T_637) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SPI.scala:132:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_643 & (_T_622 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_622 & same_cycle_resp & _T_2 & ~_T_643) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at SPI.scala:132:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_647 & (_T_622 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_622 & same_cycle_resp & _T_2 & ~_T_647) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:132:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_655 & (_T_622 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_622 & ~same_cycle_resp & _T_2 & ~_T_655) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at SPI.scala:132:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_659 & (_T_622 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_622 & ~same_cycle_resp & _T_2 & ~_T_659) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:132:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_671 & (_T_667 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_667 & _T_2 & ~_T_671) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_678 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_678) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at SPI.scala:132:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_687 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_687) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at SPI.scala:132:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[5:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[29:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[5:0];
  _RAND_7 = {1{`RANDOM}};
  size_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  source_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  inflight = _RAND_9[2:0];
  _RAND_10 = {1{`RANDOM}};
  inflight_opcodes = _RAND_10[11:0];
  _RAND_11 = {1{`RANDOM}};
  inflight_sizes = _RAND_11[11:0];
  _RAND_12 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_12[5:0];
  _RAND_13 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_13[5:0];
  _RAND_14 = {1{`RANDOM}};
  watchdog = _RAND_14[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_4(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [2:0]  io_enq_bits_opcode,
  input  [2:0]  io_enq_bits_param,
  input  [2:0]  io_enq_bits_size,
  input  [1:0]  io_enq_bits_source,
  input  [29:0] io_enq_bits_address,
  input         io_enq_bits_mask,
  input         io_enq_bits_corrupt,
  input         io_deq_ready,
  output        io_deq_valid,
  output [2:0]  io_deq_bits_opcode,
  output [2:0]  io_deq_bits_param,
  output [2:0]  io_deq_bits_size,
  output [1:0]  io_deq_bits_source,
  output [29:0] io_deq_bits_address,
  output        io_deq_bits_mask,
  output        io_deq_bits_corrupt
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
`endif // RANDOMIZE_REG_INIT
  reg [2:0] ram_opcode [0:7]; // @[Decoupled.scala 259:95]
  wire  ram_opcode_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire [2:0] ram_opcode_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [2:0] ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_opcode_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_en; // @[Decoupled.scala 259:95]
  reg [2:0] ram_param [0:7]; // @[Decoupled.scala 259:95]
  wire  ram_param_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire [2:0] ram_param_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [2:0] ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_param_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_param_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_param_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_param_MPORT_en; // @[Decoupled.scala 259:95]
  reg [2:0] ram_size [0:7]; // @[Decoupled.scala 259:95]
  wire  ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire [2:0] ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [2:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_size_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_size_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_en; // @[Decoupled.scala 259:95]
  reg [1:0] ram_source [0:7]; // @[Decoupled.scala 259:95]
  wire  ram_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire [2:0] ram_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [1:0] ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [1:0] ram_source_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_source_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_en; // @[Decoupled.scala 259:95]
  reg [29:0] ram_address [0:7]; // @[Decoupled.scala 259:95]
  wire  ram_address_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire [2:0] ram_address_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [29:0] ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [29:0] ram_address_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_address_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_address_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_address_MPORT_en; // @[Decoupled.scala 259:95]
  reg  ram_mask [0:7]; // @[Decoupled.scala 259:95]
  wire  ram_mask_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire [2:0] ram_mask_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_mask_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_mask_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_mask_MPORT_en; // @[Decoupled.scala 259:95]
  reg  ram_corrupt [0:7]; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire [2:0] ram_corrupt_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_corrupt_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_en; // @[Decoupled.scala 259:95]
  reg [2:0] value; // @[Counter.scala 62:40]
  reg [2:0] value_1; // @[Counter.scala 62:40]
  reg  maybe_full; // @[Decoupled.scala 262:27]
  wire  ptr_match = value == value_1; // @[Decoupled.scala 263:33]
  wire  empty = ptr_match & ~maybe_full; // @[Decoupled.scala 264:25]
  wire  full = ptr_match & maybe_full; // @[Decoupled.scala 265:24]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
  wire  do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
  wire [2:0] _value_T_1 = value + 3'h1; // @[Counter.scala 78:24]
  wire [2:0] _value_T_3 = value_1 + 3'h1; // @[Counter.scala 78:24]
  assign ram_opcode_io_deq_bits_MPORT_en = 1'h1;
  assign ram_opcode_io_deq_bits_MPORT_addr = value_1;
  assign ram_opcode_io_deq_bits_MPORT_data = ram_opcode[ram_opcode_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_opcode_MPORT_data = io_enq_bits_opcode;
  assign ram_opcode_MPORT_addr = value;
  assign ram_opcode_MPORT_mask = 1'h1;
  assign ram_opcode_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_param_io_deq_bits_MPORT_en = 1'h1;
  assign ram_param_io_deq_bits_MPORT_addr = value_1;
  assign ram_param_io_deq_bits_MPORT_data = ram_param[ram_param_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_param_MPORT_data = io_enq_bits_param;
  assign ram_param_MPORT_addr = value;
  assign ram_param_MPORT_mask = 1'h1;
  assign ram_param_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_size_io_deq_bits_MPORT_en = 1'h1;
  assign ram_size_io_deq_bits_MPORT_addr = value_1;
  assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_size_MPORT_data = io_enq_bits_size;
  assign ram_size_MPORT_addr = value;
  assign ram_size_MPORT_mask = 1'h1;
  assign ram_size_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_source_io_deq_bits_MPORT_en = 1'h1;
  assign ram_source_io_deq_bits_MPORT_addr = value_1;
  assign ram_source_io_deq_bits_MPORT_data = ram_source[ram_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_source_MPORT_data = io_enq_bits_source;
  assign ram_source_MPORT_addr = value;
  assign ram_source_MPORT_mask = 1'h1;
  assign ram_source_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_address_io_deq_bits_MPORT_en = 1'h1;
  assign ram_address_io_deq_bits_MPORT_addr = value_1;
  assign ram_address_io_deq_bits_MPORT_data = ram_address[ram_address_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_address_MPORT_data = io_enq_bits_address;
  assign ram_address_MPORT_addr = value;
  assign ram_address_MPORT_mask = 1'h1;
  assign ram_address_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_mask_io_deq_bits_MPORT_en = 1'h1;
  assign ram_mask_io_deq_bits_MPORT_addr = value_1;
  assign ram_mask_io_deq_bits_MPORT_data = ram_mask[ram_mask_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_mask_MPORT_data = io_enq_bits_mask;
  assign ram_mask_MPORT_addr = value;
  assign ram_mask_MPORT_mask = 1'h1;
  assign ram_mask_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_corrupt_io_deq_bits_MPORT_en = 1'h1;
  assign ram_corrupt_io_deq_bits_MPORT_addr = value_1;
  assign ram_corrupt_io_deq_bits_MPORT_data = ram_corrupt[ram_corrupt_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_corrupt_MPORT_data = io_enq_bits_corrupt;
  assign ram_corrupt_MPORT_addr = value;
  assign ram_corrupt_MPORT_mask = 1'h1;
  assign ram_corrupt_MPORT_en = io_enq_ready & io_enq_valid;
  assign io_enq_ready = ~full; // @[Decoupled.scala 289:19]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 288:19]
  assign io_deq_bits_opcode = ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_param = ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_size = ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_source = ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_address = ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_mask = ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_corrupt = ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  always @(posedge clock) begin
    if (ram_opcode_MPORT_en & ram_opcode_MPORT_mask) begin
      ram_opcode[ram_opcode_MPORT_addr] <= ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_param_MPORT_en & ram_param_MPORT_mask) begin
      ram_param[ram_param_MPORT_addr] <= ram_param_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
      ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_source_MPORT_en & ram_source_MPORT_mask) begin
      ram_source[ram_source_MPORT_addr] <= ram_source_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_address_MPORT_en & ram_address_MPORT_mask) begin
      ram_address[ram_address_MPORT_addr] <= ram_address_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_mask_MPORT_en & ram_mask_MPORT_mask) begin
      ram_mask[ram_mask_MPORT_addr] <= ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_corrupt_MPORT_en & ram_corrupt_MPORT_mask) begin
      ram_corrupt[ram_corrupt_MPORT_addr] <= ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (reset) begin // @[Counter.scala 62:40]
      value <= 3'h0; // @[Counter.scala 62:40]
    end else if (do_enq) begin // @[Decoupled.scala 272:16]
      value <= _value_T_1; // @[Counter.scala 78:15]
    end
    if (reset) begin // @[Counter.scala 62:40]
      value_1 <= 3'h0; // @[Counter.scala 62:40]
    end else if (do_deq) begin // @[Decoupled.scala 276:16]
      value_1 <= _value_T_3; // @[Counter.scala 78:15]
    end
    if (reset) begin // @[Decoupled.scala 262:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 262:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 279:27]
      maybe_full <= do_enq; // @[Decoupled.scala 280:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 8; initvar = initvar+1)
    ram_opcode[initvar] = _RAND_0[2:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 8; initvar = initvar+1)
    ram_param[initvar] = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 8; initvar = initvar+1)
    ram_size[initvar] = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 8; initvar = initvar+1)
    ram_source[initvar] = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  for (initvar = 0; initvar < 8; initvar = initvar+1)
    ram_address[initvar] = _RAND_4[29:0];
  _RAND_5 = {1{`RANDOM}};
  for (initvar = 0; initvar < 8; initvar = initvar+1)
    ram_mask[initvar] = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  for (initvar = 0; initvar < 8; initvar = initvar+1)
    ram_corrupt[initvar] = _RAND_6[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_7 = {1{`RANDOM}};
  value = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  value_1 = _RAND_8[2:0];
  _RAND_9 = {1{`RANDOM}};
  maybe_full = _RAND_9[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLBuffer_2(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [29:0] auto_in_a_bits_address,
  input         auto_in_a_bits_mask,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output [7:0]  auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [2:0]  auto_out_a_bits_size,
  output [1:0]  auto_out_a_bits_source,
  output [29:0] auto_out_a_bits_address,
  output        auto_out_a_bits_mask,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_size,
  input  [1:0]  auto_out_d_bits_source,
  input  [7:0]  auto_out_d_bits_data
);
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [29:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  bundleOut_0_a_q_clock; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_reset; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_enq_ready; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_enq_valid; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
  wire [1:0] bundleOut_0_a_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
  wire [29:0] bundleOut_0_a_q_io_enq_bits_address; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_enq_bits_mask; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_enq_bits_corrupt; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_deq_ready; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_deq_valid; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
  wire [1:0] bundleOut_0_a_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
  wire [29:0] bundleOut_0_a_q_io_deq_bits_address; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_deq_bits_mask; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
  TLMonitor_14 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  Queue_4 bundleOut_0_a_q ( // @[Decoupled.scala 361:21]
    .clock(bundleOut_0_a_q_clock),
    .reset(bundleOut_0_a_q_reset),
    .io_enq_ready(bundleOut_0_a_q_io_enq_ready),
    .io_enq_valid(bundleOut_0_a_q_io_enq_valid),
    .io_enq_bits_opcode(bundleOut_0_a_q_io_enq_bits_opcode),
    .io_enq_bits_param(bundleOut_0_a_q_io_enq_bits_param),
    .io_enq_bits_size(bundleOut_0_a_q_io_enq_bits_size),
    .io_enq_bits_source(bundleOut_0_a_q_io_enq_bits_source),
    .io_enq_bits_address(bundleOut_0_a_q_io_enq_bits_address),
    .io_enq_bits_mask(bundleOut_0_a_q_io_enq_bits_mask),
    .io_enq_bits_corrupt(bundleOut_0_a_q_io_enq_bits_corrupt),
    .io_deq_ready(bundleOut_0_a_q_io_deq_ready),
    .io_deq_valid(bundleOut_0_a_q_io_deq_valid),
    .io_deq_bits_opcode(bundleOut_0_a_q_io_deq_bits_opcode),
    .io_deq_bits_param(bundleOut_0_a_q_io_deq_bits_param),
    .io_deq_bits_size(bundleOut_0_a_q_io_deq_bits_size),
    .io_deq_bits_source(bundleOut_0_a_q_io_deq_bits_source),
    .io_deq_bits_address(bundleOut_0_a_q_io_deq_bits_address),
    .io_deq_bits_mask(bundleOut_0_a_q_io_deq_bits_mask),
    .io_deq_bits_corrupt(bundleOut_0_a_q_io_deq_bits_corrupt)
  );
  assign auto_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
  assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = bundleOut_0_a_q_io_deq_valid; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_opcode = bundleOut_0_a_q_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_param = bundleOut_0_a_q_io_deq_bits_param; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_size = bundleOut_0_a_q_io_deq_bits_size; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_source = bundleOut_0_a_q_io_deq_bits_source; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_address = bundleOut_0_a_q_io_deq_bits_address; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_mask = bundleOut_0_a_q_io_deq_bits_mask; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_corrupt = bundleOut_0_a_q_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleOut_0_a_q_clock = clock;
  assign bundleOut_0_a_q_reset = reset;
  assign bundleOut_0_a_q_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
endmodule
module TLMonitor_15(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [29:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
  wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
  wire [29:0] _GEN_71 = {{24'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [29:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 30'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [29:0] _T_45 = io_in_a_bits_address ^ 30'h20000000; // @[Parameters.scala 137:31]
  wire [30:0] _T_46 = {1'b0,$signed(_T_45)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_48 = $signed(_T_46) & -31'sh20000000; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 31'sh0; // @[Parameters.scala 137:67]
  wire  _T_59 = 3'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_60 = _source_ok_T & _T_59; // @[Mux.scala 27:73]
  wire  _T_76 = _T_60 & _T_49; // @[Monitor.scala 83:78]
  wire  _T_90 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_94 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_95 = _T_94 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_99 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_103 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_164 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_177 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_192 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
  wire  _T_200 = _T_192 & _T_49; // @[Parameters.scala 670:56]
  wire  _T_211 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_215 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_223 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_260 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_293 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_294 = io_in_a_bits_mask & _T_293; // @[Monitor.scala 127:31]
  wire  _T_295 = _T_294 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_299 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_328 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_336 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_365 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_373 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_402 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  reg [3:0] a_first_counter; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1 = a_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [29:0] address; // @[Monitor.scala 388:22]
  wire  _T_560 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_561 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_565 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_569 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_573 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_577 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
  wire [3:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:2]; // @[Edges.scala 219:59]
  reg [3:0] d_first_counter; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1 = d_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_584 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_593 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_597 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [11:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [3:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1_1 = a_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  reg [3:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_1 = d_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [11:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _GEN_76 = {{4'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_76 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_611 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_614 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [34:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [34:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_616 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_618 = ~_T_616[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [34:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_622 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _GEN_21 = io_in_d_valid & d_first_1 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 671:90 672:22]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [3:0] _GEN_22 = _d_first_T & d_first_1 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_23 = _d_first_T & d_first_1 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_611 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_635 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_637 = _T_635[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_642 = 3'h1 == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_643 = 3'h1 == _GEN_32 | _T_642; // @[Monitor.scala 685:77]
  wire  _T_647 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_654 = 3'h1 == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_655 = 3'h1 == _GEN_48 | _T_654; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_659 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_667 = _T_622 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2; // @[Monitor.scala 694:65]
  wire  _T_671 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set_wo_ready = _GEN_15[2:0];
  wire [2:0] d_clr_wo_ready = _GEN_21[2:0];
  wire  _T_678 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire [2:0] a_set = _GEN_16[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_22[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_19[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_23[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [11:0] a_sizes_set = _GEN_20[11:0];
  wire [11:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [11:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_687 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 4'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= d_first_beats1_decode;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 12'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 4'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= d_first_beats1_decode;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (a_first_done | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_164 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_164) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_200 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_200) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_260 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_260 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_260 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_260 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_260 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_260 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_260 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_260 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_295 & (io_in_a_valid & _T_260 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_260 & ~reset & ~_T_295) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_299 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_299 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_299 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_299 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_299 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_299 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_328 & (io_in_a_valid & _T_299 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_299 & ~reset & ~_T_328) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_299 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_299 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_336 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_336 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_336 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_336 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_336 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_336 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_365 & (io_in_a_valid & _T_336 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_336 & ~reset & ~_T_365) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_336 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_336 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_373 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_373 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_373 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_373 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_373 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_373 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_402 & (io_in_a_valid & _T_373 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_373 & ~reset & ~_T_402) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_373 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_373 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_373 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_373 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at SPI.scala:133:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_561 & (_T_560 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_560 & ~reset & ~_T_561) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_565 & (_T_560 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_560 & ~reset & ~_T_565) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_569 & (_T_560 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_560 & ~reset & ~_T_569) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_573 & (_T_560 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_560 & ~reset & ~_T_573) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_577 & (_T_560 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_560 & ~reset & ~_T_577) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_593 & (_T_584 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_584 & _T_2 & ~_T_593) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at SPI.scala:133:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_597 & (_T_584 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_584 & _T_2 & ~_T_597) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at SPI.scala:133:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_618 & (_T_614 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_614 & ~reset & ~_T_618) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_637 & (_T_622 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_622 & _T_2 & ~_T_637) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SPI.scala:133:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_643 & (_T_622 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_622 & same_cycle_resp & _T_2 & ~_T_643) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at SPI.scala:133:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_647 & (_T_622 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_622 & same_cycle_resp & _T_2 & ~_T_647) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:133:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_655 & (_T_622 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_622 & ~same_cycle_resp & _T_2 & ~_T_655) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at SPI.scala:133:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_659 & (_T_622 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_622 & ~same_cycle_resp & _T_2 & ~_T_659) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:133:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_671 & (_T_667 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_667 & _T_2 & ~_T_671) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_678 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_678) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at SPI.scala:133:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_687 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_687) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at SPI.scala:133:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[29:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  size_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  source_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  inflight = _RAND_9[2:0];
  _RAND_10 = {1{`RANDOM}};
  inflight_opcodes = _RAND_10[11:0];
  _RAND_11 = {1{`RANDOM}};
  inflight_sizes = _RAND_11[11:0];
  _RAND_12 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_12[3:0];
  _RAND_13 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_13[3:0];
  _RAND_14 = {1{`RANDOM}};
  watchdog = _RAND_14[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Repeater_7(
  output        io_enq_ready,
  input         io_enq_valid,
  input  [2:0]  io_enq_bits_opcode,
  input  [2:0]  io_enq_bits_param,
  input  [2:0]  io_enq_bits_size,
  input  [1:0]  io_enq_bits_source,
  input  [29:0] io_enq_bits_address,
  input  [3:0]  io_enq_bits_mask,
  input         io_enq_bits_corrupt,
  input         io_deq_ready,
  output        io_deq_valid,
  output [2:0]  io_deq_bits_opcode,
  output [2:0]  io_deq_bits_param,
  output [2:0]  io_deq_bits_size,
  output [1:0]  io_deq_bits_source,
  output [29:0] io_deq_bits_address,
  output [3:0]  io_deq_bits_mask,
  output        io_deq_bits_corrupt
);
  assign io_enq_ready = io_deq_ready; // @[Repeater.scala 24:32]
  assign io_deq_valid = io_enq_valid; // @[Repeater.scala 23:32]
  assign io_deq_bits_opcode = io_enq_bits_opcode; // @[Repeater.scala 25:21]
  assign io_deq_bits_param = io_enq_bits_param; // @[Repeater.scala 25:21]
  assign io_deq_bits_size = io_enq_bits_size; // @[Repeater.scala 25:21]
  assign io_deq_bits_source = io_enq_bits_source; // @[Repeater.scala 25:21]
  assign io_deq_bits_address = io_enq_bits_address; // @[Repeater.scala 25:21]
  assign io_deq_bits_mask = io_enq_bits_mask; // @[Repeater.scala 25:21]
  assign io_deq_bits_corrupt = io_enq_bits_corrupt; // @[Repeater.scala 25:21]
endmodule
module TLWidthWidget_3(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [29:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output [31:0] auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [2:0]  auto_out_a_bits_size,
  output [1:0]  auto_out_a_bits_source,
  output [29:0] auto_out_a_bits_address,
  output        auto_out_a_bits_mask,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_size,
  input  [1:0]  auto_out_d_bits_source,
  input  [7:0]  auto_out_d_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [29:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  repeated_repeater_io_enq_ready; // @[Repeater.scala 35:26]
  wire  repeated_repeater_io_enq_valid; // @[Repeater.scala 35:26]
  wire [2:0] repeated_repeater_io_enq_bits_opcode; // @[Repeater.scala 35:26]
  wire [2:0] repeated_repeater_io_enq_bits_param; // @[Repeater.scala 35:26]
  wire [2:0] repeated_repeater_io_enq_bits_size; // @[Repeater.scala 35:26]
  wire [1:0] repeated_repeater_io_enq_bits_source; // @[Repeater.scala 35:26]
  wire [29:0] repeated_repeater_io_enq_bits_address; // @[Repeater.scala 35:26]
  wire [3:0] repeated_repeater_io_enq_bits_mask; // @[Repeater.scala 35:26]
  wire  repeated_repeater_io_enq_bits_corrupt; // @[Repeater.scala 35:26]
  wire  repeated_repeater_io_deq_ready; // @[Repeater.scala 35:26]
  wire  repeated_repeater_io_deq_valid; // @[Repeater.scala 35:26]
  wire [2:0] repeated_repeater_io_deq_bits_opcode; // @[Repeater.scala 35:26]
  wire [2:0] repeated_repeater_io_deq_bits_param; // @[Repeater.scala 35:26]
  wire [2:0] repeated_repeater_io_deq_bits_size; // @[Repeater.scala 35:26]
  wire [1:0] repeated_repeater_io_deq_bits_source; // @[Repeater.scala 35:26]
  wire [29:0] repeated_repeater_io_deq_bits_address; // @[Repeater.scala 35:26]
  wire [3:0] repeated_repeater_io_deq_bits_mask; // @[Repeater.scala 35:26]
  wire  repeated_repeater_io_deq_bits_corrupt; // @[Repeater.scala 35:26]
  wire [29:0] cated_bits_address = repeated_repeater_io_deq_bits_address; // @[WidthWidget.scala 155:25 156:15]
  wire [1:0] repeat_sel = cated_bits_address[1:0]; // @[WidthWidget.scala 110:39]
  wire [3:0] cated_bits_mask = repeated_repeater_io_deq_bits_mask; // @[WidthWidget.scala 155:25 156:15]
  wire  repeat_bundleOut_0_a_bits_mask_mux_0 = cated_bits_mask[0]; // @[WidthWidget.scala 122:55]
  wire  repeat_bundleOut_0_a_bits_mask_mux_1 = cated_bits_mask[1]; // @[WidthWidget.scala 122:55]
  wire  repeat_bundleOut_0_a_bits_mask_mux_2 = cated_bits_mask[2]; // @[WidthWidget.scala 122:55]
  wire  repeat_bundleOut_0_a_bits_mask_mux_3 = cated_bits_mask[3]; // @[WidthWidget.scala 122:55]
  wire  _GEN_3 = 2'h1 == repeat_sel ? repeat_bundleOut_0_a_bits_mask_mux_1 : repeat_bundleOut_0_a_bits_mask_mux_0; // @[WidthWidget.scala 134:{53,53}]
  wire  _GEN_4 = 2'h2 == repeat_sel ? repeat_bundleOut_0_a_bits_mask_mux_2 : _GEN_3; // @[WidthWidget.scala 134:{53,53}]
  wire [8:0] _limit_T_1 = 9'h3 << auto_out_d_bits_size; // @[package.scala 234:77]
  wire [1:0] limit = ~_limit_T_1[1:0]; // @[package.scala 234:46]
  reg [1:0] count; // @[WidthWidget.scala 34:27]
  wire  last = count == limit; // @[WidthWidget.scala 36:26]
  wire [1:0] _enable_T_1 = count & limit; // @[WidthWidget.scala 37:63]
  wire  enable_0 = ~(|_enable_T_1); // @[WidthWidget.scala 37:47]
  wire [1:0] _enable_T_3 = count ^ 2'h1; // @[WidthWidget.scala 37:56]
  wire [1:0] _enable_T_4 = _enable_T_3 & limit; // @[WidthWidget.scala 37:63]
  wire  enable_1 = ~(|_enable_T_4); // @[WidthWidget.scala 37:47]
  wire [1:0] _enable_T_6 = count ^ 2'h2; // @[WidthWidget.scala 37:56]
  wire [1:0] _enable_T_7 = _enable_T_6 & limit; // @[WidthWidget.scala 37:63]
  wire  enable_2 = ~(|_enable_T_7); // @[WidthWidget.scala 37:47]
  wire  _bundleOut_0_d_ready_T = ~last; // @[WidthWidget.scala 70:32]
  wire  bundleOut_0_d_ready = auto_in_d_ready | ~last; // @[WidthWidget.scala 70:29]
  wire  _T = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
  wire [1:0] _count_T_1 = count + 2'h1; // @[WidthWidget.scala 44:24]
  reg  bundleIn_0_d_bits_data_rdata_written_once; // @[WidthWidget.scala 56:41]
  wire  bundleIn_0_d_bits_data_masked_enable_0 = enable_0 | ~bundleIn_0_d_bits_data_rdata_written_once; // @[WidthWidget.scala 57:42]
  wire  bundleIn_0_d_bits_data_masked_enable_1 = enable_1 | ~bundleIn_0_d_bits_data_rdata_written_once; // @[WidthWidget.scala 57:42]
  wire  bundleIn_0_d_bits_data_masked_enable_2 = enable_2 | ~bundleIn_0_d_bits_data_rdata_written_once; // @[WidthWidget.scala 57:42]
  reg [7:0] bundleIn_0_d_bits_data_rdata_0; // @[WidthWidget.scala 60:24]
  reg [7:0] bundleIn_0_d_bits_data_rdata_1; // @[WidthWidget.scala 60:24]
  reg [7:0] bundleIn_0_d_bits_data_rdata_2; // @[WidthWidget.scala 60:24]
  wire [7:0] bundleIn_0_d_bits_data_mdata_0 = bundleIn_0_d_bits_data_masked_enable_0 ? auto_out_d_bits_data :
    bundleIn_0_d_bits_data_rdata_0; // @[WidthWidget.scala 62:88]
  wire [7:0] bundleIn_0_d_bits_data_mdata_1 = bundleIn_0_d_bits_data_masked_enable_1 ? auto_out_d_bits_data :
    bundleIn_0_d_bits_data_rdata_1; // @[WidthWidget.scala 62:88]
  wire [7:0] bundleIn_0_d_bits_data_mdata_2 = bundleIn_0_d_bits_data_masked_enable_2 ? auto_out_d_bits_data :
    bundleIn_0_d_bits_data_rdata_2; // @[WidthWidget.scala 62:88]
  wire  _GEN_10 = _T & _bundleOut_0_d_ready_T | bundleIn_0_d_bits_data_rdata_written_once; // @[WidthWidget.scala 63:35 64:30 56:41]
  wire [15:0] bundleIn_0_d_bits_data_lo = {bundleIn_0_d_bits_data_mdata_1,bundleIn_0_d_bits_data_mdata_0}; // @[Cat.scala 31:58]
  wire [15:0] bundleIn_0_d_bits_data_hi = {auto_out_d_bits_data,bundleIn_0_d_bits_data_mdata_2}; // @[Cat.scala 31:58]
  TLMonitor_15 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  Repeater_7 repeated_repeater ( // @[Repeater.scala 35:26]
    .io_enq_ready(repeated_repeater_io_enq_ready),
    .io_enq_valid(repeated_repeater_io_enq_valid),
    .io_enq_bits_opcode(repeated_repeater_io_enq_bits_opcode),
    .io_enq_bits_param(repeated_repeater_io_enq_bits_param),
    .io_enq_bits_size(repeated_repeater_io_enq_bits_size),
    .io_enq_bits_source(repeated_repeater_io_enq_bits_source),
    .io_enq_bits_address(repeated_repeater_io_enq_bits_address),
    .io_enq_bits_mask(repeated_repeater_io_enq_bits_mask),
    .io_enq_bits_corrupt(repeated_repeater_io_enq_bits_corrupt),
    .io_deq_ready(repeated_repeater_io_deq_ready),
    .io_deq_valid(repeated_repeater_io_deq_valid),
    .io_deq_bits_opcode(repeated_repeater_io_deq_bits_opcode),
    .io_deq_bits_param(repeated_repeater_io_deq_bits_param),
    .io_deq_bits_size(repeated_repeater_io_deq_bits_size),
    .io_deq_bits_source(repeated_repeater_io_deq_bits_source),
    .io_deq_bits_address(repeated_repeater_io_deq_bits_address),
    .io_deq_bits_mask(repeated_repeater_io_deq_bits_mask),
    .io_deq_bits_corrupt(repeated_repeater_io_deq_bits_corrupt)
  );
  assign auto_in_a_ready = repeated_repeater_io_enq_ready; // @[Nodes.scala 1210:84 Repeater.scala 37:21]
  assign auto_in_d_valid = auto_out_d_valid & last; // @[WidthWidget.scala 71:29]
  assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_data = {bundleIn_0_d_bits_data_hi,bundleIn_0_d_bits_data_lo}; // @[Cat.scala 31:58]
  assign auto_out_a_valid = repeated_repeater_io_deq_valid; // @[WidthWidget.scala 155:25 156:15]
  assign auto_out_a_bits_opcode = repeated_repeater_io_deq_bits_opcode; // @[WidthWidget.scala 155:25 156:15]
  assign auto_out_a_bits_param = repeated_repeater_io_deq_bits_param; // @[WidthWidget.scala 155:25 156:15]
  assign auto_out_a_bits_size = repeated_repeater_io_deq_bits_size; // @[WidthWidget.scala 155:25 156:15]
  assign auto_out_a_bits_source = repeated_repeater_io_deq_bits_source; // @[WidthWidget.scala 155:25 156:15]
  assign auto_out_a_bits_address = repeated_repeater_io_deq_bits_address; // @[WidthWidget.scala 155:25 156:15]
  assign auto_out_a_bits_mask = 2'h3 == repeat_sel ? repeat_bundleOut_0_a_bits_mask_mux_3 : _GEN_4; // @[WidthWidget.scala 134:{53,53}]
  assign auto_out_a_bits_corrupt = repeated_repeater_io_deq_bits_corrupt; // @[WidthWidget.scala 155:25 156:15]
  assign auto_out_d_ready = auto_in_d_ready | ~last; // @[WidthWidget.scala 70:29]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = repeated_repeater_io_enq_ready; // @[Nodes.scala 1210:84 Repeater.scala 37:21]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid & last; // @[WidthWidget.scala 71:29]
  assign monitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign repeated_repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeated_repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeated_repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeated_repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeated_repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeated_repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeated_repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeated_repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeated_repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  always @(posedge clock) begin
    if (reset) begin // @[WidthWidget.scala 34:27]
      count <= 2'h0; // @[WidthWidget.scala 34:27]
    end else if (_T) begin // @[WidthWidget.scala 43:24]
      if (last) begin // @[WidthWidget.scala 46:21]
        count <= 2'h0; // @[WidthWidget.scala 47:17]
      end else begin
        count <= _count_T_1; // @[WidthWidget.scala 44:15]
      end
    end
    if (reset) begin // @[WidthWidget.scala 56:41]
      bundleIn_0_d_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala 56:41]
    end else begin
      bundleIn_0_d_bits_data_rdata_written_once <= _GEN_10;
    end
    if (_T & _bundleOut_0_d_ready_T) begin // @[WidthWidget.scala 63:35]
      if (bundleIn_0_d_bits_data_masked_enable_0) begin // @[WidthWidget.scala 62:88]
        bundleIn_0_d_bits_data_rdata_0 <= auto_out_d_bits_data;
      end
    end
    if (_T & _bundleOut_0_d_ready_T) begin // @[WidthWidget.scala 63:35]
      if (bundleIn_0_d_bits_data_masked_enable_1) begin // @[WidthWidget.scala 62:88]
        bundleIn_0_d_bits_data_rdata_1 <= auto_out_d_bits_data;
      end
    end
    if (_T & _bundleOut_0_d_ready_T) begin // @[WidthWidget.scala 63:35]
      if (bundleIn_0_d_bits_data_masked_enable_2) begin // @[WidthWidget.scala 62:88]
        bundleIn_0_d_bits_data_rdata_2 <= auto_out_d_bits_data;
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  count = _RAND_0[1:0];
  _RAND_1 = {1{`RANDOM}};
  bundleIn_0_d_bits_data_rdata_written_once = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  bundleIn_0_d_bits_data_rdata_0 = _RAND_2[7:0];
  _RAND_3 = {1{`RANDOM}};
  bundleIn_0_d_bits_data_rdata_1 = _RAND_3[7:0];
  _RAND_4 = {1{`RANDOM}};
  bundleIn_0_d_bits_data_rdata_2 = _RAND_4[7:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLInterconnectCoupler_10(
  input         clock,
  input         reset,
  input         auto_mem_xing_out_a_ready,
  output        auto_mem_xing_out_a_valid,
  output [2:0]  auto_mem_xing_out_a_bits_opcode,
  output [2:0]  auto_mem_xing_out_a_bits_param,
  output        auto_mem_xing_out_a_bits_size,
  output [8:0]  auto_mem_xing_out_a_bits_source,
  output [29:0] auto_mem_xing_out_a_bits_address,
  output        auto_mem_xing_out_a_bits_mask,
  output        auto_mem_xing_out_a_bits_corrupt,
  output        auto_mem_xing_out_d_ready,
  input         auto_mem_xing_out_d_valid,
  input         auto_mem_xing_out_d_bits_size,
  input  [8:0]  auto_mem_xing_out_d_bits_source,
  input  [7:0]  auto_mem_xing_out_d_bits_data,
  output        auto_tl_in_a_ready,
  input         auto_tl_in_a_valid,
  input  [2:0]  auto_tl_in_a_bits_opcode,
  input  [2:0]  auto_tl_in_a_bits_param,
  input  [2:0]  auto_tl_in_a_bits_size,
  input  [1:0]  auto_tl_in_a_bits_source,
  input  [29:0] auto_tl_in_a_bits_address,
  input  [3:0]  auto_tl_in_a_bits_mask,
  input         auto_tl_in_a_bits_corrupt,
  input         auto_tl_in_d_ready,
  output        auto_tl_in_d_valid,
  output [2:0]  auto_tl_in_d_bits_size,
  output [1:0]  auto_tl_in_d_bits_source,
  output [31:0] auto_tl_in_d_bits_data
);
  wire  fragmenter_clock; // @[Fragmenter.scala 333:34]
  wire  fragmenter_reset; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [29:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [7:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [8:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [29:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [8:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [7:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
  wire  buffer_clock; // @[Buffer.scala 68:28]
  wire  buffer_reset; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
  wire [29:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
  wire [7:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
  wire [29:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 68:28]
  wire [7:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
  wire  widget_clock; // @[WidthWidget.scala 219:28]
  wire  widget_reset; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_a_ready; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_a_valid; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_a_bits_opcode; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_a_bits_param; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_a_bits_size; // @[WidthWidget.scala 219:28]
  wire [1:0] widget_auto_in_a_bits_source; // @[WidthWidget.scala 219:28]
  wire [29:0] widget_auto_in_a_bits_address; // @[WidthWidget.scala 219:28]
  wire [3:0] widget_auto_in_a_bits_mask; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_a_bits_corrupt; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_d_ready; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_d_valid; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_d_bits_size; // @[WidthWidget.scala 219:28]
  wire [1:0] widget_auto_in_d_bits_source; // @[WidthWidget.scala 219:28]
  wire [31:0] widget_auto_in_d_bits_data; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_a_ready; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_a_valid; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_a_bits_opcode; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_a_bits_param; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_a_bits_size; // @[WidthWidget.scala 219:28]
  wire [1:0] widget_auto_out_a_bits_source; // @[WidthWidget.scala 219:28]
  wire [29:0] widget_auto_out_a_bits_address; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_a_bits_mask; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_a_bits_corrupt; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_d_ready; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_d_valid; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_d_bits_size; // @[WidthWidget.scala 219:28]
  wire [1:0] widget_auto_out_d_bits_source; // @[WidthWidget.scala 219:28]
  wire [7:0] widget_auto_out_d_bits_data; // @[WidthWidget.scala 219:28]
  TLFragmenter_6 fragmenter ( // @[Fragmenter.scala 333:34]
    .clock(fragmenter_clock),
    .reset(fragmenter_reset),
    .auto_in_a_ready(fragmenter_auto_in_a_ready),
    .auto_in_a_valid(fragmenter_auto_in_a_valid),
    .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
    .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
    .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
    .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
    .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
    .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
    .auto_in_d_ready(fragmenter_auto_in_d_ready),
    .auto_in_d_valid(fragmenter_auto_in_d_valid),
    .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
    .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
    .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
    .auto_out_a_ready(fragmenter_auto_out_a_ready),
    .auto_out_a_valid(fragmenter_auto_out_a_valid),
    .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
    .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
    .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
    .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
    .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
    .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
    .auto_out_d_ready(fragmenter_auto_out_d_ready),
    .auto_out_d_valid(fragmenter_auto_out_d_valid),
    .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
    .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
    .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
  );
  TLBuffer_2 buffer ( // @[Buffer.scala 68:28]
    .clock(buffer_clock),
    .reset(buffer_reset),
    .auto_in_a_ready(buffer_auto_in_a_ready),
    .auto_in_a_valid(buffer_auto_in_a_valid),
    .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
    .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
    .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
    .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
    .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
    .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
    .auto_in_d_ready(buffer_auto_in_d_ready),
    .auto_in_d_valid(buffer_auto_in_d_valid),
    .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
    .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
    .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
    .auto_out_a_ready(buffer_auto_out_a_ready),
    .auto_out_a_valid(buffer_auto_out_a_valid),
    .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
    .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
    .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
    .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
    .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
    .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
    .auto_out_d_ready(buffer_auto_out_d_ready),
    .auto_out_d_valid(buffer_auto_out_d_valid),
    .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
    .auto_out_d_bits_source(buffer_auto_out_d_bits_source),
    .auto_out_d_bits_data(buffer_auto_out_d_bits_data)
  );
  TLWidthWidget_3 widget ( // @[WidthWidget.scala 219:28]
    .clock(widget_clock),
    .reset(widget_reset),
    .auto_in_a_ready(widget_auto_in_a_ready),
    .auto_in_a_valid(widget_auto_in_a_valid),
    .auto_in_a_bits_opcode(widget_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(widget_auto_in_a_bits_param),
    .auto_in_a_bits_size(widget_auto_in_a_bits_size),
    .auto_in_a_bits_source(widget_auto_in_a_bits_source),
    .auto_in_a_bits_address(widget_auto_in_a_bits_address),
    .auto_in_a_bits_mask(widget_auto_in_a_bits_mask),
    .auto_in_a_bits_corrupt(widget_auto_in_a_bits_corrupt),
    .auto_in_d_ready(widget_auto_in_d_ready),
    .auto_in_d_valid(widget_auto_in_d_valid),
    .auto_in_d_bits_size(widget_auto_in_d_bits_size),
    .auto_in_d_bits_source(widget_auto_in_d_bits_source),
    .auto_in_d_bits_data(widget_auto_in_d_bits_data),
    .auto_out_a_ready(widget_auto_out_a_ready),
    .auto_out_a_valid(widget_auto_out_a_valid),
    .auto_out_a_bits_opcode(widget_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(widget_auto_out_a_bits_param),
    .auto_out_a_bits_size(widget_auto_out_a_bits_size),
    .auto_out_a_bits_source(widget_auto_out_a_bits_source),
    .auto_out_a_bits_address(widget_auto_out_a_bits_address),
    .auto_out_a_bits_mask(widget_auto_out_a_bits_mask),
    .auto_out_a_bits_corrupt(widget_auto_out_a_bits_corrupt),
    .auto_out_d_ready(widget_auto_out_d_ready),
    .auto_out_d_valid(widget_auto_out_d_valid),
    .auto_out_d_bits_size(widget_auto_out_d_bits_size),
    .auto_out_d_bits_source(widget_auto_out_d_bits_source),
    .auto_out_d_bits_data(widget_auto_out_d_bits_data)
  );
  assign auto_mem_xing_out_a_valid = fragmenter_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_mem_xing_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_mem_xing_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_mem_xing_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_mem_xing_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_mem_xing_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_mem_xing_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_mem_xing_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_mem_xing_out_d_ready = fragmenter_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_in_a_ready = widget_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_valid = widget_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_size = widget_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_source = widget_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_data = widget_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign fragmenter_clock = clock;
  assign fragmenter_reset = reset;
  assign fragmenter_auto_in_a_valid = buffer_auto_out_a_valid; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_in_a_bits_param = buffer_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_in_a_bits_size = buffer_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_in_a_bits_source = buffer_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_in_a_bits_address = buffer_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_in_d_ready = buffer_auto_out_d_ready; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_out_a_ready = auto_mem_xing_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_valid = auto_mem_xing_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_size = auto_mem_xing_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_source = auto_mem_xing_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_data = auto_mem_xing_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign buffer_clock = clock;
  assign buffer_reset = reset;
  assign buffer_auto_in_a_valid = widget_auto_out_a_valid; // @[LazyModule.scala 296:16]
  assign buffer_auto_in_a_bits_opcode = widget_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign buffer_auto_in_a_bits_param = widget_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
  assign buffer_auto_in_a_bits_size = widget_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign buffer_auto_in_a_bits_source = widget_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign buffer_auto_in_a_bits_address = widget_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign buffer_auto_in_a_bits_mask = widget_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign buffer_auto_in_a_bits_corrupt = widget_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
  assign buffer_auto_in_d_ready = widget_auto_out_d_ready; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_a_ready = fragmenter_auto_in_a_ready; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_valid = fragmenter_auto_in_d_valid; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_size = fragmenter_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_source = fragmenter_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_data = fragmenter_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
  assign widget_clock = clock;
  assign widget_reset = reset;
  assign widget_auto_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign widget_auto_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign widget_auto_out_a_ready = buffer_auto_in_a_ready; // @[LazyModule.scala 296:16]
  assign widget_auto_out_d_valid = buffer_auto_in_d_valid; // @[LazyModule.scala 296:16]
  assign widget_auto_out_d_bits_size = buffer_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
  assign widget_auto_out_d_bits_source = buffer_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
  assign widget_auto_out_d_bits_data = buffer_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
endmodule
module TLMonitor_16(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [28:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [2:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
  wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
  wire [28:0] _GEN_71 = {{23'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [28:0] _T_45 = io_in_a_bits_address ^ 29'h10034000; // @[Parameters.scala 137:31]
  wire [29:0] _T_46 = {1'b0,$signed(_T_45)}; // @[Parameters.scala 137:49]
  wire [29:0] _T_48 = $signed(_T_46) & -30'sh1000; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 30'sh0; // @[Parameters.scala 137:67]
  wire  _T_59 = 3'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_60 = _source_ok_T & _T_59; // @[Mux.scala 27:73]
  wire  _T_76 = _T_60 & _T_49; // @[Monitor.scala 83:78]
  wire  _T_90 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_94 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_95 = _T_94 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_99 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_103 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_164 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_177 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_192 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
  wire  _T_200 = _T_192 & _T_49; // @[Parameters.scala 670:56]
  wire  _T_211 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_215 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_223 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_245 = source_ok & _T_200; // @[Monitor.scala 115:71]
  wire  _T_263 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_299 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_300 = io_in_a_bits_mask & _T_299; // @[Monitor.scala 127:31]
  wire  _T_301 = _T_300 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_305 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_334 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_342 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_371 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_379 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_408 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_420 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  _T_424 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_428 = io_in_d_bits_size >= 3'h2; // @[Monitor.scala 312:27]
  wire  _T_444 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_472 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_501 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_518 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_536 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [3:0] a_first_beats1_decode = is_aligned_mask[5:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] a_first_counter; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1 = a_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [28:0] address; // @[Monitor.scala 388:22]
  wire  _T_566 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_567 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_571 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_575 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_579 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_583 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
  wire [3:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [3:0] d_first_counter; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1 = d_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_590 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_591 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_599 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_603 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [11:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [3:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1_1 = a_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  reg [3:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_1 = d_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [11:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _GEN_76 = {{4'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_76 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_617 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_620 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [34:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [34:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_622 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_624 = ~_T_622[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [34:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_628 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_630 = ~_T_424; // @[Monitor.scala 671:74]
  wire  _T_631 = io_in_d_valid & d_first_1 & ~_T_424; // @[Monitor.scala 671:71]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [3:0] _GEN_22 = _d_first_T & d_first_1 & _T_630 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_23 = _d_first_T & d_first_1 & _T_630 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_617 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_641 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_643 = _T_641[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_648 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_649 = io_in_d_bits_opcode == _GEN_32 | _T_648; // @[Monitor.scala 685:77]
  wire  _T_653 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_660 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_661 = io_in_d_bits_opcode == _GEN_48 | _T_660; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_665 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_675 = _T_628 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_630; // @[Monitor.scala 694:116]
  wire  _T_677 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set = _GEN_16[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_22[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_19[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_23[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [11:0] a_sizes_set = _GEN_20[11:0];
  wire [11:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [11:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_686 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [2:0] inflight_1; // @[Monitor.scala 723:35]
  reg [11:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [3:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_2 = d_first_counter_2 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 4'h0; // @[Edges.scala 230:25]
  wire [11:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [15:0] _GEN_87 = {{4'd0}, _c_size_lookup_T_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_87 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_712 = io_in_d_valid & d_first_2 & _T_424; // @[Monitor.scala 779:71]
  wire [3:0] _GEN_67 = _d_first_T & d_first_2 & _T_424 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 783:90 784:21]
  wire [46:0] _GEN_68 = _d_first_T & d_first_2 & _T_424 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 785:21]
  wire [2:0] _T_720 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_730 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [2:0] d_clr_1 = _GEN_67[2:0];
  wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [2:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [11:0] d_opcodes_clr_1 = _GEN_68[11:0];
  wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [11:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_750 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 4'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 4'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 12'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 4'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 4'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 3'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 12'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 4'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_164 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_164) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_200 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_200) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_301 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_301) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_334 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_334) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_371 & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~_T_371) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_408 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_408) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_420 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_420) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at SPI.scala:65:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at SPI.scala:65:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at SPI.scala:65:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at SPI.scala:65:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at SPI.scala:65:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at SPI.scala:65:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at SPI.scala:65:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at SPI.scala:65:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at SPI.scala:65:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_501 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_501 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at SPI.scala:65:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_518 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_518 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at SPI.scala:65:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_536 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_536 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at SPI.scala:65:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_567 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_567) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_571 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_571) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_575 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_575) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_579 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_579) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_583 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_583) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_591 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_591) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at SPI.scala:65:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_599 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_599) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at SPI.scala:65:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_603 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_603) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at SPI.scala:65:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_624 & (_T_620 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_620 & ~reset & ~_T_624) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_643 & (_T_631 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & _T_2 & ~_T_643) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SPI.scala:65:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_649 & (_T_631 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & same_cycle_resp & _T_2 & ~_T_649) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at SPI.scala:65:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_653 & (_T_631 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & same_cycle_resp & _T_2 & ~_T_653) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:65:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_661 & (_T_631 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & ~same_cycle_resp & _T_2 & ~_T_661) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at SPI.scala:65:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_665 & (_T_631 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & ~same_cycle_resp & _T_2 & ~_T_665) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:65:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_677 & (_T_675 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_675 & _T_2 & ~_T_677) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_686 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_686) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_720[0] & (_T_712 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_712 & _T_2 & ~_T_720[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SPI.scala:65:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_730 & (_T_712 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_712 & _T_2 & ~_T_730) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:65:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_750 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_750) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at SPI.scala:65:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[28:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[2:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[1:0];
  _RAND_10 = {1{`RANDOM}};
  inflight = _RAND_10[2:0];
  _RAND_11 = {1{`RANDOM}};
  inflight_opcodes = _RAND_11[11:0];
  _RAND_12 = {1{`RANDOM}};
  inflight_sizes = _RAND_12[11:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[3:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[3:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  inflight_1 = _RAND_16[2:0];
  _RAND_17 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_17[11:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[3:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLFragmenter_7(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [28:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output [31:0] auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [1:0]  auto_out_a_bits_size,
  output [6:0]  auto_out_a_bits_source,
  output [28:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_size,
  input  [6:0]  auto_out_d_bits_source,
  input  [31:0] auto_out_d_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  repeater_clock; // @[Fragmenter.scala 262:30]
  wire  repeater_reset; // @[Fragmenter.scala 262:30]
  wire  repeater_io_repeat; // @[Fragmenter.scala 262:30]
  wire  repeater_io_full; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
  wire [28:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
  wire [28:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
  reg [3:0] acknum; // @[Fragmenter.scala 189:29]
  reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
  reg  dToggle; // @[Fragmenter.scala 191:30]
  wire [3:0] dFragnum = auto_out_d_bits_source[3:0]; // @[Fragmenter.scala 192:41]
  wire  dFirst = acknum == 4'h0; // @[Fragmenter.scala 193:29]
  wire  dLast = dFragnum == 4'h0; // @[Fragmenter.scala 194:30]
  wire [3:0] _dsizeOH_T = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 64:12]
  wire [2:0] dsizeOH = _dsizeOH_T[2:0]; // @[OneHot.scala 64:27]
  wire [4:0] _dsizeOH1_T_1 = 5'h3 << auto_out_d_bits_size; // @[package.scala 234:77]
  wire [1:0] dsizeOH1 = ~_dsizeOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  dHasData = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  _T_5 = ~reset; // @[Fragmenter.scala 202:16]
  wire  ack_decrement = dHasData | dsizeOH[2]; // @[Fragmenter.scala 204:32]
  wire [5:0] _dFirst_size_T = {dFragnum, 2'h0}; // @[Fragmenter.scala 206:47]
  wire [5:0] _GEN_7 = {{4'd0}, dsizeOH1}; // @[Fragmenter.scala 206:69]
  wire [5:0] _dFirst_size_T_1 = _dFirst_size_T | _GEN_7; // @[Fragmenter.scala 206:69]
  wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala 232:35]
  wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
  wire [6:0] _dFirst_size_T_4 = {1'h0,_dFirst_size_T_1}; // @[Cat.scala 31:58]
  wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
  wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
  wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
  wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
  wire [3:0] _GEN_8 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
  wire [3:0] _dFirst_size_T_8 = _GEN_8 | dFirst_size_lo; // @[OneHot.scala 32:28]
  wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
  wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
  wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
  wire  drop = ~dHasData & ~dLast; // @[Fragmenter.scala 222:30]
  wire  bundleOut_0_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  wire  _T_7 = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
  wire [3:0] _GEN_9 = {{3'd0}, ack_decrement}; // @[Fragmenter.scala 209:55]
  wire [3:0] _acknum_T_1 = acknum - _GEN_9; // @[Fragmenter.scala 209:55]
  wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h2 ? 3'h2 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
  wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
  wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
  wire [8:0] _aFragOH1_T_1 = 9'h3 << aFrag; // @[package.scala 234:77]
  wire [1:0] aFragOH1 = ~_aFragOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  aHasData = ~repeater_io_deq_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] gennum; // @[Fragmenter.scala 291:29]
  wire  aFirst = gennum == 4'h0; // @[Fragmenter.scala 292:29]
  wire [3:0] _old_gennum1_T_2 = gennum - 4'h1; // @[Fragmenter.scala 293:79]
  wire [3:0] old_gennum1 = aFirst ? aOrigOH1[5:2] : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
  wire [3:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
  wire [3:0] new_gennum = ~_new_gennum_T; // @[Fragmenter.scala 294:26]
  reg  aToggle_r; // @[Reg.scala 16:16]
  wire  _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
  wire  aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
  wire  bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  wire  _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
  wire  _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala 302:31]
  wire [5:0] _bundleOut_0_a_bits_address_T = {old_gennum1, 2'h0}; // @[Fragmenter.scala 304:65]
  wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
  wire [5:0] _bundleOut_0_a_bits_address_T_2 = _bundleOut_0_a_bits_address_T | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
  wire [5:0] _GEN_10 = {{4'd0}, aFragOH1}; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_10; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_4 = _bundleOut_0_a_bits_address_T_3 | 6'h3; // @[Fragmenter.scala 304:111]
  wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_4; // @[Fragmenter.scala 304:51]
  wire [28:0] _GEN_11 = {{23'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
  wire [2:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aToggle}; // @[Cat.scala 31:58]
  wire  _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
  TLMonitor_16 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  Repeater repeater ( // @[Fragmenter.scala 262:30]
    .clock(repeater_clock),
    .reset(repeater_reset),
    .io_repeat(repeater_io_repeat),
    .io_full(repeater_io_full),
    .io_enq_ready(repeater_io_enq_ready),
    .io_enq_valid(repeater_io_enq_valid),
    .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
    .io_enq_bits_param(repeater_io_enq_bits_param),
    .io_enq_bits_size(repeater_io_enq_bits_size),
    .io_enq_bits_source(repeater_io_enq_bits_source),
    .io_enq_bits_address(repeater_io_enq_bits_address),
    .io_enq_bits_mask(repeater_io_enq_bits_mask),
    .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
    .io_deq_ready(repeater_io_deq_ready),
    .io_deq_valid(repeater_io_deq_valid),
    .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
    .io_deq_bits_param(repeater_io_deq_bits_param),
    .io_deq_bits_size(repeater_io_deq_bits_size),
    .io_deq_bits_source(repeater_io_deq_bits_source),
    .io_deq_bits_address(repeater_io_deq_bits_address),
    .io_deq_bits_mask(repeater_io_deq_bits_mask),
    .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
  );
  assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign auto_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign auto_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_size = aFrag[1:0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
  assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,new_gennum}; // @[Cat.scala 31:58]
  assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_11; // @[Fragmenter.scala 304:49]
  assign auto_out_a_bits_mask = repeater_io_full ? 4'hf : auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = repeater_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign repeater_clock = clock;
  assign repeater_reset = reset;
  assign repeater_io_repeat = ~aHasData & new_gennum != 4'h0; // @[Fragmenter.scala 302:41]
  assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  always @(posedge clock) begin
    if (reset) begin // @[Fragmenter.scala 189:29]
      acknum <= 4'h0; // @[Fragmenter.scala 189:29]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 209:24]
        acknum <= dFragnum;
      end else begin
        acknum <= _acknum_T_1;
      end
    end
    if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
      end
    end
    if (reset) begin // @[Fragmenter.scala 191:30]
      dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dToggle <= auto_out_d_bits_source[4]; // @[Fragmenter.scala 212:21]
      end
    end
    if (reset) begin // @[Fragmenter.scala 291:29]
      gennum <= 4'h0; // @[Fragmenter.scala 291:29]
    end else if (_T_8) begin // @[Fragmenter.scala 300:29]
      gennum <= new_gennum; // @[Fragmenter.scala 300:38]
    end
    if (aFirst) begin // @[Reg.scala 17:18]
      aToggle_r <= dToggle; // @[Reg.scala 17:22]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~repeater_io_full | _repeater_io_repeat_T) & _T_5) begin
          $fatal; // @[Fragmenter.scala 309:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(~repeater_io_full | _repeater_io_repeat_T)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Fragmenter.scala:309 assert (!repeater.io.full || !aHasData)\n"
            ); // @[Fragmenter.scala 309:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_9 | repeater_io_deq_bits_mask == 4'hf) & _T_5) begin
          $fatal; // @[Fragmenter.scala 312:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask == 4'hf)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
            ); // @[Fragmenter.scala 312:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  acknum = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  dOrig = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  dToggle = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  gennum = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  aToggle_r = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLInterconnectCoupler_11(
  input         clock,
  input         reset,
  input         auto_control_xing_out_a_ready,
  output        auto_control_xing_out_a_valid,
  output [2:0]  auto_control_xing_out_a_bits_opcode,
  output [2:0]  auto_control_xing_out_a_bits_param,
  output [1:0]  auto_control_xing_out_a_bits_size,
  output [6:0]  auto_control_xing_out_a_bits_source,
  output [28:0] auto_control_xing_out_a_bits_address,
  output [3:0]  auto_control_xing_out_a_bits_mask,
  output [31:0] auto_control_xing_out_a_bits_data,
  output        auto_control_xing_out_a_bits_corrupt,
  output        auto_control_xing_out_d_ready,
  input         auto_control_xing_out_d_valid,
  input  [2:0]  auto_control_xing_out_d_bits_opcode,
  input  [1:0]  auto_control_xing_out_d_bits_size,
  input  [6:0]  auto_control_xing_out_d_bits_source,
  input  [31:0] auto_control_xing_out_d_bits_data,
  output        auto_tl_in_a_ready,
  input         auto_tl_in_a_valid,
  input  [2:0]  auto_tl_in_a_bits_opcode,
  input  [2:0]  auto_tl_in_a_bits_param,
  input  [2:0]  auto_tl_in_a_bits_size,
  input  [1:0]  auto_tl_in_a_bits_source,
  input  [28:0] auto_tl_in_a_bits_address,
  input  [3:0]  auto_tl_in_a_bits_mask,
  input  [31:0] auto_tl_in_a_bits_data,
  input         auto_tl_in_a_bits_corrupt,
  input         auto_tl_in_d_ready,
  output        auto_tl_in_d_valid,
  output [2:0]  auto_tl_in_d_bits_opcode,
  output [2:0]  auto_tl_in_d_bits_size,
  output [1:0]  auto_tl_in_d_bits_source,
  output [31:0] auto_tl_in_d_bits_data
);
  wire  fragmenter_clock; // @[Fragmenter.scala 333:34]
  wire  fragmenter_reset; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [28:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [28:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
  TLFragmenter_7 fragmenter ( // @[Fragmenter.scala 333:34]
    .clock(fragmenter_clock),
    .reset(fragmenter_reset),
    .auto_in_a_ready(fragmenter_auto_in_a_ready),
    .auto_in_a_valid(fragmenter_auto_in_a_valid),
    .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
    .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
    .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
    .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
    .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
    .auto_in_a_bits_data(fragmenter_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
    .auto_in_d_ready(fragmenter_auto_in_d_ready),
    .auto_in_d_valid(fragmenter_auto_in_d_valid),
    .auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
    .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
    .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
    .auto_out_a_ready(fragmenter_auto_out_a_ready),
    .auto_out_a_valid(fragmenter_auto_out_a_valid),
    .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
    .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
    .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
    .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
    .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
    .auto_out_a_bits_data(fragmenter_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
    .auto_out_d_ready(fragmenter_auto_out_d_ready),
    .auto_out_d_valid(fragmenter_auto_out_d_valid),
    .auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
    .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
    .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
  );
  assign auto_control_xing_out_a_valid = fragmenter_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_data = fragmenter_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_d_ready = fragmenter_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_in_a_ready = fragmenter_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_valid = fragmenter_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_size = fragmenter_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_source = fragmenter_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_data = fragmenter_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign fragmenter_clock = clock;
  assign fragmenter_reset = reset;
  assign fragmenter_auto_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_data = auto_tl_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_out_a_ready = auto_control_xing_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_valid = auto_control_xing_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_opcode = auto_control_xing_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_size = auto_control_xing_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_source = auto_control_xing_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_data = auto_control_xing_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
endmodule
module TLMonitor_17(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [28:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [2:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
  wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
  wire [28:0] _GEN_71 = {{23'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [28:0] _T_45 = io_in_a_bits_address ^ 29'h10024000; // @[Parameters.scala 137:31]
  wire [29:0] _T_46 = {1'b0,$signed(_T_45)}; // @[Parameters.scala 137:49]
  wire [29:0] _T_48 = $signed(_T_46) & -30'sh1000; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 30'sh0; // @[Parameters.scala 137:67]
  wire  _T_59 = 3'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_60 = _source_ok_T & _T_59; // @[Mux.scala 27:73]
  wire  _T_76 = _T_60 & _T_49; // @[Monitor.scala 83:78]
  wire  _T_90 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_94 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_95 = _T_94 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_99 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_103 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_164 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_177 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_192 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
  wire  _T_200 = _T_192 & _T_49; // @[Parameters.scala 670:56]
  wire  _T_211 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_215 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_223 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_245 = source_ok & _T_200; // @[Monitor.scala 115:71]
  wire  _T_263 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_299 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_300 = io_in_a_bits_mask & _T_299; // @[Monitor.scala 127:31]
  wire  _T_301 = _T_300 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_305 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_334 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_342 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_371 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_379 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_408 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_420 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  _T_424 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_428 = io_in_d_bits_size >= 3'h2; // @[Monitor.scala 312:27]
  wire  _T_444 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_472 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_501 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_518 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_536 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [3:0] a_first_beats1_decode = is_aligned_mask[5:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] a_first_counter; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1 = a_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [28:0] address; // @[Monitor.scala 388:22]
  wire  _T_566 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_567 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_571 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_575 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_579 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_583 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
  wire [3:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [3:0] d_first_counter; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1 = d_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_590 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_591 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_599 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_603 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [11:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [3:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1_1 = a_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  reg [3:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_1 = d_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [11:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _GEN_76 = {{4'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_76 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_617 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_620 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [34:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [34:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_622 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_624 = ~_T_622[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [34:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_628 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_630 = ~_T_424; // @[Monitor.scala 671:74]
  wire  _T_631 = io_in_d_valid & d_first_1 & ~_T_424; // @[Monitor.scala 671:71]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [3:0] _GEN_22 = _d_first_T & d_first_1 & _T_630 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_23 = _d_first_T & d_first_1 & _T_630 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_617 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_641 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_643 = _T_641[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_648 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_649 = io_in_d_bits_opcode == _GEN_32 | _T_648; // @[Monitor.scala 685:77]
  wire  _T_653 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_660 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_661 = io_in_d_bits_opcode == _GEN_48 | _T_660; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_665 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_675 = _T_628 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_630; // @[Monitor.scala 694:116]
  wire  _T_677 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set = _GEN_16[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_22[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_19[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_23[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [11:0] a_sizes_set = _GEN_20[11:0];
  wire [11:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [11:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_686 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [2:0] inflight_1; // @[Monitor.scala 723:35]
  reg [11:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [3:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_2 = d_first_counter_2 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 4'h0; // @[Edges.scala 230:25]
  wire [11:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [15:0] _GEN_87 = {{4'd0}, _c_size_lookup_T_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_87 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_712 = io_in_d_valid & d_first_2 & _T_424; // @[Monitor.scala 779:71]
  wire [3:0] _GEN_67 = _d_first_T & d_first_2 & _T_424 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 783:90 784:21]
  wire [46:0] _GEN_68 = _d_first_T & d_first_2 & _T_424 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 785:21]
  wire [2:0] _T_720 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_730 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [2:0] d_clr_1 = _GEN_67[2:0];
  wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [2:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [11:0] d_opcodes_clr_1 = _GEN_68[11:0];
  wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [11:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_750 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 4'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 4'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 12'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 4'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 4'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 3'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 12'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 4'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_164 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_164) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_200 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_200) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_301 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_301) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_334 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_334) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_371 & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~_T_371) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_408 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_408) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_420 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_420) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at SPI.scala:61:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at SPI.scala:61:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at SPI.scala:61:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at SPI.scala:61:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at SPI.scala:61:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at SPI.scala:61:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at SPI.scala:61:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at SPI.scala:61:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at SPI.scala:61:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_501 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_501 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at SPI.scala:61:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_518 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_518 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at SPI.scala:61:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_536 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_536 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at SPI.scala:61:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_567 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_567) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_571 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_571) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_575 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_575) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_579 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_579) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_583 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_583) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_591 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_591) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at SPI.scala:61:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_599 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_599) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at SPI.scala:61:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_603 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_603) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at SPI.scala:61:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_624 & (_T_620 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_620 & ~reset & ~_T_624) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_643 & (_T_631 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & _T_2 & ~_T_643) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SPI.scala:61:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_649 & (_T_631 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & same_cycle_resp & _T_2 & ~_T_649) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at SPI.scala:61:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_653 & (_T_631 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & same_cycle_resp & _T_2 & ~_T_653) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:61:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_661 & (_T_631 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & ~same_cycle_resp & _T_2 & ~_T_661) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at SPI.scala:61:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_665 & (_T_631 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & ~same_cycle_resp & _T_2 & ~_T_665) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:61:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_677 & (_T_675 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_675 & _T_2 & ~_T_677) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_686 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_686) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_720[0] & (_T_712 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_712 & _T_2 & ~_T_720[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SPI.scala:61:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_730 & (_T_712 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_712 & _T_2 & ~_T_730) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:61:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_750 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_750) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at SPI.scala:61:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[28:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[2:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[1:0];
  _RAND_10 = {1{`RANDOM}};
  inflight = _RAND_10[2:0];
  _RAND_11 = {1{`RANDOM}};
  inflight_opcodes = _RAND_11[11:0];
  _RAND_12 = {1{`RANDOM}};
  inflight_sizes = _RAND_12[11:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[3:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[3:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  inflight_1 = _RAND_16[2:0];
  _RAND_17 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_17[11:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[3:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLFragmenter_8(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [28:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output [31:0] auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [1:0]  auto_out_a_bits_size,
  output [6:0]  auto_out_a_bits_source,
  output [28:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_size,
  input  [6:0]  auto_out_d_bits_source,
  input  [31:0] auto_out_d_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  repeater_clock; // @[Fragmenter.scala 262:30]
  wire  repeater_reset; // @[Fragmenter.scala 262:30]
  wire  repeater_io_repeat; // @[Fragmenter.scala 262:30]
  wire  repeater_io_full; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
  wire [28:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
  wire [28:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
  reg [3:0] acknum; // @[Fragmenter.scala 189:29]
  reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
  reg  dToggle; // @[Fragmenter.scala 191:30]
  wire [3:0] dFragnum = auto_out_d_bits_source[3:0]; // @[Fragmenter.scala 192:41]
  wire  dFirst = acknum == 4'h0; // @[Fragmenter.scala 193:29]
  wire  dLast = dFragnum == 4'h0; // @[Fragmenter.scala 194:30]
  wire [3:0] _dsizeOH_T = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 64:12]
  wire [2:0] dsizeOH = _dsizeOH_T[2:0]; // @[OneHot.scala 64:27]
  wire [4:0] _dsizeOH1_T_1 = 5'h3 << auto_out_d_bits_size; // @[package.scala 234:77]
  wire [1:0] dsizeOH1 = ~_dsizeOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  dHasData = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  _T_5 = ~reset; // @[Fragmenter.scala 202:16]
  wire  ack_decrement = dHasData | dsizeOH[2]; // @[Fragmenter.scala 204:32]
  wire [5:0] _dFirst_size_T = {dFragnum, 2'h0}; // @[Fragmenter.scala 206:47]
  wire [5:0] _GEN_7 = {{4'd0}, dsizeOH1}; // @[Fragmenter.scala 206:69]
  wire [5:0] _dFirst_size_T_1 = _dFirst_size_T | _GEN_7; // @[Fragmenter.scala 206:69]
  wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala 232:35]
  wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
  wire [6:0] _dFirst_size_T_4 = {1'h0,_dFirst_size_T_1}; // @[Cat.scala 31:58]
  wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
  wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
  wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
  wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
  wire [3:0] _GEN_8 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
  wire [3:0] _dFirst_size_T_8 = _GEN_8 | dFirst_size_lo; // @[OneHot.scala 32:28]
  wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
  wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
  wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
  wire  drop = ~dHasData & ~dLast; // @[Fragmenter.scala 222:30]
  wire  bundleOut_0_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  wire  _T_7 = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
  wire [3:0] _GEN_9 = {{3'd0}, ack_decrement}; // @[Fragmenter.scala 209:55]
  wire [3:0] _acknum_T_1 = acknum - _GEN_9; // @[Fragmenter.scala 209:55]
  wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h2 ? 3'h2 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
  wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
  wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
  wire [8:0] _aFragOH1_T_1 = 9'h3 << aFrag; // @[package.scala 234:77]
  wire [1:0] aFragOH1 = ~_aFragOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  aHasData = ~repeater_io_deq_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] gennum; // @[Fragmenter.scala 291:29]
  wire  aFirst = gennum == 4'h0; // @[Fragmenter.scala 292:29]
  wire [3:0] _old_gennum1_T_2 = gennum - 4'h1; // @[Fragmenter.scala 293:79]
  wire [3:0] old_gennum1 = aFirst ? aOrigOH1[5:2] : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
  wire [3:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
  wire [3:0] new_gennum = ~_new_gennum_T; // @[Fragmenter.scala 294:26]
  reg  aToggle_r; // @[Reg.scala 16:16]
  wire  _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
  wire  aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
  wire  bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  wire  _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
  wire  _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala 302:31]
  wire [5:0] _bundleOut_0_a_bits_address_T = {old_gennum1, 2'h0}; // @[Fragmenter.scala 304:65]
  wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
  wire [5:0] _bundleOut_0_a_bits_address_T_2 = _bundleOut_0_a_bits_address_T | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
  wire [5:0] _GEN_10 = {{4'd0}, aFragOH1}; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_10; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_4 = _bundleOut_0_a_bits_address_T_3 | 6'h3; // @[Fragmenter.scala 304:111]
  wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_4; // @[Fragmenter.scala 304:51]
  wire [28:0] _GEN_11 = {{23'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
  wire [2:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aToggle}; // @[Cat.scala 31:58]
  wire  _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
  TLMonitor_17 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  Repeater repeater ( // @[Fragmenter.scala 262:30]
    .clock(repeater_clock),
    .reset(repeater_reset),
    .io_repeat(repeater_io_repeat),
    .io_full(repeater_io_full),
    .io_enq_ready(repeater_io_enq_ready),
    .io_enq_valid(repeater_io_enq_valid),
    .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
    .io_enq_bits_param(repeater_io_enq_bits_param),
    .io_enq_bits_size(repeater_io_enq_bits_size),
    .io_enq_bits_source(repeater_io_enq_bits_source),
    .io_enq_bits_address(repeater_io_enq_bits_address),
    .io_enq_bits_mask(repeater_io_enq_bits_mask),
    .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
    .io_deq_ready(repeater_io_deq_ready),
    .io_deq_valid(repeater_io_deq_valid),
    .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
    .io_deq_bits_param(repeater_io_deq_bits_param),
    .io_deq_bits_size(repeater_io_deq_bits_size),
    .io_deq_bits_source(repeater_io_deq_bits_source),
    .io_deq_bits_address(repeater_io_deq_bits_address),
    .io_deq_bits_mask(repeater_io_deq_bits_mask),
    .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
  );
  assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign auto_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign auto_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_size = aFrag[1:0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
  assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,new_gennum}; // @[Cat.scala 31:58]
  assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_11; // @[Fragmenter.scala 304:49]
  assign auto_out_a_bits_mask = repeater_io_full ? 4'hf : auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = repeater_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign repeater_clock = clock;
  assign repeater_reset = reset;
  assign repeater_io_repeat = ~aHasData & new_gennum != 4'h0; // @[Fragmenter.scala 302:41]
  assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  always @(posedge clock) begin
    if (reset) begin // @[Fragmenter.scala 189:29]
      acknum <= 4'h0; // @[Fragmenter.scala 189:29]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 209:24]
        acknum <= dFragnum;
      end else begin
        acknum <= _acknum_T_1;
      end
    end
    if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
      end
    end
    if (reset) begin // @[Fragmenter.scala 191:30]
      dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dToggle <= auto_out_d_bits_source[4]; // @[Fragmenter.scala 212:21]
      end
    end
    if (reset) begin // @[Fragmenter.scala 291:29]
      gennum <= 4'h0; // @[Fragmenter.scala 291:29]
    end else if (_T_8) begin // @[Fragmenter.scala 300:29]
      gennum <= new_gennum; // @[Fragmenter.scala 300:38]
    end
    if (aFirst) begin // @[Reg.scala 17:18]
      aToggle_r <= dToggle; // @[Reg.scala 17:22]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~repeater_io_full | _repeater_io_repeat_T) & _T_5) begin
          $fatal; // @[Fragmenter.scala 309:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(~repeater_io_full | _repeater_io_repeat_T)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Fragmenter.scala:309 assert (!repeater.io.full || !aHasData)\n"
            ); // @[Fragmenter.scala 309:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_9 | repeater_io_deq_bits_mask == 4'hf) & _T_5) begin
          $fatal; // @[Fragmenter.scala 312:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask == 4'hf)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
            ); // @[Fragmenter.scala 312:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  acknum = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  dOrig = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  dToggle = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  gennum = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  aToggle_r = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLInterconnectCoupler_12(
  input         clock,
  input         reset,
  input         auto_control_xing_out_a_ready,
  output        auto_control_xing_out_a_valid,
  output [2:0]  auto_control_xing_out_a_bits_opcode,
  output [2:0]  auto_control_xing_out_a_bits_param,
  output [1:0]  auto_control_xing_out_a_bits_size,
  output [6:0]  auto_control_xing_out_a_bits_source,
  output [28:0] auto_control_xing_out_a_bits_address,
  output [3:0]  auto_control_xing_out_a_bits_mask,
  output [31:0] auto_control_xing_out_a_bits_data,
  output        auto_control_xing_out_a_bits_corrupt,
  output        auto_control_xing_out_d_ready,
  input         auto_control_xing_out_d_valid,
  input  [2:0]  auto_control_xing_out_d_bits_opcode,
  input  [1:0]  auto_control_xing_out_d_bits_size,
  input  [6:0]  auto_control_xing_out_d_bits_source,
  input  [31:0] auto_control_xing_out_d_bits_data,
  output        auto_tl_in_a_ready,
  input         auto_tl_in_a_valid,
  input  [2:0]  auto_tl_in_a_bits_opcode,
  input  [2:0]  auto_tl_in_a_bits_param,
  input  [2:0]  auto_tl_in_a_bits_size,
  input  [1:0]  auto_tl_in_a_bits_source,
  input  [28:0] auto_tl_in_a_bits_address,
  input  [3:0]  auto_tl_in_a_bits_mask,
  input  [31:0] auto_tl_in_a_bits_data,
  input         auto_tl_in_a_bits_corrupt,
  input         auto_tl_in_d_ready,
  output        auto_tl_in_d_valid,
  output [2:0]  auto_tl_in_d_bits_opcode,
  output [2:0]  auto_tl_in_d_bits_size,
  output [1:0]  auto_tl_in_d_bits_source,
  output [31:0] auto_tl_in_d_bits_data
);
  wire  fragmenter_clock; // @[Fragmenter.scala 333:34]
  wire  fragmenter_reset; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [28:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [28:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
  TLFragmenter_8 fragmenter ( // @[Fragmenter.scala 333:34]
    .clock(fragmenter_clock),
    .reset(fragmenter_reset),
    .auto_in_a_ready(fragmenter_auto_in_a_ready),
    .auto_in_a_valid(fragmenter_auto_in_a_valid),
    .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
    .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
    .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
    .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
    .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
    .auto_in_a_bits_data(fragmenter_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
    .auto_in_d_ready(fragmenter_auto_in_d_ready),
    .auto_in_d_valid(fragmenter_auto_in_d_valid),
    .auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
    .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
    .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
    .auto_out_a_ready(fragmenter_auto_out_a_ready),
    .auto_out_a_valid(fragmenter_auto_out_a_valid),
    .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
    .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
    .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
    .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
    .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
    .auto_out_a_bits_data(fragmenter_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
    .auto_out_d_ready(fragmenter_auto_out_d_ready),
    .auto_out_d_valid(fragmenter_auto_out_d_valid),
    .auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
    .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
    .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
  );
  assign auto_control_xing_out_a_valid = fragmenter_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_data = fragmenter_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_d_ready = fragmenter_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_in_a_ready = fragmenter_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_valid = fragmenter_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_size = fragmenter_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_source = fragmenter_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_data = fragmenter_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign fragmenter_clock = clock;
  assign fragmenter_reset = reset;
  assign fragmenter_auto_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_data = auto_tl_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_out_a_ready = auto_control_xing_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_valid = auto_control_xing_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_opcode = auto_control_xing_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_size = auto_control_xing_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_source = auto_control_xing_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_data = auto_control_xing_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
endmodule
module TLMonitor_18(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [28:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [2:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
  wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
  wire [28:0] _GEN_71 = {{23'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [28:0] _T_45 = io_in_a_bits_address ^ 29'h10012000; // @[Parameters.scala 137:31]
  wire [29:0] _T_46 = {1'b0,$signed(_T_45)}; // @[Parameters.scala 137:49]
  wire [29:0] _T_48 = $signed(_T_46) & -30'sh1000; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 30'sh0; // @[Parameters.scala 137:67]
  wire  _T_59 = 3'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_60 = _source_ok_T & _T_59; // @[Mux.scala 27:73]
  wire  _T_76 = _T_60 & _T_49; // @[Monitor.scala 83:78]
  wire  _T_90 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_94 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_95 = _T_94 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_99 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_103 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_164 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_177 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_192 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
  wire  _T_200 = _T_192 & _T_49; // @[Parameters.scala 670:56]
  wire  _T_211 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_215 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_223 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_245 = source_ok & _T_200; // @[Monitor.scala 115:71]
  wire  _T_263 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_299 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_300 = io_in_a_bits_mask & _T_299; // @[Monitor.scala 127:31]
  wire  _T_301 = _T_300 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_305 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_334 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_342 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_371 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_379 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_408 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_420 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  _T_424 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_428 = io_in_d_bits_size >= 3'h2; // @[Monitor.scala 312:27]
  wire  _T_444 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_472 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_501 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_518 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_536 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [3:0] a_first_beats1_decode = is_aligned_mask[5:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] a_first_counter; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1 = a_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [28:0] address; // @[Monitor.scala 388:22]
  wire  _T_566 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_567 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_571 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_575 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_579 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_583 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
  wire [3:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [3:0] d_first_counter; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1 = d_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_590 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_591 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_599 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_603 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [11:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [3:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1_1 = a_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  reg [3:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_1 = d_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [11:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _GEN_76 = {{4'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_76 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_617 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_620 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [34:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [34:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_622 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_624 = ~_T_622[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [34:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_628 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_630 = ~_T_424; // @[Monitor.scala 671:74]
  wire  _T_631 = io_in_d_valid & d_first_1 & ~_T_424; // @[Monitor.scala 671:71]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [3:0] _GEN_22 = _d_first_T & d_first_1 & _T_630 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_23 = _d_first_T & d_first_1 & _T_630 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_617 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_641 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_643 = _T_641[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_648 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_649 = io_in_d_bits_opcode == _GEN_32 | _T_648; // @[Monitor.scala 685:77]
  wire  _T_653 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_660 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_661 = io_in_d_bits_opcode == _GEN_48 | _T_660; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_665 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_675 = _T_628 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_630; // @[Monitor.scala 694:116]
  wire  _T_677 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set = _GEN_16[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_22[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_19[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_23[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [11:0] a_sizes_set = _GEN_20[11:0];
  wire [11:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [11:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_686 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [2:0] inflight_1; // @[Monitor.scala 723:35]
  reg [11:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [3:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_2 = d_first_counter_2 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 4'h0; // @[Edges.scala 230:25]
  wire [11:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [15:0] _GEN_87 = {{4'd0}, _c_size_lookup_T_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_87 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_712 = io_in_d_valid & d_first_2 & _T_424; // @[Monitor.scala 779:71]
  wire [3:0] _GEN_67 = _d_first_T & d_first_2 & _T_424 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 783:90 784:21]
  wire [46:0] _GEN_68 = _d_first_T & d_first_2 & _T_424 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 785:21]
  wire [2:0] _T_720 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_730 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [2:0] d_clr_1 = _GEN_67[2:0];
  wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [2:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [11:0] d_opcodes_clr_1 = _GEN_68[11:0];
  wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [11:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_750 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 4'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 4'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 12'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 4'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 4'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 3'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 12'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 4'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_164 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_164) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_200 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_200) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_301 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_301) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_334 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_334) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_371 & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~_T_371) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_408 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_408) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_420 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_420) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at GPIO.scala:307:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at GPIO.scala:307:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at GPIO.scala:307:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at GPIO.scala:307:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at GPIO.scala:307:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at GPIO.scala:307:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at GPIO.scala:307:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at GPIO.scala:307:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at GPIO.scala:307:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_501 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_501 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at GPIO.scala:307:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_518 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_518 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at GPIO.scala:307:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_536 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_536 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at GPIO.scala:307:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_567 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_567) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_571 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_571) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_575 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_575) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_579 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_579) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_583 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_583) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_591 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_591) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at GPIO.scala:307:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_599 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_599) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at GPIO.scala:307:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_603 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_603) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at GPIO.scala:307:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_624 & (_T_620 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_620 & ~reset & ~_T_624) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_643 & (_T_631 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & _T_2 & ~_T_643) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at GPIO.scala:307:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_649 & (_T_631 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & same_cycle_resp & _T_2 & ~_T_649) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at GPIO.scala:307:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_653 & (_T_631 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & same_cycle_resp & _T_2 & ~_T_653) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at GPIO.scala:307:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_661 & (_T_631 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & ~same_cycle_resp & _T_2 & ~_T_661) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at GPIO.scala:307:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_665 & (_T_631 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & ~same_cycle_resp & _T_2 & ~_T_665) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at GPIO.scala:307:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_677 & (_T_675 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_675 & _T_2 & ~_T_677) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_686 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_686) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_720[0] & (_T_712 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_712 & _T_2 & ~_T_720[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at GPIO.scala:307:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_730 & (_T_712 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_712 & _T_2 & ~_T_730) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at GPIO.scala:307:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_750 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_750) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at GPIO.scala:307:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[28:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[2:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[1:0];
  _RAND_10 = {1{`RANDOM}};
  inflight = _RAND_10[2:0];
  _RAND_11 = {1{`RANDOM}};
  inflight_opcodes = _RAND_11[11:0];
  _RAND_12 = {1{`RANDOM}};
  inflight_sizes = _RAND_12[11:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[3:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[3:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  inflight_1 = _RAND_16[2:0];
  _RAND_17 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_17[11:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[3:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLFragmenter_9(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [28:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output [31:0] auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [1:0]  auto_out_a_bits_size,
  output [6:0]  auto_out_a_bits_source,
  output [28:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_size,
  input  [6:0]  auto_out_d_bits_source,
  input  [31:0] auto_out_d_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  repeater_clock; // @[Fragmenter.scala 262:30]
  wire  repeater_reset; // @[Fragmenter.scala 262:30]
  wire  repeater_io_repeat; // @[Fragmenter.scala 262:30]
  wire  repeater_io_full; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
  wire [28:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
  wire [28:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
  reg [3:0] acknum; // @[Fragmenter.scala 189:29]
  reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
  reg  dToggle; // @[Fragmenter.scala 191:30]
  wire [3:0] dFragnum = auto_out_d_bits_source[3:0]; // @[Fragmenter.scala 192:41]
  wire  dFirst = acknum == 4'h0; // @[Fragmenter.scala 193:29]
  wire  dLast = dFragnum == 4'h0; // @[Fragmenter.scala 194:30]
  wire [3:0] _dsizeOH_T = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 64:12]
  wire [2:0] dsizeOH = _dsizeOH_T[2:0]; // @[OneHot.scala 64:27]
  wire [4:0] _dsizeOH1_T_1 = 5'h3 << auto_out_d_bits_size; // @[package.scala 234:77]
  wire [1:0] dsizeOH1 = ~_dsizeOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  dHasData = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  _T_5 = ~reset; // @[Fragmenter.scala 202:16]
  wire  ack_decrement = dHasData | dsizeOH[2]; // @[Fragmenter.scala 204:32]
  wire [5:0] _dFirst_size_T = {dFragnum, 2'h0}; // @[Fragmenter.scala 206:47]
  wire [5:0] _GEN_7 = {{4'd0}, dsizeOH1}; // @[Fragmenter.scala 206:69]
  wire [5:0] _dFirst_size_T_1 = _dFirst_size_T | _GEN_7; // @[Fragmenter.scala 206:69]
  wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala 232:35]
  wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
  wire [6:0] _dFirst_size_T_4 = {1'h0,_dFirst_size_T_1}; // @[Cat.scala 31:58]
  wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
  wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
  wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
  wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
  wire [3:0] _GEN_8 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
  wire [3:0] _dFirst_size_T_8 = _GEN_8 | dFirst_size_lo; // @[OneHot.scala 32:28]
  wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
  wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
  wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
  wire  drop = ~dHasData & ~dLast; // @[Fragmenter.scala 222:30]
  wire  bundleOut_0_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  wire  _T_7 = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
  wire [3:0] _GEN_9 = {{3'd0}, ack_decrement}; // @[Fragmenter.scala 209:55]
  wire [3:0] _acknum_T_1 = acknum - _GEN_9; // @[Fragmenter.scala 209:55]
  wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h2 ? 3'h2 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
  wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
  wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
  wire [8:0] _aFragOH1_T_1 = 9'h3 << aFrag; // @[package.scala 234:77]
  wire [1:0] aFragOH1 = ~_aFragOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  aHasData = ~repeater_io_deq_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] gennum; // @[Fragmenter.scala 291:29]
  wire  aFirst = gennum == 4'h0; // @[Fragmenter.scala 292:29]
  wire [3:0] _old_gennum1_T_2 = gennum - 4'h1; // @[Fragmenter.scala 293:79]
  wire [3:0] old_gennum1 = aFirst ? aOrigOH1[5:2] : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
  wire [3:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
  wire [3:0] new_gennum = ~_new_gennum_T; // @[Fragmenter.scala 294:26]
  reg  aToggle_r; // @[Reg.scala 16:16]
  wire  _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
  wire  aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
  wire  bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  wire  _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
  wire  _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala 302:31]
  wire [5:0] _bundleOut_0_a_bits_address_T = {old_gennum1, 2'h0}; // @[Fragmenter.scala 304:65]
  wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
  wire [5:0] _bundleOut_0_a_bits_address_T_2 = _bundleOut_0_a_bits_address_T | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
  wire [5:0] _GEN_10 = {{4'd0}, aFragOH1}; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_10; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_4 = _bundleOut_0_a_bits_address_T_3 | 6'h3; // @[Fragmenter.scala 304:111]
  wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_4; // @[Fragmenter.scala 304:51]
  wire [28:0] _GEN_11 = {{23'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
  wire [2:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aToggle}; // @[Cat.scala 31:58]
  wire  _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
  TLMonitor_18 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  Repeater repeater ( // @[Fragmenter.scala 262:30]
    .clock(repeater_clock),
    .reset(repeater_reset),
    .io_repeat(repeater_io_repeat),
    .io_full(repeater_io_full),
    .io_enq_ready(repeater_io_enq_ready),
    .io_enq_valid(repeater_io_enq_valid),
    .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
    .io_enq_bits_param(repeater_io_enq_bits_param),
    .io_enq_bits_size(repeater_io_enq_bits_size),
    .io_enq_bits_source(repeater_io_enq_bits_source),
    .io_enq_bits_address(repeater_io_enq_bits_address),
    .io_enq_bits_mask(repeater_io_enq_bits_mask),
    .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
    .io_deq_ready(repeater_io_deq_ready),
    .io_deq_valid(repeater_io_deq_valid),
    .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
    .io_deq_bits_param(repeater_io_deq_bits_param),
    .io_deq_bits_size(repeater_io_deq_bits_size),
    .io_deq_bits_source(repeater_io_deq_bits_source),
    .io_deq_bits_address(repeater_io_deq_bits_address),
    .io_deq_bits_mask(repeater_io_deq_bits_mask),
    .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
  );
  assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign auto_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign auto_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_size = aFrag[1:0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
  assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,new_gennum}; // @[Cat.scala 31:58]
  assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_11; // @[Fragmenter.scala 304:49]
  assign auto_out_a_bits_mask = repeater_io_full ? 4'hf : auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = repeater_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign repeater_clock = clock;
  assign repeater_reset = reset;
  assign repeater_io_repeat = ~aHasData & new_gennum != 4'h0; // @[Fragmenter.scala 302:41]
  assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  always @(posedge clock) begin
    if (reset) begin // @[Fragmenter.scala 189:29]
      acknum <= 4'h0; // @[Fragmenter.scala 189:29]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 209:24]
        acknum <= dFragnum;
      end else begin
        acknum <= _acknum_T_1;
      end
    end
    if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
      end
    end
    if (reset) begin // @[Fragmenter.scala 191:30]
      dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dToggle <= auto_out_d_bits_source[4]; // @[Fragmenter.scala 212:21]
      end
    end
    if (reset) begin // @[Fragmenter.scala 291:29]
      gennum <= 4'h0; // @[Fragmenter.scala 291:29]
    end else if (_T_8) begin // @[Fragmenter.scala 300:29]
      gennum <= new_gennum; // @[Fragmenter.scala 300:38]
    end
    if (aFirst) begin // @[Reg.scala 17:18]
      aToggle_r <= dToggle; // @[Reg.scala 17:22]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~repeater_io_full | _repeater_io_repeat_T) & _T_5) begin
          $fatal; // @[Fragmenter.scala 309:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(~repeater_io_full | _repeater_io_repeat_T)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Fragmenter.scala:309 assert (!repeater.io.full || !aHasData)\n"
            ); // @[Fragmenter.scala 309:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_9 | repeater_io_deq_bits_mask == 4'hf) & _T_5) begin
          $fatal; // @[Fragmenter.scala 312:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask == 4'hf)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
            ); // @[Fragmenter.scala 312:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  acknum = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  dOrig = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  dToggle = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  gennum = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  aToggle_r = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLInterconnectCoupler_13(
  input         clock,
  input         reset,
  input         auto_control_xing_out_a_ready,
  output        auto_control_xing_out_a_valid,
  output [2:0]  auto_control_xing_out_a_bits_opcode,
  output [2:0]  auto_control_xing_out_a_bits_param,
  output [1:0]  auto_control_xing_out_a_bits_size,
  output [6:0]  auto_control_xing_out_a_bits_source,
  output [28:0] auto_control_xing_out_a_bits_address,
  output [3:0]  auto_control_xing_out_a_bits_mask,
  output [31:0] auto_control_xing_out_a_bits_data,
  output        auto_control_xing_out_a_bits_corrupt,
  output        auto_control_xing_out_d_ready,
  input         auto_control_xing_out_d_valid,
  input  [2:0]  auto_control_xing_out_d_bits_opcode,
  input  [1:0]  auto_control_xing_out_d_bits_size,
  input  [6:0]  auto_control_xing_out_d_bits_source,
  input  [31:0] auto_control_xing_out_d_bits_data,
  output        auto_tl_in_a_ready,
  input         auto_tl_in_a_valid,
  input  [2:0]  auto_tl_in_a_bits_opcode,
  input  [2:0]  auto_tl_in_a_bits_param,
  input  [2:0]  auto_tl_in_a_bits_size,
  input  [1:0]  auto_tl_in_a_bits_source,
  input  [28:0] auto_tl_in_a_bits_address,
  input  [3:0]  auto_tl_in_a_bits_mask,
  input  [31:0] auto_tl_in_a_bits_data,
  input         auto_tl_in_a_bits_corrupt,
  input         auto_tl_in_d_ready,
  output        auto_tl_in_d_valid,
  output [2:0]  auto_tl_in_d_bits_opcode,
  output [2:0]  auto_tl_in_d_bits_size,
  output [1:0]  auto_tl_in_d_bits_source,
  output [31:0] auto_tl_in_d_bits_data
);
  wire  fragmenter_clock; // @[Fragmenter.scala 333:34]
  wire  fragmenter_reset; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [28:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [28:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
  TLFragmenter_9 fragmenter ( // @[Fragmenter.scala 333:34]
    .clock(fragmenter_clock),
    .reset(fragmenter_reset),
    .auto_in_a_ready(fragmenter_auto_in_a_ready),
    .auto_in_a_valid(fragmenter_auto_in_a_valid),
    .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
    .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
    .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
    .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
    .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
    .auto_in_a_bits_data(fragmenter_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
    .auto_in_d_ready(fragmenter_auto_in_d_ready),
    .auto_in_d_valid(fragmenter_auto_in_d_valid),
    .auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
    .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
    .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
    .auto_out_a_ready(fragmenter_auto_out_a_ready),
    .auto_out_a_valid(fragmenter_auto_out_a_valid),
    .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
    .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
    .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
    .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
    .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
    .auto_out_a_bits_data(fragmenter_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
    .auto_out_d_ready(fragmenter_auto_out_d_ready),
    .auto_out_d_valid(fragmenter_auto_out_d_valid),
    .auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
    .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
    .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
  );
  assign auto_control_xing_out_a_valid = fragmenter_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_data = fragmenter_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_d_ready = fragmenter_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_in_a_ready = fragmenter_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_valid = fragmenter_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_size = fragmenter_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_source = fragmenter_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_data = fragmenter_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign fragmenter_clock = clock;
  assign fragmenter_reset = reset;
  assign fragmenter_auto_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_data = auto_tl_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_out_a_ready = auto_control_xing_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_valid = auto_control_xing_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_opcode = auto_control_xing_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_size = auto_control_xing_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_source = auto_control_xing_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_data = auto_control_xing_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
endmodule
module TLMonitor_19(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [28:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [2:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
  wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
  wire [28:0] _GEN_71 = {{23'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [28:0] _T_45 = io_in_a_bits_address ^ 29'h10015000; // @[Parameters.scala 137:31]
  wire [29:0] _T_46 = {1'b0,$signed(_T_45)}; // @[Parameters.scala 137:49]
  wire [29:0] _T_48 = $signed(_T_46) & -30'sh1000; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 30'sh0; // @[Parameters.scala 137:67]
  wire  _T_59 = 3'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_60 = _source_ok_T & _T_59; // @[Mux.scala 27:73]
  wire  _T_76 = _T_60 & _T_49; // @[Monitor.scala 83:78]
  wire  _T_90 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_94 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_95 = _T_94 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_99 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_103 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_164 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_177 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_192 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
  wire  _T_200 = _T_192 & _T_49; // @[Parameters.scala 670:56]
  wire  _T_211 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_215 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_223 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_245 = source_ok & _T_200; // @[Monitor.scala 115:71]
  wire  _T_263 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_299 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_300 = io_in_a_bits_mask & _T_299; // @[Monitor.scala 127:31]
  wire  _T_301 = _T_300 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_305 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_334 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_342 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_371 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_379 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_408 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_420 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  _T_424 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_428 = io_in_d_bits_size >= 3'h2; // @[Monitor.scala 312:27]
  wire  _T_444 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_472 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_501 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_518 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_536 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [3:0] a_first_beats1_decode = is_aligned_mask[5:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] a_first_counter; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1 = a_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [28:0] address; // @[Monitor.scala 388:22]
  wire  _T_566 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_567 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_571 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_575 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_579 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_583 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
  wire [3:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [3:0] d_first_counter; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1 = d_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_590 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_591 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_599 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_603 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [11:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [3:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1_1 = a_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  reg [3:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_1 = d_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [11:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _GEN_76 = {{4'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_76 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_617 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_620 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [34:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [34:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_622 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_624 = ~_T_622[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [34:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_628 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_630 = ~_T_424; // @[Monitor.scala 671:74]
  wire  _T_631 = io_in_d_valid & d_first_1 & ~_T_424; // @[Monitor.scala 671:71]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [3:0] _GEN_22 = _d_first_T & d_first_1 & _T_630 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_23 = _d_first_T & d_first_1 & _T_630 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_617 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_641 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_643 = _T_641[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_648 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_649 = io_in_d_bits_opcode == _GEN_32 | _T_648; // @[Monitor.scala 685:77]
  wire  _T_653 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_660 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_661 = io_in_d_bits_opcode == _GEN_48 | _T_660; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_665 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_675 = _T_628 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_630; // @[Monitor.scala 694:116]
  wire  _T_677 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set = _GEN_16[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_22[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_19[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_23[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [11:0] a_sizes_set = _GEN_20[11:0];
  wire [11:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [11:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_686 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [2:0] inflight_1; // @[Monitor.scala 723:35]
  reg [11:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [3:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_2 = d_first_counter_2 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 4'h0; // @[Edges.scala 230:25]
  wire [11:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [15:0] _GEN_87 = {{4'd0}, _c_size_lookup_T_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_87 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_712 = io_in_d_valid & d_first_2 & _T_424; // @[Monitor.scala 779:71]
  wire [3:0] _GEN_67 = _d_first_T & d_first_2 & _T_424 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 783:90 784:21]
  wire [46:0] _GEN_68 = _d_first_T & d_first_2 & _T_424 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 785:21]
  wire [2:0] _T_720 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_730 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [2:0] d_clr_1 = _GEN_67[2:0];
  wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [2:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [11:0] d_opcodes_clr_1 = _GEN_68[11:0];
  wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [11:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_750 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 4'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 4'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 12'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 4'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 4'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 3'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 12'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 4'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_164 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_164) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_200 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_200) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_301 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_301) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_334 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_334) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_371 & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~_T_371) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_408 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_408) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_420 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_420) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_501 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_501 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_518 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_518 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_536 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_536 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_567 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_567) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_571 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_571) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_575 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_575) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_579 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_579) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_583 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_583) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_591 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_591) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_599 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_599) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_603 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_603) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_624 & (_T_620 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_620 & ~reset & ~_T_624) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_643 & (_T_631 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & _T_2 & ~_T_643) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_649 & (_T_631 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & same_cycle_resp & _T_2 & ~_T_649) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_653 & (_T_631 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & same_cycle_resp & _T_2 & ~_T_653) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_661 & (_T_631 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & ~same_cycle_resp & _T_2 & ~_T_661) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_665 & (_T_631 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & ~same_cycle_resp & _T_2 & ~_T_665) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_677 & (_T_675 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_675 & _T_2 & ~_T_677) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_686 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_686) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_720[0] & (_T_712 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_712 & _T_2 & ~_T_720[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_730 & (_T_712 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_712 & _T_2 & ~_T_730) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_750 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_750) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[28:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[2:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[1:0];
  _RAND_10 = {1{`RANDOM}};
  inflight = _RAND_10[2:0];
  _RAND_11 = {1{`RANDOM}};
  inflight_opcodes = _RAND_11[11:0];
  _RAND_12 = {1{`RANDOM}};
  inflight_sizes = _RAND_12[11:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[3:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[3:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  inflight_1 = _RAND_16[2:0];
  _RAND_17 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_17[11:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[3:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLFragmenter_10(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [28:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output [31:0] auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [1:0]  auto_out_a_bits_size,
  output [6:0]  auto_out_a_bits_source,
  output [28:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_size,
  input  [6:0]  auto_out_d_bits_source,
  input  [31:0] auto_out_d_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  repeater_clock; // @[Fragmenter.scala 262:30]
  wire  repeater_reset; // @[Fragmenter.scala 262:30]
  wire  repeater_io_repeat; // @[Fragmenter.scala 262:30]
  wire  repeater_io_full; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
  wire [28:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
  wire [28:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
  reg [3:0] acknum; // @[Fragmenter.scala 189:29]
  reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
  reg  dToggle; // @[Fragmenter.scala 191:30]
  wire [3:0] dFragnum = auto_out_d_bits_source[3:0]; // @[Fragmenter.scala 192:41]
  wire  dFirst = acknum == 4'h0; // @[Fragmenter.scala 193:29]
  wire  dLast = dFragnum == 4'h0; // @[Fragmenter.scala 194:30]
  wire [3:0] _dsizeOH_T = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 64:12]
  wire [2:0] dsizeOH = _dsizeOH_T[2:0]; // @[OneHot.scala 64:27]
  wire [4:0] _dsizeOH1_T_1 = 5'h3 << auto_out_d_bits_size; // @[package.scala 234:77]
  wire [1:0] dsizeOH1 = ~_dsizeOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  dHasData = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  _T_5 = ~reset; // @[Fragmenter.scala 202:16]
  wire  ack_decrement = dHasData | dsizeOH[2]; // @[Fragmenter.scala 204:32]
  wire [5:0] _dFirst_size_T = {dFragnum, 2'h0}; // @[Fragmenter.scala 206:47]
  wire [5:0] _GEN_7 = {{4'd0}, dsizeOH1}; // @[Fragmenter.scala 206:69]
  wire [5:0] _dFirst_size_T_1 = _dFirst_size_T | _GEN_7; // @[Fragmenter.scala 206:69]
  wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala 232:35]
  wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
  wire [6:0] _dFirst_size_T_4 = {1'h0,_dFirst_size_T_1}; // @[Cat.scala 31:58]
  wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
  wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
  wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
  wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
  wire [3:0] _GEN_8 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
  wire [3:0] _dFirst_size_T_8 = _GEN_8 | dFirst_size_lo; // @[OneHot.scala 32:28]
  wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
  wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
  wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
  wire  drop = ~dHasData & ~dLast; // @[Fragmenter.scala 222:30]
  wire  bundleOut_0_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  wire  _T_7 = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
  wire [3:0] _GEN_9 = {{3'd0}, ack_decrement}; // @[Fragmenter.scala 209:55]
  wire [3:0] _acknum_T_1 = acknum - _GEN_9; // @[Fragmenter.scala 209:55]
  wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h2 ? 3'h2 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
  wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
  wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
  wire [8:0] _aFragOH1_T_1 = 9'h3 << aFrag; // @[package.scala 234:77]
  wire [1:0] aFragOH1 = ~_aFragOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  aHasData = ~repeater_io_deq_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] gennum; // @[Fragmenter.scala 291:29]
  wire  aFirst = gennum == 4'h0; // @[Fragmenter.scala 292:29]
  wire [3:0] _old_gennum1_T_2 = gennum - 4'h1; // @[Fragmenter.scala 293:79]
  wire [3:0] old_gennum1 = aFirst ? aOrigOH1[5:2] : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
  wire [3:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
  wire [3:0] new_gennum = ~_new_gennum_T; // @[Fragmenter.scala 294:26]
  reg  aToggle_r; // @[Reg.scala 16:16]
  wire  _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
  wire  aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
  wire  bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  wire  _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
  wire  _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala 302:31]
  wire [5:0] _bundleOut_0_a_bits_address_T = {old_gennum1, 2'h0}; // @[Fragmenter.scala 304:65]
  wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
  wire [5:0] _bundleOut_0_a_bits_address_T_2 = _bundleOut_0_a_bits_address_T | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
  wire [5:0] _GEN_10 = {{4'd0}, aFragOH1}; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_10; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_4 = _bundleOut_0_a_bits_address_T_3 | 6'h3; // @[Fragmenter.scala 304:111]
  wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_4; // @[Fragmenter.scala 304:51]
  wire [28:0] _GEN_11 = {{23'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
  wire [2:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aToggle}; // @[Cat.scala 31:58]
  wire  _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
  TLMonitor_19 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  Repeater repeater ( // @[Fragmenter.scala 262:30]
    .clock(repeater_clock),
    .reset(repeater_reset),
    .io_repeat(repeater_io_repeat),
    .io_full(repeater_io_full),
    .io_enq_ready(repeater_io_enq_ready),
    .io_enq_valid(repeater_io_enq_valid),
    .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
    .io_enq_bits_param(repeater_io_enq_bits_param),
    .io_enq_bits_size(repeater_io_enq_bits_size),
    .io_enq_bits_source(repeater_io_enq_bits_source),
    .io_enq_bits_address(repeater_io_enq_bits_address),
    .io_enq_bits_mask(repeater_io_enq_bits_mask),
    .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
    .io_deq_ready(repeater_io_deq_ready),
    .io_deq_valid(repeater_io_deq_valid),
    .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
    .io_deq_bits_param(repeater_io_deq_bits_param),
    .io_deq_bits_size(repeater_io_deq_bits_size),
    .io_deq_bits_source(repeater_io_deq_bits_source),
    .io_deq_bits_address(repeater_io_deq_bits_address),
    .io_deq_bits_mask(repeater_io_deq_bits_mask),
    .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
  );
  assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign auto_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign auto_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_size = aFrag[1:0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
  assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,new_gennum}; // @[Cat.scala 31:58]
  assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_11; // @[Fragmenter.scala 304:49]
  assign auto_out_a_bits_mask = repeater_io_full ? 4'hf : auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = repeater_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign repeater_clock = clock;
  assign repeater_reset = reset;
  assign repeater_io_repeat = ~aHasData & new_gennum != 4'h0; // @[Fragmenter.scala 302:41]
  assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  always @(posedge clock) begin
    if (reset) begin // @[Fragmenter.scala 189:29]
      acknum <= 4'h0; // @[Fragmenter.scala 189:29]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 209:24]
        acknum <= dFragnum;
      end else begin
        acknum <= _acknum_T_1;
      end
    end
    if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
      end
    end
    if (reset) begin // @[Fragmenter.scala 191:30]
      dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dToggle <= auto_out_d_bits_source[4]; // @[Fragmenter.scala 212:21]
      end
    end
    if (reset) begin // @[Fragmenter.scala 291:29]
      gennum <= 4'h0; // @[Fragmenter.scala 291:29]
    end else if (_T_8) begin // @[Fragmenter.scala 300:29]
      gennum <= new_gennum; // @[Fragmenter.scala 300:38]
    end
    if (aFirst) begin // @[Reg.scala 17:18]
      aToggle_r <= dToggle; // @[Reg.scala 17:22]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~repeater_io_full | _repeater_io_repeat_T) & _T_5) begin
          $fatal; // @[Fragmenter.scala 309:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(~repeater_io_full | _repeater_io_repeat_T)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Fragmenter.scala:309 assert (!repeater.io.full || !aHasData)\n"
            ); // @[Fragmenter.scala 309:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_9 | repeater_io_deq_bits_mask == 4'hf) & _T_5) begin
          $fatal; // @[Fragmenter.scala 312:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask == 4'hf)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
            ); // @[Fragmenter.scala 312:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  acknum = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  dOrig = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  dToggle = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  gennum = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  aToggle_r = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLInterconnectCoupler_14(
  input         clock,
  input         reset,
  input         auto_control_xing_out_a_ready,
  output        auto_control_xing_out_a_valid,
  output [2:0]  auto_control_xing_out_a_bits_opcode,
  output [2:0]  auto_control_xing_out_a_bits_param,
  output [1:0]  auto_control_xing_out_a_bits_size,
  output [6:0]  auto_control_xing_out_a_bits_source,
  output [28:0] auto_control_xing_out_a_bits_address,
  output [3:0]  auto_control_xing_out_a_bits_mask,
  output [31:0] auto_control_xing_out_a_bits_data,
  output        auto_control_xing_out_a_bits_corrupt,
  output        auto_control_xing_out_d_ready,
  input         auto_control_xing_out_d_valid,
  input  [2:0]  auto_control_xing_out_d_bits_opcode,
  input  [1:0]  auto_control_xing_out_d_bits_size,
  input  [6:0]  auto_control_xing_out_d_bits_source,
  input  [31:0] auto_control_xing_out_d_bits_data,
  output        auto_tl_in_a_ready,
  input         auto_tl_in_a_valid,
  input  [2:0]  auto_tl_in_a_bits_opcode,
  input  [2:0]  auto_tl_in_a_bits_param,
  input  [2:0]  auto_tl_in_a_bits_size,
  input  [1:0]  auto_tl_in_a_bits_source,
  input  [28:0] auto_tl_in_a_bits_address,
  input  [3:0]  auto_tl_in_a_bits_mask,
  input  [31:0] auto_tl_in_a_bits_data,
  input         auto_tl_in_a_bits_corrupt,
  input         auto_tl_in_d_ready,
  output        auto_tl_in_d_valid,
  output [2:0]  auto_tl_in_d_bits_opcode,
  output [2:0]  auto_tl_in_d_bits_size,
  output [1:0]  auto_tl_in_d_bits_source,
  output [31:0] auto_tl_in_d_bits_data
);
  wire  fragmenter_clock; // @[Fragmenter.scala 333:34]
  wire  fragmenter_reset; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [28:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [28:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
  TLFragmenter_10 fragmenter ( // @[Fragmenter.scala 333:34]
    .clock(fragmenter_clock),
    .reset(fragmenter_reset),
    .auto_in_a_ready(fragmenter_auto_in_a_ready),
    .auto_in_a_valid(fragmenter_auto_in_a_valid),
    .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
    .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
    .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
    .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
    .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
    .auto_in_a_bits_data(fragmenter_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
    .auto_in_d_ready(fragmenter_auto_in_d_ready),
    .auto_in_d_valid(fragmenter_auto_in_d_valid),
    .auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
    .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
    .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
    .auto_out_a_ready(fragmenter_auto_out_a_ready),
    .auto_out_a_valid(fragmenter_auto_out_a_valid),
    .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
    .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
    .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
    .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
    .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
    .auto_out_a_bits_data(fragmenter_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
    .auto_out_d_ready(fragmenter_auto_out_d_ready),
    .auto_out_d_valid(fragmenter_auto_out_d_valid),
    .auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
    .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
    .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
  );
  assign auto_control_xing_out_a_valid = fragmenter_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_data = fragmenter_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_d_ready = fragmenter_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_in_a_ready = fragmenter_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_valid = fragmenter_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_size = fragmenter_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_source = fragmenter_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_data = fragmenter_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign fragmenter_clock = clock;
  assign fragmenter_reset = reset;
  assign fragmenter_auto_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_data = auto_tl_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_out_a_ready = auto_control_xing_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_valid = auto_control_xing_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_opcode = auto_control_xing_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_size = auto_control_xing_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_source = auto_control_xing_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_data = auto_control_xing_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
endmodule
module TLMonitor_20(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [28:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [2:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
  wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
  wire [28:0] _GEN_71 = {{23'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [28:0] _T_45 = io_in_a_bits_address ^ 29'h10025000; // @[Parameters.scala 137:31]
  wire [29:0] _T_46 = {1'b0,$signed(_T_45)}; // @[Parameters.scala 137:49]
  wire [29:0] _T_48 = $signed(_T_46) & -30'sh1000; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 30'sh0; // @[Parameters.scala 137:67]
  wire  _T_59 = 3'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_60 = _source_ok_T & _T_59; // @[Mux.scala 27:73]
  wire  _T_76 = _T_60 & _T_49; // @[Monitor.scala 83:78]
  wire  _T_90 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_94 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_95 = _T_94 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_99 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_103 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_164 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_177 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_192 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
  wire  _T_200 = _T_192 & _T_49; // @[Parameters.scala 670:56]
  wire  _T_211 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_215 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_223 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_245 = source_ok & _T_200; // @[Monitor.scala 115:71]
  wire  _T_263 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_299 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_300 = io_in_a_bits_mask & _T_299; // @[Monitor.scala 127:31]
  wire  _T_301 = _T_300 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_305 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_334 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_342 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_371 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_379 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_408 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_420 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  _T_424 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_428 = io_in_d_bits_size >= 3'h2; // @[Monitor.scala 312:27]
  wire  _T_444 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_472 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_501 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_518 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_536 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [3:0] a_first_beats1_decode = is_aligned_mask[5:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] a_first_counter; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1 = a_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [28:0] address; // @[Monitor.scala 388:22]
  wire  _T_566 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_567 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_571 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_575 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_579 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_583 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
  wire [3:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [3:0] d_first_counter; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1 = d_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_590 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_591 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_599 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_603 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [11:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [3:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1_1 = a_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  reg [3:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_1 = d_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [11:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _GEN_76 = {{4'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_76 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_617 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_620 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [34:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [34:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_622 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_624 = ~_T_622[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [34:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_628 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_630 = ~_T_424; // @[Monitor.scala 671:74]
  wire  _T_631 = io_in_d_valid & d_first_1 & ~_T_424; // @[Monitor.scala 671:71]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [3:0] _GEN_22 = _d_first_T & d_first_1 & _T_630 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_23 = _d_first_T & d_first_1 & _T_630 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_617 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_641 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_643 = _T_641[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_648 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_649 = io_in_d_bits_opcode == _GEN_32 | _T_648; // @[Monitor.scala 685:77]
  wire  _T_653 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_660 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_661 = io_in_d_bits_opcode == _GEN_48 | _T_660; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_665 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_675 = _T_628 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_630; // @[Monitor.scala 694:116]
  wire  _T_677 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set = _GEN_16[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_22[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_19[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_23[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [11:0] a_sizes_set = _GEN_20[11:0];
  wire [11:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [11:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_686 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [2:0] inflight_1; // @[Monitor.scala 723:35]
  reg [11:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [3:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_2 = d_first_counter_2 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 4'h0; // @[Edges.scala 230:25]
  wire [11:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [15:0] _GEN_87 = {{4'd0}, _c_size_lookup_T_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_87 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_712 = io_in_d_valid & d_first_2 & _T_424; // @[Monitor.scala 779:71]
  wire [3:0] _GEN_67 = _d_first_T & d_first_2 & _T_424 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 783:90 784:21]
  wire [46:0] _GEN_68 = _d_first_T & d_first_2 & _T_424 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 785:21]
  wire [2:0] _T_720 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_730 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [2:0] d_clr_1 = _GEN_67[2:0];
  wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [2:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [11:0] d_opcodes_clr_1 = _GEN_68[11:0];
  wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [11:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_750 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 4'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 4'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 12'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 4'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 4'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 3'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 12'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 4'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_164 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_164) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_200 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_200) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_301 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_301) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_334 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_334) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_371 & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~_T_371) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_408 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_408) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_420 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_420) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_501 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_501 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_518 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_518 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_536 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_536 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_567 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_567) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_571 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_571) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_575 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_575) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_579 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_579) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_583 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_583) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_591 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_591) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_599 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_599) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_603 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_603) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_624 & (_T_620 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_620 & ~reset & ~_T_624) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_643 & (_T_631 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & _T_2 & ~_T_643) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_649 & (_T_631 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & same_cycle_resp & _T_2 & ~_T_649) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_653 & (_T_631 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & same_cycle_resp & _T_2 & ~_T_653) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_661 & (_T_631 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & ~same_cycle_resp & _T_2 & ~_T_661) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_665 & (_T_631 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & ~same_cycle_resp & _T_2 & ~_T_665) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_677 & (_T_675 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_675 & _T_2 & ~_T_677) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_686 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_686) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_720[0] & (_T_712 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_712 & _T_2 & ~_T_720[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_730 & (_T_712 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_712 & _T_2 & ~_T_730) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_750 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_750) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[28:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[2:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[1:0];
  _RAND_10 = {1{`RANDOM}};
  inflight = _RAND_10[2:0];
  _RAND_11 = {1{`RANDOM}};
  inflight_opcodes = _RAND_11[11:0];
  _RAND_12 = {1{`RANDOM}};
  inflight_sizes = _RAND_12[11:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[3:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[3:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  inflight_1 = _RAND_16[2:0];
  _RAND_17 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_17[11:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[3:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLFragmenter_11(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [28:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output [31:0] auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [1:0]  auto_out_a_bits_size,
  output [6:0]  auto_out_a_bits_source,
  output [28:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_size,
  input  [6:0]  auto_out_d_bits_source,
  input  [31:0] auto_out_d_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  repeater_clock; // @[Fragmenter.scala 262:30]
  wire  repeater_reset; // @[Fragmenter.scala 262:30]
  wire  repeater_io_repeat; // @[Fragmenter.scala 262:30]
  wire  repeater_io_full; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
  wire [28:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
  wire [28:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
  reg [3:0] acknum; // @[Fragmenter.scala 189:29]
  reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
  reg  dToggle; // @[Fragmenter.scala 191:30]
  wire [3:0] dFragnum = auto_out_d_bits_source[3:0]; // @[Fragmenter.scala 192:41]
  wire  dFirst = acknum == 4'h0; // @[Fragmenter.scala 193:29]
  wire  dLast = dFragnum == 4'h0; // @[Fragmenter.scala 194:30]
  wire [3:0] _dsizeOH_T = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 64:12]
  wire [2:0] dsizeOH = _dsizeOH_T[2:0]; // @[OneHot.scala 64:27]
  wire [4:0] _dsizeOH1_T_1 = 5'h3 << auto_out_d_bits_size; // @[package.scala 234:77]
  wire [1:0] dsizeOH1 = ~_dsizeOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  dHasData = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  _T_5 = ~reset; // @[Fragmenter.scala 202:16]
  wire  ack_decrement = dHasData | dsizeOH[2]; // @[Fragmenter.scala 204:32]
  wire [5:0] _dFirst_size_T = {dFragnum, 2'h0}; // @[Fragmenter.scala 206:47]
  wire [5:0] _GEN_7 = {{4'd0}, dsizeOH1}; // @[Fragmenter.scala 206:69]
  wire [5:0] _dFirst_size_T_1 = _dFirst_size_T | _GEN_7; // @[Fragmenter.scala 206:69]
  wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala 232:35]
  wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
  wire [6:0] _dFirst_size_T_4 = {1'h0,_dFirst_size_T_1}; // @[Cat.scala 31:58]
  wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
  wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
  wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
  wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
  wire [3:0] _GEN_8 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
  wire [3:0] _dFirst_size_T_8 = _GEN_8 | dFirst_size_lo; // @[OneHot.scala 32:28]
  wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
  wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
  wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
  wire  drop = ~dHasData & ~dLast; // @[Fragmenter.scala 222:30]
  wire  bundleOut_0_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  wire  _T_7 = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
  wire [3:0] _GEN_9 = {{3'd0}, ack_decrement}; // @[Fragmenter.scala 209:55]
  wire [3:0] _acknum_T_1 = acknum - _GEN_9; // @[Fragmenter.scala 209:55]
  wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h2 ? 3'h2 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
  wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
  wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
  wire [8:0] _aFragOH1_T_1 = 9'h3 << aFrag; // @[package.scala 234:77]
  wire [1:0] aFragOH1 = ~_aFragOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  aHasData = ~repeater_io_deq_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] gennum; // @[Fragmenter.scala 291:29]
  wire  aFirst = gennum == 4'h0; // @[Fragmenter.scala 292:29]
  wire [3:0] _old_gennum1_T_2 = gennum - 4'h1; // @[Fragmenter.scala 293:79]
  wire [3:0] old_gennum1 = aFirst ? aOrigOH1[5:2] : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
  wire [3:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
  wire [3:0] new_gennum = ~_new_gennum_T; // @[Fragmenter.scala 294:26]
  reg  aToggle_r; // @[Reg.scala 16:16]
  wire  _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
  wire  aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
  wire  bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  wire  _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
  wire  _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala 302:31]
  wire [5:0] _bundleOut_0_a_bits_address_T = {old_gennum1, 2'h0}; // @[Fragmenter.scala 304:65]
  wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
  wire [5:0] _bundleOut_0_a_bits_address_T_2 = _bundleOut_0_a_bits_address_T | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
  wire [5:0] _GEN_10 = {{4'd0}, aFragOH1}; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_10; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_4 = _bundleOut_0_a_bits_address_T_3 | 6'h3; // @[Fragmenter.scala 304:111]
  wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_4; // @[Fragmenter.scala 304:51]
  wire [28:0] _GEN_11 = {{23'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
  wire [2:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aToggle}; // @[Cat.scala 31:58]
  wire  _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
  TLMonitor_20 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  Repeater repeater ( // @[Fragmenter.scala 262:30]
    .clock(repeater_clock),
    .reset(repeater_reset),
    .io_repeat(repeater_io_repeat),
    .io_full(repeater_io_full),
    .io_enq_ready(repeater_io_enq_ready),
    .io_enq_valid(repeater_io_enq_valid),
    .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
    .io_enq_bits_param(repeater_io_enq_bits_param),
    .io_enq_bits_size(repeater_io_enq_bits_size),
    .io_enq_bits_source(repeater_io_enq_bits_source),
    .io_enq_bits_address(repeater_io_enq_bits_address),
    .io_enq_bits_mask(repeater_io_enq_bits_mask),
    .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
    .io_deq_ready(repeater_io_deq_ready),
    .io_deq_valid(repeater_io_deq_valid),
    .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
    .io_deq_bits_param(repeater_io_deq_bits_param),
    .io_deq_bits_size(repeater_io_deq_bits_size),
    .io_deq_bits_source(repeater_io_deq_bits_source),
    .io_deq_bits_address(repeater_io_deq_bits_address),
    .io_deq_bits_mask(repeater_io_deq_bits_mask),
    .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
  );
  assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign auto_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign auto_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_size = aFrag[1:0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
  assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,new_gennum}; // @[Cat.scala 31:58]
  assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_11; // @[Fragmenter.scala 304:49]
  assign auto_out_a_bits_mask = repeater_io_full ? 4'hf : auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = repeater_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign repeater_clock = clock;
  assign repeater_reset = reset;
  assign repeater_io_repeat = ~aHasData & new_gennum != 4'h0; // @[Fragmenter.scala 302:41]
  assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  always @(posedge clock) begin
    if (reset) begin // @[Fragmenter.scala 189:29]
      acknum <= 4'h0; // @[Fragmenter.scala 189:29]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 209:24]
        acknum <= dFragnum;
      end else begin
        acknum <= _acknum_T_1;
      end
    end
    if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
      end
    end
    if (reset) begin // @[Fragmenter.scala 191:30]
      dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dToggle <= auto_out_d_bits_source[4]; // @[Fragmenter.scala 212:21]
      end
    end
    if (reset) begin // @[Fragmenter.scala 291:29]
      gennum <= 4'h0; // @[Fragmenter.scala 291:29]
    end else if (_T_8) begin // @[Fragmenter.scala 300:29]
      gennum <= new_gennum; // @[Fragmenter.scala 300:38]
    end
    if (aFirst) begin // @[Reg.scala 17:18]
      aToggle_r <= dToggle; // @[Reg.scala 17:22]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~repeater_io_full | _repeater_io_repeat_T) & _T_5) begin
          $fatal; // @[Fragmenter.scala 309:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(~repeater_io_full | _repeater_io_repeat_T)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Fragmenter.scala:309 assert (!repeater.io.full || !aHasData)\n"
            ); // @[Fragmenter.scala 309:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_9 | repeater_io_deq_bits_mask == 4'hf) & _T_5) begin
          $fatal; // @[Fragmenter.scala 312:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask == 4'hf)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
            ); // @[Fragmenter.scala 312:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  acknum = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  dOrig = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  dToggle = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  gennum = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  aToggle_r = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLInterconnectCoupler_15(
  input         clock,
  input         reset,
  input         auto_control_xing_out_a_ready,
  output        auto_control_xing_out_a_valid,
  output [2:0]  auto_control_xing_out_a_bits_opcode,
  output [2:0]  auto_control_xing_out_a_bits_param,
  output [1:0]  auto_control_xing_out_a_bits_size,
  output [6:0]  auto_control_xing_out_a_bits_source,
  output [28:0] auto_control_xing_out_a_bits_address,
  output [3:0]  auto_control_xing_out_a_bits_mask,
  output [31:0] auto_control_xing_out_a_bits_data,
  output        auto_control_xing_out_a_bits_corrupt,
  output        auto_control_xing_out_d_ready,
  input         auto_control_xing_out_d_valid,
  input  [2:0]  auto_control_xing_out_d_bits_opcode,
  input  [1:0]  auto_control_xing_out_d_bits_size,
  input  [6:0]  auto_control_xing_out_d_bits_source,
  input  [31:0] auto_control_xing_out_d_bits_data,
  output        auto_tl_in_a_ready,
  input         auto_tl_in_a_valid,
  input  [2:0]  auto_tl_in_a_bits_opcode,
  input  [2:0]  auto_tl_in_a_bits_param,
  input  [2:0]  auto_tl_in_a_bits_size,
  input  [1:0]  auto_tl_in_a_bits_source,
  input  [28:0] auto_tl_in_a_bits_address,
  input  [3:0]  auto_tl_in_a_bits_mask,
  input  [31:0] auto_tl_in_a_bits_data,
  input         auto_tl_in_a_bits_corrupt,
  input         auto_tl_in_d_ready,
  output        auto_tl_in_d_valid,
  output [2:0]  auto_tl_in_d_bits_opcode,
  output [2:0]  auto_tl_in_d_bits_size,
  output [1:0]  auto_tl_in_d_bits_source,
  output [31:0] auto_tl_in_d_bits_data
);
  wire  fragmenter_clock; // @[Fragmenter.scala 333:34]
  wire  fragmenter_reset; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [28:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [28:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
  TLFragmenter_11 fragmenter ( // @[Fragmenter.scala 333:34]
    .clock(fragmenter_clock),
    .reset(fragmenter_reset),
    .auto_in_a_ready(fragmenter_auto_in_a_ready),
    .auto_in_a_valid(fragmenter_auto_in_a_valid),
    .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
    .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
    .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
    .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
    .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
    .auto_in_a_bits_data(fragmenter_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
    .auto_in_d_ready(fragmenter_auto_in_d_ready),
    .auto_in_d_valid(fragmenter_auto_in_d_valid),
    .auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
    .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
    .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
    .auto_out_a_ready(fragmenter_auto_out_a_ready),
    .auto_out_a_valid(fragmenter_auto_out_a_valid),
    .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
    .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
    .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
    .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
    .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
    .auto_out_a_bits_data(fragmenter_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
    .auto_out_d_ready(fragmenter_auto_out_d_ready),
    .auto_out_d_valid(fragmenter_auto_out_d_valid),
    .auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
    .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
    .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
  );
  assign auto_control_xing_out_a_valid = fragmenter_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_data = fragmenter_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_d_ready = fragmenter_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_in_a_ready = fragmenter_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_valid = fragmenter_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_size = fragmenter_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_source = fragmenter_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_data = fragmenter_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign fragmenter_clock = clock;
  assign fragmenter_reset = reset;
  assign fragmenter_auto_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_data = auto_tl_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_out_a_ready = auto_control_xing_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_valid = auto_control_xing_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_opcode = auto_control_xing_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_size = auto_control_xing_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_source = auto_control_xing_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_data = auto_control_xing_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
endmodule
module TLMonitor_21(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [28:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [2:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
  wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
  wire [28:0] _GEN_71 = {{23'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [28:0] _T_45 = io_in_a_bits_address ^ 29'h10035000; // @[Parameters.scala 137:31]
  wire [29:0] _T_46 = {1'b0,$signed(_T_45)}; // @[Parameters.scala 137:49]
  wire [29:0] _T_48 = $signed(_T_46) & -30'sh1000; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 30'sh0; // @[Parameters.scala 137:67]
  wire  _T_59 = 3'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_60 = _source_ok_T & _T_59; // @[Mux.scala 27:73]
  wire  _T_76 = _T_60 & _T_49; // @[Monitor.scala 83:78]
  wire  _T_90 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_94 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_95 = _T_94 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_99 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_103 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_164 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_177 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_192 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
  wire  _T_200 = _T_192 & _T_49; // @[Parameters.scala 670:56]
  wire  _T_211 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_215 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_223 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_245 = source_ok & _T_200; // @[Monitor.scala 115:71]
  wire  _T_263 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_299 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_300 = io_in_a_bits_mask & _T_299; // @[Monitor.scala 127:31]
  wire  _T_301 = _T_300 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_305 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_334 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_342 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_371 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_379 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_408 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_420 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  _T_424 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_428 = io_in_d_bits_size >= 3'h2; // @[Monitor.scala 312:27]
  wire  _T_444 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_472 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_501 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_518 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_536 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [3:0] a_first_beats1_decode = is_aligned_mask[5:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] a_first_counter; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1 = a_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [28:0] address; // @[Monitor.scala 388:22]
  wire  _T_566 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_567 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_571 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_575 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_579 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_583 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
  wire [3:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [3:0] d_first_counter; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1 = d_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_590 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_591 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_599 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_603 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [11:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [3:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1_1 = a_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  reg [3:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_1 = d_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [11:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _GEN_76 = {{4'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_76 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_617 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_620 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [34:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [34:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_622 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_624 = ~_T_622[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [34:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_628 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_630 = ~_T_424; // @[Monitor.scala 671:74]
  wire  _T_631 = io_in_d_valid & d_first_1 & ~_T_424; // @[Monitor.scala 671:71]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [3:0] _GEN_22 = _d_first_T & d_first_1 & _T_630 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_23 = _d_first_T & d_first_1 & _T_630 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_617 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_641 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_643 = _T_641[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_648 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_649 = io_in_d_bits_opcode == _GEN_32 | _T_648; // @[Monitor.scala 685:77]
  wire  _T_653 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_660 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_661 = io_in_d_bits_opcode == _GEN_48 | _T_660; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_665 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_675 = _T_628 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_630; // @[Monitor.scala 694:116]
  wire  _T_677 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set = _GEN_16[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_22[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_19[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_23[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [11:0] a_sizes_set = _GEN_20[11:0];
  wire [11:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [11:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_686 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [2:0] inflight_1; // @[Monitor.scala 723:35]
  reg [11:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [3:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_2 = d_first_counter_2 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 4'h0; // @[Edges.scala 230:25]
  wire [11:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [15:0] _GEN_87 = {{4'd0}, _c_size_lookup_T_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_87 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_712 = io_in_d_valid & d_first_2 & _T_424; // @[Monitor.scala 779:71]
  wire [3:0] _GEN_67 = _d_first_T & d_first_2 & _T_424 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 783:90 784:21]
  wire [46:0] _GEN_68 = _d_first_T & d_first_2 & _T_424 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 785:21]
  wire [2:0] _T_720 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_730 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [2:0] d_clr_1 = _GEN_67[2:0];
  wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [2:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [11:0] d_opcodes_clr_1 = _GEN_68[11:0];
  wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [11:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_750 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 4'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 4'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 12'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 4'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 4'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 3'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 12'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 4'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_164 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_164) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_200 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_200) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_301 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_301) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_334 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_334) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_371 & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~_T_371) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_408 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_408) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_420 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_420) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_501 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_501 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_518 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_518 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_536 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_536 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_567 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_567) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_571 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_571) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_575 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_575) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_579 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_579) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_583 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_583) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_591 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_591) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_599 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_599) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_603 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_603) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_624 & (_T_620 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_620 & ~reset & ~_T_624) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_643 & (_T_631 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & _T_2 & ~_T_643) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_649 & (_T_631 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & same_cycle_resp & _T_2 & ~_T_649) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_653 & (_T_631 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & same_cycle_resp & _T_2 & ~_T_653) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_661 & (_T_631 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & ~same_cycle_resp & _T_2 & ~_T_661) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_665 & (_T_631 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & ~same_cycle_resp & _T_2 & ~_T_665) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_677 & (_T_675 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_675 & _T_2 & ~_T_677) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_686 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_686) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_720[0] & (_T_712 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_712 & _T_2 & ~_T_720[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_730 & (_T_712 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_712 & _T_2 & ~_T_730) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at PWM.scala:160:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_750 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_750) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at PWM.scala:160:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[28:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[2:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[1:0];
  _RAND_10 = {1{`RANDOM}};
  inflight = _RAND_10[2:0];
  _RAND_11 = {1{`RANDOM}};
  inflight_opcodes = _RAND_11[11:0];
  _RAND_12 = {1{`RANDOM}};
  inflight_sizes = _RAND_12[11:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[3:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[3:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  inflight_1 = _RAND_16[2:0];
  _RAND_17 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_17[11:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[3:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLFragmenter_12(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [28:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output [31:0] auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [1:0]  auto_out_a_bits_size,
  output [6:0]  auto_out_a_bits_source,
  output [28:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_size,
  input  [6:0]  auto_out_d_bits_source,
  input  [31:0] auto_out_d_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  repeater_clock; // @[Fragmenter.scala 262:30]
  wire  repeater_reset; // @[Fragmenter.scala 262:30]
  wire  repeater_io_repeat; // @[Fragmenter.scala 262:30]
  wire  repeater_io_full; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
  wire [28:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
  wire [28:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
  reg [3:0] acknum; // @[Fragmenter.scala 189:29]
  reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
  reg  dToggle; // @[Fragmenter.scala 191:30]
  wire [3:0] dFragnum = auto_out_d_bits_source[3:0]; // @[Fragmenter.scala 192:41]
  wire  dFirst = acknum == 4'h0; // @[Fragmenter.scala 193:29]
  wire  dLast = dFragnum == 4'h0; // @[Fragmenter.scala 194:30]
  wire [3:0] _dsizeOH_T = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 64:12]
  wire [2:0] dsizeOH = _dsizeOH_T[2:0]; // @[OneHot.scala 64:27]
  wire [4:0] _dsizeOH1_T_1 = 5'h3 << auto_out_d_bits_size; // @[package.scala 234:77]
  wire [1:0] dsizeOH1 = ~_dsizeOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  dHasData = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  _T_5 = ~reset; // @[Fragmenter.scala 202:16]
  wire  ack_decrement = dHasData | dsizeOH[2]; // @[Fragmenter.scala 204:32]
  wire [5:0] _dFirst_size_T = {dFragnum, 2'h0}; // @[Fragmenter.scala 206:47]
  wire [5:0] _GEN_7 = {{4'd0}, dsizeOH1}; // @[Fragmenter.scala 206:69]
  wire [5:0] _dFirst_size_T_1 = _dFirst_size_T | _GEN_7; // @[Fragmenter.scala 206:69]
  wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala 232:35]
  wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
  wire [6:0] _dFirst_size_T_4 = {1'h0,_dFirst_size_T_1}; // @[Cat.scala 31:58]
  wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
  wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
  wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
  wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
  wire [3:0] _GEN_8 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
  wire [3:0] _dFirst_size_T_8 = _GEN_8 | dFirst_size_lo; // @[OneHot.scala 32:28]
  wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
  wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
  wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
  wire  drop = ~dHasData & ~dLast; // @[Fragmenter.scala 222:30]
  wire  bundleOut_0_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  wire  _T_7 = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
  wire [3:0] _GEN_9 = {{3'd0}, ack_decrement}; // @[Fragmenter.scala 209:55]
  wire [3:0] _acknum_T_1 = acknum - _GEN_9; // @[Fragmenter.scala 209:55]
  wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h2 ? 3'h2 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
  wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
  wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
  wire [8:0] _aFragOH1_T_1 = 9'h3 << aFrag; // @[package.scala 234:77]
  wire [1:0] aFragOH1 = ~_aFragOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  aHasData = ~repeater_io_deq_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] gennum; // @[Fragmenter.scala 291:29]
  wire  aFirst = gennum == 4'h0; // @[Fragmenter.scala 292:29]
  wire [3:0] _old_gennum1_T_2 = gennum - 4'h1; // @[Fragmenter.scala 293:79]
  wire [3:0] old_gennum1 = aFirst ? aOrigOH1[5:2] : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
  wire [3:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
  wire [3:0] new_gennum = ~_new_gennum_T; // @[Fragmenter.scala 294:26]
  reg  aToggle_r; // @[Reg.scala 16:16]
  wire  _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
  wire  aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
  wire  bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  wire  _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
  wire  _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala 302:31]
  wire [5:0] _bundleOut_0_a_bits_address_T = {old_gennum1, 2'h0}; // @[Fragmenter.scala 304:65]
  wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
  wire [5:0] _bundleOut_0_a_bits_address_T_2 = _bundleOut_0_a_bits_address_T | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
  wire [5:0] _GEN_10 = {{4'd0}, aFragOH1}; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_10; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_4 = _bundleOut_0_a_bits_address_T_3 | 6'h3; // @[Fragmenter.scala 304:111]
  wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_4; // @[Fragmenter.scala 304:51]
  wire [28:0] _GEN_11 = {{23'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
  wire [2:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aToggle}; // @[Cat.scala 31:58]
  wire  _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
  TLMonitor_21 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  Repeater repeater ( // @[Fragmenter.scala 262:30]
    .clock(repeater_clock),
    .reset(repeater_reset),
    .io_repeat(repeater_io_repeat),
    .io_full(repeater_io_full),
    .io_enq_ready(repeater_io_enq_ready),
    .io_enq_valid(repeater_io_enq_valid),
    .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
    .io_enq_bits_param(repeater_io_enq_bits_param),
    .io_enq_bits_size(repeater_io_enq_bits_size),
    .io_enq_bits_source(repeater_io_enq_bits_source),
    .io_enq_bits_address(repeater_io_enq_bits_address),
    .io_enq_bits_mask(repeater_io_enq_bits_mask),
    .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
    .io_deq_ready(repeater_io_deq_ready),
    .io_deq_valid(repeater_io_deq_valid),
    .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
    .io_deq_bits_param(repeater_io_deq_bits_param),
    .io_deq_bits_size(repeater_io_deq_bits_size),
    .io_deq_bits_source(repeater_io_deq_bits_source),
    .io_deq_bits_address(repeater_io_deq_bits_address),
    .io_deq_bits_mask(repeater_io_deq_bits_mask),
    .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
  );
  assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign auto_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign auto_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_size = aFrag[1:0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
  assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,new_gennum}; // @[Cat.scala 31:58]
  assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_11; // @[Fragmenter.scala 304:49]
  assign auto_out_a_bits_mask = repeater_io_full ? 4'hf : auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = repeater_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign repeater_clock = clock;
  assign repeater_reset = reset;
  assign repeater_io_repeat = ~aHasData & new_gennum != 4'h0; // @[Fragmenter.scala 302:41]
  assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  always @(posedge clock) begin
    if (reset) begin // @[Fragmenter.scala 189:29]
      acknum <= 4'h0; // @[Fragmenter.scala 189:29]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 209:24]
        acknum <= dFragnum;
      end else begin
        acknum <= _acknum_T_1;
      end
    end
    if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
      end
    end
    if (reset) begin // @[Fragmenter.scala 191:30]
      dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dToggle <= auto_out_d_bits_source[4]; // @[Fragmenter.scala 212:21]
      end
    end
    if (reset) begin // @[Fragmenter.scala 291:29]
      gennum <= 4'h0; // @[Fragmenter.scala 291:29]
    end else if (_T_8) begin // @[Fragmenter.scala 300:29]
      gennum <= new_gennum; // @[Fragmenter.scala 300:38]
    end
    if (aFirst) begin // @[Reg.scala 17:18]
      aToggle_r <= dToggle; // @[Reg.scala 17:22]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~repeater_io_full | _repeater_io_repeat_T) & _T_5) begin
          $fatal; // @[Fragmenter.scala 309:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(~repeater_io_full | _repeater_io_repeat_T)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Fragmenter.scala:309 assert (!repeater.io.full || !aHasData)\n"
            ); // @[Fragmenter.scala 309:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_9 | repeater_io_deq_bits_mask == 4'hf) & _T_5) begin
          $fatal; // @[Fragmenter.scala 312:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask == 4'hf)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
            ); // @[Fragmenter.scala 312:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  acknum = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  dOrig = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  dToggle = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  gennum = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  aToggle_r = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLInterconnectCoupler_16(
  input         clock,
  input         reset,
  input         auto_control_xing_out_a_ready,
  output        auto_control_xing_out_a_valid,
  output [2:0]  auto_control_xing_out_a_bits_opcode,
  output [2:0]  auto_control_xing_out_a_bits_param,
  output [1:0]  auto_control_xing_out_a_bits_size,
  output [6:0]  auto_control_xing_out_a_bits_source,
  output [28:0] auto_control_xing_out_a_bits_address,
  output [3:0]  auto_control_xing_out_a_bits_mask,
  output [31:0] auto_control_xing_out_a_bits_data,
  output        auto_control_xing_out_a_bits_corrupt,
  output        auto_control_xing_out_d_ready,
  input         auto_control_xing_out_d_valid,
  input  [2:0]  auto_control_xing_out_d_bits_opcode,
  input  [1:0]  auto_control_xing_out_d_bits_size,
  input  [6:0]  auto_control_xing_out_d_bits_source,
  input  [31:0] auto_control_xing_out_d_bits_data,
  output        auto_tl_in_a_ready,
  input         auto_tl_in_a_valid,
  input  [2:0]  auto_tl_in_a_bits_opcode,
  input  [2:0]  auto_tl_in_a_bits_param,
  input  [2:0]  auto_tl_in_a_bits_size,
  input  [1:0]  auto_tl_in_a_bits_source,
  input  [28:0] auto_tl_in_a_bits_address,
  input  [3:0]  auto_tl_in_a_bits_mask,
  input  [31:0] auto_tl_in_a_bits_data,
  input         auto_tl_in_a_bits_corrupt,
  input         auto_tl_in_d_ready,
  output        auto_tl_in_d_valid,
  output [2:0]  auto_tl_in_d_bits_opcode,
  output [2:0]  auto_tl_in_d_bits_size,
  output [1:0]  auto_tl_in_d_bits_source,
  output [31:0] auto_tl_in_d_bits_data
);
  wire  fragmenter_clock; // @[Fragmenter.scala 333:34]
  wire  fragmenter_reset; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [28:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [28:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
  TLFragmenter_12 fragmenter ( // @[Fragmenter.scala 333:34]
    .clock(fragmenter_clock),
    .reset(fragmenter_reset),
    .auto_in_a_ready(fragmenter_auto_in_a_ready),
    .auto_in_a_valid(fragmenter_auto_in_a_valid),
    .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
    .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
    .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
    .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
    .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
    .auto_in_a_bits_data(fragmenter_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
    .auto_in_d_ready(fragmenter_auto_in_d_ready),
    .auto_in_d_valid(fragmenter_auto_in_d_valid),
    .auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
    .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
    .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
    .auto_out_a_ready(fragmenter_auto_out_a_ready),
    .auto_out_a_valid(fragmenter_auto_out_a_valid),
    .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
    .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
    .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
    .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
    .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
    .auto_out_a_bits_data(fragmenter_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
    .auto_out_d_ready(fragmenter_auto_out_d_ready),
    .auto_out_d_valid(fragmenter_auto_out_d_valid),
    .auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
    .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
    .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
  );
  assign auto_control_xing_out_a_valid = fragmenter_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_data = fragmenter_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_d_ready = fragmenter_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_in_a_ready = fragmenter_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_valid = fragmenter_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_size = fragmenter_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_source = fragmenter_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_data = fragmenter_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign fragmenter_clock = clock;
  assign fragmenter_reset = reset;
  assign fragmenter_auto_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_data = auto_tl_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_out_a_ready = auto_control_xing_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_valid = auto_control_xing_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_opcode = auto_control_xing_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_size = auto_control_xing_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_source = auto_control_xing_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_data = auto_control_xing_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
endmodule
module TLMonitor_22(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [28:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [2:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
  wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
  wire [28:0] _GEN_71 = {{23'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [28:0] _T_45 = io_in_a_bits_address ^ 29'h10016000; // @[Parameters.scala 137:31]
  wire [29:0] _T_46 = {1'b0,$signed(_T_45)}; // @[Parameters.scala 137:49]
  wire [29:0] _T_48 = $signed(_T_46) & -30'sh1000; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 30'sh0; // @[Parameters.scala 137:67]
  wire  _T_59 = 3'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_60 = _source_ok_T & _T_59; // @[Mux.scala 27:73]
  wire  _T_76 = _T_60 & _T_49; // @[Monitor.scala 83:78]
  wire  _T_90 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_94 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_95 = _T_94 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_99 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_103 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_164 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_177 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_192 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
  wire  _T_200 = _T_192 & _T_49; // @[Parameters.scala 670:56]
  wire  _T_211 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_215 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_223 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_245 = source_ok & _T_200; // @[Monitor.scala 115:71]
  wire  _T_263 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_299 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_300 = io_in_a_bits_mask & _T_299; // @[Monitor.scala 127:31]
  wire  _T_301 = _T_300 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_305 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_334 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_342 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_371 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_379 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_408 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_420 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  _T_424 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_428 = io_in_d_bits_size >= 3'h2; // @[Monitor.scala 312:27]
  wire  _T_444 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_472 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_501 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_518 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_536 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [3:0] a_first_beats1_decode = is_aligned_mask[5:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] a_first_counter; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1 = a_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [28:0] address; // @[Monitor.scala 388:22]
  wire  _T_566 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_567 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_571 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_575 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_579 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_583 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
  wire [3:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [3:0] d_first_counter; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1 = d_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_590 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_591 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_599 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_603 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [11:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [3:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1_1 = a_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  reg [3:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_1 = d_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [11:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _GEN_76 = {{4'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_76 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_617 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_620 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [34:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [34:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_622 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_624 = ~_T_622[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [34:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_628 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_630 = ~_T_424; // @[Monitor.scala 671:74]
  wire  _T_631 = io_in_d_valid & d_first_1 & ~_T_424; // @[Monitor.scala 671:71]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [3:0] _GEN_22 = _d_first_T & d_first_1 & _T_630 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_23 = _d_first_T & d_first_1 & _T_630 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_617 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_641 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_643 = _T_641[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_648 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_649 = io_in_d_bits_opcode == _GEN_32 | _T_648; // @[Monitor.scala 685:77]
  wire  _T_653 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_660 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_661 = io_in_d_bits_opcode == _GEN_48 | _T_660; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_665 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_675 = _T_628 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_630; // @[Monitor.scala 694:116]
  wire  _T_677 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set = _GEN_16[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_22[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_19[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_23[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [11:0] a_sizes_set = _GEN_20[11:0];
  wire [11:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [11:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_686 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [2:0] inflight_1; // @[Monitor.scala 723:35]
  reg [11:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [3:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_2 = d_first_counter_2 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 4'h0; // @[Edges.scala 230:25]
  wire [11:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [15:0] _GEN_87 = {{4'd0}, _c_size_lookup_T_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_87 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_712 = io_in_d_valid & d_first_2 & _T_424; // @[Monitor.scala 779:71]
  wire [3:0] _GEN_67 = _d_first_T & d_first_2 & _T_424 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 783:90 784:21]
  wire [46:0] _GEN_68 = _d_first_T & d_first_2 & _T_424 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 785:21]
  wire [2:0] _T_720 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_730 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [2:0] d_clr_1 = _GEN_67[2:0];
  wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [2:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [11:0] d_opcodes_clr_1 = _GEN_68[11:0];
  wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [11:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_750 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 4'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 4'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 12'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 4'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 4'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 3'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 12'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 4'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_164 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_164) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_200 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_200) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_301 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_301) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_334 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_334) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_371 & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~_T_371) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_408 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_408) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_420 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_420) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_501 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_501 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_518 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_518 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_536 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_536 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_567 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_567) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_571 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_571) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_575 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_575) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_579 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_579) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_583 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_583) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_591 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_591) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_599 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_599) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_603 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_603) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_624 & (_T_620 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_620 & ~reset & ~_T_624) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_643 & (_T_631 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & _T_2 & ~_T_643) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_649 & (_T_631 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & same_cycle_resp & _T_2 & ~_T_649) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_653 & (_T_631 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & same_cycle_resp & _T_2 & ~_T_653) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_661 & (_T_631 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & ~same_cycle_resp & _T_2 & ~_T_661) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_665 & (_T_631 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & ~same_cycle_resp & _T_2 & ~_T_665) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_677 & (_T_675 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_675 & _T_2 & ~_T_677) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_686 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_686) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_720[0] & (_T_712 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_712 & _T_2 & ~_T_720[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_730 & (_T_712 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_712 & _T_2 & ~_T_730) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_750 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_750) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[28:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[2:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[1:0];
  _RAND_10 = {1{`RANDOM}};
  inflight = _RAND_10[2:0];
  _RAND_11 = {1{`RANDOM}};
  inflight_opcodes = _RAND_11[11:0];
  _RAND_12 = {1{`RANDOM}};
  inflight_sizes = _RAND_12[11:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[3:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[3:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  inflight_1 = _RAND_16[2:0];
  _RAND_17 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_17[11:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[3:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLFragmenter_13(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [28:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output [31:0] auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [1:0]  auto_out_a_bits_size,
  output [6:0]  auto_out_a_bits_source,
  output [28:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_size,
  input  [6:0]  auto_out_d_bits_source,
  input  [31:0] auto_out_d_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  repeater_clock; // @[Fragmenter.scala 262:30]
  wire  repeater_reset; // @[Fragmenter.scala 262:30]
  wire  repeater_io_repeat; // @[Fragmenter.scala 262:30]
  wire  repeater_io_full; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
  wire [28:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
  wire [28:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
  reg [3:0] acknum; // @[Fragmenter.scala 189:29]
  reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
  reg  dToggle; // @[Fragmenter.scala 191:30]
  wire [3:0] dFragnum = auto_out_d_bits_source[3:0]; // @[Fragmenter.scala 192:41]
  wire  dFirst = acknum == 4'h0; // @[Fragmenter.scala 193:29]
  wire  dLast = dFragnum == 4'h0; // @[Fragmenter.scala 194:30]
  wire [3:0] _dsizeOH_T = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 64:12]
  wire [2:0] dsizeOH = _dsizeOH_T[2:0]; // @[OneHot.scala 64:27]
  wire [4:0] _dsizeOH1_T_1 = 5'h3 << auto_out_d_bits_size; // @[package.scala 234:77]
  wire [1:0] dsizeOH1 = ~_dsizeOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  dHasData = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  _T_5 = ~reset; // @[Fragmenter.scala 202:16]
  wire  ack_decrement = dHasData | dsizeOH[2]; // @[Fragmenter.scala 204:32]
  wire [5:0] _dFirst_size_T = {dFragnum, 2'h0}; // @[Fragmenter.scala 206:47]
  wire [5:0] _GEN_7 = {{4'd0}, dsizeOH1}; // @[Fragmenter.scala 206:69]
  wire [5:0] _dFirst_size_T_1 = _dFirst_size_T | _GEN_7; // @[Fragmenter.scala 206:69]
  wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala 232:35]
  wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
  wire [6:0] _dFirst_size_T_4 = {1'h0,_dFirst_size_T_1}; // @[Cat.scala 31:58]
  wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
  wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
  wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
  wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
  wire [3:0] _GEN_8 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
  wire [3:0] _dFirst_size_T_8 = _GEN_8 | dFirst_size_lo; // @[OneHot.scala 32:28]
  wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
  wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
  wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
  wire  drop = ~dHasData & ~dLast; // @[Fragmenter.scala 222:30]
  wire  bundleOut_0_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  wire  _T_7 = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
  wire [3:0] _GEN_9 = {{3'd0}, ack_decrement}; // @[Fragmenter.scala 209:55]
  wire [3:0] _acknum_T_1 = acknum - _GEN_9; // @[Fragmenter.scala 209:55]
  wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h2 ? 3'h2 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
  wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
  wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
  wire [8:0] _aFragOH1_T_1 = 9'h3 << aFrag; // @[package.scala 234:77]
  wire [1:0] aFragOH1 = ~_aFragOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  aHasData = ~repeater_io_deq_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] gennum; // @[Fragmenter.scala 291:29]
  wire  aFirst = gennum == 4'h0; // @[Fragmenter.scala 292:29]
  wire [3:0] _old_gennum1_T_2 = gennum - 4'h1; // @[Fragmenter.scala 293:79]
  wire [3:0] old_gennum1 = aFirst ? aOrigOH1[5:2] : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
  wire [3:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
  wire [3:0] new_gennum = ~_new_gennum_T; // @[Fragmenter.scala 294:26]
  reg  aToggle_r; // @[Reg.scala 16:16]
  wire  _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
  wire  aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
  wire  bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  wire  _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
  wire  _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala 302:31]
  wire [5:0] _bundleOut_0_a_bits_address_T = {old_gennum1, 2'h0}; // @[Fragmenter.scala 304:65]
  wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
  wire [5:0] _bundleOut_0_a_bits_address_T_2 = _bundleOut_0_a_bits_address_T | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
  wire [5:0] _GEN_10 = {{4'd0}, aFragOH1}; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_10; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_4 = _bundleOut_0_a_bits_address_T_3 | 6'h3; // @[Fragmenter.scala 304:111]
  wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_4; // @[Fragmenter.scala 304:51]
  wire [28:0] _GEN_11 = {{23'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
  wire [2:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aToggle}; // @[Cat.scala 31:58]
  wire  _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
  TLMonitor_22 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  Repeater repeater ( // @[Fragmenter.scala 262:30]
    .clock(repeater_clock),
    .reset(repeater_reset),
    .io_repeat(repeater_io_repeat),
    .io_full(repeater_io_full),
    .io_enq_ready(repeater_io_enq_ready),
    .io_enq_valid(repeater_io_enq_valid),
    .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
    .io_enq_bits_param(repeater_io_enq_bits_param),
    .io_enq_bits_size(repeater_io_enq_bits_size),
    .io_enq_bits_source(repeater_io_enq_bits_source),
    .io_enq_bits_address(repeater_io_enq_bits_address),
    .io_enq_bits_mask(repeater_io_enq_bits_mask),
    .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
    .io_deq_ready(repeater_io_deq_ready),
    .io_deq_valid(repeater_io_deq_valid),
    .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
    .io_deq_bits_param(repeater_io_deq_bits_param),
    .io_deq_bits_size(repeater_io_deq_bits_size),
    .io_deq_bits_source(repeater_io_deq_bits_source),
    .io_deq_bits_address(repeater_io_deq_bits_address),
    .io_deq_bits_mask(repeater_io_deq_bits_mask),
    .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
  );
  assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign auto_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign auto_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_size = aFrag[1:0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
  assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,new_gennum}; // @[Cat.scala 31:58]
  assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_11; // @[Fragmenter.scala 304:49]
  assign auto_out_a_bits_mask = repeater_io_full ? 4'hf : auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = repeater_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign repeater_clock = clock;
  assign repeater_reset = reset;
  assign repeater_io_repeat = ~aHasData & new_gennum != 4'h0; // @[Fragmenter.scala 302:41]
  assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  always @(posedge clock) begin
    if (reset) begin // @[Fragmenter.scala 189:29]
      acknum <= 4'h0; // @[Fragmenter.scala 189:29]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 209:24]
        acknum <= dFragnum;
      end else begin
        acknum <= _acknum_T_1;
      end
    end
    if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
      end
    end
    if (reset) begin // @[Fragmenter.scala 191:30]
      dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dToggle <= auto_out_d_bits_source[4]; // @[Fragmenter.scala 212:21]
      end
    end
    if (reset) begin // @[Fragmenter.scala 291:29]
      gennum <= 4'h0; // @[Fragmenter.scala 291:29]
    end else if (_T_8) begin // @[Fragmenter.scala 300:29]
      gennum <= new_gennum; // @[Fragmenter.scala 300:38]
    end
    if (aFirst) begin // @[Reg.scala 17:18]
      aToggle_r <= dToggle; // @[Reg.scala 17:22]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~repeater_io_full | _repeater_io_repeat_T) & _T_5) begin
          $fatal; // @[Fragmenter.scala 309:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(~repeater_io_full | _repeater_io_repeat_T)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Fragmenter.scala:309 assert (!repeater.io.full || !aHasData)\n"
            ); // @[Fragmenter.scala 309:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_9 | repeater_io_deq_bits_mask == 4'hf) & _T_5) begin
          $fatal; // @[Fragmenter.scala 312:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask == 4'hf)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
            ); // @[Fragmenter.scala 312:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  acknum = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  dOrig = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  dToggle = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  gennum = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  aToggle_r = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLInterconnectCoupler_17(
  input         clock,
  input         reset,
  input         auto_control_xing_out_a_ready,
  output        auto_control_xing_out_a_valid,
  output [2:0]  auto_control_xing_out_a_bits_opcode,
  output [2:0]  auto_control_xing_out_a_bits_param,
  output [1:0]  auto_control_xing_out_a_bits_size,
  output [6:0]  auto_control_xing_out_a_bits_source,
  output [28:0] auto_control_xing_out_a_bits_address,
  output [3:0]  auto_control_xing_out_a_bits_mask,
  output [31:0] auto_control_xing_out_a_bits_data,
  output        auto_control_xing_out_a_bits_corrupt,
  output        auto_control_xing_out_d_ready,
  input         auto_control_xing_out_d_valid,
  input  [2:0]  auto_control_xing_out_d_bits_opcode,
  input  [1:0]  auto_control_xing_out_d_bits_size,
  input  [6:0]  auto_control_xing_out_d_bits_source,
  input  [31:0] auto_control_xing_out_d_bits_data,
  output        auto_tl_in_a_ready,
  input         auto_tl_in_a_valid,
  input  [2:0]  auto_tl_in_a_bits_opcode,
  input  [2:0]  auto_tl_in_a_bits_param,
  input  [2:0]  auto_tl_in_a_bits_size,
  input  [1:0]  auto_tl_in_a_bits_source,
  input  [28:0] auto_tl_in_a_bits_address,
  input  [3:0]  auto_tl_in_a_bits_mask,
  input  [31:0] auto_tl_in_a_bits_data,
  input         auto_tl_in_a_bits_corrupt,
  input         auto_tl_in_d_ready,
  output        auto_tl_in_d_valid,
  output [2:0]  auto_tl_in_d_bits_opcode,
  output [2:0]  auto_tl_in_d_bits_size,
  output [1:0]  auto_tl_in_d_bits_source,
  output [31:0] auto_tl_in_d_bits_data
);
  wire  fragmenter_clock; // @[Fragmenter.scala 333:34]
  wire  fragmenter_reset; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [28:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [28:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
  TLFragmenter_13 fragmenter ( // @[Fragmenter.scala 333:34]
    .clock(fragmenter_clock),
    .reset(fragmenter_reset),
    .auto_in_a_ready(fragmenter_auto_in_a_ready),
    .auto_in_a_valid(fragmenter_auto_in_a_valid),
    .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
    .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
    .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
    .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
    .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
    .auto_in_a_bits_data(fragmenter_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
    .auto_in_d_ready(fragmenter_auto_in_d_ready),
    .auto_in_d_valid(fragmenter_auto_in_d_valid),
    .auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
    .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
    .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
    .auto_out_a_ready(fragmenter_auto_out_a_ready),
    .auto_out_a_valid(fragmenter_auto_out_a_valid),
    .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
    .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
    .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
    .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
    .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
    .auto_out_a_bits_data(fragmenter_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
    .auto_out_d_ready(fragmenter_auto_out_d_ready),
    .auto_out_d_valid(fragmenter_auto_out_d_valid),
    .auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
    .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
    .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
  );
  assign auto_control_xing_out_a_valid = fragmenter_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_data = fragmenter_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_d_ready = fragmenter_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_in_a_ready = fragmenter_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_valid = fragmenter_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_size = fragmenter_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_source = fragmenter_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_data = fragmenter_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign fragmenter_clock = clock;
  assign fragmenter_reset = reset;
  assign fragmenter_auto_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_data = auto_tl_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_out_a_ready = auto_control_xing_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_valid = auto_control_xing_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_opcode = auto_control_xing_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_size = auto_control_xing_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_source = auto_control_xing_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_data = auto_control_xing_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
endmodule
module TLMonitor_23(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [28:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [2:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
  wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
  wire [28:0] _GEN_71 = {{23'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [28:0] _T_45 = io_in_a_bits_address ^ 29'h10026000; // @[Parameters.scala 137:31]
  wire [29:0] _T_46 = {1'b0,$signed(_T_45)}; // @[Parameters.scala 137:49]
  wire [29:0] _T_48 = $signed(_T_46) & -30'sh1000; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 30'sh0; // @[Parameters.scala 137:67]
  wire  _T_59 = 3'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_60 = _source_ok_T & _T_59; // @[Mux.scala 27:73]
  wire  _T_76 = _T_60 & _T_49; // @[Monitor.scala 83:78]
  wire  _T_90 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_94 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_95 = _T_94 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_99 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_103 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_164 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_177 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_192 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
  wire  _T_200 = _T_192 & _T_49; // @[Parameters.scala 670:56]
  wire  _T_211 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_215 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_223 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_245 = source_ok & _T_200; // @[Monitor.scala 115:71]
  wire  _T_263 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_299 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_300 = io_in_a_bits_mask & _T_299; // @[Monitor.scala 127:31]
  wire  _T_301 = _T_300 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_305 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_334 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_342 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_371 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_379 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_408 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_420 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  _T_424 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_428 = io_in_d_bits_size >= 3'h2; // @[Monitor.scala 312:27]
  wire  _T_444 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_472 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_501 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_518 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_536 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [3:0] a_first_beats1_decode = is_aligned_mask[5:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] a_first_counter; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1 = a_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [28:0] address; // @[Monitor.scala 388:22]
  wire  _T_566 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_567 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_571 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_575 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_579 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_583 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
  wire [3:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [3:0] d_first_counter; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1 = d_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_590 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_591 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_599 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_603 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [11:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [3:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1_1 = a_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  reg [3:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_1 = d_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [11:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _GEN_76 = {{4'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_76 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_617 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_620 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [34:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [34:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_622 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_624 = ~_T_622[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [34:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_628 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_630 = ~_T_424; // @[Monitor.scala 671:74]
  wire  _T_631 = io_in_d_valid & d_first_1 & ~_T_424; // @[Monitor.scala 671:71]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [3:0] _GEN_22 = _d_first_T & d_first_1 & _T_630 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_23 = _d_first_T & d_first_1 & _T_630 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_617 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_641 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_643 = _T_641[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_648 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_649 = io_in_d_bits_opcode == _GEN_32 | _T_648; // @[Monitor.scala 685:77]
  wire  _T_653 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_660 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_661 = io_in_d_bits_opcode == _GEN_48 | _T_660; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_665 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_675 = _T_628 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_630; // @[Monitor.scala 694:116]
  wire  _T_677 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set = _GEN_16[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_22[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_19[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_23[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [11:0] a_sizes_set = _GEN_20[11:0];
  wire [11:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [11:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_686 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [2:0] inflight_1; // @[Monitor.scala 723:35]
  reg [11:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [3:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_2 = d_first_counter_2 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 4'h0; // @[Edges.scala 230:25]
  wire [11:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [15:0] _GEN_87 = {{4'd0}, _c_size_lookup_T_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_87 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_712 = io_in_d_valid & d_first_2 & _T_424; // @[Monitor.scala 779:71]
  wire [3:0] _GEN_67 = _d_first_T & d_first_2 & _T_424 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 783:90 784:21]
  wire [46:0] _GEN_68 = _d_first_T & d_first_2 & _T_424 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 785:21]
  wire [2:0] _T_720 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_730 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [2:0] d_clr_1 = _GEN_67[2:0];
  wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [2:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [11:0] d_opcodes_clr_1 = _GEN_68[11:0];
  wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [11:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_750 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 4'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 4'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 12'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 4'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 4'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 3'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 12'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 4'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_164 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_164) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_200 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_200) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_301 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_301) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_334 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_334) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_371 & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~_T_371) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_408 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_408) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_420 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_420) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_501 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_501 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_518 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_518 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_536 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_536 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_567 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_567) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_571 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_571) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_575 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_575) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_579 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_579) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_583 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_583) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_591 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_591) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_599 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_599) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_603 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_603) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_624 & (_T_620 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_620 & ~reset & ~_T_624) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_643 & (_T_631 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & _T_2 & ~_T_643) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_649 & (_T_631 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & same_cycle_resp & _T_2 & ~_T_649) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_653 & (_T_631 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & same_cycle_resp & _T_2 & ~_T_653) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_661 & (_T_631 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & ~same_cycle_resp & _T_2 & ~_T_661) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_665 & (_T_631 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & ~same_cycle_resp & _T_2 & ~_T_665) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_677 & (_T_675 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_675 & _T_2 & ~_T_677) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_686 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_686) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_720[0] & (_T_712 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_712 & _T_2 & ~_T_720[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_730 & (_T_712 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_712 & _T_2 & ~_T_730) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at I2C.scala:622:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_750 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_750) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at I2C.scala:622:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[28:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[2:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[1:0];
  _RAND_10 = {1{`RANDOM}};
  inflight = _RAND_10[2:0];
  _RAND_11 = {1{`RANDOM}};
  inflight_opcodes = _RAND_11[11:0];
  _RAND_12 = {1{`RANDOM}};
  inflight_sizes = _RAND_12[11:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[3:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[3:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  inflight_1 = _RAND_16[2:0];
  _RAND_17 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_17[11:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[3:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLFragmenter_14(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [28:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output [31:0] auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [1:0]  auto_out_a_bits_size,
  output [6:0]  auto_out_a_bits_source,
  output [28:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_size,
  input  [6:0]  auto_out_d_bits_source,
  input  [31:0] auto_out_d_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  repeater_clock; // @[Fragmenter.scala 262:30]
  wire  repeater_reset; // @[Fragmenter.scala 262:30]
  wire  repeater_io_repeat; // @[Fragmenter.scala 262:30]
  wire  repeater_io_full; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
  wire [28:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
  wire [28:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
  reg [3:0] acknum; // @[Fragmenter.scala 189:29]
  reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
  reg  dToggle; // @[Fragmenter.scala 191:30]
  wire [3:0] dFragnum = auto_out_d_bits_source[3:0]; // @[Fragmenter.scala 192:41]
  wire  dFirst = acknum == 4'h0; // @[Fragmenter.scala 193:29]
  wire  dLast = dFragnum == 4'h0; // @[Fragmenter.scala 194:30]
  wire [3:0] _dsizeOH_T = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 64:12]
  wire [2:0] dsizeOH = _dsizeOH_T[2:0]; // @[OneHot.scala 64:27]
  wire [4:0] _dsizeOH1_T_1 = 5'h3 << auto_out_d_bits_size; // @[package.scala 234:77]
  wire [1:0] dsizeOH1 = ~_dsizeOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  dHasData = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  _T_5 = ~reset; // @[Fragmenter.scala 202:16]
  wire  ack_decrement = dHasData | dsizeOH[2]; // @[Fragmenter.scala 204:32]
  wire [5:0] _dFirst_size_T = {dFragnum, 2'h0}; // @[Fragmenter.scala 206:47]
  wire [5:0] _GEN_7 = {{4'd0}, dsizeOH1}; // @[Fragmenter.scala 206:69]
  wire [5:0] _dFirst_size_T_1 = _dFirst_size_T | _GEN_7; // @[Fragmenter.scala 206:69]
  wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala 232:35]
  wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
  wire [6:0] _dFirst_size_T_4 = {1'h0,_dFirst_size_T_1}; // @[Cat.scala 31:58]
  wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
  wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
  wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
  wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
  wire [3:0] _GEN_8 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
  wire [3:0] _dFirst_size_T_8 = _GEN_8 | dFirst_size_lo; // @[OneHot.scala 32:28]
  wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
  wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
  wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
  wire  drop = ~dHasData & ~dLast; // @[Fragmenter.scala 222:30]
  wire  bundleOut_0_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  wire  _T_7 = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
  wire [3:0] _GEN_9 = {{3'd0}, ack_decrement}; // @[Fragmenter.scala 209:55]
  wire [3:0] _acknum_T_1 = acknum - _GEN_9; // @[Fragmenter.scala 209:55]
  wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h2 ? 3'h2 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
  wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
  wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
  wire [8:0] _aFragOH1_T_1 = 9'h3 << aFrag; // @[package.scala 234:77]
  wire [1:0] aFragOH1 = ~_aFragOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  aHasData = ~repeater_io_deq_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] gennum; // @[Fragmenter.scala 291:29]
  wire  aFirst = gennum == 4'h0; // @[Fragmenter.scala 292:29]
  wire [3:0] _old_gennum1_T_2 = gennum - 4'h1; // @[Fragmenter.scala 293:79]
  wire [3:0] old_gennum1 = aFirst ? aOrigOH1[5:2] : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
  wire [3:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
  wire [3:0] new_gennum = ~_new_gennum_T; // @[Fragmenter.scala 294:26]
  reg  aToggle_r; // @[Reg.scala 16:16]
  wire  _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
  wire  aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
  wire  bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  wire  _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
  wire  _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala 302:31]
  wire [5:0] _bundleOut_0_a_bits_address_T = {old_gennum1, 2'h0}; // @[Fragmenter.scala 304:65]
  wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
  wire [5:0] _bundleOut_0_a_bits_address_T_2 = _bundleOut_0_a_bits_address_T | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
  wire [5:0] _GEN_10 = {{4'd0}, aFragOH1}; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_10; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_4 = _bundleOut_0_a_bits_address_T_3 | 6'h3; // @[Fragmenter.scala 304:111]
  wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_4; // @[Fragmenter.scala 304:51]
  wire [28:0] _GEN_11 = {{23'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
  wire [2:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aToggle}; // @[Cat.scala 31:58]
  wire  _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
  TLMonitor_23 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  Repeater repeater ( // @[Fragmenter.scala 262:30]
    .clock(repeater_clock),
    .reset(repeater_reset),
    .io_repeat(repeater_io_repeat),
    .io_full(repeater_io_full),
    .io_enq_ready(repeater_io_enq_ready),
    .io_enq_valid(repeater_io_enq_valid),
    .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
    .io_enq_bits_param(repeater_io_enq_bits_param),
    .io_enq_bits_size(repeater_io_enq_bits_size),
    .io_enq_bits_source(repeater_io_enq_bits_source),
    .io_enq_bits_address(repeater_io_enq_bits_address),
    .io_enq_bits_mask(repeater_io_enq_bits_mask),
    .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
    .io_deq_ready(repeater_io_deq_ready),
    .io_deq_valid(repeater_io_deq_valid),
    .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
    .io_deq_bits_param(repeater_io_deq_bits_param),
    .io_deq_bits_size(repeater_io_deq_bits_size),
    .io_deq_bits_source(repeater_io_deq_bits_source),
    .io_deq_bits_address(repeater_io_deq_bits_address),
    .io_deq_bits_mask(repeater_io_deq_bits_mask),
    .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
  );
  assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign auto_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign auto_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_size = aFrag[1:0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
  assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,new_gennum}; // @[Cat.scala 31:58]
  assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_11; // @[Fragmenter.scala 304:49]
  assign auto_out_a_bits_mask = repeater_io_full ? 4'hf : auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = repeater_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign repeater_clock = clock;
  assign repeater_reset = reset;
  assign repeater_io_repeat = ~aHasData & new_gennum != 4'h0; // @[Fragmenter.scala 302:41]
  assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  always @(posedge clock) begin
    if (reset) begin // @[Fragmenter.scala 189:29]
      acknum <= 4'h0; // @[Fragmenter.scala 189:29]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 209:24]
        acknum <= dFragnum;
      end else begin
        acknum <= _acknum_T_1;
      end
    end
    if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
      end
    end
    if (reset) begin // @[Fragmenter.scala 191:30]
      dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dToggle <= auto_out_d_bits_source[4]; // @[Fragmenter.scala 212:21]
      end
    end
    if (reset) begin // @[Fragmenter.scala 291:29]
      gennum <= 4'h0; // @[Fragmenter.scala 291:29]
    end else if (_T_8) begin // @[Fragmenter.scala 300:29]
      gennum <= new_gennum; // @[Fragmenter.scala 300:38]
    end
    if (aFirst) begin // @[Reg.scala 17:18]
      aToggle_r <= dToggle; // @[Reg.scala 17:22]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~repeater_io_full | _repeater_io_repeat_T) & _T_5) begin
          $fatal; // @[Fragmenter.scala 309:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(~repeater_io_full | _repeater_io_repeat_T)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Fragmenter.scala:309 assert (!repeater.io.full || !aHasData)\n"
            ); // @[Fragmenter.scala 309:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_9 | repeater_io_deq_bits_mask == 4'hf) & _T_5) begin
          $fatal; // @[Fragmenter.scala 312:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask == 4'hf)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
            ); // @[Fragmenter.scala 312:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  acknum = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  dOrig = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  dToggle = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  gennum = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  aToggle_r = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLInterconnectCoupler_18(
  input         clock,
  input         reset,
  input         auto_control_xing_out_a_ready,
  output        auto_control_xing_out_a_valid,
  output [2:0]  auto_control_xing_out_a_bits_opcode,
  output [2:0]  auto_control_xing_out_a_bits_param,
  output [1:0]  auto_control_xing_out_a_bits_size,
  output [6:0]  auto_control_xing_out_a_bits_source,
  output [28:0] auto_control_xing_out_a_bits_address,
  output [3:0]  auto_control_xing_out_a_bits_mask,
  output [31:0] auto_control_xing_out_a_bits_data,
  output        auto_control_xing_out_a_bits_corrupt,
  output        auto_control_xing_out_d_ready,
  input         auto_control_xing_out_d_valid,
  input  [2:0]  auto_control_xing_out_d_bits_opcode,
  input  [1:0]  auto_control_xing_out_d_bits_size,
  input  [6:0]  auto_control_xing_out_d_bits_source,
  input  [31:0] auto_control_xing_out_d_bits_data,
  output        auto_tl_in_a_ready,
  input         auto_tl_in_a_valid,
  input  [2:0]  auto_tl_in_a_bits_opcode,
  input  [2:0]  auto_tl_in_a_bits_param,
  input  [2:0]  auto_tl_in_a_bits_size,
  input  [1:0]  auto_tl_in_a_bits_source,
  input  [28:0] auto_tl_in_a_bits_address,
  input  [3:0]  auto_tl_in_a_bits_mask,
  input  [31:0] auto_tl_in_a_bits_data,
  input         auto_tl_in_a_bits_corrupt,
  input         auto_tl_in_d_ready,
  output        auto_tl_in_d_valid,
  output [2:0]  auto_tl_in_d_bits_opcode,
  output [2:0]  auto_tl_in_d_bits_size,
  output [1:0]  auto_tl_in_d_bits_source,
  output [31:0] auto_tl_in_d_bits_data
);
  wire  fragmenter_clock; // @[Fragmenter.scala 333:34]
  wire  fragmenter_reset; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [28:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [28:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
  TLFragmenter_14 fragmenter ( // @[Fragmenter.scala 333:34]
    .clock(fragmenter_clock),
    .reset(fragmenter_reset),
    .auto_in_a_ready(fragmenter_auto_in_a_ready),
    .auto_in_a_valid(fragmenter_auto_in_a_valid),
    .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
    .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
    .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
    .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
    .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
    .auto_in_a_bits_data(fragmenter_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
    .auto_in_d_ready(fragmenter_auto_in_d_ready),
    .auto_in_d_valid(fragmenter_auto_in_d_valid),
    .auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
    .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
    .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
    .auto_out_a_ready(fragmenter_auto_out_a_ready),
    .auto_out_a_valid(fragmenter_auto_out_a_valid),
    .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
    .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
    .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
    .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
    .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
    .auto_out_a_bits_data(fragmenter_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
    .auto_out_d_ready(fragmenter_auto_out_d_ready),
    .auto_out_d_valid(fragmenter_auto_out_d_valid),
    .auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
    .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
    .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
  );
  assign auto_control_xing_out_a_valid = fragmenter_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_data = fragmenter_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_out_d_ready = fragmenter_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_in_a_ready = fragmenter_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_valid = fragmenter_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_size = fragmenter_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_source = fragmenter_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_data = fragmenter_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign fragmenter_clock = clock;
  assign fragmenter_reset = reset;
  assign fragmenter_auto_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_data = auto_tl_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_out_a_ready = auto_control_xing_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_valid = auto_control_xing_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_opcode = auto_control_xing_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_size = auto_control_xing_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_source = auto_control_xing_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_data = auto_control_xing_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
endmodule
module PeripheryBus(
  input         auto_coupler_to_device_named_i2c_1_control_xing_out_a_ready,
  output        auto_coupler_to_device_named_i2c_1_control_xing_out_a_valid,
  output [2:0]  auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_opcode,
  output [2:0]  auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_param,
  output [1:0]  auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_size,
  output [6:0]  auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_source,
  output [28:0] auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_address,
  output [3:0]  auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_mask,
  output [31:0] auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_data,
  output        auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_corrupt,
  output        auto_coupler_to_device_named_i2c_1_control_xing_out_d_ready,
  input         auto_coupler_to_device_named_i2c_1_control_xing_out_d_valid,
  input  [2:0]  auto_coupler_to_device_named_i2c_1_control_xing_out_d_bits_opcode,
  input  [1:0]  auto_coupler_to_device_named_i2c_1_control_xing_out_d_bits_size,
  input  [6:0]  auto_coupler_to_device_named_i2c_1_control_xing_out_d_bits_source,
  input  [31:0] auto_coupler_to_device_named_i2c_1_control_xing_out_d_bits_data,
  input         auto_coupler_to_device_named_i2c_0_control_xing_out_a_ready,
  output        auto_coupler_to_device_named_i2c_0_control_xing_out_a_valid,
  output [2:0]  auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_opcode,
  output [2:0]  auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_param,
  output [1:0]  auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_size,
  output [6:0]  auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_source,
  output [28:0] auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_address,
  output [3:0]  auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_mask,
  output [31:0] auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_data,
  output        auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_corrupt,
  output        auto_coupler_to_device_named_i2c_0_control_xing_out_d_ready,
  input         auto_coupler_to_device_named_i2c_0_control_xing_out_d_valid,
  input  [2:0]  auto_coupler_to_device_named_i2c_0_control_xing_out_d_bits_opcode,
  input  [1:0]  auto_coupler_to_device_named_i2c_0_control_xing_out_d_bits_size,
  input  [6:0]  auto_coupler_to_device_named_i2c_0_control_xing_out_d_bits_source,
  input  [31:0] auto_coupler_to_device_named_i2c_0_control_xing_out_d_bits_data,
  input         auto_coupler_to_device_named_pwm_2_control_xing_out_a_ready,
  output        auto_coupler_to_device_named_pwm_2_control_xing_out_a_valid,
  output [2:0]  auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_opcode,
  output [2:0]  auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_param,
  output [1:0]  auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_size,
  output [6:0]  auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_source,
  output [28:0] auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_address,
  output [3:0]  auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_mask,
  output [31:0] auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_data,
  output        auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_corrupt,
  output        auto_coupler_to_device_named_pwm_2_control_xing_out_d_ready,
  input         auto_coupler_to_device_named_pwm_2_control_xing_out_d_valid,
  input  [2:0]  auto_coupler_to_device_named_pwm_2_control_xing_out_d_bits_opcode,
  input  [1:0]  auto_coupler_to_device_named_pwm_2_control_xing_out_d_bits_size,
  input  [6:0]  auto_coupler_to_device_named_pwm_2_control_xing_out_d_bits_source,
  input  [31:0] auto_coupler_to_device_named_pwm_2_control_xing_out_d_bits_data,
  input         auto_coupler_to_device_named_pwm_1_control_xing_out_a_ready,
  output        auto_coupler_to_device_named_pwm_1_control_xing_out_a_valid,
  output [2:0]  auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_opcode,
  output [2:0]  auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_param,
  output [1:0]  auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_size,
  output [6:0]  auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_source,
  output [28:0] auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_address,
  output [3:0]  auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_mask,
  output [31:0] auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_data,
  output        auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_corrupt,
  output        auto_coupler_to_device_named_pwm_1_control_xing_out_d_ready,
  input         auto_coupler_to_device_named_pwm_1_control_xing_out_d_valid,
  input  [2:0]  auto_coupler_to_device_named_pwm_1_control_xing_out_d_bits_opcode,
  input  [1:0]  auto_coupler_to_device_named_pwm_1_control_xing_out_d_bits_size,
  input  [6:0]  auto_coupler_to_device_named_pwm_1_control_xing_out_d_bits_source,
  input  [31:0] auto_coupler_to_device_named_pwm_1_control_xing_out_d_bits_data,
  input         auto_coupler_to_device_named_pwm_0_control_xing_out_a_ready,
  output        auto_coupler_to_device_named_pwm_0_control_xing_out_a_valid,
  output [2:0]  auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_opcode,
  output [2:0]  auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_param,
  output [1:0]  auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_size,
  output [6:0]  auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_source,
  output [28:0] auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_address,
  output [3:0]  auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_mask,
  output [31:0] auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_data,
  output        auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_corrupt,
  output        auto_coupler_to_device_named_pwm_0_control_xing_out_d_ready,
  input         auto_coupler_to_device_named_pwm_0_control_xing_out_d_valid,
  input  [2:0]  auto_coupler_to_device_named_pwm_0_control_xing_out_d_bits_opcode,
  input  [1:0]  auto_coupler_to_device_named_pwm_0_control_xing_out_d_bits_size,
  input  [6:0]  auto_coupler_to_device_named_pwm_0_control_xing_out_d_bits_source,
  input  [31:0] auto_coupler_to_device_named_pwm_0_control_xing_out_d_bits_data,
  input         auto_coupler_to_device_named_gpio_0_control_xing_out_a_ready,
  output        auto_coupler_to_device_named_gpio_0_control_xing_out_a_valid,
  output [2:0]  auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_opcode,
  output [2:0]  auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_param,
  output [1:0]  auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_size,
  output [6:0]  auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_source,
  output [28:0] auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_address,
  output [3:0]  auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_mask,
  output [31:0] auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_data,
  output        auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_corrupt,
  output        auto_coupler_to_device_named_gpio_0_control_xing_out_d_ready,
  input         auto_coupler_to_device_named_gpio_0_control_xing_out_d_valid,
  input  [2:0]  auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_opcode,
  input  [1:0]  auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_size,
  input  [6:0]  auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_source,
  input  [31:0] auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_data,
  input         auto_coupler_to_device_named_spi_0_control_xing_out_a_ready,
  output        auto_coupler_to_device_named_spi_0_control_xing_out_a_valid,
  output [2:0]  auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_opcode,
  output [2:0]  auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_param,
  output [1:0]  auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_size,
  output [6:0]  auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_source,
  output [28:0] auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_address,
  output [3:0]  auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_mask,
  output [31:0] auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_data,
  output        auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_corrupt,
  output        auto_coupler_to_device_named_spi_0_control_xing_out_d_ready,
  input         auto_coupler_to_device_named_spi_0_control_xing_out_d_valid,
  input  [2:0]  auto_coupler_to_device_named_spi_0_control_xing_out_d_bits_opcode,
  input  [1:0]  auto_coupler_to_device_named_spi_0_control_xing_out_d_bits_size,
  input  [6:0]  auto_coupler_to_device_named_spi_0_control_xing_out_d_bits_source,
  input  [31:0] auto_coupler_to_device_named_spi_0_control_xing_out_d_bits_data,
  input         auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_ready,
  output        auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_valid,
  output [2:0]  auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_opcode,
  output [2:0]  auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_param,
  output [1:0]  auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_size,
  output [6:0]  auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_source,
  output [28:0] auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_address,
  output [3:0]  auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_mask,
  output [31:0] auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_data,
  output        auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_corrupt,
  output        auto_coupler_to_device_named_qspi_ram_0_control_xing_out_d_ready,
  input         auto_coupler_to_device_named_qspi_ram_0_control_xing_out_d_valid,
  input  [2:0]  auto_coupler_to_device_named_qspi_ram_0_control_xing_out_d_bits_opcode,
  input  [1:0]  auto_coupler_to_device_named_qspi_ram_0_control_xing_out_d_bits_size,
  input  [6:0]  auto_coupler_to_device_named_qspi_ram_0_control_xing_out_d_bits_source,
  input  [31:0] auto_coupler_to_device_named_qspi_ram_0_control_xing_out_d_bits_data,
  input         auto_coupler_to_device_named_qspi_0_mem_xing_out_a_ready,
  output        auto_coupler_to_device_named_qspi_0_mem_xing_out_a_valid,
  output [2:0]  auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_opcode,
  output [2:0]  auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_param,
  output        auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_size,
  output [8:0]  auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_source,
  output [29:0] auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_address,
  output        auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_mask,
  output        auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_corrupt,
  output        auto_coupler_to_device_named_qspi_0_mem_xing_out_d_ready,
  input         auto_coupler_to_device_named_qspi_0_mem_xing_out_d_valid,
  input         auto_coupler_to_device_named_qspi_0_mem_xing_out_d_bits_size,
  input  [8:0]  auto_coupler_to_device_named_qspi_0_mem_xing_out_d_bits_source,
  input  [7:0]  auto_coupler_to_device_named_qspi_0_mem_xing_out_d_bits_data,
  input         auto_coupler_to_device_named_qspi_0_control_xing_out_a_ready,
  output        auto_coupler_to_device_named_qspi_0_control_xing_out_a_valid,
  output [2:0]  auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_opcode,
  output [2:0]  auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_param,
  output [1:0]  auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_size,
  output [6:0]  auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_source,
  output [28:0] auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_address,
  output [3:0]  auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_mask,
  output [31:0] auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_data,
  output        auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_corrupt,
  output        auto_coupler_to_device_named_qspi_0_control_xing_out_d_ready,
  input         auto_coupler_to_device_named_qspi_0_control_xing_out_d_valid,
  input  [2:0]  auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_opcode,
  input  [1:0]  auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_size,
  input  [6:0]  auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_source,
  input  [31:0] auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_data,
  input         auto_coupler_to_device_named_uart_4_control_xing_out_a_ready,
  output        auto_coupler_to_device_named_uart_4_control_xing_out_a_valid,
  output [2:0]  auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_opcode,
  output [2:0]  auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_param,
  output [1:0]  auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_size,
  output [6:0]  auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_source,
  output [28:0] auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_address,
  output [3:0]  auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_mask,
  output [31:0] auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_data,
  output        auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_corrupt,
  output        auto_coupler_to_device_named_uart_4_control_xing_out_d_ready,
  input         auto_coupler_to_device_named_uart_4_control_xing_out_d_valid,
  input  [2:0]  auto_coupler_to_device_named_uart_4_control_xing_out_d_bits_opcode,
  input  [1:0]  auto_coupler_to_device_named_uart_4_control_xing_out_d_bits_size,
  input  [6:0]  auto_coupler_to_device_named_uart_4_control_xing_out_d_bits_source,
  input  [31:0] auto_coupler_to_device_named_uart_4_control_xing_out_d_bits_data,
  input         auto_coupler_to_device_named_uart_3_control_xing_out_a_ready,
  output        auto_coupler_to_device_named_uart_3_control_xing_out_a_valid,
  output [2:0]  auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_opcode,
  output [2:0]  auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_param,
  output [1:0]  auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_size,
  output [6:0]  auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_source,
  output [28:0] auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_address,
  output [3:0]  auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_mask,
  output [31:0] auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_data,
  output        auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_corrupt,
  output        auto_coupler_to_device_named_uart_3_control_xing_out_d_ready,
  input         auto_coupler_to_device_named_uart_3_control_xing_out_d_valid,
  input  [2:0]  auto_coupler_to_device_named_uart_3_control_xing_out_d_bits_opcode,
  input  [1:0]  auto_coupler_to_device_named_uart_3_control_xing_out_d_bits_size,
  input  [6:0]  auto_coupler_to_device_named_uart_3_control_xing_out_d_bits_source,
  input  [31:0] auto_coupler_to_device_named_uart_3_control_xing_out_d_bits_data,
  input         auto_coupler_to_device_named_uart_2_control_xing_out_a_ready,
  output        auto_coupler_to_device_named_uart_2_control_xing_out_a_valid,
  output [2:0]  auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_opcode,
  output [2:0]  auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_param,
  output [1:0]  auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_size,
  output [6:0]  auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_source,
  output [28:0] auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_address,
  output [3:0]  auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_mask,
  output [31:0] auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_data,
  output        auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_corrupt,
  output        auto_coupler_to_device_named_uart_2_control_xing_out_d_ready,
  input         auto_coupler_to_device_named_uart_2_control_xing_out_d_valid,
  input  [2:0]  auto_coupler_to_device_named_uart_2_control_xing_out_d_bits_opcode,
  input  [1:0]  auto_coupler_to_device_named_uart_2_control_xing_out_d_bits_size,
  input  [6:0]  auto_coupler_to_device_named_uart_2_control_xing_out_d_bits_source,
  input  [31:0] auto_coupler_to_device_named_uart_2_control_xing_out_d_bits_data,
  input         auto_coupler_to_device_named_uart_1_control_xing_out_a_ready,
  output        auto_coupler_to_device_named_uart_1_control_xing_out_a_valid,
  output [2:0]  auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_opcode,
  output [2:0]  auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_param,
  output [1:0]  auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_size,
  output [6:0]  auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_source,
  output [28:0] auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_address,
  output [3:0]  auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_mask,
  output [31:0] auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_data,
  output        auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_corrupt,
  output        auto_coupler_to_device_named_uart_1_control_xing_out_d_ready,
  input         auto_coupler_to_device_named_uart_1_control_xing_out_d_valid,
  input  [2:0]  auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_opcode,
  input  [1:0]  auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_size,
  input  [6:0]  auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_source,
  input  [31:0] auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_data,
  input         auto_coupler_to_device_named_uart_0_control_xing_out_a_ready,
  output        auto_coupler_to_device_named_uart_0_control_xing_out_a_valid,
  output [2:0]  auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode,
  output [2:0]  auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param,
  output [1:0]  auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size,
  output [6:0]  auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source,
  output [28:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address,
  output [3:0]  auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask,
  output [31:0] auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data,
  output        auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt,
  output        auto_coupler_to_device_named_uart_0_control_xing_out_d_ready,
  input         auto_coupler_to_device_named_uart_0_control_xing_out_d_valid,
  input  [2:0]  auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode,
  input  [1:0]  auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size,
  input  [6:0]  auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source,
  input  [31:0] auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data,
  output        auto_fixedClockNode_out_13_clock,
  output        auto_fixedClockNode_out_13_reset,
  output        auto_fixedClockNode_out_12_clock,
  output        auto_fixedClockNode_out_12_reset,
  output        auto_fixedClockNode_out_11_clock,
  output        auto_fixedClockNode_out_11_reset,
  output        auto_fixedClockNode_out_10_clock,
  output        auto_fixedClockNode_out_10_reset,
  output        auto_fixedClockNode_out_9_clock,
  output        auto_fixedClockNode_out_9_reset,
  output        auto_fixedClockNode_out_8_clock,
  output        auto_fixedClockNode_out_8_reset,
  output        auto_fixedClockNode_out_7_clock,
  output        auto_fixedClockNode_out_7_reset,
  output        auto_fixedClockNode_out_6_clock,
  output        auto_fixedClockNode_out_6_reset,
  output        auto_fixedClockNode_out_5_clock,
  output        auto_fixedClockNode_out_5_reset,
  output        auto_fixedClockNode_out_4_clock,
  output        auto_fixedClockNode_out_4_reset,
  output        auto_fixedClockNode_out_3_clock,
  output        auto_fixedClockNode_out_3_reset,
  output        auto_fixedClockNode_out_2_clock,
  output        auto_fixedClockNode_out_2_reset,
  output        auto_fixedClockNode_out_1_clock,
  output        auto_fixedClockNode_out_1_reset,
  output        auto_fixedClockNode_out_0_clock,
  output        auto_fixedClockNode_out_0_reset,
  input         auto_subsystem_pbus_clock_groups_in_member_subsystem_pbus_0_clock,
  input         auto_subsystem_pbus_clock_groups_in_member_subsystem_pbus_0_reset,
  output        auto_bus_xing_in_a_ready,
  input         auto_bus_xing_in_a_valid,
  input  [2:0]  auto_bus_xing_in_a_bits_opcode,
  input  [2:0]  auto_bus_xing_in_a_bits_param,
  input  [2:0]  auto_bus_xing_in_a_bits_size,
  input  [1:0]  auto_bus_xing_in_a_bits_source,
  input  [29:0] auto_bus_xing_in_a_bits_address,
  input  [3:0]  auto_bus_xing_in_a_bits_mask,
  input  [31:0] auto_bus_xing_in_a_bits_data,
  input         auto_bus_xing_in_a_bits_corrupt,
  input         auto_bus_xing_in_d_ready,
  output        auto_bus_xing_in_d_valid,
  output [2:0]  auto_bus_xing_in_d_bits_opcode,
  output [1:0]  auto_bus_xing_in_d_bits_param,
  output [2:0]  auto_bus_xing_in_d_bits_size,
  output [1:0]  auto_bus_xing_in_d_bits_source,
  output        auto_bus_xing_in_d_bits_sink,
  output        auto_bus_xing_in_d_bits_denied,
  output [31:0] auto_bus_xing_in_d_bits_data,
  output        auto_bus_xing_in_d_bits_corrupt
);
  wire  subsystem_pbus_clock_groups_auto_in_member_subsystem_pbus_0_clock; // @[BusWrapper.scala 40:48]
  wire  subsystem_pbus_clock_groups_auto_in_member_subsystem_pbus_0_reset; // @[BusWrapper.scala 40:48]
  wire  subsystem_pbus_clock_groups_auto_out_member_subsystem_pbus_0_clock; // @[BusWrapper.scala 40:48]
  wire  subsystem_pbus_clock_groups_auto_out_member_subsystem_pbus_0_reset; // @[BusWrapper.scala 40:48]
  wire  clockGroup_auto_in_member_subsystem_pbus_0_clock; // @[BusWrapper.scala 41:38]
  wire  clockGroup_auto_in_member_subsystem_pbus_0_reset; // @[BusWrapper.scala 41:38]
  wire  clockGroup_auto_out_clock; // @[BusWrapper.scala 41:38]
  wire  clockGroup_auto_out_reset; // @[BusWrapper.scala 41:38]
  wire  fixedClockNode_auto_in_clock; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_in_reset; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_14_clock; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_14_reset; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_13_clock; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_13_reset; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_12_clock; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_12_reset; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_11_clock; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_11_reset; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_10_clock; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_10_reset; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_9_clock; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_9_reset; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_8_clock; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_8_reset; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_7_clock; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_7_reset; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_6_clock; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_6_reset; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_5_clock; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_5_reset; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_4_clock; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_4_reset; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_3_clock; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_3_reset; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_2_clock; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_2_reset; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_1_clock; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_1_reset; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_0_clock; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_0_reset; // @[ClockGroup.scala 106:107]
  wire  fixer_clock; // @[PeripheryBus.scala 47:33]
  wire  fixer_reset; // @[PeripheryBus.scala 47:33]
  wire  fixer_auto_in_a_ready; // @[PeripheryBus.scala 47:33]
  wire  fixer_auto_in_a_valid; // @[PeripheryBus.scala 47:33]
  wire [2:0] fixer_auto_in_a_bits_opcode; // @[PeripheryBus.scala 47:33]
  wire [2:0] fixer_auto_in_a_bits_param; // @[PeripheryBus.scala 47:33]
  wire [2:0] fixer_auto_in_a_bits_size; // @[PeripheryBus.scala 47:33]
  wire [1:0] fixer_auto_in_a_bits_source; // @[PeripheryBus.scala 47:33]
  wire [29:0] fixer_auto_in_a_bits_address; // @[PeripheryBus.scala 47:33]
  wire [3:0] fixer_auto_in_a_bits_mask; // @[PeripheryBus.scala 47:33]
  wire [31:0] fixer_auto_in_a_bits_data; // @[PeripheryBus.scala 47:33]
  wire  fixer_auto_in_a_bits_corrupt; // @[PeripheryBus.scala 47:33]
  wire  fixer_auto_in_d_ready; // @[PeripheryBus.scala 47:33]
  wire  fixer_auto_in_d_valid; // @[PeripheryBus.scala 47:33]
  wire [2:0] fixer_auto_in_d_bits_opcode; // @[PeripheryBus.scala 47:33]
  wire [2:0] fixer_auto_in_d_bits_size; // @[PeripheryBus.scala 47:33]
  wire [1:0] fixer_auto_in_d_bits_source; // @[PeripheryBus.scala 47:33]
  wire [31:0] fixer_auto_in_d_bits_data; // @[PeripheryBus.scala 47:33]
  wire  fixer_auto_out_a_ready; // @[PeripheryBus.scala 47:33]
  wire  fixer_auto_out_a_valid; // @[PeripheryBus.scala 47:33]
  wire [2:0] fixer_auto_out_a_bits_opcode; // @[PeripheryBus.scala 47:33]
  wire [2:0] fixer_auto_out_a_bits_param; // @[PeripheryBus.scala 47:33]
  wire [2:0] fixer_auto_out_a_bits_size; // @[PeripheryBus.scala 47:33]
  wire [1:0] fixer_auto_out_a_bits_source; // @[PeripheryBus.scala 47:33]
  wire [29:0] fixer_auto_out_a_bits_address; // @[PeripheryBus.scala 47:33]
  wire [3:0] fixer_auto_out_a_bits_mask; // @[PeripheryBus.scala 47:33]
  wire [31:0] fixer_auto_out_a_bits_data; // @[PeripheryBus.scala 47:33]
  wire  fixer_auto_out_a_bits_corrupt; // @[PeripheryBus.scala 47:33]
  wire  fixer_auto_out_d_ready; // @[PeripheryBus.scala 47:33]
  wire  fixer_auto_out_d_valid; // @[PeripheryBus.scala 47:33]
  wire [2:0] fixer_auto_out_d_bits_opcode; // @[PeripheryBus.scala 47:33]
  wire [2:0] fixer_auto_out_d_bits_size; // @[PeripheryBus.scala 47:33]
  wire [1:0] fixer_auto_out_d_bits_source; // @[PeripheryBus.scala 47:33]
  wire [31:0] fixer_auto_out_d_bits_data; // @[PeripheryBus.scala 47:33]
  wire  in_xbar_auto_in_a_ready; // @[PeripheryBus.scala 49:29]
  wire  in_xbar_auto_in_a_valid; // @[PeripheryBus.scala 49:29]
  wire [2:0] in_xbar_auto_in_a_bits_opcode; // @[PeripheryBus.scala 49:29]
  wire [2:0] in_xbar_auto_in_a_bits_param; // @[PeripheryBus.scala 49:29]
  wire [2:0] in_xbar_auto_in_a_bits_size; // @[PeripheryBus.scala 49:29]
  wire [1:0] in_xbar_auto_in_a_bits_source; // @[PeripheryBus.scala 49:29]
  wire [29:0] in_xbar_auto_in_a_bits_address; // @[PeripheryBus.scala 49:29]
  wire [3:0] in_xbar_auto_in_a_bits_mask; // @[PeripheryBus.scala 49:29]
  wire [31:0] in_xbar_auto_in_a_bits_data; // @[PeripheryBus.scala 49:29]
  wire  in_xbar_auto_in_a_bits_corrupt; // @[PeripheryBus.scala 49:29]
  wire  in_xbar_auto_in_d_ready; // @[PeripheryBus.scala 49:29]
  wire  in_xbar_auto_in_d_valid; // @[PeripheryBus.scala 49:29]
  wire [2:0] in_xbar_auto_in_d_bits_opcode; // @[PeripheryBus.scala 49:29]
  wire [1:0] in_xbar_auto_in_d_bits_param; // @[PeripheryBus.scala 49:29]
  wire [2:0] in_xbar_auto_in_d_bits_size; // @[PeripheryBus.scala 49:29]
  wire [1:0] in_xbar_auto_in_d_bits_source; // @[PeripheryBus.scala 49:29]
  wire  in_xbar_auto_in_d_bits_sink; // @[PeripheryBus.scala 49:29]
  wire  in_xbar_auto_in_d_bits_denied; // @[PeripheryBus.scala 49:29]
  wire [31:0] in_xbar_auto_in_d_bits_data; // @[PeripheryBus.scala 49:29]
  wire  in_xbar_auto_in_d_bits_corrupt; // @[PeripheryBus.scala 49:29]
  wire  in_xbar_auto_out_a_ready; // @[PeripheryBus.scala 49:29]
  wire  in_xbar_auto_out_a_valid; // @[PeripheryBus.scala 49:29]
  wire [2:0] in_xbar_auto_out_a_bits_opcode; // @[PeripheryBus.scala 49:29]
  wire [2:0] in_xbar_auto_out_a_bits_param; // @[PeripheryBus.scala 49:29]
  wire [2:0] in_xbar_auto_out_a_bits_size; // @[PeripheryBus.scala 49:29]
  wire [1:0] in_xbar_auto_out_a_bits_source; // @[PeripheryBus.scala 49:29]
  wire [29:0] in_xbar_auto_out_a_bits_address; // @[PeripheryBus.scala 49:29]
  wire [3:0] in_xbar_auto_out_a_bits_mask; // @[PeripheryBus.scala 49:29]
  wire [31:0] in_xbar_auto_out_a_bits_data; // @[PeripheryBus.scala 49:29]
  wire  in_xbar_auto_out_a_bits_corrupt; // @[PeripheryBus.scala 49:29]
  wire  in_xbar_auto_out_d_ready; // @[PeripheryBus.scala 49:29]
  wire  in_xbar_auto_out_d_valid; // @[PeripheryBus.scala 49:29]
  wire [2:0] in_xbar_auto_out_d_bits_opcode; // @[PeripheryBus.scala 49:29]
  wire [1:0] in_xbar_auto_out_d_bits_param; // @[PeripheryBus.scala 49:29]
  wire [2:0] in_xbar_auto_out_d_bits_size; // @[PeripheryBus.scala 49:29]
  wire [1:0] in_xbar_auto_out_d_bits_source; // @[PeripheryBus.scala 49:29]
  wire  in_xbar_auto_out_d_bits_sink; // @[PeripheryBus.scala 49:29]
  wire  in_xbar_auto_out_d_bits_denied; // @[PeripheryBus.scala 49:29]
  wire [31:0] in_xbar_auto_out_d_bits_data; // @[PeripheryBus.scala 49:29]
  wire  in_xbar_auto_out_d_bits_corrupt; // @[PeripheryBus.scala 49:29]
  wire  out_xbar_clock; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_reset; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_in_a_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_in_a_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_in_a_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_in_a_bits_param; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_in_a_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_in_a_bits_source; // @[PeripheryBus.scala 50:30]
  wire [29:0] out_xbar_auto_in_a_bits_address; // @[PeripheryBus.scala 50:30]
  wire [3:0] out_xbar_auto_in_a_bits_mask; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_in_a_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_in_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_in_d_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_in_d_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_in_d_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_in_d_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_in_d_bits_source; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_in_d_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_14_a_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_14_a_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_14_a_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_14_a_bits_param; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_14_a_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_14_a_bits_source; // @[PeripheryBus.scala 50:30]
  wire [28:0] out_xbar_auto_out_14_a_bits_address; // @[PeripheryBus.scala 50:30]
  wire [3:0] out_xbar_auto_out_14_a_bits_mask; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_14_a_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_14_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_14_d_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_14_d_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_14_d_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_14_d_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_14_d_bits_source; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_14_d_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_13_a_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_13_a_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_13_a_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_13_a_bits_param; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_13_a_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_13_a_bits_source; // @[PeripheryBus.scala 50:30]
  wire [28:0] out_xbar_auto_out_13_a_bits_address; // @[PeripheryBus.scala 50:30]
  wire [3:0] out_xbar_auto_out_13_a_bits_mask; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_13_a_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_13_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_13_d_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_13_d_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_13_d_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_13_d_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_13_d_bits_source; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_13_d_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_12_a_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_12_a_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_12_a_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_12_a_bits_param; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_12_a_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_12_a_bits_source; // @[PeripheryBus.scala 50:30]
  wire [28:0] out_xbar_auto_out_12_a_bits_address; // @[PeripheryBus.scala 50:30]
  wire [3:0] out_xbar_auto_out_12_a_bits_mask; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_12_a_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_12_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_12_d_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_12_d_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_12_d_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_12_d_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_12_d_bits_source; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_12_d_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_11_a_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_11_a_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_11_a_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_11_a_bits_param; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_11_a_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_11_a_bits_source; // @[PeripheryBus.scala 50:30]
  wire [28:0] out_xbar_auto_out_11_a_bits_address; // @[PeripheryBus.scala 50:30]
  wire [3:0] out_xbar_auto_out_11_a_bits_mask; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_11_a_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_11_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_11_d_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_11_d_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_11_d_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_11_d_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_11_d_bits_source; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_11_d_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_10_a_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_10_a_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_10_a_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_10_a_bits_param; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_10_a_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_10_a_bits_source; // @[PeripheryBus.scala 50:30]
  wire [28:0] out_xbar_auto_out_10_a_bits_address; // @[PeripheryBus.scala 50:30]
  wire [3:0] out_xbar_auto_out_10_a_bits_mask; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_10_a_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_10_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_10_d_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_10_d_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_10_d_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_10_d_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_10_d_bits_source; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_10_d_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_9_a_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_9_a_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_9_a_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_9_a_bits_param; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_9_a_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_9_a_bits_source; // @[PeripheryBus.scala 50:30]
  wire [28:0] out_xbar_auto_out_9_a_bits_address; // @[PeripheryBus.scala 50:30]
  wire [3:0] out_xbar_auto_out_9_a_bits_mask; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_9_a_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_9_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_9_d_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_9_d_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_9_d_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_9_d_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_9_d_bits_source; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_9_d_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_8_a_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_8_a_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_8_a_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_8_a_bits_param; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_8_a_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_8_a_bits_source; // @[PeripheryBus.scala 50:30]
  wire [28:0] out_xbar_auto_out_8_a_bits_address; // @[PeripheryBus.scala 50:30]
  wire [3:0] out_xbar_auto_out_8_a_bits_mask; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_8_a_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_8_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_8_d_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_8_d_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_8_d_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_8_d_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_8_d_bits_source; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_8_d_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_7_a_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_7_a_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_7_a_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_7_a_bits_param; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_7_a_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_7_a_bits_source; // @[PeripheryBus.scala 50:30]
  wire [28:0] out_xbar_auto_out_7_a_bits_address; // @[PeripheryBus.scala 50:30]
  wire [3:0] out_xbar_auto_out_7_a_bits_mask; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_7_a_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_7_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_7_d_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_7_d_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_7_d_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_7_d_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_7_d_bits_source; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_7_d_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_6_a_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_6_a_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_6_a_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_6_a_bits_param; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_6_a_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_6_a_bits_source; // @[PeripheryBus.scala 50:30]
  wire [29:0] out_xbar_auto_out_6_a_bits_address; // @[PeripheryBus.scala 50:30]
  wire [3:0] out_xbar_auto_out_6_a_bits_mask; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_6_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_6_d_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_6_d_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_6_d_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_6_d_bits_source; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_6_d_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_5_a_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_5_a_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_5_a_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_5_a_bits_param; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_5_a_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_5_a_bits_source; // @[PeripheryBus.scala 50:30]
  wire [28:0] out_xbar_auto_out_5_a_bits_address; // @[PeripheryBus.scala 50:30]
  wire [3:0] out_xbar_auto_out_5_a_bits_mask; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_5_a_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_5_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_5_d_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_5_d_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_5_d_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_5_d_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_5_d_bits_source; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_5_d_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_4_a_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_4_a_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_4_a_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_4_a_bits_param; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_4_a_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_4_a_bits_source; // @[PeripheryBus.scala 50:30]
  wire [28:0] out_xbar_auto_out_4_a_bits_address; // @[PeripheryBus.scala 50:30]
  wire [3:0] out_xbar_auto_out_4_a_bits_mask; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_4_a_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_4_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_4_d_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_4_d_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_4_d_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_4_d_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_4_d_bits_source; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_4_d_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_3_a_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_3_a_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_3_a_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_3_a_bits_param; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_3_a_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_3_a_bits_source; // @[PeripheryBus.scala 50:30]
  wire [28:0] out_xbar_auto_out_3_a_bits_address; // @[PeripheryBus.scala 50:30]
  wire [3:0] out_xbar_auto_out_3_a_bits_mask; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_3_a_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_3_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_3_d_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_3_d_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_3_d_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_3_d_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_3_d_bits_source; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_3_d_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_2_a_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_2_a_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_2_a_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_2_a_bits_param; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_2_a_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_2_a_bits_source; // @[PeripheryBus.scala 50:30]
  wire [28:0] out_xbar_auto_out_2_a_bits_address; // @[PeripheryBus.scala 50:30]
  wire [3:0] out_xbar_auto_out_2_a_bits_mask; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_2_a_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_2_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_2_d_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_2_d_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_2_d_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_2_d_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_2_d_bits_source; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_2_d_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_1_a_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_1_a_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_1_a_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_1_a_bits_param; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_1_a_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_1_a_bits_source; // @[PeripheryBus.scala 50:30]
  wire [28:0] out_xbar_auto_out_1_a_bits_address; // @[PeripheryBus.scala 50:30]
  wire [3:0] out_xbar_auto_out_1_a_bits_mask; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_1_a_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_1_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_1_d_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_1_d_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_1_d_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_1_d_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_1_d_bits_source; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_1_d_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_0_a_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_0_a_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_0_a_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_0_a_bits_param; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_0_a_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_0_a_bits_source; // @[PeripheryBus.scala 50:30]
  wire [28:0] out_xbar_auto_out_0_a_bits_address; // @[PeripheryBus.scala 50:30]
  wire [3:0] out_xbar_auto_out_0_a_bits_mask; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_0_a_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_0_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_0_d_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_0_d_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_0_d_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_0_d_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_0_d_bits_source; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_0_d_bits_data; // @[PeripheryBus.scala 50:30]
  wire  buffer_clock; // @[Buffer.scala 68:28]
  wire  buffer_reset; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
  wire [29:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_bits_sink; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_bits_denied; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
  wire [29:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
  wire  atomics_clock; // @[AtomicAutomata.scala 283:29]
  wire  atomics_reset; // @[AtomicAutomata.scala 283:29]
  wire  atomics_auto_in_a_ready; // @[AtomicAutomata.scala 283:29]
  wire  atomics_auto_in_a_valid; // @[AtomicAutomata.scala 283:29]
  wire [2:0] atomics_auto_in_a_bits_opcode; // @[AtomicAutomata.scala 283:29]
  wire [2:0] atomics_auto_in_a_bits_param; // @[AtomicAutomata.scala 283:29]
  wire [2:0] atomics_auto_in_a_bits_size; // @[AtomicAutomata.scala 283:29]
  wire [1:0] atomics_auto_in_a_bits_source; // @[AtomicAutomata.scala 283:29]
  wire [29:0] atomics_auto_in_a_bits_address; // @[AtomicAutomata.scala 283:29]
  wire [3:0] atomics_auto_in_a_bits_mask; // @[AtomicAutomata.scala 283:29]
  wire [31:0] atomics_auto_in_a_bits_data; // @[AtomicAutomata.scala 283:29]
  wire  atomics_auto_in_a_bits_corrupt; // @[AtomicAutomata.scala 283:29]
  wire  atomics_auto_in_d_ready; // @[AtomicAutomata.scala 283:29]
  wire  atomics_auto_in_d_valid; // @[AtomicAutomata.scala 283:29]
  wire [2:0] atomics_auto_in_d_bits_opcode; // @[AtomicAutomata.scala 283:29]
  wire [1:0] atomics_auto_in_d_bits_param; // @[AtomicAutomata.scala 283:29]
  wire [2:0] atomics_auto_in_d_bits_size; // @[AtomicAutomata.scala 283:29]
  wire [1:0] atomics_auto_in_d_bits_source; // @[AtomicAutomata.scala 283:29]
  wire  atomics_auto_in_d_bits_sink; // @[AtomicAutomata.scala 283:29]
  wire  atomics_auto_in_d_bits_denied; // @[AtomicAutomata.scala 283:29]
  wire [31:0] atomics_auto_in_d_bits_data; // @[AtomicAutomata.scala 283:29]
  wire  atomics_auto_in_d_bits_corrupt; // @[AtomicAutomata.scala 283:29]
  wire  atomics_auto_out_a_ready; // @[AtomicAutomata.scala 283:29]
  wire  atomics_auto_out_a_valid; // @[AtomicAutomata.scala 283:29]
  wire [2:0] atomics_auto_out_a_bits_opcode; // @[AtomicAutomata.scala 283:29]
  wire [2:0] atomics_auto_out_a_bits_param; // @[AtomicAutomata.scala 283:29]
  wire [2:0] atomics_auto_out_a_bits_size; // @[AtomicAutomata.scala 283:29]
  wire [1:0] atomics_auto_out_a_bits_source; // @[AtomicAutomata.scala 283:29]
  wire [29:0] atomics_auto_out_a_bits_address; // @[AtomicAutomata.scala 283:29]
  wire [3:0] atomics_auto_out_a_bits_mask; // @[AtomicAutomata.scala 283:29]
  wire [31:0] atomics_auto_out_a_bits_data; // @[AtomicAutomata.scala 283:29]
  wire  atomics_auto_out_a_bits_corrupt; // @[AtomicAutomata.scala 283:29]
  wire  atomics_auto_out_d_ready; // @[AtomicAutomata.scala 283:29]
  wire  atomics_auto_out_d_valid; // @[AtomicAutomata.scala 283:29]
  wire [2:0] atomics_auto_out_d_bits_opcode; // @[AtomicAutomata.scala 283:29]
  wire [1:0] atomics_auto_out_d_bits_param; // @[AtomicAutomata.scala 283:29]
  wire [2:0] atomics_auto_out_d_bits_size; // @[AtomicAutomata.scala 283:29]
  wire [1:0] atomics_auto_out_d_bits_source; // @[AtomicAutomata.scala 283:29]
  wire  atomics_auto_out_d_bits_sink; // @[AtomicAutomata.scala 283:29]
  wire  atomics_auto_out_d_bits_denied; // @[AtomicAutomata.scala 283:29]
  wire [31:0] atomics_auto_out_d_bits_data; // @[AtomicAutomata.scala 283:29]
  wire  atomics_auto_out_d_bits_corrupt; // @[AtomicAutomata.scala 283:29]
  wire  buffer_1_clock; // @[Buffer.scala 68:28]
  wire  buffer_1_reset; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_in_a_bits_param; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_in_a_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_1_auto_in_a_bits_source; // @[Buffer.scala 68:28]
  wire [29:0] buffer_1_auto_in_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_1_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_1_auto_in_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_1_auto_in_d_bits_param; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_in_d_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_1_auto_in_d_bits_source; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_d_bits_sink; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_d_bits_denied; // @[Buffer.scala 68:28]
  wire [31:0] buffer_1_auto_in_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_d_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_out_a_bits_param; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_out_a_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_1_auto_out_a_bits_source; // @[Buffer.scala 68:28]
  wire [29:0] buffer_1_auto_out_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_1_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_1_auto_out_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_1_auto_out_d_bits_param; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_out_d_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_1_auto_out_d_bits_source; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_d_bits_sink; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_d_bits_denied; // @[Buffer.scala 68:28]
  wire [31:0] buffer_1_auto_out_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_d_bits_corrupt; // @[Buffer.scala 68:28]
  wire  coupler_to_device_named_uart_0_clock; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_0_reset; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_0_auto_control_xing_out_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_0_auto_control_xing_out_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 432:27]
  wire [28:0] coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_0_auto_control_xing_out_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_0_auto_control_xing_out_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_0_auto_control_xing_out_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_uart_0_auto_control_xing_out_d_bits_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_device_named_uart_0_auto_control_xing_out_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_uart_0_auto_control_xing_out_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_0_auto_tl_in_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_0_auto_tl_in_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_0_auto_tl_in_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_0_auto_tl_in_a_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_0_auto_tl_in_a_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_uart_0_auto_tl_in_a_bits_source; // @[LazyModule.scala 432:27]
  wire [28:0] coupler_to_device_named_uart_0_auto_tl_in_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_device_named_uart_0_auto_tl_in_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_uart_0_auto_tl_in_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_0_auto_tl_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_0_auto_tl_in_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_0_auto_tl_in_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_0_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_0_auto_tl_in_d_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_uart_0_auto_tl_in_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_uart_0_auto_tl_in_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_1_clock; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_1_reset; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_1_auto_control_xing_out_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_1_auto_control_xing_out_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 432:27]
  wire [28:0] coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_1_auto_control_xing_out_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_1_auto_control_xing_out_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_1_auto_control_xing_out_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_uart_1_auto_control_xing_out_d_bits_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_device_named_uart_1_auto_control_xing_out_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_uart_1_auto_control_xing_out_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_1_auto_tl_in_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_1_auto_tl_in_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_1_auto_tl_in_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_1_auto_tl_in_a_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_1_auto_tl_in_a_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_uart_1_auto_tl_in_a_bits_source; // @[LazyModule.scala 432:27]
  wire [28:0] coupler_to_device_named_uart_1_auto_tl_in_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_device_named_uart_1_auto_tl_in_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_uart_1_auto_tl_in_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_1_auto_tl_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_1_auto_tl_in_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_1_auto_tl_in_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_1_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_1_auto_tl_in_d_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_uart_1_auto_tl_in_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_uart_1_auto_tl_in_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_2_clock; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_2_reset; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_2_auto_control_xing_out_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_2_auto_control_xing_out_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_2_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_2_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_uart_2_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_device_named_uart_2_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 432:27]
  wire [28:0] coupler_to_device_named_uart_2_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_device_named_uart_2_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_uart_2_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_2_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_2_auto_control_xing_out_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_2_auto_control_xing_out_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_2_auto_control_xing_out_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_uart_2_auto_control_xing_out_d_bits_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_device_named_uart_2_auto_control_xing_out_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_uart_2_auto_control_xing_out_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_2_auto_tl_in_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_2_auto_tl_in_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_2_auto_tl_in_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_2_auto_tl_in_a_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_2_auto_tl_in_a_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_uart_2_auto_tl_in_a_bits_source; // @[LazyModule.scala 432:27]
  wire [28:0] coupler_to_device_named_uart_2_auto_tl_in_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_device_named_uart_2_auto_tl_in_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_uart_2_auto_tl_in_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_2_auto_tl_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_2_auto_tl_in_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_2_auto_tl_in_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_2_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_2_auto_tl_in_d_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_uart_2_auto_tl_in_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_uart_2_auto_tl_in_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_3_clock; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_3_reset; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_3_auto_control_xing_out_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_3_auto_control_xing_out_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_3_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_3_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_uart_3_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_device_named_uart_3_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 432:27]
  wire [28:0] coupler_to_device_named_uart_3_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_device_named_uart_3_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_uart_3_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_3_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_3_auto_control_xing_out_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_3_auto_control_xing_out_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_3_auto_control_xing_out_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_uart_3_auto_control_xing_out_d_bits_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_device_named_uart_3_auto_control_xing_out_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_uart_3_auto_control_xing_out_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_3_auto_tl_in_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_3_auto_tl_in_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_3_auto_tl_in_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_3_auto_tl_in_a_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_3_auto_tl_in_a_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_uart_3_auto_tl_in_a_bits_source; // @[LazyModule.scala 432:27]
  wire [28:0] coupler_to_device_named_uart_3_auto_tl_in_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_device_named_uart_3_auto_tl_in_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_uart_3_auto_tl_in_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_3_auto_tl_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_3_auto_tl_in_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_3_auto_tl_in_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_3_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_3_auto_tl_in_d_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_uart_3_auto_tl_in_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_uart_3_auto_tl_in_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_4_clock; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_4_reset; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_4_auto_control_xing_out_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_4_auto_control_xing_out_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_4_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_4_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_uart_4_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_device_named_uart_4_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 432:27]
  wire [28:0] coupler_to_device_named_uart_4_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_device_named_uart_4_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_uart_4_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_4_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_4_auto_control_xing_out_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_4_auto_control_xing_out_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_4_auto_control_xing_out_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_uart_4_auto_control_xing_out_d_bits_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_device_named_uart_4_auto_control_xing_out_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_uart_4_auto_control_xing_out_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_4_auto_tl_in_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_4_auto_tl_in_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_4_auto_tl_in_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_4_auto_tl_in_a_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_4_auto_tl_in_a_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_uart_4_auto_tl_in_a_bits_source; // @[LazyModule.scala 432:27]
  wire [28:0] coupler_to_device_named_uart_4_auto_tl_in_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_device_named_uart_4_auto_tl_in_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_uart_4_auto_tl_in_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_4_auto_tl_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_4_auto_tl_in_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_uart_4_auto_tl_in_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_4_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_uart_4_auto_tl_in_d_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_uart_4_auto_tl_in_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_uart_4_auto_tl_in_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_0_clock; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_0_reset; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_0_auto_control_xing_out_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_0_auto_control_xing_out_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 432:27]
  wire [28:0] coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_0_auto_control_xing_out_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_0_auto_control_xing_out_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_qspi_0_auto_control_xing_out_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_qspi_0_auto_control_xing_out_d_bits_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_device_named_qspi_0_auto_control_xing_out_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_qspi_0_auto_control_xing_out_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_0_auto_tl_in_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_0_auto_tl_in_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_qspi_0_auto_tl_in_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_qspi_0_auto_tl_in_a_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_qspi_0_auto_tl_in_a_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_qspi_0_auto_tl_in_a_bits_source; // @[LazyModule.scala 432:27]
  wire [28:0] coupler_to_device_named_qspi_0_auto_tl_in_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_device_named_qspi_0_auto_tl_in_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_qspi_0_auto_tl_in_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_0_auto_tl_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_0_auto_tl_in_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_0_auto_tl_in_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_qspi_0_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_qspi_0_auto_tl_in_d_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_qspi_0_auto_tl_in_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_qspi_0_auto_tl_in_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_0_1_clock; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_0_1_reset; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_param; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_size; // @[LazyModule.scala 432:27]
  wire [8:0] coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_source; // @[LazyModule.scala 432:27]
  wire [29:0] coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_address; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_mask; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_0_1_auto_mem_xing_out_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_0_1_auto_mem_xing_out_d_valid; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_0_1_auto_mem_xing_out_d_bits_size; // @[LazyModule.scala 432:27]
  wire [8:0] coupler_to_device_named_qspi_0_1_auto_mem_xing_out_d_bits_source; // @[LazyModule.scala 432:27]
  wire [7:0] coupler_to_device_named_qspi_0_1_auto_mem_xing_out_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_0_1_auto_tl_in_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_0_1_auto_tl_in_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_source; // @[LazyModule.scala 432:27]
  wire [29:0] coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_mask; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_0_1_auto_tl_in_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_0_1_auto_tl_in_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_qspi_0_1_auto_tl_in_d_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_qspi_0_1_auto_tl_in_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_qspi_0_1_auto_tl_in_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_ram_0_clock; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_ram_0_reset; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_ram_0_auto_control_xing_out_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_ram_0_auto_control_xing_out_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_qspi_ram_0_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_qspi_ram_0_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_qspi_ram_0_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_device_named_qspi_ram_0_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 432:27]
  wire [28:0] coupler_to_device_named_qspi_ram_0_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_device_named_qspi_ram_0_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_qspi_ram_0_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_ram_0_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_ram_0_auto_control_xing_out_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_ram_0_auto_control_xing_out_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_qspi_ram_0_auto_control_xing_out_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_qspi_ram_0_auto_control_xing_out_d_bits_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_device_named_qspi_ram_0_auto_control_xing_out_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_qspi_ram_0_auto_control_xing_out_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_ram_0_auto_tl_in_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_ram_0_auto_tl_in_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_source; // @[LazyModule.scala 432:27]
  wire [28:0] coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_ram_0_auto_tl_in_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_ram_0_auto_tl_in_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_qspi_ram_0_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_qspi_ram_0_auto_tl_in_d_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_qspi_ram_0_auto_tl_in_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_qspi_ram_0_auto_tl_in_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_spi_0_clock; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_spi_0_reset; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_spi_0_auto_control_xing_out_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_spi_0_auto_control_xing_out_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_spi_0_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_spi_0_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_spi_0_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_device_named_spi_0_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 432:27]
  wire [28:0] coupler_to_device_named_spi_0_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_device_named_spi_0_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_spi_0_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_spi_0_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_spi_0_auto_control_xing_out_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_spi_0_auto_control_xing_out_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_spi_0_auto_control_xing_out_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_spi_0_auto_control_xing_out_d_bits_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_device_named_spi_0_auto_control_xing_out_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_spi_0_auto_control_xing_out_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_spi_0_auto_tl_in_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_spi_0_auto_tl_in_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_spi_0_auto_tl_in_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_spi_0_auto_tl_in_a_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_spi_0_auto_tl_in_a_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_spi_0_auto_tl_in_a_bits_source; // @[LazyModule.scala 432:27]
  wire [28:0] coupler_to_device_named_spi_0_auto_tl_in_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_device_named_spi_0_auto_tl_in_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_spi_0_auto_tl_in_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_spi_0_auto_tl_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_spi_0_auto_tl_in_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_spi_0_auto_tl_in_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_spi_0_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_spi_0_auto_tl_in_d_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_spi_0_auto_tl_in_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_spi_0_auto_tl_in_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_gpio_0_clock; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_gpio_0_reset; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_gpio_0_auto_control_xing_out_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_gpio_0_auto_control_xing_out_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 432:27]
  wire [28:0] coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_gpio_0_auto_control_xing_out_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_gpio_0_auto_control_xing_out_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_gpio_0_auto_control_xing_out_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_gpio_0_auto_control_xing_out_d_bits_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_device_named_gpio_0_auto_control_xing_out_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_gpio_0_auto_control_xing_out_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_gpio_0_auto_tl_in_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_gpio_0_auto_tl_in_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_gpio_0_auto_tl_in_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_gpio_0_auto_tl_in_a_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_gpio_0_auto_tl_in_a_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_gpio_0_auto_tl_in_a_bits_source; // @[LazyModule.scala 432:27]
  wire [28:0] coupler_to_device_named_gpio_0_auto_tl_in_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_device_named_gpio_0_auto_tl_in_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_gpio_0_auto_tl_in_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_gpio_0_auto_tl_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_gpio_0_auto_tl_in_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_gpio_0_auto_tl_in_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_gpio_0_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_gpio_0_auto_tl_in_d_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_gpio_0_auto_tl_in_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_gpio_0_auto_tl_in_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_pwm_0_clock; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_pwm_0_reset; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_pwm_0_auto_control_xing_out_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_pwm_0_auto_control_xing_out_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_pwm_0_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_pwm_0_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_pwm_0_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_device_named_pwm_0_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 432:27]
  wire [28:0] coupler_to_device_named_pwm_0_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_device_named_pwm_0_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_pwm_0_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_pwm_0_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_pwm_0_auto_control_xing_out_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_pwm_0_auto_control_xing_out_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_pwm_0_auto_control_xing_out_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_pwm_0_auto_control_xing_out_d_bits_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_device_named_pwm_0_auto_control_xing_out_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_pwm_0_auto_control_xing_out_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_pwm_0_auto_tl_in_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_pwm_0_auto_tl_in_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_pwm_0_auto_tl_in_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_pwm_0_auto_tl_in_a_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_pwm_0_auto_tl_in_a_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_pwm_0_auto_tl_in_a_bits_source; // @[LazyModule.scala 432:27]
  wire [28:0] coupler_to_device_named_pwm_0_auto_tl_in_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_device_named_pwm_0_auto_tl_in_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_pwm_0_auto_tl_in_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_pwm_0_auto_tl_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_pwm_0_auto_tl_in_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_pwm_0_auto_tl_in_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_pwm_0_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_pwm_0_auto_tl_in_d_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_pwm_0_auto_tl_in_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_pwm_0_auto_tl_in_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_pwm_1_clock; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_pwm_1_reset; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_pwm_1_auto_control_xing_out_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_pwm_1_auto_control_xing_out_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_pwm_1_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_pwm_1_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_pwm_1_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_device_named_pwm_1_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 432:27]
  wire [28:0] coupler_to_device_named_pwm_1_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_device_named_pwm_1_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_pwm_1_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_pwm_1_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_pwm_1_auto_control_xing_out_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_pwm_1_auto_control_xing_out_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_pwm_1_auto_control_xing_out_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_pwm_1_auto_control_xing_out_d_bits_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_device_named_pwm_1_auto_control_xing_out_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_pwm_1_auto_control_xing_out_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_pwm_1_auto_tl_in_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_pwm_1_auto_tl_in_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_pwm_1_auto_tl_in_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_pwm_1_auto_tl_in_a_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_pwm_1_auto_tl_in_a_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_pwm_1_auto_tl_in_a_bits_source; // @[LazyModule.scala 432:27]
  wire [28:0] coupler_to_device_named_pwm_1_auto_tl_in_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_device_named_pwm_1_auto_tl_in_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_pwm_1_auto_tl_in_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_pwm_1_auto_tl_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_pwm_1_auto_tl_in_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_pwm_1_auto_tl_in_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_pwm_1_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_pwm_1_auto_tl_in_d_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_pwm_1_auto_tl_in_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_pwm_1_auto_tl_in_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_pwm_2_clock; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_pwm_2_reset; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_pwm_2_auto_control_xing_out_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_pwm_2_auto_control_xing_out_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_pwm_2_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_pwm_2_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_pwm_2_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_device_named_pwm_2_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 432:27]
  wire [28:0] coupler_to_device_named_pwm_2_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_device_named_pwm_2_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_pwm_2_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_pwm_2_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_pwm_2_auto_control_xing_out_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_pwm_2_auto_control_xing_out_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_pwm_2_auto_control_xing_out_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_pwm_2_auto_control_xing_out_d_bits_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_device_named_pwm_2_auto_control_xing_out_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_pwm_2_auto_control_xing_out_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_pwm_2_auto_tl_in_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_pwm_2_auto_tl_in_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_pwm_2_auto_tl_in_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_pwm_2_auto_tl_in_a_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_pwm_2_auto_tl_in_a_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_pwm_2_auto_tl_in_a_bits_source; // @[LazyModule.scala 432:27]
  wire [28:0] coupler_to_device_named_pwm_2_auto_tl_in_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_device_named_pwm_2_auto_tl_in_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_pwm_2_auto_tl_in_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_pwm_2_auto_tl_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_pwm_2_auto_tl_in_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_pwm_2_auto_tl_in_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_pwm_2_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_pwm_2_auto_tl_in_d_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_pwm_2_auto_tl_in_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_pwm_2_auto_tl_in_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_i2c_0_clock; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_i2c_0_reset; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_i2c_0_auto_control_xing_out_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_i2c_0_auto_control_xing_out_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_i2c_0_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_i2c_0_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_i2c_0_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_device_named_i2c_0_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 432:27]
  wire [28:0] coupler_to_device_named_i2c_0_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_device_named_i2c_0_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_i2c_0_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_i2c_0_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_i2c_0_auto_control_xing_out_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_i2c_0_auto_control_xing_out_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_i2c_0_auto_control_xing_out_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_i2c_0_auto_control_xing_out_d_bits_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_device_named_i2c_0_auto_control_xing_out_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_i2c_0_auto_control_xing_out_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_i2c_0_auto_tl_in_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_i2c_0_auto_tl_in_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_i2c_0_auto_tl_in_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_i2c_0_auto_tl_in_a_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_i2c_0_auto_tl_in_a_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_i2c_0_auto_tl_in_a_bits_source; // @[LazyModule.scala 432:27]
  wire [28:0] coupler_to_device_named_i2c_0_auto_tl_in_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_device_named_i2c_0_auto_tl_in_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_i2c_0_auto_tl_in_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_i2c_0_auto_tl_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_i2c_0_auto_tl_in_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_i2c_0_auto_tl_in_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_i2c_0_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_i2c_0_auto_tl_in_d_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_i2c_0_auto_tl_in_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_i2c_0_auto_tl_in_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_i2c_1_clock; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_i2c_1_reset; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_i2c_1_auto_control_xing_out_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_i2c_1_auto_control_xing_out_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_i2c_1_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_i2c_1_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_i2c_1_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_device_named_i2c_1_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 432:27]
  wire [28:0] coupler_to_device_named_i2c_1_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_device_named_i2c_1_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_i2c_1_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_i2c_1_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_i2c_1_auto_control_xing_out_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_i2c_1_auto_control_xing_out_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_i2c_1_auto_control_xing_out_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_i2c_1_auto_control_xing_out_d_bits_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_device_named_i2c_1_auto_control_xing_out_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_i2c_1_auto_control_xing_out_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_i2c_1_auto_tl_in_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_i2c_1_auto_tl_in_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_i2c_1_auto_tl_in_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_i2c_1_auto_tl_in_a_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_i2c_1_auto_tl_in_a_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_i2c_1_auto_tl_in_a_bits_source; // @[LazyModule.scala 432:27]
  wire [28:0] coupler_to_device_named_i2c_1_auto_tl_in_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_device_named_i2c_1_auto_tl_in_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_i2c_1_auto_tl_in_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_i2c_1_auto_tl_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_i2c_1_auto_tl_in_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_i2c_1_auto_tl_in_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_i2c_1_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_i2c_1_auto_tl_in_d_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_device_named_i2c_1_auto_tl_in_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_i2c_1_auto_tl_in_d_bits_data; // @[LazyModule.scala 432:27]
  ClockGroupAggregator_1 subsystem_pbus_clock_groups ( // @[BusWrapper.scala 40:48]
    .auto_in_member_subsystem_pbus_0_clock(subsystem_pbus_clock_groups_auto_in_member_subsystem_pbus_0_clock),
    .auto_in_member_subsystem_pbus_0_reset(subsystem_pbus_clock_groups_auto_in_member_subsystem_pbus_0_reset),
    .auto_out_member_subsystem_pbus_0_clock(subsystem_pbus_clock_groups_auto_out_member_subsystem_pbus_0_clock),
    .auto_out_member_subsystem_pbus_0_reset(subsystem_pbus_clock_groups_auto_out_member_subsystem_pbus_0_reset)
  );
  ClockGroup_1 clockGroup ( // @[BusWrapper.scala 41:38]
    .auto_in_member_subsystem_pbus_0_clock(clockGroup_auto_in_member_subsystem_pbus_0_clock),
    .auto_in_member_subsystem_pbus_0_reset(clockGroup_auto_in_member_subsystem_pbus_0_reset),
    .auto_out_clock(clockGroup_auto_out_clock),
    .auto_out_reset(clockGroup_auto_out_reset)
  );
  FixedClockBroadcast_1 fixedClockNode ( // @[ClockGroup.scala 106:107]
    .auto_in_clock(fixedClockNode_auto_in_clock),
    .auto_in_reset(fixedClockNode_auto_in_reset),
    .auto_out_14_clock(fixedClockNode_auto_out_14_clock),
    .auto_out_14_reset(fixedClockNode_auto_out_14_reset),
    .auto_out_13_clock(fixedClockNode_auto_out_13_clock),
    .auto_out_13_reset(fixedClockNode_auto_out_13_reset),
    .auto_out_12_clock(fixedClockNode_auto_out_12_clock),
    .auto_out_12_reset(fixedClockNode_auto_out_12_reset),
    .auto_out_11_clock(fixedClockNode_auto_out_11_clock),
    .auto_out_11_reset(fixedClockNode_auto_out_11_reset),
    .auto_out_10_clock(fixedClockNode_auto_out_10_clock),
    .auto_out_10_reset(fixedClockNode_auto_out_10_reset),
    .auto_out_9_clock(fixedClockNode_auto_out_9_clock),
    .auto_out_9_reset(fixedClockNode_auto_out_9_reset),
    .auto_out_8_clock(fixedClockNode_auto_out_8_clock),
    .auto_out_8_reset(fixedClockNode_auto_out_8_reset),
    .auto_out_7_clock(fixedClockNode_auto_out_7_clock),
    .auto_out_7_reset(fixedClockNode_auto_out_7_reset),
    .auto_out_6_clock(fixedClockNode_auto_out_6_clock),
    .auto_out_6_reset(fixedClockNode_auto_out_6_reset),
    .auto_out_5_clock(fixedClockNode_auto_out_5_clock),
    .auto_out_5_reset(fixedClockNode_auto_out_5_reset),
    .auto_out_4_clock(fixedClockNode_auto_out_4_clock),
    .auto_out_4_reset(fixedClockNode_auto_out_4_reset),
    .auto_out_3_clock(fixedClockNode_auto_out_3_clock),
    .auto_out_3_reset(fixedClockNode_auto_out_3_reset),
    .auto_out_2_clock(fixedClockNode_auto_out_2_clock),
    .auto_out_2_reset(fixedClockNode_auto_out_2_reset),
    .auto_out_1_clock(fixedClockNode_auto_out_1_clock),
    .auto_out_1_reset(fixedClockNode_auto_out_1_reset),
    .auto_out_0_clock(fixedClockNode_auto_out_0_clock),
    .auto_out_0_reset(fixedClockNode_auto_out_0_reset)
  );
  TLFIFOFixer_1 fixer ( // @[PeripheryBus.scala 47:33]
    .clock(fixer_clock),
    .reset(fixer_reset),
    .auto_in_a_ready(fixer_auto_in_a_ready),
    .auto_in_a_valid(fixer_auto_in_a_valid),
    .auto_in_a_bits_opcode(fixer_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(fixer_auto_in_a_bits_param),
    .auto_in_a_bits_size(fixer_auto_in_a_bits_size),
    .auto_in_a_bits_source(fixer_auto_in_a_bits_source),
    .auto_in_a_bits_address(fixer_auto_in_a_bits_address),
    .auto_in_a_bits_mask(fixer_auto_in_a_bits_mask),
    .auto_in_a_bits_data(fixer_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(fixer_auto_in_a_bits_corrupt),
    .auto_in_d_ready(fixer_auto_in_d_ready),
    .auto_in_d_valid(fixer_auto_in_d_valid),
    .auto_in_d_bits_opcode(fixer_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(fixer_auto_in_d_bits_size),
    .auto_in_d_bits_source(fixer_auto_in_d_bits_source),
    .auto_in_d_bits_data(fixer_auto_in_d_bits_data),
    .auto_out_a_ready(fixer_auto_out_a_ready),
    .auto_out_a_valid(fixer_auto_out_a_valid),
    .auto_out_a_bits_opcode(fixer_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(fixer_auto_out_a_bits_param),
    .auto_out_a_bits_size(fixer_auto_out_a_bits_size),
    .auto_out_a_bits_source(fixer_auto_out_a_bits_source),
    .auto_out_a_bits_address(fixer_auto_out_a_bits_address),
    .auto_out_a_bits_mask(fixer_auto_out_a_bits_mask),
    .auto_out_a_bits_data(fixer_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(fixer_auto_out_a_bits_corrupt),
    .auto_out_d_ready(fixer_auto_out_d_ready),
    .auto_out_d_valid(fixer_auto_out_d_valid),
    .auto_out_d_bits_opcode(fixer_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(fixer_auto_out_d_bits_size),
    .auto_out_d_bits_source(fixer_auto_out_d_bits_source),
    .auto_out_d_bits_data(fixer_auto_out_d_bits_data)
  );
  TLXbar_1 in_xbar ( // @[PeripheryBus.scala 49:29]
    .auto_in_a_ready(in_xbar_auto_in_a_ready),
    .auto_in_a_valid(in_xbar_auto_in_a_valid),
    .auto_in_a_bits_opcode(in_xbar_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(in_xbar_auto_in_a_bits_param),
    .auto_in_a_bits_size(in_xbar_auto_in_a_bits_size),
    .auto_in_a_bits_source(in_xbar_auto_in_a_bits_source),
    .auto_in_a_bits_address(in_xbar_auto_in_a_bits_address),
    .auto_in_a_bits_mask(in_xbar_auto_in_a_bits_mask),
    .auto_in_a_bits_data(in_xbar_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(in_xbar_auto_in_a_bits_corrupt),
    .auto_in_d_ready(in_xbar_auto_in_d_ready),
    .auto_in_d_valid(in_xbar_auto_in_d_valid),
    .auto_in_d_bits_opcode(in_xbar_auto_in_d_bits_opcode),
    .auto_in_d_bits_param(in_xbar_auto_in_d_bits_param),
    .auto_in_d_bits_size(in_xbar_auto_in_d_bits_size),
    .auto_in_d_bits_source(in_xbar_auto_in_d_bits_source),
    .auto_in_d_bits_sink(in_xbar_auto_in_d_bits_sink),
    .auto_in_d_bits_denied(in_xbar_auto_in_d_bits_denied),
    .auto_in_d_bits_data(in_xbar_auto_in_d_bits_data),
    .auto_in_d_bits_corrupt(in_xbar_auto_in_d_bits_corrupt),
    .auto_out_a_ready(in_xbar_auto_out_a_ready),
    .auto_out_a_valid(in_xbar_auto_out_a_valid),
    .auto_out_a_bits_opcode(in_xbar_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(in_xbar_auto_out_a_bits_param),
    .auto_out_a_bits_size(in_xbar_auto_out_a_bits_size),
    .auto_out_a_bits_source(in_xbar_auto_out_a_bits_source),
    .auto_out_a_bits_address(in_xbar_auto_out_a_bits_address),
    .auto_out_a_bits_mask(in_xbar_auto_out_a_bits_mask),
    .auto_out_a_bits_data(in_xbar_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(in_xbar_auto_out_a_bits_corrupt),
    .auto_out_d_ready(in_xbar_auto_out_d_ready),
    .auto_out_d_valid(in_xbar_auto_out_d_valid),
    .auto_out_d_bits_opcode(in_xbar_auto_out_d_bits_opcode),
    .auto_out_d_bits_param(in_xbar_auto_out_d_bits_param),
    .auto_out_d_bits_size(in_xbar_auto_out_d_bits_size),
    .auto_out_d_bits_source(in_xbar_auto_out_d_bits_source),
    .auto_out_d_bits_sink(in_xbar_auto_out_d_bits_sink),
    .auto_out_d_bits_denied(in_xbar_auto_out_d_bits_denied),
    .auto_out_d_bits_data(in_xbar_auto_out_d_bits_data),
    .auto_out_d_bits_corrupt(in_xbar_auto_out_d_bits_corrupt)
  );
  TLXbar_2 out_xbar ( // @[PeripheryBus.scala 50:30]
    .clock(out_xbar_clock),
    .reset(out_xbar_reset),
    .auto_in_a_ready(out_xbar_auto_in_a_ready),
    .auto_in_a_valid(out_xbar_auto_in_a_valid),
    .auto_in_a_bits_opcode(out_xbar_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(out_xbar_auto_in_a_bits_param),
    .auto_in_a_bits_size(out_xbar_auto_in_a_bits_size),
    .auto_in_a_bits_source(out_xbar_auto_in_a_bits_source),
    .auto_in_a_bits_address(out_xbar_auto_in_a_bits_address),
    .auto_in_a_bits_mask(out_xbar_auto_in_a_bits_mask),
    .auto_in_a_bits_data(out_xbar_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(out_xbar_auto_in_a_bits_corrupt),
    .auto_in_d_ready(out_xbar_auto_in_d_ready),
    .auto_in_d_valid(out_xbar_auto_in_d_valid),
    .auto_in_d_bits_opcode(out_xbar_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(out_xbar_auto_in_d_bits_size),
    .auto_in_d_bits_source(out_xbar_auto_in_d_bits_source),
    .auto_in_d_bits_data(out_xbar_auto_in_d_bits_data),
    .auto_out_14_a_ready(out_xbar_auto_out_14_a_ready),
    .auto_out_14_a_valid(out_xbar_auto_out_14_a_valid),
    .auto_out_14_a_bits_opcode(out_xbar_auto_out_14_a_bits_opcode),
    .auto_out_14_a_bits_param(out_xbar_auto_out_14_a_bits_param),
    .auto_out_14_a_bits_size(out_xbar_auto_out_14_a_bits_size),
    .auto_out_14_a_bits_source(out_xbar_auto_out_14_a_bits_source),
    .auto_out_14_a_bits_address(out_xbar_auto_out_14_a_bits_address),
    .auto_out_14_a_bits_mask(out_xbar_auto_out_14_a_bits_mask),
    .auto_out_14_a_bits_data(out_xbar_auto_out_14_a_bits_data),
    .auto_out_14_a_bits_corrupt(out_xbar_auto_out_14_a_bits_corrupt),
    .auto_out_14_d_ready(out_xbar_auto_out_14_d_ready),
    .auto_out_14_d_valid(out_xbar_auto_out_14_d_valid),
    .auto_out_14_d_bits_opcode(out_xbar_auto_out_14_d_bits_opcode),
    .auto_out_14_d_bits_size(out_xbar_auto_out_14_d_bits_size),
    .auto_out_14_d_bits_source(out_xbar_auto_out_14_d_bits_source),
    .auto_out_14_d_bits_data(out_xbar_auto_out_14_d_bits_data),
    .auto_out_13_a_ready(out_xbar_auto_out_13_a_ready),
    .auto_out_13_a_valid(out_xbar_auto_out_13_a_valid),
    .auto_out_13_a_bits_opcode(out_xbar_auto_out_13_a_bits_opcode),
    .auto_out_13_a_bits_param(out_xbar_auto_out_13_a_bits_param),
    .auto_out_13_a_bits_size(out_xbar_auto_out_13_a_bits_size),
    .auto_out_13_a_bits_source(out_xbar_auto_out_13_a_bits_source),
    .auto_out_13_a_bits_address(out_xbar_auto_out_13_a_bits_address),
    .auto_out_13_a_bits_mask(out_xbar_auto_out_13_a_bits_mask),
    .auto_out_13_a_bits_data(out_xbar_auto_out_13_a_bits_data),
    .auto_out_13_a_bits_corrupt(out_xbar_auto_out_13_a_bits_corrupt),
    .auto_out_13_d_ready(out_xbar_auto_out_13_d_ready),
    .auto_out_13_d_valid(out_xbar_auto_out_13_d_valid),
    .auto_out_13_d_bits_opcode(out_xbar_auto_out_13_d_bits_opcode),
    .auto_out_13_d_bits_size(out_xbar_auto_out_13_d_bits_size),
    .auto_out_13_d_bits_source(out_xbar_auto_out_13_d_bits_source),
    .auto_out_13_d_bits_data(out_xbar_auto_out_13_d_bits_data),
    .auto_out_12_a_ready(out_xbar_auto_out_12_a_ready),
    .auto_out_12_a_valid(out_xbar_auto_out_12_a_valid),
    .auto_out_12_a_bits_opcode(out_xbar_auto_out_12_a_bits_opcode),
    .auto_out_12_a_bits_param(out_xbar_auto_out_12_a_bits_param),
    .auto_out_12_a_bits_size(out_xbar_auto_out_12_a_bits_size),
    .auto_out_12_a_bits_source(out_xbar_auto_out_12_a_bits_source),
    .auto_out_12_a_bits_address(out_xbar_auto_out_12_a_bits_address),
    .auto_out_12_a_bits_mask(out_xbar_auto_out_12_a_bits_mask),
    .auto_out_12_a_bits_data(out_xbar_auto_out_12_a_bits_data),
    .auto_out_12_a_bits_corrupt(out_xbar_auto_out_12_a_bits_corrupt),
    .auto_out_12_d_ready(out_xbar_auto_out_12_d_ready),
    .auto_out_12_d_valid(out_xbar_auto_out_12_d_valid),
    .auto_out_12_d_bits_opcode(out_xbar_auto_out_12_d_bits_opcode),
    .auto_out_12_d_bits_size(out_xbar_auto_out_12_d_bits_size),
    .auto_out_12_d_bits_source(out_xbar_auto_out_12_d_bits_source),
    .auto_out_12_d_bits_data(out_xbar_auto_out_12_d_bits_data),
    .auto_out_11_a_ready(out_xbar_auto_out_11_a_ready),
    .auto_out_11_a_valid(out_xbar_auto_out_11_a_valid),
    .auto_out_11_a_bits_opcode(out_xbar_auto_out_11_a_bits_opcode),
    .auto_out_11_a_bits_param(out_xbar_auto_out_11_a_bits_param),
    .auto_out_11_a_bits_size(out_xbar_auto_out_11_a_bits_size),
    .auto_out_11_a_bits_source(out_xbar_auto_out_11_a_bits_source),
    .auto_out_11_a_bits_address(out_xbar_auto_out_11_a_bits_address),
    .auto_out_11_a_bits_mask(out_xbar_auto_out_11_a_bits_mask),
    .auto_out_11_a_bits_data(out_xbar_auto_out_11_a_bits_data),
    .auto_out_11_a_bits_corrupt(out_xbar_auto_out_11_a_bits_corrupt),
    .auto_out_11_d_ready(out_xbar_auto_out_11_d_ready),
    .auto_out_11_d_valid(out_xbar_auto_out_11_d_valid),
    .auto_out_11_d_bits_opcode(out_xbar_auto_out_11_d_bits_opcode),
    .auto_out_11_d_bits_size(out_xbar_auto_out_11_d_bits_size),
    .auto_out_11_d_bits_source(out_xbar_auto_out_11_d_bits_source),
    .auto_out_11_d_bits_data(out_xbar_auto_out_11_d_bits_data),
    .auto_out_10_a_ready(out_xbar_auto_out_10_a_ready),
    .auto_out_10_a_valid(out_xbar_auto_out_10_a_valid),
    .auto_out_10_a_bits_opcode(out_xbar_auto_out_10_a_bits_opcode),
    .auto_out_10_a_bits_param(out_xbar_auto_out_10_a_bits_param),
    .auto_out_10_a_bits_size(out_xbar_auto_out_10_a_bits_size),
    .auto_out_10_a_bits_source(out_xbar_auto_out_10_a_bits_source),
    .auto_out_10_a_bits_address(out_xbar_auto_out_10_a_bits_address),
    .auto_out_10_a_bits_mask(out_xbar_auto_out_10_a_bits_mask),
    .auto_out_10_a_bits_data(out_xbar_auto_out_10_a_bits_data),
    .auto_out_10_a_bits_corrupt(out_xbar_auto_out_10_a_bits_corrupt),
    .auto_out_10_d_ready(out_xbar_auto_out_10_d_ready),
    .auto_out_10_d_valid(out_xbar_auto_out_10_d_valid),
    .auto_out_10_d_bits_opcode(out_xbar_auto_out_10_d_bits_opcode),
    .auto_out_10_d_bits_size(out_xbar_auto_out_10_d_bits_size),
    .auto_out_10_d_bits_source(out_xbar_auto_out_10_d_bits_source),
    .auto_out_10_d_bits_data(out_xbar_auto_out_10_d_bits_data),
    .auto_out_9_a_ready(out_xbar_auto_out_9_a_ready),
    .auto_out_9_a_valid(out_xbar_auto_out_9_a_valid),
    .auto_out_9_a_bits_opcode(out_xbar_auto_out_9_a_bits_opcode),
    .auto_out_9_a_bits_param(out_xbar_auto_out_9_a_bits_param),
    .auto_out_9_a_bits_size(out_xbar_auto_out_9_a_bits_size),
    .auto_out_9_a_bits_source(out_xbar_auto_out_9_a_bits_source),
    .auto_out_9_a_bits_address(out_xbar_auto_out_9_a_bits_address),
    .auto_out_9_a_bits_mask(out_xbar_auto_out_9_a_bits_mask),
    .auto_out_9_a_bits_data(out_xbar_auto_out_9_a_bits_data),
    .auto_out_9_a_bits_corrupt(out_xbar_auto_out_9_a_bits_corrupt),
    .auto_out_9_d_ready(out_xbar_auto_out_9_d_ready),
    .auto_out_9_d_valid(out_xbar_auto_out_9_d_valid),
    .auto_out_9_d_bits_opcode(out_xbar_auto_out_9_d_bits_opcode),
    .auto_out_9_d_bits_size(out_xbar_auto_out_9_d_bits_size),
    .auto_out_9_d_bits_source(out_xbar_auto_out_9_d_bits_source),
    .auto_out_9_d_bits_data(out_xbar_auto_out_9_d_bits_data),
    .auto_out_8_a_ready(out_xbar_auto_out_8_a_ready),
    .auto_out_8_a_valid(out_xbar_auto_out_8_a_valid),
    .auto_out_8_a_bits_opcode(out_xbar_auto_out_8_a_bits_opcode),
    .auto_out_8_a_bits_param(out_xbar_auto_out_8_a_bits_param),
    .auto_out_8_a_bits_size(out_xbar_auto_out_8_a_bits_size),
    .auto_out_8_a_bits_source(out_xbar_auto_out_8_a_bits_source),
    .auto_out_8_a_bits_address(out_xbar_auto_out_8_a_bits_address),
    .auto_out_8_a_bits_mask(out_xbar_auto_out_8_a_bits_mask),
    .auto_out_8_a_bits_data(out_xbar_auto_out_8_a_bits_data),
    .auto_out_8_a_bits_corrupt(out_xbar_auto_out_8_a_bits_corrupt),
    .auto_out_8_d_ready(out_xbar_auto_out_8_d_ready),
    .auto_out_8_d_valid(out_xbar_auto_out_8_d_valid),
    .auto_out_8_d_bits_opcode(out_xbar_auto_out_8_d_bits_opcode),
    .auto_out_8_d_bits_size(out_xbar_auto_out_8_d_bits_size),
    .auto_out_8_d_bits_source(out_xbar_auto_out_8_d_bits_source),
    .auto_out_8_d_bits_data(out_xbar_auto_out_8_d_bits_data),
    .auto_out_7_a_ready(out_xbar_auto_out_7_a_ready),
    .auto_out_7_a_valid(out_xbar_auto_out_7_a_valid),
    .auto_out_7_a_bits_opcode(out_xbar_auto_out_7_a_bits_opcode),
    .auto_out_7_a_bits_param(out_xbar_auto_out_7_a_bits_param),
    .auto_out_7_a_bits_size(out_xbar_auto_out_7_a_bits_size),
    .auto_out_7_a_bits_source(out_xbar_auto_out_7_a_bits_source),
    .auto_out_7_a_bits_address(out_xbar_auto_out_7_a_bits_address),
    .auto_out_7_a_bits_mask(out_xbar_auto_out_7_a_bits_mask),
    .auto_out_7_a_bits_data(out_xbar_auto_out_7_a_bits_data),
    .auto_out_7_a_bits_corrupt(out_xbar_auto_out_7_a_bits_corrupt),
    .auto_out_7_d_ready(out_xbar_auto_out_7_d_ready),
    .auto_out_7_d_valid(out_xbar_auto_out_7_d_valid),
    .auto_out_7_d_bits_opcode(out_xbar_auto_out_7_d_bits_opcode),
    .auto_out_7_d_bits_size(out_xbar_auto_out_7_d_bits_size),
    .auto_out_7_d_bits_source(out_xbar_auto_out_7_d_bits_source),
    .auto_out_7_d_bits_data(out_xbar_auto_out_7_d_bits_data),
    .auto_out_6_a_ready(out_xbar_auto_out_6_a_ready),
    .auto_out_6_a_valid(out_xbar_auto_out_6_a_valid),
    .auto_out_6_a_bits_opcode(out_xbar_auto_out_6_a_bits_opcode),
    .auto_out_6_a_bits_param(out_xbar_auto_out_6_a_bits_param),
    .auto_out_6_a_bits_size(out_xbar_auto_out_6_a_bits_size),
    .auto_out_6_a_bits_source(out_xbar_auto_out_6_a_bits_source),
    .auto_out_6_a_bits_address(out_xbar_auto_out_6_a_bits_address),
    .auto_out_6_a_bits_mask(out_xbar_auto_out_6_a_bits_mask),
    .auto_out_6_a_bits_corrupt(out_xbar_auto_out_6_a_bits_corrupt),
    .auto_out_6_d_ready(out_xbar_auto_out_6_d_ready),
    .auto_out_6_d_valid(out_xbar_auto_out_6_d_valid),
    .auto_out_6_d_bits_size(out_xbar_auto_out_6_d_bits_size),
    .auto_out_6_d_bits_source(out_xbar_auto_out_6_d_bits_source),
    .auto_out_6_d_bits_data(out_xbar_auto_out_6_d_bits_data),
    .auto_out_5_a_ready(out_xbar_auto_out_5_a_ready),
    .auto_out_5_a_valid(out_xbar_auto_out_5_a_valid),
    .auto_out_5_a_bits_opcode(out_xbar_auto_out_5_a_bits_opcode),
    .auto_out_5_a_bits_param(out_xbar_auto_out_5_a_bits_param),
    .auto_out_5_a_bits_size(out_xbar_auto_out_5_a_bits_size),
    .auto_out_5_a_bits_source(out_xbar_auto_out_5_a_bits_source),
    .auto_out_5_a_bits_address(out_xbar_auto_out_5_a_bits_address),
    .auto_out_5_a_bits_mask(out_xbar_auto_out_5_a_bits_mask),
    .auto_out_5_a_bits_data(out_xbar_auto_out_5_a_bits_data),
    .auto_out_5_a_bits_corrupt(out_xbar_auto_out_5_a_bits_corrupt),
    .auto_out_5_d_ready(out_xbar_auto_out_5_d_ready),
    .auto_out_5_d_valid(out_xbar_auto_out_5_d_valid),
    .auto_out_5_d_bits_opcode(out_xbar_auto_out_5_d_bits_opcode),
    .auto_out_5_d_bits_size(out_xbar_auto_out_5_d_bits_size),
    .auto_out_5_d_bits_source(out_xbar_auto_out_5_d_bits_source),
    .auto_out_5_d_bits_data(out_xbar_auto_out_5_d_bits_data),
    .auto_out_4_a_ready(out_xbar_auto_out_4_a_ready),
    .auto_out_4_a_valid(out_xbar_auto_out_4_a_valid),
    .auto_out_4_a_bits_opcode(out_xbar_auto_out_4_a_bits_opcode),
    .auto_out_4_a_bits_param(out_xbar_auto_out_4_a_bits_param),
    .auto_out_4_a_bits_size(out_xbar_auto_out_4_a_bits_size),
    .auto_out_4_a_bits_source(out_xbar_auto_out_4_a_bits_source),
    .auto_out_4_a_bits_address(out_xbar_auto_out_4_a_bits_address),
    .auto_out_4_a_bits_mask(out_xbar_auto_out_4_a_bits_mask),
    .auto_out_4_a_bits_data(out_xbar_auto_out_4_a_bits_data),
    .auto_out_4_a_bits_corrupt(out_xbar_auto_out_4_a_bits_corrupt),
    .auto_out_4_d_ready(out_xbar_auto_out_4_d_ready),
    .auto_out_4_d_valid(out_xbar_auto_out_4_d_valid),
    .auto_out_4_d_bits_opcode(out_xbar_auto_out_4_d_bits_opcode),
    .auto_out_4_d_bits_size(out_xbar_auto_out_4_d_bits_size),
    .auto_out_4_d_bits_source(out_xbar_auto_out_4_d_bits_source),
    .auto_out_4_d_bits_data(out_xbar_auto_out_4_d_bits_data),
    .auto_out_3_a_ready(out_xbar_auto_out_3_a_ready),
    .auto_out_3_a_valid(out_xbar_auto_out_3_a_valid),
    .auto_out_3_a_bits_opcode(out_xbar_auto_out_3_a_bits_opcode),
    .auto_out_3_a_bits_param(out_xbar_auto_out_3_a_bits_param),
    .auto_out_3_a_bits_size(out_xbar_auto_out_3_a_bits_size),
    .auto_out_3_a_bits_source(out_xbar_auto_out_3_a_bits_source),
    .auto_out_3_a_bits_address(out_xbar_auto_out_3_a_bits_address),
    .auto_out_3_a_bits_mask(out_xbar_auto_out_3_a_bits_mask),
    .auto_out_3_a_bits_data(out_xbar_auto_out_3_a_bits_data),
    .auto_out_3_a_bits_corrupt(out_xbar_auto_out_3_a_bits_corrupt),
    .auto_out_3_d_ready(out_xbar_auto_out_3_d_ready),
    .auto_out_3_d_valid(out_xbar_auto_out_3_d_valid),
    .auto_out_3_d_bits_opcode(out_xbar_auto_out_3_d_bits_opcode),
    .auto_out_3_d_bits_size(out_xbar_auto_out_3_d_bits_size),
    .auto_out_3_d_bits_source(out_xbar_auto_out_3_d_bits_source),
    .auto_out_3_d_bits_data(out_xbar_auto_out_3_d_bits_data),
    .auto_out_2_a_ready(out_xbar_auto_out_2_a_ready),
    .auto_out_2_a_valid(out_xbar_auto_out_2_a_valid),
    .auto_out_2_a_bits_opcode(out_xbar_auto_out_2_a_bits_opcode),
    .auto_out_2_a_bits_param(out_xbar_auto_out_2_a_bits_param),
    .auto_out_2_a_bits_size(out_xbar_auto_out_2_a_bits_size),
    .auto_out_2_a_bits_source(out_xbar_auto_out_2_a_bits_source),
    .auto_out_2_a_bits_address(out_xbar_auto_out_2_a_bits_address),
    .auto_out_2_a_bits_mask(out_xbar_auto_out_2_a_bits_mask),
    .auto_out_2_a_bits_data(out_xbar_auto_out_2_a_bits_data),
    .auto_out_2_a_bits_corrupt(out_xbar_auto_out_2_a_bits_corrupt),
    .auto_out_2_d_ready(out_xbar_auto_out_2_d_ready),
    .auto_out_2_d_valid(out_xbar_auto_out_2_d_valid),
    .auto_out_2_d_bits_opcode(out_xbar_auto_out_2_d_bits_opcode),
    .auto_out_2_d_bits_size(out_xbar_auto_out_2_d_bits_size),
    .auto_out_2_d_bits_source(out_xbar_auto_out_2_d_bits_source),
    .auto_out_2_d_bits_data(out_xbar_auto_out_2_d_bits_data),
    .auto_out_1_a_ready(out_xbar_auto_out_1_a_ready),
    .auto_out_1_a_valid(out_xbar_auto_out_1_a_valid),
    .auto_out_1_a_bits_opcode(out_xbar_auto_out_1_a_bits_opcode),
    .auto_out_1_a_bits_param(out_xbar_auto_out_1_a_bits_param),
    .auto_out_1_a_bits_size(out_xbar_auto_out_1_a_bits_size),
    .auto_out_1_a_bits_source(out_xbar_auto_out_1_a_bits_source),
    .auto_out_1_a_bits_address(out_xbar_auto_out_1_a_bits_address),
    .auto_out_1_a_bits_mask(out_xbar_auto_out_1_a_bits_mask),
    .auto_out_1_a_bits_data(out_xbar_auto_out_1_a_bits_data),
    .auto_out_1_a_bits_corrupt(out_xbar_auto_out_1_a_bits_corrupt),
    .auto_out_1_d_ready(out_xbar_auto_out_1_d_ready),
    .auto_out_1_d_valid(out_xbar_auto_out_1_d_valid),
    .auto_out_1_d_bits_opcode(out_xbar_auto_out_1_d_bits_opcode),
    .auto_out_1_d_bits_size(out_xbar_auto_out_1_d_bits_size),
    .auto_out_1_d_bits_source(out_xbar_auto_out_1_d_bits_source),
    .auto_out_1_d_bits_data(out_xbar_auto_out_1_d_bits_data),
    .auto_out_0_a_ready(out_xbar_auto_out_0_a_ready),
    .auto_out_0_a_valid(out_xbar_auto_out_0_a_valid),
    .auto_out_0_a_bits_opcode(out_xbar_auto_out_0_a_bits_opcode),
    .auto_out_0_a_bits_param(out_xbar_auto_out_0_a_bits_param),
    .auto_out_0_a_bits_size(out_xbar_auto_out_0_a_bits_size),
    .auto_out_0_a_bits_source(out_xbar_auto_out_0_a_bits_source),
    .auto_out_0_a_bits_address(out_xbar_auto_out_0_a_bits_address),
    .auto_out_0_a_bits_mask(out_xbar_auto_out_0_a_bits_mask),
    .auto_out_0_a_bits_data(out_xbar_auto_out_0_a_bits_data),
    .auto_out_0_a_bits_corrupt(out_xbar_auto_out_0_a_bits_corrupt),
    .auto_out_0_d_ready(out_xbar_auto_out_0_d_ready),
    .auto_out_0_d_valid(out_xbar_auto_out_0_d_valid),
    .auto_out_0_d_bits_opcode(out_xbar_auto_out_0_d_bits_opcode),
    .auto_out_0_d_bits_size(out_xbar_auto_out_0_d_bits_size),
    .auto_out_0_d_bits_source(out_xbar_auto_out_0_d_bits_source),
    .auto_out_0_d_bits_data(out_xbar_auto_out_0_d_bits_data)
  );
  TLBuffer buffer ( // @[Buffer.scala 68:28]
    .clock(buffer_clock),
    .reset(buffer_reset),
    .auto_in_a_ready(buffer_auto_in_a_ready),
    .auto_in_a_valid(buffer_auto_in_a_valid),
    .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
    .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
    .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
    .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
    .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
    .auto_in_a_bits_data(buffer_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
    .auto_in_d_ready(buffer_auto_in_d_ready),
    .auto_in_d_valid(buffer_auto_in_d_valid),
    .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
    .auto_in_d_bits_param(buffer_auto_in_d_bits_param),
    .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
    .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
    .auto_in_d_bits_sink(buffer_auto_in_d_bits_sink),
    .auto_in_d_bits_denied(buffer_auto_in_d_bits_denied),
    .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
    .auto_in_d_bits_corrupt(buffer_auto_in_d_bits_corrupt),
    .auto_out_a_ready(buffer_auto_out_a_ready),
    .auto_out_a_valid(buffer_auto_out_a_valid),
    .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
    .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
    .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
    .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
    .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
    .auto_out_a_bits_data(buffer_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
    .auto_out_d_ready(buffer_auto_out_d_ready),
    .auto_out_d_valid(buffer_auto_out_d_valid),
    .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
    .auto_out_d_bits_source(buffer_auto_out_d_bits_source),
    .auto_out_d_bits_data(buffer_auto_out_d_bits_data)
  );
  TLAtomicAutomata atomics ( // @[AtomicAutomata.scala 283:29]
    .clock(atomics_clock),
    .reset(atomics_reset),
    .auto_in_a_ready(atomics_auto_in_a_ready),
    .auto_in_a_valid(atomics_auto_in_a_valid),
    .auto_in_a_bits_opcode(atomics_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(atomics_auto_in_a_bits_param),
    .auto_in_a_bits_size(atomics_auto_in_a_bits_size),
    .auto_in_a_bits_source(atomics_auto_in_a_bits_source),
    .auto_in_a_bits_address(atomics_auto_in_a_bits_address),
    .auto_in_a_bits_mask(atomics_auto_in_a_bits_mask),
    .auto_in_a_bits_data(atomics_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(atomics_auto_in_a_bits_corrupt),
    .auto_in_d_ready(atomics_auto_in_d_ready),
    .auto_in_d_valid(atomics_auto_in_d_valid),
    .auto_in_d_bits_opcode(atomics_auto_in_d_bits_opcode),
    .auto_in_d_bits_param(atomics_auto_in_d_bits_param),
    .auto_in_d_bits_size(atomics_auto_in_d_bits_size),
    .auto_in_d_bits_source(atomics_auto_in_d_bits_source),
    .auto_in_d_bits_sink(atomics_auto_in_d_bits_sink),
    .auto_in_d_bits_denied(atomics_auto_in_d_bits_denied),
    .auto_in_d_bits_data(atomics_auto_in_d_bits_data),
    .auto_in_d_bits_corrupt(atomics_auto_in_d_bits_corrupt),
    .auto_out_a_ready(atomics_auto_out_a_ready),
    .auto_out_a_valid(atomics_auto_out_a_valid),
    .auto_out_a_bits_opcode(atomics_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(atomics_auto_out_a_bits_param),
    .auto_out_a_bits_size(atomics_auto_out_a_bits_size),
    .auto_out_a_bits_source(atomics_auto_out_a_bits_source),
    .auto_out_a_bits_address(atomics_auto_out_a_bits_address),
    .auto_out_a_bits_mask(atomics_auto_out_a_bits_mask),
    .auto_out_a_bits_data(atomics_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(atomics_auto_out_a_bits_corrupt),
    .auto_out_d_ready(atomics_auto_out_d_ready),
    .auto_out_d_valid(atomics_auto_out_d_valid),
    .auto_out_d_bits_opcode(atomics_auto_out_d_bits_opcode),
    .auto_out_d_bits_param(atomics_auto_out_d_bits_param),
    .auto_out_d_bits_size(atomics_auto_out_d_bits_size),
    .auto_out_d_bits_source(atomics_auto_out_d_bits_source),
    .auto_out_d_bits_sink(atomics_auto_out_d_bits_sink),
    .auto_out_d_bits_denied(atomics_auto_out_d_bits_denied),
    .auto_out_d_bits_data(atomics_auto_out_d_bits_data),
    .auto_out_d_bits_corrupt(atomics_auto_out_d_bits_corrupt)
  );
  TLBuffer_1 buffer_1 ( // @[Buffer.scala 68:28]
    .clock(buffer_1_clock),
    .reset(buffer_1_reset),
    .auto_in_a_ready(buffer_1_auto_in_a_ready),
    .auto_in_a_valid(buffer_1_auto_in_a_valid),
    .auto_in_a_bits_opcode(buffer_1_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(buffer_1_auto_in_a_bits_param),
    .auto_in_a_bits_size(buffer_1_auto_in_a_bits_size),
    .auto_in_a_bits_source(buffer_1_auto_in_a_bits_source),
    .auto_in_a_bits_address(buffer_1_auto_in_a_bits_address),
    .auto_in_a_bits_mask(buffer_1_auto_in_a_bits_mask),
    .auto_in_a_bits_data(buffer_1_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(buffer_1_auto_in_a_bits_corrupt),
    .auto_in_d_ready(buffer_1_auto_in_d_ready),
    .auto_in_d_valid(buffer_1_auto_in_d_valid),
    .auto_in_d_bits_opcode(buffer_1_auto_in_d_bits_opcode),
    .auto_in_d_bits_param(buffer_1_auto_in_d_bits_param),
    .auto_in_d_bits_size(buffer_1_auto_in_d_bits_size),
    .auto_in_d_bits_source(buffer_1_auto_in_d_bits_source),
    .auto_in_d_bits_sink(buffer_1_auto_in_d_bits_sink),
    .auto_in_d_bits_denied(buffer_1_auto_in_d_bits_denied),
    .auto_in_d_bits_data(buffer_1_auto_in_d_bits_data),
    .auto_in_d_bits_corrupt(buffer_1_auto_in_d_bits_corrupt),
    .auto_out_a_ready(buffer_1_auto_out_a_ready),
    .auto_out_a_valid(buffer_1_auto_out_a_valid),
    .auto_out_a_bits_opcode(buffer_1_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(buffer_1_auto_out_a_bits_param),
    .auto_out_a_bits_size(buffer_1_auto_out_a_bits_size),
    .auto_out_a_bits_source(buffer_1_auto_out_a_bits_source),
    .auto_out_a_bits_address(buffer_1_auto_out_a_bits_address),
    .auto_out_a_bits_mask(buffer_1_auto_out_a_bits_mask),
    .auto_out_a_bits_data(buffer_1_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(buffer_1_auto_out_a_bits_corrupt),
    .auto_out_d_ready(buffer_1_auto_out_d_ready),
    .auto_out_d_valid(buffer_1_auto_out_d_valid),
    .auto_out_d_bits_opcode(buffer_1_auto_out_d_bits_opcode),
    .auto_out_d_bits_param(buffer_1_auto_out_d_bits_param),
    .auto_out_d_bits_size(buffer_1_auto_out_d_bits_size),
    .auto_out_d_bits_source(buffer_1_auto_out_d_bits_source),
    .auto_out_d_bits_sink(buffer_1_auto_out_d_bits_sink),
    .auto_out_d_bits_denied(buffer_1_auto_out_d_bits_denied),
    .auto_out_d_bits_data(buffer_1_auto_out_d_bits_data),
    .auto_out_d_bits_corrupt(buffer_1_auto_out_d_bits_corrupt)
  );
  TLInterconnectCoupler_4 coupler_to_device_named_uart_0 ( // @[LazyModule.scala 432:27]
    .clock(coupler_to_device_named_uart_0_clock),
    .reset(coupler_to_device_named_uart_0_reset),
    .auto_control_xing_out_a_ready(coupler_to_device_named_uart_0_auto_control_xing_out_a_ready),
    .auto_control_xing_out_a_valid(coupler_to_device_named_uart_0_auto_control_xing_out_a_valid),
    .auto_control_xing_out_a_bits_opcode(coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_opcode),
    .auto_control_xing_out_a_bits_param(coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_param),
    .auto_control_xing_out_a_bits_size(coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_size),
    .auto_control_xing_out_a_bits_source(coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_source),
    .auto_control_xing_out_a_bits_address(coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_address),
    .auto_control_xing_out_a_bits_mask(coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_mask),
    .auto_control_xing_out_a_bits_data(coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_data),
    .auto_control_xing_out_a_bits_corrupt(coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_corrupt),
    .auto_control_xing_out_d_ready(coupler_to_device_named_uart_0_auto_control_xing_out_d_ready),
    .auto_control_xing_out_d_valid(coupler_to_device_named_uart_0_auto_control_xing_out_d_valid),
    .auto_control_xing_out_d_bits_opcode(coupler_to_device_named_uart_0_auto_control_xing_out_d_bits_opcode),
    .auto_control_xing_out_d_bits_size(coupler_to_device_named_uart_0_auto_control_xing_out_d_bits_size),
    .auto_control_xing_out_d_bits_source(coupler_to_device_named_uart_0_auto_control_xing_out_d_bits_source),
    .auto_control_xing_out_d_bits_data(coupler_to_device_named_uart_0_auto_control_xing_out_d_bits_data),
    .auto_tl_in_a_ready(coupler_to_device_named_uart_0_auto_tl_in_a_ready),
    .auto_tl_in_a_valid(coupler_to_device_named_uart_0_auto_tl_in_a_valid),
    .auto_tl_in_a_bits_opcode(coupler_to_device_named_uart_0_auto_tl_in_a_bits_opcode),
    .auto_tl_in_a_bits_param(coupler_to_device_named_uart_0_auto_tl_in_a_bits_param),
    .auto_tl_in_a_bits_size(coupler_to_device_named_uart_0_auto_tl_in_a_bits_size),
    .auto_tl_in_a_bits_source(coupler_to_device_named_uart_0_auto_tl_in_a_bits_source),
    .auto_tl_in_a_bits_address(coupler_to_device_named_uart_0_auto_tl_in_a_bits_address),
    .auto_tl_in_a_bits_mask(coupler_to_device_named_uart_0_auto_tl_in_a_bits_mask),
    .auto_tl_in_a_bits_data(coupler_to_device_named_uart_0_auto_tl_in_a_bits_data),
    .auto_tl_in_a_bits_corrupt(coupler_to_device_named_uart_0_auto_tl_in_a_bits_corrupt),
    .auto_tl_in_d_ready(coupler_to_device_named_uart_0_auto_tl_in_d_ready),
    .auto_tl_in_d_valid(coupler_to_device_named_uart_0_auto_tl_in_d_valid),
    .auto_tl_in_d_bits_opcode(coupler_to_device_named_uart_0_auto_tl_in_d_bits_opcode),
    .auto_tl_in_d_bits_size(coupler_to_device_named_uart_0_auto_tl_in_d_bits_size),
    .auto_tl_in_d_bits_source(coupler_to_device_named_uart_0_auto_tl_in_d_bits_source),
    .auto_tl_in_d_bits_data(coupler_to_device_named_uart_0_auto_tl_in_d_bits_data)
  );
  TLInterconnectCoupler_5 coupler_to_device_named_uart_1 ( // @[LazyModule.scala 432:27]
    .clock(coupler_to_device_named_uart_1_clock),
    .reset(coupler_to_device_named_uart_1_reset),
    .auto_control_xing_out_a_ready(coupler_to_device_named_uart_1_auto_control_xing_out_a_ready),
    .auto_control_xing_out_a_valid(coupler_to_device_named_uart_1_auto_control_xing_out_a_valid),
    .auto_control_xing_out_a_bits_opcode(coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_opcode),
    .auto_control_xing_out_a_bits_param(coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_param),
    .auto_control_xing_out_a_bits_size(coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_size),
    .auto_control_xing_out_a_bits_source(coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_source),
    .auto_control_xing_out_a_bits_address(coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_address),
    .auto_control_xing_out_a_bits_mask(coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_mask),
    .auto_control_xing_out_a_bits_data(coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_data),
    .auto_control_xing_out_a_bits_corrupt(coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_corrupt),
    .auto_control_xing_out_d_ready(coupler_to_device_named_uart_1_auto_control_xing_out_d_ready),
    .auto_control_xing_out_d_valid(coupler_to_device_named_uart_1_auto_control_xing_out_d_valid),
    .auto_control_xing_out_d_bits_opcode(coupler_to_device_named_uart_1_auto_control_xing_out_d_bits_opcode),
    .auto_control_xing_out_d_bits_size(coupler_to_device_named_uart_1_auto_control_xing_out_d_bits_size),
    .auto_control_xing_out_d_bits_source(coupler_to_device_named_uart_1_auto_control_xing_out_d_bits_source),
    .auto_control_xing_out_d_bits_data(coupler_to_device_named_uart_1_auto_control_xing_out_d_bits_data),
    .auto_tl_in_a_ready(coupler_to_device_named_uart_1_auto_tl_in_a_ready),
    .auto_tl_in_a_valid(coupler_to_device_named_uart_1_auto_tl_in_a_valid),
    .auto_tl_in_a_bits_opcode(coupler_to_device_named_uart_1_auto_tl_in_a_bits_opcode),
    .auto_tl_in_a_bits_param(coupler_to_device_named_uart_1_auto_tl_in_a_bits_param),
    .auto_tl_in_a_bits_size(coupler_to_device_named_uart_1_auto_tl_in_a_bits_size),
    .auto_tl_in_a_bits_source(coupler_to_device_named_uart_1_auto_tl_in_a_bits_source),
    .auto_tl_in_a_bits_address(coupler_to_device_named_uart_1_auto_tl_in_a_bits_address),
    .auto_tl_in_a_bits_mask(coupler_to_device_named_uart_1_auto_tl_in_a_bits_mask),
    .auto_tl_in_a_bits_data(coupler_to_device_named_uart_1_auto_tl_in_a_bits_data),
    .auto_tl_in_a_bits_corrupt(coupler_to_device_named_uart_1_auto_tl_in_a_bits_corrupt),
    .auto_tl_in_d_ready(coupler_to_device_named_uart_1_auto_tl_in_d_ready),
    .auto_tl_in_d_valid(coupler_to_device_named_uart_1_auto_tl_in_d_valid),
    .auto_tl_in_d_bits_opcode(coupler_to_device_named_uart_1_auto_tl_in_d_bits_opcode),
    .auto_tl_in_d_bits_size(coupler_to_device_named_uart_1_auto_tl_in_d_bits_size),
    .auto_tl_in_d_bits_source(coupler_to_device_named_uart_1_auto_tl_in_d_bits_source),
    .auto_tl_in_d_bits_data(coupler_to_device_named_uart_1_auto_tl_in_d_bits_data)
  );
  TLInterconnectCoupler_6 coupler_to_device_named_uart_2 ( // @[LazyModule.scala 432:27]
    .clock(coupler_to_device_named_uart_2_clock),
    .reset(coupler_to_device_named_uart_2_reset),
    .auto_control_xing_out_a_ready(coupler_to_device_named_uart_2_auto_control_xing_out_a_ready),
    .auto_control_xing_out_a_valid(coupler_to_device_named_uart_2_auto_control_xing_out_a_valid),
    .auto_control_xing_out_a_bits_opcode(coupler_to_device_named_uart_2_auto_control_xing_out_a_bits_opcode),
    .auto_control_xing_out_a_bits_param(coupler_to_device_named_uart_2_auto_control_xing_out_a_bits_param),
    .auto_control_xing_out_a_bits_size(coupler_to_device_named_uart_2_auto_control_xing_out_a_bits_size),
    .auto_control_xing_out_a_bits_source(coupler_to_device_named_uart_2_auto_control_xing_out_a_bits_source),
    .auto_control_xing_out_a_bits_address(coupler_to_device_named_uart_2_auto_control_xing_out_a_bits_address),
    .auto_control_xing_out_a_bits_mask(coupler_to_device_named_uart_2_auto_control_xing_out_a_bits_mask),
    .auto_control_xing_out_a_bits_data(coupler_to_device_named_uart_2_auto_control_xing_out_a_bits_data),
    .auto_control_xing_out_a_bits_corrupt(coupler_to_device_named_uart_2_auto_control_xing_out_a_bits_corrupt),
    .auto_control_xing_out_d_ready(coupler_to_device_named_uart_2_auto_control_xing_out_d_ready),
    .auto_control_xing_out_d_valid(coupler_to_device_named_uart_2_auto_control_xing_out_d_valid),
    .auto_control_xing_out_d_bits_opcode(coupler_to_device_named_uart_2_auto_control_xing_out_d_bits_opcode),
    .auto_control_xing_out_d_bits_size(coupler_to_device_named_uart_2_auto_control_xing_out_d_bits_size),
    .auto_control_xing_out_d_bits_source(coupler_to_device_named_uart_2_auto_control_xing_out_d_bits_source),
    .auto_control_xing_out_d_bits_data(coupler_to_device_named_uart_2_auto_control_xing_out_d_bits_data),
    .auto_tl_in_a_ready(coupler_to_device_named_uart_2_auto_tl_in_a_ready),
    .auto_tl_in_a_valid(coupler_to_device_named_uart_2_auto_tl_in_a_valid),
    .auto_tl_in_a_bits_opcode(coupler_to_device_named_uart_2_auto_tl_in_a_bits_opcode),
    .auto_tl_in_a_bits_param(coupler_to_device_named_uart_2_auto_tl_in_a_bits_param),
    .auto_tl_in_a_bits_size(coupler_to_device_named_uart_2_auto_tl_in_a_bits_size),
    .auto_tl_in_a_bits_source(coupler_to_device_named_uart_2_auto_tl_in_a_bits_source),
    .auto_tl_in_a_bits_address(coupler_to_device_named_uart_2_auto_tl_in_a_bits_address),
    .auto_tl_in_a_bits_mask(coupler_to_device_named_uart_2_auto_tl_in_a_bits_mask),
    .auto_tl_in_a_bits_data(coupler_to_device_named_uart_2_auto_tl_in_a_bits_data),
    .auto_tl_in_a_bits_corrupt(coupler_to_device_named_uart_2_auto_tl_in_a_bits_corrupt),
    .auto_tl_in_d_ready(coupler_to_device_named_uart_2_auto_tl_in_d_ready),
    .auto_tl_in_d_valid(coupler_to_device_named_uart_2_auto_tl_in_d_valid),
    .auto_tl_in_d_bits_opcode(coupler_to_device_named_uart_2_auto_tl_in_d_bits_opcode),
    .auto_tl_in_d_bits_size(coupler_to_device_named_uart_2_auto_tl_in_d_bits_size),
    .auto_tl_in_d_bits_source(coupler_to_device_named_uart_2_auto_tl_in_d_bits_source),
    .auto_tl_in_d_bits_data(coupler_to_device_named_uart_2_auto_tl_in_d_bits_data)
  );
  TLInterconnectCoupler_7 coupler_to_device_named_uart_3 ( // @[LazyModule.scala 432:27]
    .clock(coupler_to_device_named_uart_3_clock),
    .reset(coupler_to_device_named_uart_3_reset),
    .auto_control_xing_out_a_ready(coupler_to_device_named_uart_3_auto_control_xing_out_a_ready),
    .auto_control_xing_out_a_valid(coupler_to_device_named_uart_3_auto_control_xing_out_a_valid),
    .auto_control_xing_out_a_bits_opcode(coupler_to_device_named_uart_3_auto_control_xing_out_a_bits_opcode),
    .auto_control_xing_out_a_bits_param(coupler_to_device_named_uart_3_auto_control_xing_out_a_bits_param),
    .auto_control_xing_out_a_bits_size(coupler_to_device_named_uart_3_auto_control_xing_out_a_bits_size),
    .auto_control_xing_out_a_bits_source(coupler_to_device_named_uart_3_auto_control_xing_out_a_bits_source),
    .auto_control_xing_out_a_bits_address(coupler_to_device_named_uart_3_auto_control_xing_out_a_bits_address),
    .auto_control_xing_out_a_bits_mask(coupler_to_device_named_uart_3_auto_control_xing_out_a_bits_mask),
    .auto_control_xing_out_a_bits_data(coupler_to_device_named_uart_3_auto_control_xing_out_a_bits_data),
    .auto_control_xing_out_a_bits_corrupt(coupler_to_device_named_uart_3_auto_control_xing_out_a_bits_corrupt),
    .auto_control_xing_out_d_ready(coupler_to_device_named_uart_3_auto_control_xing_out_d_ready),
    .auto_control_xing_out_d_valid(coupler_to_device_named_uart_3_auto_control_xing_out_d_valid),
    .auto_control_xing_out_d_bits_opcode(coupler_to_device_named_uart_3_auto_control_xing_out_d_bits_opcode),
    .auto_control_xing_out_d_bits_size(coupler_to_device_named_uart_3_auto_control_xing_out_d_bits_size),
    .auto_control_xing_out_d_bits_source(coupler_to_device_named_uart_3_auto_control_xing_out_d_bits_source),
    .auto_control_xing_out_d_bits_data(coupler_to_device_named_uart_3_auto_control_xing_out_d_bits_data),
    .auto_tl_in_a_ready(coupler_to_device_named_uart_3_auto_tl_in_a_ready),
    .auto_tl_in_a_valid(coupler_to_device_named_uart_3_auto_tl_in_a_valid),
    .auto_tl_in_a_bits_opcode(coupler_to_device_named_uart_3_auto_tl_in_a_bits_opcode),
    .auto_tl_in_a_bits_param(coupler_to_device_named_uart_3_auto_tl_in_a_bits_param),
    .auto_tl_in_a_bits_size(coupler_to_device_named_uart_3_auto_tl_in_a_bits_size),
    .auto_tl_in_a_bits_source(coupler_to_device_named_uart_3_auto_tl_in_a_bits_source),
    .auto_tl_in_a_bits_address(coupler_to_device_named_uart_3_auto_tl_in_a_bits_address),
    .auto_tl_in_a_bits_mask(coupler_to_device_named_uart_3_auto_tl_in_a_bits_mask),
    .auto_tl_in_a_bits_data(coupler_to_device_named_uart_3_auto_tl_in_a_bits_data),
    .auto_tl_in_a_bits_corrupt(coupler_to_device_named_uart_3_auto_tl_in_a_bits_corrupt),
    .auto_tl_in_d_ready(coupler_to_device_named_uart_3_auto_tl_in_d_ready),
    .auto_tl_in_d_valid(coupler_to_device_named_uart_3_auto_tl_in_d_valid),
    .auto_tl_in_d_bits_opcode(coupler_to_device_named_uart_3_auto_tl_in_d_bits_opcode),
    .auto_tl_in_d_bits_size(coupler_to_device_named_uart_3_auto_tl_in_d_bits_size),
    .auto_tl_in_d_bits_source(coupler_to_device_named_uart_3_auto_tl_in_d_bits_source),
    .auto_tl_in_d_bits_data(coupler_to_device_named_uart_3_auto_tl_in_d_bits_data)
  );
  TLInterconnectCoupler_8 coupler_to_device_named_uart_4 ( // @[LazyModule.scala 432:27]
    .clock(coupler_to_device_named_uart_4_clock),
    .reset(coupler_to_device_named_uart_4_reset),
    .auto_control_xing_out_a_ready(coupler_to_device_named_uart_4_auto_control_xing_out_a_ready),
    .auto_control_xing_out_a_valid(coupler_to_device_named_uart_4_auto_control_xing_out_a_valid),
    .auto_control_xing_out_a_bits_opcode(coupler_to_device_named_uart_4_auto_control_xing_out_a_bits_opcode),
    .auto_control_xing_out_a_bits_param(coupler_to_device_named_uart_4_auto_control_xing_out_a_bits_param),
    .auto_control_xing_out_a_bits_size(coupler_to_device_named_uart_4_auto_control_xing_out_a_bits_size),
    .auto_control_xing_out_a_bits_source(coupler_to_device_named_uart_4_auto_control_xing_out_a_bits_source),
    .auto_control_xing_out_a_bits_address(coupler_to_device_named_uart_4_auto_control_xing_out_a_bits_address),
    .auto_control_xing_out_a_bits_mask(coupler_to_device_named_uart_4_auto_control_xing_out_a_bits_mask),
    .auto_control_xing_out_a_bits_data(coupler_to_device_named_uart_4_auto_control_xing_out_a_bits_data),
    .auto_control_xing_out_a_bits_corrupt(coupler_to_device_named_uart_4_auto_control_xing_out_a_bits_corrupt),
    .auto_control_xing_out_d_ready(coupler_to_device_named_uart_4_auto_control_xing_out_d_ready),
    .auto_control_xing_out_d_valid(coupler_to_device_named_uart_4_auto_control_xing_out_d_valid),
    .auto_control_xing_out_d_bits_opcode(coupler_to_device_named_uart_4_auto_control_xing_out_d_bits_opcode),
    .auto_control_xing_out_d_bits_size(coupler_to_device_named_uart_4_auto_control_xing_out_d_bits_size),
    .auto_control_xing_out_d_bits_source(coupler_to_device_named_uart_4_auto_control_xing_out_d_bits_source),
    .auto_control_xing_out_d_bits_data(coupler_to_device_named_uart_4_auto_control_xing_out_d_bits_data),
    .auto_tl_in_a_ready(coupler_to_device_named_uart_4_auto_tl_in_a_ready),
    .auto_tl_in_a_valid(coupler_to_device_named_uart_4_auto_tl_in_a_valid),
    .auto_tl_in_a_bits_opcode(coupler_to_device_named_uart_4_auto_tl_in_a_bits_opcode),
    .auto_tl_in_a_bits_param(coupler_to_device_named_uart_4_auto_tl_in_a_bits_param),
    .auto_tl_in_a_bits_size(coupler_to_device_named_uart_4_auto_tl_in_a_bits_size),
    .auto_tl_in_a_bits_source(coupler_to_device_named_uart_4_auto_tl_in_a_bits_source),
    .auto_tl_in_a_bits_address(coupler_to_device_named_uart_4_auto_tl_in_a_bits_address),
    .auto_tl_in_a_bits_mask(coupler_to_device_named_uart_4_auto_tl_in_a_bits_mask),
    .auto_tl_in_a_bits_data(coupler_to_device_named_uart_4_auto_tl_in_a_bits_data),
    .auto_tl_in_a_bits_corrupt(coupler_to_device_named_uart_4_auto_tl_in_a_bits_corrupt),
    .auto_tl_in_d_ready(coupler_to_device_named_uart_4_auto_tl_in_d_ready),
    .auto_tl_in_d_valid(coupler_to_device_named_uart_4_auto_tl_in_d_valid),
    .auto_tl_in_d_bits_opcode(coupler_to_device_named_uart_4_auto_tl_in_d_bits_opcode),
    .auto_tl_in_d_bits_size(coupler_to_device_named_uart_4_auto_tl_in_d_bits_size),
    .auto_tl_in_d_bits_source(coupler_to_device_named_uart_4_auto_tl_in_d_bits_source),
    .auto_tl_in_d_bits_data(coupler_to_device_named_uart_4_auto_tl_in_d_bits_data)
  );
  TLInterconnectCoupler_9 coupler_to_device_named_qspi_0 ( // @[LazyModule.scala 432:27]
    .clock(coupler_to_device_named_qspi_0_clock),
    .reset(coupler_to_device_named_qspi_0_reset),
    .auto_control_xing_out_a_ready(coupler_to_device_named_qspi_0_auto_control_xing_out_a_ready),
    .auto_control_xing_out_a_valid(coupler_to_device_named_qspi_0_auto_control_xing_out_a_valid),
    .auto_control_xing_out_a_bits_opcode(coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_opcode),
    .auto_control_xing_out_a_bits_param(coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_param),
    .auto_control_xing_out_a_bits_size(coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_size),
    .auto_control_xing_out_a_bits_source(coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_source),
    .auto_control_xing_out_a_bits_address(coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_address),
    .auto_control_xing_out_a_bits_mask(coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_mask),
    .auto_control_xing_out_a_bits_data(coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_data),
    .auto_control_xing_out_a_bits_corrupt(coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_corrupt),
    .auto_control_xing_out_d_ready(coupler_to_device_named_qspi_0_auto_control_xing_out_d_ready),
    .auto_control_xing_out_d_valid(coupler_to_device_named_qspi_0_auto_control_xing_out_d_valid),
    .auto_control_xing_out_d_bits_opcode(coupler_to_device_named_qspi_0_auto_control_xing_out_d_bits_opcode),
    .auto_control_xing_out_d_bits_size(coupler_to_device_named_qspi_0_auto_control_xing_out_d_bits_size),
    .auto_control_xing_out_d_bits_source(coupler_to_device_named_qspi_0_auto_control_xing_out_d_bits_source),
    .auto_control_xing_out_d_bits_data(coupler_to_device_named_qspi_0_auto_control_xing_out_d_bits_data),
    .auto_tl_in_a_ready(coupler_to_device_named_qspi_0_auto_tl_in_a_ready),
    .auto_tl_in_a_valid(coupler_to_device_named_qspi_0_auto_tl_in_a_valid),
    .auto_tl_in_a_bits_opcode(coupler_to_device_named_qspi_0_auto_tl_in_a_bits_opcode),
    .auto_tl_in_a_bits_param(coupler_to_device_named_qspi_0_auto_tl_in_a_bits_param),
    .auto_tl_in_a_bits_size(coupler_to_device_named_qspi_0_auto_tl_in_a_bits_size),
    .auto_tl_in_a_bits_source(coupler_to_device_named_qspi_0_auto_tl_in_a_bits_source),
    .auto_tl_in_a_bits_address(coupler_to_device_named_qspi_0_auto_tl_in_a_bits_address),
    .auto_tl_in_a_bits_mask(coupler_to_device_named_qspi_0_auto_tl_in_a_bits_mask),
    .auto_tl_in_a_bits_data(coupler_to_device_named_qspi_0_auto_tl_in_a_bits_data),
    .auto_tl_in_a_bits_corrupt(coupler_to_device_named_qspi_0_auto_tl_in_a_bits_corrupt),
    .auto_tl_in_d_ready(coupler_to_device_named_qspi_0_auto_tl_in_d_ready),
    .auto_tl_in_d_valid(coupler_to_device_named_qspi_0_auto_tl_in_d_valid),
    .auto_tl_in_d_bits_opcode(coupler_to_device_named_qspi_0_auto_tl_in_d_bits_opcode),
    .auto_tl_in_d_bits_size(coupler_to_device_named_qspi_0_auto_tl_in_d_bits_size),
    .auto_tl_in_d_bits_source(coupler_to_device_named_qspi_0_auto_tl_in_d_bits_source),
    .auto_tl_in_d_bits_data(coupler_to_device_named_qspi_0_auto_tl_in_d_bits_data)
  );
  TLInterconnectCoupler_10 coupler_to_device_named_qspi_0_1 ( // @[LazyModule.scala 432:27]
    .clock(coupler_to_device_named_qspi_0_1_clock),
    .reset(coupler_to_device_named_qspi_0_1_reset),
    .auto_mem_xing_out_a_ready(coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_ready),
    .auto_mem_xing_out_a_valid(coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_valid),
    .auto_mem_xing_out_a_bits_opcode(coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_opcode),
    .auto_mem_xing_out_a_bits_param(coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_param),
    .auto_mem_xing_out_a_bits_size(coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_size),
    .auto_mem_xing_out_a_bits_source(coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_source),
    .auto_mem_xing_out_a_bits_address(coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_address),
    .auto_mem_xing_out_a_bits_mask(coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_mask),
    .auto_mem_xing_out_a_bits_corrupt(coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_corrupt),
    .auto_mem_xing_out_d_ready(coupler_to_device_named_qspi_0_1_auto_mem_xing_out_d_ready),
    .auto_mem_xing_out_d_valid(coupler_to_device_named_qspi_0_1_auto_mem_xing_out_d_valid),
    .auto_mem_xing_out_d_bits_size(coupler_to_device_named_qspi_0_1_auto_mem_xing_out_d_bits_size),
    .auto_mem_xing_out_d_bits_source(coupler_to_device_named_qspi_0_1_auto_mem_xing_out_d_bits_source),
    .auto_mem_xing_out_d_bits_data(coupler_to_device_named_qspi_0_1_auto_mem_xing_out_d_bits_data),
    .auto_tl_in_a_ready(coupler_to_device_named_qspi_0_1_auto_tl_in_a_ready),
    .auto_tl_in_a_valid(coupler_to_device_named_qspi_0_1_auto_tl_in_a_valid),
    .auto_tl_in_a_bits_opcode(coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_opcode),
    .auto_tl_in_a_bits_param(coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_param),
    .auto_tl_in_a_bits_size(coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_size),
    .auto_tl_in_a_bits_source(coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_source),
    .auto_tl_in_a_bits_address(coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_address),
    .auto_tl_in_a_bits_mask(coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_mask),
    .auto_tl_in_a_bits_corrupt(coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_corrupt),
    .auto_tl_in_d_ready(coupler_to_device_named_qspi_0_1_auto_tl_in_d_ready),
    .auto_tl_in_d_valid(coupler_to_device_named_qspi_0_1_auto_tl_in_d_valid),
    .auto_tl_in_d_bits_size(coupler_to_device_named_qspi_0_1_auto_tl_in_d_bits_size),
    .auto_tl_in_d_bits_source(coupler_to_device_named_qspi_0_1_auto_tl_in_d_bits_source),
    .auto_tl_in_d_bits_data(coupler_to_device_named_qspi_0_1_auto_tl_in_d_bits_data)
  );
  TLInterconnectCoupler_11 coupler_to_device_named_qspi_ram_0 ( // @[LazyModule.scala 432:27]
    .clock(coupler_to_device_named_qspi_ram_0_clock),
    .reset(coupler_to_device_named_qspi_ram_0_reset),
    .auto_control_xing_out_a_ready(coupler_to_device_named_qspi_ram_0_auto_control_xing_out_a_ready),
    .auto_control_xing_out_a_valid(coupler_to_device_named_qspi_ram_0_auto_control_xing_out_a_valid),
    .auto_control_xing_out_a_bits_opcode(coupler_to_device_named_qspi_ram_0_auto_control_xing_out_a_bits_opcode),
    .auto_control_xing_out_a_bits_param(coupler_to_device_named_qspi_ram_0_auto_control_xing_out_a_bits_param),
    .auto_control_xing_out_a_bits_size(coupler_to_device_named_qspi_ram_0_auto_control_xing_out_a_bits_size),
    .auto_control_xing_out_a_bits_source(coupler_to_device_named_qspi_ram_0_auto_control_xing_out_a_bits_source),
    .auto_control_xing_out_a_bits_address(coupler_to_device_named_qspi_ram_0_auto_control_xing_out_a_bits_address),
    .auto_control_xing_out_a_bits_mask(coupler_to_device_named_qspi_ram_0_auto_control_xing_out_a_bits_mask),
    .auto_control_xing_out_a_bits_data(coupler_to_device_named_qspi_ram_0_auto_control_xing_out_a_bits_data),
    .auto_control_xing_out_a_bits_corrupt(coupler_to_device_named_qspi_ram_0_auto_control_xing_out_a_bits_corrupt),
    .auto_control_xing_out_d_ready(coupler_to_device_named_qspi_ram_0_auto_control_xing_out_d_ready),
    .auto_control_xing_out_d_valid(coupler_to_device_named_qspi_ram_0_auto_control_xing_out_d_valid),
    .auto_control_xing_out_d_bits_opcode(coupler_to_device_named_qspi_ram_0_auto_control_xing_out_d_bits_opcode),
    .auto_control_xing_out_d_bits_size(coupler_to_device_named_qspi_ram_0_auto_control_xing_out_d_bits_size),
    .auto_control_xing_out_d_bits_source(coupler_to_device_named_qspi_ram_0_auto_control_xing_out_d_bits_source),
    .auto_control_xing_out_d_bits_data(coupler_to_device_named_qspi_ram_0_auto_control_xing_out_d_bits_data),
    .auto_tl_in_a_ready(coupler_to_device_named_qspi_ram_0_auto_tl_in_a_ready),
    .auto_tl_in_a_valid(coupler_to_device_named_qspi_ram_0_auto_tl_in_a_valid),
    .auto_tl_in_a_bits_opcode(coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_opcode),
    .auto_tl_in_a_bits_param(coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_param),
    .auto_tl_in_a_bits_size(coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_size),
    .auto_tl_in_a_bits_source(coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_source),
    .auto_tl_in_a_bits_address(coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_address),
    .auto_tl_in_a_bits_mask(coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_mask),
    .auto_tl_in_a_bits_data(coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_data),
    .auto_tl_in_a_bits_corrupt(coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_corrupt),
    .auto_tl_in_d_ready(coupler_to_device_named_qspi_ram_0_auto_tl_in_d_ready),
    .auto_tl_in_d_valid(coupler_to_device_named_qspi_ram_0_auto_tl_in_d_valid),
    .auto_tl_in_d_bits_opcode(coupler_to_device_named_qspi_ram_0_auto_tl_in_d_bits_opcode),
    .auto_tl_in_d_bits_size(coupler_to_device_named_qspi_ram_0_auto_tl_in_d_bits_size),
    .auto_tl_in_d_bits_source(coupler_to_device_named_qspi_ram_0_auto_tl_in_d_bits_source),
    .auto_tl_in_d_bits_data(coupler_to_device_named_qspi_ram_0_auto_tl_in_d_bits_data)
  );
  TLInterconnectCoupler_12 coupler_to_device_named_spi_0 ( // @[LazyModule.scala 432:27]
    .clock(coupler_to_device_named_spi_0_clock),
    .reset(coupler_to_device_named_spi_0_reset),
    .auto_control_xing_out_a_ready(coupler_to_device_named_spi_0_auto_control_xing_out_a_ready),
    .auto_control_xing_out_a_valid(coupler_to_device_named_spi_0_auto_control_xing_out_a_valid),
    .auto_control_xing_out_a_bits_opcode(coupler_to_device_named_spi_0_auto_control_xing_out_a_bits_opcode),
    .auto_control_xing_out_a_bits_param(coupler_to_device_named_spi_0_auto_control_xing_out_a_bits_param),
    .auto_control_xing_out_a_bits_size(coupler_to_device_named_spi_0_auto_control_xing_out_a_bits_size),
    .auto_control_xing_out_a_bits_source(coupler_to_device_named_spi_0_auto_control_xing_out_a_bits_source),
    .auto_control_xing_out_a_bits_address(coupler_to_device_named_spi_0_auto_control_xing_out_a_bits_address),
    .auto_control_xing_out_a_bits_mask(coupler_to_device_named_spi_0_auto_control_xing_out_a_bits_mask),
    .auto_control_xing_out_a_bits_data(coupler_to_device_named_spi_0_auto_control_xing_out_a_bits_data),
    .auto_control_xing_out_a_bits_corrupt(coupler_to_device_named_spi_0_auto_control_xing_out_a_bits_corrupt),
    .auto_control_xing_out_d_ready(coupler_to_device_named_spi_0_auto_control_xing_out_d_ready),
    .auto_control_xing_out_d_valid(coupler_to_device_named_spi_0_auto_control_xing_out_d_valid),
    .auto_control_xing_out_d_bits_opcode(coupler_to_device_named_spi_0_auto_control_xing_out_d_bits_opcode),
    .auto_control_xing_out_d_bits_size(coupler_to_device_named_spi_0_auto_control_xing_out_d_bits_size),
    .auto_control_xing_out_d_bits_source(coupler_to_device_named_spi_0_auto_control_xing_out_d_bits_source),
    .auto_control_xing_out_d_bits_data(coupler_to_device_named_spi_0_auto_control_xing_out_d_bits_data),
    .auto_tl_in_a_ready(coupler_to_device_named_spi_0_auto_tl_in_a_ready),
    .auto_tl_in_a_valid(coupler_to_device_named_spi_0_auto_tl_in_a_valid),
    .auto_tl_in_a_bits_opcode(coupler_to_device_named_spi_0_auto_tl_in_a_bits_opcode),
    .auto_tl_in_a_bits_param(coupler_to_device_named_spi_0_auto_tl_in_a_bits_param),
    .auto_tl_in_a_bits_size(coupler_to_device_named_spi_0_auto_tl_in_a_bits_size),
    .auto_tl_in_a_bits_source(coupler_to_device_named_spi_0_auto_tl_in_a_bits_source),
    .auto_tl_in_a_bits_address(coupler_to_device_named_spi_0_auto_tl_in_a_bits_address),
    .auto_tl_in_a_bits_mask(coupler_to_device_named_spi_0_auto_tl_in_a_bits_mask),
    .auto_tl_in_a_bits_data(coupler_to_device_named_spi_0_auto_tl_in_a_bits_data),
    .auto_tl_in_a_bits_corrupt(coupler_to_device_named_spi_0_auto_tl_in_a_bits_corrupt),
    .auto_tl_in_d_ready(coupler_to_device_named_spi_0_auto_tl_in_d_ready),
    .auto_tl_in_d_valid(coupler_to_device_named_spi_0_auto_tl_in_d_valid),
    .auto_tl_in_d_bits_opcode(coupler_to_device_named_spi_0_auto_tl_in_d_bits_opcode),
    .auto_tl_in_d_bits_size(coupler_to_device_named_spi_0_auto_tl_in_d_bits_size),
    .auto_tl_in_d_bits_source(coupler_to_device_named_spi_0_auto_tl_in_d_bits_source),
    .auto_tl_in_d_bits_data(coupler_to_device_named_spi_0_auto_tl_in_d_bits_data)
  );
  TLInterconnectCoupler_13 coupler_to_device_named_gpio_0 ( // @[LazyModule.scala 432:27]
    .clock(coupler_to_device_named_gpio_0_clock),
    .reset(coupler_to_device_named_gpio_0_reset),
    .auto_control_xing_out_a_ready(coupler_to_device_named_gpio_0_auto_control_xing_out_a_ready),
    .auto_control_xing_out_a_valid(coupler_to_device_named_gpio_0_auto_control_xing_out_a_valid),
    .auto_control_xing_out_a_bits_opcode(coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_opcode),
    .auto_control_xing_out_a_bits_param(coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_param),
    .auto_control_xing_out_a_bits_size(coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_size),
    .auto_control_xing_out_a_bits_source(coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_source),
    .auto_control_xing_out_a_bits_address(coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_address),
    .auto_control_xing_out_a_bits_mask(coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_mask),
    .auto_control_xing_out_a_bits_data(coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_data),
    .auto_control_xing_out_a_bits_corrupt(coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_corrupt),
    .auto_control_xing_out_d_ready(coupler_to_device_named_gpio_0_auto_control_xing_out_d_ready),
    .auto_control_xing_out_d_valid(coupler_to_device_named_gpio_0_auto_control_xing_out_d_valid),
    .auto_control_xing_out_d_bits_opcode(coupler_to_device_named_gpio_0_auto_control_xing_out_d_bits_opcode),
    .auto_control_xing_out_d_bits_size(coupler_to_device_named_gpio_0_auto_control_xing_out_d_bits_size),
    .auto_control_xing_out_d_bits_source(coupler_to_device_named_gpio_0_auto_control_xing_out_d_bits_source),
    .auto_control_xing_out_d_bits_data(coupler_to_device_named_gpio_0_auto_control_xing_out_d_bits_data),
    .auto_tl_in_a_ready(coupler_to_device_named_gpio_0_auto_tl_in_a_ready),
    .auto_tl_in_a_valid(coupler_to_device_named_gpio_0_auto_tl_in_a_valid),
    .auto_tl_in_a_bits_opcode(coupler_to_device_named_gpio_0_auto_tl_in_a_bits_opcode),
    .auto_tl_in_a_bits_param(coupler_to_device_named_gpio_0_auto_tl_in_a_bits_param),
    .auto_tl_in_a_bits_size(coupler_to_device_named_gpio_0_auto_tl_in_a_bits_size),
    .auto_tl_in_a_bits_source(coupler_to_device_named_gpio_0_auto_tl_in_a_bits_source),
    .auto_tl_in_a_bits_address(coupler_to_device_named_gpio_0_auto_tl_in_a_bits_address),
    .auto_tl_in_a_bits_mask(coupler_to_device_named_gpio_0_auto_tl_in_a_bits_mask),
    .auto_tl_in_a_bits_data(coupler_to_device_named_gpio_0_auto_tl_in_a_bits_data),
    .auto_tl_in_a_bits_corrupt(coupler_to_device_named_gpio_0_auto_tl_in_a_bits_corrupt),
    .auto_tl_in_d_ready(coupler_to_device_named_gpio_0_auto_tl_in_d_ready),
    .auto_tl_in_d_valid(coupler_to_device_named_gpio_0_auto_tl_in_d_valid),
    .auto_tl_in_d_bits_opcode(coupler_to_device_named_gpio_0_auto_tl_in_d_bits_opcode),
    .auto_tl_in_d_bits_size(coupler_to_device_named_gpio_0_auto_tl_in_d_bits_size),
    .auto_tl_in_d_bits_source(coupler_to_device_named_gpio_0_auto_tl_in_d_bits_source),
    .auto_tl_in_d_bits_data(coupler_to_device_named_gpio_0_auto_tl_in_d_bits_data)
  );
  TLInterconnectCoupler_14 coupler_to_device_named_pwm_0 ( // @[LazyModule.scala 432:27]
    .clock(coupler_to_device_named_pwm_0_clock),
    .reset(coupler_to_device_named_pwm_0_reset),
    .auto_control_xing_out_a_ready(coupler_to_device_named_pwm_0_auto_control_xing_out_a_ready),
    .auto_control_xing_out_a_valid(coupler_to_device_named_pwm_0_auto_control_xing_out_a_valid),
    .auto_control_xing_out_a_bits_opcode(coupler_to_device_named_pwm_0_auto_control_xing_out_a_bits_opcode),
    .auto_control_xing_out_a_bits_param(coupler_to_device_named_pwm_0_auto_control_xing_out_a_bits_param),
    .auto_control_xing_out_a_bits_size(coupler_to_device_named_pwm_0_auto_control_xing_out_a_bits_size),
    .auto_control_xing_out_a_bits_source(coupler_to_device_named_pwm_0_auto_control_xing_out_a_bits_source),
    .auto_control_xing_out_a_bits_address(coupler_to_device_named_pwm_0_auto_control_xing_out_a_bits_address),
    .auto_control_xing_out_a_bits_mask(coupler_to_device_named_pwm_0_auto_control_xing_out_a_bits_mask),
    .auto_control_xing_out_a_bits_data(coupler_to_device_named_pwm_0_auto_control_xing_out_a_bits_data),
    .auto_control_xing_out_a_bits_corrupt(coupler_to_device_named_pwm_0_auto_control_xing_out_a_bits_corrupt),
    .auto_control_xing_out_d_ready(coupler_to_device_named_pwm_0_auto_control_xing_out_d_ready),
    .auto_control_xing_out_d_valid(coupler_to_device_named_pwm_0_auto_control_xing_out_d_valid),
    .auto_control_xing_out_d_bits_opcode(coupler_to_device_named_pwm_0_auto_control_xing_out_d_bits_opcode),
    .auto_control_xing_out_d_bits_size(coupler_to_device_named_pwm_0_auto_control_xing_out_d_bits_size),
    .auto_control_xing_out_d_bits_source(coupler_to_device_named_pwm_0_auto_control_xing_out_d_bits_source),
    .auto_control_xing_out_d_bits_data(coupler_to_device_named_pwm_0_auto_control_xing_out_d_bits_data),
    .auto_tl_in_a_ready(coupler_to_device_named_pwm_0_auto_tl_in_a_ready),
    .auto_tl_in_a_valid(coupler_to_device_named_pwm_0_auto_tl_in_a_valid),
    .auto_tl_in_a_bits_opcode(coupler_to_device_named_pwm_0_auto_tl_in_a_bits_opcode),
    .auto_tl_in_a_bits_param(coupler_to_device_named_pwm_0_auto_tl_in_a_bits_param),
    .auto_tl_in_a_bits_size(coupler_to_device_named_pwm_0_auto_tl_in_a_bits_size),
    .auto_tl_in_a_bits_source(coupler_to_device_named_pwm_0_auto_tl_in_a_bits_source),
    .auto_tl_in_a_bits_address(coupler_to_device_named_pwm_0_auto_tl_in_a_bits_address),
    .auto_tl_in_a_bits_mask(coupler_to_device_named_pwm_0_auto_tl_in_a_bits_mask),
    .auto_tl_in_a_bits_data(coupler_to_device_named_pwm_0_auto_tl_in_a_bits_data),
    .auto_tl_in_a_bits_corrupt(coupler_to_device_named_pwm_0_auto_tl_in_a_bits_corrupt),
    .auto_tl_in_d_ready(coupler_to_device_named_pwm_0_auto_tl_in_d_ready),
    .auto_tl_in_d_valid(coupler_to_device_named_pwm_0_auto_tl_in_d_valid),
    .auto_tl_in_d_bits_opcode(coupler_to_device_named_pwm_0_auto_tl_in_d_bits_opcode),
    .auto_tl_in_d_bits_size(coupler_to_device_named_pwm_0_auto_tl_in_d_bits_size),
    .auto_tl_in_d_bits_source(coupler_to_device_named_pwm_0_auto_tl_in_d_bits_source),
    .auto_tl_in_d_bits_data(coupler_to_device_named_pwm_0_auto_tl_in_d_bits_data)
  );
  TLInterconnectCoupler_15 coupler_to_device_named_pwm_1 ( // @[LazyModule.scala 432:27]
    .clock(coupler_to_device_named_pwm_1_clock),
    .reset(coupler_to_device_named_pwm_1_reset),
    .auto_control_xing_out_a_ready(coupler_to_device_named_pwm_1_auto_control_xing_out_a_ready),
    .auto_control_xing_out_a_valid(coupler_to_device_named_pwm_1_auto_control_xing_out_a_valid),
    .auto_control_xing_out_a_bits_opcode(coupler_to_device_named_pwm_1_auto_control_xing_out_a_bits_opcode),
    .auto_control_xing_out_a_bits_param(coupler_to_device_named_pwm_1_auto_control_xing_out_a_bits_param),
    .auto_control_xing_out_a_bits_size(coupler_to_device_named_pwm_1_auto_control_xing_out_a_bits_size),
    .auto_control_xing_out_a_bits_source(coupler_to_device_named_pwm_1_auto_control_xing_out_a_bits_source),
    .auto_control_xing_out_a_bits_address(coupler_to_device_named_pwm_1_auto_control_xing_out_a_bits_address),
    .auto_control_xing_out_a_bits_mask(coupler_to_device_named_pwm_1_auto_control_xing_out_a_bits_mask),
    .auto_control_xing_out_a_bits_data(coupler_to_device_named_pwm_1_auto_control_xing_out_a_bits_data),
    .auto_control_xing_out_a_bits_corrupt(coupler_to_device_named_pwm_1_auto_control_xing_out_a_bits_corrupt),
    .auto_control_xing_out_d_ready(coupler_to_device_named_pwm_1_auto_control_xing_out_d_ready),
    .auto_control_xing_out_d_valid(coupler_to_device_named_pwm_1_auto_control_xing_out_d_valid),
    .auto_control_xing_out_d_bits_opcode(coupler_to_device_named_pwm_1_auto_control_xing_out_d_bits_opcode),
    .auto_control_xing_out_d_bits_size(coupler_to_device_named_pwm_1_auto_control_xing_out_d_bits_size),
    .auto_control_xing_out_d_bits_source(coupler_to_device_named_pwm_1_auto_control_xing_out_d_bits_source),
    .auto_control_xing_out_d_bits_data(coupler_to_device_named_pwm_1_auto_control_xing_out_d_bits_data),
    .auto_tl_in_a_ready(coupler_to_device_named_pwm_1_auto_tl_in_a_ready),
    .auto_tl_in_a_valid(coupler_to_device_named_pwm_1_auto_tl_in_a_valid),
    .auto_tl_in_a_bits_opcode(coupler_to_device_named_pwm_1_auto_tl_in_a_bits_opcode),
    .auto_tl_in_a_bits_param(coupler_to_device_named_pwm_1_auto_tl_in_a_bits_param),
    .auto_tl_in_a_bits_size(coupler_to_device_named_pwm_1_auto_tl_in_a_bits_size),
    .auto_tl_in_a_bits_source(coupler_to_device_named_pwm_1_auto_tl_in_a_bits_source),
    .auto_tl_in_a_bits_address(coupler_to_device_named_pwm_1_auto_tl_in_a_bits_address),
    .auto_tl_in_a_bits_mask(coupler_to_device_named_pwm_1_auto_tl_in_a_bits_mask),
    .auto_tl_in_a_bits_data(coupler_to_device_named_pwm_1_auto_tl_in_a_bits_data),
    .auto_tl_in_a_bits_corrupt(coupler_to_device_named_pwm_1_auto_tl_in_a_bits_corrupt),
    .auto_tl_in_d_ready(coupler_to_device_named_pwm_1_auto_tl_in_d_ready),
    .auto_tl_in_d_valid(coupler_to_device_named_pwm_1_auto_tl_in_d_valid),
    .auto_tl_in_d_bits_opcode(coupler_to_device_named_pwm_1_auto_tl_in_d_bits_opcode),
    .auto_tl_in_d_bits_size(coupler_to_device_named_pwm_1_auto_tl_in_d_bits_size),
    .auto_tl_in_d_bits_source(coupler_to_device_named_pwm_1_auto_tl_in_d_bits_source),
    .auto_tl_in_d_bits_data(coupler_to_device_named_pwm_1_auto_tl_in_d_bits_data)
  );
  TLInterconnectCoupler_16 coupler_to_device_named_pwm_2 ( // @[LazyModule.scala 432:27]
    .clock(coupler_to_device_named_pwm_2_clock),
    .reset(coupler_to_device_named_pwm_2_reset),
    .auto_control_xing_out_a_ready(coupler_to_device_named_pwm_2_auto_control_xing_out_a_ready),
    .auto_control_xing_out_a_valid(coupler_to_device_named_pwm_2_auto_control_xing_out_a_valid),
    .auto_control_xing_out_a_bits_opcode(coupler_to_device_named_pwm_2_auto_control_xing_out_a_bits_opcode),
    .auto_control_xing_out_a_bits_param(coupler_to_device_named_pwm_2_auto_control_xing_out_a_bits_param),
    .auto_control_xing_out_a_bits_size(coupler_to_device_named_pwm_2_auto_control_xing_out_a_bits_size),
    .auto_control_xing_out_a_bits_source(coupler_to_device_named_pwm_2_auto_control_xing_out_a_bits_source),
    .auto_control_xing_out_a_bits_address(coupler_to_device_named_pwm_2_auto_control_xing_out_a_bits_address),
    .auto_control_xing_out_a_bits_mask(coupler_to_device_named_pwm_2_auto_control_xing_out_a_bits_mask),
    .auto_control_xing_out_a_bits_data(coupler_to_device_named_pwm_2_auto_control_xing_out_a_bits_data),
    .auto_control_xing_out_a_bits_corrupt(coupler_to_device_named_pwm_2_auto_control_xing_out_a_bits_corrupt),
    .auto_control_xing_out_d_ready(coupler_to_device_named_pwm_2_auto_control_xing_out_d_ready),
    .auto_control_xing_out_d_valid(coupler_to_device_named_pwm_2_auto_control_xing_out_d_valid),
    .auto_control_xing_out_d_bits_opcode(coupler_to_device_named_pwm_2_auto_control_xing_out_d_bits_opcode),
    .auto_control_xing_out_d_bits_size(coupler_to_device_named_pwm_2_auto_control_xing_out_d_bits_size),
    .auto_control_xing_out_d_bits_source(coupler_to_device_named_pwm_2_auto_control_xing_out_d_bits_source),
    .auto_control_xing_out_d_bits_data(coupler_to_device_named_pwm_2_auto_control_xing_out_d_bits_data),
    .auto_tl_in_a_ready(coupler_to_device_named_pwm_2_auto_tl_in_a_ready),
    .auto_tl_in_a_valid(coupler_to_device_named_pwm_2_auto_tl_in_a_valid),
    .auto_tl_in_a_bits_opcode(coupler_to_device_named_pwm_2_auto_tl_in_a_bits_opcode),
    .auto_tl_in_a_bits_param(coupler_to_device_named_pwm_2_auto_tl_in_a_bits_param),
    .auto_tl_in_a_bits_size(coupler_to_device_named_pwm_2_auto_tl_in_a_bits_size),
    .auto_tl_in_a_bits_source(coupler_to_device_named_pwm_2_auto_tl_in_a_bits_source),
    .auto_tl_in_a_bits_address(coupler_to_device_named_pwm_2_auto_tl_in_a_bits_address),
    .auto_tl_in_a_bits_mask(coupler_to_device_named_pwm_2_auto_tl_in_a_bits_mask),
    .auto_tl_in_a_bits_data(coupler_to_device_named_pwm_2_auto_tl_in_a_bits_data),
    .auto_tl_in_a_bits_corrupt(coupler_to_device_named_pwm_2_auto_tl_in_a_bits_corrupt),
    .auto_tl_in_d_ready(coupler_to_device_named_pwm_2_auto_tl_in_d_ready),
    .auto_tl_in_d_valid(coupler_to_device_named_pwm_2_auto_tl_in_d_valid),
    .auto_tl_in_d_bits_opcode(coupler_to_device_named_pwm_2_auto_tl_in_d_bits_opcode),
    .auto_tl_in_d_bits_size(coupler_to_device_named_pwm_2_auto_tl_in_d_bits_size),
    .auto_tl_in_d_bits_source(coupler_to_device_named_pwm_2_auto_tl_in_d_bits_source),
    .auto_tl_in_d_bits_data(coupler_to_device_named_pwm_2_auto_tl_in_d_bits_data)
  );
  TLInterconnectCoupler_17 coupler_to_device_named_i2c_0 ( // @[LazyModule.scala 432:27]
    .clock(coupler_to_device_named_i2c_0_clock),
    .reset(coupler_to_device_named_i2c_0_reset),
    .auto_control_xing_out_a_ready(coupler_to_device_named_i2c_0_auto_control_xing_out_a_ready),
    .auto_control_xing_out_a_valid(coupler_to_device_named_i2c_0_auto_control_xing_out_a_valid),
    .auto_control_xing_out_a_bits_opcode(coupler_to_device_named_i2c_0_auto_control_xing_out_a_bits_opcode),
    .auto_control_xing_out_a_bits_param(coupler_to_device_named_i2c_0_auto_control_xing_out_a_bits_param),
    .auto_control_xing_out_a_bits_size(coupler_to_device_named_i2c_0_auto_control_xing_out_a_bits_size),
    .auto_control_xing_out_a_bits_source(coupler_to_device_named_i2c_0_auto_control_xing_out_a_bits_source),
    .auto_control_xing_out_a_bits_address(coupler_to_device_named_i2c_0_auto_control_xing_out_a_bits_address),
    .auto_control_xing_out_a_bits_mask(coupler_to_device_named_i2c_0_auto_control_xing_out_a_bits_mask),
    .auto_control_xing_out_a_bits_data(coupler_to_device_named_i2c_0_auto_control_xing_out_a_bits_data),
    .auto_control_xing_out_a_bits_corrupt(coupler_to_device_named_i2c_0_auto_control_xing_out_a_bits_corrupt),
    .auto_control_xing_out_d_ready(coupler_to_device_named_i2c_0_auto_control_xing_out_d_ready),
    .auto_control_xing_out_d_valid(coupler_to_device_named_i2c_0_auto_control_xing_out_d_valid),
    .auto_control_xing_out_d_bits_opcode(coupler_to_device_named_i2c_0_auto_control_xing_out_d_bits_opcode),
    .auto_control_xing_out_d_bits_size(coupler_to_device_named_i2c_0_auto_control_xing_out_d_bits_size),
    .auto_control_xing_out_d_bits_source(coupler_to_device_named_i2c_0_auto_control_xing_out_d_bits_source),
    .auto_control_xing_out_d_bits_data(coupler_to_device_named_i2c_0_auto_control_xing_out_d_bits_data),
    .auto_tl_in_a_ready(coupler_to_device_named_i2c_0_auto_tl_in_a_ready),
    .auto_tl_in_a_valid(coupler_to_device_named_i2c_0_auto_tl_in_a_valid),
    .auto_tl_in_a_bits_opcode(coupler_to_device_named_i2c_0_auto_tl_in_a_bits_opcode),
    .auto_tl_in_a_bits_param(coupler_to_device_named_i2c_0_auto_tl_in_a_bits_param),
    .auto_tl_in_a_bits_size(coupler_to_device_named_i2c_0_auto_tl_in_a_bits_size),
    .auto_tl_in_a_bits_source(coupler_to_device_named_i2c_0_auto_tl_in_a_bits_source),
    .auto_tl_in_a_bits_address(coupler_to_device_named_i2c_0_auto_tl_in_a_bits_address),
    .auto_tl_in_a_bits_mask(coupler_to_device_named_i2c_0_auto_tl_in_a_bits_mask),
    .auto_tl_in_a_bits_data(coupler_to_device_named_i2c_0_auto_tl_in_a_bits_data),
    .auto_tl_in_a_bits_corrupt(coupler_to_device_named_i2c_0_auto_tl_in_a_bits_corrupt),
    .auto_tl_in_d_ready(coupler_to_device_named_i2c_0_auto_tl_in_d_ready),
    .auto_tl_in_d_valid(coupler_to_device_named_i2c_0_auto_tl_in_d_valid),
    .auto_tl_in_d_bits_opcode(coupler_to_device_named_i2c_0_auto_tl_in_d_bits_opcode),
    .auto_tl_in_d_bits_size(coupler_to_device_named_i2c_0_auto_tl_in_d_bits_size),
    .auto_tl_in_d_bits_source(coupler_to_device_named_i2c_0_auto_tl_in_d_bits_source),
    .auto_tl_in_d_bits_data(coupler_to_device_named_i2c_0_auto_tl_in_d_bits_data)
  );
  TLInterconnectCoupler_18 coupler_to_device_named_i2c_1 ( // @[LazyModule.scala 432:27]
    .clock(coupler_to_device_named_i2c_1_clock),
    .reset(coupler_to_device_named_i2c_1_reset),
    .auto_control_xing_out_a_ready(coupler_to_device_named_i2c_1_auto_control_xing_out_a_ready),
    .auto_control_xing_out_a_valid(coupler_to_device_named_i2c_1_auto_control_xing_out_a_valid),
    .auto_control_xing_out_a_bits_opcode(coupler_to_device_named_i2c_1_auto_control_xing_out_a_bits_opcode),
    .auto_control_xing_out_a_bits_param(coupler_to_device_named_i2c_1_auto_control_xing_out_a_bits_param),
    .auto_control_xing_out_a_bits_size(coupler_to_device_named_i2c_1_auto_control_xing_out_a_bits_size),
    .auto_control_xing_out_a_bits_source(coupler_to_device_named_i2c_1_auto_control_xing_out_a_bits_source),
    .auto_control_xing_out_a_bits_address(coupler_to_device_named_i2c_1_auto_control_xing_out_a_bits_address),
    .auto_control_xing_out_a_bits_mask(coupler_to_device_named_i2c_1_auto_control_xing_out_a_bits_mask),
    .auto_control_xing_out_a_bits_data(coupler_to_device_named_i2c_1_auto_control_xing_out_a_bits_data),
    .auto_control_xing_out_a_bits_corrupt(coupler_to_device_named_i2c_1_auto_control_xing_out_a_bits_corrupt),
    .auto_control_xing_out_d_ready(coupler_to_device_named_i2c_1_auto_control_xing_out_d_ready),
    .auto_control_xing_out_d_valid(coupler_to_device_named_i2c_1_auto_control_xing_out_d_valid),
    .auto_control_xing_out_d_bits_opcode(coupler_to_device_named_i2c_1_auto_control_xing_out_d_bits_opcode),
    .auto_control_xing_out_d_bits_size(coupler_to_device_named_i2c_1_auto_control_xing_out_d_bits_size),
    .auto_control_xing_out_d_bits_source(coupler_to_device_named_i2c_1_auto_control_xing_out_d_bits_source),
    .auto_control_xing_out_d_bits_data(coupler_to_device_named_i2c_1_auto_control_xing_out_d_bits_data),
    .auto_tl_in_a_ready(coupler_to_device_named_i2c_1_auto_tl_in_a_ready),
    .auto_tl_in_a_valid(coupler_to_device_named_i2c_1_auto_tl_in_a_valid),
    .auto_tl_in_a_bits_opcode(coupler_to_device_named_i2c_1_auto_tl_in_a_bits_opcode),
    .auto_tl_in_a_bits_param(coupler_to_device_named_i2c_1_auto_tl_in_a_bits_param),
    .auto_tl_in_a_bits_size(coupler_to_device_named_i2c_1_auto_tl_in_a_bits_size),
    .auto_tl_in_a_bits_source(coupler_to_device_named_i2c_1_auto_tl_in_a_bits_source),
    .auto_tl_in_a_bits_address(coupler_to_device_named_i2c_1_auto_tl_in_a_bits_address),
    .auto_tl_in_a_bits_mask(coupler_to_device_named_i2c_1_auto_tl_in_a_bits_mask),
    .auto_tl_in_a_bits_data(coupler_to_device_named_i2c_1_auto_tl_in_a_bits_data),
    .auto_tl_in_a_bits_corrupt(coupler_to_device_named_i2c_1_auto_tl_in_a_bits_corrupt),
    .auto_tl_in_d_ready(coupler_to_device_named_i2c_1_auto_tl_in_d_ready),
    .auto_tl_in_d_valid(coupler_to_device_named_i2c_1_auto_tl_in_d_valid),
    .auto_tl_in_d_bits_opcode(coupler_to_device_named_i2c_1_auto_tl_in_d_bits_opcode),
    .auto_tl_in_d_bits_size(coupler_to_device_named_i2c_1_auto_tl_in_d_bits_size),
    .auto_tl_in_d_bits_source(coupler_to_device_named_i2c_1_auto_tl_in_d_bits_source),
    .auto_tl_in_d_bits_data(coupler_to_device_named_i2c_1_auto_tl_in_d_bits_data)
  );
  assign auto_coupler_to_device_named_i2c_1_control_xing_out_a_valid =
    coupler_to_device_named_i2c_1_auto_control_xing_out_a_valid; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_opcode =
    coupler_to_device_named_i2c_1_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_param =
    coupler_to_device_named_i2c_1_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_size =
    coupler_to_device_named_i2c_1_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_source =
    coupler_to_device_named_i2c_1_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_address =
    coupler_to_device_named_i2c_1_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_mask =
    coupler_to_device_named_i2c_1_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_data =
    coupler_to_device_named_i2c_1_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_corrupt =
    coupler_to_device_named_i2c_1_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_i2c_1_control_xing_out_d_ready =
    coupler_to_device_named_i2c_1_auto_control_xing_out_d_ready; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_i2c_0_control_xing_out_a_valid =
    coupler_to_device_named_i2c_0_auto_control_xing_out_a_valid; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_opcode =
    coupler_to_device_named_i2c_0_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_param =
    coupler_to_device_named_i2c_0_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_size =
    coupler_to_device_named_i2c_0_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_source =
    coupler_to_device_named_i2c_0_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_address =
    coupler_to_device_named_i2c_0_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_mask =
    coupler_to_device_named_i2c_0_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_data =
    coupler_to_device_named_i2c_0_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_corrupt =
    coupler_to_device_named_i2c_0_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_i2c_0_control_xing_out_d_ready =
    coupler_to_device_named_i2c_0_auto_control_xing_out_d_ready; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_pwm_2_control_xing_out_a_valid =
    coupler_to_device_named_pwm_2_auto_control_xing_out_a_valid; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_opcode =
    coupler_to_device_named_pwm_2_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_param =
    coupler_to_device_named_pwm_2_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_size =
    coupler_to_device_named_pwm_2_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_source =
    coupler_to_device_named_pwm_2_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_address =
    coupler_to_device_named_pwm_2_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_mask =
    coupler_to_device_named_pwm_2_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_data =
    coupler_to_device_named_pwm_2_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_corrupt =
    coupler_to_device_named_pwm_2_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_pwm_2_control_xing_out_d_ready =
    coupler_to_device_named_pwm_2_auto_control_xing_out_d_ready; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_pwm_1_control_xing_out_a_valid =
    coupler_to_device_named_pwm_1_auto_control_xing_out_a_valid; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_opcode =
    coupler_to_device_named_pwm_1_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_param =
    coupler_to_device_named_pwm_1_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_size =
    coupler_to_device_named_pwm_1_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_source =
    coupler_to_device_named_pwm_1_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_address =
    coupler_to_device_named_pwm_1_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_mask =
    coupler_to_device_named_pwm_1_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_data =
    coupler_to_device_named_pwm_1_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_corrupt =
    coupler_to_device_named_pwm_1_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_pwm_1_control_xing_out_d_ready =
    coupler_to_device_named_pwm_1_auto_control_xing_out_d_ready; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_pwm_0_control_xing_out_a_valid =
    coupler_to_device_named_pwm_0_auto_control_xing_out_a_valid; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_opcode =
    coupler_to_device_named_pwm_0_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_param =
    coupler_to_device_named_pwm_0_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_size =
    coupler_to_device_named_pwm_0_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_source =
    coupler_to_device_named_pwm_0_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_address =
    coupler_to_device_named_pwm_0_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_mask =
    coupler_to_device_named_pwm_0_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_data =
    coupler_to_device_named_pwm_0_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_corrupt =
    coupler_to_device_named_pwm_0_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_pwm_0_control_xing_out_d_ready =
    coupler_to_device_named_pwm_0_auto_control_xing_out_d_ready; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_gpio_0_control_xing_out_a_valid =
    coupler_to_device_named_gpio_0_auto_control_xing_out_a_valid; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_opcode =
    coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_param =
    coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_size =
    coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_source =
    coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_address =
    coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_mask =
    coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_data =
    coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_corrupt =
    coupler_to_device_named_gpio_0_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_gpio_0_control_xing_out_d_ready =
    coupler_to_device_named_gpio_0_auto_control_xing_out_d_ready; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_spi_0_control_xing_out_a_valid =
    coupler_to_device_named_spi_0_auto_control_xing_out_a_valid; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_opcode =
    coupler_to_device_named_spi_0_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_param =
    coupler_to_device_named_spi_0_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_size =
    coupler_to_device_named_spi_0_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_source =
    coupler_to_device_named_spi_0_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_address =
    coupler_to_device_named_spi_0_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_mask =
    coupler_to_device_named_spi_0_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_data =
    coupler_to_device_named_spi_0_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_corrupt =
    coupler_to_device_named_spi_0_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_spi_0_control_xing_out_d_ready =
    coupler_to_device_named_spi_0_auto_control_xing_out_d_ready; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_valid =
    coupler_to_device_named_qspi_ram_0_auto_control_xing_out_a_valid; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_opcode =
    coupler_to_device_named_qspi_ram_0_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_param =
    coupler_to_device_named_qspi_ram_0_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_size =
    coupler_to_device_named_qspi_ram_0_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_source =
    coupler_to_device_named_qspi_ram_0_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_address =
    coupler_to_device_named_qspi_ram_0_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_mask =
    coupler_to_device_named_qspi_ram_0_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_data =
    coupler_to_device_named_qspi_ram_0_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_corrupt =
    coupler_to_device_named_qspi_ram_0_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_ram_0_control_xing_out_d_ready =
    coupler_to_device_named_qspi_ram_0_auto_control_xing_out_d_ready; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_0_mem_xing_out_a_valid =
    coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_valid; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_opcode =
    coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_opcode; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_param =
    coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_param; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_size =
    coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_size; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_source =
    coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_source; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_address =
    coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_address; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_mask =
    coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_mask; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_corrupt =
    coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_0_mem_xing_out_d_ready =
    coupler_to_device_named_qspi_0_1_auto_mem_xing_out_d_ready; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_0_control_xing_out_a_valid =
    coupler_to_device_named_qspi_0_auto_control_xing_out_a_valid; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_opcode =
    coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_param =
    coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_size =
    coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_source =
    coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_address =
    coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_mask =
    coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_data =
    coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_corrupt =
    coupler_to_device_named_qspi_0_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_0_control_xing_out_d_ready =
    coupler_to_device_named_qspi_0_auto_control_xing_out_d_ready; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_4_control_xing_out_a_valid =
    coupler_to_device_named_uart_4_auto_control_xing_out_a_valid; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_opcode =
    coupler_to_device_named_uart_4_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_param =
    coupler_to_device_named_uart_4_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_size =
    coupler_to_device_named_uart_4_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_source =
    coupler_to_device_named_uart_4_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_address =
    coupler_to_device_named_uart_4_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_mask =
    coupler_to_device_named_uart_4_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_data =
    coupler_to_device_named_uart_4_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_corrupt =
    coupler_to_device_named_uart_4_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_4_control_xing_out_d_ready =
    coupler_to_device_named_uart_4_auto_control_xing_out_d_ready; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_3_control_xing_out_a_valid =
    coupler_to_device_named_uart_3_auto_control_xing_out_a_valid; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_opcode =
    coupler_to_device_named_uart_3_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_param =
    coupler_to_device_named_uart_3_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_size =
    coupler_to_device_named_uart_3_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_source =
    coupler_to_device_named_uart_3_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_address =
    coupler_to_device_named_uart_3_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_mask =
    coupler_to_device_named_uart_3_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_data =
    coupler_to_device_named_uart_3_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_corrupt =
    coupler_to_device_named_uart_3_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_3_control_xing_out_d_ready =
    coupler_to_device_named_uart_3_auto_control_xing_out_d_ready; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_2_control_xing_out_a_valid =
    coupler_to_device_named_uart_2_auto_control_xing_out_a_valid; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_opcode =
    coupler_to_device_named_uart_2_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_param =
    coupler_to_device_named_uart_2_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_size =
    coupler_to_device_named_uart_2_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_source =
    coupler_to_device_named_uart_2_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_address =
    coupler_to_device_named_uart_2_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_mask =
    coupler_to_device_named_uart_2_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_data =
    coupler_to_device_named_uart_2_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_corrupt =
    coupler_to_device_named_uart_2_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_2_control_xing_out_d_ready =
    coupler_to_device_named_uart_2_auto_control_xing_out_d_ready; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_1_control_xing_out_a_valid =
    coupler_to_device_named_uart_1_auto_control_xing_out_a_valid; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_opcode =
    coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_param =
    coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_size =
    coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_source =
    coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_address =
    coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_mask =
    coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_data =
    coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_corrupt =
    coupler_to_device_named_uart_1_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_1_control_xing_out_d_ready =
    coupler_to_device_named_uart_1_auto_control_xing_out_d_ready; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_0_control_xing_out_a_valid =
    coupler_to_device_named_uart_0_auto_control_xing_out_a_valid; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode =
    coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_opcode; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param =
    coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_param; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size =
    coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_size; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source =
    coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_source; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address =
    coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_address; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask =
    coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_mask; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data =
    coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_data; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt =
    coupler_to_device_named_uart_0_auto_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_uart_0_control_xing_out_d_ready =
    coupler_to_device_named_uart_0_auto_control_xing_out_d_ready; // @[LazyModule.scala 311:12]
  assign auto_fixedClockNode_out_13_clock = fixedClockNode_auto_out_14_clock; // @[LazyModule.scala 311:12]
  assign auto_fixedClockNode_out_13_reset = fixedClockNode_auto_out_14_reset; // @[LazyModule.scala 311:12]
  assign auto_fixedClockNode_out_12_clock = fixedClockNode_auto_out_13_clock; // @[LazyModule.scala 311:12]
  assign auto_fixedClockNode_out_12_reset = fixedClockNode_auto_out_13_reset; // @[LazyModule.scala 311:12]
  assign auto_fixedClockNode_out_11_clock = fixedClockNode_auto_out_12_clock; // @[LazyModule.scala 311:12]
  assign auto_fixedClockNode_out_11_reset = fixedClockNode_auto_out_12_reset; // @[LazyModule.scala 311:12]
  assign auto_fixedClockNode_out_10_clock = fixedClockNode_auto_out_11_clock; // @[LazyModule.scala 311:12]
  assign auto_fixedClockNode_out_10_reset = fixedClockNode_auto_out_11_reset; // @[LazyModule.scala 311:12]
  assign auto_fixedClockNode_out_9_clock = fixedClockNode_auto_out_10_clock; // @[LazyModule.scala 311:12]
  assign auto_fixedClockNode_out_9_reset = fixedClockNode_auto_out_10_reset; // @[LazyModule.scala 311:12]
  assign auto_fixedClockNode_out_8_clock = fixedClockNode_auto_out_9_clock; // @[LazyModule.scala 311:12]
  assign auto_fixedClockNode_out_8_reset = fixedClockNode_auto_out_9_reset; // @[LazyModule.scala 311:12]
  assign auto_fixedClockNode_out_7_clock = fixedClockNode_auto_out_8_clock; // @[LazyModule.scala 311:12]
  assign auto_fixedClockNode_out_7_reset = fixedClockNode_auto_out_8_reset; // @[LazyModule.scala 311:12]
  assign auto_fixedClockNode_out_6_clock = fixedClockNode_auto_out_7_clock; // @[LazyModule.scala 311:12]
  assign auto_fixedClockNode_out_6_reset = fixedClockNode_auto_out_7_reset; // @[LazyModule.scala 311:12]
  assign auto_fixedClockNode_out_5_clock = fixedClockNode_auto_out_6_clock; // @[LazyModule.scala 311:12]
  assign auto_fixedClockNode_out_5_reset = fixedClockNode_auto_out_6_reset; // @[LazyModule.scala 311:12]
  assign auto_fixedClockNode_out_4_clock = fixedClockNode_auto_out_5_clock; // @[LazyModule.scala 311:12]
  assign auto_fixedClockNode_out_4_reset = fixedClockNode_auto_out_5_reset; // @[LazyModule.scala 311:12]
  assign auto_fixedClockNode_out_3_clock = fixedClockNode_auto_out_4_clock; // @[LazyModule.scala 311:12]
  assign auto_fixedClockNode_out_3_reset = fixedClockNode_auto_out_4_reset; // @[LazyModule.scala 311:12]
  assign auto_fixedClockNode_out_2_clock = fixedClockNode_auto_out_3_clock; // @[LazyModule.scala 311:12]
  assign auto_fixedClockNode_out_2_reset = fixedClockNode_auto_out_3_reset; // @[LazyModule.scala 311:12]
  assign auto_fixedClockNode_out_1_clock = fixedClockNode_auto_out_2_clock; // @[LazyModule.scala 311:12]
  assign auto_fixedClockNode_out_1_reset = fixedClockNode_auto_out_2_reset; // @[LazyModule.scala 311:12]
  assign auto_fixedClockNode_out_0_clock = fixedClockNode_auto_out_1_clock; // @[LazyModule.scala 311:12]
  assign auto_fixedClockNode_out_0_reset = fixedClockNode_auto_out_1_reset; // @[LazyModule.scala 311:12]
  assign auto_bus_xing_in_a_ready = buffer_1_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_bus_xing_in_d_valid = buffer_1_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_bus_xing_in_d_bits_opcode = buffer_1_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_bus_xing_in_d_bits_param = buffer_1_auto_in_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_bus_xing_in_d_bits_size = buffer_1_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_bus_xing_in_d_bits_source = buffer_1_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_bus_xing_in_d_bits_sink = buffer_1_auto_in_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_bus_xing_in_d_bits_denied = buffer_1_auto_in_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_bus_xing_in_d_bits_data = buffer_1_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_bus_xing_in_d_bits_corrupt = buffer_1_auto_in_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign subsystem_pbus_clock_groups_auto_in_member_subsystem_pbus_0_clock =
    auto_subsystem_pbus_clock_groups_in_member_subsystem_pbus_0_clock; // @[LazyModule.scala 309:16]
  assign subsystem_pbus_clock_groups_auto_in_member_subsystem_pbus_0_reset =
    auto_subsystem_pbus_clock_groups_in_member_subsystem_pbus_0_reset; // @[LazyModule.scala 309:16]
  assign clockGroup_auto_in_member_subsystem_pbus_0_clock =
    subsystem_pbus_clock_groups_auto_out_member_subsystem_pbus_0_clock; // @[LazyModule.scala 298:16]
  assign clockGroup_auto_in_member_subsystem_pbus_0_reset =
    subsystem_pbus_clock_groups_auto_out_member_subsystem_pbus_0_reset; // @[LazyModule.scala 298:16]
  assign fixedClockNode_auto_in_clock = clockGroup_auto_out_clock; // @[LazyModule.scala 298:16]
  assign fixedClockNode_auto_in_reset = clockGroup_auto_out_reset; // @[LazyModule.scala 298:16]
  assign fixer_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign fixer_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign fixer_auto_in_a_valid = buffer_auto_out_a_valid; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_param = buffer_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_size = buffer_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_source = buffer_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_address = buffer_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_data = buffer_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_d_ready = buffer_auto_out_d_ready; // @[LazyModule.scala 296:16]
  assign fixer_auto_out_a_ready = out_xbar_auto_in_a_ready; // @[LazyModule.scala 298:16]
  assign fixer_auto_out_d_valid = out_xbar_auto_in_d_valid; // @[LazyModule.scala 298:16]
  assign fixer_auto_out_d_bits_opcode = out_xbar_auto_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign fixer_auto_out_d_bits_size = out_xbar_auto_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign fixer_auto_out_d_bits_source = out_xbar_auto_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign fixer_auto_out_d_bits_data = out_xbar_auto_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign in_xbar_auto_in_a_valid = buffer_1_auto_out_a_valid; // @[LazyModule.scala 296:16]
  assign in_xbar_auto_in_a_bits_opcode = buffer_1_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign in_xbar_auto_in_a_bits_param = buffer_1_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
  assign in_xbar_auto_in_a_bits_size = buffer_1_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign in_xbar_auto_in_a_bits_source = buffer_1_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign in_xbar_auto_in_a_bits_address = buffer_1_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign in_xbar_auto_in_a_bits_mask = buffer_1_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign in_xbar_auto_in_a_bits_data = buffer_1_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign in_xbar_auto_in_a_bits_corrupt = buffer_1_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
  assign in_xbar_auto_in_d_ready = buffer_1_auto_out_d_ready; // @[LazyModule.scala 296:16]
  assign in_xbar_auto_out_a_ready = atomics_auto_in_a_ready; // @[LazyModule.scala 298:16]
  assign in_xbar_auto_out_d_valid = atomics_auto_in_d_valid; // @[LazyModule.scala 298:16]
  assign in_xbar_auto_out_d_bits_opcode = atomics_auto_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign in_xbar_auto_out_d_bits_param = atomics_auto_in_d_bits_param; // @[LazyModule.scala 298:16]
  assign in_xbar_auto_out_d_bits_size = atomics_auto_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign in_xbar_auto_out_d_bits_source = atomics_auto_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign in_xbar_auto_out_d_bits_sink = atomics_auto_in_d_bits_sink; // @[LazyModule.scala 298:16]
  assign in_xbar_auto_out_d_bits_denied = atomics_auto_in_d_bits_denied; // @[LazyModule.scala 298:16]
  assign in_xbar_auto_out_d_bits_data = atomics_auto_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign in_xbar_auto_out_d_bits_corrupt = atomics_auto_in_d_bits_corrupt; // @[LazyModule.scala 298:16]
  assign out_xbar_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign out_xbar_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign out_xbar_auto_in_a_valid = fixer_auto_out_a_valid; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_in_a_bits_opcode = fixer_auto_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_in_a_bits_param = fixer_auto_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_in_a_bits_size = fixer_auto_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_in_a_bits_source = fixer_auto_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_in_a_bits_address = fixer_auto_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_in_a_bits_mask = fixer_auto_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_in_a_bits_data = fixer_auto_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_in_a_bits_corrupt = fixer_auto_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_in_d_ready = fixer_auto_out_d_ready; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_14_a_ready = coupler_to_device_named_i2c_1_auto_tl_in_a_ready; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_14_d_valid = coupler_to_device_named_i2c_1_auto_tl_in_d_valid; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_14_d_bits_opcode = coupler_to_device_named_i2c_1_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_14_d_bits_size = coupler_to_device_named_i2c_1_auto_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_14_d_bits_source = coupler_to_device_named_i2c_1_auto_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_14_d_bits_data = coupler_to_device_named_i2c_1_auto_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_13_a_ready = coupler_to_device_named_i2c_0_auto_tl_in_a_ready; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_13_d_valid = coupler_to_device_named_i2c_0_auto_tl_in_d_valid; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_13_d_bits_opcode = coupler_to_device_named_i2c_0_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_13_d_bits_size = coupler_to_device_named_i2c_0_auto_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_13_d_bits_source = coupler_to_device_named_i2c_0_auto_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_13_d_bits_data = coupler_to_device_named_i2c_0_auto_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_12_a_ready = coupler_to_device_named_pwm_2_auto_tl_in_a_ready; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_12_d_valid = coupler_to_device_named_pwm_2_auto_tl_in_d_valid; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_12_d_bits_opcode = coupler_to_device_named_pwm_2_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_12_d_bits_size = coupler_to_device_named_pwm_2_auto_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_12_d_bits_source = coupler_to_device_named_pwm_2_auto_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_12_d_bits_data = coupler_to_device_named_pwm_2_auto_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_11_a_ready = coupler_to_device_named_pwm_1_auto_tl_in_a_ready; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_11_d_valid = coupler_to_device_named_pwm_1_auto_tl_in_d_valid; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_11_d_bits_opcode = coupler_to_device_named_pwm_1_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_11_d_bits_size = coupler_to_device_named_pwm_1_auto_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_11_d_bits_source = coupler_to_device_named_pwm_1_auto_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_11_d_bits_data = coupler_to_device_named_pwm_1_auto_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_10_a_ready = coupler_to_device_named_pwm_0_auto_tl_in_a_ready; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_10_d_valid = coupler_to_device_named_pwm_0_auto_tl_in_d_valid; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_10_d_bits_opcode = coupler_to_device_named_pwm_0_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_10_d_bits_size = coupler_to_device_named_pwm_0_auto_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_10_d_bits_source = coupler_to_device_named_pwm_0_auto_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_10_d_bits_data = coupler_to_device_named_pwm_0_auto_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_9_a_ready = coupler_to_device_named_gpio_0_auto_tl_in_a_ready; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_9_d_valid = coupler_to_device_named_gpio_0_auto_tl_in_d_valid; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_9_d_bits_opcode = coupler_to_device_named_gpio_0_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_9_d_bits_size = coupler_to_device_named_gpio_0_auto_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_9_d_bits_source = coupler_to_device_named_gpio_0_auto_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_9_d_bits_data = coupler_to_device_named_gpio_0_auto_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_8_a_ready = coupler_to_device_named_spi_0_auto_tl_in_a_ready; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_8_d_valid = coupler_to_device_named_spi_0_auto_tl_in_d_valid; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_8_d_bits_opcode = coupler_to_device_named_spi_0_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_8_d_bits_size = coupler_to_device_named_spi_0_auto_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_8_d_bits_source = coupler_to_device_named_spi_0_auto_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_8_d_bits_data = coupler_to_device_named_spi_0_auto_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_7_a_ready = coupler_to_device_named_qspi_ram_0_auto_tl_in_a_ready; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_7_d_valid = coupler_to_device_named_qspi_ram_0_auto_tl_in_d_valid; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_7_d_bits_opcode = coupler_to_device_named_qspi_ram_0_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_7_d_bits_size = coupler_to_device_named_qspi_ram_0_auto_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_7_d_bits_source = coupler_to_device_named_qspi_ram_0_auto_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_7_d_bits_data = coupler_to_device_named_qspi_ram_0_auto_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_6_a_ready = coupler_to_device_named_qspi_0_1_auto_tl_in_a_ready; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_6_d_valid = coupler_to_device_named_qspi_0_1_auto_tl_in_d_valid; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_6_d_bits_size = coupler_to_device_named_qspi_0_1_auto_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_6_d_bits_source = coupler_to_device_named_qspi_0_1_auto_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_6_d_bits_data = coupler_to_device_named_qspi_0_1_auto_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_5_a_ready = coupler_to_device_named_qspi_0_auto_tl_in_a_ready; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_5_d_valid = coupler_to_device_named_qspi_0_auto_tl_in_d_valid; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_5_d_bits_opcode = coupler_to_device_named_qspi_0_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_5_d_bits_size = coupler_to_device_named_qspi_0_auto_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_5_d_bits_source = coupler_to_device_named_qspi_0_auto_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_5_d_bits_data = coupler_to_device_named_qspi_0_auto_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_4_a_ready = coupler_to_device_named_uart_4_auto_tl_in_a_ready; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_4_d_valid = coupler_to_device_named_uart_4_auto_tl_in_d_valid; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_4_d_bits_opcode = coupler_to_device_named_uart_4_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_4_d_bits_size = coupler_to_device_named_uart_4_auto_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_4_d_bits_source = coupler_to_device_named_uart_4_auto_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_4_d_bits_data = coupler_to_device_named_uart_4_auto_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_3_a_ready = coupler_to_device_named_uart_3_auto_tl_in_a_ready; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_3_d_valid = coupler_to_device_named_uart_3_auto_tl_in_d_valid; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_3_d_bits_opcode = coupler_to_device_named_uart_3_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_3_d_bits_size = coupler_to_device_named_uart_3_auto_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_3_d_bits_source = coupler_to_device_named_uart_3_auto_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_3_d_bits_data = coupler_to_device_named_uart_3_auto_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_2_a_ready = coupler_to_device_named_uart_2_auto_tl_in_a_ready; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_2_d_valid = coupler_to_device_named_uart_2_auto_tl_in_d_valid; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_2_d_bits_opcode = coupler_to_device_named_uart_2_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_2_d_bits_size = coupler_to_device_named_uart_2_auto_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_2_d_bits_source = coupler_to_device_named_uart_2_auto_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_2_d_bits_data = coupler_to_device_named_uart_2_auto_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_1_a_ready = coupler_to_device_named_uart_1_auto_tl_in_a_ready; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_1_d_valid = coupler_to_device_named_uart_1_auto_tl_in_d_valid; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_1_d_bits_opcode = coupler_to_device_named_uart_1_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_1_d_bits_size = coupler_to_device_named_uart_1_auto_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_1_d_bits_source = coupler_to_device_named_uart_1_auto_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_1_d_bits_data = coupler_to_device_named_uart_1_auto_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_0_a_ready = coupler_to_device_named_uart_0_auto_tl_in_a_ready; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_0_d_valid = coupler_to_device_named_uart_0_auto_tl_in_d_valid; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_0_d_bits_opcode = coupler_to_device_named_uart_0_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_0_d_bits_size = coupler_to_device_named_uart_0_auto_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_0_d_bits_source = coupler_to_device_named_uart_0_auto_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_0_d_bits_data = coupler_to_device_named_uart_0_auto_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign buffer_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_in_a_valid = atomics_auto_out_a_valid; // @[LazyModule.scala 296:16]
  assign buffer_auto_in_a_bits_opcode = atomics_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign buffer_auto_in_a_bits_param = atomics_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
  assign buffer_auto_in_a_bits_size = atomics_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign buffer_auto_in_a_bits_source = atomics_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign buffer_auto_in_a_bits_address = atomics_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign buffer_auto_in_a_bits_mask = atomics_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign buffer_auto_in_a_bits_data = atomics_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign buffer_auto_in_a_bits_corrupt = atomics_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
  assign buffer_auto_in_d_ready = atomics_auto_out_d_ready; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_a_ready = fixer_auto_in_a_ready; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_valid = fixer_auto_in_d_valid; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_opcode = fixer_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_size = fixer_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_source = fixer_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_data = fixer_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
  assign atomics_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign atomics_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign atomics_auto_in_a_valid = in_xbar_auto_out_a_valid; // @[LazyModule.scala 298:16]
  assign atomics_auto_in_a_bits_opcode = in_xbar_auto_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign atomics_auto_in_a_bits_param = in_xbar_auto_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign atomics_auto_in_a_bits_size = in_xbar_auto_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign atomics_auto_in_a_bits_source = in_xbar_auto_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign atomics_auto_in_a_bits_address = in_xbar_auto_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign atomics_auto_in_a_bits_mask = in_xbar_auto_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign atomics_auto_in_a_bits_data = in_xbar_auto_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign atomics_auto_in_a_bits_corrupt = in_xbar_auto_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign atomics_auto_in_d_ready = in_xbar_auto_out_d_ready; // @[LazyModule.scala 298:16]
  assign atomics_auto_out_a_ready = buffer_auto_in_a_ready; // @[LazyModule.scala 296:16]
  assign atomics_auto_out_d_valid = buffer_auto_in_d_valid; // @[LazyModule.scala 296:16]
  assign atomics_auto_out_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign atomics_auto_out_d_bits_param = buffer_auto_in_d_bits_param; // @[LazyModule.scala 296:16]
  assign atomics_auto_out_d_bits_size = buffer_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
  assign atomics_auto_out_d_bits_source = buffer_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
  assign atomics_auto_out_d_bits_sink = buffer_auto_in_d_bits_sink; // @[LazyModule.scala 296:16]
  assign atomics_auto_out_d_bits_denied = buffer_auto_in_d_bits_denied; // @[LazyModule.scala 296:16]
  assign atomics_auto_out_d_bits_data = buffer_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
  assign atomics_auto_out_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[LazyModule.scala 296:16]
  assign buffer_1_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_1_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_1_auto_in_a_valid = auto_bus_xing_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_in_a_bits_opcode = auto_bus_xing_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_in_a_bits_param = auto_bus_xing_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_in_a_bits_size = auto_bus_xing_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_in_a_bits_source = auto_bus_xing_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_in_a_bits_address = auto_bus_xing_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_in_a_bits_mask = auto_bus_xing_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_in_a_bits_data = auto_bus_xing_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_in_a_bits_corrupt = auto_bus_xing_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_in_d_ready = auto_bus_xing_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_out_a_ready = in_xbar_auto_in_a_ready; // @[LazyModule.scala 296:16]
  assign buffer_1_auto_out_d_valid = in_xbar_auto_in_d_valid; // @[LazyModule.scala 296:16]
  assign buffer_1_auto_out_d_bits_opcode = in_xbar_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign buffer_1_auto_out_d_bits_param = in_xbar_auto_in_d_bits_param; // @[LazyModule.scala 296:16]
  assign buffer_1_auto_out_d_bits_size = in_xbar_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
  assign buffer_1_auto_out_d_bits_source = in_xbar_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
  assign buffer_1_auto_out_d_bits_sink = in_xbar_auto_in_d_bits_sink; // @[LazyModule.scala 296:16]
  assign buffer_1_auto_out_d_bits_denied = in_xbar_auto_in_d_bits_denied; // @[LazyModule.scala 296:16]
  assign buffer_1_auto_out_d_bits_data = in_xbar_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
  assign buffer_1_auto_out_d_bits_corrupt = in_xbar_auto_in_d_bits_corrupt; // @[LazyModule.scala 296:16]
  assign coupler_to_device_named_uart_0_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_device_named_uart_0_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_device_named_uart_0_auto_control_xing_out_a_ready =
    auto_coupler_to_device_named_uart_0_control_xing_out_a_ready; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_uart_0_auto_control_xing_out_d_valid =
    auto_coupler_to_device_named_uart_0_control_xing_out_d_valid; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_uart_0_auto_control_xing_out_d_bits_opcode =
    auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_uart_0_auto_control_xing_out_d_bits_size =
    auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_uart_0_auto_control_xing_out_d_bits_source =
    auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_uart_0_auto_control_xing_out_d_bits_data =
    auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_uart_0_auto_tl_in_a_valid = out_xbar_auto_out_0_a_valid; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_0_auto_tl_in_a_bits_opcode = out_xbar_auto_out_0_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_0_auto_tl_in_a_bits_param = out_xbar_auto_out_0_a_bits_param; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_0_auto_tl_in_a_bits_size = out_xbar_auto_out_0_a_bits_size; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_0_auto_tl_in_a_bits_source = out_xbar_auto_out_0_a_bits_source; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_0_auto_tl_in_a_bits_address = out_xbar_auto_out_0_a_bits_address; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_0_auto_tl_in_a_bits_mask = out_xbar_auto_out_0_a_bits_mask; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_0_auto_tl_in_a_bits_data = out_xbar_auto_out_0_a_bits_data; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_0_auto_tl_in_a_bits_corrupt = out_xbar_auto_out_0_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_0_auto_tl_in_d_ready = out_xbar_auto_out_0_d_ready; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_1_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_device_named_uart_1_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_device_named_uart_1_auto_control_xing_out_a_ready =
    auto_coupler_to_device_named_uart_1_control_xing_out_a_ready; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_uart_1_auto_control_xing_out_d_valid =
    auto_coupler_to_device_named_uart_1_control_xing_out_d_valid; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_uart_1_auto_control_xing_out_d_bits_opcode =
    auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_opcode; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_uart_1_auto_control_xing_out_d_bits_size =
    auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_size; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_uart_1_auto_control_xing_out_d_bits_source =
    auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_source; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_uart_1_auto_control_xing_out_d_bits_data =
    auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_data; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_uart_1_auto_tl_in_a_valid = out_xbar_auto_out_1_a_valid; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_1_auto_tl_in_a_bits_opcode = out_xbar_auto_out_1_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_1_auto_tl_in_a_bits_param = out_xbar_auto_out_1_a_bits_param; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_1_auto_tl_in_a_bits_size = out_xbar_auto_out_1_a_bits_size; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_1_auto_tl_in_a_bits_source = out_xbar_auto_out_1_a_bits_source; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_1_auto_tl_in_a_bits_address = out_xbar_auto_out_1_a_bits_address; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_1_auto_tl_in_a_bits_mask = out_xbar_auto_out_1_a_bits_mask; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_1_auto_tl_in_a_bits_data = out_xbar_auto_out_1_a_bits_data; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_1_auto_tl_in_a_bits_corrupt = out_xbar_auto_out_1_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_1_auto_tl_in_d_ready = out_xbar_auto_out_1_d_ready; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_2_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_device_named_uart_2_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_device_named_uart_2_auto_control_xing_out_a_ready =
    auto_coupler_to_device_named_uart_2_control_xing_out_a_ready; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_uart_2_auto_control_xing_out_d_valid =
    auto_coupler_to_device_named_uart_2_control_xing_out_d_valid; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_uart_2_auto_control_xing_out_d_bits_opcode =
    auto_coupler_to_device_named_uart_2_control_xing_out_d_bits_opcode; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_uart_2_auto_control_xing_out_d_bits_size =
    auto_coupler_to_device_named_uart_2_control_xing_out_d_bits_size; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_uart_2_auto_control_xing_out_d_bits_source =
    auto_coupler_to_device_named_uart_2_control_xing_out_d_bits_source; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_uart_2_auto_control_xing_out_d_bits_data =
    auto_coupler_to_device_named_uart_2_control_xing_out_d_bits_data; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_uart_2_auto_tl_in_a_valid = out_xbar_auto_out_2_a_valid; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_2_auto_tl_in_a_bits_opcode = out_xbar_auto_out_2_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_2_auto_tl_in_a_bits_param = out_xbar_auto_out_2_a_bits_param; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_2_auto_tl_in_a_bits_size = out_xbar_auto_out_2_a_bits_size; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_2_auto_tl_in_a_bits_source = out_xbar_auto_out_2_a_bits_source; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_2_auto_tl_in_a_bits_address = out_xbar_auto_out_2_a_bits_address; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_2_auto_tl_in_a_bits_mask = out_xbar_auto_out_2_a_bits_mask; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_2_auto_tl_in_a_bits_data = out_xbar_auto_out_2_a_bits_data; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_2_auto_tl_in_a_bits_corrupt = out_xbar_auto_out_2_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_2_auto_tl_in_d_ready = out_xbar_auto_out_2_d_ready; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_3_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_device_named_uart_3_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_device_named_uart_3_auto_control_xing_out_a_ready =
    auto_coupler_to_device_named_uart_3_control_xing_out_a_ready; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_uart_3_auto_control_xing_out_d_valid =
    auto_coupler_to_device_named_uart_3_control_xing_out_d_valid; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_uart_3_auto_control_xing_out_d_bits_opcode =
    auto_coupler_to_device_named_uart_3_control_xing_out_d_bits_opcode; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_uart_3_auto_control_xing_out_d_bits_size =
    auto_coupler_to_device_named_uart_3_control_xing_out_d_bits_size; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_uart_3_auto_control_xing_out_d_bits_source =
    auto_coupler_to_device_named_uart_3_control_xing_out_d_bits_source; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_uart_3_auto_control_xing_out_d_bits_data =
    auto_coupler_to_device_named_uart_3_control_xing_out_d_bits_data; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_uart_3_auto_tl_in_a_valid = out_xbar_auto_out_3_a_valid; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_3_auto_tl_in_a_bits_opcode = out_xbar_auto_out_3_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_3_auto_tl_in_a_bits_param = out_xbar_auto_out_3_a_bits_param; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_3_auto_tl_in_a_bits_size = out_xbar_auto_out_3_a_bits_size; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_3_auto_tl_in_a_bits_source = out_xbar_auto_out_3_a_bits_source; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_3_auto_tl_in_a_bits_address = out_xbar_auto_out_3_a_bits_address; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_3_auto_tl_in_a_bits_mask = out_xbar_auto_out_3_a_bits_mask; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_3_auto_tl_in_a_bits_data = out_xbar_auto_out_3_a_bits_data; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_3_auto_tl_in_a_bits_corrupt = out_xbar_auto_out_3_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_3_auto_tl_in_d_ready = out_xbar_auto_out_3_d_ready; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_4_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_device_named_uart_4_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_device_named_uart_4_auto_control_xing_out_a_ready =
    auto_coupler_to_device_named_uart_4_control_xing_out_a_ready; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_uart_4_auto_control_xing_out_d_valid =
    auto_coupler_to_device_named_uart_4_control_xing_out_d_valid; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_uart_4_auto_control_xing_out_d_bits_opcode =
    auto_coupler_to_device_named_uart_4_control_xing_out_d_bits_opcode; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_uart_4_auto_control_xing_out_d_bits_size =
    auto_coupler_to_device_named_uart_4_control_xing_out_d_bits_size; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_uart_4_auto_control_xing_out_d_bits_source =
    auto_coupler_to_device_named_uart_4_control_xing_out_d_bits_source; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_uart_4_auto_control_xing_out_d_bits_data =
    auto_coupler_to_device_named_uart_4_control_xing_out_d_bits_data; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_uart_4_auto_tl_in_a_valid = out_xbar_auto_out_4_a_valid; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_4_auto_tl_in_a_bits_opcode = out_xbar_auto_out_4_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_4_auto_tl_in_a_bits_param = out_xbar_auto_out_4_a_bits_param; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_4_auto_tl_in_a_bits_size = out_xbar_auto_out_4_a_bits_size; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_4_auto_tl_in_a_bits_source = out_xbar_auto_out_4_a_bits_source; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_4_auto_tl_in_a_bits_address = out_xbar_auto_out_4_a_bits_address; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_4_auto_tl_in_a_bits_mask = out_xbar_auto_out_4_a_bits_mask; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_4_auto_tl_in_a_bits_data = out_xbar_auto_out_4_a_bits_data; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_4_auto_tl_in_a_bits_corrupt = out_xbar_auto_out_4_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_uart_4_auto_tl_in_d_ready = out_xbar_auto_out_4_d_ready; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_0_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_device_named_qspi_0_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_device_named_qspi_0_auto_control_xing_out_a_ready =
    auto_coupler_to_device_named_qspi_0_control_xing_out_a_ready; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_qspi_0_auto_control_xing_out_d_valid =
    auto_coupler_to_device_named_qspi_0_control_xing_out_d_valid; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_qspi_0_auto_control_xing_out_d_bits_opcode =
    auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_opcode; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_qspi_0_auto_control_xing_out_d_bits_size =
    auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_size; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_qspi_0_auto_control_xing_out_d_bits_source =
    auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_source; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_qspi_0_auto_control_xing_out_d_bits_data =
    auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_data; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_qspi_0_auto_tl_in_a_valid = out_xbar_auto_out_5_a_valid; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_0_auto_tl_in_a_bits_opcode = out_xbar_auto_out_5_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_0_auto_tl_in_a_bits_param = out_xbar_auto_out_5_a_bits_param; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_0_auto_tl_in_a_bits_size = out_xbar_auto_out_5_a_bits_size; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_0_auto_tl_in_a_bits_source = out_xbar_auto_out_5_a_bits_source; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_0_auto_tl_in_a_bits_address = out_xbar_auto_out_5_a_bits_address; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_0_auto_tl_in_a_bits_mask = out_xbar_auto_out_5_a_bits_mask; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_0_auto_tl_in_a_bits_data = out_xbar_auto_out_5_a_bits_data; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_0_auto_tl_in_a_bits_corrupt = out_xbar_auto_out_5_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_0_auto_tl_in_d_ready = out_xbar_auto_out_5_d_ready; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_0_1_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_device_named_qspi_0_1_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_device_named_qspi_0_1_auto_mem_xing_out_a_ready =
    auto_coupler_to_device_named_qspi_0_mem_xing_out_a_ready; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_qspi_0_1_auto_mem_xing_out_d_valid =
    auto_coupler_to_device_named_qspi_0_mem_xing_out_d_valid; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_qspi_0_1_auto_mem_xing_out_d_bits_size =
    auto_coupler_to_device_named_qspi_0_mem_xing_out_d_bits_size; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_qspi_0_1_auto_mem_xing_out_d_bits_source =
    auto_coupler_to_device_named_qspi_0_mem_xing_out_d_bits_source; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_qspi_0_1_auto_mem_xing_out_d_bits_data =
    auto_coupler_to_device_named_qspi_0_mem_xing_out_d_bits_data; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_qspi_0_1_auto_tl_in_a_valid = out_xbar_auto_out_6_a_valid; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_opcode = out_xbar_auto_out_6_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_param = out_xbar_auto_out_6_a_bits_param; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_size = out_xbar_auto_out_6_a_bits_size; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_source = out_xbar_auto_out_6_a_bits_source; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_address = out_xbar_auto_out_6_a_bits_address; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_mask = out_xbar_auto_out_6_a_bits_mask; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_0_1_auto_tl_in_a_bits_corrupt = out_xbar_auto_out_6_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_0_1_auto_tl_in_d_ready = out_xbar_auto_out_6_d_ready; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_ram_0_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_device_named_qspi_ram_0_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_device_named_qspi_ram_0_auto_control_xing_out_a_ready =
    auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_ready; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_qspi_ram_0_auto_control_xing_out_d_valid =
    auto_coupler_to_device_named_qspi_ram_0_control_xing_out_d_valid; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_qspi_ram_0_auto_control_xing_out_d_bits_opcode =
    auto_coupler_to_device_named_qspi_ram_0_control_xing_out_d_bits_opcode; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_qspi_ram_0_auto_control_xing_out_d_bits_size =
    auto_coupler_to_device_named_qspi_ram_0_control_xing_out_d_bits_size; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_qspi_ram_0_auto_control_xing_out_d_bits_source =
    auto_coupler_to_device_named_qspi_ram_0_control_xing_out_d_bits_source; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_qspi_ram_0_auto_control_xing_out_d_bits_data =
    auto_coupler_to_device_named_qspi_ram_0_control_xing_out_d_bits_data; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_qspi_ram_0_auto_tl_in_a_valid = out_xbar_auto_out_7_a_valid; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_opcode = out_xbar_auto_out_7_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_param = out_xbar_auto_out_7_a_bits_param; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_size = out_xbar_auto_out_7_a_bits_size; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_source = out_xbar_auto_out_7_a_bits_source; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_address = out_xbar_auto_out_7_a_bits_address; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_mask = out_xbar_auto_out_7_a_bits_mask; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_data = out_xbar_auto_out_7_a_bits_data; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_corrupt = out_xbar_auto_out_7_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_ram_0_auto_tl_in_d_ready = out_xbar_auto_out_7_d_ready; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_spi_0_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_device_named_spi_0_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_device_named_spi_0_auto_control_xing_out_a_ready =
    auto_coupler_to_device_named_spi_0_control_xing_out_a_ready; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_spi_0_auto_control_xing_out_d_valid =
    auto_coupler_to_device_named_spi_0_control_xing_out_d_valid; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_spi_0_auto_control_xing_out_d_bits_opcode =
    auto_coupler_to_device_named_spi_0_control_xing_out_d_bits_opcode; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_spi_0_auto_control_xing_out_d_bits_size =
    auto_coupler_to_device_named_spi_0_control_xing_out_d_bits_size; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_spi_0_auto_control_xing_out_d_bits_source =
    auto_coupler_to_device_named_spi_0_control_xing_out_d_bits_source; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_spi_0_auto_control_xing_out_d_bits_data =
    auto_coupler_to_device_named_spi_0_control_xing_out_d_bits_data; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_spi_0_auto_tl_in_a_valid = out_xbar_auto_out_8_a_valid; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_spi_0_auto_tl_in_a_bits_opcode = out_xbar_auto_out_8_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_spi_0_auto_tl_in_a_bits_param = out_xbar_auto_out_8_a_bits_param; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_spi_0_auto_tl_in_a_bits_size = out_xbar_auto_out_8_a_bits_size; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_spi_0_auto_tl_in_a_bits_source = out_xbar_auto_out_8_a_bits_source; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_spi_0_auto_tl_in_a_bits_address = out_xbar_auto_out_8_a_bits_address; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_spi_0_auto_tl_in_a_bits_mask = out_xbar_auto_out_8_a_bits_mask; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_spi_0_auto_tl_in_a_bits_data = out_xbar_auto_out_8_a_bits_data; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_spi_0_auto_tl_in_a_bits_corrupt = out_xbar_auto_out_8_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_spi_0_auto_tl_in_d_ready = out_xbar_auto_out_8_d_ready; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_gpio_0_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_device_named_gpio_0_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_device_named_gpio_0_auto_control_xing_out_a_ready =
    auto_coupler_to_device_named_gpio_0_control_xing_out_a_ready; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_gpio_0_auto_control_xing_out_d_valid =
    auto_coupler_to_device_named_gpio_0_control_xing_out_d_valid; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_gpio_0_auto_control_xing_out_d_bits_opcode =
    auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_opcode; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_gpio_0_auto_control_xing_out_d_bits_size =
    auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_size; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_gpio_0_auto_control_xing_out_d_bits_source =
    auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_source; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_gpio_0_auto_control_xing_out_d_bits_data =
    auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_data; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_gpio_0_auto_tl_in_a_valid = out_xbar_auto_out_9_a_valid; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_gpio_0_auto_tl_in_a_bits_opcode = out_xbar_auto_out_9_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_gpio_0_auto_tl_in_a_bits_param = out_xbar_auto_out_9_a_bits_param; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_gpio_0_auto_tl_in_a_bits_size = out_xbar_auto_out_9_a_bits_size; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_gpio_0_auto_tl_in_a_bits_source = out_xbar_auto_out_9_a_bits_source; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_gpio_0_auto_tl_in_a_bits_address = out_xbar_auto_out_9_a_bits_address; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_gpio_0_auto_tl_in_a_bits_mask = out_xbar_auto_out_9_a_bits_mask; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_gpio_0_auto_tl_in_a_bits_data = out_xbar_auto_out_9_a_bits_data; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_gpio_0_auto_tl_in_a_bits_corrupt = out_xbar_auto_out_9_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_gpio_0_auto_tl_in_d_ready = out_xbar_auto_out_9_d_ready; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_pwm_0_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_device_named_pwm_0_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_device_named_pwm_0_auto_control_xing_out_a_ready =
    auto_coupler_to_device_named_pwm_0_control_xing_out_a_ready; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_pwm_0_auto_control_xing_out_d_valid =
    auto_coupler_to_device_named_pwm_0_control_xing_out_d_valid; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_pwm_0_auto_control_xing_out_d_bits_opcode =
    auto_coupler_to_device_named_pwm_0_control_xing_out_d_bits_opcode; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_pwm_0_auto_control_xing_out_d_bits_size =
    auto_coupler_to_device_named_pwm_0_control_xing_out_d_bits_size; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_pwm_0_auto_control_xing_out_d_bits_source =
    auto_coupler_to_device_named_pwm_0_control_xing_out_d_bits_source; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_pwm_0_auto_control_xing_out_d_bits_data =
    auto_coupler_to_device_named_pwm_0_control_xing_out_d_bits_data; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_pwm_0_auto_tl_in_a_valid = out_xbar_auto_out_10_a_valid; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_pwm_0_auto_tl_in_a_bits_opcode = out_xbar_auto_out_10_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_pwm_0_auto_tl_in_a_bits_param = out_xbar_auto_out_10_a_bits_param; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_pwm_0_auto_tl_in_a_bits_size = out_xbar_auto_out_10_a_bits_size; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_pwm_0_auto_tl_in_a_bits_source = out_xbar_auto_out_10_a_bits_source; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_pwm_0_auto_tl_in_a_bits_address = out_xbar_auto_out_10_a_bits_address; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_pwm_0_auto_tl_in_a_bits_mask = out_xbar_auto_out_10_a_bits_mask; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_pwm_0_auto_tl_in_a_bits_data = out_xbar_auto_out_10_a_bits_data; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_pwm_0_auto_tl_in_a_bits_corrupt = out_xbar_auto_out_10_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_pwm_0_auto_tl_in_d_ready = out_xbar_auto_out_10_d_ready; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_pwm_1_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_device_named_pwm_1_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_device_named_pwm_1_auto_control_xing_out_a_ready =
    auto_coupler_to_device_named_pwm_1_control_xing_out_a_ready; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_pwm_1_auto_control_xing_out_d_valid =
    auto_coupler_to_device_named_pwm_1_control_xing_out_d_valid; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_pwm_1_auto_control_xing_out_d_bits_opcode =
    auto_coupler_to_device_named_pwm_1_control_xing_out_d_bits_opcode; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_pwm_1_auto_control_xing_out_d_bits_size =
    auto_coupler_to_device_named_pwm_1_control_xing_out_d_bits_size; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_pwm_1_auto_control_xing_out_d_bits_source =
    auto_coupler_to_device_named_pwm_1_control_xing_out_d_bits_source; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_pwm_1_auto_control_xing_out_d_bits_data =
    auto_coupler_to_device_named_pwm_1_control_xing_out_d_bits_data; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_pwm_1_auto_tl_in_a_valid = out_xbar_auto_out_11_a_valid; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_pwm_1_auto_tl_in_a_bits_opcode = out_xbar_auto_out_11_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_pwm_1_auto_tl_in_a_bits_param = out_xbar_auto_out_11_a_bits_param; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_pwm_1_auto_tl_in_a_bits_size = out_xbar_auto_out_11_a_bits_size; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_pwm_1_auto_tl_in_a_bits_source = out_xbar_auto_out_11_a_bits_source; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_pwm_1_auto_tl_in_a_bits_address = out_xbar_auto_out_11_a_bits_address; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_pwm_1_auto_tl_in_a_bits_mask = out_xbar_auto_out_11_a_bits_mask; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_pwm_1_auto_tl_in_a_bits_data = out_xbar_auto_out_11_a_bits_data; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_pwm_1_auto_tl_in_a_bits_corrupt = out_xbar_auto_out_11_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_pwm_1_auto_tl_in_d_ready = out_xbar_auto_out_11_d_ready; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_pwm_2_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_device_named_pwm_2_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_device_named_pwm_2_auto_control_xing_out_a_ready =
    auto_coupler_to_device_named_pwm_2_control_xing_out_a_ready; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_pwm_2_auto_control_xing_out_d_valid =
    auto_coupler_to_device_named_pwm_2_control_xing_out_d_valid; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_pwm_2_auto_control_xing_out_d_bits_opcode =
    auto_coupler_to_device_named_pwm_2_control_xing_out_d_bits_opcode; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_pwm_2_auto_control_xing_out_d_bits_size =
    auto_coupler_to_device_named_pwm_2_control_xing_out_d_bits_size; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_pwm_2_auto_control_xing_out_d_bits_source =
    auto_coupler_to_device_named_pwm_2_control_xing_out_d_bits_source; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_pwm_2_auto_control_xing_out_d_bits_data =
    auto_coupler_to_device_named_pwm_2_control_xing_out_d_bits_data; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_pwm_2_auto_tl_in_a_valid = out_xbar_auto_out_12_a_valid; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_pwm_2_auto_tl_in_a_bits_opcode = out_xbar_auto_out_12_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_pwm_2_auto_tl_in_a_bits_param = out_xbar_auto_out_12_a_bits_param; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_pwm_2_auto_tl_in_a_bits_size = out_xbar_auto_out_12_a_bits_size; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_pwm_2_auto_tl_in_a_bits_source = out_xbar_auto_out_12_a_bits_source; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_pwm_2_auto_tl_in_a_bits_address = out_xbar_auto_out_12_a_bits_address; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_pwm_2_auto_tl_in_a_bits_mask = out_xbar_auto_out_12_a_bits_mask; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_pwm_2_auto_tl_in_a_bits_data = out_xbar_auto_out_12_a_bits_data; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_pwm_2_auto_tl_in_a_bits_corrupt = out_xbar_auto_out_12_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_pwm_2_auto_tl_in_d_ready = out_xbar_auto_out_12_d_ready; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_i2c_0_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_device_named_i2c_0_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_device_named_i2c_0_auto_control_xing_out_a_ready =
    auto_coupler_to_device_named_i2c_0_control_xing_out_a_ready; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_i2c_0_auto_control_xing_out_d_valid =
    auto_coupler_to_device_named_i2c_0_control_xing_out_d_valid; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_i2c_0_auto_control_xing_out_d_bits_opcode =
    auto_coupler_to_device_named_i2c_0_control_xing_out_d_bits_opcode; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_i2c_0_auto_control_xing_out_d_bits_size =
    auto_coupler_to_device_named_i2c_0_control_xing_out_d_bits_size; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_i2c_0_auto_control_xing_out_d_bits_source =
    auto_coupler_to_device_named_i2c_0_control_xing_out_d_bits_source; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_i2c_0_auto_control_xing_out_d_bits_data =
    auto_coupler_to_device_named_i2c_0_control_xing_out_d_bits_data; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_i2c_0_auto_tl_in_a_valid = out_xbar_auto_out_13_a_valid; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_i2c_0_auto_tl_in_a_bits_opcode = out_xbar_auto_out_13_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_i2c_0_auto_tl_in_a_bits_param = out_xbar_auto_out_13_a_bits_param; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_i2c_0_auto_tl_in_a_bits_size = out_xbar_auto_out_13_a_bits_size; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_i2c_0_auto_tl_in_a_bits_source = out_xbar_auto_out_13_a_bits_source; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_i2c_0_auto_tl_in_a_bits_address = out_xbar_auto_out_13_a_bits_address; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_i2c_0_auto_tl_in_a_bits_mask = out_xbar_auto_out_13_a_bits_mask; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_i2c_0_auto_tl_in_a_bits_data = out_xbar_auto_out_13_a_bits_data; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_i2c_0_auto_tl_in_a_bits_corrupt = out_xbar_auto_out_13_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_i2c_0_auto_tl_in_d_ready = out_xbar_auto_out_13_d_ready; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_i2c_1_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_device_named_i2c_1_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_device_named_i2c_1_auto_control_xing_out_a_ready =
    auto_coupler_to_device_named_i2c_1_control_xing_out_a_ready; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_i2c_1_auto_control_xing_out_d_valid =
    auto_coupler_to_device_named_i2c_1_control_xing_out_d_valid; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_i2c_1_auto_control_xing_out_d_bits_opcode =
    auto_coupler_to_device_named_i2c_1_control_xing_out_d_bits_opcode; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_i2c_1_auto_control_xing_out_d_bits_size =
    auto_coupler_to_device_named_i2c_1_control_xing_out_d_bits_size; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_i2c_1_auto_control_xing_out_d_bits_source =
    auto_coupler_to_device_named_i2c_1_control_xing_out_d_bits_source; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_i2c_1_auto_control_xing_out_d_bits_data =
    auto_coupler_to_device_named_i2c_1_control_xing_out_d_bits_data; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_i2c_1_auto_tl_in_a_valid = out_xbar_auto_out_14_a_valid; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_i2c_1_auto_tl_in_a_bits_opcode = out_xbar_auto_out_14_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_i2c_1_auto_tl_in_a_bits_param = out_xbar_auto_out_14_a_bits_param; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_i2c_1_auto_tl_in_a_bits_size = out_xbar_auto_out_14_a_bits_size; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_i2c_1_auto_tl_in_a_bits_source = out_xbar_auto_out_14_a_bits_source; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_i2c_1_auto_tl_in_a_bits_address = out_xbar_auto_out_14_a_bits_address; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_i2c_1_auto_tl_in_a_bits_mask = out_xbar_auto_out_14_a_bits_mask; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_i2c_1_auto_tl_in_a_bits_data = out_xbar_auto_out_14_a_bits_data; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_i2c_1_auto_tl_in_a_bits_corrupt = out_xbar_auto_out_14_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_i2c_1_auto_tl_in_d_ready = out_xbar_auto_out_14_d_ready; // @[LazyModule.scala 298:16]
endmodule
module ClockGroupAggregator_2(
  input   auto_in_member_subsystem_fbus_0_clock,
  input   auto_in_member_subsystem_fbus_0_reset,
  output  auto_out_member_subsystem_fbus_0_clock,
  output  auto_out_member_subsystem_fbus_0_reset
);
  assign auto_out_member_subsystem_fbus_0_clock = auto_in_member_subsystem_fbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_member_subsystem_fbus_0_reset = auto_in_member_subsystem_fbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module ClockGroup_2(
  input   auto_in_member_subsystem_fbus_0_clock,
  input   auto_in_member_subsystem_fbus_0_reset,
  output  auto_out_clock,
  output  auto_out_reset
);
  assign auto_out_clock = auto_in_member_subsystem_fbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_reset = auto_in_member_subsystem_fbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module FixedClockBroadcast_2(
  input   auto_in_clock,
  input   auto_in_reset,
  output  auto_out_clock,
  output  auto_out_reset
);
  assign auto_out_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module FrontBus(
  input   auto_subsystem_fbus_clock_groups_in_member_subsystem_fbus_0_clock,
  input   auto_subsystem_fbus_clock_groups_in_member_subsystem_fbus_0_reset
);
  wire  subsystem_fbus_clock_groups_auto_in_member_subsystem_fbus_0_clock; // @[BusWrapper.scala 40:48]
  wire  subsystem_fbus_clock_groups_auto_in_member_subsystem_fbus_0_reset; // @[BusWrapper.scala 40:48]
  wire  subsystem_fbus_clock_groups_auto_out_member_subsystem_fbus_0_clock; // @[BusWrapper.scala 40:48]
  wire  subsystem_fbus_clock_groups_auto_out_member_subsystem_fbus_0_reset; // @[BusWrapper.scala 40:48]
  wire  clockGroup_auto_in_member_subsystem_fbus_0_clock; // @[BusWrapper.scala 41:38]
  wire  clockGroup_auto_in_member_subsystem_fbus_0_reset; // @[BusWrapper.scala 41:38]
  wire  clockGroup_auto_out_clock; // @[BusWrapper.scala 41:38]
  wire  clockGroup_auto_out_reset; // @[BusWrapper.scala 41:38]
  wire  fixedClockNode_auto_in_clock; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_in_reset; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_clock; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_reset; // @[ClockGroup.scala 106:107]
  ClockGroupAggregator_2 subsystem_fbus_clock_groups ( // @[BusWrapper.scala 40:48]
    .auto_in_member_subsystem_fbus_0_clock(subsystem_fbus_clock_groups_auto_in_member_subsystem_fbus_0_clock),
    .auto_in_member_subsystem_fbus_0_reset(subsystem_fbus_clock_groups_auto_in_member_subsystem_fbus_0_reset),
    .auto_out_member_subsystem_fbus_0_clock(subsystem_fbus_clock_groups_auto_out_member_subsystem_fbus_0_clock),
    .auto_out_member_subsystem_fbus_0_reset(subsystem_fbus_clock_groups_auto_out_member_subsystem_fbus_0_reset)
  );
  ClockGroup_2 clockGroup ( // @[BusWrapper.scala 41:38]
    .auto_in_member_subsystem_fbus_0_clock(clockGroup_auto_in_member_subsystem_fbus_0_clock),
    .auto_in_member_subsystem_fbus_0_reset(clockGroup_auto_in_member_subsystem_fbus_0_reset),
    .auto_out_clock(clockGroup_auto_out_clock),
    .auto_out_reset(clockGroup_auto_out_reset)
  );
  FixedClockBroadcast_2 fixedClockNode ( // @[ClockGroup.scala 106:107]
    .auto_in_clock(fixedClockNode_auto_in_clock),
    .auto_in_reset(fixedClockNode_auto_in_reset),
    .auto_out_clock(fixedClockNode_auto_out_clock),
    .auto_out_reset(fixedClockNode_auto_out_reset)
  );
  assign subsystem_fbus_clock_groups_auto_in_member_subsystem_fbus_0_clock =
    auto_subsystem_fbus_clock_groups_in_member_subsystem_fbus_0_clock; // @[LazyModule.scala 309:16]
  assign subsystem_fbus_clock_groups_auto_in_member_subsystem_fbus_0_reset =
    auto_subsystem_fbus_clock_groups_in_member_subsystem_fbus_0_reset; // @[LazyModule.scala 309:16]
  assign clockGroup_auto_in_member_subsystem_fbus_0_clock =
    subsystem_fbus_clock_groups_auto_out_member_subsystem_fbus_0_clock; // @[LazyModule.scala 298:16]
  assign clockGroup_auto_in_member_subsystem_fbus_0_reset =
    subsystem_fbus_clock_groups_auto_out_member_subsystem_fbus_0_reset; // @[LazyModule.scala 298:16]
  assign fixedClockNode_auto_in_clock = clockGroup_auto_out_clock; // @[LazyModule.scala 298:16]
  assign fixedClockNode_auto_in_reset = clockGroup_auto_out_reset; // @[LazyModule.scala 298:16]
endmodule
module ClockGroupAggregator_3(
  input   auto_in_member_subsystem_cbus_1_clock,
  input   auto_in_member_subsystem_cbus_1_reset,
  input   auto_in_member_subsystem_cbus_0_clock,
  input   auto_in_member_subsystem_cbus_0_reset,
  output  auto_out_1_member_subsystem_pbus_0_clock,
  output  auto_out_1_member_subsystem_pbus_0_reset,
  output  auto_out_0_member_subsystem_cbus_0_clock,
  output  auto_out_0_member_subsystem_cbus_0_reset
);
  assign auto_out_1_member_subsystem_pbus_0_clock = auto_in_member_subsystem_cbus_1_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_member_subsystem_pbus_0_reset = auto_in_member_subsystem_cbus_1_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_0_member_subsystem_cbus_0_clock = auto_in_member_subsystem_cbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_0_member_subsystem_cbus_0_reset = auto_in_member_subsystem_cbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module ClockGroup_3(
  input   auto_in_member_subsystem_cbus_0_clock,
  input   auto_in_member_subsystem_cbus_0_reset,
  output  auto_out_clock,
  output  auto_out_reset
);
  assign auto_out_clock = auto_in_member_subsystem_cbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_reset = auto_in_member_subsystem_cbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module FixedClockBroadcast_3(
  input   auto_in_clock,
  input   auto_in_reset,
  output  auto_out_3_clock,
  output  auto_out_3_reset,
  output  auto_out_1_clock,
  output  auto_out_1_reset,
  output  auto_out_0_clock,
  output  auto_out_0_reset
);
  assign auto_out_3_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_3_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_0_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_0_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module TLMonitor_24(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [3:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [29:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_param,
  input  [3:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source,
  input         io_in_d_bits_sink,
  input         io_in_d_bits_denied,
  input         io_in_d_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [26:0] _is_aligned_mask_T_1 = 27'hfff << io_in_a_bits_size; // @[package.scala 234:77]
  wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1[11:0]; // @[package.scala 234:46]
  wire [29:0] _GEN_71 = {{18'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [29:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 30'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 4'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire [30:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire  _T_35 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42]
  wire  _T_42 = _T_35 & source_ok; // @[Parameters.scala 1160:30]
  wire [30:0] _T_48 = $signed(_T_7) & -31'sh10001000; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_50 = io_in_a_bits_address ^ 30'h3000; // @[Parameters.scala 137:31]
  wire [30:0] _T_51 = {1'b0,$signed(_T_50)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_53 = $signed(_T_51) & -31'sh1000; // @[Parameters.scala 137:52]
  wire  _T_54 = $signed(_T_53) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_55 = io_in_a_bits_address ^ 30'h10000; // @[Parameters.scala 137:31]
  wire [30:0] _T_56 = {1'b0,$signed(_T_55)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_58 = $signed(_T_56) & -31'sh10000; // @[Parameters.scala 137:52]
  wire  _T_59 = $signed(_T_58) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_60 = io_in_a_bits_address ^ 30'h2000000; // @[Parameters.scala 137:31]
  wire [30:0] _T_61 = {1'b0,$signed(_T_60)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_63 = $signed(_T_61) & -31'sh10000; // @[Parameters.scala 137:52]
  wire  _T_64 = $signed(_T_63) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_65 = io_in_a_bits_address ^ 30'h8000000; // @[Parameters.scala 137:31]
  wire [30:0] _T_66 = {1'b0,$signed(_T_65)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_68 = $signed(_T_66) & -31'sh4000; // @[Parameters.scala 137:52]
  wire  _T_69 = $signed(_T_68) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_70 = io_in_a_bits_address ^ 30'hc000000; // @[Parameters.scala 137:31]
  wire [30:0] _T_71 = {1'b0,$signed(_T_70)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_73 = $signed(_T_71) & -31'sh4000000; // @[Parameters.scala 137:52]
  wire  _T_74 = $signed(_T_73) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_75 = io_in_a_bits_address ^ 30'h10012000; // @[Parameters.scala 137:31]
  wire [30:0] _T_76 = {1'b0,$signed(_T_75)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_78 = $signed(_T_76) & -31'sh2000; // @[Parameters.scala 137:52]
  wire  _T_79 = $signed(_T_78) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_80 = io_in_a_bits_address ^ 30'h10014000; // @[Parameters.scala 137:31]
  wire [30:0] _T_81 = {1'b0,$signed(_T_80)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_83 = $signed(_T_81) & -31'sh2000; // @[Parameters.scala 137:52]
  wire  _T_84 = $signed(_T_83) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_85 = io_in_a_bits_address ^ 30'h10016000; // @[Parameters.scala 137:31]
  wire [30:0] _T_86 = {1'b0,$signed(_T_85)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_88 = $signed(_T_86) & -31'sh1000; // @[Parameters.scala 137:52]
  wire  _T_89 = $signed(_T_88) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_90 = io_in_a_bits_address ^ 30'h10023000; // @[Parameters.scala 137:31]
  wire [30:0] _T_91 = {1'b0,$signed(_T_90)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_93 = $signed(_T_91) & -31'sh11000; // @[Parameters.scala 137:52]
  wire  _T_94 = $signed(_T_93) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_95 = io_in_a_bits_address ^ 30'h10024000; // @[Parameters.scala 137:31]
  wire [30:0] _T_96 = {1'b0,$signed(_T_95)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_98 = $signed(_T_96) & -31'sh12000; // @[Parameters.scala 137:52]
  wire  _T_99 = $signed(_T_98) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_100 = io_in_a_bits_address ^ 30'h10026000; // @[Parameters.scala 137:31]
  wire [30:0] _T_101 = {1'b0,$signed(_T_100)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_103 = $signed(_T_101) & -31'sh1000; // @[Parameters.scala 137:52]
  wire  _T_104 = $signed(_T_103) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_105 = io_in_a_bits_address ^ 30'h10043000; // @[Parameters.scala 137:31]
  wire [30:0] _T_106 = {1'b0,$signed(_T_105)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_108 = $signed(_T_106) & -31'sh11000; // @[Parameters.scala 137:52]
  wire  _T_109 = $signed(_T_108) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_110 = io_in_a_bits_address ^ 30'h20000000; // @[Parameters.scala 137:31]
  wire [30:0] _T_111 = {1'b0,$signed(_T_110)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_113 = $signed(_T_111) & -31'sh20000000; // @[Parameters.scala 137:52]
  wire  _T_114 = $signed(_T_113) == 31'sh0; // @[Parameters.scala 137:67]
  wire  _T_127 = _T_49 | _T_54 | _T_59 | _T_64 | _T_69 | _T_74 | _T_79 | _T_84 | _T_89 | _T_94 | _T_99 | _T_104 | _T_109
     | _T_114; // @[Parameters.scala 671:42]
  wire  _T_137 = 4'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_138 = _source_ok_T & _T_137; // @[Mux.scala 27:73]
  wire  _T_230 = _T_35 & _T_127; // @[Parameters.scala 670:56]
  wire  _T_232 = _T_138 & _T_230; // @[Monitor.scala 83:78]
  wire  _T_246 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_250 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_251 = _T_250 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_255 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_259 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_476 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_489 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_512 = _T_35 & _T_54; // @[Parameters.scala 670:56]
  wire  _T_514 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42]
  wire  _T_593 = _T_49 | _T_59 | _T_64 | _T_69 | _T_74 | _T_79 | _T_84 | _T_89 | _T_94 | _T_99 | _T_104 | _T_109 |
    _T_114; // @[Parameters.scala 671:42]
  wire  _T_594 = _T_514 & _T_593; // @[Parameters.scala 670:56]
  wire  _T_596 = _T_512 | _T_594; // @[Parameters.scala 672:30]
  wire  _T_606 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_610 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_618 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_707 = _T_49 | _T_64 | _T_69 | _T_74 | _T_79 | _T_84 | _T_89 | _T_94 | _T_99 | _T_104 | _T_109; // @[Parameters.scala 671:42]
  wire  _T_708 = _T_514 & _T_707; // @[Parameters.scala 670:56]
  wire  _T_723 = _T_512 | _T_708; // @[Parameters.scala 672:30]
  wire  _T_725 = _T_42 & _T_723; // @[Monitor.scala 115:71]
  wire  _T_743 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_864 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_865 = io_in_a_bits_mask & _T_864; // @[Monitor.scala 127:31]
  wire  _T_866 = _T_865 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_870 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_882 = io_in_a_bits_size <= 4'h2; // @[Parameters.scala 92:42]
  wire  _T_931 = _T_54 | _T_79 | _T_84 | _T_89 | _T_94 | _T_99 | _T_104 | _T_109; // @[Parameters.scala 671:42]
  wire  _T_932 = _T_882 & _T_931; // @[Parameters.scala 670:56]
  wire  _T_972 = _T_42 & _T_932; // @[Monitor.scala 131:74]
  wire  _T_982 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_990 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_1102 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_1110 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_1212 = _T_42 & _T_512; // @[Monitor.scala 147:68]
  wire  _T_1222 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_1234 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  _T_1238 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_1242 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 312:27]
  wire  _T_1246 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
  wire  _T_1250 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
  wire  _T_1254 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
  wire  _T_1258 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_1269 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
  wire  _T_1273 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
  wire  _T_1286 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_1306 = _T_1254 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
  wire  _T_1315 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_1332 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_1350 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [9:0] a_first_beats1_decode = is_aligned_mask[11:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [9:0] a_first_counter; // @[Edges.scala 228:27]
  wire [9:0] a_first_counter1 = a_first_counter - 10'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 10'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [3:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [29:0] address; // @[Monitor.scala 388:22]
  wire  _T_1380 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_1381 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_1385 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_1389 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_1393 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_1397 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [26:0] _d_first_beats1_decode_T_1 = 27'hfff << io_in_d_bits_size; // @[package.scala 234:77]
  wire [11:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
  wire [9:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[11:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [9:0] d_first_counter; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1 = d_first_counter - 10'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 10'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] param_1; // @[Monitor.scala 536:22]
  reg [3:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  reg  sink; // @[Monitor.scala 539:22]
  reg  denied; // @[Monitor.scala 540:22]
  wire  _T_1404 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_1405 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_1409 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
  wire  _T_1413 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_1417 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  wire  _T_1421 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
  wire  _T_1425 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [23:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [9:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [9:0] a_first_counter1_1 = a_first_counter_1 - 10'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 10'h0; // @[Edges.scala 230:25]
  reg [9:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1_1 = d_first_counter_1 - 10'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 10'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [4:0] _a_size_lookup_T = {io_in_d_bits_source, 3'h0}; // @[Monitor.scala 638:65]
  wire [23:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _a_size_lookup_T_5 = 16'h100 - 16'h1; // @[Monitor.scala 609:57]
  wire [23:0] _GEN_75 = {{8'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 638:91]
  wire [23:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_75; // @[Monitor.scala 638:91]
  wire [23:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[23:1]}; // @[Monitor.scala 638:144]
  wire  _T_1431 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_1434 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [4:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 5'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_77 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_77}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [4:0] _a_sizes_set_T = {io_in_a_bits_source, 3'h0}; // @[Monitor.scala 657:77]
  wire [4:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala 652:72 655:28]
  wire [35:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [35:0] _a_sizes_set_T_1 = _GEN_2 << _a_sizes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_1436 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_1438 = ~_T_1436[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [35:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 36'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_1442 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_1444 = ~_T_1238; // @[Monitor.scala 671:74]
  wire  _T_1445 = io_in_d_valid & d_first_1 & ~_T_1238; // @[Monitor.scala 671:71]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [46:0] _GEN_4 = {{31'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 678:74]
  wire [46:0] _d_sizes_clr_T_5 = _GEN_4 << _a_size_lookup_T; // @[Monitor.scala 678:74]
  wire [3:0] _GEN_22 = _d_first_T & d_first_1 & _T_1444 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_23 = _d_first_T & d_first_1 & _T_1444 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire [46:0] _GEN_24 = _d_first_T & d_first_1 & _T_1444 ? _d_sizes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 678:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_1431 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_1455 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_1457 = _T_1455[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_1462 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_1463 = io_in_d_bits_opcode == _GEN_32 | _T_1462; // @[Monitor.scala 685:77]
  wire  _T_1467 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_1474 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_1475 = io_in_d_bits_opcode == _GEN_48 | _T_1474; // @[Monitor.scala 689:72]
  wire [7:0] a_size_lookup = _a_size_lookup_T_7[7:0];
  wire [7:0] _GEN_79 = {{4'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_1479 = _GEN_79 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_1489 = _T_1442 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_1444; // @[Monitor.scala 694:116]
  wire  _T_1491 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set = _GEN_16[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_22[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_19[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_23[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [23:0] a_sizes_set = _GEN_20[23:0];
  wire [23:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [23:0] d_sizes_clr = _GEN_24[23:0];
  wire [23:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala 704:56]
  wire [23:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_1500 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [2:0] inflight_1; // @[Monitor.scala 723:35]
  reg [23:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [9:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1_2 = d_first_counter_2 - 10'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 10'h0; // @[Edges.scala 230:25]
  wire [23:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_size_lookup_T; // @[Monitor.scala 747:42]
  wire [23:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_75; // @[Monitor.scala 747:93]
  wire [23:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[23:1]}; // @[Monitor.scala 747:146]
  wire  _T_1526 = io_in_d_valid & d_first_2 & _T_1238; // @[Monitor.scala 779:71]
  wire [3:0] _GEN_67 = _d_first_T & d_first_2 & _T_1238 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 783:90 784:21]
  wire [46:0] _GEN_69 = _d_first_T & d_first_2 & _T_1238 ? _d_sizes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 786:21]
  wire [2:0] _T_1534 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [7:0] c_size_lookup = _c_size_lookup_T_7[7:0];
  wire  _T_1544 = _GEN_79 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [2:0] d_clr_1 = _GEN_67[2:0];
  wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [2:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [23:0] d_sizes_clr_1 = _GEN_69[23:0];
  wire [23:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
  wire [23:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_1564 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 10'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 10'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 10'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 24'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 10'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 10'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 3'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 24'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 10'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_232 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_232) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_246 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_246) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_251 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_251) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_255 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_255) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_232 & (io_in_a_valid & _T_259 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset & ~_T_232) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_259 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_259 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_259 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_246 & (io_in_a_valid & _T_259 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset & ~_T_246) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_476 & (io_in_a_valid & _T_259 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset & ~_T_476) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_251 & (io_in_a_valid & _T_259 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset & ~_T_251) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_255 & (io_in_a_valid & _T_259 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset & ~_T_255) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_42 & (io_in_a_valid & _T_489 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_489 & ~reset & ~_T_42) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_596 & (io_in_a_valid & _T_489 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_489 & ~reset & ~_T_596) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_489 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_489 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_489 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_489 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_606 & (io_in_a_valid & _T_489 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_489 & ~reset & ~_T_606) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_610 & (io_in_a_valid & _T_489 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_489 & ~reset & ~_T_610) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_255 & (io_in_a_valid & _T_489 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_489 & ~reset & ~_T_255) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_725 & (io_in_a_valid & _T_618 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_618 & ~reset & ~_T_725) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_618 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_618 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_618 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_618 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_606 & (io_in_a_valid & _T_618 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_618 & ~reset & ~_T_606) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_610 & (io_in_a_valid & _T_618 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_618 & ~reset & ~_T_610) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_725 & (io_in_a_valid & _T_743 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_743 & ~reset & ~_T_725) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_743 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_743 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_743 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_743 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_606 & (io_in_a_valid & _T_743 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_743 & ~reset & ~_T_606) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_866 & (io_in_a_valid & _T_743 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_743 & ~reset & ~_T_866) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_972 & (io_in_a_valid & _T_870 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_870 & ~reset & ~_T_972) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_870 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_870 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_870 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_870 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_982 & (io_in_a_valid & _T_870 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_870 & ~reset & ~_T_982) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_610 & (io_in_a_valid & _T_870 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_870 & ~reset & ~_T_610) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_972 & (io_in_a_valid & _T_990 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_990 & ~reset & ~_T_972) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_990 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_990 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_990 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_990 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1102 & (io_in_a_valid & _T_990 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_990 & ~reset & ~_T_1102) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_610 & (io_in_a_valid & _T_990 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_990 & ~reset & ~_T_610) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1212 & (io_in_a_valid & _T_1110 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1110 & ~reset & ~_T_1212) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_1110 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1110 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_1110 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1110 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1222 & (io_in_a_valid & _T_1110 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1110 & ~reset & ~_T_1222) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_610 & (io_in_a_valid & _T_1110 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1110 & ~reset & ~_T_610) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_255 & (io_in_a_valid & _T_1110 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1110 & ~reset & ~_T_255) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1234 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_1234) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1238 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1238 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1242 & (io_in_d_valid & _T_1238 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1238 & _T_2 & ~_T_1242) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1246 & (io_in_d_valid & _T_1238 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1238 & _T_2 & ~_T_1246) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1250 & (io_in_d_valid & _T_1238 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1238 & _T_2 & ~_T_1250) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1254 & (io_in_d_valid & _T_1238 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1238 & _T_2 & ~_T_1254) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is denied (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1258 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1258 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_1258 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1258 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1242 & (io_in_d_valid & _T_1258 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1258 & _T_2 & ~_T_1242) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1269 & (io_in_d_valid & _T_1258 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1258 & _T_2 & ~_T_1269) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid cap param (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1273 & (io_in_d_valid & _T_1258 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1258 & _T_2 & ~_T_1273) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries toN param (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1250 & (io_in_d_valid & _T_1258 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1258 & _T_2 & ~_T_1250) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is corrupt (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1286 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1286 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_1286 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1286 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1242 & (io_in_d_valid & _T_1286 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1286 & _T_2 & ~_T_1242) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1269 & (io_in_d_valid & _T_1286 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1286 & _T_2 & ~_T_1269) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1273 & (io_in_d_valid & _T_1286 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1286 & _T_2 & ~_T_1273) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries toN param (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1306 & (io_in_d_valid & _T_1286 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1286 & _T_2 & ~_T_1306) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1315 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1315 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1246 & (io_in_d_valid & _T_1315 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1315 & _T_2 & ~_T_1246) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid param (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1250 & (io_in_d_valid & _T_1315 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1315 & _T_2 & ~_T_1250) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is corrupt (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1332 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1332 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1246 & (io_in_d_valid & _T_1332 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1332 & _T_2 & ~_T_1246) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1306 & (io_in_d_valid & _T_1332 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1332 & _T_2 & ~_T_1306) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1350 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1350 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1246 & (io_in_d_valid & _T_1350 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1350 & _T_2 & ~_T_1246) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid param (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1250 & (io_in_d_valid & _T_1350 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1350 & _T_2 & ~_T_1250) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is corrupt (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1381 & (_T_1380 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1380 & ~reset & ~_T_1381) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1385 & (_T_1380 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1380 & ~reset & ~_T_1385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1389 & (_T_1380 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1380 & ~reset & ~_T_1389) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1393 & (_T_1380 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1380 & ~reset & ~_T_1393) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1397 & (_T_1380 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1380 & ~reset & ~_T_1397) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1405 & (_T_1404 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1404 & _T_2 & ~_T_1405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1409 & (_T_1404 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1404 & _T_2 & ~_T_1409) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel param changed within multibeat operation (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1413 & (_T_1404 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1404 & _T_2 & ~_T_1413) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1417 & (_T_1404 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1404 & _T_2 & ~_T_1417) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1421 & (_T_1404 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1404 & _T_2 & ~_T_1421) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel sink changed with multibeat operation (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1425 & (_T_1404 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1404 & _T_2 & ~_T_1425) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel denied changed with multibeat operation (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1438 & (_T_1434 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1434 & ~reset & ~_T_1438) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1457 & (_T_1445 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1445 & _T_2 & ~_T_1457) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1463 & (_T_1445 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1445 & same_cycle_resp & _T_2 & ~_T_1463) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1467 & (_T_1445 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1445 & same_cycle_resp & _T_2 & ~_T_1467) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1475 & (_T_1445 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1445 & ~same_cycle_resp & _T_2 & ~_T_1475) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1479 & (_T_1445 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1445 & ~same_cycle_resp & _T_2 & ~_T_1479) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1491 & (_T_1489 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1489 & _T_2 & ~_T_1491) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1500 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_1500) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1534[0] & (_T_1526 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1526 & _T_2 & ~_T_1534[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1544 & (_T_1526 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1526 & _T_2 & ~_T_1544) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1564 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_1564) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:54:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[9:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[29:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[9:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  param_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  size_1 = _RAND_9[3:0];
  _RAND_10 = {1{`RANDOM}};
  source_1 = _RAND_10[1:0];
  _RAND_11 = {1{`RANDOM}};
  sink = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  denied = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  inflight = _RAND_13[2:0];
  _RAND_14 = {1{`RANDOM}};
  inflight_opcodes = _RAND_14[11:0];
  _RAND_15 = {1{`RANDOM}};
  inflight_sizes = _RAND_15[23:0];
  _RAND_16 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_16[9:0];
  _RAND_17 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_17[9:0];
  _RAND_18 = {1{`RANDOM}};
  watchdog = _RAND_18[31:0];
  _RAND_19 = {1{`RANDOM}};
  inflight_1 = _RAND_19[2:0];
  _RAND_20 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_20[23:0];
  _RAND_21 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_21[9:0];
  _RAND_22 = {1{`RANDOM}};
  watchdog_1 = _RAND_22[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLFIFOFixer_2(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [3:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [29:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [1:0]  auto_in_d_bits_param,
  output [3:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output        auto_in_d_bits_sink,
  output        auto_in_d_bits_denied,
  output [31:0] auto_in_d_bits_data,
  output        auto_in_d_bits_corrupt,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [3:0]  auto_out_a_bits_size,
  output [1:0]  auto_out_a_bits_source,
  output [29:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_param,
  input  [3:0]  auto_out_d_bits_size,
  input  [1:0]  auto_out_d_bits_source,
  input         auto_out_d_bits_sink,
  input         auto_out_d_bits_denied,
  input  [31:0] auto_out_d_bits_data,
  input         auto_out_d_bits_corrupt
);
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [29:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
  TLMonitor_24 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_param(monitor_io_in_d_bits_param),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source),
    .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
    .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
    .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
  );
  assign auto_in_a_ready = auto_out_a_ready; // @[FIFOFixer.scala 88:33]
  assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = auto_in_a_valid; // @[FIFOFixer.scala 87:33]
  assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = auto_out_a_ready; // @[FIFOFixer.scala 88:33]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
endmodule
module TLXbar_4(
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [3:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [29:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [1:0]  auto_in_d_bits_param,
  output [3:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output        auto_in_d_bits_sink,
  output        auto_in_d_bits_denied,
  output [31:0] auto_in_d_bits_data,
  output        auto_in_d_bits_corrupt,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [3:0]  auto_out_a_bits_size,
  output [1:0]  auto_out_a_bits_source,
  output [29:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_param,
  input  [3:0]  auto_out_d_bits_size,
  input  [1:0]  auto_out_d_bits_source,
  input         auto_out_d_bits_sink,
  input         auto_out_d_bits_denied,
  input  [31:0] auto_out_d_bits_data,
  input         auto_out_d_bits_corrupt
);
  assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_valid = auto_out_d_valid; // @[ReadyValidCancel.scala 21:38]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Xbar.scala 228:69]
  assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[Xbar.scala 323:53]
  assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = auto_in_a_valid; // @[ReadyValidCancel.scala 21:38]
  assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
  assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module TLMonitor_25(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [3:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [29:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_param,
  input  [3:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source,
  input         io_in_d_bits_sink,
  input         io_in_d_bits_denied,
  input         io_in_d_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [26:0] _is_aligned_mask_T_1 = 27'hfff << io_in_a_bits_size; // @[package.scala 234:77]
  wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1[11:0]; // @[package.scala 234:46]
  wire [29:0] _GEN_71 = {{18'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [29:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 30'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 4'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire [30:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire  _T_35 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42]
  wire  _T_42 = _T_35 & source_ok; // @[Parameters.scala 1160:30]
  wire [30:0] _T_48 = $signed(_T_7) & -31'sh10001000; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_50 = io_in_a_bits_address ^ 30'h3000; // @[Parameters.scala 137:31]
  wire [30:0] _T_51 = {1'b0,$signed(_T_50)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_53 = $signed(_T_51) & -31'sh1000; // @[Parameters.scala 137:52]
  wire  _T_54 = $signed(_T_53) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_55 = io_in_a_bits_address ^ 30'h10000; // @[Parameters.scala 137:31]
  wire [30:0] _T_56 = {1'b0,$signed(_T_55)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_58 = $signed(_T_56) & -31'sh10000; // @[Parameters.scala 137:52]
  wire  _T_59 = $signed(_T_58) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_60 = io_in_a_bits_address ^ 30'h2000000; // @[Parameters.scala 137:31]
  wire [30:0] _T_61 = {1'b0,$signed(_T_60)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_63 = $signed(_T_61) & -31'sh10000; // @[Parameters.scala 137:52]
  wire  _T_64 = $signed(_T_63) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_65 = io_in_a_bits_address ^ 30'h8000000; // @[Parameters.scala 137:31]
  wire [30:0] _T_66 = {1'b0,$signed(_T_65)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_68 = $signed(_T_66) & -31'sh4000; // @[Parameters.scala 137:52]
  wire  _T_69 = $signed(_T_68) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_70 = io_in_a_bits_address ^ 30'hc000000; // @[Parameters.scala 137:31]
  wire [30:0] _T_71 = {1'b0,$signed(_T_70)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_73 = $signed(_T_71) & -31'sh4000000; // @[Parameters.scala 137:52]
  wire  _T_74 = $signed(_T_73) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_75 = io_in_a_bits_address ^ 30'h10012000; // @[Parameters.scala 137:31]
  wire [30:0] _T_76 = {1'b0,$signed(_T_75)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_78 = $signed(_T_76) & -31'sh2000; // @[Parameters.scala 137:52]
  wire  _T_79 = $signed(_T_78) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_80 = io_in_a_bits_address ^ 30'h10014000; // @[Parameters.scala 137:31]
  wire [30:0] _T_81 = {1'b0,$signed(_T_80)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_83 = $signed(_T_81) & -31'sh2000; // @[Parameters.scala 137:52]
  wire  _T_84 = $signed(_T_83) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_85 = io_in_a_bits_address ^ 30'h10016000; // @[Parameters.scala 137:31]
  wire [30:0] _T_86 = {1'b0,$signed(_T_85)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_88 = $signed(_T_86) & -31'sh1000; // @[Parameters.scala 137:52]
  wire  _T_89 = $signed(_T_88) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_90 = io_in_a_bits_address ^ 30'h10023000; // @[Parameters.scala 137:31]
  wire [30:0] _T_91 = {1'b0,$signed(_T_90)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_93 = $signed(_T_91) & -31'sh11000; // @[Parameters.scala 137:52]
  wire  _T_94 = $signed(_T_93) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_95 = io_in_a_bits_address ^ 30'h10024000; // @[Parameters.scala 137:31]
  wire [30:0] _T_96 = {1'b0,$signed(_T_95)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_98 = $signed(_T_96) & -31'sh12000; // @[Parameters.scala 137:52]
  wire  _T_99 = $signed(_T_98) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_100 = io_in_a_bits_address ^ 30'h10026000; // @[Parameters.scala 137:31]
  wire [30:0] _T_101 = {1'b0,$signed(_T_100)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_103 = $signed(_T_101) & -31'sh1000; // @[Parameters.scala 137:52]
  wire  _T_104 = $signed(_T_103) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_105 = io_in_a_bits_address ^ 30'h10043000; // @[Parameters.scala 137:31]
  wire [30:0] _T_106 = {1'b0,$signed(_T_105)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_108 = $signed(_T_106) & -31'sh11000; // @[Parameters.scala 137:52]
  wire  _T_109 = $signed(_T_108) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_110 = io_in_a_bits_address ^ 30'h20000000; // @[Parameters.scala 137:31]
  wire [30:0] _T_111 = {1'b0,$signed(_T_110)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_113 = $signed(_T_111) & -31'sh20000000; // @[Parameters.scala 137:52]
  wire  _T_114 = $signed(_T_113) == 31'sh0; // @[Parameters.scala 137:67]
  wire  _T_127 = _T_49 | _T_54 | _T_59 | _T_64 | _T_69 | _T_74 | _T_79 | _T_84 | _T_89 | _T_94 | _T_99 | _T_104 | _T_109
     | _T_114; // @[Parameters.scala 671:42]
  wire  _T_137 = 4'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_138 = _source_ok_T & _T_137; // @[Mux.scala 27:73]
  wire  _T_230 = _T_35 & _T_127; // @[Parameters.scala 670:56]
  wire  _T_232 = _T_138 & _T_230; // @[Monitor.scala 83:78]
  wire  _T_246 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_250 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_251 = _T_250 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_255 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_259 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_476 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_489 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_512 = _T_35 & _T_54; // @[Parameters.scala 670:56]
  wire  _T_514 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42]
  wire  _T_593 = _T_49 | _T_59 | _T_64 | _T_69 | _T_74 | _T_79 | _T_84 | _T_89 | _T_94 | _T_99 | _T_104 | _T_109 |
    _T_114; // @[Parameters.scala 671:42]
  wire  _T_594 = _T_514 & _T_593; // @[Parameters.scala 670:56]
  wire  _T_596 = _T_512 | _T_594; // @[Parameters.scala 672:30]
  wire  _T_606 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_610 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_618 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_707 = _T_49 | _T_64 | _T_69 | _T_74 | _T_79 | _T_84 | _T_89 | _T_94 | _T_99 | _T_104 | _T_109; // @[Parameters.scala 671:42]
  wire  _T_708 = _T_514 & _T_707; // @[Parameters.scala 670:56]
  wire  _T_723 = _T_512 | _T_708; // @[Parameters.scala 672:30]
  wire  _T_725 = _T_42 & _T_723; // @[Monitor.scala 115:71]
  wire  _T_743 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_864 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_865 = io_in_a_bits_mask & _T_864; // @[Monitor.scala 127:31]
  wire  _T_866 = _T_865 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_870 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_882 = io_in_a_bits_size <= 4'h2; // @[Parameters.scala 92:42]
  wire  _T_931 = _T_54 | _T_79 | _T_84 | _T_89 | _T_94 | _T_99 | _T_104 | _T_109; // @[Parameters.scala 671:42]
  wire  _T_932 = _T_882 & _T_931; // @[Parameters.scala 670:56]
  wire  _T_972 = _T_42 & _T_932; // @[Monitor.scala 131:74]
  wire  _T_982 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_990 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_1102 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_1110 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_1212 = _T_42 & _T_512; // @[Monitor.scala 147:68]
  wire  _T_1222 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_1234 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  _T_1238 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_1242 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 312:27]
  wire  _T_1246 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
  wire  _T_1250 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
  wire  _T_1254 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
  wire  _T_1258 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_1269 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
  wire  _T_1273 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
  wire  _T_1286 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_1306 = _T_1254 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
  wire  _T_1315 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_1332 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_1350 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [9:0] a_first_beats1_decode = is_aligned_mask[11:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [9:0] a_first_counter; // @[Edges.scala 228:27]
  wire [9:0] a_first_counter1 = a_first_counter - 10'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 10'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [3:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [29:0] address; // @[Monitor.scala 388:22]
  wire  _T_1380 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_1381 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_1385 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_1389 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_1393 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_1397 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [26:0] _d_first_beats1_decode_T_1 = 27'hfff << io_in_d_bits_size; // @[package.scala 234:77]
  wire [11:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
  wire [9:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[11:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [9:0] d_first_counter; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1 = d_first_counter - 10'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 10'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] param_1; // @[Monitor.scala 536:22]
  reg [3:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  reg  sink; // @[Monitor.scala 539:22]
  reg  denied; // @[Monitor.scala 540:22]
  wire  _T_1404 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_1405 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_1409 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
  wire  _T_1413 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_1417 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  wire  _T_1421 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
  wire  _T_1425 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [23:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [9:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [9:0] a_first_counter1_1 = a_first_counter_1 - 10'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 10'h0; // @[Edges.scala 230:25]
  reg [9:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1_1 = d_first_counter_1 - 10'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 10'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [4:0] _a_size_lookup_T = {io_in_d_bits_source, 3'h0}; // @[Monitor.scala 638:65]
  wire [23:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _a_size_lookup_T_5 = 16'h100 - 16'h1; // @[Monitor.scala 609:57]
  wire [23:0] _GEN_75 = {{8'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 638:91]
  wire [23:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_75; // @[Monitor.scala 638:91]
  wire [23:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[23:1]}; // @[Monitor.scala 638:144]
  wire  _T_1431 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_1434 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [4:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 5'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_77 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_77}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [4:0] _a_sizes_set_T = {io_in_a_bits_source, 3'h0}; // @[Monitor.scala 657:77]
  wire [4:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala 652:72 655:28]
  wire [35:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [35:0] _a_sizes_set_T_1 = _GEN_2 << _a_sizes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_1436 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_1438 = ~_T_1436[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [35:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 36'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_1442 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_1444 = ~_T_1238; // @[Monitor.scala 671:74]
  wire  _T_1445 = io_in_d_valid & d_first_1 & ~_T_1238; // @[Monitor.scala 671:71]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [46:0] _GEN_4 = {{31'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 678:74]
  wire [46:0] _d_sizes_clr_T_5 = _GEN_4 << _a_size_lookup_T; // @[Monitor.scala 678:74]
  wire [3:0] _GEN_22 = _d_first_T & d_first_1 & _T_1444 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_23 = _d_first_T & d_first_1 & _T_1444 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire [46:0] _GEN_24 = _d_first_T & d_first_1 & _T_1444 ? _d_sizes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 678:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_1431 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_1455 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_1457 = _T_1455[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_1462 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_1463 = io_in_d_bits_opcode == _GEN_32 | _T_1462; // @[Monitor.scala 685:77]
  wire  _T_1467 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_1474 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_1475 = io_in_d_bits_opcode == _GEN_48 | _T_1474; // @[Monitor.scala 689:72]
  wire [7:0] a_size_lookup = _a_size_lookup_T_7[7:0];
  wire [7:0] _GEN_79 = {{4'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_1479 = _GEN_79 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_1489 = _T_1442 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_1444; // @[Monitor.scala 694:116]
  wire  _T_1491 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set = _GEN_16[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_22[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_19[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_23[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [23:0] a_sizes_set = _GEN_20[23:0];
  wire [23:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [23:0] d_sizes_clr = _GEN_24[23:0];
  wire [23:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala 704:56]
  wire [23:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_1500 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [2:0] inflight_1; // @[Monitor.scala 723:35]
  reg [23:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [9:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1_2 = d_first_counter_2 - 10'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 10'h0; // @[Edges.scala 230:25]
  wire [23:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_size_lookup_T; // @[Monitor.scala 747:42]
  wire [23:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_75; // @[Monitor.scala 747:93]
  wire [23:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[23:1]}; // @[Monitor.scala 747:146]
  wire  _T_1526 = io_in_d_valid & d_first_2 & _T_1238; // @[Monitor.scala 779:71]
  wire [3:0] _GEN_67 = _d_first_T & d_first_2 & _T_1238 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 783:90 784:21]
  wire [46:0] _GEN_69 = _d_first_T & d_first_2 & _T_1238 ? _d_sizes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 786:21]
  wire [2:0] _T_1534 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [7:0] c_size_lookup = _c_size_lookup_T_7[7:0];
  wire  _T_1544 = _GEN_79 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [2:0] d_clr_1 = _GEN_67[2:0];
  wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [2:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [23:0] d_sizes_clr_1 = _GEN_69[23:0];
  wire [23:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
  wire [23:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_1564 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 10'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 10'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 10'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 24'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 10'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 10'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 3'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 24'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 10'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_232 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_232) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_246 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_246) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_251 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_251) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_255 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_255) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_232 & (io_in_a_valid & _T_259 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset & ~_T_232) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_259 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_259 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_259 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_246 & (io_in_a_valid & _T_259 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset & ~_T_246) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_476 & (io_in_a_valid & _T_259 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset & ~_T_476) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_251 & (io_in_a_valid & _T_259 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset & ~_T_251) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_255 & (io_in_a_valid & _T_259 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset & ~_T_255) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_42 & (io_in_a_valid & _T_489 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_489 & ~reset & ~_T_42) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_596 & (io_in_a_valid & _T_489 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_489 & ~reset & ~_T_596) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_489 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_489 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_489 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_489 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_606 & (io_in_a_valid & _T_489 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_489 & ~reset & ~_T_606) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_610 & (io_in_a_valid & _T_489 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_489 & ~reset & ~_T_610) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_255 & (io_in_a_valid & _T_489 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_489 & ~reset & ~_T_255) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_725 & (io_in_a_valid & _T_618 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_618 & ~reset & ~_T_725) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_618 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_618 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_618 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_618 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_606 & (io_in_a_valid & _T_618 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_618 & ~reset & ~_T_606) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_610 & (io_in_a_valid & _T_618 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_618 & ~reset & ~_T_610) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_725 & (io_in_a_valid & _T_743 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_743 & ~reset & ~_T_725) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_743 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_743 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_743 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_743 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_606 & (io_in_a_valid & _T_743 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_743 & ~reset & ~_T_606) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_866 & (io_in_a_valid & _T_743 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_743 & ~reset & ~_T_866) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_972 & (io_in_a_valid & _T_870 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_870 & ~reset & ~_T_972) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_870 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_870 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_870 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_870 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_982 & (io_in_a_valid & _T_870 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_870 & ~reset & ~_T_982) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_610 & (io_in_a_valid & _T_870 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_870 & ~reset & ~_T_610) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_972 & (io_in_a_valid & _T_990 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_990 & ~reset & ~_T_972) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_990 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_990 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_990 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_990 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1102 & (io_in_a_valid & _T_990 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_990 & ~reset & ~_T_1102) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_610 & (io_in_a_valid & _T_990 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_990 & ~reset & ~_T_610) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1212 & (io_in_a_valid & _T_1110 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1110 & ~reset & ~_T_1212) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_1110 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1110 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_1110 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1110 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1222 & (io_in_a_valid & _T_1110 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1110 & ~reset & ~_T_1222) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_610 & (io_in_a_valid & _T_1110 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1110 & ~reset & ~_T_610) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_255 & (io_in_a_valid & _T_1110 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1110 & ~reset & ~_T_255) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1234 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_1234) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1238 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1238 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1242 & (io_in_d_valid & _T_1238 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1238 & _T_2 & ~_T_1242) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1246 & (io_in_d_valid & _T_1238 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1238 & _T_2 & ~_T_1246) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1250 & (io_in_d_valid & _T_1238 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1238 & _T_2 & ~_T_1250) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1254 & (io_in_d_valid & _T_1238 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1238 & _T_2 & ~_T_1254) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is denied (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1258 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1258 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_1258 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1258 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1242 & (io_in_d_valid & _T_1258 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1258 & _T_2 & ~_T_1242) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1269 & (io_in_d_valid & _T_1258 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1258 & _T_2 & ~_T_1269) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid cap param (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1273 & (io_in_d_valid & _T_1258 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1258 & _T_2 & ~_T_1273) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries toN param (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1250 & (io_in_d_valid & _T_1258 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1258 & _T_2 & ~_T_1250) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is corrupt (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1286 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1286 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_1286 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1286 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1242 & (io_in_d_valid & _T_1286 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1286 & _T_2 & ~_T_1242) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1269 & (io_in_d_valid & _T_1286 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1286 & _T_2 & ~_T_1269) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1273 & (io_in_d_valid & _T_1286 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1286 & _T_2 & ~_T_1273) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries toN param (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1306 & (io_in_d_valid & _T_1286 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1286 & _T_2 & ~_T_1306) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1315 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1315 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1246 & (io_in_d_valid & _T_1315 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1315 & _T_2 & ~_T_1246) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid param (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1250 & (io_in_d_valid & _T_1315 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1315 & _T_2 & ~_T_1250) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is corrupt (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1332 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1332 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1246 & (io_in_d_valid & _T_1332 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1332 & _T_2 & ~_T_1246) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1306 & (io_in_d_valid & _T_1332 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1332 & _T_2 & ~_T_1306) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1350 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1350 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1246 & (io_in_d_valid & _T_1350 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1350 & _T_2 & ~_T_1246) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid param (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1250 & (io_in_d_valid & _T_1350 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1350 & _T_2 & ~_T_1250) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is corrupt (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1381 & (_T_1380 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1380 & ~reset & ~_T_1381) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1385 & (_T_1380 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1380 & ~reset & ~_T_1385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1389 & (_T_1380 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1380 & ~reset & ~_T_1389) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1393 & (_T_1380 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1380 & ~reset & ~_T_1393) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1397 & (_T_1380 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1380 & ~reset & ~_T_1397) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1405 & (_T_1404 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1404 & _T_2 & ~_T_1405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1409 & (_T_1404 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1404 & _T_2 & ~_T_1409) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel param changed within multibeat operation (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1413 & (_T_1404 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1404 & _T_2 & ~_T_1413) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1417 & (_T_1404 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1404 & _T_2 & ~_T_1417) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1421 & (_T_1404 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1404 & _T_2 & ~_T_1421) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel sink changed with multibeat operation (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1425 & (_T_1404 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1404 & _T_2 & ~_T_1425) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel denied changed with multibeat operation (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1438 & (_T_1434 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1434 & ~reset & ~_T_1438) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1457 & (_T_1445 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1445 & _T_2 & ~_T_1457) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1463 & (_T_1445 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1445 & same_cycle_resp & _T_2 & ~_T_1463) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1467 & (_T_1445 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1445 & same_cycle_resp & _T_2 & ~_T_1467) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1475 & (_T_1445 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1445 & ~same_cycle_resp & _T_2 & ~_T_1475) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1479 & (_T_1445 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1445 & ~same_cycle_resp & _T_2 & ~_T_1479) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1491 & (_T_1489 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1489 & _T_2 & ~_T_1491) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1500 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_1500) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1534[0] & (_T_1526 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1526 & _T_2 & ~_T_1534[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1544 & (_T_1526 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1526 & _T_2 & ~_T_1544) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1564 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_1564) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:53:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[9:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[29:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[9:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  param_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  size_1 = _RAND_9[3:0];
  _RAND_10 = {1{`RANDOM}};
  source_1 = _RAND_10[1:0];
  _RAND_11 = {1{`RANDOM}};
  sink = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  denied = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  inflight = _RAND_13[2:0];
  _RAND_14 = {1{`RANDOM}};
  inflight_opcodes = _RAND_14[11:0];
  _RAND_15 = {1{`RANDOM}};
  inflight_sizes = _RAND_15[23:0];
  _RAND_16 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_16[9:0];
  _RAND_17 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_17[9:0];
  _RAND_18 = {1{`RANDOM}};
  watchdog = _RAND_18[31:0];
  _RAND_19 = {1{`RANDOM}};
  inflight_1 = _RAND_19[2:0];
  _RAND_20 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_20[23:0];
  _RAND_21 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_21[9:0];
  _RAND_22 = {1{`RANDOM}};
  watchdog_1 = _RAND_22[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLXbar_5(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [3:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [29:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [1:0]  auto_in_d_bits_param,
  output [3:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output        auto_in_d_bits_sink,
  output        auto_in_d_bits_denied,
  output [31:0] auto_in_d_bits_data,
  output        auto_in_d_bits_corrupt,
  input         auto_out_7_a_ready,
  output        auto_out_7_a_valid,
  output [2:0]  auto_out_7_a_bits_opcode,
  output [2:0]  auto_out_7_a_bits_param,
  output [2:0]  auto_out_7_a_bits_size,
  output [1:0]  auto_out_7_a_bits_source,
  output [16:0] auto_out_7_a_bits_address,
  output [3:0]  auto_out_7_a_bits_mask,
  output        auto_out_7_a_bits_corrupt,
  output        auto_out_7_d_ready,
  input         auto_out_7_d_valid,
  input  [2:0]  auto_out_7_d_bits_size,
  input  [1:0]  auto_out_7_d_bits_source,
  input  [31:0] auto_out_7_d_bits_data,
  input         auto_out_6_a_ready,
  output        auto_out_6_a_valid,
  output [2:0]  auto_out_6_a_bits_opcode,
  output [2:0]  auto_out_6_a_bits_param,
  output [2:0]  auto_out_6_a_bits_size,
  output [1:0]  auto_out_6_a_bits_source,
  output [28:0] auto_out_6_a_bits_address,
  output [3:0]  auto_out_6_a_bits_mask,
  output [31:0] auto_out_6_a_bits_data,
  output        auto_out_6_a_bits_corrupt,
  output        auto_out_6_d_ready,
  input         auto_out_6_d_valid,
  input  [2:0]  auto_out_6_d_bits_opcode,
  input  [1:0]  auto_out_6_d_bits_param,
  input  [2:0]  auto_out_6_d_bits_size,
  input  [1:0]  auto_out_6_d_bits_source,
  input         auto_out_6_d_bits_sink,
  input         auto_out_6_d_bits_denied,
  input  [31:0] auto_out_6_d_bits_data,
  input         auto_out_6_d_bits_corrupt,
  input         auto_out_5_a_ready,
  output        auto_out_5_a_valid,
  output [2:0]  auto_out_5_a_bits_opcode,
  output [2:0]  auto_out_5_a_bits_param,
  output [2:0]  auto_out_5_a_bits_size,
  output [1:0]  auto_out_5_a_bits_source,
  output [27:0] auto_out_5_a_bits_address,
  output [3:0]  auto_out_5_a_bits_mask,
  output [31:0] auto_out_5_a_bits_data,
  output        auto_out_5_a_bits_corrupt,
  output        auto_out_5_d_ready,
  input         auto_out_5_d_valid,
  input  [2:0]  auto_out_5_d_bits_opcode,
  input  [1:0]  auto_out_5_d_bits_param,
  input  [2:0]  auto_out_5_d_bits_size,
  input  [1:0]  auto_out_5_d_bits_source,
  input         auto_out_5_d_bits_sink,
  input         auto_out_5_d_bits_denied,
  input  [31:0] auto_out_5_d_bits_data,
  input         auto_out_5_d_bits_corrupt,
  input         auto_out_4_a_ready,
  output        auto_out_4_a_valid,
  output [2:0]  auto_out_4_a_bits_opcode,
  output [2:0]  auto_out_4_a_bits_param,
  output [2:0]  auto_out_4_a_bits_size,
  output [1:0]  auto_out_4_a_bits_source,
  output [11:0] auto_out_4_a_bits_address,
  output [3:0]  auto_out_4_a_bits_mask,
  output [31:0] auto_out_4_a_bits_data,
  output        auto_out_4_a_bits_corrupt,
  output        auto_out_4_d_ready,
  input         auto_out_4_d_valid,
  input  [2:0]  auto_out_4_d_bits_opcode,
  input  [2:0]  auto_out_4_d_bits_size,
  input  [1:0]  auto_out_4_d_bits_source,
  input  [31:0] auto_out_4_d_bits_data,
  input         auto_out_3_a_ready,
  output        auto_out_3_a_valid,
  output [2:0]  auto_out_3_a_bits_opcode,
  output [2:0]  auto_out_3_a_bits_param,
  output [2:0]  auto_out_3_a_bits_size,
  output [1:0]  auto_out_3_a_bits_source,
  output [25:0] auto_out_3_a_bits_address,
  output [3:0]  auto_out_3_a_bits_mask,
  output [31:0] auto_out_3_a_bits_data,
  output        auto_out_3_a_bits_corrupt,
  output        auto_out_3_d_ready,
  input         auto_out_3_d_valid,
  input  [2:0]  auto_out_3_d_bits_opcode,
  input  [2:0]  auto_out_3_d_bits_size,
  input  [1:0]  auto_out_3_d_bits_source,
  input  [31:0] auto_out_3_d_bits_data,
  input         auto_out_2_a_ready,
  output        auto_out_2_a_valid,
  output [2:0]  auto_out_2_a_bits_opcode,
  output [2:0]  auto_out_2_a_bits_param,
  output [2:0]  auto_out_2_a_bits_size,
  output [1:0]  auto_out_2_a_bits_source,
  output [27:0] auto_out_2_a_bits_address,
  output [3:0]  auto_out_2_a_bits_mask,
  output [31:0] auto_out_2_a_bits_data,
  output        auto_out_2_a_bits_corrupt,
  output        auto_out_2_d_ready,
  input         auto_out_2_d_valid,
  input  [2:0]  auto_out_2_d_bits_opcode,
  input  [2:0]  auto_out_2_d_bits_size,
  input  [1:0]  auto_out_2_d_bits_source,
  input  [31:0] auto_out_2_d_bits_data,
  input         auto_out_1_a_ready,
  output        auto_out_1_a_valid,
  output [2:0]  auto_out_1_a_bits_opcode,
  output [2:0]  auto_out_1_a_bits_param,
  output [2:0]  auto_out_1_a_bits_size,
  output [1:0]  auto_out_1_a_bits_source,
  output [29:0] auto_out_1_a_bits_address,
  output [3:0]  auto_out_1_a_bits_mask,
  output [31:0] auto_out_1_a_bits_data,
  output        auto_out_1_a_bits_corrupt,
  output        auto_out_1_d_ready,
  input         auto_out_1_d_valid,
  input  [2:0]  auto_out_1_d_bits_opcode,
  input  [1:0]  auto_out_1_d_bits_param,
  input  [2:0]  auto_out_1_d_bits_size,
  input  [1:0]  auto_out_1_d_bits_source,
  input         auto_out_1_d_bits_sink,
  input         auto_out_1_d_bits_denied,
  input  [31:0] auto_out_1_d_bits_data,
  input         auto_out_1_d_bits_corrupt,
  input         auto_out_0_a_ready,
  output        auto_out_0_a_valid,
  output [2:0]  auto_out_0_a_bits_opcode,
  output [2:0]  auto_out_0_a_bits_param,
  output [3:0]  auto_out_0_a_bits_size,
  output [1:0]  auto_out_0_a_bits_source,
  output [13:0] auto_out_0_a_bits_address,
  output [3:0]  auto_out_0_a_bits_mask,
  output        auto_out_0_a_bits_corrupt,
  output        auto_out_0_d_ready,
  input         auto_out_0_d_valid,
  input  [2:0]  auto_out_0_d_bits_opcode,
  input  [1:0]  auto_out_0_d_bits_param,
  input  [3:0]  auto_out_0_d_bits_size,
  input  [1:0]  auto_out_0_d_bits_source,
  input         auto_out_0_d_bits_sink,
  input         auto_out_0_d_bits_denied,
  input  [31:0] auto_out_0_d_bits_data,
  input         auto_out_0_d_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [29:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
  reg [9:0] beatsLeft; // @[Arbiter.scala 87:30]
  wire  idle = beatsLeft == 10'h0; // @[Arbiter.scala 88:28]
  wire [7:0] readys_valid = {auto_out_7_d_valid,auto_out_6_d_valid,auto_out_5_d_valid,auto_out_4_d_valid,
    auto_out_3_d_valid,auto_out_2_d_valid,auto_out_1_d_valid,auto_out_0_d_valid}; // @[Cat.scala 31:58]
  reg [7:0] readys_mask; // @[Arbiter.scala 23:23]
  wire [7:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala 24:30]
  wire [7:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala 24:28]
  wire [15:0] readys_filter = {_readys_filter_T_1,auto_out_7_d_valid,auto_out_6_d_valid,auto_out_5_d_valid,
    auto_out_4_d_valid,auto_out_3_d_valid,auto_out_2_d_valid,auto_out_1_d_valid,auto_out_0_d_valid}; // @[Cat.scala 31:58]
  wire [15:0] _GEN_1 = {{1'd0}, readys_filter[15:1]}; // @[package.scala 253:43]
  wire [15:0] _readys_unready_T_1 = readys_filter | _GEN_1; // @[package.scala 253:43]
  wire [15:0] _GEN_2 = {{2'd0}, _readys_unready_T_1[15:2]}; // @[package.scala 253:43]
  wire [15:0] _readys_unready_T_3 = _readys_unready_T_1 | _GEN_2; // @[package.scala 253:43]
  wire [15:0] _GEN_3 = {{4'd0}, _readys_unready_T_3[15:4]}; // @[package.scala 253:43]
  wire [15:0] _readys_unready_T_5 = _readys_unready_T_3 | _GEN_3; // @[package.scala 253:43]
  wire [15:0] _readys_unready_T_8 = {readys_mask, 8'h0}; // @[Arbiter.scala 25:66]
  wire [15:0] _GEN_4 = {{1'd0}, _readys_unready_T_5[15:1]}; // @[Arbiter.scala 25:58]
  wire [15:0] readys_unready = _GEN_4 | _readys_unready_T_8; // @[Arbiter.scala 25:58]
  wire [7:0] _readys_readys_T_2 = readys_unready[15:8] & readys_unready[7:0]; // @[Arbiter.scala 26:39]
  wire [7:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala 26:18]
  wire  readys_0 = readys_readys[0]; // @[Arbiter.scala 95:86]
  wire  earlyWinner_0 = readys_0 & auto_out_0_d_valid; // @[Arbiter.scala 97:79]
  reg  state_0; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_0 = idle ? earlyWinner_0 : state_0; // @[Arbiter.scala 117:30]
  wire [1:0] _T_132 = muxStateEarly_0 ? auto_out_0_d_bits_source : 2'h0; // @[Mux.scala 27:73]
  wire  readys_1 = readys_readys[1]; // @[Arbiter.scala 95:86]
  wire  earlyWinner_1 = readys_1 & auto_out_1_d_valid; // @[Arbiter.scala 97:79]
  reg  state_1; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_1 = idle ? earlyWinner_1 : state_1; // @[Arbiter.scala 117:30]
  wire [1:0] _T_133 = muxStateEarly_1 ? auto_out_1_d_bits_source : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_140 = _T_132 | _T_133; // @[Mux.scala 27:73]
  wire  readys_2 = readys_readys[2]; // @[Arbiter.scala 95:86]
  wire  earlyWinner_2 = readys_2 & auto_out_2_d_valid; // @[Arbiter.scala 97:79]
  reg  state_2; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_2 = idle ? earlyWinner_2 : state_2; // @[Arbiter.scala 117:30]
  wire [1:0] _T_134 = muxStateEarly_2 ? auto_out_2_d_bits_source : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_141 = _T_140 | _T_134; // @[Mux.scala 27:73]
  wire  readys_3 = readys_readys[3]; // @[Arbiter.scala 95:86]
  wire  earlyWinner_3 = readys_3 & auto_out_3_d_valid; // @[Arbiter.scala 97:79]
  reg  state_3; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_3 = idle ? earlyWinner_3 : state_3; // @[Arbiter.scala 117:30]
  wire [1:0] _T_135 = muxStateEarly_3 ? auto_out_3_d_bits_source : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_142 = _T_141 | _T_135; // @[Mux.scala 27:73]
  wire  readys_4 = readys_readys[4]; // @[Arbiter.scala 95:86]
  wire  earlyWinner_4 = readys_4 & auto_out_4_d_valid; // @[Arbiter.scala 97:79]
  reg  state_4; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_4 = idle ? earlyWinner_4 : state_4; // @[Arbiter.scala 117:30]
  wire [1:0] _T_136 = muxStateEarly_4 ? auto_out_4_d_bits_source : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_143 = _T_142 | _T_136; // @[Mux.scala 27:73]
  wire  readys_5 = readys_readys[5]; // @[Arbiter.scala 95:86]
  wire  earlyWinner_5 = readys_5 & auto_out_5_d_valid; // @[Arbiter.scala 97:79]
  reg  state_5; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_5 = idle ? earlyWinner_5 : state_5; // @[Arbiter.scala 117:30]
  wire [1:0] _T_137 = muxStateEarly_5 ? auto_out_5_d_bits_source : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_144 = _T_143 | _T_137; // @[Mux.scala 27:73]
  wire  readys_6 = readys_readys[6]; // @[Arbiter.scala 95:86]
  wire  earlyWinner_6 = readys_6 & auto_out_6_d_valid; // @[Arbiter.scala 97:79]
  reg  state_6; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_6 = idle ? earlyWinner_6 : state_6; // @[Arbiter.scala 117:30]
  wire [1:0] _T_138 = muxStateEarly_6 ? auto_out_6_d_bits_source : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_145 = _T_144 | _T_138; // @[Mux.scala 27:73]
  wire  readys_7 = readys_readys[7]; // @[Arbiter.scala 95:86]
  wire  earlyWinner_7 = readys_7 & auto_out_7_d_valid; // @[Arbiter.scala 97:79]
  reg  state_7; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_7 = idle ? earlyWinner_7 : state_7; // @[Arbiter.scala 117:30]
  wire [1:0] _T_139 = muxStateEarly_7 ? auto_out_7_d_bits_source : 2'h0; // @[Mux.scala 27:73]
  wire [29:0] _requestAIO_T = auto_in_a_bits_address ^ 30'h3000; // @[Parameters.scala 137:31]
  wire [30:0] _requestAIO_T_1 = {1'b0,$signed(_requestAIO_T)}; // @[Parameters.scala 137:49]
  wire [30:0] _requestAIO_T_3 = $signed(_requestAIO_T_1) & 31'sh3e057000; // @[Parameters.scala 137:52]
  wire  requestAIO_0_0 = $signed(_requestAIO_T_3) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _requestAIO_T_5 = auto_in_a_bits_address ^ 30'h10003000; // @[Parameters.scala 137:31]
  wire [30:0] _requestAIO_T_6 = {1'b0,$signed(_requestAIO_T_5)}; // @[Parameters.scala 137:49]
  wire [30:0] _requestAIO_T_8 = $signed(_requestAIO_T_6) & 31'sh3e057000; // @[Parameters.scala 137:52]
  wire  _requestAIO_T_9 = $signed(_requestAIO_T_8) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _requestAIO_T_10 = auto_in_a_bits_address ^ 30'h10004000; // @[Parameters.scala 137:31]
  wire [30:0] _requestAIO_T_11 = {1'b0,$signed(_requestAIO_T_10)}; // @[Parameters.scala 137:49]
  wire [30:0] _requestAIO_T_13 = $signed(_requestAIO_T_11) & 31'sh3e046000; // @[Parameters.scala 137:52]
  wire  _requestAIO_T_14 = $signed(_requestAIO_T_13) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _requestAIO_T_15 = auto_in_a_bits_address ^ 30'h10006000; // @[Parameters.scala 137:31]
  wire [30:0] _requestAIO_T_16 = {1'b0,$signed(_requestAIO_T_15)}; // @[Parameters.scala 137:49]
  wire [30:0] _requestAIO_T_18 = $signed(_requestAIO_T_16) & 31'sh3e047000; // @[Parameters.scala 137:52]
  wire  _requestAIO_T_19 = $signed(_requestAIO_T_18) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _requestAIO_T_20 = auto_in_a_bits_address ^ 30'h10012000; // @[Parameters.scala 137:31]
  wire [30:0] _requestAIO_T_21 = {1'b0,$signed(_requestAIO_T_20)}; // @[Parameters.scala 137:49]
  wire [30:0] _requestAIO_T_23 = $signed(_requestAIO_T_21) & 31'sh3e056000; // @[Parameters.scala 137:52]
  wire  _requestAIO_T_24 = $signed(_requestAIO_T_23) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _requestAIO_T_25 = auto_in_a_bits_address ^ 30'h10043000; // @[Parameters.scala 137:31]
  wire [30:0] _requestAIO_T_26 = {1'b0,$signed(_requestAIO_T_25)}; // @[Parameters.scala 137:49]
  wire [30:0] _requestAIO_T_28 = $signed(_requestAIO_T_26) & 31'sh3e047000; // @[Parameters.scala 137:52]
  wire  _requestAIO_T_29 = $signed(_requestAIO_T_28) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _requestAIO_T_30 = auto_in_a_bits_address ^ 30'h20000000; // @[Parameters.scala 137:31]
  wire [30:0] _requestAIO_T_31 = {1'b0,$signed(_requestAIO_T_30)}; // @[Parameters.scala 137:49]
  wire [30:0] _requestAIO_T_33 = $signed(_requestAIO_T_31) & 31'sh20000000; // @[Parameters.scala 137:52]
  wire  _requestAIO_T_34 = $signed(_requestAIO_T_33) == 31'sh0; // @[Parameters.scala 137:67]
  wire  requestAIO_0_1 = _requestAIO_T_9 | _requestAIO_T_14 | _requestAIO_T_19 | _requestAIO_T_24 | _requestAIO_T_29 |
    _requestAIO_T_34; // @[Xbar.scala 363:92]
  wire [29:0] _requestAIO_T_40 = auto_in_a_bits_address ^ 30'hc000000; // @[Parameters.scala 137:31]
  wire [30:0] _requestAIO_T_41 = {1'b0,$signed(_requestAIO_T_40)}; // @[Parameters.scala 137:49]
  wire [30:0] _requestAIO_T_43 = $signed(_requestAIO_T_41) & 31'sh3c000000; // @[Parameters.scala 137:52]
  wire  requestAIO_0_2 = $signed(_requestAIO_T_43) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _requestAIO_T_45 = auto_in_a_bits_address ^ 30'h2000000; // @[Parameters.scala 137:31]
  wire [30:0] _requestAIO_T_46 = {1'b0,$signed(_requestAIO_T_45)}; // @[Parameters.scala 137:49]
  wire [30:0] _requestAIO_T_48 = $signed(_requestAIO_T_46) & 31'sh3e050000; // @[Parameters.scala 137:52]
  wire  requestAIO_0_3 = $signed(_requestAIO_T_48) == 31'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _requestAIO_T_51 = {1'b0,$signed(auto_in_a_bits_address)}; // @[Parameters.scala 137:49]
  wire [30:0] _requestAIO_T_53 = $signed(_requestAIO_T_51) & 31'sh3e057000; // @[Parameters.scala 137:52]
  wire  requestAIO_0_4 = $signed(_requestAIO_T_53) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _requestAIO_T_55 = auto_in_a_bits_address ^ 30'h8000000; // @[Parameters.scala 137:31]
  wire [30:0] _requestAIO_T_56 = {1'b0,$signed(_requestAIO_T_55)}; // @[Parameters.scala 137:49]
  wire [30:0] _requestAIO_T_58 = $signed(_requestAIO_T_56) & 31'sh3e054000; // @[Parameters.scala 137:52]
  wire  requestAIO_0_5 = $signed(_requestAIO_T_58) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _requestAIO_T_60 = auto_in_a_bits_address ^ 30'h10000000; // @[Parameters.scala 137:31]
  wire [30:0] _requestAIO_T_61 = {1'b0,$signed(_requestAIO_T_60)}; // @[Parameters.scala 137:49]
  wire [30:0] _requestAIO_T_63 = $signed(_requestAIO_T_61) & 31'sh3e057000; // @[Parameters.scala 137:52]
  wire  requestAIO_0_6 = $signed(_requestAIO_T_63) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _requestAIO_T_65 = auto_in_a_bits_address ^ 30'h10000; // @[Parameters.scala 137:31]
  wire [30:0] _requestAIO_T_66 = {1'b0,$signed(_requestAIO_T_65)}; // @[Parameters.scala 137:49]
  wire [30:0] _requestAIO_T_68 = $signed(_requestAIO_T_66) & 31'sh3e050000; // @[Parameters.scala 137:52]
  wire  requestAIO_0_7 = $signed(_requestAIO_T_68) == 31'sh0; // @[Parameters.scala 137:67]
  wire [26:0] _beatsDO_decode_T_1 = 27'hfff << auto_out_0_d_bits_size; // @[package.scala 234:77]
  wire [11:0] _beatsDO_decode_T_3 = ~_beatsDO_decode_T_1[11:0]; // @[package.scala 234:46]
  wire [9:0] beatsDO_decode = _beatsDO_decode_T_3[11:2]; // @[Edges.scala 219:59]
  wire  beatsDO_opdata = auto_out_0_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire [9:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 10'h0; // @[Edges.scala 220:14]
  wire [3:0] out_1_1_d_bits_size = {{1'd0}, auto_out_1_d_bits_size}; // @[BundleMap.scala 247:19 Xbar.scala 288:19]
  wire [20:0] _beatsDO_decode_T_5 = 21'h3f << out_1_1_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _beatsDO_decode_T_7 = ~_beatsDO_decode_T_5[5:0]; // @[package.scala 234:46]
  wire [3:0] beatsDO_decode_1 = _beatsDO_decode_T_7[5:2]; // @[Edges.scala 219:59]
  wire  beatsDO_opdata_1 = auto_out_1_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire [3:0] beatsDO_1 = beatsDO_opdata_1 ? beatsDO_decode_1 : 4'h0; // @[Edges.scala 220:14]
  wire [3:0] out_1_2_d_bits_size = {{1'd0}, auto_out_2_d_bits_size}; // @[BundleMap.scala 247:19 Xbar.scala 288:19]
  wire [20:0] _beatsDO_decode_T_9 = 21'h3f << out_1_2_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _beatsDO_decode_T_11 = ~_beatsDO_decode_T_9[5:0]; // @[package.scala 234:46]
  wire [3:0] beatsDO_decode_2 = _beatsDO_decode_T_11[5:2]; // @[Edges.scala 219:59]
  wire  beatsDO_opdata_2 = auto_out_2_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire [3:0] beatsDO_2 = beatsDO_opdata_2 ? beatsDO_decode_2 : 4'h0; // @[Edges.scala 220:14]
  wire [3:0] out_1_3_d_bits_size = {{1'd0}, auto_out_3_d_bits_size}; // @[BundleMap.scala 247:19 Xbar.scala 288:19]
  wire [20:0] _beatsDO_decode_T_13 = 21'h3f << out_1_3_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _beatsDO_decode_T_15 = ~_beatsDO_decode_T_13[5:0]; // @[package.scala 234:46]
  wire [3:0] beatsDO_decode_3 = _beatsDO_decode_T_15[5:2]; // @[Edges.scala 219:59]
  wire  beatsDO_opdata_3 = auto_out_3_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire [3:0] beatsDO_3 = beatsDO_opdata_3 ? beatsDO_decode_3 : 4'h0; // @[Edges.scala 220:14]
  wire [3:0] out_1_4_d_bits_size = {{1'd0}, auto_out_4_d_bits_size}; // @[BundleMap.scala 247:19 Xbar.scala 288:19]
  wire [20:0] _beatsDO_decode_T_17 = 21'h3f << out_1_4_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _beatsDO_decode_T_19 = ~_beatsDO_decode_T_17[5:0]; // @[package.scala 234:46]
  wire [3:0] beatsDO_decode_4 = _beatsDO_decode_T_19[5:2]; // @[Edges.scala 219:59]
  wire  beatsDO_opdata_4 = auto_out_4_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire [3:0] beatsDO_4 = beatsDO_opdata_4 ? beatsDO_decode_4 : 4'h0; // @[Edges.scala 220:14]
  wire [3:0] out_1_5_d_bits_size = {{1'd0}, auto_out_5_d_bits_size}; // @[BundleMap.scala 247:19 Xbar.scala 288:19]
  wire [20:0] _beatsDO_decode_T_21 = 21'h3f << out_1_5_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _beatsDO_decode_T_23 = ~_beatsDO_decode_T_21[5:0]; // @[package.scala 234:46]
  wire [3:0] beatsDO_decode_5 = _beatsDO_decode_T_23[5:2]; // @[Edges.scala 219:59]
  wire  beatsDO_opdata_5 = auto_out_5_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire [3:0] beatsDO_5 = beatsDO_opdata_5 ? beatsDO_decode_5 : 4'h0; // @[Edges.scala 220:14]
  wire [3:0] out_1_6_d_bits_size = {{1'd0}, auto_out_6_d_bits_size}; // @[BundleMap.scala 247:19 Xbar.scala 288:19]
  wire [20:0] _beatsDO_decode_T_25 = 21'h3f << out_1_6_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _beatsDO_decode_T_27 = ~_beatsDO_decode_T_25[5:0]; // @[package.scala 234:46]
  wire [3:0] beatsDO_decode_6 = _beatsDO_decode_T_27[5:2]; // @[Edges.scala 219:59]
  wire  beatsDO_opdata_6 = auto_out_6_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire [3:0] beatsDO_6 = beatsDO_opdata_6 ? beatsDO_decode_6 : 4'h0; // @[Edges.scala 220:14]
  wire [3:0] out_1_7_d_bits_size = {{1'd0}, auto_out_7_d_bits_size}; // @[BundleMap.scala 247:19 Xbar.scala 288:19]
  wire [20:0] _beatsDO_decode_T_29 = 21'h3f << out_1_7_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _beatsDO_decode_T_31 = ~_beatsDO_decode_T_29[5:0]; // @[package.scala 234:46]
  wire [3:0] beatsDO_decode_7 = _beatsDO_decode_T_31[5:2]; // @[Edges.scala 219:59]
  wire  latch = idle & auto_in_d_ready; // @[Arbiter.scala 89:24]
  wire  _readys_T_3 = ~reset; // @[Arbiter.scala 22:12]
  wire [7:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala 28:29]
  wire [8:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala 244:48]
  wire [7:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_1[7:0]; // @[package.scala 244:43]
  wire [9:0] _readys_mask_T_4 = {_readys_mask_T_3, 2'h0}; // @[package.scala 244:48]
  wire [7:0] _readys_mask_T_6 = _readys_mask_T_3 | _readys_mask_T_4[7:0]; // @[package.scala 244:43]
  wire [11:0] _readys_mask_T_7 = {_readys_mask_T_6, 4'h0}; // @[package.scala 244:48]
  wire [7:0] _readys_mask_T_9 = _readys_mask_T_6 | _readys_mask_T_7[7:0]; // @[package.scala 244:43]
  wire  prefixOR_2 = earlyWinner_0 | earlyWinner_1; // @[Arbiter.scala 104:53]
  wire  prefixOR_3 = prefixOR_2 | earlyWinner_2; // @[Arbiter.scala 104:53]
  wire  prefixOR_4 = prefixOR_3 | earlyWinner_3; // @[Arbiter.scala 104:53]
  wire  prefixOR_5 = prefixOR_4 | earlyWinner_4; // @[Arbiter.scala 104:53]
  wire  prefixOR_6 = prefixOR_5 | earlyWinner_5; // @[Arbiter.scala 104:53]
  wire  prefixOR_7 = prefixOR_6 | earlyWinner_6; // @[Arbiter.scala 104:53]
  wire  _prefixOR_T = prefixOR_7 | earlyWinner_7; // @[Arbiter.scala 104:53]
  wire  _T_40 = auto_out_0_d_valid | auto_out_1_d_valid | auto_out_2_d_valid | auto_out_3_d_valid | auto_out_4_d_valid
     | auto_out_5_d_valid | auto_out_6_d_valid | auto_out_7_d_valid; // @[Arbiter.scala 107:36]
  wire  _T_41 = ~(auto_out_0_d_valid | auto_out_1_d_valid | auto_out_2_d_valid | auto_out_3_d_valid | auto_out_4_d_valid
     | auto_out_5_d_valid | auto_out_6_d_valid | auto_out_7_d_valid); // @[Arbiter.scala 107:15]
  wire [9:0] maskedBeats_0 = earlyWinner_0 ? beatsDO_0 : 10'h0; // @[Arbiter.scala 111:73]
  wire [3:0] maskedBeats_1 = earlyWinner_1 ? beatsDO_1 : 4'h0; // @[Arbiter.scala 111:73]
  wire [3:0] maskedBeats_2 = earlyWinner_2 ? beatsDO_2 : 4'h0; // @[Arbiter.scala 111:73]
  wire [3:0] maskedBeats_3 = earlyWinner_3 ? beatsDO_3 : 4'h0; // @[Arbiter.scala 111:73]
  wire [3:0] maskedBeats_4 = earlyWinner_4 ? beatsDO_4 : 4'h0; // @[Arbiter.scala 111:73]
  wire [3:0] maskedBeats_5 = earlyWinner_5 ? beatsDO_5 : 4'h0; // @[Arbiter.scala 111:73]
  wire [3:0] maskedBeats_6 = earlyWinner_6 ? beatsDO_6 : 4'h0; // @[Arbiter.scala 111:73]
  wire [3:0] maskedBeats_7 = earlyWinner_7 ? beatsDO_decode_7 : 4'h0; // @[Arbiter.scala 111:73]
  wire [9:0] _GEN_5 = {{6'd0}, maskedBeats_1}; // @[Arbiter.scala 112:44]
  wire [9:0] _initBeats_T = maskedBeats_0 | _GEN_5; // @[Arbiter.scala 112:44]
  wire [9:0] _GEN_6 = {{6'd0}, maskedBeats_2}; // @[Arbiter.scala 112:44]
  wire [9:0] _initBeats_T_1 = _initBeats_T | _GEN_6; // @[Arbiter.scala 112:44]
  wire [9:0] _GEN_7 = {{6'd0}, maskedBeats_3}; // @[Arbiter.scala 112:44]
  wire [9:0] _initBeats_T_2 = _initBeats_T_1 | _GEN_7; // @[Arbiter.scala 112:44]
  wire [9:0] _GEN_8 = {{6'd0}, maskedBeats_4}; // @[Arbiter.scala 112:44]
  wire [9:0] _initBeats_T_3 = _initBeats_T_2 | _GEN_8; // @[Arbiter.scala 112:44]
  wire [9:0] _GEN_9 = {{6'd0}, maskedBeats_5}; // @[Arbiter.scala 112:44]
  wire [9:0] _initBeats_T_4 = _initBeats_T_3 | _GEN_9; // @[Arbiter.scala 112:44]
  wire [9:0] _GEN_10 = {{6'd0}, maskedBeats_6}; // @[Arbiter.scala 112:44]
  wire [9:0] _initBeats_T_5 = _initBeats_T_4 | _GEN_10; // @[Arbiter.scala 112:44]
  wire [9:0] _GEN_11 = {{6'd0}, maskedBeats_7}; // @[Arbiter.scala 112:44]
  wire [9:0] initBeats = _initBeats_T_5 | _GEN_11; // @[Arbiter.scala 112:44]
  wire  _sink_ACancel_earlyValid_T_21 = state_0 & auto_out_0_d_valid | state_1 & auto_out_1_d_valid | state_2 &
    auto_out_2_d_valid | state_3 & auto_out_3_d_valid | state_4 & auto_out_4_d_valid | state_5 & auto_out_5_d_valid |
    state_6 & auto_out_6_d_valid | state_7 & auto_out_7_d_valid; // @[Mux.scala 27:73]
  wire  sink_ACancel_17_earlyValid = idle ? _T_40 : _sink_ACancel_earlyValid_T_21; // @[Arbiter.scala 125:29]
  wire  _beatsLeft_T_2 = auto_in_d_ready & sink_ACancel_17_earlyValid; // @[ReadyValidCancel.scala 49:33]
  wire [9:0] _GEN_12 = {{9'd0}, _beatsLeft_T_2}; // @[Arbiter.scala 113:52]
  wire [9:0] _beatsLeft_T_4 = beatsLeft - _GEN_12; // @[Arbiter.scala 113:52]
  wire  allowed_0 = idle ? readys_0 : state_0; // @[Arbiter.scala 121:24]
  wire  allowed_1 = idle ? readys_1 : state_1; // @[Arbiter.scala 121:24]
  wire  allowed_2 = idle ? readys_2 : state_2; // @[Arbiter.scala 121:24]
  wire  allowed_3 = idle ? readys_3 : state_3; // @[Arbiter.scala 121:24]
  wire  allowed_4 = idle ? readys_4 : state_4; // @[Arbiter.scala 121:24]
  wire  allowed_5 = idle ? readys_5 : state_5; // @[Arbiter.scala 121:24]
  wire  allowed_6 = idle ? readys_6 : state_6; // @[Arbiter.scala 121:24]
  wire  allowed_7 = idle ? readys_7 : state_7; // @[Arbiter.scala 121:24]
  wire [31:0] _T_87 = muxStateEarly_0 ? auto_out_0_d_bits_data : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_88 = muxStateEarly_1 ? auto_out_1_d_bits_data : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_89 = muxStateEarly_2 ? auto_out_2_d_bits_data : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_90 = muxStateEarly_3 ? auto_out_3_d_bits_data : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_91 = muxStateEarly_4 ? auto_out_4_d_bits_data : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_92 = muxStateEarly_5 ? auto_out_5_d_bits_data : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_93 = muxStateEarly_6 ? auto_out_6_d_bits_data : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_94 = muxStateEarly_7 ? auto_out_7_d_bits_data : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_95 = _T_87 | _T_88; // @[Mux.scala 27:73]
  wire [31:0] _T_96 = _T_95 | _T_89; // @[Mux.scala 27:73]
  wire [31:0] _T_97 = _T_96 | _T_90; // @[Mux.scala 27:73]
  wire [31:0] _T_98 = _T_97 | _T_91; // @[Mux.scala 27:73]
  wire [31:0] _T_99 = _T_98 | _T_92; // @[Mux.scala 27:73]
  wire [31:0] _T_100 = _T_99 | _T_93; // @[Mux.scala 27:73]
  wire [3:0] _T_147 = muxStateEarly_0 ? auto_out_0_d_bits_size : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _T_148 = muxStateEarly_1 ? out_1_1_d_bits_size : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _T_149 = muxStateEarly_2 ? out_1_2_d_bits_size : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _T_150 = muxStateEarly_3 ? out_1_3_d_bits_size : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _T_151 = muxStateEarly_4 ? out_1_4_d_bits_size : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _T_152 = muxStateEarly_5 ? out_1_5_d_bits_size : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _T_153 = muxStateEarly_6 ? out_1_6_d_bits_size : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _T_154 = muxStateEarly_7 ? out_1_7_d_bits_size : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _T_155 = _T_147 | _T_148; // @[Mux.scala 27:73]
  wire [3:0] _T_156 = _T_155 | _T_149; // @[Mux.scala 27:73]
  wire [3:0] _T_157 = _T_156 | _T_150; // @[Mux.scala 27:73]
  wire [3:0] _T_158 = _T_157 | _T_151; // @[Mux.scala 27:73]
  wire [3:0] _T_159 = _T_158 | _T_152; // @[Mux.scala 27:73]
  wire [3:0] _T_160 = _T_159 | _T_153; // @[Mux.scala 27:73]
  wire [1:0] _T_162 = muxStateEarly_0 ? auto_out_0_d_bits_param : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_163 = muxStateEarly_1 ? auto_out_1_d_bits_param : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_167 = muxStateEarly_5 ? auto_out_5_d_bits_param : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_168 = muxStateEarly_6 ? auto_out_6_d_bits_param : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_170 = _T_162 | _T_163; // @[Mux.scala 27:73]
  wire [1:0] _T_174 = _T_170 | _T_167; // @[Mux.scala 27:73]
  wire [2:0] _T_177 = muxStateEarly_0 ? auto_out_0_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_178 = muxStateEarly_1 ? auto_out_1_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_179 = muxStateEarly_2 ? auto_out_2_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_180 = muxStateEarly_3 ? auto_out_3_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_181 = muxStateEarly_4 ? auto_out_4_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_182 = muxStateEarly_5 ? auto_out_5_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_183 = muxStateEarly_6 ? auto_out_6_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_184 = muxStateEarly_7 ? 3'h1 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_185 = _T_177 | _T_178; // @[Mux.scala 27:73]
  wire [2:0] _T_186 = _T_185 | _T_179; // @[Mux.scala 27:73]
  wire [2:0] _T_187 = _T_186 | _T_180; // @[Mux.scala 27:73]
  wire [2:0] _T_188 = _T_187 | _T_181; // @[Mux.scala 27:73]
  wire [2:0] _T_189 = _T_188 | _T_182; // @[Mux.scala 27:73]
  wire [2:0] _T_190 = _T_189 | _T_183; // @[Mux.scala 27:73]
  TLMonitor_25 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_param(monitor_io_in_d_bits_param),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source),
    .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
    .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
    .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
  );
  assign auto_in_a_ready = requestAIO_0_0 & auto_out_0_a_ready | requestAIO_0_1 & auto_out_1_a_ready | requestAIO_0_2 &
    auto_out_2_a_ready | requestAIO_0_3 & auto_out_3_a_ready | requestAIO_0_4 & auto_out_4_a_ready | requestAIO_0_5 &
    auto_out_5_a_ready | requestAIO_0_6 & auto_out_6_a_ready | requestAIO_0_7 & auto_out_7_a_ready; // @[Mux.scala 27:73]
  assign auto_in_d_valid = idle ? _T_40 : _sink_ACancel_earlyValid_T_21; // @[Arbiter.scala 125:29]
  assign auto_in_d_bits_opcode = _T_190 | _T_184; // @[Mux.scala 27:73]
  assign auto_in_d_bits_param = _T_174 | _T_168; // @[Mux.scala 27:73]
  assign auto_in_d_bits_size = _T_160 | _T_154; // @[Mux.scala 27:73]
  assign auto_in_d_bits_source = _T_145 | _T_139; // @[Mux.scala 27:73]
  assign auto_in_d_bits_sink = muxStateEarly_0 & auto_out_0_d_bits_sink | muxStateEarly_1 & auto_out_1_d_bits_sink |
    muxStateEarly_5 & auto_out_5_d_bits_sink | muxStateEarly_6 & auto_out_6_d_bits_sink; // @[Mux.scala 27:73]
  assign auto_in_d_bits_denied = muxStateEarly_0 & auto_out_0_d_bits_denied | muxStateEarly_1 & auto_out_1_d_bits_denied
     | muxStateEarly_5 & auto_out_5_d_bits_denied | muxStateEarly_6 & auto_out_6_d_bits_denied; // @[Mux.scala 27:73]
  assign auto_in_d_bits_data = _T_100 | _T_94; // @[Mux.scala 27:73]
  assign auto_in_d_bits_corrupt = muxStateEarly_0 & auto_out_0_d_bits_corrupt | muxStateEarly_1 &
    auto_out_1_d_bits_corrupt | muxStateEarly_5 & auto_out_5_d_bits_corrupt | muxStateEarly_6 &
    auto_out_6_d_bits_corrupt; // @[Mux.scala 27:73]
  assign auto_out_7_a_valid = auto_in_a_valid & requestAIO_0_7; // @[Xbar.scala 428:50]
  assign auto_out_7_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_7_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_7_a_bits_size = auto_in_a_bits_size[2:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
  assign auto_out_7_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
  assign auto_out_7_a_bits_address = auto_in_a_bits_address[16:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
  assign auto_out_7_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_7_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_7_d_ready = auto_in_d_ready & allowed_7; // @[Arbiter.scala 123:31]
  assign auto_out_6_a_valid = auto_in_a_valid & requestAIO_0_6; // @[Xbar.scala 428:50]
  assign auto_out_6_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_6_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_6_a_bits_size = auto_in_a_bits_size[2:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
  assign auto_out_6_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
  assign auto_out_6_a_bits_address = auto_in_a_bits_address[28:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
  assign auto_out_6_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_6_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_6_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_6_d_ready = auto_in_d_ready & allowed_6; // @[Arbiter.scala 123:31]
  assign auto_out_5_a_valid = auto_in_a_valid & requestAIO_0_5; // @[Xbar.scala 428:50]
  assign auto_out_5_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_5_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_5_a_bits_size = auto_in_a_bits_size[2:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
  assign auto_out_5_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
  assign auto_out_5_a_bits_address = auto_in_a_bits_address[27:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
  assign auto_out_5_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_5_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_5_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_5_d_ready = auto_in_d_ready & allowed_5; // @[Arbiter.scala 123:31]
  assign auto_out_4_a_valid = auto_in_a_valid & requestAIO_0_4; // @[Xbar.scala 428:50]
  assign auto_out_4_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_4_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_4_a_bits_size = auto_in_a_bits_size[2:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
  assign auto_out_4_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
  assign auto_out_4_a_bits_address = auto_in_a_bits_address[11:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
  assign auto_out_4_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_4_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_4_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_4_d_ready = auto_in_d_ready & allowed_4; // @[Arbiter.scala 123:31]
  assign auto_out_3_a_valid = auto_in_a_valid & requestAIO_0_3; // @[Xbar.scala 428:50]
  assign auto_out_3_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_3_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_3_a_bits_size = auto_in_a_bits_size[2:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
  assign auto_out_3_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
  assign auto_out_3_a_bits_address = auto_in_a_bits_address[25:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
  assign auto_out_3_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_3_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_3_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_3_d_ready = auto_in_d_ready & allowed_3; // @[Arbiter.scala 123:31]
  assign auto_out_2_a_valid = auto_in_a_valid & requestAIO_0_2; // @[Xbar.scala 428:50]
  assign auto_out_2_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_2_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_2_a_bits_size = auto_in_a_bits_size[2:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
  assign auto_out_2_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
  assign auto_out_2_a_bits_address = auto_in_a_bits_address[27:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
  assign auto_out_2_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_2_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_2_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_2_d_ready = auto_in_d_ready & allowed_2; // @[Arbiter.scala 123:31]
  assign auto_out_1_a_valid = auto_in_a_valid & requestAIO_0_1; // @[Xbar.scala 428:50]
  assign auto_out_1_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_a_bits_size = auto_in_a_bits_size[2:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
  assign auto_out_1_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
  assign auto_out_1_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_d_ready = auto_in_d_ready & allowed_1; // @[Arbiter.scala 123:31]
  assign auto_out_0_a_valid = auto_in_a_valid & requestAIO_0_0; // @[Xbar.scala 428:50]
  assign auto_out_0_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_0_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_0_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_0_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
  assign auto_out_0_a_bits_address = auto_in_a_bits_address[13:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
  assign auto_out_0_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_0_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_0_d_ready = auto_in_d_ready & allowed_0; // @[Arbiter.scala 123:31]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = requestAIO_0_0 & auto_out_0_a_ready | requestAIO_0_1 & auto_out_1_a_ready |
    requestAIO_0_2 & auto_out_2_a_ready | requestAIO_0_3 & auto_out_3_a_ready | requestAIO_0_4 & auto_out_4_a_ready |
    requestAIO_0_5 & auto_out_5_a_ready | requestAIO_0_6 & auto_out_6_a_ready | requestAIO_0_7 & auto_out_7_a_ready; // @[Mux.scala 27:73]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = idle ? _T_40 : _sink_ACancel_earlyValid_T_21; // @[Arbiter.scala 125:29]
  assign monitor_io_in_d_bits_opcode = _T_190 | _T_184; // @[Mux.scala 27:73]
  assign monitor_io_in_d_bits_param = _T_174 | _T_168; // @[Mux.scala 27:73]
  assign monitor_io_in_d_bits_size = _T_160 | _T_154; // @[Mux.scala 27:73]
  assign monitor_io_in_d_bits_source = _T_145 | _T_139; // @[Mux.scala 27:73]
  assign monitor_io_in_d_bits_sink = muxStateEarly_0 & auto_out_0_d_bits_sink | muxStateEarly_1 & auto_out_1_d_bits_sink
     | muxStateEarly_5 & auto_out_5_d_bits_sink | muxStateEarly_6 & auto_out_6_d_bits_sink; // @[Mux.scala 27:73]
  assign monitor_io_in_d_bits_denied = muxStateEarly_0 & auto_out_0_d_bits_denied | muxStateEarly_1 &
    auto_out_1_d_bits_denied | muxStateEarly_5 & auto_out_5_d_bits_denied | muxStateEarly_6 & auto_out_6_d_bits_denied; // @[Mux.scala 27:73]
  assign monitor_io_in_d_bits_corrupt = muxStateEarly_0 & auto_out_0_d_bits_corrupt | muxStateEarly_1 &
    auto_out_1_d_bits_corrupt | muxStateEarly_5 & auto_out_5_d_bits_corrupt | muxStateEarly_6 &
    auto_out_6_d_bits_corrupt; // @[Mux.scala 27:73]
  always @(posedge clock) begin
    if (reset) begin // @[Arbiter.scala 87:30]
      beatsLeft <= 10'h0; // @[Arbiter.scala 87:30]
    end else if (latch) begin // @[Arbiter.scala 113:23]
      beatsLeft <= initBeats;
    end else begin
      beatsLeft <= _beatsLeft_T_4;
    end
    if (reset) begin // @[Arbiter.scala 23:23]
      readys_mask <= 8'hff; // @[Arbiter.scala 23:23]
    end else if (latch & |readys_valid) begin // @[Arbiter.scala 27:32]
      readys_mask <= _readys_mask_T_9; // @[Arbiter.scala 28:12]
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_0 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_0 <= earlyWinner_0;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_1 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_1 <= earlyWinner_1;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_2 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_2 <= earlyWinner_2;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_3 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_3 <= earlyWinner_3;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_4 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_4 <= earlyWinner_4;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_5 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_5 <= earlyWinner_5;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_6 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_6 <= earlyWinner_6;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_7 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_7 <= earlyWinner_7;
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~((~earlyWinner_0 | ~earlyWinner_1) & (~prefixOR_2 | ~earlyWinner_2) & (~prefixOR_3 | ~earlyWinner_3) & (~
          prefixOR_4 | ~earlyWinner_4) & (~prefixOR_5 | ~earlyWinner_5) & (~prefixOR_6 | ~earlyWinner_6) & (~prefixOR_7
           | ~earlyWinner_7)) & _readys_T_3) begin
          $fatal; // @[Arbiter.scala 105:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_readys_T_3 & ~((~earlyWinner_0 | ~earlyWinner_1) & (~prefixOR_2 | ~earlyWinner_2) & (~prefixOR_3 | ~
          earlyWinner_3) & (~prefixOR_4 | ~earlyWinner_4) & (~prefixOR_5 | ~earlyWinner_5) & (~prefixOR_6 | ~
          earlyWinner_6) & (~prefixOR_7 | ~earlyWinner_7))) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:105 assert((prefixOR zip earlyWinner) map { case (p,w) => !p || !w } reduce {_ && _})\n"
            ); // @[Arbiter.scala 105:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(auto_out_0_d_valid | auto_out_1_d_valid | auto_out_2_d_valid | auto_out_3_d_valid | auto_out_4_d_valid
           | auto_out_5_d_valid | auto_out_6_d_valid | auto_out_7_d_valid) | _prefixOR_T) & _readys_T_3) begin
          $fatal; // @[Arbiter.scala 107:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_readys_T_3 & ~(~(auto_out_0_d_valid | auto_out_1_d_valid | auto_out_2_d_valid | auto_out_3_d_valid |
          auto_out_4_d_valid | auto_out_5_d_valid | auto_out_6_d_valid | auto_out_7_d_valid) | _prefixOR_T)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:107 assert (!earlyValids.reduce(_||_) || earlyWinner.reduce(_||_))\n"
            ); // @[Arbiter.scala 107:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_41 | _T_40) & _readys_T_3) begin
          $fatal; // @[Arbiter.scala 108:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_readys_T_3 & ~(_T_41 | _T_40)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:108 assert (!validQuals .reduce(_||_) || validQuals .reduce(_||_))\n"
            ); // @[Arbiter.scala 108:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  beatsLeft = _RAND_0[9:0];
  _RAND_1 = {1{`RANDOM}};
  readys_mask = _RAND_1[7:0];
  _RAND_2 = {1{`RANDOM}};
  state_0 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  state_1 = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  state_2 = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  state_3 = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  state_4 = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  state_5 = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  state_6 = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  state_7 = _RAND_9[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLMonitor_26(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [3:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [29:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_param,
  input  [3:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source,
  input         io_in_d_bits_sink,
  input         io_in_d_bits_denied,
  input         io_in_d_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [26:0] _is_aligned_mask_T_1 = 27'hfff << io_in_a_bits_size; // @[package.scala 234:77]
  wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1[11:0]; // @[package.scala 234:46]
  wire [29:0] _GEN_71 = {{18'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [29:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 30'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 4'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire [30:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire  _T_35 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42]
  wire  _T_42 = _T_35 & source_ok; // @[Parameters.scala 1160:30]
  wire [30:0] _T_48 = $signed(_T_7) & -31'sh10001000; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_50 = io_in_a_bits_address ^ 30'h3000; // @[Parameters.scala 137:31]
  wire [30:0] _T_51 = {1'b0,$signed(_T_50)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_53 = $signed(_T_51) & -31'sh1000; // @[Parameters.scala 137:52]
  wire  _T_54 = $signed(_T_53) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_55 = io_in_a_bits_address ^ 30'h10000; // @[Parameters.scala 137:31]
  wire [30:0] _T_56 = {1'b0,$signed(_T_55)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_58 = $signed(_T_56) & -31'sh10000; // @[Parameters.scala 137:52]
  wire  _T_59 = $signed(_T_58) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_60 = io_in_a_bits_address ^ 30'h2000000; // @[Parameters.scala 137:31]
  wire [30:0] _T_61 = {1'b0,$signed(_T_60)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_63 = $signed(_T_61) & -31'sh10000; // @[Parameters.scala 137:52]
  wire  _T_64 = $signed(_T_63) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_65 = io_in_a_bits_address ^ 30'h8000000; // @[Parameters.scala 137:31]
  wire [30:0] _T_66 = {1'b0,$signed(_T_65)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_68 = $signed(_T_66) & -31'sh4000; // @[Parameters.scala 137:52]
  wire  _T_69 = $signed(_T_68) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_70 = io_in_a_bits_address ^ 30'hc000000; // @[Parameters.scala 137:31]
  wire [30:0] _T_71 = {1'b0,$signed(_T_70)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_73 = $signed(_T_71) & -31'sh4000000; // @[Parameters.scala 137:52]
  wire  _T_74 = $signed(_T_73) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_75 = io_in_a_bits_address ^ 30'h10012000; // @[Parameters.scala 137:31]
  wire [30:0] _T_76 = {1'b0,$signed(_T_75)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_78 = $signed(_T_76) & -31'sh2000; // @[Parameters.scala 137:52]
  wire  _T_79 = $signed(_T_78) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_80 = io_in_a_bits_address ^ 30'h10014000; // @[Parameters.scala 137:31]
  wire [30:0] _T_81 = {1'b0,$signed(_T_80)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_83 = $signed(_T_81) & -31'sh2000; // @[Parameters.scala 137:52]
  wire  _T_84 = $signed(_T_83) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_85 = io_in_a_bits_address ^ 30'h10016000; // @[Parameters.scala 137:31]
  wire [30:0] _T_86 = {1'b0,$signed(_T_85)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_88 = $signed(_T_86) & -31'sh1000; // @[Parameters.scala 137:52]
  wire  _T_89 = $signed(_T_88) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_90 = io_in_a_bits_address ^ 30'h10023000; // @[Parameters.scala 137:31]
  wire [30:0] _T_91 = {1'b0,$signed(_T_90)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_93 = $signed(_T_91) & -31'sh11000; // @[Parameters.scala 137:52]
  wire  _T_94 = $signed(_T_93) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_95 = io_in_a_bits_address ^ 30'h10024000; // @[Parameters.scala 137:31]
  wire [30:0] _T_96 = {1'b0,$signed(_T_95)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_98 = $signed(_T_96) & -31'sh12000; // @[Parameters.scala 137:52]
  wire  _T_99 = $signed(_T_98) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_100 = io_in_a_bits_address ^ 30'h10026000; // @[Parameters.scala 137:31]
  wire [30:0] _T_101 = {1'b0,$signed(_T_100)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_103 = $signed(_T_101) & -31'sh1000; // @[Parameters.scala 137:52]
  wire  _T_104 = $signed(_T_103) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_105 = io_in_a_bits_address ^ 30'h10043000; // @[Parameters.scala 137:31]
  wire [30:0] _T_106 = {1'b0,$signed(_T_105)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_108 = $signed(_T_106) & -31'sh11000; // @[Parameters.scala 137:52]
  wire  _T_109 = $signed(_T_108) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_110 = io_in_a_bits_address ^ 30'h20000000; // @[Parameters.scala 137:31]
  wire [30:0] _T_111 = {1'b0,$signed(_T_110)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_113 = $signed(_T_111) & -31'sh20000000; // @[Parameters.scala 137:52]
  wire  _T_114 = $signed(_T_113) == 31'sh0; // @[Parameters.scala 137:67]
  wire  _T_127 = _T_49 | _T_54 | _T_59 | _T_64 | _T_69 | _T_74 | _T_79 | _T_84 | _T_89 | _T_94 | _T_99 | _T_104 | _T_109
     | _T_114; // @[Parameters.scala 671:42]
  wire  _T_137 = 4'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_138 = _source_ok_T & _T_137; // @[Mux.scala 27:73]
  wire  _T_230 = _T_35 & _T_127; // @[Parameters.scala 670:56]
  wire  _T_232 = _T_138 & _T_230; // @[Monitor.scala 83:78]
  wire  _T_246 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_250 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_251 = _T_250 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_255 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_259 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_476 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_489 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_512 = _T_35 & _T_54; // @[Parameters.scala 670:56]
  wire  _T_514 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42]
  wire  _T_593 = _T_49 | _T_59 | _T_64 | _T_69 | _T_74 | _T_79 | _T_84 | _T_89 | _T_94 | _T_99 | _T_104 | _T_109 |
    _T_114; // @[Parameters.scala 671:42]
  wire  _T_594 = _T_514 & _T_593; // @[Parameters.scala 670:56]
  wire  _T_596 = _T_512 | _T_594; // @[Parameters.scala 672:30]
  wire  _T_606 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_610 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_618 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_707 = _T_49 | _T_64 | _T_69 | _T_74 | _T_79 | _T_84 | _T_89 | _T_94 | _T_99 | _T_104 | _T_109; // @[Parameters.scala 671:42]
  wire  _T_708 = _T_514 & _T_707; // @[Parameters.scala 670:56]
  wire  _T_723 = _T_512 | _T_708; // @[Parameters.scala 672:30]
  wire  _T_725 = _T_42 & _T_723; // @[Monitor.scala 115:71]
  wire  _T_743 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_864 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_865 = io_in_a_bits_mask & _T_864; // @[Monitor.scala 127:31]
  wire  _T_866 = _T_865 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_870 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_882 = io_in_a_bits_size <= 4'h2; // @[Parameters.scala 92:42]
  wire  _T_931 = _T_54 | _T_79 | _T_84 | _T_89 | _T_94 | _T_99 | _T_104 | _T_109; // @[Parameters.scala 671:42]
  wire  _T_932 = _T_882 & _T_931; // @[Parameters.scala 670:56]
  wire  _T_972 = _T_42 & _T_932; // @[Monitor.scala 131:74]
  wire  _T_982 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_990 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_1102 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_1110 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_1212 = _T_42 & _T_512; // @[Monitor.scala 147:68]
  wire  _T_1222 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_1234 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  _T_1238 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_1242 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 312:27]
  wire  _T_1246 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
  wire  _T_1250 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
  wire  _T_1254 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
  wire  _T_1258 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_1269 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
  wire  _T_1273 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
  wire  _T_1286 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_1306 = _T_1254 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
  wire  _T_1315 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_1332 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_1350 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [9:0] a_first_beats1_decode = is_aligned_mask[11:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [9:0] a_first_counter; // @[Edges.scala 228:27]
  wire [9:0] a_first_counter1 = a_first_counter - 10'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 10'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [3:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [29:0] address; // @[Monitor.scala 388:22]
  wire  _T_1380 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_1381 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_1385 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_1389 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_1393 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_1397 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [26:0] _d_first_beats1_decode_T_1 = 27'hfff << io_in_d_bits_size; // @[package.scala 234:77]
  wire [11:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
  wire [9:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[11:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [9:0] d_first_counter; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1 = d_first_counter - 10'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 10'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] param_1; // @[Monitor.scala 536:22]
  reg [3:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  reg  sink; // @[Monitor.scala 539:22]
  reg  denied; // @[Monitor.scala 540:22]
  wire  _T_1404 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_1405 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_1409 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
  wire  _T_1413 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_1417 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  wire  _T_1421 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
  wire  _T_1425 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [23:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [9:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [9:0] a_first_counter1_1 = a_first_counter_1 - 10'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 10'h0; // @[Edges.scala 230:25]
  reg [9:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1_1 = d_first_counter_1 - 10'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 10'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [4:0] _a_size_lookup_T = {io_in_d_bits_source, 3'h0}; // @[Monitor.scala 638:65]
  wire [23:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _a_size_lookup_T_5 = 16'h100 - 16'h1; // @[Monitor.scala 609:57]
  wire [23:0] _GEN_75 = {{8'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 638:91]
  wire [23:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_75; // @[Monitor.scala 638:91]
  wire [23:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[23:1]}; // @[Monitor.scala 638:144]
  wire  _T_1431 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_1434 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [4:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 5'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_77 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_77}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [4:0] _a_sizes_set_T = {io_in_a_bits_source, 3'h0}; // @[Monitor.scala 657:77]
  wire [4:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala 652:72 655:28]
  wire [35:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [35:0] _a_sizes_set_T_1 = _GEN_2 << _a_sizes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_1436 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_1438 = ~_T_1436[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [35:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 36'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_1442 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_1444 = ~_T_1238; // @[Monitor.scala 671:74]
  wire  _T_1445 = io_in_d_valid & d_first_1 & ~_T_1238; // @[Monitor.scala 671:71]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_1238 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 671:90 672:22]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [46:0] _GEN_4 = {{31'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 678:74]
  wire [46:0] _d_sizes_clr_T_5 = _GEN_4 << _a_size_lookup_T; // @[Monitor.scala 678:74]
  wire [3:0] _GEN_22 = _d_first_T & d_first_1 & _T_1444 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_23 = _d_first_T & d_first_1 & _T_1444 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire [46:0] _GEN_24 = _d_first_T & d_first_1 & _T_1444 ? _d_sizes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 678:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_1431 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_1455 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_1457 = _T_1455[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_1462 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_1463 = io_in_d_bits_opcode == _GEN_32 | _T_1462; // @[Monitor.scala 685:77]
  wire  _T_1467 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_1474 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_1475 = io_in_d_bits_opcode == _GEN_48 | _T_1474; // @[Monitor.scala 689:72]
  wire [7:0] a_size_lookup = _a_size_lookup_T_7[7:0];
  wire [7:0] _GEN_79 = {{4'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_1479 = _GEN_79 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_1489 = _T_1442 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_1444; // @[Monitor.scala 694:116]
  wire  _T_1491 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set_wo_ready = _GEN_15[2:0];
  wire [2:0] d_clr_wo_ready = _GEN_21[2:0];
  wire  _T_1498 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire [2:0] a_set = _GEN_16[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_22[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_19[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_23[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [23:0] a_sizes_set = _GEN_20[23:0];
  wire [23:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [23:0] d_sizes_clr = _GEN_24[23:0];
  wire [23:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala 704:56]
  wire [23:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_1507 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [2:0] inflight_1; // @[Monitor.scala 723:35]
  reg [23:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [9:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1_2 = d_first_counter_2 - 10'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 10'h0; // @[Edges.scala 230:25]
  wire [23:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_size_lookup_T; // @[Monitor.scala 747:42]
  wire [23:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_75; // @[Monitor.scala 747:93]
  wire [23:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[23:1]}; // @[Monitor.scala 747:146]
  wire  _T_1533 = io_in_d_valid & d_first_2 & _T_1238; // @[Monitor.scala 779:71]
  wire [3:0] _GEN_67 = _d_first_T & d_first_2 & _T_1238 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 783:90 784:21]
  wire [46:0] _GEN_69 = _d_first_T & d_first_2 & _T_1238 ? _d_sizes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 786:21]
  wire [2:0] _T_1541 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [7:0] c_size_lookup = _c_size_lookup_T_7[7:0];
  wire  _T_1551 = _GEN_79 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [2:0] d_clr_1 = _GEN_67[2:0];
  wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [2:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [23:0] d_sizes_clr_1 = _GEN_69[23:0];
  wire [23:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
  wire [23:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_1576 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 10'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 10'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 10'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 24'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 10'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 10'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 3'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 24'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 10'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_232 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_232) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_246 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_246) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_251 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_251) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_255 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_255) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_232 & (io_in_a_valid & _T_259 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset & ~_T_232) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_259 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_259 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_259 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_246 & (io_in_a_valid & _T_259 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset & ~_T_246) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_476 & (io_in_a_valid & _T_259 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset & ~_T_476) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_251 & (io_in_a_valid & _T_259 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset & ~_T_251) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_255 & (io_in_a_valid & _T_259 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset & ~_T_255) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_42 & (io_in_a_valid & _T_489 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_489 & ~reset & ~_T_42) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_596 & (io_in_a_valid & _T_489 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_489 & ~reset & ~_T_596) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_489 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_489 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_489 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_489 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_606 & (io_in_a_valid & _T_489 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_489 & ~reset & ~_T_606) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_610 & (io_in_a_valid & _T_489 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_489 & ~reset & ~_T_610) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_255 & (io_in_a_valid & _T_489 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_489 & ~reset & ~_T_255) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_725 & (io_in_a_valid & _T_618 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_618 & ~reset & ~_T_725) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_618 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_618 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_618 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_618 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_606 & (io_in_a_valid & _T_618 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_618 & ~reset & ~_T_606) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_610 & (io_in_a_valid & _T_618 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_618 & ~reset & ~_T_610) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_725 & (io_in_a_valid & _T_743 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_743 & ~reset & ~_T_725) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_743 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_743 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_743 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_743 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_606 & (io_in_a_valid & _T_743 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_743 & ~reset & ~_T_606) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_866 & (io_in_a_valid & _T_743 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_743 & ~reset & ~_T_866) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_972 & (io_in_a_valid & _T_870 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_870 & ~reset & ~_T_972) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_870 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_870 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_870 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_870 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_982 & (io_in_a_valid & _T_870 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_870 & ~reset & ~_T_982) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_610 & (io_in_a_valid & _T_870 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_870 & ~reset & ~_T_610) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_972 & (io_in_a_valid & _T_990 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_990 & ~reset & ~_T_972) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_990 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_990 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_990 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_990 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1102 & (io_in_a_valid & _T_990 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_990 & ~reset & ~_T_1102) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_610 & (io_in_a_valid & _T_990 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_990 & ~reset & ~_T_610) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1212 & (io_in_a_valid & _T_1110 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1110 & ~reset & ~_T_1212) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_1110 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1110 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_1110 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1110 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1222 & (io_in_a_valid & _T_1110 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1110 & ~reset & ~_T_1222) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_610 & (io_in_a_valid & _T_1110 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1110 & ~reset & ~_T_610) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_255 & (io_in_a_valid & _T_1110 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1110 & ~reset & ~_T_255) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1234 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_1234) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1238 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1238 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1242 & (io_in_d_valid & _T_1238 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1238 & _T_2 & ~_T_1242) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1246 & (io_in_d_valid & _T_1238 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1238 & _T_2 & ~_T_1246) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1250 & (io_in_d_valid & _T_1238 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1238 & _T_2 & ~_T_1250) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1254 & (io_in_d_valid & _T_1238 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1238 & _T_2 & ~_T_1254) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is denied (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1258 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1258 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_1258 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1258 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1242 & (io_in_d_valid & _T_1258 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1258 & _T_2 & ~_T_1242) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1269 & (io_in_d_valid & _T_1258 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1258 & _T_2 & ~_T_1269) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid cap param (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1273 & (io_in_d_valid & _T_1258 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1258 & _T_2 & ~_T_1273) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries toN param (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1250 & (io_in_d_valid & _T_1258 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1258 & _T_2 & ~_T_1250) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is corrupt (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1286 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1286 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_1286 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1286 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1242 & (io_in_d_valid & _T_1286 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1286 & _T_2 & ~_T_1242) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1269 & (io_in_d_valid & _T_1286 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1286 & _T_2 & ~_T_1269) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1273 & (io_in_d_valid & _T_1286 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1286 & _T_2 & ~_T_1273) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries toN param (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1306 & (io_in_d_valid & _T_1286 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1286 & _T_2 & ~_T_1306) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1315 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1315 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1246 & (io_in_d_valid & _T_1315 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1315 & _T_2 & ~_T_1246) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid param (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1250 & (io_in_d_valid & _T_1315 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1315 & _T_2 & ~_T_1250) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is corrupt (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1332 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1332 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1246 & (io_in_d_valid & _T_1332 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1332 & _T_2 & ~_T_1246) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1306 & (io_in_d_valid & _T_1332 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1332 & _T_2 & ~_T_1306) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1350 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1350 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1246 & (io_in_d_valid & _T_1350 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1350 & _T_2 & ~_T_1246) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid param (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1250 & (io_in_d_valid & _T_1350 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1350 & _T_2 & ~_T_1250) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is corrupt (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1381 & (_T_1380 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1380 & ~reset & ~_T_1381) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1385 & (_T_1380 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1380 & ~reset & ~_T_1385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1389 & (_T_1380 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1380 & ~reset & ~_T_1389) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1393 & (_T_1380 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1380 & ~reset & ~_T_1393) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1397 & (_T_1380 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1380 & ~reset & ~_T_1397) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1405 & (_T_1404 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1404 & _T_2 & ~_T_1405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1409 & (_T_1404 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1404 & _T_2 & ~_T_1409) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel param changed within multibeat operation (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1413 & (_T_1404 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1404 & _T_2 & ~_T_1413) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1417 & (_T_1404 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1404 & _T_2 & ~_T_1417) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1421 & (_T_1404 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1404 & _T_2 & ~_T_1421) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel sink changed with multibeat operation (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1425 & (_T_1404 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1404 & _T_2 & ~_T_1425) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel denied changed with multibeat operation (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1438 & (_T_1434 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1434 & ~reset & ~_T_1438) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1457 & (_T_1445 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1445 & _T_2 & ~_T_1457) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1463 & (_T_1445 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1445 & same_cycle_resp & _T_2 & ~_T_1463) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1467 & (_T_1445 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1445 & same_cycle_resp & _T_2 & ~_T_1467) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1475 & (_T_1445 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1445 & ~same_cycle_resp & _T_2 & ~_T_1475) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1479 & (_T_1445 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1445 & ~same_cycle_resp & _T_2 & ~_T_1479) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1491 & (_T_1489 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1489 & _T_2 & ~_T_1491) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1498 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_1498) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1507 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_1507) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1541[0] & (_T_1533 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1533 & _T_2 & ~_T_1541[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1551 & (_T_1533 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1533 & _T_2 & ~_T_1551) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1576 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_1576) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:55:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[9:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[29:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[9:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  param_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  size_1 = _RAND_9[3:0];
  _RAND_10 = {1{`RANDOM}};
  source_1 = _RAND_10[1:0];
  _RAND_11 = {1{`RANDOM}};
  sink = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  denied = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  inflight = _RAND_13[2:0];
  _RAND_14 = {1{`RANDOM}};
  inflight_opcodes = _RAND_14[11:0];
  _RAND_15 = {1{`RANDOM}};
  inflight_sizes = _RAND_15[23:0];
  _RAND_16 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_16[9:0];
  _RAND_17 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_17[9:0];
  _RAND_18 = {1{`RANDOM}};
  watchdog = _RAND_18[31:0];
  _RAND_19 = {1{`RANDOM}};
  inflight_1 = _RAND_19[2:0];
  _RAND_20 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_20[23:0];
  _RAND_21 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_21[9:0];
  _RAND_22 = {1{`RANDOM}};
  watchdog_1 = _RAND_22[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_5(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [2:0]  io_enq_bits_opcode,
  input  [2:0]  io_enq_bits_param,
  input  [3:0]  io_enq_bits_size,
  input  [1:0]  io_enq_bits_source,
  input  [29:0] io_enq_bits_address,
  input  [3:0]  io_enq_bits_mask,
  input  [31:0] io_enq_bits_data,
  input         io_enq_bits_corrupt,
  input         io_deq_ready,
  output        io_deq_valid,
  output [2:0]  io_deq_bits_opcode,
  output [2:0]  io_deq_bits_param,
  output [3:0]  io_deq_bits_size,
  output [1:0]  io_deq_bits_source,
  output [29:0] io_deq_bits_address,
  output [3:0]  io_deq_bits_mask,
  output [31:0] io_deq_bits_data,
  output        io_deq_bits_corrupt
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
`endif // RANDOMIZE_REG_INIT
  reg [2:0] ram_opcode [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_opcode_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_opcode_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [2:0] ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_en; // @[Decoupled.scala 259:95]
  reg [2:0] ram_param [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_param_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_param_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [2:0] ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_param_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_param_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_param_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_param_MPORT_en; // @[Decoupled.scala 259:95]
  reg [3:0] ram_size [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [3:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [3:0] ram_size_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_en; // @[Decoupled.scala 259:95]
  reg [1:0] ram_source [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [1:0] ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [1:0] ram_source_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_en; // @[Decoupled.scala 259:95]
  reg [29:0] ram_address [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_address_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_address_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [29:0] ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [29:0] ram_address_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_address_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_address_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_address_MPORT_en; // @[Decoupled.scala 259:95]
  reg [3:0] ram_mask [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_mask_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_mask_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [3:0] ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [3:0] ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_mask_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_mask_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_mask_MPORT_en; // @[Decoupled.scala 259:95]
  reg [31:0] ram_data [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_data_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_data_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [31:0] ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [31:0] ram_data_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_data_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_data_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_data_MPORT_en; // @[Decoupled.scala 259:95]
  reg  ram_corrupt [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_en; // @[Decoupled.scala 259:95]
  reg  value; // @[Counter.scala 62:40]
  reg  value_1; // @[Counter.scala 62:40]
  reg  maybe_full; // @[Decoupled.scala 262:27]
  wire  ptr_match = value == value_1; // @[Decoupled.scala 263:33]
  wire  empty = ptr_match & ~maybe_full; // @[Decoupled.scala 264:25]
  wire  full = ptr_match & maybe_full; // @[Decoupled.scala 265:24]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
  wire  do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
  assign ram_opcode_io_deq_bits_MPORT_en = 1'h1;
  assign ram_opcode_io_deq_bits_MPORT_addr = value_1;
  assign ram_opcode_io_deq_bits_MPORT_data = ram_opcode[ram_opcode_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_opcode_MPORT_data = io_enq_bits_opcode;
  assign ram_opcode_MPORT_addr = value;
  assign ram_opcode_MPORT_mask = 1'h1;
  assign ram_opcode_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_param_io_deq_bits_MPORT_en = 1'h1;
  assign ram_param_io_deq_bits_MPORT_addr = value_1;
  assign ram_param_io_deq_bits_MPORT_data = ram_param[ram_param_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_param_MPORT_data = io_enq_bits_param;
  assign ram_param_MPORT_addr = value;
  assign ram_param_MPORT_mask = 1'h1;
  assign ram_param_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_size_io_deq_bits_MPORT_en = 1'h1;
  assign ram_size_io_deq_bits_MPORT_addr = value_1;
  assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_size_MPORT_data = io_enq_bits_size;
  assign ram_size_MPORT_addr = value;
  assign ram_size_MPORT_mask = 1'h1;
  assign ram_size_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_source_io_deq_bits_MPORT_en = 1'h1;
  assign ram_source_io_deq_bits_MPORT_addr = value_1;
  assign ram_source_io_deq_bits_MPORT_data = ram_source[ram_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_source_MPORT_data = io_enq_bits_source;
  assign ram_source_MPORT_addr = value;
  assign ram_source_MPORT_mask = 1'h1;
  assign ram_source_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_address_io_deq_bits_MPORT_en = 1'h1;
  assign ram_address_io_deq_bits_MPORT_addr = value_1;
  assign ram_address_io_deq_bits_MPORT_data = ram_address[ram_address_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_address_MPORT_data = io_enq_bits_address;
  assign ram_address_MPORT_addr = value;
  assign ram_address_MPORT_mask = 1'h1;
  assign ram_address_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_mask_io_deq_bits_MPORT_en = 1'h1;
  assign ram_mask_io_deq_bits_MPORT_addr = value_1;
  assign ram_mask_io_deq_bits_MPORT_data = ram_mask[ram_mask_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_mask_MPORT_data = io_enq_bits_mask;
  assign ram_mask_MPORT_addr = value;
  assign ram_mask_MPORT_mask = 1'h1;
  assign ram_mask_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_data_io_deq_bits_MPORT_en = 1'h1;
  assign ram_data_io_deq_bits_MPORT_addr = value_1;
  assign ram_data_io_deq_bits_MPORT_data = ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_data_MPORT_data = io_enq_bits_data;
  assign ram_data_MPORT_addr = value;
  assign ram_data_MPORT_mask = 1'h1;
  assign ram_data_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_corrupt_io_deq_bits_MPORT_en = 1'h1;
  assign ram_corrupt_io_deq_bits_MPORT_addr = value_1;
  assign ram_corrupt_io_deq_bits_MPORT_data = ram_corrupt[ram_corrupt_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_corrupt_MPORT_data = io_enq_bits_corrupt;
  assign ram_corrupt_MPORT_addr = value;
  assign ram_corrupt_MPORT_mask = 1'h1;
  assign ram_corrupt_MPORT_en = io_enq_ready & io_enq_valid;
  assign io_enq_ready = ~full; // @[Decoupled.scala 289:19]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 288:19]
  assign io_deq_bits_opcode = ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_param = ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_size = ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_source = ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_address = ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_mask = ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_data = ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_corrupt = ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  always @(posedge clock) begin
    if (ram_opcode_MPORT_en & ram_opcode_MPORT_mask) begin
      ram_opcode[ram_opcode_MPORT_addr] <= ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_param_MPORT_en & ram_param_MPORT_mask) begin
      ram_param[ram_param_MPORT_addr] <= ram_param_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
      ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_source_MPORT_en & ram_source_MPORT_mask) begin
      ram_source[ram_source_MPORT_addr] <= ram_source_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_address_MPORT_en & ram_address_MPORT_mask) begin
      ram_address[ram_address_MPORT_addr] <= ram_address_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_mask_MPORT_en & ram_mask_MPORT_mask) begin
      ram_mask[ram_mask_MPORT_addr] <= ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_data_MPORT_en & ram_data_MPORT_mask) begin
      ram_data[ram_data_MPORT_addr] <= ram_data_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_corrupt_MPORT_en & ram_corrupt_MPORT_mask) begin
      ram_corrupt[ram_corrupt_MPORT_addr] <= ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (reset) begin // @[Counter.scala 62:40]
      value <= 1'h0; // @[Counter.scala 62:40]
    end else if (do_enq) begin // @[Decoupled.scala 272:16]
      value <= value + 1'h1; // @[Counter.scala 78:15]
    end
    if (reset) begin // @[Counter.scala 62:40]
      value_1 <= 1'h0; // @[Counter.scala 62:40]
    end else if (do_deq) begin // @[Decoupled.scala 276:16]
      value_1 <= value_1 + 1'h1; // @[Counter.scala 78:15]
    end
    if (reset) begin // @[Decoupled.scala 262:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 262:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 279:27]
      maybe_full <= do_enq; // @[Decoupled.scala 280:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_opcode[initvar] = _RAND_0[2:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_param[initvar] = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_size[initvar] = _RAND_2[3:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_source[initvar] = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_address[initvar] = _RAND_4[29:0];
  _RAND_5 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_mask[initvar] = _RAND_5[3:0];
  _RAND_6 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_data[initvar] = _RAND_6[31:0];
  _RAND_7 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_corrupt[initvar] = _RAND_7[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_8 = {1{`RANDOM}};
  value = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  value_1 = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  maybe_full = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_6(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [2:0]  io_enq_bits_opcode,
  input  [1:0]  io_enq_bits_param,
  input  [3:0]  io_enq_bits_size,
  input  [1:0]  io_enq_bits_source,
  input         io_enq_bits_sink,
  input         io_enq_bits_denied,
  input  [31:0] io_enq_bits_data,
  input         io_enq_bits_corrupt,
  input         io_deq_ready,
  output        io_deq_valid,
  output [2:0]  io_deq_bits_opcode,
  output [1:0]  io_deq_bits_param,
  output [3:0]  io_deq_bits_size,
  output [1:0]  io_deq_bits_source,
  output        io_deq_bits_sink,
  output        io_deq_bits_denied,
  output [31:0] io_deq_bits_data,
  output        io_deq_bits_corrupt
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
`endif // RANDOMIZE_REG_INIT
  reg [2:0] ram_opcode [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_opcode_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_opcode_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [2:0] ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_en; // @[Decoupled.scala 259:95]
  reg [1:0] ram_param [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_param_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_param_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [1:0] ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [1:0] ram_param_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_param_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_param_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_param_MPORT_en; // @[Decoupled.scala 259:95]
  reg [3:0] ram_size [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [3:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [3:0] ram_size_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_en; // @[Decoupled.scala 259:95]
  reg [1:0] ram_source [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [1:0] ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [1:0] ram_source_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_en; // @[Decoupled.scala 259:95]
  reg  ram_sink [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_sink_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_sink_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_sink_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_sink_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_sink_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_sink_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_sink_MPORT_en; // @[Decoupled.scala 259:95]
  reg  ram_denied [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_denied_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_denied_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_denied_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_denied_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_denied_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_denied_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_denied_MPORT_en; // @[Decoupled.scala 259:95]
  reg [31:0] ram_data [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_data_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_data_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [31:0] ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [31:0] ram_data_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_data_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_data_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_data_MPORT_en; // @[Decoupled.scala 259:95]
  reg  ram_corrupt [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_en; // @[Decoupled.scala 259:95]
  reg  value; // @[Counter.scala 62:40]
  reg  value_1; // @[Counter.scala 62:40]
  reg  maybe_full; // @[Decoupled.scala 262:27]
  wire  ptr_match = value == value_1; // @[Decoupled.scala 263:33]
  wire  empty = ptr_match & ~maybe_full; // @[Decoupled.scala 264:25]
  wire  full = ptr_match & maybe_full; // @[Decoupled.scala 265:24]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
  wire  do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
  assign ram_opcode_io_deq_bits_MPORT_en = 1'h1;
  assign ram_opcode_io_deq_bits_MPORT_addr = value_1;
  assign ram_opcode_io_deq_bits_MPORT_data = ram_opcode[ram_opcode_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_opcode_MPORT_data = io_enq_bits_opcode;
  assign ram_opcode_MPORT_addr = value;
  assign ram_opcode_MPORT_mask = 1'h1;
  assign ram_opcode_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_param_io_deq_bits_MPORT_en = 1'h1;
  assign ram_param_io_deq_bits_MPORT_addr = value_1;
  assign ram_param_io_deq_bits_MPORT_data = ram_param[ram_param_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_param_MPORT_data = io_enq_bits_param;
  assign ram_param_MPORT_addr = value;
  assign ram_param_MPORT_mask = 1'h1;
  assign ram_param_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_size_io_deq_bits_MPORT_en = 1'h1;
  assign ram_size_io_deq_bits_MPORT_addr = value_1;
  assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_size_MPORT_data = io_enq_bits_size;
  assign ram_size_MPORT_addr = value;
  assign ram_size_MPORT_mask = 1'h1;
  assign ram_size_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_source_io_deq_bits_MPORT_en = 1'h1;
  assign ram_source_io_deq_bits_MPORT_addr = value_1;
  assign ram_source_io_deq_bits_MPORT_data = ram_source[ram_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_source_MPORT_data = io_enq_bits_source;
  assign ram_source_MPORT_addr = value;
  assign ram_source_MPORT_mask = 1'h1;
  assign ram_source_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_sink_io_deq_bits_MPORT_en = 1'h1;
  assign ram_sink_io_deq_bits_MPORT_addr = value_1;
  assign ram_sink_io_deq_bits_MPORT_data = ram_sink[ram_sink_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_sink_MPORT_data = io_enq_bits_sink;
  assign ram_sink_MPORT_addr = value;
  assign ram_sink_MPORT_mask = 1'h1;
  assign ram_sink_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_denied_io_deq_bits_MPORT_en = 1'h1;
  assign ram_denied_io_deq_bits_MPORT_addr = value_1;
  assign ram_denied_io_deq_bits_MPORT_data = ram_denied[ram_denied_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_denied_MPORT_data = io_enq_bits_denied;
  assign ram_denied_MPORT_addr = value;
  assign ram_denied_MPORT_mask = 1'h1;
  assign ram_denied_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_data_io_deq_bits_MPORT_en = 1'h1;
  assign ram_data_io_deq_bits_MPORT_addr = value_1;
  assign ram_data_io_deq_bits_MPORT_data = ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_data_MPORT_data = io_enq_bits_data;
  assign ram_data_MPORT_addr = value;
  assign ram_data_MPORT_mask = 1'h1;
  assign ram_data_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_corrupt_io_deq_bits_MPORT_en = 1'h1;
  assign ram_corrupt_io_deq_bits_MPORT_addr = value_1;
  assign ram_corrupt_io_deq_bits_MPORT_data = ram_corrupt[ram_corrupt_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_corrupt_MPORT_data = io_enq_bits_corrupt;
  assign ram_corrupt_MPORT_addr = value;
  assign ram_corrupt_MPORT_mask = 1'h1;
  assign ram_corrupt_MPORT_en = io_enq_ready & io_enq_valid;
  assign io_enq_ready = ~full; // @[Decoupled.scala 289:19]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 288:19]
  assign io_deq_bits_opcode = ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_param = ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_size = ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_source = ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_sink = ram_sink_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_denied = ram_denied_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_data = ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_corrupt = ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  always @(posedge clock) begin
    if (ram_opcode_MPORT_en & ram_opcode_MPORT_mask) begin
      ram_opcode[ram_opcode_MPORT_addr] <= ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_param_MPORT_en & ram_param_MPORT_mask) begin
      ram_param[ram_param_MPORT_addr] <= ram_param_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
      ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_source_MPORT_en & ram_source_MPORT_mask) begin
      ram_source[ram_source_MPORT_addr] <= ram_source_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_sink_MPORT_en & ram_sink_MPORT_mask) begin
      ram_sink[ram_sink_MPORT_addr] <= ram_sink_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_denied_MPORT_en & ram_denied_MPORT_mask) begin
      ram_denied[ram_denied_MPORT_addr] <= ram_denied_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_data_MPORT_en & ram_data_MPORT_mask) begin
      ram_data[ram_data_MPORT_addr] <= ram_data_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_corrupt_MPORT_en & ram_corrupt_MPORT_mask) begin
      ram_corrupt[ram_corrupt_MPORT_addr] <= ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (reset) begin // @[Counter.scala 62:40]
      value <= 1'h0; // @[Counter.scala 62:40]
    end else if (do_enq) begin // @[Decoupled.scala 272:16]
      value <= value + 1'h1; // @[Counter.scala 78:15]
    end
    if (reset) begin // @[Counter.scala 62:40]
      value_1 <= 1'h0; // @[Counter.scala 62:40]
    end else if (do_deq) begin // @[Decoupled.scala 276:16]
      value_1 <= value_1 + 1'h1; // @[Counter.scala 78:15]
    end
    if (reset) begin // @[Decoupled.scala 262:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 262:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 279:27]
      maybe_full <= do_enq; // @[Decoupled.scala 280:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_opcode[initvar] = _RAND_0[2:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_param[initvar] = _RAND_1[1:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_size[initvar] = _RAND_2[3:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_source[initvar] = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_sink[initvar] = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_denied[initvar] = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_data[initvar] = _RAND_6[31:0];
  _RAND_7 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_corrupt[initvar] = _RAND_7[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_8 = {1{`RANDOM}};
  value = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  value_1 = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  maybe_full = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLBuffer_4(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [3:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [29:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [1:0]  auto_in_d_bits_param,
  output [3:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output        auto_in_d_bits_sink,
  output        auto_in_d_bits_denied,
  output [31:0] auto_in_d_bits_data,
  output        auto_in_d_bits_corrupt,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [3:0]  auto_out_a_bits_size,
  output [1:0]  auto_out_a_bits_source,
  output [29:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_param,
  input  [3:0]  auto_out_d_bits_size,
  input  [1:0]  auto_out_d_bits_source,
  input         auto_out_d_bits_sink,
  input         auto_out_d_bits_denied,
  input  [31:0] auto_out_d_bits_data,
  input         auto_out_d_bits_corrupt
);
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [29:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
  wire  bundleOut_0_a_q_clock; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_reset; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_enq_ready; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_enq_valid; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
  wire [3:0] bundleOut_0_a_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
  wire [1:0] bundleOut_0_a_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
  wire [29:0] bundleOut_0_a_q_io_enq_bits_address; // @[Decoupled.scala 361:21]
  wire [3:0] bundleOut_0_a_q_io_enq_bits_mask; // @[Decoupled.scala 361:21]
  wire [31:0] bundleOut_0_a_q_io_enq_bits_data; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_enq_bits_corrupt; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_deq_ready; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_deq_valid; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
  wire [3:0] bundleOut_0_a_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
  wire [1:0] bundleOut_0_a_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
  wire [29:0] bundleOut_0_a_q_io_deq_bits_address; // @[Decoupled.scala 361:21]
  wire [3:0] bundleOut_0_a_q_io_deq_bits_mask; // @[Decoupled.scala 361:21]
  wire [31:0] bundleOut_0_a_q_io_deq_bits_data; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_clock; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_reset; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_enq_ready; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_enq_valid; // @[Decoupled.scala 361:21]
  wire [2:0] bundleIn_0_d_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
  wire [1:0] bundleIn_0_d_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
  wire [3:0] bundleIn_0_d_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
  wire [1:0] bundleIn_0_d_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_enq_bits_sink; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_enq_bits_denied; // @[Decoupled.scala 361:21]
  wire [31:0] bundleIn_0_d_q_io_enq_bits_data; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_enq_bits_corrupt; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_deq_ready; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_deq_valid; // @[Decoupled.scala 361:21]
  wire [2:0] bundleIn_0_d_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
  wire [1:0] bundleIn_0_d_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
  wire [3:0] bundleIn_0_d_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
  wire [1:0] bundleIn_0_d_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_deq_bits_sink; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_deq_bits_denied; // @[Decoupled.scala 361:21]
  wire [31:0] bundleIn_0_d_q_io_deq_bits_data; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
  TLMonitor_26 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_param(monitor_io_in_d_bits_param),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source),
    .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
    .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
    .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
  );
  Queue_5 bundleOut_0_a_q ( // @[Decoupled.scala 361:21]
    .clock(bundleOut_0_a_q_clock),
    .reset(bundleOut_0_a_q_reset),
    .io_enq_ready(bundleOut_0_a_q_io_enq_ready),
    .io_enq_valid(bundleOut_0_a_q_io_enq_valid),
    .io_enq_bits_opcode(bundleOut_0_a_q_io_enq_bits_opcode),
    .io_enq_bits_param(bundleOut_0_a_q_io_enq_bits_param),
    .io_enq_bits_size(bundleOut_0_a_q_io_enq_bits_size),
    .io_enq_bits_source(bundleOut_0_a_q_io_enq_bits_source),
    .io_enq_bits_address(bundleOut_0_a_q_io_enq_bits_address),
    .io_enq_bits_mask(bundleOut_0_a_q_io_enq_bits_mask),
    .io_enq_bits_data(bundleOut_0_a_q_io_enq_bits_data),
    .io_enq_bits_corrupt(bundleOut_0_a_q_io_enq_bits_corrupt),
    .io_deq_ready(bundleOut_0_a_q_io_deq_ready),
    .io_deq_valid(bundleOut_0_a_q_io_deq_valid),
    .io_deq_bits_opcode(bundleOut_0_a_q_io_deq_bits_opcode),
    .io_deq_bits_param(bundleOut_0_a_q_io_deq_bits_param),
    .io_deq_bits_size(bundleOut_0_a_q_io_deq_bits_size),
    .io_deq_bits_source(bundleOut_0_a_q_io_deq_bits_source),
    .io_deq_bits_address(bundleOut_0_a_q_io_deq_bits_address),
    .io_deq_bits_mask(bundleOut_0_a_q_io_deq_bits_mask),
    .io_deq_bits_data(bundleOut_0_a_q_io_deq_bits_data),
    .io_deq_bits_corrupt(bundleOut_0_a_q_io_deq_bits_corrupt)
  );
  Queue_6 bundleIn_0_d_q ( // @[Decoupled.scala 361:21]
    .clock(bundleIn_0_d_q_clock),
    .reset(bundleIn_0_d_q_reset),
    .io_enq_ready(bundleIn_0_d_q_io_enq_ready),
    .io_enq_valid(bundleIn_0_d_q_io_enq_valid),
    .io_enq_bits_opcode(bundleIn_0_d_q_io_enq_bits_opcode),
    .io_enq_bits_param(bundleIn_0_d_q_io_enq_bits_param),
    .io_enq_bits_size(bundleIn_0_d_q_io_enq_bits_size),
    .io_enq_bits_source(bundleIn_0_d_q_io_enq_bits_source),
    .io_enq_bits_sink(bundleIn_0_d_q_io_enq_bits_sink),
    .io_enq_bits_denied(bundleIn_0_d_q_io_enq_bits_denied),
    .io_enq_bits_data(bundleIn_0_d_q_io_enq_bits_data),
    .io_enq_bits_corrupt(bundleIn_0_d_q_io_enq_bits_corrupt),
    .io_deq_ready(bundleIn_0_d_q_io_deq_ready),
    .io_deq_valid(bundleIn_0_d_q_io_deq_valid),
    .io_deq_bits_opcode(bundleIn_0_d_q_io_deq_bits_opcode),
    .io_deq_bits_param(bundleIn_0_d_q_io_deq_bits_param),
    .io_deq_bits_size(bundleIn_0_d_q_io_deq_bits_size),
    .io_deq_bits_source(bundleIn_0_d_q_io_deq_bits_source),
    .io_deq_bits_sink(bundleIn_0_d_q_io_deq_bits_sink),
    .io_deq_bits_denied(bundleIn_0_d_q_io_deq_bits_denied),
    .io_deq_bits_data(bundleIn_0_d_q_io_deq_bits_data),
    .io_deq_bits_corrupt(bundleIn_0_d_q_io_deq_bits_corrupt)
  );
  assign auto_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
  assign auto_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_param = bundleIn_0_d_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_source = bundleIn_0_d_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_sink = bundleIn_0_d_q_io_deq_bits_sink; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_denied = bundleIn_0_d_q_io_deq_bits_denied; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_data = bundleIn_0_d_q_io_deq_bits_data; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_corrupt = bundleIn_0_d_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_out_a_valid = bundleOut_0_a_q_io_deq_valid; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_opcode = bundleOut_0_a_q_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_param = bundleOut_0_a_q_io_deq_bits_param; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_size = bundleOut_0_a_q_io_deq_bits_size; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_source = bundleOut_0_a_q_io_deq_bits_source; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_address = bundleOut_0_a_q_io_deq_bits_address; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_mask = bundleOut_0_a_q_io_deq_bits_mask; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_data = bundleOut_0_a_q_io_deq_bits_data; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_corrupt = bundleOut_0_a_q_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_d_ready = bundleIn_0_d_q_io_enq_ready; // @[Nodes.scala 1207:84 Decoupled.scala 365:17]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_param = bundleIn_0_d_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_source = bundleIn_0_d_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_sink = bundleIn_0_d_q_io_deq_bits_sink; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_denied = bundleIn_0_d_q_io_deq_bits_denied; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_corrupt = bundleIn_0_d_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign bundleOut_0_a_q_clock = clock;
  assign bundleOut_0_a_q_reset = reset;
  assign bundleOut_0_a_q_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_clock = clock;
  assign bundleIn_0_d_q_reset = reset;
  assign bundleIn_0_d_q_io_enq_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_deq_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module TLMonitor_27(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [3:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [29:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_param,
  input  [3:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source,
  input         io_in_d_bits_sink,
  input         io_in_d_bits_denied,
  input         io_in_d_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [26:0] _is_aligned_mask_T_1 = 27'hfff << io_in_a_bits_size; // @[package.scala 234:77]
  wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1[11:0]; // @[package.scala 234:46]
  wire [29:0] _GEN_71 = {{18'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [29:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 30'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 4'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire [30:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire  _T_35 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42]
  wire  _T_42 = _T_35 & source_ok; // @[Parameters.scala 1160:30]
  wire [30:0] _T_48 = $signed(_T_7) & -31'sh10001000; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_50 = io_in_a_bits_address ^ 30'h3000; // @[Parameters.scala 137:31]
  wire [30:0] _T_51 = {1'b0,$signed(_T_50)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_53 = $signed(_T_51) & -31'sh1000; // @[Parameters.scala 137:52]
  wire  _T_54 = $signed(_T_53) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_55 = io_in_a_bits_address ^ 30'h10000; // @[Parameters.scala 137:31]
  wire [30:0] _T_56 = {1'b0,$signed(_T_55)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_58 = $signed(_T_56) & -31'sh10000; // @[Parameters.scala 137:52]
  wire  _T_59 = $signed(_T_58) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_60 = io_in_a_bits_address ^ 30'h2000000; // @[Parameters.scala 137:31]
  wire [30:0] _T_61 = {1'b0,$signed(_T_60)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_63 = $signed(_T_61) & -31'sh10000; // @[Parameters.scala 137:52]
  wire  _T_64 = $signed(_T_63) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_65 = io_in_a_bits_address ^ 30'h8000000; // @[Parameters.scala 137:31]
  wire [30:0] _T_66 = {1'b0,$signed(_T_65)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_68 = $signed(_T_66) & -31'sh4000; // @[Parameters.scala 137:52]
  wire  _T_69 = $signed(_T_68) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_70 = io_in_a_bits_address ^ 30'hc000000; // @[Parameters.scala 137:31]
  wire [30:0] _T_71 = {1'b0,$signed(_T_70)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_73 = $signed(_T_71) & -31'sh4000000; // @[Parameters.scala 137:52]
  wire  _T_74 = $signed(_T_73) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_75 = io_in_a_bits_address ^ 30'h10012000; // @[Parameters.scala 137:31]
  wire [30:0] _T_76 = {1'b0,$signed(_T_75)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_78 = $signed(_T_76) & -31'sh2000; // @[Parameters.scala 137:52]
  wire  _T_79 = $signed(_T_78) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_80 = io_in_a_bits_address ^ 30'h10014000; // @[Parameters.scala 137:31]
  wire [30:0] _T_81 = {1'b0,$signed(_T_80)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_83 = $signed(_T_81) & -31'sh2000; // @[Parameters.scala 137:52]
  wire  _T_84 = $signed(_T_83) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_85 = io_in_a_bits_address ^ 30'h10016000; // @[Parameters.scala 137:31]
  wire [30:0] _T_86 = {1'b0,$signed(_T_85)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_88 = $signed(_T_86) & -31'sh1000; // @[Parameters.scala 137:52]
  wire  _T_89 = $signed(_T_88) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_90 = io_in_a_bits_address ^ 30'h10023000; // @[Parameters.scala 137:31]
  wire [30:0] _T_91 = {1'b0,$signed(_T_90)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_93 = $signed(_T_91) & -31'sh11000; // @[Parameters.scala 137:52]
  wire  _T_94 = $signed(_T_93) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_95 = io_in_a_bits_address ^ 30'h10024000; // @[Parameters.scala 137:31]
  wire [30:0] _T_96 = {1'b0,$signed(_T_95)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_98 = $signed(_T_96) & -31'sh12000; // @[Parameters.scala 137:52]
  wire  _T_99 = $signed(_T_98) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_100 = io_in_a_bits_address ^ 30'h10026000; // @[Parameters.scala 137:31]
  wire [30:0] _T_101 = {1'b0,$signed(_T_100)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_103 = $signed(_T_101) & -31'sh1000; // @[Parameters.scala 137:52]
  wire  _T_104 = $signed(_T_103) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_105 = io_in_a_bits_address ^ 30'h10043000; // @[Parameters.scala 137:31]
  wire [30:0] _T_106 = {1'b0,$signed(_T_105)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_108 = $signed(_T_106) & -31'sh11000; // @[Parameters.scala 137:52]
  wire  _T_109 = $signed(_T_108) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _T_110 = io_in_a_bits_address ^ 30'h20000000; // @[Parameters.scala 137:31]
  wire [30:0] _T_111 = {1'b0,$signed(_T_110)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_113 = $signed(_T_111) & -31'sh20000000; // @[Parameters.scala 137:52]
  wire  _T_114 = $signed(_T_113) == 31'sh0; // @[Parameters.scala 137:67]
  wire  _T_127 = _T_49 | _T_54 | _T_59 | _T_64 | _T_69 | _T_74 | _T_79 | _T_84 | _T_89 | _T_94 | _T_99 | _T_104 | _T_109
     | _T_114; // @[Parameters.scala 671:42]
  wire  _T_137 = 4'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_138 = _source_ok_T & _T_137; // @[Mux.scala 27:73]
  wire  _T_230 = _T_35 & _T_127; // @[Parameters.scala 670:56]
  wire  _T_232 = _T_138 & _T_230; // @[Monitor.scala 83:78]
  wire  _T_246 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_250 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_251 = _T_250 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_255 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_259 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_476 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_489 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_512 = _T_35 & _T_54; // @[Parameters.scala 670:56]
  wire  _T_514 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42]
  wire  _T_593 = _T_49 | _T_59 | _T_64 | _T_69 | _T_74 | _T_79 | _T_84 | _T_89 | _T_94 | _T_99 | _T_104 | _T_109 |
    _T_114; // @[Parameters.scala 671:42]
  wire  _T_594 = _T_514 & _T_593; // @[Parameters.scala 670:56]
  wire  _T_596 = _T_512 | _T_594; // @[Parameters.scala 672:30]
  wire  _T_606 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_610 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_618 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_707 = _T_49 | _T_64 | _T_69 | _T_74 | _T_79 | _T_84 | _T_89 | _T_94 | _T_99 | _T_104 | _T_109; // @[Parameters.scala 671:42]
  wire  _T_708 = _T_514 & _T_707; // @[Parameters.scala 670:56]
  wire  _T_723 = _T_512 | _T_708; // @[Parameters.scala 672:30]
  wire  _T_725 = _T_42 & _T_723; // @[Monitor.scala 115:71]
  wire  _T_743 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_864 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_865 = io_in_a_bits_mask & _T_864; // @[Monitor.scala 127:31]
  wire  _T_866 = _T_865 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_870 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_882 = io_in_a_bits_size <= 4'h2; // @[Parameters.scala 92:42]
  wire  _T_955 = _T_49 | _T_54 | _T_64 | _T_69 | _T_74 | _T_79 | _T_84 | _T_89 | _T_94 | _T_99 | _T_104 | _T_109; // @[Parameters.scala 671:42]
  wire  _T_956 = _T_882 & _T_955; // @[Parameters.scala 670:56]
  wire  _T_972 = _T_42 & _T_956; // @[Monitor.scala 131:74]
  wire  _T_982 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_990 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_1102 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_1110 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_1212 = _T_42 & _T_512; // @[Monitor.scala 147:68]
  wire  _T_1222 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_1234 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  _T_1238 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_1242 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 312:27]
  wire  _T_1246 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
  wire  _T_1250 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
  wire  _T_1254 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
  wire  _T_1258 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_1269 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
  wire  _T_1273 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
  wire  _T_1286 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_1306 = _T_1254 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
  wire  _T_1315 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_1332 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_1350 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [9:0] a_first_beats1_decode = is_aligned_mask[11:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [9:0] a_first_counter; // @[Edges.scala 228:27]
  wire [9:0] a_first_counter1 = a_first_counter - 10'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 10'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [3:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [29:0] address; // @[Monitor.scala 388:22]
  wire  _T_1380 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_1381 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_1385 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_1389 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_1393 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_1397 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [26:0] _d_first_beats1_decode_T_1 = 27'hfff << io_in_d_bits_size; // @[package.scala 234:77]
  wire [11:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
  wire [9:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[11:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [9:0] d_first_counter; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1 = d_first_counter - 10'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 10'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] param_1; // @[Monitor.scala 536:22]
  reg [3:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  reg  sink; // @[Monitor.scala 539:22]
  reg  denied; // @[Monitor.scala 540:22]
  wire  _T_1404 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_1405 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_1409 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
  wire  _T_1413 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_1417 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  wire  _T_1421 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
  wire  _T_1425 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [23:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [9:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [9:0] a_first_counter1_1 = a_first_counter_1 - 10'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 10'h0; // @[Edges.scala 230:25]
  reg [9:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1_1 = d_first_counter_1 - 10'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 10'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [4:0] _a_size_lookup_T = {io_in_d_bits_source, 3'h0}; // @[Monitor.scala 638:65]
  wire [23:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _a_size_lookup_T_5 = 16'h100 - 16'h1; // @[Monitor.scala 609:57]
  wire [23:0] _GEN_75 = {{8'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 638:91]
  wire [23:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_75; // @[Monitor.scala 638:91]
  wire [23:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[23:1]}; // @[Monitor.scala 638:144]
  wire  _T_1431 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_1434 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [4:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 5'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_77 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_77}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [4:0] _a_sizes_set_T = {io_in_a_bits_source, 3'h0}; // @[Monitor.scala 657:77]
  wire [4:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala 652:72 655:28]
  wire [35:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [35:0] _a_sizes_set_T_1 = _GEN_2 << _a_sizes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_1436 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_1438 = ~_T_1436[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [35:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 36'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_1442 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_1444 = ~_T_1238; // @[Monitor.scala 671:74]
  wire  _T_1445 = io_in_d_valid & d_first_1 & ~_T_1238; // @[Monitor.scala 671:71]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_1238 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 671:90 672:22]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [46:0] _GEN_4 = {{31'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 678:74]
  wire [46:0] _d_sizes_clr_T_5 = _GEN_4 << _a_size_lookup_T; // @[Monitor.scala 678:74]
  wire [3:0] _GEN_22 = _d_first_T & d_first_1 & _T_1444 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_23 = _d_first_T & d_first_1 & _T_1444 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire [46:0] _GEN_24 = _d_first_T & d_first_1 & _T_1444 ? _d_sizes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 678:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_1431 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_1455 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_1457 = _T_1455[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_1462 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_1463 = io_in_d_bits_opcode == _GEN_32 | _T_1462; // @[Monitor.scala 685:77]
  wire  _T_1467 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_1474 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_1475 = io_in_d_bits_opcode == _GEN_48 | _T_1474; // @[Monitor.scala 689:72]
  wire [7:0] a_size_lookup = _a_size_lookup_T_7[7:0];
  wire [7:0] _GEN_79 = {{4'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_1479 = _GEN_79 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_1489 = _T_1442 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_1444; // @[Monitor.scala 694:116]
  wire  _T_1491 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set_wo_ready = _GEN_15[2:0];
  wire [2:0] d_clr_wo_ready = _GEN_21[2:0];
  wire  _T_1498 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire [2:0] a_set = _GEN_16[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_22[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_19[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_23[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [23:0] a_sizes_set = _GEN_20[23:0];
  wire [23:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [23:0] d_sizes_clr = _GEN_24[23:0];
  wire [23:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala 704:56]
  wire [23:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_1507 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [2:0] inflight_1; // @[Monitor.scala 723:35]
  reg [23:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [9:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1_2 = d_first_counter_2 - 10'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 10'h0; // @[Edges.scala 230:25]
  wire [23:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_size_lookup_T; // @[Monitor.scala 747:42]
  wire [23:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_75; // @[Monitor.scala 747:93]
  wire [23:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[23:1]}; // @[Monitor.scala 747:146]
  wire  _T_1533 = io_in_d_valid & d_first_2 & _T_1238; // @[Monitor.scala 779:71]
  wire [3:0] _GEN_67 = _d_first_T & d_first_2 & _T_1238 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 783:90 784:21]
  wire [46:0] _GEN_69 = _d_first_T & d_first_2 & _T_1238 ? _d_sizes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 786:21]
  wire [2:0] _T_1541 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [7:0] c_size_lookup = _c_size_lookup_T_7[7:0];
  wire  _T_1551 = _GEN_79 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [2:0] d_clr_1 = _GEN_67[2:0];
  wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [2:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [23:0] d_sizes_clr_1 = _GEN_69[23:0];
  wire [23:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
  wire [23:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_1576 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 10'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 10'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 10'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 24'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 10'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 10'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 3'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 24'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 10'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_232 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_232) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_246 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_246) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_251 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_251) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_255 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_255) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_232 & (io_in_a_valid & _T_259 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset & ~_T_232) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_259 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_259 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_259 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_246 & (io_in_a_valid & _T_259 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset & ~_T_246) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_476 & (io_in_a_valid & _T_259 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset & ~_T_476) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_251 & (io_in_a_valid & _T_259 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset & ~_T_251) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_255 & (io_in_a_valid & _T_259 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_259 & ~reset & ~_T_255) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_42 & (io_in_a_valid & _T_489 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_489 & ~reset & ~_T_42) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_596 & (io_in_a_valid & _T_489 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_489 & ~reset & ~_T_596) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_489 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_489 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_489 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_489 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_606 & (io_in_a_valid & _T_489 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_489 & ~reset & ~_T_606) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_610 & (io_in_a_valid & _T_489 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_489 & ~reset & ~_T_610) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_255 & (io_in_a_valid & _T_489 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_489 & ~reset & ~_T_255) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_725 & (io_in_a_valid & _T_618 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_618 & ~reset & ~_T_725) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_618 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_618 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_618 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_618 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_606 & (io_in_a_valid & _T_618 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_618 & ~reset & ~_T_606) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_610 & (io_in_a_valid & _T_618 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_618 & ~reset & ~_T_610) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_725 & (io_in_a_valid & _T_743 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_743 & ~reset & ~_T_725) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_743 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_743 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_743 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_743 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_606 & (io_in_a_valid & _T_743 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_743 & ~reset & ~_T_606) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_866 & (io_in_a_valid & _T_743 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_743 & ~reset & ~_T_866) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_972 & (io_in_a_valid & _T_870 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_870 & ~reset & ~_T_972) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_870 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_870 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_870 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_870 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_982 & (io_in_a_valid & _T_870 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_870 & ~reset & ~_T_982) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_610 & (io_in_a_valid & _T_870 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_870 & ~reset & ~_T_610) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_972 & (io_in_a_valid & _T_990 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_990 & ~reset & ~_T_972) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_990 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_990 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_990 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_990 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1102 & (io_in_a_valid & _T_990 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_990 & ~reset & ~_T_1102) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_610 & (io_in_a_valid & _T_990 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_990 & ~reset & ~_T_610) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1212 & (io_in_a_valid & _T_1110 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1110 & ~reset & ~_T_1212) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_1110 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1110 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_1110 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1110 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1222 & (io_in_a_valid & _T_1110 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1110 & ~reset & ~_T_1222) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_610 & (io_in_a_valid & _T_1110 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1110 & ~reset & ~_T_610) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_255 & (io_in_a_valid & _T_1110 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1110 & ~reset & ~_T_255) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1234 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_1234) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1238 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1238 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1242 & (io_in_d_valid & _T_1238 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1238 & _T_2 & ~_T_1242) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1246 & (io_in_d_valid & _T_1238 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1238 & _T_2 & ~_T_1246) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1250 & (io_in_d_valid & _T_1238 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1238 & _T_2 & ~_T_1250) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1254 & (io_in_d_valid & _T_1238 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1238 & _T_2 & ~_T_1254) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is denied (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1258 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1258 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_1258 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1258 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1242 & (io_in_d_valid & _T_1258 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1258 & _T_2 & ~_T_1242) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1269 & (io_in_d_valid & _T_1258 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1258 & _T_2 & ~_T_1269) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid cap param (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1273 & (io_in_d_valid & _T_1258 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1258 & _T_2 & ~_T_1273) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries toN param (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1250 & (io_in_d_valid & _T_1258 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1258 & _T_2 & ~_T_1250) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is corrupt (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1286 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1286 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_1286 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1286 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1242 & (io_in_d_valid & _T_1286 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1286 & _T_2 & ~_T_1242) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1269 & (io_in_d_valid & _T_1286 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1286 & _T_2 & ~_T_1269) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1273 & (io_in_d_valid & _T_1286 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1286 & _T_2 & ~_T_1273) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries toN param (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1306 & (io_in_d_valid & _T_1286 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1286 & _T_2 & ~_T_1306) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1315 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1315 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1246 & (io_in_d_valid & _T_1315 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1315 & _T_2 & ~_T_1246) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid param (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1250 & (io_in_d_valid & _T_1315 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1315 & _T_2 & ~_T_1250) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is corrupt (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1332 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1332 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1246 & (io_in_d_valid & _T_1332 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1332 & _T_2 & ~_T_1246) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1306 & (io_in_d_valid & _T_1332 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1332 & _T_2 & ~_T_1306) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1350 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1350 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1246 & (io_in_d_valid & _T_1350 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1350 & _T_2 & ~_T_1246) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid param (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1250 & (io_in_d_valid & _T_1350 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1350 & _T_2 & ~_T_1250) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is corrupt (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1381 & (_T_1380 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1380 & ~reset & ~_T_1381) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1385 & (_T_1380 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1380 & ~reset & ~_T_1385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1389 & (_T_1380 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1380 & ~reset & ~_T_1389) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1393 & (_T_1380 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1380 & ~reset & ~_T_1393) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1397 & (_T_1380 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1380 & ~reset & ~_T_1397) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1405 & (_T_1404 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1404 & _T_2 & ~_T_1405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1409 & (_T_1404 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1404 & _T_2 & ~_T_1409) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel param changed within multibeat operation (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1413 & (_T_1404 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1404 & _T_2 & ~_T_1413) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1417 & (_T_1404 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1404 & _T_2 & ~_T_1417) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1421 & (_T_1404 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1404 & _T_2 & ~_T_1421) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel sink changed with multibeat operation (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1425 & (_T_1404 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1404 & _T_2 & ~_T_1425) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel denied changed with multibeat operation (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1438 & (_T_1434 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1434 & ~reset & ~_T_1438) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1457 & (_T_1445 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1445 & _T_2 & ~_T_1457) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1463 & (_T_1445 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1445 & same_cycle_resp & _T_2 & ~_T_1463) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1467 & (_T_1445 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1445 & same_cycle_resp & _T_2 & ~_T_1467) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1475 & (_T_1445 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1445 & ~same_cycle_resp & _T_2 & ~_T_1475) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1479 & (_T_1445 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1445 & ~same_cycle_resp & _T_2 & ~_T_1479) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1491 & (_T_1489 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1489 & _T_2 & ~_T_1491) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1498 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_1498) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1507 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_1507) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1541[0] & (_T_1533 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1533 & _T_2 & ~_T_1541[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1551 & (_T_1533 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1533 & _T_2 & ~_T_1551) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1576 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_1576) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:58:7)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[9:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[29:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[9:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  param_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  size_1 = _RAND_9[3:0];
  _RAND_10 = {1{`RANDOM}};
  source_1 = _RAND_10[1:0];
  _RAND_11 = {1{`RANDOM}};
  sink = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  denied = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  inflight = _RAND_13[2:0];
  _RAND_14 = {1{`RANDOM}};
  inflight_opcodes = _RAND_14[11:0];
  _RAND_15 = {1{`RANDOM}};
  inflight_sizes = _RAND_15[23:0];
  _RAND_16 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_16[9:0];
  _RAND_17 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_17[9:0];
  _RAND_18 = {1{`RANDOM}};
  watchdog = _RAND_18[31:0];
  _RAND_19 = {1{`RANDOM}};
  inflight_1 = _RAND_19[2:0];
  _RAND_20 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_20[23:0];
  _RAND_21 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_21[9:0];
  _RAND_22 = {1{`RANDOM}};
  watchdog_1 = _RAND_22[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLAtomicAutomata_1(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [3:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [29:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [1:0]  auto_in_d_bits_param,
  output [3:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output        auto_in_d_bits_sink,
  output        auto_in_d_bits_denied,
  output [31:0] auto_in_d_bits_data,
  output        auto_in_d_bits_corrupt,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [3:0]  auto_out_a_bits_size,
  output [1:0]  auto_out_a_bits_source,
  output [29:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_param,
  input  [3:0]  auto_out_d_bits_size,
  input  [1:0]  auto_out_d_bits_source,
  input         auto_out_d_bits_sink,
  input         auto_out_d_bits_denied,
  input  [31:0] auto_out_d_bits_data,
  input         auto_out_d_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [29:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
  reg [1:0] cam_s_0_state; // @[AtomicAutomata.scala 76:28]
  reg [2:0] cam_a_0_bits_opcode; // @[AtomicAutomata.scala 77:24]
  reg [2:0] cam_a_0_bits_param; // @[AtomicAutomata.scala 77:24]
  reg [3:0] cam_a_0_bits_size; // @[AtomicAutomata.scala 77:24]
  reg [1:0] cam_a_0_bits_source; // @[AtomicAutomata.scala 77:24]
  reg [29:0] cam_a_0_bits_address; // @[AtomicAutomata.scala 77:24]
  reg [3:0] cam_a_0_bits_mask; // @[AtomicAutomata.scala 77:24]
  reg [31:0] cam_a_0_bits_data; // @[AtomicAutomata.scala 77:24]
  reg  cam_a_0_bits_corrupt; // @[AtomicAutomata.scala 77:24]
  reg [3:0] cam_a_0_lut; // @[AtomicAutomata.scala 77:24]
  reg [31:0] cam_d_0_data; // @[AtomicAutomata.scala 78:24]
  reg  cam_d_0_denied; // @[AtomicAutomata.scala 78:24]
  reg  cam_d_0_corrupt; // @[AtomicAutomata.scala 78:24]
  wire  cam_free_0 = cam_s_0_state == 2'h0; // @[AtomicAutomata.scala 80:44]
  wire  cam_amo_0 = cam_s_0_state == 2'h2; // @[AtomicAutomata.scala 81:44]
  wire  cam_abusy_0 = cam_s_0_state == 2'h3 | cam_amo_0; // @[AtomicAutomata.scala 82:57]
  wire  cam_dmatch_0 = cam_s_0_state != 2'h0; // @[AtomicAutomata.scala 83:49]
  wire  _a_canLogical_T_1 = auto_in_a_bits_size <= 4'h2; // @[Parameters.scala 92:42]
  wire [29:0] _a_canLogical_T_4 = auto_in_a_bits_address ^ 30'h2000; // @[Parameters.scala 137:31]
  wire [30:0] _a_canLogical_T_5 = {1'b0,$signed(_a_canLogical_T_4)}; // @[Parameters.scala 137:49]
  wire [30:0] _a_canLogical_T_7 = $signed(_a_canLogical_T_5) & 31'sh3e03e000; // @[Parameters.scala 137:52]
  wire  _a_canLogical_T_8 = $signed(_a_canLogical_T_7) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _a_canLogical_T_9 = auto_in_a_bits_address ^ 30'h10002000; // @[Parameters.scala 137:31]
  wire [30:0] _a_canLogical_T_10 = {1'b0,$signed(_a_canLogical_T_9)}; // @[Parameters.scala 137:49]
  wire [30:0] _a_canLogical_T_12 = $signed(_a_canLogical_T_10) & 31'sh3e00e000; // @[Parameters.scala 137:52]
  wire  _a_canLogical_T_13 = $signed(_a_canLogical_T_12) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _a_canLogical_T_14 = auto_in_a_bits_address ^ 30'h10014000; // @[Parameters.scala 137:31]
  wire [30:0] _a_canLogical_T_15 = {1'b0,$signed(_a_canLogical_T_14)}; // @[Parameters.scala 137:49]
  wire [30:0] _a_canLogical_T_17 = $signed(_a_canLogical_T_15) & 31'sh3e03c000; // @[Parameters.scala 137:52]
  wire  _a_canLogical_T_18 = $signed(_a_canLogical_T_17) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _a_canLogical_T_19 = auto_in_a_bits_address ^ 30'h10024000; // @[Parameters.scala 137:31]
  wire [30:0] _a_canLogical_T_20 = {1'b0,$signed(_a_canLogical_T_19)}; // @[Parameters.scala 137:49]
  wire [30:0] _a_canLogical_T_22 = $signed(_a_canLogical_T_20) & 31'sh3e03c000; // @[Parameters.scala 137:52]
  wire  _a_canLogical_T_23 = $signed(_a_canLogical_T_22) == 31'sh0; // @[Parameters.scala 137:67]
  wire [29:0] _a_canLogical_T_24 = auto_in_a_bits_address ^ 30'h10034000; // @[Parameters.scala 137:31]
  wire [30:0] _a_canLogical_T_25 = {1'b0,$signed(_a_canLogical_T_24)}; // @[Parameters.scala 137:49]
  wire [30:0] _a_canLogical_T_27 = $signed(_a_canLogical_T_25) & 31'sh3e03e000; // @[Parameters.scala 137:52]
  wire  _a_canLogical_T_28 = $signed(_a_canLogical_T_27) == 31'sh0; // @[Parameters.scala 137:67]
  wire  _a_canLogical_T_32 = _a_canLogical_T_8 | _a_canLogical_T_13 | _a_canLogical_T_18 | _a_canLogical_T_23 |
    _a_canLogical_T_28; // @[Parameters.scala 671:42]
  wire  a_canLogical = _a_canLogical_T_1 & _a_canLogical_T_32; // @[Parameters.scala 670:56]
  wire  a_isLogical = auto_in_a_bits_opcode == 3'h3; // @[AtomicAutomata.scala 90:47]
  wire  a_isArithmetic = auto_in_a_bits_opcode == 3'h2; // @[AtomicAutomata.scala 91:47]
  wire  _a_isSupported_T = a_isArithmetic ? a_canLogical : 1'h1; // @[AtomicAutomata.scala 92:63]
  wire  a_isSupported = a_isLogical ? a_canLogical : _a_isSupported_T; // @[AtomicAutomata.scala 92:32]
  wire [1:0] indexes_0 = {cam_a_0_bits_data[0],cam_d_0_data[0]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_1 = {cam_a_0_bits_data[1],cam_d_0_data[1]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_2 = {cam_a_0_bits_data[2],cam_d_0_data[2]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_3 = {cam_a_0_bits_data[3],cam_d_0_data[3]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_4 = {cam_a_0_bits_data[4],cam_d_0_data[4]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_5 = {cam_a_0_bits_data[5],cam_d_0_data[5]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_6 = {cam_a_0_bits_data[6],cam_d_0_data[6]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_7 = {cam_a_0_bits_data[7],cam_d_0_data[7]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_8 = {cam_a_0_bits_data[8],cam_d_0_data[8]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_9 = {cam_a_0_bits_data[9],cam_d_0_data[9]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_10 = {cam_a_0_bits_data[10],cam_d_0_data[10]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_11 = {cam_a_0_bits_data[11],cam_d_0_data[11]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_12 = {cam_a_0_bits_data[12],cam_d_0_data[12]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_13 = {cam_a_0_bits_data[13],cam_d_0_data[13]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_14 = {cam_a_0_bits_data[14],cam_d_0_data[14]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_15 = {cam_a_0_bits_data[15],cam_d_0_data[15]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_16 = {cam_a_0_bits_data[16],cam_d_0_data[16]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_17 = {cam_a_0_bits_data[17],cam_d_0_data[17]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_18 = {cam_a_0_bits_data[18],cam_d_0_data[18]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_19 = {cam_a_0_bits_data[19],cam_d_0_data[19]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_20 = {cam_a_0_bits_data[20],cam_d_0_data[20]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_21 = {cam_a_0_bits_data[21],cam_d_0_data[21]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_22 = {cam_a_0_bits_data[22],cam_d_0_data[22]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_23 = {cam_a_0_bits_data[23],cam_d_0_data[23]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_24 = {cam_a_0_bits_data[24],cam_d_0_data[24]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_25 = {cam_a_0_bits_data[25],cam_d_0_data[25]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_26 = {cam_a_0_bits_data[26],cam_d_0_data[26]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_27 = {cam_a_0_bits_data[27],cam_d_0_data[27]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_28 = {cam_a_0_bits_data[28],cam_d_0_data[28]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_29 = {cam_a_0_bits_data[29],cam_d_0_data[29]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_30 = {cam_a_0_bits_data[30],cam_d_0_data[30]}; // @[Cat.scala 31:58]
  wire [1:0] indexes_31 = {cam_a_0_bits_data[31],cam_d_0_data[31]}; // @[Cat.scala 31:58]
  wire [3:0] _logic_out_T = cam_a_0_lut >> indexes_0; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_2 = cam_a_0_lut >> indexes_1; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_4 = cam_a_0_lut >> indexes_2; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_6 = cam_a_0_lut >> indexes_3; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_8 = cam_a_0_lut >> indexes_4; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_10 = cam_a_0_lut >> indexes_5; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_12 = cam_a_0_lut >> indexes_6; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_14 = cam_a_0_lut >> indexes_7; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_16 = cam_a_0_lut >> indexes_8; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_18 = cam_a_0_lut >> indexes_9; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_20 = cam_a_0_lut >> indexes_10; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_22 = cam_a_0_lut >> indexes_11; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_24 = cam_a_0_lut >> indexes_12; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_26 = cam_a_0_lut >> indexes_13; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_28 = cam_a_0_lut >> indexes_14; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_30 = cam_a_0_lut >> indexes_15; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_32 = cam_a_0_lut >> indexes_16; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_34 = cam_a_0_lut >> indexes_17; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_36 = cam_a_0_lut >> indexes_18; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_38 = cam_a_0_lut >> indexes_19; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_40 = cam_a_0_lut >> indexes_20; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_42 = cam_a_0_lut >> indexes_21; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_44 = cam_a_0_lut >> indexes_22; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_46 = cam_a_0_lut >> indexes_23; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_48 = cam_a_0_lut >> indexes_24; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_50 = cam_a_0_lut >> indexes_25; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_52 = cam_a_0_lut >> indexes_26; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_54 = cam_a_0_lut >> indexes_27; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_56 = cam_a_0_lut >> indexes_28; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_58 = cam_a_0_lut >> indexes_29; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_60 = cam_a_0_lut >> indexes_30; // @[AtomicAutomata.scala 114:57]
  wire [3:0] _logic_out_T_62 = cam_a_0_lut >> indexes_31; // @[AtomicAutomata.scala 114:57]
  wire [7:0] logic_out_lo_lo = {_logic_out_T_14[0],_logic_out_T_12[0],_logic_out_T_10[0],_logic_out_T_8[0],
    _logic_out_T_6[0],_logic_out_T_4[0],_logic_out_T_2[0],_logic_out_T[0]}; // @[Cat.scala 31:58]
  wire [15:0] logic_out_lo = {_logic_out_T_30[0],_logic_out_T_28[0],_logic_out_T_26[0],_logic_out_T_24[0],
    _logic_out_T_22[0],_logic_out_T_20[0],_logic_out_T_18[0],_logic_out_T_16[0],logic_out_lo_lo}; // @[Cat.scala 31:58]
  wire [7:0] logic_out_hi_lo = {_logic_out_T_46[0],_logic_out_T_44[0],_logic_out_T_42[0],_logic_out_T_40[0],
    _logic_out_T_38[0],_logic_out_T_36[0],_logic_out_T_34[0],_logic_out_T_32[0]}; // @[Cat.scala 31:58]
  wire [31:0] logic_out = {_logic_out_T_62[0],_logic_out_T_60[0],_logic_out_T_58[0],_logic_out_T_56[0],_logic_out_T_54[0
    ],_logic_out_T_52[0],_logic_out_T_50[0],_logic_out_T_48[0],logic_out_hi_lo,logic_out_lo}; // @[Cat.scala 31:58]
  wire  unsigned_ = cam_a_0_bits_param[1]; // @[AtomicAutomata.scala 117:42]
  wire  take_max = cam_a_0_bits_param[0]; // @[AtomicAutomata.scala 118:42]
  wire  adder = cam_a_0_bits_param[2]; // @[AtomicAutomata.scala 119:39]
  wire [3:0] _signSel_T = ~cam_a_0_bits_mask; // @[AtomicAutomata.scala 121:25]
  wire [3:0] _GEN_39 = {{1'd0}, cam_a_0_bits_mask[3:1]}; // @[AtomicAutomata.scala 121:31]
  wire [3:0] _signSel_T_2 = _signSel_T | _GEN_39; // @[AtomicAutomata.scala 121:31]
  wire [3:0] signSel = ~_signSel_T_2; // @[AtomicAutomata.scala 121:23]
  wire [3:0] signbits_a = {cam_a_0_bits_data[31],cam_a_0_bits_data[23],cam_a_0_bits_data[15],cam_a_0_bits_data[7]}; // @[Cat.scala 31:58]
  wire [3:0] signbits_d = {cam_d_0_data[31],cam_d_0_data[23],cam_d_0_data[15],cam_d_0_data[7]}; // @[Cat.scala 31:58]
  wire [3:0] _signbit_a_T = signbits_a & signSel; // @[AtomicAutomata.scala 125:38]
  wire [4:0] _signbit_a_T_1 = {_signbit_a_T, 1'h0}; // @[AtomicAutomata.scala 125:49]
  wire [3:0] signbit_a = _signbit_a_T_1[3:0]; // @[AtomicAutomata.scala 125:54]
  wire [3:0] _signbit_d_T = signbits_d & signSel; // @[AtomicAutomata.scala 126:38]
  wire [4:0] _signbit_d_T_1 = {_signbit_d_T, 1'h0}; // @[AtomicAutomata.scala 126:49]
  wire [3:0] signbit_d = _signbit_d_T_1[3:0]; // @[AtomicAutomata.scala 126:54]
  wire [4:0] _signext_a_T = {signbit_a, 1'h0}; // @[package.scala 244:48]
  wire [3:0] _signext_a_T_2 = signbit_a | _signext_a_T[3:0]; // @[package.scala 244:43]
  wire [5:0] _signext_a_T_3 = {_signext_a_T_2, 2'h0}; // @[package.scala 244:48]
  wire [3:0] _signext_a_T_5 = _signext_a_T_2 | _signext_a_T_3[3:0]; // @[package.scala 244:43]
  wire [7:0] _signext_a_T_12 = _signext_a_T_5[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _signext_a_T_14 = _signext_a_T_5[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _signext_a_T_16 = _signext_a_T_5[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _signext_a_T_18 = _signext_a_T_5[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [31:0] signext_a = {_signext_a_T_18,_signext_a_T_16,_signext_a_T_14,_signext_a_T_12}; // @[Cat.scala 31:58]
  wire [4:0] _signext_d_T = {signbit_d, 1'h0}; // @[package.scala 244:48]
  wire [3:0] _signext_d_T_2 = signbit_d | _signext_d_T[3:0]; // @[package.scala 244:43]
  wire [5:0] _signext_d_T_3 = {_signext_d_T_2, 2'h0}; // @[package.scala 244:48]
  wire [3:0] _signext_d_T_5 = _signext_d_T_2 | _signext_d_T_3[3:0]; // @[package.scala 244:43]
  wire [7:0] _signext_d_T_12 = _signext_d_T_5[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _signext_d_T_14 = _signext_d_T_5[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _signext_d_T_16 = _signext_d_T_5[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _signext_d_T_18 = _signext_d_T_5[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [31:0] signext_d = {_signext_d_T_18,_signext_d_T_16,_signext_d_T_14,_signext_d_T_12}; // @[Cat.scala 31:58]
  wire [7:0] _wide_mask_T_5 = cam_a_0_bits_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _wide_mask_T_7 = cam_a_0_bits_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _wide_mask_T_9 = cam_a_0_bits_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _wide_mask_T_11 = cam_a_0_bits_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [31:0] wide_mask = {_wide_mask_T_11,_wide_mask_T_9,_wide_mask_T_7,_wide_mask_T_5}; // @[Cat.scala 31:58]
  wire [31:0] _a_a_ext_T = cam_a_0_bits_data & wide_mask; // @[AtomicAutomata.scala 131:28]
  wire [31:0] a_a_ext = _a_a_ext_T | signext_a; // @[AtomicAutomata.scala 131:41]
  wire [31:0] _a_d_ext_T = cam_d_0_data & wide_mask; // @[AtomicAutomata.scala 132:28]
  wire [31:0] a_d_ext = _a_d_ext_T | signext_d; // @[AtomicAutomata.scala 132:41]
  wire [31:0] _a_d_inv_T = ~a_d_ext; // @[AtomicAutomata.scala 133:43]
  wire [31:0] a_d_inv = adder ? a_d_ext : _a_d_inv_T; // @[AtomicAutomata.scala 133:26]
  wire [31:0] adder_out = a_a_ext + a_d_inv; // @[AtomicAutomata.scala 134:33]
  wire  a_bigger_uneq = unsigned_ == a_a_ext[31]; // @[AtomicAutomata.scala 136:38]
  wire  a_bigger = a_a_ext[31] == a_d_ext[31] ? ~adder_out[31] : a_bigger_uneq; // @[AtomicAutomata.scala 137:27]
  wire  pick_a = take_max == a_bigger; // @[AtomicAutomata.scala 138:31]
  wire [31:0] _arith_out_T = pick_a ? cam_a_0_bits_data : cam_d_0_data; // @[AtomicAutomata.scala 139:50]
  wire [31:0] arith_out = adder ? adder_out : _arith_out_T; // @[AtomicAutomata.scala 139:28]
  wire [31:0] amo_data = cam_a_0_bits_opcode[0] ? logic_out : arith_out; // @[AtomicAutomata.scala 145:14]
  wire  a_allow = ~cam_abusy_0 & (a_isSupported | cam_free_0); // @[AtomicAutomata.scala 149:35]
  reg [9:0] beatsLeft; // @[Arbiter.scala 87:30]
  wire  idle = beatsLeft == 10'h0; // @[Arbiter.scala 88:28]
  wire  source_i_valid = auto_in_a_valid & a_allow; // @[AtomicAutomata.scala 151:38]
  wire [1:0] _readys_T = {source_i_valid,cam_amo_0}; // @[Cat.scala 31:58]
  wire [2:0] _readys_T_1 = {_readys_T, 1'h0}; // @[package.scala 244:48]
  wire [1:0] _readys_T_3 = _readys_T | _readys_T_1[1:0]; // @[package.scala 244:43]
  wire [2:0] _readys_T_5 = {_readys_T_3, 1'h0}; // @[Arbiter.scala 16:78]
  wire [1:0] _readys_T_7 = ~_readys_T_5[1:0]; // @[Arbiter.scala 16:61]
  wire  readys_1 = _readys_T_7[1]; // @[Arbiter.scala 95:86]
  reg  state_1; // @[Arbiter.scala 116:26]
  wire  allowed_1 = idle ? readys_1 : state_1; // @[Arbiter.scala 121:24]
  wire  out_1_ready = auto_out_a_ready & allowed_1; // @[Arbiter.scala 123:31]
  wire  _T = ~a_isSupported; // @[AtomicAutomata.scala 153:15]
  wire [2:0] source_i_bits_opcode = ~a_isSupported ? 3'h4 : auto_in_a_bits_opcode; // @[AtomicAutomata.scala 152:24 153:31 154:32]
  wire [2:0] source_i_bits_param = ~a_isSupported ? 3'h0 : auto_in_a_bits_param; // @[AtomicAutomata.scala 152:24 153:31 155:32]
  wire  source_c_bits_a_corrupt = cam_a_0_bits_corrupt | cam_d_0_corrupt; // @[AtomicAutomata.scala 166:45]
  wire  source_c_bits_a_mask_sizeOH_shiftAmount = cam_a_0_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _source_c_bits_a_mask_sizeOH_T_1 = 2'h1 << source_c_bits_a_mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] source_c_bits_a_mask_sizeOH = _source_c_bits_a_mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _source_c_bits_a_mask_T = cam_a_0_bits_size >= 4'h2; // @[Misc.scala 205:21]
  wire  source_c_bits_a_mask_size = source_c_bits_a_mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  source_c_bits_a_mask_bit = cam_a_0_bits_address[1]; // @[Misc.scala 209:26]
  wire  source_c_bits_a_mask_nbit = ~source_c_bits_a_mask_bit; // @[Misc.scala 210:20]
  wire  source_c_bits_a_mask_acc = _source_c_bits_a_mask_T | source_c_bits_a_mask_size & source_c_bits_a_mask_nbit; // @[Misc.scala 214:29]
  wire  source_c_bits_a_mask_acc_1 = _source_c_bits_a_mask_T | source_c_bits_a_mask_size & source_c_bits_a_mask_bit; // @[Misc.scala 214:29]
  wire  source_c_bits_a_mask_size_1 = source_c_bits_a_mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  source_c_bits_a_mask_bit_1 = cam_a_0_bits_address[0]; // @[Misc.scala 209:26]
  wire  source_c_bits_a_mask_nbit_1 = ~source_c_bits_a_mask_bit_1; // @[Misc.scala 210:20]
  wire  source_c_bits_a_mask_eq_2 = source_c_bits_a_mask_nbit & source_c_bits_a_mask_nbit_1; // @[Misc.scala 213:27]
  wire  source_c_bits_a_mask_acc_2 = source_c_bits_a_mask_acc | source_c_bits_a_mask_size_1 & source_c_bits_a_mask_eq_2; // @[Misc.scala 214:29]
  wire  source_c_bits_a_mask_eq_3 = source_c_bits_a_mask_nbit & source_c_bits_a_mask_bit_1; // @[Misc.scala 213:27]
  wire  source_c_bits_a_mask_acc_3 = source_c_bits_a_mask_acc | source_c_bits_a_mask_size_1 & source_c_bits_a_mask_eq_3; // @[Misc.scala 214:29]
  wire  source_c_bits_a_mask_eq_4 = source_c_bits_a_mask_bit & source_c_bits_a_mask_nbit_1; // @[Misc.scala 213:27]
  wire  source_c_bits_a_mask_acc_4 = source_c_bits_a_mask_acc_1 | source_c_bits_a_mask_size_1 &
    source_c_bits_a_mask_eq_4; // @[Misc.scala 214:29]
  wire  source_c_bits_a_mask_eq_5 = source_c_bits_a_mask_bit & source_c_bits_a_mask_bit_1; // @[Misc.scala 213:27]
  wire  source_c_bits_a_mask_acc_5 = source_c_bits_a_mask_acc_1 | source_c_bits_a_mask_size_1 &
    source_c_bits_a_mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] source_c_bits_a_mask = {source_c_bits_a_mask_acc_5,source_c_bits_a_mask_acc_4,source_c_bits_a_mask_acc_3,
    source_c_bits_a_mask_acc_2}; // @[Cat.scala 31:58]
  wire [26:0] _decode_T_1 = 27'hfff << auto_in_a_bits_size; // @[package.scala 234:77]
  wire [11:0] _decode_T_3 = ~_decode_T_1[11:0]; // @[package.scala 234:46]
  wire [9:0] decode = _decode_T_3[11:2]; // @[Edges.scala 219:59]
  wire  opdata = ~auto_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  wire  latch = idle & auto_out_a_ready; // @[Arbiter.scala 89:24]
  wire  readys_0 = _readys_T_7[0]; // @[Arbiter.scala 95:86]
  wire  earlyWinner_0 = readys_0 & cam_amo_0; // @[Arbiter.scala 97:79]
  wire  earlyWinner_1 = readys_1 & source_i_valid; // @[Arbiter.scala 97:79]
  wire  _prefixOR_T = earlyWinner_0 | earlyWinner_1; // @[Arbiter.scala 104:53]
  wire  _T_10 = ~reset; // @[Arbiter.scala 105:13]
  wire  _T_12 = cam_amo_0 | source_i_valid; // @[Arbiter.scala 107:36]
  wire  _T_13 = ~(cam_amo_0 | source_i_valid); // @[Arbiter.scala 107:15]
  reg  state_0; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_0 = idle ? earlyWinner_0 : state_0; // @[Arbiter.scala 117:30]
  wire  muxStateEarly_1 = idle ? earlyWinner_1 : state_1; // @[Arbiter.scala 117:30]
  wire  _sink_ACancel_earlyValid_T_3 = state_0 & cam_amo_0 | state_1 & source_i_valid; // @[Mux.scala 27:73]
  wire  sink_ACancel_earlyValid = idle ? _T_12 : _sink_ACancel_earlyValid_T_3; // @[Arbiter.scala 125:29]
  wire  _beatsLeft_T_2 = auto_out_a_ready & sink_ACancel_earlyValid; // @[ReadyValidCancel.scala 49:33]
  wire [9:0] _GEN_40 = {{9'd0}, _beatsLeft_T_2}; // @[Arbiter.scala 113:52]
  wire [9:0] _beatsLeft_T_4 = beatsLeft - _GEN_40; // @[Arbiter.scala 113:52]
  wire  allowed_0 = idle ? readys_0 : state_0; // @[Arbiter.scala 121:24]
  wire  out_ready = auto_out_a_ready & allowed_0; // @[Arbiter.scala 123:31]
  wire [31:0] _T_29 = muxStateEarly_0 ? amo_data : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_30 = muxStateEarly_1 ? auto_in_a_bits_data : 32'h0; // @[Mux.scala 27:73]
  wire [3:0] _T_32 = muxStateEarly_0 ? source_c_bits_a_mask : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _T_33 = muxStateEarly_1 ? auto_in_a_bits_mask : 4'h0; // @[Mux.scala 27:73]
  wire [29:0] _T_35 = muxStateEarly_0 ? cam_a_0_bits_address : 30'h0; // @[Mux.scala 27:73]
  wire [29:0] _T_36 = muxStateEarly_1 ? auto_in_a_bits_address : 30'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_38 = muxStateEarly_0 ? cam_a_0_bits_source : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_39 = muxStateEarly_1 ? auto_in_a_bits_source : 2'h0; // @[Mux.scala 27:73]
  wire [3:0] _T_41 = muxStateEarly_0 ? cam_a_0_bits_size : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _T_42 = muxStateEarly_1 ? auto_in_a_bits_size : 4'h0; // @[Mux.scala 27:73]
  wire  _T_50 = out_1_ready & source_i_valid; // @[Decoupled.scala 50:35]
  wire [2:0] _GEN_41 = {{1'd0}, auto_in_a_bits_param[1:0]}; // @[Mux.scala 81:61]
  wire [3:0] _cam_a_0_lut_T_2 = 3'h1 == _GEN_41 ? 4'he : 4'h8; // @[Mux.scala 81:58]
  wire [1:0] _GEN_12 = cam_free_0 ? 2'h3 : cam_s_0_state; // @[AtomicAutomata.scala 187:23 188:23 76:28]
  wire [1:0] _GEN_23 = _T_50 & _T ? _GEN_12 : cam_s_0_state; // @[AtomicAutomata.scala 174:50 76:28]
  wire  _T_53 = out_ready & cam_amo_0; // @[Decoupled.scala 50:35]
  wire [1:0] _GEN_24 = cam_amo_0 ? 2'h1 : _GEN_23; // @[AtomicAutomata.scala 196:23 197:23]
  wire [1:0] _GEN_25 = _T_53 ? _GEN_24 : _GEN_23; // @[AtomicAutomata.scala 194:32]
  reg [9:0] d_first_counter; // @[Edges.scala 228:27]
  wire  d_first = d_first_counter == 10'h0; // @[Edges.scala 230:25]
  wire  d_ackd = auto_out_d_bits_opcode == 3'h1; // @[AtomicAutomata.scala 213:40]
  wire  d_cam_sel_raw_0 = cam_a_0_bits_source == auto_out_d_bits_source; // @[AtomicAutomata.scala 204:53]
  wire  d_cam_sel_match_0 = d_cam_sel_raw_0 & cam_dmatch_0; // @[AtomicAutomata.scala 205:83]
  wire  d_drop = d_first & d_ackd & d_cam_sel_match_0; // @[AtomicAutomata.scala 232:40]
  wire  bundleOut_0_d_ready = auto_in_d_ready | d_drop; // @[AtomicAutomata.scala 236:35]
  wire  _d_first_T = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
  wire [26:0] _d_first_beats1_decode_T_1 = 27'hfff << auto_out_d_bits_size; // @[package.scala 234:77]
  wire [11:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
  wire [9:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[11:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire [9:0] d_first_counter1 = d_first_counter - 10'h1; // @[Edges.scala 229:28]
  wire  d_ack = auto_out_d_bits_opcode == 3'h0; // @[AtomicAutomata.scala 214:40]
  wire  d_replace = d_first & d_ack & d_cam_sel_match_0; // @[AtomicAutomata.scala 233:42]
  TLMonitor_27 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_param(monitor_io_in_d_bits_param),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source),
    .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
    .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
    .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
  );
  assign auto_in_a_ready = out_1_ready & a_allow; // @[AtomicAutomata.scala 150:38]
  assign auto_in_d_valid = auto_out_d_valid & ~d_drop; // @[AtomicAutomata.scala 235:35]
  assign auto_in_d_bits_opcode = d_replace ? 3'h1 : auto_out_d_bits_opcode; // @[AtomicAutomata.scala 238:19 239:26 240:28]
  assign auto_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_denied = d_replace ? cam_d_0_denied | auto_out_d_bits_denied : auto_out_d_bits_denied; // @[AtomicAutomata.scala 238:19 239:26 243:29]
  assign auto_in_d_bits_data = d_replace ? cam_d_0_data : auto_out_d_bits_data; // @[AtomicAutomata.scala 238:19 239:26 241:26]
  assign auto_in_d_bits_corrupt = d_replace ? cam_d_0_corrupt | auto_out_d_bits_denied : auto_out_d_bits_corrupt; // @[AtomicAutomata.scala 238:19 239:26 242:29]
  assign auto_out_a_valid = idle ? _T_12 : _sink_ACancel_earlyValid_T_3; // @[Arbiter.scala 125:29]
  assign auto_out_a_bits_opcode = muxStateEarly_1 ? source_i_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  assign auto_out_a_bits_param = muxStateEarly_1 ? source_i_bits_param : 3'h0; // @[Mux.scala 27:73]
  assign auto_out_a_bits_size = _T_41 | _T_42; // @[Mux.scala 27:73]
  assign auto_out_a_bits_source = _T_38 | _T_39; // @[Mux.scala 27:73]
  assign auto_out_a_bits_address = _T_35 | _T_36; // @[Mux.scala 27:73]
  assign auto_out_a_bits_mask = _T_32 | _T_33; // @[Mux.scala 27:73]
  assign auto_out_a_bits_data = _T_29 | _T_30; // @[Mux.scala 27:73]
  assign auto_out_a_bits_corrupt = muxStateEarly_0 & source_c_bits_a_corrupt | muxStateEarly_1 & auto_in_a_bits_corrupt; // @[Mux.scala 27:73]
  assign auto_out_d_ready = auto_in_d_ready | d_drop; // @[AtomicAutomata.scala 236:35]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = out_1_ready & a_allow; // @[AtomicAutomata.scala 150:38]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid & ~d_drop; // @[AtomicAutomata.scala 235:35]
  assign monitor_io_in_d_bits_opcode = d_replace ? 3'h1 : auto_out_d_bits_opcode; // @[AtomicAutomata.scala 238:19 239:26 240:28]
  assign monitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_denied = d_replace ? cam_d_0_denied | auto_out_d_bits_denied : auto_out_d_bits_denied; // @[AtomicAutomata.scala 238:19 239:26 243:29]
  assign monitor_io_in_d_bits_corrupt = d_replace ? cam_d_0_corrupt | auto_out_d_bits_denied : auto_out_d_bits_corrupt; // @[AtomicAutomata.scala 238:19 239:26 242:29]
  always @(posedge clock) begin
    if (reset) begin // @[AtomicAutomata.scala 76:28]
      cam_s_0_state <= 2'h0; // @[AtomicAutomata.scala 76:28]
    end else if (_d_first_T & d_first) begin // @[AtomicAutomata.scala 216:40]
      if (d_cam_sel_match_0) begin // @[AtomicAutomata.scala 225:23]
        if (d_ackd) begin // @[AtomicAutomata.scala 227:29]
          cam_s_0_state <= 2'h2;
        end else begin
          cam_s_0_state <= 2'h0;
        end
      end else begin
        cam_s_0_state <= _GEN_25;
      end
    end else begin
      cam_s_0_state <= _GEN_25;
    end
    if (_T_50 & _T) begin // @[AtomicAutomata.scala 174:50]
      if (cam_free_0) begin // @[AtomicAutomata.scala 176:23]
        cam_a_0_bits_opcode <= auto_in_a_bits_opcode; // @[AtomicAutomata.scala 178:24]
      end
    end
    if (_T_50 & _T) begin // @[AtomicAutomata.scala 174:50]
      if (cam_free_0) begin // @[AtomicAutomata.scala 176:23]
        cam_a_0_bits_param <= auto_in_a_bits_param; // @[AtomicAutomata.scala 178:24]
      end
    end
    if (_T_50 & _T) begin // @[AtomicAutomata.scala 174:50]
      if (cam_free_0) begin // @[AtomicAutomata.scala 176:23]
        cam_a_0_bits_size <= auto_in_a_bits_size; // @[AtomicAutomata.scala 178:24]
      end
    end
    if (_T_50 & _T) begin // @[AtomicAutomata.scala 174:50]
      if (cam_free_0) begin // @[AtomicAutomata.scala 176:23]
        cam_a_0_bits_source <= auto_in_a_bits_source; // @[AtomicAutomata.scala 178:24]
      end
    end
    if (_T_50 & _T) begin // @[AtomicAutomata.scala 174:50]
      if (cam_free_0) begin // @[AtomicAutomata.scala 176:23]
        cam_a_0_bits_address <= auto_in_a_bits_address; // @[AtomicAutomata.scala 178:24]
      end
    end
    if (_T_50 & _T) begin // @[AtomicAutomata.scala 174:50]
      if (cam_free_0) begin // @[AtomicAutomata.scala 176:23]
        cam_a_0_bits_mask <= auto_in_a_bits_mask; // @[AtomicAutomata.scala 178:24]
      end
    end
    if (_T_50 & _T) begin // @[AtomicAutomata.scala 174:50]
      if (cam_free_0) begin // @[AtomicAutomata.scala 176:23]
        cam_a_0_bits_data <= auto_in_a_bits_data; // @[AtomicAutomata.scala 178:24]
      end
    end
    if (_T_50 & _T) begin // @[AtomicAutomata.scala 174:50]
      if (cam_free_0) begin // @[AtomicAutomata.scala 176:23]
        cam_a_0_bits_corrupt <= auto_in_a_bits_corrupt; // @[AtomicAutomata.scala 178:24]
      end
    end
    if (_T_50 & _T) begin // @[AtomicAutomata.scala 174:50]
      if (cam_free_0) begin // @[AtomicAutomata.scala 176:23]
        if (3'h3 == _GEN_41) begin // @[Mux.scala 81:58]
          cam_a_0_lut <= 4'hc;
        end else if (3'h0 == _GEN_41) begin // @[Mux.scala 81:58]
          cam_a_0_lut <= 4'h6;
        end else begin
          cam_a_0_lut <= _cam_a_0_lut_T_2;
        end
      end
    end
    if (_d_first_T & d_first) begin // @[AtomicAutomata.scala 216:40]
      if (d_cam_sel_match_0 & d_ackd) begin // @[AtomicAutomata.scala 218:33]
        cam_d_0_data <= auto_out_d_bits_data; // @[AtomicAutomata.scala 219:22]
      end
    end
    if (_d_first_T & d_first) begin // @[AtomicAutomata.scala 216:40]
      if (d_cam_sel_match_0 & d_ackd) begin // @[AtomicAutomata.scala 218:33]
        cam_d_0_denied <= auto_out_d_bits_denied; // @[AtomicAutomata.scala 220:24]
      end
    end
    if (_d_first_T & d_first) begin // @[AtomicAutomata.scala 216:40]
      if (d_cam_sel_match_0 & d_ackd) begin // @[AtomicAutomata.scala 218:33]
        cam_d_0_corrupt <= auto_out_d_bits_corrupt; // @[AtomicAutomata.scala 221:25]
      end
    end
    if (reset) begin // @[Arbiter.scala 87:30]
      beatsLeft <= 10'h0; // @[Arbiter.scala 87:30]
    end else if (latch) begin // @[Arbiter.scala 113:23]
      if (earlyWinner_1) begin // @[Arbiter.scala 111:73]
        if (opdata) begin // @[Edges.scala 220:14]
          beatsLeft <= decode;
        end else begin
          beatsLeft <= 10'h0;
        end
      end else begin
        beatsLeft <= 10'h0;
      end
    end else begin
      beatsLeft <= _beatsLeft_T_4;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_1 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_1 <= earlyWinner_1;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_0 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_0 <= earlyWinner_0;
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 10'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~earlyWinner_0 | ~earlyWinner_1) & ~reset) begin
          $fatal; // @[Arbiter.scala 105:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~earlyWinner_0 | ~earlyWinner_1)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:105 assert((prefixOR zip earlyWinner) map { case (p,w) => !p || !w } reduce {_ && _})\n"
            ); // @[Arbiter.scala 105:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(cam_amo_0 | source_i_valid) | _prefixOR_T) & _T_10) begin
          $fatal; // @[Arbiter.scala 107:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_10 & ~(~(cam_amo_0 | source_i_valid) | _prefixOR_T)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:107 assert (!earlyValids.reduce(_||_) || earlyWinner.reduce(_||_))\n"
            ); // @[Arbiter.scala 107:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_13 | _T_12) & _T_10) begin
          $fatal; // @[Arbiter.scala 108:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_10 & ~(_T_13 | _T_12)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:108 assert (!validQuals .reduce(_||_) || validQuals .reduce(_||_))\n"
            ); // @[Arbiter.scala 108:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  cam_s_0_state = _RAND_0[1:0];
  _RAND_1 = {1{`RANDOM}};
  cam_a_0_bits_opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  cam_a_0_bits_param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  cam_a_0_bits_size = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  cam_a_0_bits_source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  cam_a_0_bits_address = _RAND_5[29:0];
  _RAND_6 = {1{`RANDOM}};
  cam_a_0_bits_mask = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  cam_a_0_bits_data = _RAND_7[31:0];
  _RAND_8 = {1{`RANDOM}};
  cam_a_0_bits_corrupt = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  cam_a_0_lut = _RAND_9[3:0];
  _RAND_10 = {1{`RANDOM}};
  cam_d_0_data = _RAND_10[31:0];
  _RAND_11 = {1{`RANDOM}};
  cam_d_0_denied = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  cam_d_0_corrupt = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  beatsLeft = _RAND_13[9:0];
  _RAND_14 = {1{`RANDOM}};
  state_1 = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  state_0 = _RAND_15[0:0];
  _RAND_16 = {1{`RANDOM}};
  d_first_counter = _RAND_16[9:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLMonitor_28(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [3:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [13:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [3:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source,
  input         io_in_d_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [26:0] _is_aligned_mask_T_1 = 27'hfff << io_in_a_bits_size; // @[package.scala 234:77]
  wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1[11:0]; // @[package.scala 234:46]
  wire [13:0] _GEN_71 = {{2'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [13:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 14'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 4'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire  _T_35 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42]
  wire  _T_42 = _T_35 & source_ok; // @[Parameters.scala 1160:30]
  wire [13:0] _T_45 = io_in_a_bits_address ^ 14'h3000; // @[Parameters.scala 137:31]
  wire [14:0] _T_46 = {1'b0,$signed(_T_45)}; // @[Parameters.scala 137:49]
  wire [14:0] _T_48 = $signed(_T_46) & -15'sh1000; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 15'sh0; // @[Parameters.scala 137:67]
  wire  _T_59 = 4'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_60 = _source_ok_T & _T_59; // @[Mux.scala 27:73]
  wire  _T_74 = _T_35 & _T_49; // @[Parameters.scala 670:56]
  wire  _T_76 = _T_60 & _T_74; // @[Monitor.scala 83:78]
  wire  _T_90 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_94 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_95 = _T_94 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_99 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_103 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_164 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_177 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_211 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_215 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_223 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_245 = _T_42 & _T_74; // @[Monitor.scala 115:71]
  wire  _T_263 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_299 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_300 = io_in_a_bits_mask & _T_299; // @[Monitor.scala 127:31]
  wire  _T_301 = _T_300 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_305 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_317 = io_in_a_bits_size <= 4'h2; // @[Parameters.scala 92:42]
  wire  _T_325 = _T_317 & _T_49; // @[Parameters.scala 670:56]
  wire  _T_327 = _T_42 & _T_325; // @[Monitor.scala 131:74]
  wire  _T_337 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_345 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_377 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_385 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_417 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_429 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  _T_433 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_437 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 312:27]
  wire  _T_445 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
  wire  _T_453 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_481 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_510 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_527 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_545 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [9:0] a_first_beats1_decode = is_aligned_mask[11:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [9:0] a_first_counter; // @[Edges.scala 228:27]
  wire [9:0] a_first_counter1 = a_first_counter - 10'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 10'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [3:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [13:0] address; // @[Monitor.scala 388:22]
  wire  _T_575 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_576 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_580 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_584 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_588 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_592 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [26:0] _d_first_beats1_decode_T_1 = 27'hfff << io_in_d_bits_size; // @[package.scala 234:77]
  wire [11:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
  wire [9:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[11:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [9:0] d_first_counter; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1 = d_first_counter - 10'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 10'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [3:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_599 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_600 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_608 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_612 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [23:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [9:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [9:0] a_first_counter1_1 = a_first_counter_1 - 10'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 10'h0; // @[Edges.scala 230:25]
  reg [9:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1_1 = d_first_counter_1 - 10'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 10'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [4:0] _a_size_lookup_T = {io_in_d_bits_source, 3'h0}; // @[Monitor.scala 638:65]
  wire [23:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _a_size_lookup_T_5 = 16'h100 - 16'h1; // @[Monitor.scala 609:57]
  wire [23:0] _GEN_75 = {{8'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 638:91]
  wire [23:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_75; // @[Monitor.scala 638:91]
  wire [23:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[23:1]}; // @[Monitor.scala 638:144]
  wire  _T_626 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_629 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [4:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 5'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_77 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_77}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [4:0] _a_sizes_set_T = {io_in_a_bits_source, 3'h0}; // @[Monitor.scala 657:77]
  wire [4:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala 652:72 655:28]
  wire [35:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [35:0] _a_sizes_set_T_1 = _GEN_2 << _a_sizes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_631 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_633 = ~_T_631[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [35:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 36'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_637 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_639 = ~_T_433; // @[Monitor.scala 671:74]
  wire  _T_640 = io_in_d_valid & d_first_1 & ~_T_433; // @[Monitor.scala 671:71]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_433 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 671:90 672:22]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [46:0] _GEN_4 = {{31'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 678:74]
  wire [46:0] _d_sizes_clr_T_5 = _GEN_4 << _a_size_lookup_T; // @[Monitor.scala 678:74]
  wire [3:0] _GEN_22 = _d_first_T & d_first_1 & _T_639 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_23 = _d_first_T & d_first_1 & _T_639 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire [46:0] _GEN_24 = _d_first_T & d_first_1 & _T_639 ? _d_sizes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 678:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_626 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_650 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_652 = _T_650[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_657 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_658 = io_in_d_bits_opcode == _GEN_32 | _T_657; // @[Monitor.scala 685:77]
  wire  _T_662 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_669 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_670 = io_in_d_bits_opcode == _GEN_48 | _T_669; // @[Monitor.scala 689:72]
  wire [7:0] a_size_lookup = _a_size_lookup_T_7[7:0];
  wire [7:0] _GEN_79 = {{4'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_674 = _GEN_79 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_684 = _T_637 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_639; // @[Monitor.scala 694:116]
  wire  _T_686 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set_wo_ready = _GEN_15[2:0];
  wire [2:0] d_clr_wo_ready = _GEN_21[2:0];
  wire  _T_693 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire [2:0] a_set = _GEN_16[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_22[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_19[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_23[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [23:0] a_sizes_set = _GEN_20[23:0];
  wire [23:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [23:0] d_sizes_clr = _GEN_24[23:0];
  wire [23:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala 704:56]
  wire [23:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_702 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [2:0] inflight_1; // @[Monitor.scala 723:35]
  reg [23:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [9:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1_2 = d_first_counter_2 - 10'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 10'h0; // @[Edges.scala 230:25]
  wire [23:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_size_lookup_T; // @[Monitor.scala 747:42]
  wire [23:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_75; // @[Monitor.scala 747:93]
  wire [23:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[23:1]}; // @[Monitor.scala 747:146]
  wire  _T_728 = io_in_d_valid & d_first_2 & _T_433; // @[Monitor.scala 779:71]
  wire [3:0] _GEN_67 = _d_first_T & d_first_2 & _T_433 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 783:90 784:21]
  wire [46:0] _GEN_69 = _d_first_T & d_first_2 & _T_433 ? _d_sizes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 786:21]
  wire [2:0] _T_736 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [7:0] c_size_lookup = _c_size_lookup_T_7[7:0];
  wire  _T_746 = _GEN_79 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [2:0] d_clr_1 = _GEN_67[2:0];
  wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [2:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [23:0] d_sizes_clr_1 = _GEN_69[23:0];
  wire [23:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
  wire [23:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_771 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 10'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 10'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 10'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 24'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 10'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 10'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 3'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 24'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 10'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_164 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_164) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_42 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_42) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_301 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_301) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_327 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_327) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_337 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_337) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_327 & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~_T_327) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_377 & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~_T_377) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_385 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_385 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_385 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_385 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_385 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_385 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_417 & (io_in_a_valid & _T_385 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_385 & ~reset & ~_T_417) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_385 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_385 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_385 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_385 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_429 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_429) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_433 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_433 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_437 & (io_in_d_valid & _T_433 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_433 & _T_2 & ~_T_437) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_445 & (io_in_d_valid & _T_433 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_433 & _T_2 & ~_T_445) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_433 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_433 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is denied (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_453 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_453 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_453 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_453 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_437 & (io_in_d_valid & _T_453 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_453 & _T_2 & ~_T_437) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_445 & (io_in_d_valid & _T_453 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_453 & _T_2 & ~_T_445) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is corrupt (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_481 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_481 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_481 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_481 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_437 & (io_in_d_valid & _T_481 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_481 & _T_2 & ~_T_437) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_445 & (io_in_d_valid & _T_481 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_481 & _T_2 & _T_445) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_510 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_510 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_445 & (io_in_d_valid & _T_510 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_510 & _T_2 & ~_T_445) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is corrupt (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_527 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_527 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_445 & (io_in_d_valid & _T_527 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_527 & _T_2 & _T_445) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_545 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_545 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_445 & (io_in_d_valid & _T_545 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_545 & _T_2 & ~_T_445) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is corrupt (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_576 & (_T_575 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_575 & ~reset & ~_T_576) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_580 & (_T_575 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_575 & ~reset & ~_T_580) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_584 & (_T_575 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_575 & ~reset & ~_T_584) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_588 & (_T_575 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_575 & ~reset & ~_T_588) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_592 & (_T_575 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_575 & ~reset & ~_T_592) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_600 & (_T_599 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_599 & _T_2 & ~_T_600) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_608 & (_T_599 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_599 & _T_2 & ~_T_608) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_612 & (_T_599 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_599 & _T_2 & ~_T_612) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_633 & (_T_629 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_629 & ~reset & ~_T_633) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_652 & (_T_640 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_640 & _T_2 & ~_T_652) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_658 & (_T_640 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_640 & same_cycle_resp & _T_2 & ~_T_658) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_662 & (_T_640 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_640 & same_cycle_resp & _T_2 & ~_T_662) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_670 & (_T_640 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_640 & ~same_cycle_resp & _T_2 & ~_T_670) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_674 & (_T_640 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_640 & ~same_cycle_resp & _T_2 & ~_T_674) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_686 & (_T_684 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_684 & _T_2 & ~_T_686) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_693 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_693) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_702 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_702) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_736[0] & (_T_728 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_728 & _T_2 & ~_T_736[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_746 & (_T_728 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_728 & _T_2 & ~_T_746) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_771 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_771) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CanHaveBuiltInDevices.scala:43:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[9:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[13:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[9:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[3:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[1:0];
  _RAND_10 = {1{`RANDOM}};
  inflight = _RAND_10[2:0];
  _RAND_11 = {1{`RANDOM}};
  inflight_opcodes = _RAND_11[11:0];
  _RAND_12 = {1{`RANDOM}};
  inflight_sizes = _RAND_12[23:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[9:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[9:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  inflight_1 = _RAND_16[2:0];
  _RAND_17 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_17[23:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[9:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_7(
  input        clock,
  input        reset,
  output       io_enq_ready,
  input        io_enq_valid,
  input  [2:0] io_enq_bits_opcode,
  input  [3:0] io_enq_bits_size,
  input  [1:0] io_enq_bits_source,
  input        io_deq_ready,
  output       io_deq_valid,
  output [2:0] io_deq_bits_opcode,
  output [3:0] io_deq_bits_size,
  output [1:0] io_deq_bits_source
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_3;
`endif // RANDOMIZE_REG_INIT
  reg [2:0] ram_opcode [0:0]; // @[Decoupled.scala 259:95]
  wire  ram_opcode_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_opcode_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [2:0] ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_en; // @[Decoupled.scala 259:95]
  reg [3:0] ram_size [0:0]; // @[Decoupled.scala 259:95]
  wire  ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [3:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [3:0] ram_size_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_en; // @[Decoupled.scala 259:95]
  reg [1:0] ram_source [0:0]; // @[Decoupled.scala 259:95]
  wire  ram_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [1:0] ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [1:0] ram_source_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_en; // @[Decoupled.scala 259:95]
  reg  maybe_full; // @[Decoupled.scala 262:27]
  wire  empty = ~maybe_full; // @[Decoupled.scala 264:28]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
  wire  do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
  assign ram_opcode_io_deq_bits_MPORT_en = 1'h1;
  assign ram_opcode_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_opcode_io_deq_bits_MPORT_data = ram_opcode[ram_opcode_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_opcode_MPORT_data = io_enq_bits_opcode;
  assign ram_opcode_MPORT_addr = 1'h0;
  assign ram_opcode_MPORT_mask = 1'h1;
  assign ram_opcode_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_size_io_deq_bits_MPORT_en = 1'h1;
  assign ram_size_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_size_MPORT_data = io_enq_bits_size;
  assign ram_size_MPORT_addr = 1'h0;
  assign ram_size_MPORT_mask = 1'h1;
  assign ram_size_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_source_io_deq_bits_MPORT_en = 1'h1;
  assign ram_source_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_source_io_deq_bits_MPORT_data = ram_source[ram_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_source_MPORT_data = io_enq_bits_source;
  assign ram_source_MPORT_addr = 1'h0;
  assign ram_source_MPORT_mask = 1'h1;
  assign ram_source_MPORT_en = io_enq_ready & io_enq_valid;
  assign io_enq_ready = ~maybe_full; // @[Decoupled.scala 289:19]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 288:19]
  assign io_deq_bits_opcode = ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_size = ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_source = ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  always @(posedge clock) begin
    if (ram_opcode_MPORT_en & ram_opcode_MPORT_mask) begin
      ram_opcode[ram_opcode_MPORT_addr] <= ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
      ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_source_MPORT_en & ram_source_MPORT_mask) begin
      ram_source[ram_source_MPORT_addr] <= ram_source_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (reset) begin // @[Decoupled.scala 262:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 262:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 279:27]
      maybe_full <= do_enq; // @[Decoupled.scala 280:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_opcode[initvar] = _RAND_0[2:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_size[initvar] = _RAND_1[3:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_source[initvar] = _RAND_2[1:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_3 = {1{`RANDOM}};
  maybe_full = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLError(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [3:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [13:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [3:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output        auto_in_d_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [13:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
  wire  a_clock; // @[Decoupled.scala 361:21]
  wire  a_reset; // @[Decoupled.scala 361:21]
  wire  a_io_enq_ready; // @[Decoupled.scala 361:21]
  wire  a_io_enq_valid; // @[Decoupled.scala 361:21]
  wire [2:0] a_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
  wire [3:0] a_io_enq_bits_size; // @[Decoupled.scala 361:21]
  wire [1:0] a_io_enq_bits_source; // @[Decoupled.scala 361:21]
  wire  a_io_deq_ready; // @[Decoupled.scala 361:21]
  wire  a_io_deq_valid; // @[Decoupled.scala 361:21]
  wire [2:0] a_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
  wire [3:0] a_io_deq_bits_size; // @[Decoupled.scala 361:21]
  wire [1:0] a_io_deq_bits_source; // @[Decoupled.scala 361:21]
  wire  _a_last_T = a_io_deq_ready & a_io_deq_valid; // @[Decoupled.scala 50:35]
  wire [26:0] _a_last_beats1_decode_T_1 = 27'hfff << a_io_deq_bits_size; // @[package.scala 234:77]
  wire [11:0] _a_last_beats1_decode_T_3 = ~_a_last_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
  wire [9:0] a_last_beats1_decode = _a_last_beats1_decode_T_3[11:2]; // @[Edges.scala 219:59]
  wire  a_last_beats1_opdata = ~a_io_deq_bits_opcode[2]; // @[Edges.scala 91:28]
  wire [9:0] a_last_beats1 = a_last_beats1_opdata ? a_last_beats1_decode : 10'h0; // @[Edges.scala 220:14]
  reg [9:0] a_last_counter; // @[Edges.scala 228:27]
  wire [9:0] a_last_counter1 = a_last_counter - 10'h1; // @[Edges.scala 229:28]
  wire  a_last_first = a_last_counter == 10'h0; // @[Edges.scala 230:25]
  wire  a_last = a_last_counter == 10'h1 | a_last_beats1 == 10'h0; // @[Edges.scala 231:37]
  wire  da_valid = a_io_deq_valid & a_last; // @[Error.scala 51:25]
  wire  _T = auto_in_d_ready & da_valid; // @[Decoupled.scala 50:35]
  wire [3:0] da_bits_size = a_io_deq_bits_size; // @[Error.scala 43:18 55:21]
  wire [26:0] _beats1_decode_T_1 = 27'hfff << da_bits_size; // @[package.scala 234:77]
  wire [11:0] _beats1_decode_T_3 = ~_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
  wire [9:0] beats1_decode = _beats1_decode_T_3[11:2]; // @[Edges.scala 219:59]
  wire [2:0] _GEN_4 = 3'h2 == a_io_deq_bits_opcode ? 3'h1 : 3'h0; // @[Error.scala 53:{21,21}]
  wire [2:0] _GEN_5 = 3'h3 == a_io_deq_bits_opcode ? 3'h1 : _GEN_4; // @[Error.scala 53:{21,21}]
  wire [2:0] _GEN_6 = 3'h4 == a_io_deq_bits_opcode ? 3'h1 : _GEN_5; // @[Error.scala 53:{21,21}]
  wire [2:0] _GEN_7 = 3'h5 == a_io_deq_bits_opcode ? 3'h2 : _GEN_6; // @[Error.scala 53:{21,21}]
  wire [2:0] _GEN_8 = 3'h6 == a_io_deq_bits_opcode ? 3'h4 : _GEN_7; // @[Error.scala 53:{21,21}]
  wire [2:0] da_bits_opcode = 3'h7 == a_io_deq_bits_opcode ? 3'h4 : _GEN_8; // @[Error.scala 53:{21,21}]
  wire  beats1_opdata = da_bits_opcode[0]; // @[Edges.scala 105:36]
  wire [9:0] beats1 = beats1_opdata ? beats1_decode : 10'h0; // @[Edges.scala 220:14]
  reg [9:0] counter; // @[Edges.scala 228:27]
  wire [9:0] counter1 = counter - 10'h1; // @[Edges.scala 229:28]
  wire  da_first = counter == 10'h0; // @[Edges.scala 230:25]
  wire  da_last = counter == 10'h1 | beats1 == 10'h0; // @[Edges.scala 231:37]
  TLMonitor_28 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source),
    .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
  );
  Queue_7 a ( // @[Decoupled.scala 361:21]
    .clock(a_clock),
    .reset(a_reset),
    .io_enq_ready(a_io_enq_ready),
    .io_enq_valid(a_io_enq_valid),
    .io_enq_bits_opcode(a_io_enq_bits_opcode),
    .io_enq_bits_size(a_io_enq_bits_size),
    .io_enq_bits_source(a_io_enq_bits_source),
    .io_deq_ready(a_io_deq_ready),
    .io_deq_valid(a_io_deq_valid),
    .io_deq_bits_opcode(a_io_deq_bits_opcode),
    .io_deq_bits_size(a_io_deq_bits_size),
    .io_deq_bits_source(a_io_deq_bits_source)
  );
  assign auto_in_a_ready = a_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
  assign auto_in_d_valid = a_io_deq_valid & a_last; // @[Error.scala 51:25]
  assign auto_in_d_bits_opcode = 3'h7 == a_io_deq_bits_opcode ? 3'h4 : _GEN_8; // @[Error.scala 53:{21,21}]
  assign auto_in_d_bits_size = a_io_deq_bits_size; // @[Error.scala 43:18 55:21]
  assign auto_in_d_bits_source = a_io_deq_bits_source; // @[Error.scala 43:18 56:21]
  assign auto_in_d_bits_corrupt = da_bits_opcode[0]; // @[Edges.scala 105:36]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = a_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = a_io_deq_valid & a_last; // @[Error.scala 51:25]
  assign monitor_io_in_d_bits_opcode = 3'h7 == a_io_deq_bits_opcode ? 3'h4 : _GEN_8; // @[Error.scala 53:{21,21}]
  assign monitor_io_in_d_bits_size = a_io_deq_bits_size; // @[Error.scala 43:18 55:21]
  assign monitor_io_in_d_bits_source = a_io_deq_bits_source; // @[Error.scala 43:18 56:21]
  assign monitor_io_in_d_bits_corrupt = da_bits_opcode[0]; // @[Edges.scala 105:36]
  assign a_clock = clock;
  assign a_reset = reset;
  assign a_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign a_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign a_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign a_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign a_io_deq_ready = auto_in_d_ready & da_last | ~a_last; // @[Error.scala 50:46]
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_last_counter <= 10'h0; // @[Edges.scala 228:27]
    end else if (_a_last_T) begin // @[Edges.scala 234:17]
      if (a_last_first) begin // @[Edges.scala 235:21]
        if (a_last_beats1_opdata) begin // @[Edges.scala 220:14]
          a_last_counter <= a_last_beats1_decode;
        end else begin
          a_last_counter <= 10'h0;
        end
      end else begin
        a_last_counter <= a_last_counter1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      counter <= 10'h0; // @[Edges.scala 228:27]
    end else if (_T) begin // @[Edges.scala 234:17]
      if (da_first) begin // @[Edges.scala 235:21]
        if (beats1_opdata) begin // @[Edges.scala 220:14]
          counter <= beats1_decode;
        end else begin
          counter <= 10'h0;
        end
      end else begin
        counter <= counter1;
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_last_counter = _RAND_0[9:0];
  _RAND_1 = {1{`RANDOM}};
  counter = _RAND_1[9:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLMonitor_29(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [3:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [13:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_param,
  input  [3:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source,
  input         io_in_d_bits_sink,
  input         io_in_d_bits_denied,
  input         io_in_d_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [26:0] _is_aligned_mask_T_1 = 27'hfff << io_in_a_bits_size; // @[package.scala 234:77]
  wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1[11:0]; // @[package.scala 234:46]
  wire [13:0] _GEN_71 = {{2'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [13:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 14'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 4'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire  _T_35 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42]
  wire  _T_42 = _T_35 & source_ok; // @[Parameters.scala 1160:30]
  wire [13:0] _T_45 = io_in_a_bits_address ^ 14'h3000; // @[Parameters.scala 137:31]
  wire [14:0] _T_46 = {1'b0,$signed(_T_45)}; // @[Parameters.scala 137:49]
  wire [14:0] _T_48 = $signed(_T_46) & -15'sh1000; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 15'sh0; // @[Parameters.scala 137:67]
  wire  _T_59 = 4'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_60 = _source_ok_T & _T_59; // @[Mux.scala 27:73]
  wire  _T_74 = _T_35 & _T_49; // @[Parameters.scala 670:56]
  wire  _T_76 = _T_60 & _T_74; // @[Monitor.scala 83:78]
  wire  _T_90 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_94 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_95 = _T_94 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_99 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_103 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_164 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_177 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_211 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_215 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_223 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_245 = _T_42 & _T_74; // @[Monitor.scala 115:71]
  wire  _T_263 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_299 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_300 = io_in_a_bits_mask & _T_299; // @[Monitor.scala 127:31]
  wire  _T_301 = _T_300 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_305 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_317 = io_in_a_bits_size <= 4'h2; // @[Parameters.scala 92:42]
  wire  _T_325 = _T_317 & _T_49; // @[Parameters.scala 670:56]
  wire  _T_327 = _T_42 & _T_325; // @[Monitor.scala 131:74]
  wire  _T_337 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_345 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_377 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_385 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_417 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_429 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  _T_433 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_437 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 312:27]
  wire  _T_441 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
  wire  _T_445 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
  wire  _T_449 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
  wire  _T_453 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_464 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
  wire  _T_468 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
  wire  _T_481 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_501 = _T_449 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
  wire  _T_510 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_527 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_545 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [9:0] a_first_beats1_decode = is_aligned_mask[11:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [9:0] a_first_counter; // @[Edges.scala 228:27]
  wire [9:0] a_first_counter1 = a_first_counter - 10'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 10'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [3:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [13:0] address; // @[Monitor.scala 388:22]
  wire  _T_575 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_576 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_580 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_584 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_588 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_592 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [26:0] _d_first_beats1_decode_T_1 = 27'hfff << io_in_d_bits_size; // @[package.scala 234:77]
  wire [11:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
  wire [9:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[11:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [9:0] d_first_counter; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1 = d_first_counter - 10'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 10'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] param_1; // @[Monitor.scala 536:22]
  reg [3:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  reg  sink; // @[Monitor.scala 539:22]
  reg  denied; // @[Monitor.scala 540:22]
  wire  _T_599 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_600 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_604 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
  wire  _T_608 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_612 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  wire  _T_616 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
  wire  _T_620 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [23:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [9:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [9:0] a_first_counter1_1 = a_first_counter_1 - 10'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 10'h0; // @[Edges.scala 230:25]
  reg [9:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1_1 = d_first_counter_1 - 10'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 10'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [4:0] _a_size_lookup_T = {io_in_d_bits_source, 3'h0}; // @[Monitor.scala 638:65]
  wire [23:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _a_size_lookup_T_5 = 16'h100 - 16'h1; // @[Monitor.scala 609:57]
  wire [23:0] _GEN_75 = {{8'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 638:91]
  wire [23:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_75; // @[Monitor.scala 638:91]
  wire [23:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[23:1]}; // @[Monitor.scala 638:144]
  wire  _T_626 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_629 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [4:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 5'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_77 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_77}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [4:0] _a_sizes_set_T = {io_in_a_bits_source, 3'h0}; // @[Monitor.scala 657:77]
  wire [4:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala 652:72 655:28]
  wire [35:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [35:0] _a_sizes_set_T_1 = _GEN_2 << _a_sizes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_631 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_633 = ~_T_631[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [35:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 36'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_637 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_639 = ~_T_433; // @[Monitor.scala 671:74]
  wire  _T_640 = io_in_d_valid & d_first_1 & ~_T_433; // @[Monitor.scala 671:71]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_433 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 671:90 672:22]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [46:0] _GEN_4 = {{31'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 678:74]
  wire [46:0] _d_sizes_clr_T_5 = _GEN_4 << _a_size_lookup_T; // @[Monitor.scala 678:74]
  wire [3:0] _GEN_22 = _d_first_T & d_first_1 & _T_639 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_23 = _d_first_T & d_first_1 & _T_639 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire [46:0] _GEN_24 = _d_first_T & d_first_1 & _T_639 ? _d_sizes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 678:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_626 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_650 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_652 = _T_650[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_657 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_658 = io_in_d_bits_opcode == _GEN_32 | _T_657; // @[Monitor.scala 685:77]
  wire  _T_662 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_669 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_670 = io_in_d_bits_opcode == _GEN_48 | _T_669; // @[Monitor.scala 689:72]
  wire [7:0] a_size_lookup = _a_size_lookup_T_7[7:0];
  wire [7:0] _GEN_79 = {{4'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_674 = _GEN_79 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_684 = _T_637 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_639; // @[Monitor.scala 694:116]
  wire  _T_686 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set_wo_ready = _GEN_15[2:0];
  wire [2:0] d_clr_wo_ready = _GEN_21[2:0];
  wire  _T_693 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire [2:0] a_set = _GEN_16[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_22[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_19[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_23[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [23:0] a_sizes_set = _GEN_20[23:0];
  wire [23:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [23:0] d_sizes_clr = _GEN_24[23:0];
  wire [23:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala 704:56]
  wire [23:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_702 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [2:0] inflight_1; // @[Monitor.scala 723:35]
  reg [23:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [9:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1_2 = d_first_counter_2 - 10'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 10'h0; // @[Edges.scala 230:25]
  wire [23:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_size_lookup_T; // @[Monitor.scala 747:42]
  wire [23:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_75; // @[Monitor.scala 747:93]
  wire [23:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[23:1]}; // @[Monitor.scala 747:146]
  wire  _T_728 = io_in_d_valid & d_first_2 & _T_433; // @[Monitor.scala 779:71]
  wire [3:0] _GEN_67 = _d_first_T & d_first_2 & _T_433 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 783:90 784:21]
  wire [46:0] _GEN_69 = _d_first_T & d_first_2 & _T_433 ? _d_sizes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 786:21]
  wire [2:0] _T_736 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [7:0] c_size_lookup = _c_size_lookup_T_7[7:0];
  wire  _T_746 = _GEN_79 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [2:0] d_clr_1 = _GEN_67[2:0];
  wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [2:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [23:0] d_sizes_clr_1 = _GEN_69[23:0];
  wire [23:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
  wire [23:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_771 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 10'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 10'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 10'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 24'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 10'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 10'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 3'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 24'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 10'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_164 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_164) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_42 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_42) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_301 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_301) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_327 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_327) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_337 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_337) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_327 & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~_T_327) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_377 & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~_T_377) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_385 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_385 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_385 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_385 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_385 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_385 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_417 & (io_in_a_valid & _T_385 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_385 & ~reset & ~_T_417) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_385 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_385 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_385 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_385 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_429 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_429) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_433 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_433 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_437 & (io_in_d_valid & _T_433 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_433 & _T_2 & ~_T_437) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_441 & (io_in_d_valid & _T_433 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_433 & _T_2 & ~_T_441) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_445 & (io_in_d_valid & _T_433 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_433 & _T_2 & ~_T_445) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_449 & (io_in_d_valid & _T_433 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_433 & _T_2 & ~_T_449) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is denied (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_453 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_453 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_453 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_453 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_437 & (io_in_d_valid & _T_453 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_453 & _T_2 & ~_T_437) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_464 & (io_in_d_valid & _T_453 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_453 & _T_2 & ~_T_464) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid cap param (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_468 & (io_in_d_valid & _T_453 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_453 & _T_2 & ~_T_468) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries toN param (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_445 & (io_in_d_valid & _T_453 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_453 & _T_2 & ~_T_445) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is corrupt (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_481 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_481 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_481 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_481 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_437 & (io_in_d_valid & _T_481 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_481 & _T_2 & ~_T_437) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_464 & (io_in_d_valid & _T_481 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_481 & _T_2 & ~_T_464) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_468 & (io_in_d_valid & _T_481 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_481 & _T_2 & ~_T_468) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries toN param (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_501 & (io_in_d_valid & _T_481 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_481 & _T_2 & ~_T_501) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_510 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_510 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_441 & (io_in_d_valid & _T_510 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_510 & _T_2 & ~_T_441) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid param (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_445 & (io_in_d_valid & _T_510 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_510 & _T_2 & ~_T_445) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is corrupt (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_527 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_527 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_441 & (io_in_d_valid & _T_527 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_527 & _T_2 & ~_T_441) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_501 & (io_in_d_valid & _T_527 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_527 & _T_2 & ~_T_501) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_545 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_545 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_441 & (io_in_d_valid & _T_545 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_545 & _T_2 & ~_T_441) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid param (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_445 & (io_in_d_valid & _T_545 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_545 & _T_2 & ~_T_445) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is corrupt (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_576 & (_T_575 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_575 & ~reset & ~_T_576) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_580 & (_T_575 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_575 & ~reset & ~_T_580) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_584 & (_T_575 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_575 & ~reset & ~_T_584) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_588 & (_T_575 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_575 & ~reset & ~_T_588) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_592 & (_T_575 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_575 & ~reset & ~_T_592) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_600 & (_T_599 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_599 & _T_2 & ~_T_600) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_604 & (_T_599 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_599 & _T_2 & ~_T_604) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel param changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_608 & (_T_599 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_599 & _T_2 & ~_T_608) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_612 & (_T_599 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_599 & _T_2 & ~_T_612) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_616 & (_T_599 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_599 & _T_2 & ~_T_616) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel sink changed with multibeat operation (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_620 & (_T_599 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_599 & _T_2 & ~_T_620) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel denied changed with multibeat operation (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_633 & (_T_629 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_629 & ~reset & ~_T_633) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_652 & (_T_640 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_640 & _T_2 & ~_T_652) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_658 & (_T_640 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_640 & same_cycle_resp & _T_2 & ~_T_658) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_662 & (_T_640 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_640 & same_cycle_resp & _T_2 & ~_T_662) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_670 & (_T_640 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_640 & ~same_cycle_resp & _T_2 & ~_T_670) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_674 & (_T_640 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_640 & ~same_cycle_resp & _T_2 & ~_T_674) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_686 & (_T_684 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_684 & _T_2 & ~_T_686) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_693 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_693) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 3 (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_702 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_702) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_736[0] & (_T_728 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_728 & _T_2 & ~_T_736[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_746 & (_T_728 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_728 & _T_2 & ~_T_746) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_771 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_771) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CanHaveBuiltInDevices.scala:44:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[9:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[13:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[9:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  param_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  size_1 = _RAND_9[3:0];
  _RAND_10 = {1{`RANDOM}};
  source_1 = _RAND_10[1:0];
  _RAND_11 = {1{`RANDOM}};
  sink = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  denied = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  inflight = _RAND_13[2:0];
  _RAND_14 = {1{`RANDOM}};
  inflight_opcodes = _RAND_14[11:0];
  _RAND_15 = {1{`RANDOM}};
  inflight_sizes = _RAND_15[23:0];
  _RAND_16 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_16[9:0];
  _RAND_17 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_17[9:0];
  _RAND_18 = {1{`RANDOM}};
  watchdog = _RAND_18[31:0];
  _RAND_19 = {1{`RANDOM}};
  inflight_1 = _RAND_19[2:0];
  _RAND_20 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_20[23:0];
  _RAND_21 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_21[9:0];
  _RAND_22 = {1{`RANDOM}};
  watchdog_1 = _RAND_22[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_8(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [2:0]  io_enq_bits_opcode,
  input  [2:0]  io_enq_bits_param,
  input  [3:0]  io_enq_bits_size,
  input  [1:0]  io_enq_bits_source,
  input  [13:0] io_enq_bits_address,
  input  [3:0]  io_enq_bits_mask,
  input         io_enq_bits_corrupt,
  input         io_deq_ready,
  output        io_deq_valid,
  output [2:0]  io_deq_bits_opcode,
  output [2:0]  io_deq_bits_param,
  output [3:0]  io_deq_bits_size,
  output [1:0]  io_deq_bits_source,
  output [13:0] io_deq_bits_address,
  output [3:0]  io_deq_bits_mask,
  output        io_deq_bits_corrupt
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
`endif // RANDOMIZE_REG_INIT
  reg [2:0] ram_opcode [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_opcode_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_opcode_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [2:0] ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_en; // @[Decoupled.scala 259:95]
  reg [2:0] ram_param [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_param_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_param_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [2:0] ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_param_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_param_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_param_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_param_MPORT_en; // @[Decoupled.scala 259:95]
  reg [3:0] ram_size [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [3:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [3:0] ram_size_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_en; // @[Decoupled.scala 259:95]
  reg [1:0] ram_source [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [1:0] ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [1:0] ram_source_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_en; // @[Decoupled.scala 259:95]
  reg [13:0] ram_address [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_address_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_address_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [13:0] ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [13:0] ram_address_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_address_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_address_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_address_MPORT_en; // @[Decoupled.scala 259:95]
  reg [3:0] ram_mask [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_mask_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_mask_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [3:0] ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [3:0] ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_mask_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_mask_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_mask_MPORT_en; // @[Decoupled.scala 259:95]
  reg  ram_corrupt [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_en; // @[Decoupled.scala 259:95]
  reg  value; // @[Counter.scala 62:40]
  reg  value_1; // @[Counter.scala 62:40]
  reg  maybe_full; // @[Decoupled.scala 262:27]
  wire  ptr_match = value == value_1; // @[Decoupled.scala 263:33]
  wire  empty = ptr_match & ~maybe_full; // @[Decoupled.scala 264:25]
  wire  full = ptr_match & maybe_full; // @[Decoupled.scala 265:24]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
  wire  do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
  assign ram_opcode_io_deq_bits_MPORT_en = 1'h1;
  assign ram_opcode_io_deq_bits_MPORT_addr = value_1;
  assign ram_opcode_io_deq_bits_MPORT_data = ram_opcode[ram_opcode_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_opcode_MPORT_data = io_enq_bits_opcode;
  assign ram_opcode_MPORT_addr = value;
  assign ram_opcode_MPORT_mask = 1'h1;
  assign ram_opcode_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_param_io_deq_bits_MPORT_en = 1'h1;
  assign ram_param_io_deq_bits_MPORT_addr = value_1;
  assign ram_param_io_deq_bits_MPORT_data = ram_param[ram_param_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_param_MPORT_data = io_enq_bits_param;
  assign ram_param_MPORT_addr = value;
  assign ram_param_MPORT_mask = 1'h1;
  assign ram_param_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_size_io_deq_bits_MPORT_en = 1'h1;
  assign ram_size_io_deq_bits_MPORT_addr = value_1;
  assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_size_MPORT_data = io_enq_bits_size;
  assign ram_size_MPORT_addr = value;
  assign ram_size_MPORT_mask = 1'h1;
  assign ram_size_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_source_io_deq_bits_MPORT_en = 1'h1;
  assign ram_source_io_deq_bits_MPORT_addr = value_1;
  assign ram_source_io_deq_bits_MPORT_data = ram_source[ram_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_source_MPORT_data = io_enq_bits_source;
  assign ram_source_MPORT_addr = value;
  assign ram_source_MPORT_mask = 1'h1;
  assign ram_source_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_address_io_deq_bits_MPORT_en = 1'h1;
  assign ram_address_io_deq_bits_MPORT_addr = value_1;
  assign ram_address_io_deq_bits_MPORT_data = ram_address[ram_address_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_address_MPORT_data = io_enq_bits_address;
  assign ram_address_MPORT_addr = value;
  assign ram_address_MPORT_mask = 1'h1;
  assign ram_address_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_mask_io_deq_bits_MPORT_en = 1'h1;
  assign ram_mask_io_deq_bits_MPORT_addr = value_1;
  assign ram_mask_io_deq_bits_MPORT_data = ram_mask[ram_mask_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_mask_MPORT_data = io_enq_bits_mask;
  assign ram_mask_MPORT_addr = value;
  assign ram_mask_MPORT_mask = 1'h1;
  assign ram_mask_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_corrupt_io_deq_bits_MPORT_en = 1'h1;
  assign ram_corrupt_io_deq_bits_MPORT_addr = value_1;
  assign ram_corrupt_io_deq_bits_MPORT_data = ram_corrupt[ram_corrupt_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_corrupt_MPORT_data = io_enq_bits_corrupt;
  assign ram_corrupt_MPORT_addr = value;
  assign ram_corrupt_MPORT_mask = 1'h1;
  assign ram_corrupt_MPORT_en = io_enq_ready & io_enq_valid;
  assign io_enq_ready = ~full; // @[Decoupled.scala 289:19]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 288:19]
  assign io_deq_bits_opcode = ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_param = ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_size = ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_source = ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_address = ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_mask = ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_corrupt = ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  always @(posedge clock) begin
    if (ram_opcode_MPORT_en & ram_opcode_MPORT_mask) begin
      ram_opcode[ram_opcode_MPORT_addr] <= ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_param_MPORT_en & ram_param_MPORT_mask) begin
      ram_param[ram_param_MPORT_addr] <= ram_param_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
      ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_source_MPORT_en & ram_source_MPORT_mask) begin
      ram_source[ram_source_MPORT_addr] <= ram_source_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_address_MPORT_en & ram_address_MPORT_mask) begin
      ram_address[ram_address_MPORT_addr] <= ram_address_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_mask_MPORT_en & ram_mask_MPORT_mask) begin
      ram_mask[ram_mask_MPORT_addr] <= ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_corrupt_MPORT_en & ram_corrupt_MPORT_mask) begin
      ram_corrupt[ram_corrupt_MPORT_addr] <= ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (reset) begin // @[Counter.scala 62:40]
      value <= 1'h0; // @[Counter.scala 62:40]
    end else if (do_enq) begin // @[Decoupled.scala 272:16]
      value <= value + 1'h1; // @[Counter.scala 78:15]
    end
    if (reset) begin // @[Counter.scala 62:40]
      value_1 <= 1'h0; // @[Counter.scala 62:40]
    end else if (do_deq) begin // @[Decoupled.scala 276:16]
      value_1 <= value_1 + 1'h1; // @[Counter.scala 78:15]
    end
    if (reset) begin // @[Decoupled.scala 262:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 262:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 279:27]
      maybe_full <= do_enq; // @[Decoupled.scala 280:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_opcode[initvar] = _RAND_0[2:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_param[initvar] = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_size[initvar] = _RAND_2[3:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_source[initvar] = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_address[initvar] = _RAND_4[13:0];
  _RAND_5 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_mask[initvar] = _RAND_5[3:0];
  _RAND_6 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_corrupt[initvar] = _RAND_6[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_7 = {1{`RANDOM}};
  value = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  value_1 = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  maybe_full = _RAND_9[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLBuffer_5(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [3:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [13:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [1:0]  auto_in_d_bits_param,
  output [3:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output        auto_in_d_bits_sink,
  output        auto_in_d_bits_denied,
  output [31:0] auto_in_d_bits_data,
  output        auto_in_d_bits_corrupt,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [3:0]  auto_out_a_bits_size,
  output [1:0]  auto_out_a_bits_source,
  output [13:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [3:0]  auto_out_d_bits_size,
  input  [1:0]  auto_out_d_bits_source,
  input         auto_out_d_bits_corrupt
);
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [13:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
  wire  bundleOut_0_a_q_clock; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_reset; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_enq_ready; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_enq_valid; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
  wire [3:0] bundleOut_0_a_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
  wire [1:0] bundleOut_0_a_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
  wire [13:0] bundleOut_0_a_q_io_enq_bits_address; // @[Decoupled.scala 361:21]
  wire [3:0] bundleOut_0_a_q_io_enq_bits_mask; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_enq_bits_corrupt; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_deq_ready; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_deq_valid; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
  wire [3:0] bundleOut_0_a_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
  wire [1:0] bundleOut_0_a_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
  wire [13:0] bundleOut_0_a_q_io_deq_bits_address; // @[Decoupled.scala 361:21]
  wire [3:0] bundleOut_0_a_q_io_deq_bits_mask; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_clock; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_reset; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_enq_ready; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_enq_valid; // @[Decoupled.scala 361:21]
  wire [2:0] bundleIn_0_d_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
  wire [1:0] bundleIn_0_d_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
  wire [3:0] bundleIn_0_d_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
  wire [1:0] bundleIn_0_d_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_enq_bits_sink; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_enq_bits_denied; // @[Decoupled.scala 361:21]
  wire [31:0] bundleIn_0_d_q_io_enq_bits_data; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_enq_bits_corrupt; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_deq_ready; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_deq_valid; // @[Decoupled.scala 361:21]
  wire [2:0] bundleIn_0_d_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
  wire [1:0] bundleIn_0_d_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
  wire [3:0] bundleIn_0_d_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
  wire [1:0] bundleIn_0_d_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_deq_bits_sink; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_deq_bits_denied; // @[Decoupled.scala 361:21]
  wire [31:0] bundleIn_0_d_q_io_deq_bits_data; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
  TLMonitor_29 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_param(monitor_io_in_d_bits_param),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source),
    .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
    .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
    .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
  );
  Queue_8 bundleOut_0_a_q ( // @[Decoupled.scala 361:21]
    .clock(bundleOut_0_a_q_clock),
    .reset(bundleOut_0_a_q_reset),
    .io_enq_ready(bundleOut_0_a_q_io_enq_ready),
    .io_enq_valid(bundleOut_0_a_q_io_enq_valid),
    .io_enq_bits_opcode(bundleOut_0_a_q_io_enq_bits_opcode),
    .io_enq_bits_param(bundleOut_0_a_q_io_enq_bits_param),
    .io_enq_bits_size(bundleOut_0_a_q_io_enq_bits_size),
    .io_enq_bits_source(bundleOut_0_a_q_io_enq_bits_source),
    .io_enq_bits_address(bundleOut_0_a_q_io_enq_bits_address),
    .io_enq_bits_mask(bundleOut_0_a_q_io_enq_bits_mask),
    .io_enq_bits_corrupt(bundleOut_0_a_q_io_enq_bits_corrupt),
    .io_deq_ready(bundleOut_0_a_q_io_deq_ready),
    .io_deq_valid(bundleOut_0_a_q_io_deq_valid),
    .io_deq_bits_opcode(bundleOut_0_a_q_io_deq_bits_opcode),
    .io_deq_bits_param(bundleOut_0_a_q_io_deq_bits_param),
    .io_deq_bits_size(bundleOut_0_a_q_io_deq_bits_size),
    .io_deq_bits_source(bundleOut_0_a_q_io_deq_bits_source),
    .io_deq_bits_address(bundleOut_0_a_q_io_deq_bits_address),
    .io_deq_bits_mask(bundleOut_0_a_q_io_deq_bits_mask),
    .io_deq_bits_corrupt(bundleOut_0_a_q_io_deq_bits_corrupt)
  );
  Queue_6 bundleIn_0_d_q ( // @[Decoupled.scala 361:21]
    .clock(bundleIn_0_d_q_clock),
    .reset(bundleIn_0_d_q_reset),
    .io_enq_ready(bundleIn_0_d_q_io_enq_ready),
    .io_enq_valid(bundleIn_0_d_q_io_enq_valid),
    .io_enq_bits_opcode(bundleIn_0_d_q_io_enq_bits_opcode),
    .io_enq_bits_param(bundleIn_0_d_q_io_enq_bits_param),
    .io_enq_bits_size(bundleIn_0_d_q_io_enq_bits_size),
    .io_enq_bits_source(bundleIn_0_d_q_io_enq_bits_source),
    .io_enq_bits_sink(bundleIn_0_d_q_io_enq_bits_sink),
    .io_enq_bits_denied(bundleIn_0_d_q_io_enq_bits_denied),
    .io_enq_bits_data(bundleIn_0_d_q_io_enq_bits_data),
    .io_enq_bits_corrupt(bundleIn_0_d_q_io_enq_bits_corrupt),
    .io_deq_ready(bundleIn_0_d_q_io_deq_ready),
    .io_deq_valid(bundleIn_0_d_q_io_deq_valid),
    .io_deq_bits_opcode(bundleIn_0_d_q_io_deq_bits_opcode),
    .io_deq_bits_param(bundleIn_0_d_q_io_deq_bits_param),
    .io_deq_bits_size(bundleIn_0_d_q_io_deq_bits_size),
    .io_deq_bits_source(bundleIn_0_d_q_io_deq_bits_source),
    .io_deq_bits_sink(bundleIn_0_d_q_io_deq_bits_sink),
    .io_deq_bits_denied(bundleIn_0_d_q_io_deq_bits_denied),
    .io_deq_bits_data(bundleIn_0_d_q_io_deq_bits_data),
    .io_deq_bits_corrupt(bundleIn_0_d_q_io_deq_bits_corrupt)
  );
  assign auto_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
  assign auto_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_param = bundleIn_0_d_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_source = bundleIn_0_d_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_sink = bundleIn_0_d_q_io_deq_bits_sink; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_denied = bundleIn_0_d_q_io_deq_bits_denied; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_data = bundleIn_0_d_q_io_deq_bits_data; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_corrupt = bundleIn_0_d_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_out_a_valid = bundleOut_0_a_q_io_deq_valid; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_opcode = bundleOut_0_a_q_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_param = bundleOut_0_a_q_io_deq_bits_param; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_size = bundleOut_0_a_q_io_deq_bits_size; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_source = bundleOut_0_a_q_io_deq_bits_source; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_address = bundleOut_0_a_q_io_deq_bits_address; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_mask = bundleOut_0_a_q_io_deq_bits_mask; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_corrupt = bundleOut_0_a_q_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_d_ready = bundleIn_0_d_q_io_enq_ready; // @[Nodes.scala 1207:84 Decoupled.scala 365:17]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_param = bundleIn_0_d_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_source = bundleIn_0_d_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_sink = bundleIn_0_d_q_io_deq_bits_sink; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_denied = bundleIn_0_d_q_io_deq_bits_denied; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_corrupt = bundleIn_0_d_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign bundleOut_0_a_q_clock = clock;
  assign bundleOut_0_a_q_reset = reset;
  assign bundleOut_0_a_q_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_clock = clock;
  assign bundleIn_0_d_q_reset = reset;
  assign bundleIn_0_d_q_io_enq_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_param = 2'h0; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_sink = 1'h0; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_denied = 1'h1; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_data = 32'h0; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_deq_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module ErrorDeviceWrapper(
  input         clock,
  input         reset,
  output        auto_buffer_in_a_ready,
  input         auto_buffer_in_a_valid,
  input  [2:0]  auto_buffer_in_a_bits_opcode,
  input  [2:0]  auto_buffer_in_a_bits_param,
  input  [3:0]  auto_buffer_in_a_bits_size,
  input  [1:0]  auto_buffer_in_a_bits_source,
  input  [13:0] auto_buffer_in_a_bits_address,
  input  [3:0]  auto_buffer_in_a_bits_mask,
  input         auto_buffer_in_a_bits_corrupt,
  input         auto_buffer_in_d_ready,
  output        auto_buffer_in_d_valid,
  output [2:0]  auto_buffer_in_d_bits_opcode,
  output [1:0]  auto_buffer_in_d_bits_param,
  output [3:0]  auto_buffer_in_d_bits_size,
  output [1:0]  auto_buffer_in_d_bits_source,
  output        auto_buffer_in_d_bits_sink,
  output        auto_buffer_in_d_bits_denied,
  output [31:0] auto_buffer_in_d_bits_data,
  output        auto_buffer_in_d_bits_corrupt
);
  wire  error_clock; // @[CanHaveBuiltInDevices.scala 38:29]
  wire  error_reset; // @[CanHaveBuiltInDevices.scala 38:29]
  wire  error_auto_in_a_ready; // @[CanHaveBuiltInDevices.scala 38:29]
  wire  error_auto_in_a_valid; // @[CanHaveBuiltInDevices.scala 38:29]
  wire [2:0] error_auto_in_a_bits_opcode; // @[CanHaveBuiltInDevices.scala 38:29]
  wire [2:0] error_auto_in_a_bits_param; // @[CanHaveBuiltInDevices.scala 38:29]
  wire [3:0] error_auto_in_a_bits_size; // @[CanHaveBuiltInDevices.scala 38:29]
  wire [1:0] error_auto_in_a_bits_source; // @[CanHaveBuiltInDevices.scala 38:29]
  wire [13:0] error_auto_in_a_bits_address; // @[CanHaveBuiltInDevices.scala 38:29]
  wire [3:0] error_auto_in_a_bits_mask; // @[CanHaveBuiltInDevices.scala 38:29]
  wire  error_auto_in_a_bits_corrupt; // @[CanHaveBuiltInDevices.scala 38:29]
  wire  error_auto_in_d_ready; // @[CanHaveBuiltInDevices.scala 38:29]
  wire  error_auto_in_d_valid; // @[CanHaveBuiltInDevices.scala 38:29]
  wire [2:0] error_auto_in_d_bits_opcode; // @[CanHaveBuiltInDevices.scala 38:29]
  wire [3:0] error_auto_in_d_bits_size; // @[CanHaveBuiltInDevices.scala 38:29]
  wire [1:0] error_auto_in_d_bits_source; // @[CanHaveBuiltInDevices.scala 38:29]
  wire  error_auto_in_d_bits_corrupt; // @[CanHaveBuiltInDevices.scala 38:29]
  wire  buffer_clock; // @[Buffer.scala 68:28]
  wire  buffer_reset; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
  wire [13:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_bits_sink; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_bits_denied; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
  wire [13:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_bits_corrupt; // @[Buffer.scala 68:28]
  TLError error ( // @[CanHaveBuiltInDevices.scala 38:29]
    .clock(error_clock),
    .reset(error_reset),
    .auto_in_a_ready(error_auto_in_a_ready),
    .auto_in_a_valid(error_auto_in_a_valid),
    .auto_in_a_bits_opcode(error_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(error_auto_in_a_bits_param),
    .auto_in_a_bits_size(error_auto_in_a_bits_size),
    .auto_in_a_bits_source(error_auto_in_a_bits_source),
    .auto_in_a_bits_address(error_auto_in_a_bits_address),
    .auto_in_a_bits_mask(error_auto_in_a_bits_mask),
    .auto_in_a_bits_corrupt(error_auto_in_a_bits_corrupt),
    .auto_in_d_ready(error_auto_in_d_ready),
    .auto_in_d_valid(error_auto_in_d_valid),
    .auto_in_d_bits_opcode(error_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(error_auto_in_d_bits_size),
    .auto_in_d_bits_source(error_auto_in_d_bits_source),
    .auto_in_d_bits_corrupt(error_auto_in_d_bits_corrupt)
  );
  TLBuffer_5 buffer ( // @[Buffer.scala 68:28]
    .clock(buffer_clock),
    .reset(buffer_reset),
    .auto_in_a_ready(buffer_auto_in_a_ready),
    .auto_in_a_valid(buffer_auto_in_a_valid),
    .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
    .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
    .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
    .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
    .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
    .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
    .auto_in_d_ready(buffer_auto_in_d_ready),
    .auto_in_d_valid(buffer_auto_in_d_valid),
    .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
    .auto_in_d_bits_param(buffer_auto_in_d_bits_param),
    .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
    .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
    .auto_in_d_bits_sink(buffer_auto_in_d_bits_sink),
    .auto_in_d_bits_denied(buffer_auto_in_d_bits_denied),
    .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
    .auto_in_d_bits_corrupt(buffer_auto_in_d_bits_corrupt),
    .auto_out_a_ready(buffer_auto_out_a_ready),
    .auto_out_a_valid(buffer_auto_out_a_valid),
    .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
    .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
    .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
    .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
    .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
    .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
    .auto_out_d_ready(buffer_auto_out_d_ready),
    .auto_out_d_valid(buffer_auto_out_d_valid),
    .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
    .auto_out_d_bits_source(buffer_auto_out_d_bits_source),
    .auto_out_d_bits_corrupt(buffer_auto_out_d_bits_corrupt)
  );
  assign auto_buffer_in_a_ready = buffer_auto_in_a_ready; // @[LazyModule.scala 309:16]
  assign auto_buffer_in_d_valid = buffer_auto_in_d_valid; // @[LazyModule.scala 309:16]
  assign auto_buffer_in_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[LazyModule.scala 309:16]
  assign auto_buffer_in_d_bits_param = buffer_auto_in_d_bits_param; // @[LazyModule.scala 309:16]
  assign auto_buffer_in_d_bits_size = buffer_auto_in_d_bits_size; // @[LazyModule.scala 309:16]
  assign auto_buffer_in_d_bits_source = buffer_auto_in_d_bits_source; // @[LazyModule.scala 309:16]
  assign auto_buffer_in_d_bits_sink = buffer_auto_in_d_bits_sink; // @[LazyModule.scala 309:16]
  assign auto_buffer_in_d_bits_denied = buffer_auto_in_d_bits_denied; // @[LazyModule.scala 309:16]
  assign auto_buffer_in_d_bits_data = buffer_auto_in_d_bits_data; // @[LazyModule.scala 309:16]
  assign auto_buffer_in_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[LazyModule.scala 309:16]
  assign error_clock = clock;
  assign error_reset = reset;
  assign error_auto_in_a_valid = buffer_auto_out_a_valid; // @[LazyModule.scala 296:16]
  assign error_auto_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign error_auto_in_a_bits_param = buffer_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
  assign error_auto_in_a_bits_size = buffer_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign error_auto_in_a_bits_source = buffer_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign error_auto_in_a_bits_address = buffer_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign error_auto_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign error_auto_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
  assign error_auto_in_d_ready = buffer_auto_out_d_ready; // @[LazyModule.scala 296:16]
  assign buffer_clock = clock;
  assign buffer_reset = reset;
  assign buffer_auto_in_a_valid = auto_buffer_in_a_valid; // @[LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_opcode = auto_buffer_in_a_bits_opcode; // @[LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_param = auto_buffer_in_a_bits_param; // @[LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_size = auto_buffer_in_a_bits_size; // @[LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_source = auto_buffer_in_a_bits_source; // @[LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_address = auto_buffer_in_a_bits_address; // @[LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_mask = auto_buffer_in_a_bits_mask; // @[LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_corrupt = auto_buffer_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
  assign buffer_auto_in_d_ready = auto_buffer_in_d_ready; // @[LazyModule.scala 309:16]
  assign buffer_auto_out_a_ready = error_auto_in_a_ready; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_valid = error_auto_in_d_valid; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_opcode = error_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_size = error_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_source = error_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_corrupt = error_auto_in_d_bits_corrupt; // @[LazyModule.scala 296:16]
endmodule
module TLBuffer_6(
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [3:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [29:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [1:0]  auto_in_d_bits_param,
  output [3:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output        auto_in_d_bits_sink,
  output        auto_in_d_bits_denied,
  output [31:0] auto_in_d_bits_data,
  output        auto_in_d_bits_corrupt,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [3:0]  auto_out_a_bits_size,
  output [1:0]  auto_out_a_bits_source,
  output [29:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_param,
  input  [3:0]  auto_out_d_bits_size,
  input  [1:0]  auto_out_d_bits_source,
  input         auto_out_d_bits_sink,
  input         auto_out_d_bits_denied,
  input  [31:0] auto_out_d_bits_data,
  input         auto_out_d_bits_corrupt
);
  assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module TLWidthWidget_4(
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [29:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [1:0]  auto_in_d_bits_param,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output        auto_in_d_bits_sink,
  output        auto_in_d_bits_denied,
  output [31:0] auto_in_d_bits_data,
  output        auto_in_d_bits_corrupt,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [2:0]  auto_out_a_bits_size,
  output [1:0]  auto_out_a_bits_source,
  output [29:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_param,
  input  [2:0]  auto_out_d_bits_size,
  input  [1:0]  auto_out_d_bits_source,
  input         auto_out_d_bits_sink,
  input         auto_out_d_bits_denied,
  input  [31:0] auto_out_d_bits_data,
  input         auto_out_d_bits_corrupt
);
  assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module TLInterconnectCoupler_19(
  output        auto_widget_in_a_ready,
  input         auto_widget_in_a_valid,
  input  [2:0]  auto_widget_in_a_bits_opcode,
  input  [2:0]  auto_widget_in_a_bits_param,
  input  [2:0]  auto_widget_in_a_bits_size,
  input  [1:0]  auto_widget_in_a_bits_source,
  input  [29:0] auto_widget_in_a_bits_address,
  input  [3:0]  auto_widget_in_a_bits_mask,
  input  [31:0] auto_widget_in_a_bits_data,
  input         auto_widget_in_a_bits_corrupt,
  input         auto_widget_in_d_ready,
  output        auto_widget_in_d_valid,
  output [2:0]  auto_widget_in_d_bits_opcode,
  output [1:0]  auto_widget_in_d_bits_param,
  output [2:0]  auto_widget_in_d_bits_size,
  output [1:0]  auto_widget_in_d_bits_source,
  output        auto_widget_in_d_bits_sink,
  output        auto_widget_in_d_bits_denied,
  output [31:0] auto_widget_in_d_bits_data,
  output        auto_widget_in_d_bits_corrupt,
  input         auto_bus_xing_out_a_ready,
  output        auto_bus_xing_out_a_valid,
  output [2:0]  auto_bus_xing_out_a_bits_opcode,
  output [2:0]  auto_bus_xing_out_a_bits_param,
  output [2:0]  auto_bus_xing_out_a_bits_size,
  output [1:0]  auto_bus_xing_out_a_bits_source,
  output [29:0] auto_bus_xing_out_a_bits_address,
  output [3:0]  auto_bus_xing_out_a_bits_mask,
  output [31:0] auto_bus_xing_out_a_bits_data,
  output        auto_bus_xing_out_a_bits_corrupt,
  output        auto_bus_xing_out_d_ready,
  input         auto_bus_xing_out_d_valid,
  input  [2:0]  auto_bus_xing_out_d_bits_opcode,
  input  [1:0]  auto_bus_xing_out_d_bits_param,
  input  [2:0]  auto_bus_xing_out_d_bits_size,
  input  [1:0]  auto_bus_xing_out_d_bits_source,
  input         auto_bus_xing_out_d_bits_sink,
  input         auto_bus_xing_out_d_bits_denied,
  input  [31:0] auto_bus_xing_out_d_bits_data,
  input         auto_bus_xing_out_d_bits_corrupt
);
  wire  widget_auto_in_a_ready; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_a_valid; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_a_bits_opcode; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_a_bits_param; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_a_bits_size; // @[WidthWidget.scala 219:28]
  wire [1:0] widget_auto_in_a_bits_source; // @[WidthWidget.scala 219:28]
  wire [29:0] widget_auto_in_a_bits_address; // @[WidthWidget.scala 219:28]
  wire [3:0] widget_auto_in_a_bits_mask; // @[WidthWidget.scala 219:28]
  wire [31:0] widget_auto_in_a_bits_data; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_a_bits_corrupt; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_d_ready; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_d_valid; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_d_bits_opcode; // @[WidthWidget.scala 219:28]
  wire [1:0] widget_auto_in_d_bits_param; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_d_bits_size; // @[WidthWidget.scala 219:28]
  wire [1:0] widget_auto_in_d_bits_source; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_d_bits_sink; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_d_bits_denied; // @[WidthWidget.scala 219:28]
  wire [31:0] widget_auto_in_d_bits_data; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_d_bits_corrupt; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_a_ready; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_a_valid; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_a_bits_opcode; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_a_bits_param; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_a_bits_size; // @[WidthWidget.scala 219:28]
  wire [1:0] widget_auto_out_a_bits_source; // @[WidthWidget.scala 219:28]
  wire [29:0] widget_auto_out_a_bits_address; // @[WidthWidget.scala 219:28]
  wire [3:0] widget_auto_out_a_bits_mask; // @[WidthWidget.scala 219:28]
  wire [31:0] widget_auto_out_a_bits_data; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_a_bits_corrupt; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_d_ready; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_d_valid; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_d_bits_opcode; // @[WidthWidget.scala 219:28]
  wire [1:0] widget_auto_out_d_bits_param; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_d_bits_size; // @[WidthWidget.scala 219:28]
  wire [1:0] widget_auto_out_d_bits_source; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_d_bits_sink; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_d_bits_denied; // @[WidthWidget.scala 219:28]
  wire [31:0] widget_auto_out_d_bits_data; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_d_bits_corrupt; // @[WidthWidget.scala 219:28]
  TLWidthWidget_4 widget ( // @[WidthWidget.scala 219:28]
    .auto_in_a_ready(widget_auto_in_a_ready),
    .auto_in_a_valid(widget_auto_in_a_valid),
    .auto_in_a_bits_opcode(widget_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(widget_auto_in_a_bits_param),
    .auto_in_a_bits_size(widget_auto_in_a_bits_size),
    .auto_in_a_bits_source(widget_auto_in_a_bits_source),
    .auto_in_a_bits_address(widget_auto_in_a_bits_address),
    .auto_in_a_bits_mask(widget_auto_in_a_bits_mask),
    .auto_in_a_bits_data(widget_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(widget_auto_in_a_bits_corrupt),
    .auto_in_d_ready(widget_auto_in_d_ready),
    .auto_in_d_valid(widget_auto_in_d_valid),
    .auto_in_d_bits_opcode(widget_auto_in_d_bits_opcode),
    .auto_in_d_bits_param(widget_auto_in_d_bits_param),
    .auto_in_d_bits_size(widget_auto_in_d_bits_size),
    .auto_in_d_bits_source(widget_auto_in_d_bits_source),
    .auto_in_d_bits_sink(widget_auto_in_d_bits_sink),
    .auto_in_d_bits_denied(widget_auto_in_d_bits_denied),
    .auto_in_d_bits_data(widget_auto_in_d_bits_data),
    .auto_in_d_bits_corrupt(widget_auto_in_d_bits_corrupt),
    .auto_out_a_ready(widget_auto_out_a_ready),
    .auto_out_a_valid(widget_auto_out_a_valid),
    .auto_out_a_bits_opcode(widget_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(widget_auto_out_a_bits_param),
    .auto_out_a_bits_size(widget_auto_out_a_bits_size),
    .auto_out_a_bits_source(widget_auto_out_a_bits_source),
    .auto_out_a_bits_address(widget_auto_out_a_bits_address),
    .auto_out_a_bits_mask(widget_auto_out_a_bits_mask),
    .auto_out_a_bits_data(widget_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(widget_auto_out_a_bits_corrupt),
    .auto_out_d_ready(widget_auto_out_d_ready),
    .auto_out_d_valid(widget_auto_out_d_valid),
    .auto_out_d_bits_opcode(widget_auto_out_d_bits_opcode),
    .auto_out_d_bits_param(widget_auto_out_d_bits_param),
    .auto_out_d_bits_size(widget_auto_out_d_bits_size),
    .auto_out_d_bits_source(widget_auto_out_d_bits_source),
    .auto_out_d_bits_sink(widget_auto_out_d_bits_sink),
    .auto_out_d_bits_denied(widget_auto_out_d_bits_denied),
    .auto_out_d_bits_data(widget_auto_out_d_bits_data),
    .auto_out_d_bits_corrupt(widget_auto_out_d_bits_corrupt)
  );
  assign auto_widget_in_a_ready = widget_auto_in_a_ready; // @[LazyModule.scala 309:16]
  assign auto_widget_in_d_valid = widget_auto_in_d_valid; // @[LazyModule.scala 309:16]
  assign auto_widget_in_d_bits_opcode = widget_auto_in_d_bits_opcode; // @[LazyModule.scala 309:16]
  assign auto_widget_in_d_bits_param = widget_auto_in_d_bits_param; // @[LazyModule.scala 309:16]
  assign auto_widget_in_d_bits_size = widget_auto_in_d_bits_size; // @[LazyModule.scala 309:16]
  assign auto_widget_in_d_bits_source = widget_auto_in_d_bits_source; // @[LazyModule.scala 309:16]
  assign auto_widget_in_d_bits_sink = widget_auto_in_d_bits_sink; // @[LazyModule.scala 309:16]
  assign auto_widget_in_d_bits_denied = widget_auto_in_d_bits_denied; // @[LazyModule.scala 309:16]
  assign auto_widget_in_d_bits_data = widget_auto_in_d_bits_data; // @[LazyModule.scala 309:16]
  assign auto_widget_in_d_bits_corrupt = widget_auto_in_d_bits_corrupt; // @[LazyModule.scala 309:16]
  assign auto_bus_xing_out_a_valid = widget_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_bus_xing_out_a_bits_opcode = widget_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_bus_xing_out_a_bits_param = widget_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_bus_xing_out_a_bits_size = widget_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_bus_xing_out_a_bits_source = widget_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_bus_xing_out_a_bits_address = widget_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_bus_xing_out_a_bits_mask = widget_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_bus_xing_out_a_bits_data = widget_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_bus_xing_out_a_bits_corrupt = widget_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_bus_xing_out_d_ready = widget_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign widget_auto_in_a_valid = auto_widget_in_a_valid; // @[LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_opcode = auto_widget_in_a_bits_opcode; // @[LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_param = auto_widget_in_a_bits_param; // @[LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_size = auto_widget_in_a_bits_size; // @[LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_source = auto_widget_in_a_bits_source; // @[LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_address = auto_widget_in_a_bits_address; // @[LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_mask = auto_widget_in_a_bits_mask; // @[LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_data = auto_widget_in_a_bits_data; // @[LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_corrupt = auto_widget_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
  assign widget_auto_in_d_ready = auto_widget_in_d_ready; // @[LazyModule.scala 309:16]
  assign widget_auto_out_a_ready = auto_bus_xing_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign widget_auto_out_d_valid = auto_bus_xing_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign widget_auto_out_d_bits_opcode = auto_bus_xing_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign widget_auto_out_d_bits_param = auto_bus_xing_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign widget_auto_out_d_bits_size = auto_bus_xing_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign widget_auto_out_d_bits_source = auto_bus_xing_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign widget_auto_out_d_bits_sink = auto_bus_xing_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign widget_auto_out_d_bits_denied = auto_bus_xing_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign widget_auto_out_d_bits_data = auto_bus_xing_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign widget_auto_out_d_bits_corrupt = auto_bus_xing_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
endmodule
module TLMonitor_30(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [27:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [2:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
  wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
  wire [27:0] _GEN_71 = {{22'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [27:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [27:0] _T_45 = io_in_a_bits_address ^ 28'hc000000; // @[Parameters.scala 137:31]
  wire [28:0] _T_46 = {1'b0,$signed(_T_45)}; // @[Parameters.scala 137:49]
  wire [28:0] _T_48 = $signed(_T_46) & -29'sh4000000; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 29'sh0; // @[Parameters.scala 137:67]
  wire  _T_59 = 3'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_60 = _source_ok_T & _T_59; // @[Mux.scala 27:73]
  wire  _T_76 = _T_60 & _T_49; // @[Monitor.scala 83:78]
  wire  _T_90 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_94 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_95 = _T_94 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_99 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_103 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_164 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_177 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_192 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
  wire  _T_200 = _T_192 & _T_49; // @[Parameters.scala 670:56]
  wire  _T_211 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_215 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_223 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_245 = source_ok & _T_200; // @[Monitor.scala 115:71]
  wire  _T_263 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_299 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_300 = io_in_a_bits_mask & _T_299; // @[Monitor.scala 127:31]
  wire  _T_301 = _T_300 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_305 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_334 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_342 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_371 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_379 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_408 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_420 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  _T_424 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_428 = io_in_d_bits_size >= 3'h2; // @[Monitor.scala 312:27]
  wire  _T_444 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_472 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_501 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_518 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_536 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [3:0] a_first_beats1_decode = is_aligned_mask[5:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] a_first_counter; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1 = a_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [27:0] address; // @[Monitor.scala 388:22]
  wire  _T_566 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_567 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_571 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_575 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_579 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_583 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
  wire [3:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [3:0] d_first_counter; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1 = d_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_590 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_591 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_599 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_603 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [11:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [3:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1_1 = a_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  reg [3:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_1 = d_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [11:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _GEN_76 = {{4'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_76 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_617 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_620 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [34:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [34:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_622 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_624 = ~_T_622[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [34:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_628 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_630 = ~_T_424; // @[Monitor.scala 671:74]
  wire  _T_631 = io_in_d_valid & d_first_1 & ~_T_424; // @[Monitor.scala 671:71]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_424 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 671:90 672:22]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [3:0] _GEN_22 = _d_first_T & d_first_1 & _T_630 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_23 = _d_first_T & d_first_1 & _T_630 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_617 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_641 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_643 = _T_641[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_648 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_649 = io_in_d_bits_opcode == _GEN_32 | _T_648; // @[Monitor.scala 685:77]
  wire  _T_653 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_660 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_661 = io_in_d_bits_opcode == _GEN_48 | _T_660; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_665 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_675 = _T_628 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_630; // @[Monitor.scala 694:116]
  wire  _T_677 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set_wo_ready = _GEN_15[2:0];
  wire [2:0] d_clr_wo_ready = _GEN_21[2:0];
  wire  _T_684 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire [2:0] a_set = _GEN_16[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_22[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_19[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_23[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [11:0] a_sizes_set = _GEN_20[11:0];
  wire [11:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [11:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_693 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [2:0] inflight_1; // @[Monitor.scala 723:35]
  reg [11:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [3:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_2 = d_first_counter_2 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 4'h0; // @[Edges.scala 230:25]
  wire [11:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [15:0] _GEN_87 = {{4'd0}, _c_size_lookup_T_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_87 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_719 = io_in_d_valid & d_first_2 & _T_424; // @[Monitor.scala 779:71]
  wire [3:0] _GEN_67 = _d_first_T & d_first_2 & _T_424 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 783:90 784:21]
  wire [46:0] _GEN_68 = _d_first_T & d_first_2 & _T_424 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 785:21]
  wire [2:0] _T_727 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_737 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [2:0] d_clr_1 = _GEN_67[2:0];
  wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [2:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [11:0] d_opcodes_clr_1 = _GEN_68[11:0];
  wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [11:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_762 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 4'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 4'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 12'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 4'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 4'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 3'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 12'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 4'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_164 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_164) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_200 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_200) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_301 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_301) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_334 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_334) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_371 & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~_T_371) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_408 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_408) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_420 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_420) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at Plic.scala:363:63)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Plic.scala:363:63)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Plic.scala:363:63)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at Plic.scala:363:63)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Plic.scala:363:63)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at Plic.scala:363:63)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Plic.scala:363:63)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Plic.scala:363:63)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Plic.scala:363:63)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_501 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_501 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Plic.scala:363:63)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_518 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_518 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Plic.scala:363:63)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_536 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_536 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Plic.scala:363:63)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_567 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_567) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_571 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_571) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_575 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_575) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_579 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_579) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_583 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_583) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_591 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_591) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Plic.scala:363:63)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_599 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_599) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at Plic.scala:363:63)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_603 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_603) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at Plic.scala:363:63)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_624 & (_T_620 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_620 & ~reset & ~_T_624) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_643 & (_T_631 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & _T_2 & ~_T_643) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Plic.scala:363:63)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_649 & (_T_631 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & same_cycle_resp & _T_2 & ~_T_649) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Plic.scala:363:63)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_653 & (_T_631 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & same_cycle_resp & _T_2 & ~_T_653) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Plic.scala:363:63)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_661 & (_T_631 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & ~same_cycle_resp & _T_2 & ~_T_661) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Plic.scala:363:63)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_665 & (_T_631 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & ~same_cycle_resp & _T_2 & ~_T_665) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Plic.scala:363:63)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_677 & (_T_675 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_675 & _T_2 & ~_T_677) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_684 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_684) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at Plic.scala:363:63)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_693 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_693) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_727[0] & (_T_719 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_719 & _T_2 & ~_T_727[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Plic.scala:363:63)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_737 & (_T_719 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_719 & _T_2 & ~_T_737) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Plic.scala:363:63)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_762 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_762) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Plic.scala:363:63)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[27:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[2:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[1:0];
  _RAND_10 = {1{`RANDOM}};
  inflight = _RAND_10[2:0];
  _RAND_11 = {1{`RANDOM}};
  inflight_opcodes = _RAND_11[11:0];
  _RAND_12 = {1{`RANDOM}};
  inflight_sizes = _RAND_12[11:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[3:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[3:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  inflight_1 = _RAND_16[2:0];
  _RAND_17 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_17[11:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[3:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Repeater_16(
  input         clock,
  input         reset,
  input         io_repeat,
  output        io_full,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [2:0]  io_enq_bits_opcode,
  input  [2:0]  io_enq_bits_param,
  input  [2:0]  io_enq_bits_size,
  input  [1:0]  io_enq_bits_source,
  input  [27:0] io_enq_bits_address,
  input  [3:0]  io_enq_bits_mask,
  input         io_enq_bits_corrupt,
  input         io_deq_ready,
  output        io_deq_valid,
  output [2:0]  io_deq_bits_opcode,
  output [2:0]  io_deq_bits_param,
  output [2:0]  io_deq_bits_size,
  output [1:0]  io_deq_bits_source,
  output [27:0] io_deq_bits_address,
  output [3:0]  io_deq_bits_mask,
  output        io_deq_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
`endif // RANDOMIZE_REG_INIT
  reg  full; // @[Repeater.scala 19:21]
  reg [2:0] saved_opcode; // @[Repeater.scala 20:18]
  reg [2:0] saved_param; // @[Repeater.scala 20:18]
  reg [2:0] saved_size; // @[Repeater.scala 20:18]
  reg [1:0] saved_source; // @[Repeater.scala 20:18]
  reg [27:0] saved_address; // @[Repeater.scala 20:18]
  reg [3:0] saved_mask; // @[Repeater.scala 20:18]
  reg  saved_corrupt; // @[Repeater.scala 20:18]
  wire  _T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
  wire  _GEN_0 = _T & io_repeat | full; // @[Repeater.scala 19:21 28:{38,45}]
  wire  _T_2 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
  assign io_full = full; // @[Repeater.scala 26:11]
  assign io_enq_ready = io_deq_ready & ~full; // @[Repeater.scala 24:32]
  assign io_deq_valid = io_enq_valid | full; // @[Repeater.scala 23:32]
  assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode; // @[Repeater.scala 25:21]
  assign io_deq_bits_param = full ? saved_param : io_enq_bits_param; // @[Repeater.scala 25:21]
  assign io_deq_bits_size = full ? saved_size : io_enq_bits_size; // @[Repeater.scala 25:21]
  assign io_deq_bits_source = full ? saved_source : io_enq_bits_source; // @[Repeater.scala 25:21]
  assign io_deq_bits_address = full ? saved_address : io_enq_bits_address; // @[Repeater.scala 25:21]
  assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask; // @[Repeater.scala 25:21]
  assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt; // @[Repeater.scala 25:21]
  always @(posedge clock) begin
    if (reset) begin // @[Repeater.scala 19:21]
      full <= 1'h0; // @[Repeater.scala 19:21]
    end else if (_T_2 & ~io_repeat) begin // @[Repeater.scala 29:38]
      full <= 1'h0; // @[Repeater.scala 29:45]
    end else begin
      full <= _GEN_0;
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_opcode <= io_enq_bits_opcode; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_param <= io_enq_bits_param; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_size <= io_enq_bits_size; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_source <= io_enq_bits_source; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_address <= io_enq_bits_address; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_mask <= io_enq_bits_mask; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_corrupt <= io_enq_bits_corrupt; // @[Repeater.scala 28:62]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  full = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  saved_opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  saved_param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  saved_size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  saved_source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  saved_address = _RAND_5[27:0];
  _RAND_6 = {1{`RANDOM}};
  saved_mask = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  saved_corrupt = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLFragmenter_15(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [27:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output [31:0] auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [1:0]  auto_out_a_bits_size,
  output [6:0]  auto_out_a_bits_source,
  output [27:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_size,
  input  [6:0]  auto_out_d_bits_source,
  input  [31:0] auto_out_d_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [27:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  repeater_clock; // @[Fragmenter.scala 262:30]
  wire  repeater_reset; // @[Fragmenter.scala 262:30]
  wire  repeater_io_repeat; // @[Fragmenter.scala 262:30]
  wire  repeater_io_full; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
  wire [27:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
  wire [27:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
  reg [3:0] acknum; // @[Fragmenter.scala 189:29]
  reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
  reg  dToggle; // @[Fragmenter.scala 191:30]
  wire [3:0] dFragnum = auto_out_d_bits_source[3:0]; // @[Fragmenter.scala 192:41]
  wire  dFirst = acknum == 4'h0; // @[Fragmenter.scala 193:29]
  wire  dLast = dFragnum == 4'h0; // @[Fragmenter.scala 194:30]
  wire [3:0] _dsizeOH_T = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 64:12]
  wire [2:0] dsizeOH = _dsizeOH_T[2:0]; // @[OneHot.scala 64:27]
  wire [4:0] _dsizeOH1_T_1 = 5'h3 << auto_out_d_bits_size; // @[package.scala 234:77]
  wire [1:0] dsizeOH1 = ~_dsizeOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  dHasData = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  _T_5 = ~reset; // @[Fragmenter.scala 202:16]
  wire  ack_decrement = dHasData | dsizeOH[2]; // @[Fragmenter.scala 204:32]
  wire [5:0] _dFirst_size_T = {dFragnum, 2'h0}; // @[Fragmenter.scala 206:47]
  wire [5:0] _GEN_7 = {{4'd0}, dsizeOH1}; // @[Fragmenter.scala 206:69]
  wire [5:0] _dFirst_size_T_1 = _dFirst_size_T | _GEN_7; // @[Fragmenter.scala 206:69]
  wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala 232:35]
  wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
  wire [6:0] _dFirst_size_T_4 = {1'h0,_dFirst_size_T_1}; // @[Cat.scala 31:58]
  wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
  wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
  wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
  wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
  wire [3:0] _GEN_8 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
  wire [3:0] _dFirst_size_T_8 = _GEN_8 | dFirst_size_lo; // @[OneHot.scala 32:28]
  wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
  wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
  wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
  wire  drop = ~dHasData & ~dLast; // @[Fragmenter.scala 222:30]
  wire  bundleOut_0_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  wire  _T_7 = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
  wire [3:0] _GEN_9 = {{3'd0}, ack_decrement}; // @[Fragmenter.scala 209:55]
  wire [3:0] _acknum_T_1 = acknum - _GEN_9; // @[Fragmenter.scala 209:55]
  wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h2 ? 3'h2 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
  wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
  wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
  wire [8:0] _aFragOH1_T_1 = 9'h3 << aFrag; // @[package.scala 234:77]
  wire [1:0] aFragOH1 = ~_aFragOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  aHasData = ~repeater_io_deq_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] gennum; // @[Fragmenter.scala 291:29]
  wire  aFirst = gennum == 4'h0; // @[Fragmenter.scala 292:29]
  wire [3:0] _old_gennum1_T_2 = gennum - 4'h1; // @[Fragmenter.scala 293:79]
  wire [3:0] old_gennum1 = aFirst ? aOrigOH1[5:2] : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
  wire [3:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
  wire [3:0] new_gennum = ~_new_gennum_T; // @[Fragmenter.scala 294:26]
  reg  aToggle_r; // @[Reg.scala 16:16]
  wire  _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
  wire  aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
  wire  bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  wire  _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
  wire  _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala 302:31]
  wire [5:0] _bundleOut_0_a_bits_address_T = {old_gennum1, 2'h0}; // @[Fragmenter.scala 304:65]
  wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
  wire [5:0] _bundleOut_0_a_bits_address_T_2 = _bundleOut_0_a_bits_address_T | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
  wire [5:0] _GEN_10 = {{4'd0}, aFragOH1}; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_10; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_4 = _bundleOut_0_a_bits_address_T_3 | 6'h3; // @[Fragmenter.scala 304:111]
  wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_4; // @[Fragmenter.scala 304:51]
  wire [27:0] _GEN_11 = {{22'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
  wire [2:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aToggle}; // @[Cat.scala 31:58]
  wire  _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
  TLMonitor_30 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  Repeater_16 repeater ( // @[Fragmenter.scala 262:30]
    .clock(repeater_clock),
    .reset(repeater_reset),
    .io_repeat(repeater_io_repeat),
    .io_full(repeater_io_full),
    .io_enq_ready(repeater_io_enq_ready),
    .io_enq_valid(repeater_io_enq_valid),
    .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
    .io_enq_bits_param(repeater_io_enq_bits_param),
    .io_enq_bits_size(repeater_io_enq_bits_size),
    .io_enq_bits_source(repeater_io_enq_bits_source),
    .io_enq_bits_address(repeater_io_enq_bits_address),
    .io_enq_bits_mask(repeater_io_enq_bits_mask),
    .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
    .io_deq_ready(repeater_io_deq_ready),
    .io_deq_valid(repeater_io_deq_valid),
    .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
    .io_deq_bits_param(repeater_io_deq_bits_param),
    .io_deq_bits_size(repeater_io_deq_bits_size),
    .io_deq_bits_source(repeater_io_deq_bits_source),
    .io_deq_bits_address(repeater_io_deq_bits_address),
    .io_deq_bits_mask(repeater_io_deq_bits_mask),
    .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
  );
  assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign auto_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign auto_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_size = aFrag[1:0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
  assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,new_gennum}; // @[Cat.scala 31:58]
  assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_11; // @[Fragmenter.scala 304:49]
  assign auto_out_a_bits_mask = repeater_io_full ? 4'hf : auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = repeater_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign repeater_clock = clock;
  assign repeater_reset = reset;
  assign repeater_io_repeat = ~aHasData & new_gennum != 4'h0; // @[Fragmenter.scala 302:41]
  assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  always @(posedge clock) begin
    if (reset) begin // @[Fragmenter.scala 189:29]
      acknum <= 4'h0; // @[Fragmenter.scala 189:29]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 209:24]
        acknum <= dFragnum;
      end else begin
        acknum <= _acknum_T_1;
      end
    end
    if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
      end
    end
    if (reset) begin // @[Fragmenter.scala 191:30]
      dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dToggle <= auto_out_d_bits_source[4]; // @[Fragmenter.scala 212:21]
      end
    end
    if (reset) begin // @[Fragmenter.scala 291:29]
      gennum <= 4'h0; // @[Fragmenter.scala 291:29]
    end else if (_T_8) begin // @[Fragmenter.scala 300:29]
      gennum <= new_gennum; // @[Fragmenter.scala 300:38]
    end
    if (aFirst) begin // @[Reg.scala 17:18]
      aToggle_r <= dToggle; // @[Reg.scala 17:22]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~repeater_io_full | _repeater_io_repeat_T) & _T_5) begin
          $fatal; // @[Fragmenter.scala 309:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(~repeater_io_full | _repeater_io_repeat_T)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Fragmenter.scala:309 assert (!repeater.io.full || !aHasData)\n"
            ); // @[Fragmenter.scala 309:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_9 | repeater_io_deq_bits_mask == 4'hf) & _T_5) begin
          $fatal; // @[Fragmenter.scala 312:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask == 4'hf)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
            ); // @[Fragmenter.scala 312:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  acknum = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  dOrig = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  dToggle = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  gennum = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  aToggle_r = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLInterconnectCoupler_20(
  input         clock,
  input         reset,
  input         auto_fragmenter_out_a_ready,
  output        auto_fragmenter_out_a_valid,
  output [2:0]  auto_fragmenter_out_a_bits_opcode,
  output [2:0]  auto_fragmenter_out_a_bits_param,
  output [1:0]  auto_fragmenter_out_a_bits_size,
  output [6:0]  auto_fragmenter_out_a_bits_source,
  output [27:0] auto_fragmenter_out_a_bits_address,
  output [3:0]  auto_fragmenter_out_a_bits_mask,
  output [31:0] auto_fragmenter_out_a_bits_data,
  output        auto_fragmenter_out_a_bits_corrupt,
  output        auto_fragmenter_out_d_ready,
  input         auto_fragmenter_out_d_valid,
  input  [2:0]  auto_fragmenter_out_d_bits_opcode,
  input  [1:0]  auto_fragmenter_out_d_bits_size,
  input  [6:0]  auto_fragmenter_out_d_bits_source,
  input  [31:0] auto_fragmenter_out_d_bits_data,
  output        auto_tl_in_a_ready,
  input         auto_tl_in_a_valid,
  input  [2:0]  auto_tl_in_a_bits_opcode,
  input  [2:0]  auto_tl_in_a_bits_param,
  input  [2:0]  auto_tl_in_a_bits_size,
  input  [1:0]  auto_tl_in_a_bits_source,
  input  [27:0] auto_tl_in_a_bits_address,
  input  [3:0]  auto_tl_in_a_bits_mask,
  input  [31:0] auto_tl_in_a_bits_data,
  input         auto_tl_in_a_bits_corrupt,
  input         auto_tl_in_d_ready,
  output        auto_tl_in_d_valid,
  output [2:0]  auto_tl_in_d_bits_opcode,
  output [2:0]  auto_tl_in_d_bits_size,
  output [1:0]  auto_tl_in_d_bits_source,
  output [31:0] auto_tl_in_d_bits_data
);
  wire  fragmenter_clock; // @[Fragmenter.scala 333:34]
  wire  fragmenter_reset; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [27:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [27:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
  TLFragmenter_15 fragmenter ( // @[Fragmenter.scala 333:34]
    .clock(fragmenter_clock),
    .reset(fragmenter_reset),
    .auto_in_a_ready(fragmenter_auto_in_a_ready),
    .auto_in_a_valid(fragmenter_auto_in_a_valid),
    .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
    .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
    .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
    .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
    .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
    .auto_in_a_bits_data(fragmenter_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
    .auto_in_d_ready(fragmenter_auto_in_d_ready),
    .auto_in_d_valid(fragmenter_auto_in_d_valid),
    .auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
    .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
    .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
    .auto_out_a_ready(fragmenter_auto_out_a_ready),
    .auto_out_a_valid(fragmenter_auto_out_a_valid),
    .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
    .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
    .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
    .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
    .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
    .auto_out_a_bits_data(fragmenter_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
    .auto_out_d_ready(fragmenter_auto_out_d_ready),
    .auto_out_d_valid(fragmenter_auto_out_d_valid),
    .auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
    .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
    .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
  );
  assign auto_fragmenter_out_a_valid = fragmenter_auto_out_a_valid; // @[LazyModule.scala 311:12]
  assign auto_fragmenter_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[LazyModule.scala 311:12]
  assign auto_fragmenter_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[LazyModule.scala 311:12]
  assign auto_fragmenter_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[LazyModule.scala 311:12]
  assign auto_fragmenter_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[LazyModule.scala 311:12]
  assign auto_fragmenter_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[LazyModule.scala 311:12]
  assign auto_fragmenter_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[LazyModule.scala 311:12]
  assign auto_fragmenter_out_a_bits_data = fragmenter_auto_out_a_bits_data; // @[LazyModule.scala 311:12]
  assign auto_fragmenter_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
  assign auto_fragmenter_out_d_ready = fragmenter_auto_out_d_ready; // @[LazyModule.scala 311:12]
  assign auto_tl_in_a_ready = fragmenter_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_valid = fragmenter_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_size = fragmenter_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_source = fragmenter_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_data = fragmenter_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign fragmenter_clock = clock;
  assign fragmenter_reset = reset;
  assign fragmenter_auto_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_data = auto_tl_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_out_a_ready = auto_fragmenter_out_a_ready; // @[LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_valid = auto_fragmenter_out_d_valid; // @[LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_opcode = auto_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_size = auto_fragmenter_out_d_bits_size; // @[LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_source = auto_fragmenter_out_d_bits_source; // @[LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_data = auto_fragmenter_out_d_bits_data; // @[LazyModule.scala 311:12]
endmodule
module TLMonitor_31(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [25:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [2:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
  wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
  wire [25:0] _GEN_71 = {{20'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [25:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [25:0] _T_45 = io_in_a_bits_address ^ 26'h2000000; // @[Parameters.scala 137:31]
  wire [26:0] _T_46 = {1'b0,$signed(_T_45)}; // @[Parameters.scala 137:49]
  wire [26:0] _T_48 = $signed(_T_46) & -27'sh10000; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 27'sh0; // @[Parameters.scala 137:67]
  wire  _T_59 = 3'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_60 = _source_ok_T & _T_59; // @[Mux.scala 27:73]
  wire  _T_76 = _T_60 & _T_49; // @[Monitor.scala 83:78]
  wire  _T_90 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_94 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_95 = _T_94 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_99 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_103 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_164 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_177 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_192 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
  wire  _T_200 = _T_192 & _T_49; // @[Parameters.scala 670:56]
  wire  _T_211 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_215 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_223 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_245 = source_ok & _T_200; // @[Monitor.scala 115:71]
  wire  _T_263 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_299 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_300 = io_in_a_bits_mask & _T_299; // @[Monitor.scala 127:31]
  wire  _T_301 = _T_300 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_305 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_334 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_342 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_371 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_379 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_408 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_420 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  _T_424 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_428 = io_in_d_bits_size >= 3'h2; // @[Monitor.scala 312:27]
  wire  _T_444 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_472 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_501 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_518 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_536 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [3:0] a_first_beats1_decode = is_aligned_mask[5:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] a_first_counter; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1 = a_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [25:0] address; // @[Monitor.scala 388:22]
  wire  _T_566 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_567 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_571 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_575 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_579 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_583 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
  wire [3:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [3:0] d_first_counter; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1 = d_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_590 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_591 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_599 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_603 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [11:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [3:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1_1 = a_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  reg [3:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_1 = d_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [11:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _GEN_76 = {{4'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_76 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_617 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_620 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [34:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [34:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_622 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_624 = ~_T_622[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [34:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_628 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_630 = ~_T_424; // @[Monitor.scala 671:74]
  wire  _T_631 = io_in_d_valid & d_first_1 & ~_T_424; // @[Monitor.scala 671:71]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [3:0] _GEN_22 = _d_first_T & d_first_1 & _T_630 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_23 = _d_first_T & d_first_1 & _T_630 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_617 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_641 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_643 = _T_641[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_648 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_649 = io_in_d_bits_opcode == _GEN_32 | _T_648; // @[Monitor.scala 685:77]
  wire  _T_653 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_660 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_661 = io_in_d_bits_opcode == _GEN_48 | _T_660; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_665 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_675 = _T_628 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_630; // @[Monitor.scala 694:116]
  wire  _T_677 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set = _GEN_16[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_22[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_19[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_23[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [11:0] a_sizes_set = _GEN_20[11:0];
  wire [11:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [11:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_686 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [2:0] inflight_1; // @[Monitor.scala 723:35]
  reg [11:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [3:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_2 = d_first_counter_2 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 4'h0; // @[Edges.scala 230:25]
  wire [11:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [15:0] _GEN_87 = {{4'd0}, _c_size_lookup_T_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_87 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_712 = io_in_d_valid & d_first_2 & _T_424; // @[Monitor.scala 779:71]
  wire [3:0] _GEN_67 = _d_first_T & d_first_2 & _T_424 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 783:90 784:21]
  wire [46:0] _GEN_68 = _d_first_T & d_first_2 & _T_424 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 785:21]
  wire [2:0] _T_720 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_730 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [2:0] d_clr_1 = _GEN_67[2:0];
  wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [2:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [11:0] d_opcodes_clr_1 = _GEN_68[11:0];
  wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [11:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_750 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 4'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 4'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 12'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 4'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 4'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 3'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 12'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 4'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_164 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_164) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_200 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_200) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_301 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_301) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_334 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_334) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_371 & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~_T_371) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_408 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_408) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_420 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_420) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at CLINT.scala:111:65)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CLINT.scala:111:65)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CLINT.scala:111:65)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CLINT.scala:111:65)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CLINT.scala:111:65)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at CLINT.scala:111:65)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CLINT.scala:111:65)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CLINT.scala:111:65)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CLINT.scala:111:65)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_501 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_501 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CLINT.scala:111:65)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_518 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_518 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CLINT.scala:111:65)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_536 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_536 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CLINT.scala:111:65)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_567 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_567) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_571 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_571) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_575 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_575) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_579 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_579) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_583 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_583) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_591 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_591) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CLINT.scala:111:65)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_599 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_599) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at CLINT.scala:111:65)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_603 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_603) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at CLINT.scala:111:65)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_624 & (_T_620 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_620 & ~reset & ~_T_624) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_643 & (_T_631 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & _T_2 & ~_T_643) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CLINT.scala:111:65)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_649 & (_T_631 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & same_cycle_resp & _T_2 & ~_T_649) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CLINT.scala:111:65)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_653 & (_T_631 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & same_cycle_resp & _T_2 & ~_T_653) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CLINT.scala:111:65)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_661 & (_T_631 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & ~same_cycle_resp & _T_2 & ~_T_661) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CLINT.scala:111:65)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_665 & (_T_631 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & ~same_cycle_resp & _T_2 & ~_T_665) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CLINT.scala:111:65)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_677 & (_T_675 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_675 & _T_2 & ~_T_677) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_686 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_686) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_720[0] & (_T_712 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_712 & _T_2 & ~_T_720[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CLINT.scala:111:65)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_730 & (_T_712 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_712 & _T_2 & ~_T_730) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CLINT.scala:111:65)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_750 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_750) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CLINT.scala:111:65)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[25:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[2:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[1:0];
  _RAND_10 = {1{`RANDOM}};
  inflight = _RAND_10[2:0];
  _RAND_11 = {1{`RANDOM}};
  inflight_opcodes = _RAND_11[11:0];
  _RAND_12 = {1{`RANDOM}};
  inflight_sizes = _RAND_12[11:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[3:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[3:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  inflight_1 = _RAND_16[2:0];
  _RAND_17 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_17[11:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[3:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Repeater_17(
  input         clock,
  input         reset,
  input         io_repeat,
  output        io_full,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [2:0]  io_enq_bits_opcode,
  input  [2:0]  io_enq_bits_param,
  input  [2:0]  io_enq_bits_size,
  input  [1:0]  io_enq_bits_source,
  input  [25:0] io_enq_bits_address,
  input  [3:0]  io_enq_bits_mask,
  input         io_enq_bits_corrupt,
  input         io_deq_ready,
  output        io_deq_valid,
  output [2:0]  io_deq_bits_opcode,
  output [2:0]  io_deq_bits_param,
  output [2:0]  io_deq_bits_size,
  output [1:0]  io_deq_bits_source,
  output [25:0] io_deq_bits_address,
  output [3:0]  io_deq_bits_mask,
  output        io_deq_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
`endif // RANDOMIZE_REG_INIT
  reg  full; // @[Repeater.scala 19:21]
  reg [2:0] saved_opcode; // @[Repeater.scala 20:18]
  reg [2:0] saved_param; // @[Repeater.scala 20:18]
  reg [2:0] saved_size; // @[Repeater.scala 20:18]
  reg [1:0] saved_source; // @[Repeater.scala 20:18]
  reg [25:0] saved_address; // @[Repeater.scala 20:18]
  reg [3:0] saved_mask; // @[Repeater.scala 20:18]
  reg  saved_corrupt; // @[Repeater.scala 20:18]
  wire  _T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
  wire  _GEN_0 = _T & io_repeat | full; // @[Repeater.scala 19:21 28:{38,45}]
  wire  _T_2 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
  assign io_full = full; // @[Repeater.scala 26:11]
  assign io_enq_ready = io_deq_ready & ~full; // @[Repeater.scala 24:32]
  assign io_deq_valid = io_enq_valid | full; // @[Repeater.scala 23:32]
  assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode; // @[Repeater.scala 25:21]
  assign io_deq_bits_param = full ? saved_param : io_enq_bits_param; // @[Repeater.scala 25:21]
  assign io_deq_bits_size = full ? saved_size : io_enq_bits_size; // @[Repeater.scala 25:21]
  assign io_deq_bits_source = full ? saved_source : io_enq_bits_source; // @[Repeater.scala 25:21]
  assign io_deq_bits_address = full ? saved_address : io_enq_bits_address; // @[Repeater.scala 25:21]
  assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask; // @[Repeater.scala 25:21]
  assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt; // @[Repeater.scala 25:21]
  always @(posedge clock) begin
    if (reset) begin // @[Repeater.scala 19:21]
      full <= 1'h0; // @[Repeater.scala 19:21]
    end else if (_T_2 & ~io_repeat) begin // @[Repeater.scala 29:38]
      full <= 1'h0; // @[Repeater.scala 29:45]
    end else begin
      full <= _GEN_0;
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_opcode <= io_enq_bits_opcode; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_param <= io_enq_bits_param; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_size <= io_enq_bits_size; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_source <= io_enq_bits_source; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_address <= io_enq_bits_address; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_mask <= io_enq_bits_mask; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_corrupt <= io_enq_bits_corrupt; // @[Repeater.scala 28:62]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  full = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  saved_opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  saved_param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  saved_size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  saved_source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  saved_address = _RAND_5[25:0];
  _RAND_6 = {1{`RANDOM}};
  saved_mask = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  saved_corrupt = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLFragmenter_16(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [25:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output [31:0] auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [1:0]  auto_out_a_bits_size,
  output [6:0]  auto_out_a_bits_source,
  output [25:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_size,
  input  [6:0]  auto_out_d_bits_source,
  input  [31:0] auto_out_d_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [25:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  repeater_clock; // @[Fragmenter.scala 262:30]
  wire  repeater_reset; // @[Fragmenter.scala 262:30]
  wire  repeater_io_repeat; // @[Fragmenter.scala 262:30]
  wire  repeater_io_full; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
  wire [25:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
  wire [25:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
  reg [3:0] acknum; // @[Fragmenter.scala 189:29]
  reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
  reg  dToggle; // @[Fragmenter.scala 191:30]
  wire [3:0] dFragnum = auto_out_d_bits_source[3:0]; // @[Fragmenter.scala 192:41]
  wire  dFirst = acknum == 4'h0; // @[Fragmenter.scala 193:29]
  wire  dLast = dFragnum == 4'h0; // @[Fragmenter.scala 194:30]
  wire [3:0] _dsizeOH_T = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 64:12]
  wire [2:0] dsizeOH = _dsizeOH_T[2:0]; // @[OneHot.scala 64:27]
  wire [4:0] _dsizeOH1_T_1 = 5'h3 << auto_out_d_bits_size; // @[package.scala 234:77]
  wire [1:0] dsizeOH1 = ~_dsizeOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  dHasData = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  _T_5 = ~reset; // @[Fragmenter.scala 202:16]
  wire  ack_decrement = dHasData | dsizeOH[2]; // @[Fragmenter.scala 204:32]
  wire [5:0] _dFirst_size_T = {dFragnum, 2'h0}; // @[Fragmenter.scala 206:47]
  wire [5:0] _GEN_7 = {{4'd0}, dsizeOH1}; // @[Fragmenter.scala 206:69]
  wire [5:0] _dFirst_size_T_1 = _dFirst_size_T | _GEN_7; // @[Fragmenter.scala 206:69]
  wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala 232:35]
  wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
  wire [6:0] _dFirst_size_T_4 = {1'h0,_dFirst_size_T_1}; // @[Cat.scala 31:58]
  wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
  wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
  wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
  wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
  wire [3:0] _GEN_8 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
  wire [3:0] _dFirst_size_T_8 = _GEN_8 | dFirst_size_lo; // @[OneHot.scala 32:28]
  wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
  wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
  wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
  wire  drop = ~dHasData & ~dLast; // @[Fragmenter.scala 222:30]
  wire  bundleOut_0_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  wire  _T_7 = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
  wire [3:0] _GEN_9 = {{3'd0}, ack_decrement}; // @[Fragmenter.scala 209:55]
  wire [3:0] _acknum_T_1 = acknum - _GEN_9; // @[Fragmenter.scala 209:55]
  wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h2 ? 3'h2 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
  wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
  wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
  wire [8:0] _aFragOH1_T_1 = 9'h3 << aFrag; // @[package.scala 234:77]
  wire [1:0] aFragOH1 = ~_aFragOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  aHasData = ~repeater_io_deq_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] gennum; // @[Fragmenter.scala 291:29]
  wire  aFirst = gennum == 4'h0; // @[Fragmenter.scala 292:29]
  wire [3:0] _old_gennum1_T_2 = gennum - 4'h1; // @[Fragmenter.scala 293:79]
  wire [3:0] old_gennum1 = aFirst ? aOrigOH1[5:2] : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
  wire [3:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
  wire [3:0] new_gennum = ~_new_gennum_T; // @[Fragmenter.scala 294:26]
  reg  aToggle_r; // @[Reg.scala 16:16]
  wire  _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
  wire  aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
  wire  bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  wire  _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
  wire  _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala 302:31]
  wire [5:0] _bundleOut_0_a_bits_address_T = {old_gennum1, 2'h0}; // @[Fragmenter.scala 304:65]
  wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
  wire [5:0] _bundleOut_0_a_bits_address_T_2 = _bundleOut_0_a_bits_address_T | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
  wire [5:0] _GEN_10 = {{4'd0}, aFragOH1}; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_10; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_4 = _bundleOut_0_a_bits_address_T_3 | 6'h3; // @[Fragmenter.scala 304:111]
  wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_4; // @[Fragmenter.scala 304:51]
  wire [25:0] _GEN_11 = {{20'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
  wire [2:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aToggle}; // @[Cat.scala 31:58]
  wire  _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
  TLMonitor_31 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  Repeater_17 repeater ( // @[Fragmenter.scala 262:30]
    .clock(repeater_clock),
    .reset(repeater_reset),
    .io_repeat(repeater_io_repeat),
    .io_full(repeater_io_full),
    .io_enq_ready(repeater_io_enq_ready),
    .io_enq_valid(repeater_io_enq_valid),
    .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
    .io_enq_bits_param(repeater_io_enq_bits_param),
    .io_enq_bits_size(repeater_io_enq_bits_size),
    .io_enq_bits_source(repeater_io_enq_bits_source),
    .io_enq_bits_address(repeater_io_enq_bits_address),
    .io_enq_bits_mask(repeater_io_enq_bits_mask),
    .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
    .io_deq_ready(repeater_io_deq_ready),
    .io_deq_valid(repeater_io_deq_valid),
    .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
    .io_deq_bits_param(repeater_io_deq_bits_param),
    .io_deq_bits_size(repeater_io_deq_bits_size),
    .io_deq_bits_source(repeater_io_deq_bits_source),
    .io_deq_bits_address(repeater_io_deq_bits_address),
    .io_deq_bits_mask(repeater_io_deq_bits_mask),
    .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
  );
  assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign auto_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign auto_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_size = aFrag[1:0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
  assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,new_gennum}; // @[Cat.scala 31:58]
  assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_11; // @[Fragmenter.scala 304:49]
  assign auto_out_a_bits_mask = repeater_io_full ? 4'hf : auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = repeater_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign repeater_clock = clock;
  assign repeater_reset = reset;
  assign repeater_io_repeat = ~aHasData & new_gennum != 4'h0; // @[Fragmenter.scala 302:41]
  assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  always @(posedge clock) begin
    if (reset) begin // @[Fragmenter.scala 189:29]
      acknum <= 4'h0; // @[Fragmenter.scala 189:29]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 209:24]
        acknum <= dFragnum;
      end else begin
        acknum <= _acknum_T_1;
      end
    end
    if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
      end
    end
    if (reset) begin // @[Fragmenter.scala 191:30]
      dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dToggle <= auto_out_d_bits_source[4]; // @[Fragmenter.scala 212:21]
      end
    end
    if (reset) begin // @[Fragmenter.scala 291:29]
      gennum <= 4'h0; // @[Fragmenter.scala 291:29]
    end else if (_T_8) begin // @[Fragmenter.scala 300:29]
      gennum <= new_gennum; // @[Fragmenter.scala 300:38]
    end
    if (aFirst) begin // @[Reg.scala 17:18]
      aToggle_r <= dToggle; // @[Reg.scala 17:22]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~repeater_io_full | _repeater_io_repeat_T) & _T_5) begin
          $fatal; // @[Fragmenter.scala 309:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(~repeater_io_full | _repeater_io_repeat_T)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Fragmenter.scala:309 assert (!repeater.io.full || !aHasData)\n"
            ); // @[Fragmenter.scala 309:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_9 | repeater_io_deq_bits_mask == 4'hf) & _T_5) begin
          $fatal; // @[Fragmenter.scala 312:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask == 4'hf)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
            ); // @[Fragmenter.scala 312:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  acknum = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  dOrig = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  dToggle = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  gennum = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  aToggle_r = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLInterconnectCoupler_21(
  input         clock,
  input         reset,
  input         auto_fragmenter_out_a_ready,
  output        auto_fragmenter_out_a_valid,
  output [2:0]  auto_fragmenter_out_a_bits_opcode,
  output [2:0]  auto_fragmenter_out_a_bits_param,
  output [1:0]  auto_fragmenter_out_a_bits_size,
  output [6:0]  auto_fragmenter_out_a_bits_source,
  output [25:0] auto_fragmenter_out_a_bits_address,
  output [3:0]  auto_fragmenter_out_a_bits_mask,
  output [31:0] auto_fragmenter_out_a_bits_data,
  output        auto_fragmenter_out_a_bits_corrupt,
  output        auto_fragmenter_out_d_ready,
  input         auto_fragmenter_out_d_valid,
  input  [2:0]  auto_fragmenter_out_d_bits_opcode,
  input  [1:0]  auto_fragmenter_out_d_bits_size,
  input  [6:0]  auto_fragmenter_out_d_bits_source,
  input  [31:0] auto_fragmenter_out_d_bits_data,
  output        auto_tl_in_a_ready,
  input         auto_tl_in_a_valid,
  input  [2:0]  auto_tl_in_a_bits_opcode,
  input  [2:0]  auto_tl_in_a_bits_param,
  input  [2:0]  auto_tl_in_a_bits_size,
  input  [1:0]  auto_tl_in_a_bits_source,
  input  [25:0] auto_tl_in_a_bits_address,
  input  [3:0]  auto_tl_in_a_bits_mask,
  input  [31:0] auto_tl_in_a_bits_data,
  input         auto_tl_in_a_bits_corrupt,
  input         auto_tl_in_d_ready,
  output        auto_tl_in_d_valid,
  output [2:0]  auto_tl_in_d_bits_opcode,
  output [2:0]  auto_tl_in_d_bits_size,
  output [1:0]  auto_tl_in_d_bits_source,
  output [31:0] auto_tl_in_d_bits_data
);
  wire  fragmenter_clock; // @[Fragmenter.scala 333:34]
  wire  fragmenter_reset; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [25:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [25:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
  TLFragmenter_16 fragmenter ( // @[Fragmenter.scala 333:34]
    .clock(fragmenter_clock),
    .reset(fragmenter_reset),
    .auto_in_a_ready(fragmenter_auto_in_a_ready),
    .auto_in_a_valid(fragmenter_auto_in_a_valid),
    .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
    .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
    .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
    .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
    .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
    .auto_in_a_bits_data(fragmenter_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
    .auto_in_d_ready(fragmenter_auto_in_d_ready),
    .auto_in_d_valid(fragmenter_auto_in_d_valid),
    .auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
    .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
    .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
    .auto_out_a_ready(fragmenter_auto_out_a_ready),
    .auto_out_a_valid(fragmenter_auto_out_a_valid),
    .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
    .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
    .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
    .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
    .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
    .auto_out_a_bits_data(fragmenter_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
    .auto_out_d_ready(fragmenter_auto_out_d_ready),
    .auto_out_d_valid(fragmenter_auto_out_d_valid),
    .auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
    .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
    .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
  );
  assign auto_fragmenter_out_a_valid = fragmenter_auto_out_a_valid; // @[LazyModule.scala 311:12]
  assign auto_fragmenter_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[LazyModule.scala 311:12]
  assign auto_fragmenter_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[LazyModule.scala 311:12]
  assign auto_fragmenter_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[LazyModule.scala 311:12]
  assign auto_fragmenter_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[LazyModule.scala 311:12]
  assign auto_fragmenter_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[LazyModule.scala 311:12]
  assign auto_fragmenter_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[LazyModule.scala 311:12]
  assign auto_fragmenter_out_a_bits_data = fragmenter_auto_out_a_bits_data; // @[LazyModule.scala 311:12]
  assign auto_fragmenter_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
  assign auto_fragmenter_out_d_ready = fragmenter_auto_out_d_ready; // @[LazyModule.scala 311:12]
  assign auto_tl_in_a_ready = fragmenter_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_valid = fragmenter_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_size = fragmenter_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_source = fragmenter_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_data = fragmenter_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign fragmenter_clock = clock;
  assign fragmenter_reset = reset;
  assign fragmenter_auto_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_data = auto_tl_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_out_a_ready = auto_fragmenter_out_a_ready; // @[LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_valid = auto_fragmenter_out_d_valid; // @[LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_opcode = auto_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_size = auto_fragmenter_out_d_bits_size; // @[LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_source = auto_fragmenter_out_d_bits_source; // @[LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_data = auto_fragmenter_out_d_bits_data; // @[LazyModule.scala 311:12]
endmodule
module TLMonitor_32(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [11:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [2:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
  wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
  wire [11:0] _GEN_71 = {{6'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [11:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 12'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire [12:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [12:0] _T_48 = $signed(_T_7) & 13'sh1000; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 13'sh0; // @[Parameters.scala 137:67]
  wire  _T_59 = 3'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_60 = _source_ok_T & _T_59; // @[Mux.scala 27:73]
  wire  _T_76 = _T_60 & _T_49; // @[Monitor.scala 83:78]
  wire  _T_90 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_94 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_95 = _T_94 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_99 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_103 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_164 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_177 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_192 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
  wire  _T_200 = _T_192 & _T_49; // @[Parameters.scala 670:56]
  wire  _T_211 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_215 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_223 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_245 = source_ok & _T_200; // @[Monitor.scala 115:71]
  wire  _T_263 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_299 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_300 = io_in_a_bits_mask & _T_299; // @[Monitor.scala 127:31]
  wire  _T_301 = _T_300 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_305 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_334 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_342 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_371 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_379 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_408 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_420 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  _T_424 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_428 = io_in_d_bits_size >= 3'h2; // @[Monitor.scala 312:27]
  wire  _T_444 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_472 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_501 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_518 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_536 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [3:0] a_first_beats1_decode = is_aligned_mask[5:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] a_first_counter; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1 = a_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [11:0] address; // @[Monitor.scala 388:22]
  wire  _T_566 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_567 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_571 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_575 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_579 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_583 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
  wire [3:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [3:0] d_first_counter; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1 = d_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_590 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_591 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_599 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_603 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [11:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [3:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1_1 = a_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  reg [3:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_1 = d_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [11:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _GEN_76 = {{4'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_76 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_617 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_620 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [34:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [34:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_622 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_624 = ~_T_622[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [34:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_628 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_630 = ~_T_424; // @[Monitor.scala 671:74]
  wire  _T_631 = io_in_d_valid & d_first_1 & ~_T_424; // @[Monitor.scala 671:71]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [3:0] _GEN_22 = _d_first_T & d_first_1 & _T_630 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_23 = _d_first_T & d_first_1 & _T_630 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_617 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_641 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_643 = _T_641[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_648 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_649 = io_in_d_bits_opcode == _GEN_32 | _T_648; // @[Monitor.scala 685:77]
  wire  _T_653 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_660 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_661 = io_in_d_bits_opcode == _GEN_48 | _T_660; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_665 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_675 = _T_628 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_630; // @[Monitor.scala 694:116]
  wire  _T_677 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set = _GEN_16[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_22[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_19[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_23[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [11:0] a_sizes_set = _GEN_20[11:0];
  wire [11:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [11:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_686 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [2:0] inflight_1; // @[Monitor.scala 723:35]
  reg [11:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [3:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_2 = d_first_counter_2 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 4'h0; // @[Edges.scala 230:25]
  wire [11:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [15:0] _GEN_87 = {{4'd0}, _c_size_lookup_T_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_87 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_712 = io_in_d_valid & d_first_2 & _T_424; // @[Monitor.scala 779:71]
  wire [3:0] _GEN_67 = _d_first_T & d_first_2 & _T_424 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 783:90 784:21]
  wire [46:0] _GEN_68 = _d_first_T & d_first_2 & _T_424 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 785:21]
  wire [2:0] _T_720 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_730 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [2:0] d_clr_1 = _GEN_67[2:0];
  wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [2:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [11:0] d_opcodes_clr_1 = _GEN_68[11:0];
  wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [11:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_750 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 4'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 4'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 12'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 4'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 4'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 3'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 12'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 4'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_164 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_164) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_200 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_200) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_301 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_301) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_334 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_334) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_371 & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~_T_371) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_408 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_408) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_420 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_420) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at Periphery.scala:88:64)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Periphery.scala:88:64)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Periphery.scala:88:64)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at Periphery.scala:88:64)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Periphery.scala:88:64)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at Periphery.scala:88:64)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Periphery.scala:88:64)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Periphery.scala:88:64)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Periphery.scala:88:64)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_501 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_501 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Periphery.scala:88:64)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_518 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_518 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Periphery.scala:88:64)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_536 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_536 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Periphery.scala:88:64)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_567 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_567) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_571 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_571) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_575 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_575) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_579 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_579) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_583 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_583) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_591 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_591) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Periphery.scala:88:64)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_599 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_599) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at Periphery.scala:88:64)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_603 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_603) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at Periphery.scala:88:64)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_624 & (_T_620 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_620 & ~reset & ~_T_624) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_643 & (_T_631 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & _T_2 & ~_T_643) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Periphery.scala:88:64)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_649 & (_T_631 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & same_cycle_resp & _T_2 & ~_T_649) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Periphery.scala:88:64)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_653 & (_T_631 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & same_cycle_resp & _T_2 & ~_T_653) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Periphery.scala:88:64)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_661 & (_T_631 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & ~same_cycle_resp & _T_2 & ~_T_661) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Periphery.scala:88:64)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_665 & (_T_631 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & ~same_cycle_resp & _T_2 & ~_T_665) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Periphery.scala:88:64)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_677 & (_T_675 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_675 & _T_2 & ~_T_677) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_686 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_686) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_720[0] & (_T_712 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_712 & _T_2 & ~_T_720[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Periphery.scala:88:64)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_730 & (_T_712 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_712 & _T_2 & ~_T_730) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Periphery.scala:88:64)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_750 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_750) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Periphery.scala:88:64)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[11:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[2:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[1:0];
  _RAND_10 = {1{`RANDOM}};
  inflight = _RAND_10[2:0];
  _RAND_11 = {1{`RANDOM}};
  inflight_opcodes = _RAND_11[11:0];
  _RAND_12 = {1{`RANDOM}};
  inflight_sizes = _RAND_12[11:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[3:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[3:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  inflight_1 = _RAND_16[2:0];
  _RAND_17 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_17[11:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[3:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Repeater_18(
  input         clock,
  input         reset,
  input         io_repeat,
  output        io_full,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [2:0]  io_enq_bits_opcode,
  input  [2:0]  io_enq_bits_param,
  input  [2:0]  io_enq_bits_size,
  input  [1:0]  io_enq_bits_source,
  input  [11:0] io_enq_bits_address,
  input  [3:0]  io_enq_bits_mask,
  input         io_enq_bits_corrupt,
  input         io_deq_ready,
  output        io_deq_valid,
  output [2:0]  io_deq_bits_opcode,
  output [2:0]  io_deq_bits_param,
  output [2:0]  io_deq_bits_size,
  output [1:0]  io_deq_bits_source,
  output [11:0] io_deq_bits_address,
  output [3:0]  io_deq_bits_mask,
  output        io_deq_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
`endif // RANDOMIZE_REG_INIT
  reg  full; // @[Repeater.scala 19:21]
  reg [2:0] saved_opcode; // @[Repeater.scala 20:18]
  reg [2:0] saved_param; // @[Repeater.scala 20:18]
  reg [2:0] saved_size; // @[Repeater.scala 20:18]
  reg [1:0] saved_source; // @[Repeater.scala 20:18]
  reg [11:0] saved_address; // @[Repeater.scala 20:18]
  reg [3:0] saved_mask; // @[Repeater.scala 20:18]
  reg  saved_corrupt; // @[Repeater.scala 20:18]
  wire  _T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
  wire  _GEN_0 = _T & io_repeat | full; // @[Repeater.scala 19:21 28:{38,45}]
  wire  _T_2 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
  assign io_full = full; // @[Repeater.scala 26:11]
  assign io_enq_ready = io_deq_ready & ~full; // @[Repeater.scala 24:32]
  assign io_deq_valid = io_enq_valid | full; // @[Repeater.scala 23:32]
  assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode; // @[Repeater.scala 25:21]
  assign io_deq_bits_param = full ? saved_param : io_enq_bits_param; // @[Repeater.scala 25:21]
  assign io_deq_bits_size = full ? saved_size : io_enq_bits_size; // @[Repeater.scala 25:21]
  assign io_deq_bits_source = full ? saved_source : io_enq_bits_source; // @[Repeater.scala 25:21]
  assign io_deq_bits_address = full ? saved_address : io_enq_bits_address; // @[Repeater.scala 25:21]
  assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask; // @[Repeater.scala 25:21]
  assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt; // @[Repeater.scala 25:21]
  always @(posedge clock) begin
    if (reset) begin // @[Repeater.scala 19:21]
      full <= 1'h0; // @[Repeater.scala 19:21]
    end else if (_T_2 & ~io_repeat) begin // @[Repeater.scala 29:38]
      full <= 1'h0; // @[Repeater.scala 29:45]
    end else begin
      full <= _GEN_0;
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_opcode <= io_enq_bits_opcode; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_param <= io_enq_bits_param; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_size <= io_enq_bits_size; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_source <= io_enq_bits_source; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_address <= io_enq_bits_address; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_mask <= io_enq_bits_mask; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_corrupt <= io_enq_bits_corrupt; // @[Repeater.scala 28:62]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  full = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  saved_opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  saved_param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  saved_size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  saved_source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  saved_address = _RAND_5[11:0];
  _RAND_6 = {1{`RANDOM}};
  saved_mask = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  saved_corrupt = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLFragmenter_17(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [11:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output [31:0] auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [1:0]  auto_out_a_bits_size,
  output [6:0]  auto_out_a_bits_source,
  output [11:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_size,
  input  [6:0]  auto_out_d_bits_source,
  input  [31:0] auto_out_d_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [11:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  repeater_clock; // @[Fragmenter.scala 262:30]
  wire  repeater_reset; // @[Fragmenter.scala 262:30]
  wire  repeater_io_repeat; // @[Fragmenter.scala 262:30]
  wire  repeater_io_full; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
  wire [11:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
  wire [11:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
  reg [3:0] acknum; // @[Fragmenter.scala 189:29]
  reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
  reg  dToggle; // @[Fragmenter.scala 191:30]
  wire [3:0] dFragnum = auto_out_d_bits_source[3:0]; // @[Fragmenter.scala 192:41]
  wire  dFirst = acknum == 4'h0; // @[Fragmenter.scala 193:29]
  wire  dLast = dFragnum == 4'h0; // @[Fragmenter.scala 194:30]
  wire [3:0] _dsizeOH_T = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 64:12]
  wire [2:0] dsizeOH = _dsizeOH_T[2:0]; // @[OneHot.scala 64:27]
  wire [4:0] _dsizeOH1_T_1 = 5'h3 << auto_out_d_bits_size; // @[package.scala 234:77]
  wire [1:0] dsizeOH1 = ~_dsizeOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  dHasData = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  _T_5 = ~reset; // @[Fragmenter.scala 202:16]
  wire  ack_decrement = dHasData | dsizeOH[2]; // @[Fragmenter.scala 204:32]
  wire [5:0] _dFirst_size_T = {dFragnum, 2'h0}; // @[Fragmenter.scala 206:47]
  wire [5:0] _GEN_7 = {{4'd0}, dsizeOH1}; // @[Fragmenter.scala 206:69]
  wire [5:0] _dFirst_size_T_1 = _dFirst_size_T | _GEN_7; // @[Fragmenter.scala 206:69]
  wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala 232:35]
  wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
  wire [6:0] _dFirst_size_T_4 = {1'h0,_dFirst_size_T_1}; // @[Cat.scala 31:58]
  wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
  wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
  wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
  wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
  wire [3:0] _GEN_8 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
  wire [3:0] _dFirst_size_T_8 = _GEN_8 | dFirst_size_lo; // @[OneHot.scala 32:28]
  wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
  wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
  wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
  wire  drop = ~dHasData & ~dLast; // @[Fragmenter.scala 222:30]
  wire  bundleOut_0_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  wire  _T_7 = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
  wire [3:0] _GEN_9 = {{3'd0}, ack_decrement}; // @[Fragmenter.scala 209:55]
  wire [3:0] _acknum_T_1 = acknum - _GEN_9; // @[Fragmenter.scala 209:55]
  wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h2 ? 3'h2 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
  wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
  wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
  wire [8:0] _aFragOH1_T_1 = 9'h3 << aFrag; // @[package.scala 234:77]
  wire [1:0] aFragOH1 = ~_aFragOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  aHasData = ~repeater_io_deq_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] gennum; // @[Fragmenter.scala 291:29]
  wire  aFirst = gennum == 4'h0; // @[Fragmenter.scala 292:29]
  wire [3:0] _old_gennum1_T_2 = gennum - 4'h1; // @[Fragmenter.scala 293:79]
  wire [3:0] old_gennum1 = aFirst ? aOrigOH1[5:2] : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
  wire [3:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
  wire [3:0] new_gennum = ~_new_gennum_T; // @[Fragmenter.scala 294:26]
  reg  aToggle_r; // @[Reg.scala 16:16]
  wire  _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
  wire  aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
  wire  bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  wire  _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
  wire  _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala 302:31]
  wire [5:0] _bundleOut_0_a_bits_address_T = {old_gennum1, 2'h0}; // @[Fragmenter.scala 304:65]
  wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
  wire [5:0] _bundleOut_0_a_bits_address_T_2 = _bundleOut_0_a_bits_address_T | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
  wire [5:0] _GEN_10 = {{4'd0}, aFragOH1}; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_10; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_4 = _bundleOut_0_a_bits_address_T_3 | 6'h3; // @[Fragmenter.scala 304:111]
  wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_4; // @[Fragmenter.scala 304:51]
  wire [11:0] _GEN_11 = {{6'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
  wire [2:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aToggle}; // @[Cat.scala 31:58]
  wire  _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
  TLMonitor_32 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  Repeater_18 repeater ( // @[Fragmenter.scala 262:30]
    .clock(repeater_clock),
    .reset(repeater_reset),
    .io_repeat(repeater_io_repeat),
    .io_full(repeater_io_full),
    .io_enq_ready(repeater_io_enq_ready),
    .io_enq_valid(repeater_io_enq_valid),
    .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
    .io_enq_bits_param(repeater_io_enq_bits_param),
    .io_enq_bits_size(repeater_io_enq_bits_size),
    .io_enq_bits_source(repeater_io_enq_bits_source),
    .io_enq_bits_address(repeater_io_enq_bits_address),
    .io_enq_bits_mask(repeater_io_enq_bits_mask),
    .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
    .io_deq_ready(repeater_io_deq_ready),
    .io_deq_valid(repeater_io_deq_valid),
    .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
    .io_deq_bits_param(repeater_io_deq_bits_param),
    .io_deq_bits_size(repeater_io_deq_bits_size),
    .io_deq_bits_source(repeater_io_deq_bits_source),
    .io_deq_bits_address(repeater_io_deq_bits_address),
    .io_deq_bits_mask(repeater_io_deq_bits_mask),
    .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
  );
  assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign auto_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign auto_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_size = aFrag[1:0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
  assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,new_gennum}; // @[Cat.scala 31:58]
  assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_11; // @[Fragmenter.scala 304:49]
  assign auto_out_a_bits_mask = repeater_io_full ? 4'hf : auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = repeater_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign repeater_clock = clock;
  assign repeater_reset = reset;
  assign repeater_io_repeat = ~aHasData & new_gennum != 4'h0; // @[Fragmenter.scala 302:41]
  assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  always @(posedge clock) begin
    if (reset) begin // @[Fragmenter.scala 189:29]
      acknum <= 4'h0; // @[Fragmenter.scala 189:29]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 209:24]
        acknum <= dFragnum;
      end else begin
        acknum <= _acknum_T_1;
      end
    end
    if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
      end
    end
    if (reset) begin // @[Fragmenter.scala 191:30]
      dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dToggle <= auto_out_d_bits_source[4]; // @[Fragmenter.scala 212:21]
      end
    end
    if (reset) begin // @[Fragmenter.scala 291:29]
      gennum <= 4'h0; // @[Fragmenter.scala 291:29]
    end else if (_T_8) begin // @[Fragmenter.scala 300:29]
      gennum <= new_gennum; // @[Fragmenter.scala 300:38]
    end
    if (aFirst) begin // @[Reg.scala 17:18]
      aToggle_r <= dToggle; // @[Reg.scala 17:22]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~repeater_io_full | _repeater_io_repeat_T) & _T_5) begin
          $fatal; // @[Fragmenter.scala 309:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(~repeater_io_full | _repeater_io_repeat_T)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Fragmenter.scala:309 assert (!repeater.io.full || !aHasData)\n"
            ); // @[Fragmenter.scala 309:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_9 | repeater_io_deq_bits_mask == 4'hf) & _T_5) begin
          $fatal; // @[Fragmenter.scala 312:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask == 4'hf)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
            ); // @[Fragmenter.scala 312:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  acknum = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  dOrig = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  dToggle = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  gennum = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  aToggle_r = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLInterconnectCoupler_22(
  input         clock,
  input         reset,
  input         auto_fragmenter_out_a_ready,
  output        auto_fragmenter_out_a_valid,
  output [2:0]  auto_fragmenter_out_a_bits_opcode,
  output [2:0]  auto_fragmenter_out_a_bits_param,
  output [1:0]  auto_fragmenter_out_a_bits_size,
  output [6:0]  auto_fragmenter_out_a_bits_source,
  output [11:0] auto_fragmenter_out_a_bits_address,
  output [3:0]  auto_fragmenter_out_a_bits_mask,
  output [31:0] auto_fragmenter_out_a_bits_data,
  output        auto_fragmenter_out_a_bits_corrupt,
  output        auto_fragmenter_out_d_ready,
  input         auto_fragmenter_out_d_valid,
  input  [2:0]  auto_fragmenter_out_d_bits_opcode,
  input  [1:0]  auto_fragmenter_out_d_bits_size,
  input  [6:0]  auto_fragmenter_out_d_bits_source,
  input  [31:0] auto_fragmenter_out_d_bits_data,
  output        auto_tl_in_a_ready,
  input         auto_tl_in_a_valid,
  input  [2:0]  auto_tl_in_a_bits_opcode,
  input  [2:0]  auto_tl_in_a_bits_param,
  input  [2:0]  auto_tl_in_a_bits_size,
  input  [1:0]  auto_tl_in_a_bits_source,
  input  [11:0] auto_tl_in_a_bits_address,
  input  [3:0]  auto_tl_in_a_bits_mask,
  input  [31:0] auto_tl_in_a_bits_data,
  input         auto_tl_in_a_bits_corrupt,
  input         auto_tl_in_d_ready,
  output        auto_tl_in_d_valid,
  output [2:0]  auto_tl_in_d_bits_opcode,
  output [2:0]  auto_tl_in_d_bits_size,
  output [1:0]  auto_tl_in_d_bits_source,
  output [31:0] auto_tl_in_d_bits_data
);
  wire  fragmenter_clock; // @[Fragmenter.scala 333:34]
  wire  fragmenter_reset; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [11:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [11:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
  TLFragmenter_17 fragmenter ( // @[Fragmenter.scala 333:34]
    .clock(fragmenter_clock),
    .reset(fragmenter_reset),
    .auto_in_a_ready(fragmenter_auto_in_a_ready),
    .auto_in_a_valid(fragmenter_auto_in_a_valid),
    .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
    .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
    .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
    .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
    .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
    .auto_in_a_bits_data(fragmenter_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
    .auto_in_d_ready(fragmenter_auto_in_d_ready),
    .auto_in_d_valid(fragmenter_auto_in_d_valid),
    .auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
    .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
    .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
    .auto_out_a_ready(fragmenter_auto_out_a_ready),
    .auto_out_a_valid(fragmenter_auto_out_a_valid),
    .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
    .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
    .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
    .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
    .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
    .auto_out_a_bits_data(fragmenter_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
    .auto_out_d_ready(fragmenter_auto_out_d_ready),
    .auto_out_d_valid(fragmenter_auto_out_d_valid),
    .auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
    .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
    .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
  );
  assign auto_fragmenter_out_a_valid = fragmenter_auto_out_a_valid; // @[LazyModule.scala 311:12]
  assign auto_fragmenter_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[LazyModule.scala 311:12]
  assign auto_fragmenter_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[LazyModule.scala 311:12]
  assign auto_fragmenter_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[LazyModule.scala 311:12]
  assign auto_fragmenter_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[LazyModule.scala 311:12]
  assign auto_fragmenter_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[LazyModule.scala 311:12]
  assign auto_fragmenter_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[LazyModule.scala 311:12]
  assign auto_fragmenter_out_a_bits_data = fragmenter_auto_out_a_bits_data; // @[LazyModule.scala 311:12]
  assign auto_fragmenter_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
  assign auto_fragmenter_out_d_ready = fragmenter_auto_out_d_ready; // @[LazyModule.scala 311:12]
  assign auto_tl_in_a_ready = fragmenter_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_valid = fragmenter_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_size = fragmenter_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_source = fragmenter_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_data = fragmenter_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign fragmenter_clock = clock;
  assign fragmenter_reset = reset;
  assign fragmenter_auto_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_data = auto_tl_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_out_a_ready = auto_fragmenter_out_a_ready; // @[LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_valid = auto_fragmenter_out_d_valid; // @[LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_opcode = auto_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_size = auto_fragmenter_out_d_bits_size; // @[LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_source = auto_fragmenter_out_d_bits_source; // @[LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_data = auto_fragmenter_out_d_bits_data; // @[LazyModule.scala 311:12]
endmodule
module TLWidthWidget_5(
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [27:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [1:0]  auto_in_d_bits_param,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output        auto_in_d_bits_sink,
  output        auto_in_d_bits_denied,
  output [31:0] auto_in_d_bits_data,
  output        auto_in_d_bits_corrupt,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [2:0]  auto_out_a_bits_size,
  output [1:0]  auto_out_a_bits_source,
  output [27:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_param,
  input  [2:0]  auto_out_d_bits_size,
  input  [1:0]  auto_out_d_bits_source,
  input         auto_out_d_bits_sink,
  input         auto_out_d_bits_denied,
  input  [31:0] auto_out_d_bits_data,
  input         auto_out_d_bits_corrupt
);
  assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module TLInterconnectCoupler_23(
  input         auto_tl_slave_clock_xing_out_a_ready,
  output        auto_tl_slave_clock_xing_out_a_valid,
  output [2:0]  auto_tl_slave_clock_xing_out_a_bits_opcode,
  output [2:0]  auto_tl_slave_clock_xing_out_a_bits_param,
  output [2:0]  auto_tl_slave_clock_xing_out_a_bits_size,
  output [1:0]  auto_tl_slave_clock_xing_out_a_bits_source,
  output [27:0] auto_tl_slave_clock_xing_out_a_bits_address,
  output [3:0]  auto_tl_slave_clock_xing_out_a_bits_mask,
  output [31:0] auto_tl_slave_clock_xing_out_a_bits_data,
  output        auto_tl_slave_clock_xing_out_a_bits_corrupt,
  output        auto_tl_slave_clock_xing_out_d_ready,
  input         auto_tl_slave_clock_xing_out_d_valid,
  input  [2:0]  auto_tl_slave_clock_xing_out_d_bits_opcode,
  input  [1:0]  auto_tl_slave_clock_xing_out_d_bits_param,
  input  [2:0]  auto_tl_slave_clock_xing_out_d_bits_size,
  input  [1:0]  auto_tl_slave_clock_xing_out_d_bits_source,
  input         auto_tl_slave_clock_xing_out_d_bits_sink,
  input         auto_tl_slave_clock_xing_out_d_bits_denied,
  input  [31:0] auto_tl_slave_clock_xing_out_d_bits_data,
  input         auto_tl_slave_clock_xing_out_d_bits_corrupt,
  output        auto_tl_in_a_ready,
  input         auto_tl_in_a_valid,
  input  [2:0]  auto_tl_in_a_bits_opcode,
  input  [2:0]  auto_tl_in_a_bits_param,
  input  [2:0]  auto_tl_in_a_bits_size,
  input  [1:0]  auto_tl_in_a_bits_source,
  input  [27:0] auto_tl_in_a_bits_address,
  input  [3:0]  auto_tl_in_a_bits_mask,
  input  [31:0] auto_tl_in_a_bits_data,
  input         auto_tl_in_a_bits_corrupt,
  input         auto_tl_in_d_ready,
  output        auto_tl_in_d_valid,
  output [2:0]  auto_tl_in_d_bits_opcode,
  output [1:0]  auto_tl_in_d_bits_param,
  output [2:0]  auto_tl_in_d_bits_size,
  output [1:0]  auto_tl_in_d_bits_source,
  output        auto_tl_in_d_bits_sink,
  output        auto_tl_in_d_bits_denied,
  output [31:0] auto_tl_in_d_bits_data,
  output        auto_tl_in_d_bits_corrupt
);
  wire  widget_auto_in_a_ready; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_a_valid; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_a_bits_opcode; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_a_bits_param; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_a_bits_size; // @[WidthWidget.scala 219:28]
  wire [1:0] widget_auto_in_a_bits_source; // @[WidthWidget.scala 219:28]
  wire [27:0] widget_auto_in_a_bits_address; // @[WidthWidget.scala 219:28]
  wire [3:0] widget_auto_in_a_bits_mask; // @[WidthWidget.scala 219:28]
  wire [31:0] widget_auto_in_a_bits_data; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_a_bits_corrupt; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_d_ready; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_d_valid; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_d_bits_opcode; // @[WidthWidget.scala 219:28]
  wire [1:0] widget_auto_in_d_bits_param; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_d_bits_size; // @[WidthWidget.scala 219:28]
  wire [1:0] widget_auto_in_d_bits_source; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_d_bits_sink; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_d_bits_denied; // @[WidthWidget.scala 219:28]
  wire [31:0] widget_auto_in_d_bits_data; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_d_bits_corrupt; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_a_ready; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_a_valid; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_a_bits_opcode; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_a_bits_param; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_a_bits_size; // @[WidthWidget.scala 219:28]
  wire [1:0] widget_auto_out_a_bits_source; // @[WidthWidget.scala 219:28]
  wire [27:0] widget_auto_out_a_bits_address; // @[WidthWidget.scala 219:28]
  wire [3:0] widget_auto_out_a_bits_mask; // @[WidthWidget.scala 219:28]
  wire [31:0] widget_auto_out_a_bits_data; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_a_bits_corrupt; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_d_ready; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_d_valid; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_d_bits_opcode; // @[WidthWidget.scala 219:28]
  wire [1:0] widget_auto_out_d_bits_param; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_d_bits_size; // @[WidthWidget.scala 219:28]
  wire [1:0] widget_auto_out_d_bits_source; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_d_bits_sink; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_d_bits_denied; // @[WidthWidget.scala 219:28]
  wire [31:0] widget_auto_out_d_bits_data; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_d_bits_corrupt; // @[WidthWidget.scala 219:28]
  TLWidthWidget_5 widget ( // @[WidthWidget.scala 219:28]
    .auto_in_a_ready(widget_auto_in_a_ready),
    .auto_in_a_valid(widget_auto_in_a_valid),
    .auto_in_a_bits_opcode(widget_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(widget_auto_in_a_bits_param),
    .auto_in_a_bits_size(widget_auto_in_a_bits_size),
    .auto_in_a_bits_source(widget_auto_in_a_bits_source),
    .auto_in_a_bits_address(widget_auto_in_a_bits_address),
    .auto_in_a_bits_mask(widget_auto_in_a_bits_mask),
    .auto_in_a_bits_data(widget_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(widget_auto_in_a_bits_corrupt),
    .auto_in_d_ready(widget_auto_in_d_ready),
    .auto_in_d_valid(widget_auto_in_d_valid),
    .auto_in_d_bits_opcode(widget_auto_in_d_bits_opcode),
    .auto_in_d_bits_param(widget_auto_in_d_bits_param),
    .auto_in_d_bits_size(widget_auto_in_d_bits_size),
    .auto_in_d_bits_source(widget_auto_in_d_bits_source),
    .auto_in_d_bits_sink(widget_auto_in_d_bits_sink),
    .auto_in_d_bits_denied(widget_auto_in_d_bits_denied),
    .auto_in_d_bits_data(widget_auto_in_d_bits_data),
    .auto_in_d_bits_corrupt(widget_auto_in_d_bits_corrupt),
    .auto_out_a_ready(widget_auto_out_a_ready),
    .auto_out_a_valid(widget_auto_out_a_valid),
    .auto_out_a_bits_opcode(widget_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(widget_auto_out_a_bits_param),
    .auto_out_a_bits_size(widget_auto_out_a_bits_size),
    .auto_out_a_bits_source(widget_auto_out_a_bits_source),
    .auto_out_a_bits_address(widget_auto_out_a_bits_address),
    .auto_out_a_bits_mask(widget_auto_out_a_bits_mask),
    .auto_out_a_bits_data(widget_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(widget_auto_out_a_bits_corrupt),
    .auto_out_d_ready(widget_auto_out_d_ready),
    .auto_out_d_valid(widget_auto_out_d_valid),
    .auto_out_d_bits_opcode(widget_auto_out_d_bits_opcode),
    .auto_out_d_bits_param(widget_auto_out_d_bits_param),
    .auto_out_d_bits_size(widget_auto_out_d_bits_size),
    .auto_out_d_bits_source(widget_auto_out_d_bits_source),
    .auto_out_d_bits_sink(widget_auto_out_d_bits_sink),
    .auto_out_d_bits_denied(widget_auto_out_d_bits_denied),
    .auto_out_d_bits_data(widget_auto_out_d_bits_data),
    .auto_out_d_bits_corrupt(widget_auto_out_d_bits_corrupt)
  );
  assign auto_tl_slave_clock_xing_out_a_valid = widget_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_slave_clock_xing_out_a_bits_opcode = widget_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_slave_clock_xing_out_a_bits_param = widget_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_slave_clock_xing_out_a_bits_size = widget_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_slave_clock_xing_out_a_bits_source = widget_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_slave_clock_xing_out_a_bits_address = widget_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_slave_clock_xing_out_a_bits_mask = widget_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_slave_clock_xing_out_a_bits_data = widget_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_slave_clock_xing_out_a_bits_corrupt = widget_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_slave_clock_xing_out_d_ready = widget_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_in_a_ready = widget_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_valid = widget_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_opcode = widget_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_param = widget_auto_in_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_size = widget_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_source = widget_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_sink = widget_auto_in_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_denied = widget_auto_in_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_data = widget_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_corrupt = widget_auto_in_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign widget_auto_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_data = auto_tl_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign widget_auto_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign widget_auto_out_a_ready = auto_tl_slave_clock_xing_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign widget_auto_out_d_valid = auto_tl_slave_clock_xing_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign widget_auto_out_d_bits_opcode = auto_tl_slave_clock_xing_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign widget_auto_out_d_bits_param = auto_tl_slave_clock_xing_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign widget_auto_out_d_bits_size = auto_tl_slave_clock_xing_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign widget_auto_out_d_bits_source = auto_tl_slave_clock_xing_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign widget_auto_out_d_bits_sink = auto_tl_slave_clock_xing_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign widget_auto_out_d_bits_denied = auto_tl_slave_clock_xing_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign widget_auto_out_d_bits_data = auto_tl_slave_clock_xing_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign widget_auto_out_d_bits_corrupt = auto_tl_slave_clock_xing_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
endmodule
module TLMonitor_33(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [1:0]  io_in_a_bits_size,
  input  [6:0]  io_in_a_bits_source,
  input  [28:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_param,
  input  [1:0]  io_in_d_bits_size,
  input  [6:0]  io_in_d_bits_source,
  input         io_in_d_bits_sink,
  input         io_in_d_bits_denied,
  input         io_in_d_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [95:0] _RAND_13;
  reg [383:0] _RAND_14;
  reg [383:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [95:0] _RAND_19;
  reg [383:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T_4 = io_in_a_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire [4:0] _is_aligned_mask_T_1 = 5'h3 << io_in_a_bits_size; // @[package.scala 234:77]
  wire [1:0] is_aligned_mask = ~_is_aligned_mask_T_1[1:0]; // @[package.scala 234:46]
  wire [28:0] _GEN_71 = {{27'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 2'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [28:0] _T_33 = io_in_a_bits_address ^ 29'h10000000; // @[Parameters.scala 137:31]
  wire [29:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
  wire [29:0] _T_36 = $signed(_T_34) & -30'sh1000; // @[Parameters.scala 137:52]
  wire  _T_37 = $signed(_T_36) == 30'sh0; // @[Parameters.scala 137:67]
  wire  _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_74 = _T_73 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_164 = io_in_a_bits_size <= 2'h2; // @[Parameters.scala 92:42]
  wire  _T_172 = _T_164 & _T_37; // @[Parameters.scala 670:56]
  wire  _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_218 = _source_ok_T_4 & _T_172; // @[Monitor.scala 115:71]
  wire  _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_273 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_274 = io_in_a_bits_mask & _T_273; // @[Monitor.scala 127:31]
  wire  _T_275 = _T_274 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_279 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_347 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_355 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_385 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_397 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_10 = io_in_d_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire  _T_401 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_405 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 312:27]
  wire  _T_409 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
  wire  _T_413 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
  wire  _T_417 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
  wire  _T_421 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_432 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
  wire  _T_436 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
  wire  _T_449 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_469 = _T_417 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
  wire  _T_478 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_495 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_513 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [1:0] size; // @[Monitor.scala 386:22]
  reg [6:0] source; // @[Monitor.scala 387:22]
  reg [28:0] address; // @[Monitor.scala 388:22]
  wire  _T_543 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_544 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_548 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_552 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_556 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_560 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] param_1; // @[Monitor.scala 536:22]
  reg [1:0] size_1; // @[Monitor.scala 537:22]
  reg [6:0] source_1; // @[Monitor.scala 538:22]
  reg  sink; // @[Monitor.scala 539:22]
  reg  denied; // @[Monitor.scala 540:22]
  wire  _T_567 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_568 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_572 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
  wire  _T_576 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_580 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  wire  _T_584 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
  wire  _T_588 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
  reg [95:0] inflight; // @[Monitor.scala 611:27]
  reg [383:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [383:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [8:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [9:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [383:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [383:0] _GEN_73 = {{368'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[383:1]}; // @[Monitor.scala 634:152]
  wire [383:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [383:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
  wire [383:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[383:1]}; // @[Monitor.scala 638:144]
  wire  _T_594 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [127:0] _a_set_wo_ready_T = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [127:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_597 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
  wire [8:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [9:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [1026:0] _GEN_1 = {{1023'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [1026:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
  wire [1025:0] _GEN_2 = {{1023'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [1025:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [95:0] _T_599 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_601 = ~_T_599[0]; // @[Monitor.scala 658:17]
  wire [127:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 652:72 653:28]
  wire [1026:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 1027'h0; // @[Monitor.scala 652:72 656:28]
  wire [1025:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 1026'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_605 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_607 = ~_T_401; // @[Monitor.scala 671:74]
  wire  _T_608 = io_in_d_valid & d_first_1 & ~_T_401; // @[Monitor.scala 671:71]
  wire [127:0] _d_clr_wo_ready_T = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [127:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 671:90 672:22]
  wire [1038:0] _GEN_3 = {{1023'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [1038:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [127:0] _GEN_22 = d_first_done & d_first_1 & _T_607 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 675:91 676:21]
  wire [1038:0] _GEN_23 = d_first_done & d_first_1 & _T_607 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_594 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [95:0] _T_618 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_620 = _T_618[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_625 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_626 = io_in_d_bits_opcode == _GEN_32 | _T_625; // @[Monitor.scala 685:77]
  wire  _T_630 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_637 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_638 = io_in_d_bits_opcode == _GEN_48 | _T_637; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_642 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_652 = _T_605 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_607; // @[Monitor.scala 694:116]
  wire  _T_654 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [95:0] a_set_wo_ready = _GEN_15[95:0];
  wire [95:0] d_clr_wo_ready = _GEN_21[95:0];
  wire  _T_661 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire [95:0] a_set = _GEN_16[95:0];
  wire [95:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [95:0] d_clr = _GEN_22[95:0];
  wire [95:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [95:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [383:0] a_opcodes_set = _GEN_19[383:0];
  wire [383:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [383:0] d_opcodes_clr = _GEN_23[383:0];
  wire [383:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [383:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [383:0] a_sizes_set = _GEN_20[383:0];
  wire [383:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [383:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_670 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [95:0] inflight_1; // @[Monitor.scala 723:35]
  reg [383:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [383:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [383:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
  wire [383:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[383:1]}; // @[Monitor.scala 747:146]
  wire  _T_696 = io_in_d_valid & d_first_2 & _T_401; // @[Monitor.scala 779:71]
  wire [127:0] _GEN_67 = d_first_done & d_first_2 & _T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 783:90 784:21]
  wire [1038:0] _GEN_68 = d_first_done & d_first_2 & _T_401 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 783:90 785:21]
  wire [95:0] _T_704 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_714 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [95:0] d_clr_1 = _GEN_67[95:0];
  wire [95:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [95:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [383:0] d_opcodes_clr_1 = _GEN_68[383:0];
  wire [383:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [383:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_739 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 1'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= 1'h0;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 96'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 384'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 384'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 1'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= 1'h0;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 96'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 384'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= 1'h0;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (d_first_done) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_172 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_172) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_275 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_275) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_309 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_309) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_347 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_347) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_385 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_397 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_397) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_409 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_T_409) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_413 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_T_413) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_417 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_T_417) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is denied (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_432 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_T_432) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid cap param (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_436 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_T_436) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries toN param (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_413 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_T_413) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is corrupt (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_417 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_T_417) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is denied (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_432 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_T_432) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_436 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_T_436) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries toN param (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_469 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_T_469) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_417 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_T_417) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_478 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_478 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_409 & (io_in_d_valid & _T_478 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_478 & _T_2 & ~_T_409) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid param (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_413 & (io_in_d_valid & _T_478 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_478 & _T_2 & ~_T_413) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is corrupt (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_417 & (io_in_d_valid & _T_478 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_478 & _T_2 & ~_T_417) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is denied (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_495 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_495 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_409 & (io_in_d_valid & _T_495 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_495 & _T_2 & ~_T_409) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_469 & (io_in_d_valid & _T_495 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_495 & _T_2 & ~_T_469) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_417 & (io_in_d_valid & _T_495 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_495 & _T_2 & ~_T_417) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_513 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_513 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_409 & (io_in_d_valid & _T_513 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_513 & _T_2 & ~_T_409) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid param (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_413 & (io_in_d_valid & _T_513 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_513 & _T_2 & ~_T_413) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is corrupt (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_417 & (io_in_d_valid & _T_513 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_513 & _T_2 & ~_T_417) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is denied (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_544 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_544) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_548 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_548) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_552 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_552) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_556 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_556) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_560 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_560) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_568 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_568) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_572 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_572) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel param changed within multibeat operation (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_576 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_576) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_580 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_580) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_584 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_584) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel sink changed with multibeat operation (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_588 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_588) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel denied changed with multibeat operation (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_601 & (_T_597 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_597 & ~reset & ~_T_601) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_620 & (_T_608 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & _T_2 & ~_T_620) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_626 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_626) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_630 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_630) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_638 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_638) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_642 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_642) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_654 & (_T_652 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_652 & _T_2 & ~_T_654) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_661 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_661) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 4 (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_670 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_670) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_704[0] & (_T_696 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_696 & _T_2 & ~_T_704[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_714 & (_T_696 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_696 & _T_2 & ~_T_714) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_739 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_739) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at MockAONPeriphery.scala:22:62)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[6:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[28:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  param_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  size_1 = _RAND_9[1:0];
  _RAND_10 = {1{`RANDOM}};
  source_1 = _RAND_10[6:0];
  _RAND_11 = {1{`RANDOM}};
  sink = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  denied = _RAND_12[0:0];
  _RAND_13 = {3{`RANDOM}};
  inflight = _RAND_13[95:0];
  _RAND_14 = {12{`RANDOM}};
  inflight_opcodes = _RAND_14[383:0];
  _RAND_15 = {12{`RANDOM}};
  inflight_sizes = _RAND_15[383:0];
  _RAND_16 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_17[0:0];
  _RAND_18 = {1{`RANDOM}};
  watchdog = _RAND_18[31:0];
  _RAND_19 = {3{`RANDOM}};
  inflight_1 = _RAND_19[95:0];
  _RAND_20 = {12{`RANDOM}};
  inflight_sizes_1 = _RAND_20[383:0];
  _RAND_21 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_21[0:0];
  _RAND_22 = {1{`RANDOM}};
  watchdog_1 = _RAND_22[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0(
  input   clock,
  input   reset,
  input   io_d,
  output  io_q
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
  reg  sync_0; // @[SynchronizerReg.scala 51:87]
  reg  sync_1; // @[SynchronizerReg.scala 51:87]
  reg  sync_2; // @[SynchronizerReg.scala 51:87]
  assign io_q = sync_0; // @[SynchronizerReg.scala 59:8]
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[SynchronizerReg.scala 51:87]
      sync_0 <= 1'h0; // @[SynchronizerReg.scala 51:87]
    end else begin
      sync_0 <= sync_1; // @[SynchronizerReg.scala 57:10]
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[SynchronizerReg.scala 51:87]
      sync_1 <= 1'h0; // @[SynchronizerReg.scala 51:87]
    end else begin
      sync_1 <= sync_2; // @[SynchronizerReg.scala 57:10]
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[SynchronizerReg.scala 54:22]
      sync_2 <= 1'h0;
    end else begin
      sync_2 <= io_d;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  sync_0 = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  sync_1 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  sync_2 = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
  if (reset) begin
    sync_0 = 1'h0;
  end
  if (reset) begin
    sync_1 = 1'h0;
  end
  if (reset) begin
    sync_2 = 1'h0;
  end
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module AsyncResetSynchronizerShiftReg_w1_d3_i0(
  input   clock,
  input   reset,
  input   io_d,
  output  io_q
);
  wire  output_chain_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_reset; // @[ShiftReg.scala 45:23]
  wire  output_chain_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_io_q; // @[ShiftReg.scala 45:23]
  AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 output_chain ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_clock),
    .reset(output_chain_reset),
    .io_d(output_chain_io_d),
    .io_q(output_chain_io_q)
  );
  assign io_q = output_chain_io_q; // @[ShiftReg.scala 48:{24,24}]
  assign output_chain_clock = clock;
  assign output_chain_reset = reset; // @[SynchronizerReg.scala 86:21]
  assign output_chain_io_d = io_d; // @[SynchronizerReg.scala 87:41]
endmodule
module AsyncResetSynchronizerShiftReg_w1_d3_i0_1(
  input   clock,
  input   reset,
  input   io_d,
  output  io_q
);
  wire  output_chain_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_reset; // @[ShiftReg.scala 45:23]
  wire  output_chain_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_io_q; // @[ShiftReg.scala 45:23]
  AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 output_chain ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_clock),
    .reset(output_chain_reset),
    .io_d(output_chain_io_d),
    .io_q(output_chain_io_q)
  );
  assign io_q = output_chain_io_q; // @[ShiftReg.scala 48:{24,24}]
  assign output_chain_clock = clock;
  assign output_chain_reset = reset; // @[SynchronizerReg.scala 86:21]
  assign output_chain_io_d = io_d; // @[SynchronizerReg.scala 87:41]
endmodule
module AsyncValidSync(
  input   io_in,
  output  io_out,
  input   clock,
  input   reset
);
  wire  io_out_source_valid_0_clock; // @[ShiftReg.scala 45:23]
  wire  io_out_source_valid_0_reset; // @[ShiftReg.scala 45:23]
  wire  io_out_source_valid_0_io_d; // @[ShiftReg.scala 45:23]
  wire  io_out_source_valid_0_io_q; // @[ShiftReg.scala 45:23]
  AsyncResetSynchronizerShiftReg_w1_d3_i0_1 io_out_source_valid_0 ( // @[ShiftReg.scala 45:23]
    .clock(io_out_source_valid_0_clock),
    .reset(io_out_source_valid_0_reset),
    .io_d(io_out_source_valid_0_io_d),
    .io_q(io_out_source_valid_0_io_q)
  );
  assign io_out = io_out_source_valid_0_io_q; // @[ShiftReg.scala 48:{24,24}]
  assign io_out_source_valid_0_clock = clock;
  assign io_out_source_valid_0_reset = reset;
  assign io_out_source_valid_0_io_d = io_in; // @[ShiftReg.scala 47:16]
endmodule
module AsyncQueueSource(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [2:0]  io_enq_bits_opcode,
  input  [2:0]  io_enq_bits_param,
  input  [1:0]  io_enq_bits_size,
  input  [6:0]  io_enq_bits_source,
  input  [28:0] io_enq_bits_address,
  input  [3:0]  io_enq_bits_mask,
  input  [31:0] io_enq_bits_data,
  input         io_enq_bits_corrupt,
  output [2:0]  io_async_mem_0_opcode,
  output [2:0]  io_async_mem_0_param,
  output [1:0]  io_async_mem_0_size,
  output [6:0]  io_async_mem_0_source,
  output [28:0] io_async_mem_0_address,
  output [3:0]  io_async_mem_0_mask,
  output [31:0] io_async_mem_0_data,
  output        io_async_mem_0_corrupt,
  input         io_async_ridx,
  output        io_async_widx,
  input         io_async_safe_ridx_valid,
  output        io_async_safe_widx_valid,
  output        io_async_safe_source_reset_n,
  input         io_async_safe_sink_reset_n
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
`endif // RANDOMIZE_REG_INIT
  wire  ridx_ridx_gray_clock; // @[ShiftReg.scala 45:23]
  wire  ridx_ridx_gray_reset; // @[ShiftReg.scala 45:23]
  wire  ridx_ridx_gray_io_d; // @[ShiftReg.scala 45:23]
  wire  ridx_ridx_gray_io_q; // @[ShiftReg.scala 45:23]
  wire  source_valid_0_io_in; // @[AsyncQueue.scala 100:32]
  wire  source_valid_0_io_out; // @[AsyncQueue.scala 100:32]
  wire  source_valid_0_clock; // @[AsyncQueue.scala 100:32]
  wire  source_valid_0_reset; // @[AsyncQueue.scala 100:32]
  wire  source_valid_1_io_in; // @[AsyncQueue.scala 101:32]
  wire  source_valid_1_io_out; // @[AsyncQueue.scala 101:32]
  wire  source_valid_1_clock; // @[AsyncQueue.scala 101:32]
  wire  source_valid_1_reset; // @[AsyncQueue.scala 101:32]
  wire  sink_extend_io_in; // @[AsyncQueue.scala 103:30]
  wire  sink_extend_io_out; // @[AsyncQueue.scala 103:30]
  wire  sink_extend_clock; // @[AsyncQueue.scala 103:30]
  wire  sink_extend_reset; // @[AsyncQueue.scala 103:30]
  wire  sink_valid_io_in; // @[AsyncQueue.scala 104:30]
  wire  sink_valid_io_out; // @[AsyncQueue.scala 104:30]
  wire  sink_valid_clock; // @[AsyncQueue.scala 104:30]
  wire  sink_valid_reset; // @[AsyncQueue.scala 104:30]
  reg [2:0] mem_0_opcode; // @[AsyncQueue.scala 80:16]
  reg [2:0] mem_0_param; // @[AsyncQueue.scala 80:16]
  reg [1:0] mem_0_size; // @[AsyncQueue.scala 80:16]
  reg [6:0] mem_0_source; // @[AsyncQueue.scala 80:16]
  reg [28:0] mem_0_address; // @[AsyncQueue.scala 80:16]
  reg [3:0] mem_0_mask; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_0_data; // @[AsyncQueue.scala 80:16]
  reg  mem_0_corrupt; // @[AsyncQueue.scala 80:16]
  wire  _widx_T_1 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
  wire  sink_ready = sink_valid_io_out;
  wire  _widx_T_2 = ~sink_ready; // @[AsyncQueue.scala 81:79]
  reg  widx_widx_bin; // @[AsyncQueue.scala 52:25]
  wire  widx_incremented = _widx_T_2 ? 1'h0 : widx_widx_bin + _widx_T_1; // @[AsyncQueue.scala 53:23]
  wire  ridx = ridx_ridx_gray_io_q; // @[ShiftReg.scala 48:{24,24}]
  reg  ready_reg; // @[AsyncQueue.scala 88:56]
  reg  widx_gray; // @[AsyncQueue.scala 91:55]
  AsyncResetSynchronizerShiftReg_w1_d3_i0 ridx_ridx_gray ( // @[ShiftReg.scala 45:23]
    .clock(ridx_ridx_gray_clock),
    .reset(ridx_ridx_gray_reset),
    .io_d(ridx_ridx_gray_io_d),
    .io_q(ridx_ridx_gray_io_q)
  );
  AsyncValidSync source_valid_0 ( // @[AsyncQueue.scala 100:32]
    .io_in(source_valid_0_io_in),
    .io_out(source_valid_0_io_out),
    .clock(source_valid_0_clock),
    .reset(source_valid_0_reset)
  );
  AsyncValidSync source_valid_1 ( // @[AsyncQueue.scala 101:32]
    .io_in(source_valid_1_io_in),
    .io_out(source_valid_1_io_out),
    .clock(source_valid_1_clock),
    .reset(source_valid_1_reset)
  );
  AsyncValidSync sink_extend ( // @[AsyncQueue.scala 103:30]
    .io_in(sink_extend_io_in),
    .io_out(sink_extend_io_out),
    .clock(sink_extend_clock),
    .reset(sink_extend_reset)
  );
  AsyncValidSync sink_valid ( // @[AsyncQueue.scala 104:30]
    .io_in(sink_valid_io_in),
    .io_out(sink_valid_io_out),
    .clock(sink_valid_clock),
    .reset(sink_valid_reset)
  );
  assign io_enq_ready = ready_reg & sink_ready; // @[AsyncQueue.scala 89:29]
  assign io_async_mem_0_opcode = mem_0_opcode; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_0_param = mem_0_param; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_0_size = mem_0_size; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_0_source = mem_0_source; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_0_address = mem_0_address; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_0_mask = mem_0_mask; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_0_data = mem_0_data; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_0_corrupt = mem_0_corrupt; // @[AsyncQueue.scala 96:31]
  assign io_async_widx = widx_gray; // @[AsyncQueue.scala 92:17]
  assign io_async_safe_widx_valid = source_valid_1_io_out; // @[AsyncQueue.scala 117:20]
  assign io_async_safe_source_reset_n = ~reset; // @[AsyncQueue.scala 121:27]
  assign ridx_ridx_gray_clock = clock;
  assign ridx_ridx_gray_reset = reset;
  assign ridx_ridx_gray_io_d = io_async_ridx; // @[ShiftReg.scala 47:16]
  assign source_valid_0_io_in = 1'h1; // @[AsyncQueue.scala 115:26]
  assign source_valid_0_clock = clock; // @[AsyncQueue.scala 110:26]
  assign source_valid_0_reset = reset | ~io_async_safe_sink_reset_n; // @[AsyncQueue.scala 105:65]
  assign source_valid_1_io_in = source_valid_0_io_out; // @[AsyncQueue.scala 116:26]
  assign source_valid_1_clock = clock; // @[AsyncQueue.scala 111:26]
  assign source_valid_1_reset = reset | ~io_async_safe_sink_reset_n; // @[AsyncQueue.scala 106:65]
  assign sink_extend_io_in = io_async_safe_ridx_valid; // @[AsyncQueue.scala 118:23]
  assign sink_extend_clock = clock; // @[AsyncQueue.scala 112:26]
  assign sink_extend_reset = reset | ~io_async_safe_sink_reset_n; // @[AsyncQueue.scala 107:65]
  assign sink_valid_io_in = sink_extend_io_out; // @[AsyncQueue.scala 119:22]
  assign sink_valid_clock = clock; // @[AsyncQueue.scala 113:26]
  assign sink_valid_reset = reset; // @[AsyncQueue.scala 108:35]
  always @(posedge clock) begin
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      mem_0_opcode <= io_enq_bits_opcode; // @[AsyncQueue.scala 86:37]
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      mem_0_param <= io_enq_bits_param; // @[AsyncQueue.scala 86:37]
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      mem_0_size <= io_enq_bits_size; // @[AsyncQueue.scala 86:37]
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      mem_0_source <= io_enq_bits_source; // @[AsyncQueue.scala 86:37]
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      mem_0_address <= io_enq_bits_address; // @[AsyncQueue.scala 86:37]
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      mem_0_mask <= io_enq_bits_mask; // @[AsyncQueue.scala 86:37]
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      mem_0_data <= io_enq_bits_data; // @[AsyncQueue.scala 86:37]
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      mem_0_corrupt <= io_enq_bits_corrupt; // @[AsyncQueue.scala 86:37]
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[AsyncQueue.scala 53:23]
      widx_widx_bin <= 1'h0;
    end else if (_widx_T_2) begin
      widx_widx_bin <= 1'h0;
    end else begin
      widx_widx_bin <= widx_widx_bin + _widx_T_1;
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[AsyncQueue.scala 83:26]
      ready_reg <= 1'h0;
    end else begin
      ready_reg <= sink_ready & widx_incremented != (ridx ^ 1'h1);
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[AsyncQueue.scala 53:23]
      widx_gray <= 1'h0;
    end else if (_widx_T_2) begin
      widx_gray <= 1'h0;
    end else begin
      widx_gray <= widx_widx_bin + _widx_T_1;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  mem_0_opcode = _RAND_0[2:0];
  _RAND_1 = {1{`RANDOM}};
  mem_0_param = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  mem_0_size = _RAND_2[1:0];
  _RAND_3 = {1{`RANDOM}};
  mem_0_source = _RAND_3[6:0];
  _RAND_4 = {1{`RANDOM}};
  mem_0_address = _RAND_4[28:0];
  _RAND_5 = {1{`RANDOM}};
  mem_0_mask = _RAND_5[3:0];
  _RAND_6 = {1{`RANDOM}};
  mem_0_data = _RAND_6[31:0];
  _RAND_7 = {1{`RANDOM}};
  mem_0_corrupt = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  widx_widx_bin = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  ready_reg = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  widx_gray = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
  if (reset) begin
    widx_widx_bin = 1'h0;
  end
  if (reset) begin
    ready_reg = 1'h0;
  end
  if (reset) begin
    widx_gray = 1'h0;
  end
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ClockCrossingReg_w49(
  input         clock,
  input  [48:0] io_d,
  output [48:0] io_q,
  input         io_en
);
`ifdef RANDOMIZE_REG_INIT
  reg [63:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg [48:0] cdc_reg; // @[Reg.scala 16:16]
  assign io_q = cdc_reg; // @[SynchronizerReg.scala 202:8]
  always @(posedge clock) begin
    if (io_en) begin // @[Reg.scala 17:18]
      cdc_reg <= io_d; // @[Reg.scala 17:22]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {2{`RANDOM}};
  cdc_reg = _RAND_0[48:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module AsyncQueueSink(
  input         clock,
  input         reset,
  input         io_deq_ready,
  output        io_deq_valid,
  output [2:0]  io_deq_bits_opcode,
  output [1:0]  io_deq_bits_param,
  output [1:0]  io_deq_bits_size,
  output [6:0]  io_deq_bits_source,
  output        io_deq_bits_sink,
  output        io_deq_bits_denied,
  output [31:0] io_deq_bits_data,
  output        io_deq_bits_corrupt,
  input  [2:0]  io_async_mem_0_opcode,
  input  [1:0]  io_async_mem_0_param,
  input  [1:0]  io_async_mem_0_size,
  input  [6:0]  io_async_mem_0_source,
  input         io_async_mem_0_sink,
  input         io_async_mem_0_denied,
  input  [31:0] io_async_mem_0_data,
  input         io_async_mem_0_corrupt,
  output        io_async_ridx,
  input         io_async_widx,
  output        io_async_safe_ridx_valid,
  input         io_async_safe_widx_valid,
  input         io_async_safe_source_reset_n,
  output        io_async_safe_sink_reset_n
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
  wire  widx_widx_gray_clock; // @[ShiftReg.scala 45:23]
  wire  widx_widx_gray_reset; // @[ShiftReg.scala 45:23]
  wire  widx_widx_gray_io_d; // @[ShiftReg.scala 45:23]
  wire  widx_widx_gray_io_q; // @[ShiftReg.scala 45:23]
  wire  io_deq_bits_deq_bits_reg_clock; // @[SynchronizerReg.scala 207:25]
  wire [48:0] io_deq_bits_deq_bits_reg_io_d; // @[SynchronizerReg.scala 207:25]
  wire [48:0] io_deq_bits_deq_bits_reg_io_q; // @[SynchronizerReg.scala 207:25]
  wire  io_deq_bits_deq_bits_reg_io_en; // @[SynchronizerReg.scala 207:25]
  wire  sink_valid_0_io_in; // @[AsyncQueue.scala 168:33]
  wire  sink_valid_0_io_out; // @[AsyncQueue.scala 168:33]
  wire  sink_valid_0_clock; // @[AsyncQueue.scala 168:33]
  wire  sink_valid_0_reset; // @[AsyncQueue.scala 168:33]
  wire  sink_valid_1_io_in; // @[AsyncQueue.scala 169:33]
  wire  sink_valid_1_io_out; // @[AsyncQueue.scala 169:33]
  wire  sink_valid_1_clock; // @[AsyncQueue.scala 169:33]
  wire  sink_valid_1_reset; // @[AsyncQueue.scala 169:33]
  wire  source_extend_io_in; // @[AsyncQueue.scala 171:31]
  wire  source_extend_io_out; // @[AsyncQueue.scala 171:31]
  wire  source_extend_clock; // @[AsyncQueue.scala 171:31]
  wire  source_extend_reset; // @[AsyncQueue.scala 171:31]
  wire  source_valid_io_in; // @[AsyncQueue.scala 172:31]
  wire  source_valid_io_out; // @[AsyncQueue.scala 172:31]
  wire  source_valid_clock; // @[AsyncQueue.scala 172:31]
  wire  source_valid_reset; // @[AsyncQueue.scala 172:31]
  wire  _ridx_T_1 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
  wire  source_ready = source_valid_io_out;
  wire  _ridx_T_2 = ~source_ready; // @[AsyncQueue.scala 144:79]
  reg  ridx_ridx_bin; // @[AsyncQueue.scala 52:25]
  wire  ridx_incremented = _ridx_T_2 ? 1'h0 : ridx_ridx_bin + _ridx_T_1; // @[AsyncQueue.scala 53:23]
  wire  widx = widx_widx_gray_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire [34:0] io_deq_bits_deq_bits_reg_io_d_lo = {io_async_mem_0_sink,io_async_mem_0_denied,io_async_mem_0_data,
    io_async_mem_0_corrupt}; // @[SynchronizerReg.scala 209:24]
  wire [13:0] io_deq_bits_deq_bits_reg_io_d_hi = {io_async_mem_0_opcode,io_async_mem_0_param,io_async_mem_0_size,
    io_async_mem_0_source}; // @[SynchronizerReg.scala 209:24]
  wire [48:0] _io_deq_bits_WIRE_1 = io_deq_bits_deq_bits_reg_io_q;
  reg  valid_reg; // @[AsyncQueue.scala 161:56]
  reg  ridx_gray; // @[AsyncQueue.scala 164:55]
  AsyncResetSynchronizerShiftReg_w1_d3_i0 widx_widx_gray ( // @[ShiftReg.scala 45:23]
    .clock(widx_widx_gray_clock),
    .reset(widx_widx_gray_reset),
    .io_d(widx_widx_gray_io_d),
    .io_q(widx_widx_gray_io_q)
  );
  ClockCrossingReg_w49 io_deq_bits_deq_bits_reg ( // @[SynchronizerReg.scala 207:25]
    .clock(io_deq_bits_deq_bits_reg_clock),
    .io_d(io_deq_bits_deq_bits_reg_io_d),
    .io_q(io_deq_bits_deq_bits_reg_io_q),
    .io_en(io_deq_bits_deq_bits_reg_io_en)
  );
  AsyncValidSync sink_valid_0 ( // @[AsyncQueue.scala 168:33]
    .io_in(sink_valid_0_io_in),
    .io_out(sink_valid_0_io_out),
    .clock(sink_valid_0_clock),
    .reset(sink_valid_0_reset)
  );
  AsyncValidSync sink_valid_1 ( // @[AsyncQueue.scala 169:33]
    .io_in(sink_valid_1_io_in),
    .io_out(sink_valid_1_io_out),
    .clock(sink_valid_1_clock),
    .reset(sink_valid_1_reset)
  );
  AsyncValidSync source_extend ( // @[AsyncQueue.scala 171:31]
    .io_in(source_extend_io_in),
    .io_out(source_extend_io_out),
    .clock(source_extend_clock),
    .reset(source_extend_reset)
  );
  AsyncValidSync source_valid ( // @[AsyncQueue.scala 172:31]
    .io_in(source_valid_io_in),
    .io_out(source_valid_io_out),
    .clock(source_valid_clock),
    .reset(source_valid_reset)
  );
  assign io_deq_valid = valid_reg & source_ready; // @[AsyncQueue.scala 162:29]
  assign io_deq_bits_opcode = _io_deq_bits_WIRE_1[48:46]; // @[SynchronizerReg.scala 211:26]
  assign io_deq_bits_param = _io_deq_bits_WIRE_1[45:44]; // @[SynchronizerReg.scala 211:26]
  assign io_deq_bits_size = _io_deq_bits_WIRE_1[43:42]; // @[SynchronizerReg.scala 211:26]
  assign io_deq_bits_source = _io_deq_bits_WIRE_1[41:35]; // @[SynchronizerReg.scala 211:26]
  assign io_deq_bits_sink = _io_deq_bits_WIRE_1[34]; // @[SynchronizerReg.scala 211:26]
  assign io_deq_bits_denied = _io_deq_bits_WIRE_1[33]; // @[SynchronizerReg.scala 211:26]
  assign io_deq_bits_data = _io_deq_bits_WIRE_1[32:1]; // @[SynchronizerReg.scala 211:26]
  assign io_deq_bits_corrupt = _io_deq_bits_WIRE_1[0]; // @[SynchronizerReg.scala 211:26]
  assign io_async_ridx = ridx_gray; // @[AsyncQueue.scala 165:17]
  assign io_async_safe_ridx_valid = sink_valid_1_io_out; // @[AsyncQueue.scala 185:20]
  assign io_async_safe_sink_reset_n = ~reset; // @[AsyncQueue.scala 189:25]
  assign widx_widx_gray_clock = clock;
  assign widx_widx_gray_reset = reset;
  assign widx_widx_gray_io_d = io_async_widx; // @[ShiftReg.scala 47:16]
  assign io_deq_bits_deq_bits_reg_clock = clock;
  assign io_deq_bits_deq_bits_reg_io_d = {io_deq_bits_deq_bits_reg_io_d_hi,io_deq_bits_deq_bits_reg_io_d_lo}; // @[SynchronizerReg.scala 209:24]
  assign io_deq_bits_deq_bits_reg_io_en = source_ready & ridx_incremented != widx; // @[AsyncQueue.scala 146:28]
  assign sink_valid_0_io_in = 1'h1; // @[AsyncQueue.scala 183:24]
  assign sink_valid_0_clock = clock; // @[AsyncQueue.scala 178:25]
  assign sink_valid_0_reset = reset | ~io_async_safe_source_reset_n; // @[AsyncQueue.scala 173:66]
  assign sink_valid_1_io_in = sink_valid_0_io_out; // @[AsyncQueue.scala 184:24]
  assign sink_valid_1_clock = clock; // @[AsyncQueue.scala 179:25]
  assign sink_valid_1_reset = reset | ~io_async_safe_source_reset_n; // @[AsyncQueue.scala 174:66]
  assign source_extend_io_in = io_async_safe_widx_valid; // @[AsyncQueue.scala 186:25]
  assign source_extend_clock = clock; // @[AsyncQueue.scala 180:25]
  assign source_extend_reset = reset | ~io_async_safe_source_reset_n; // @[AsyncQueue.scala 175:66]
  assign source_valid_io_in = source_extend_io_out; // @[AsyncQueue.scala 187:24]
  assign source_valid_clock = clock; // @[AsyncQueue.scala 181:25]
  assign source_valid_reset = reset; // @[AsyncQueue.scala 176:34]
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[AsyncQueue.scala 53:23]
      ridx_ridx_bin <= 1'h0;
    end else if (_ridx_T_2) begin
      ridx_ridx_bin <= 1'h0;
    end else begin
      ridx_ridx_bin <= ridx_ridx_bin + _ridx_T_1;
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[AsyncQueue.scala 146:28]
      valid_reg <= 1'h0;
    end else begin
      valid_reg <= source_ready & ridx_incremented != widx;
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[AsyncQueue.scala 53:23]
      ridx_gray <= 1'h0;
    end else if (_ridx_T_2) begin
      ridx_gray <= 1'h0;
    end else begin
      ridx_gray <= ridx_ridx_bin + _ridx_T_1;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  ridx_ridx_bin = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  valid_reg = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  ridx_gray = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
  if (reset) begin
    ridx_ridx_bin = 1'h0;
  end
  if (reset) begin
    valid_reg = 1'h0;
  end
  if (reset) begin
    ridx_gray = 1'h0;
  end
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLAsyncCrossingSource(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [1:0]  auto_in_a_bits_size,
  input  [6:0]  auto_in_a_bits_source,
  input  [28:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [1:0]  auto_in_d_bits_param,
  output [1:0]  auto_in_d_bits_size,
  output [6:0]  auto_in_d_bits_source,
  output        auto_in_d_bits_sink,
  output        auto_in_d_bits_denied,
  output [31:0] auto_in_d_bits_data,
  output        auto_in_d_bits_corrupt,
  output [2:0]  auto_out_a_mem_0_opcode,
  output [2:0]  auto_out_a_mem_0_param,
  output [1:0]  auto_out_a_mem_0_size,
  output [6:0]  auto_out_a_mem_0_source,
  output [28:0] auto_out_a_mem_0_address,
  output [3:0]  auto_out_a_mem_0_mask,
  output [31:0] auto_out_a_mem_0_data,
  output        auto_out_a_mem_0_corrupt,
  input         auto_out_a_ridx,
  output        auto_out_a_widx,
  input         auto_out_a_safe_ridx_valid,
  output        auto_out_a_safe_widx_valid,
  output        auto_out_a_safe_source_reset_n,
  input         auto_out_a_safe_sink_reset_n,
  input  [2:0]  auto_out_d_mem_0_opcode,
  input  [1:0]  auto_out_d_mem_0_param,
  input  [1:0]  auto_out_d_mem_0_size,
  input  [6:0]  auto_out_d_mem_0_source,
  input         auto_out_d_mem_0_sink,
  input         auto_out_d_mem_0_denied,
  input  [31:0] auto_out_d_mem_0_data,
  input         auto_out_d_mem_0_corrupt,
  output        auto_out_d_ridx,
  input         auto_out_d_widx,
  output        auto_out_d_safe_ridx_valid,
  input         auto_out_d_safe_widx_valid,
  input         auto_out_d_safe_source_reset_n,
  output        auto_out_d_safe_sink_reset_n
);
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
  wire  bundleOut_0_a_source_clock; // @[AsyncQueue.scala 216:24]
  wire  bundleOut_0_a_source_reset; // @[AsyncQueue.scala 216:24]
  wire  bundleOut_0_a_source_io_enq_ready; // @[AsyncQueue.scala 216:24]
  wire  bundleOut_0_a_source_io_enq_valid; // @[AsyncQueue.scala 216:24]
  wire [2:0] bundleOut_0_a_source_io_enq_bits_opcode; // @[AsyncQueue.scala 216:24]
  wire [2:0] bundleOut_0_a_source_io_enq_bits_param; // @[AsyncQueue.scala 216:24]
  wire [1:0] bundleOut_0_a_source_io_enq_bits_size; // @[AsyncQueue.scala 216:24]
  wire [6:0] bundleOut_0_a_source_io_enq_bits_source; // @[AsyncQueue.scala 216:24]
  wire [28:0] bundleOut_0_a_source_io_enq_bits_address; // @[AsyncQueue.scala 216:24]
  wire [3:0] bundleOut_0_a_source_io_enq_bits_mask; // @[AsyncQueue.scala 216:24]
  wire [31:0] bundleOut_0_a_source_io_enq_bits_data; // @[AsyncQueue.scala 216:24]
  wire  bundleOut_0_a_source_io_enq_bits_corrupt; // @[AsyncQueue.scala 216:24]
  wire [2:0] bundleOut_0_a_source_io_async_mem_0_opcode; // @[AsyncQueue.scala 216:24]
  wire [2:0] bundleOut_0_a_source_io_async_mem_0_param; // @[AsyncQueue.scala 216:24]
  wire [1:0] bundleOut_0_a_source_io_async_mem_0_size; // @[AsyncQueue.scala 216:24]
  wire [6:0] bundleOut_0_a_source_io_async_mem_0_source; // @[AsyncQueue.scala 216:24]
  wire [28:0] bundleOut_0_a_source_io_async_mem_0_address; // @[AsyncQueue.scala 216:24]
  wire [3:0] bundleOut_0_a_source_io_async_mem_0_mask; // @[AsyncQueue.scala 216:24]
  wire [31:0] bundleOut_0_a_source_io_async_mem_0_data; // @[AsyncQueue.scala 216:24]
  wire  bundleOut_0_a_source_io_async_mem_0_corrupt; // @[AsyncQueue.scala 216:24]
  wire  bundleOut_0_a_source_io_async_ridx; // @[AsyncQueue.scala 216:24]
  wire  bundleOut_0_a_source_io_async_widx; // @[AsyncQueue.scala 216:24]
  wire  bundleOut_0_a_source_io_async_safe_ridx_valid; // @[AsyncQueue.scala 216:24]
  wire  bundleOut_0_a_source_io_async_safe_widx_valid; // @[AsyncQueue.scala 216:24]
  wire  bundleOut_0_a_source_io_async_safe_source_reset_n; // @[AsyncQueue.scala 216:24]
  wire  bundleOut_0_a_source_io_async_safe_sink_reset_n; // @[AsyncQueue.scala 216:24]
  wire  bundleIn_0_d_sink_clock; // @[AsyncQueue.scala 207:22]
  wire  bundleIn_0_d_sink_reset; // @[AsyncQueue.scala 207:22]
  wire  bundleIn_0_d_sink_io_deq_ready; // @[AsyncQueue.scala 207:22]
  wire  bundleIn_0_d_sink_io_deq_valid; // @[AsyncQueue.scala 207:22]
  wire [2:0] bundleIn_0_d_sink_io_deq_bits_opcode; // @[AsyncQueue.scala 207:22]
  wire [1:0] bundleIn_0_d_sink_io_deq_bits_param; // @[AsyncQueue.scala 207:22]
  wire [1:0] bundleIn_0_d_sink_io_deq_bits_size; // @[AsyncQueue.scala 207:22]
  wire [6:0] bundleIn_0_d_sink_io_deq_bits_source; // @[AsyncQueue.scala 207:22]
  wire  bundleIn_0_d_sink_io_deq_bits_sink; // @[AsyncQueue.scala 207:22]
  wire  bundleIn_0_d_sink_io_deq_bits_denied; // @[AsyncQueue.scala 207:22]
  wire [31:0] bundleIn_0_d_sink_io_deq_bits_data; // @[AsyncQueue.scala 207:22]
  wire  bundleIn_0_d_sink_io_deq_bits_corrupt; // @[AsyncQueue.scala 207:22]
  wire [2:0] bundleIn_0_d_sink_io_async_mem_0_opcode; // @[AsyncQueue.scala 207:22]
  wire [1:0] bundleIn_0_d_sink_io_async_mem_0_param; // @[AsyncQueue.scala 207:22]
  wire [1:0] bundleIn_0_d_sink_io_async_mem_0_size; // @[AsyncQueue.scala 207:22]
  wire [6:0] bundleIn_0_d_sink_io_async_mem_0_source; // @[AsyncQueue.scala 207:22]
  wire  bundleIn_0_d_sink_io_async_mem_0_sink; // @[AsyncQueue.scala 207:22]
  wire  bundleIn_0_d_sink_io_async_mem_0_denied; // @[AsyncQueue.scala 207:22]
  wire [31:0] bundleIn_0_d_sink_io_async_mem_0_data; // @[AsyncQueue.scala 207:22]
  wire  bundleIn_0_d_sink_io_async_mem_0_corrupt; // @[AsyncQueue.scala 207:22]
  wire  bundleIn_0_d_sink_io_async_ridx; // @[AsyncQueue.scala 207:22]
  wire  bundleIn_0_d_sink_io_async_widx; // @[AsyncQueue.scala 207:22]
  wire  bundleIn_0_d_sink_io_async_safe_ridx_valid; // @[AsyncQueue.scala 207:22]
  wire  bundleIn_0_d_sink_io_async_safe_widx_valid; // @[AsyncQueue.scala 207:22]
  wire  bundleIn_0_d_sink_io_async_safe_source_reset_n; // @[AsyncQueue.scala 207:22]
  wire  bundleIn_0_d_sink_io_async_safe_sink_reset_n; // @[AsyncQueue.scala 207:22]
  TLMonitor_33 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_param(monitor_io_in_d_bits_param),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source),
    .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
    .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
    .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
  );
  AsyncQueueSource bundleOut_0_a_source ( // @[AsyncQueue.scala 216:24]
    .clock(bundleOut_0_a_source_clock),
    .reset(bundleOut_0_a_source_reset),
    .io_enq_ready(bundleOut_0_a_source_io_enq_ready),
    .io_enq_valid(bundleOut_0_a_source_io_enq_valid),
    .io_enq_bits_opcode(bundleOut_0_a_source_io_enq_bits_opcode),
    .io_enq_bits_param(bundleOut_0_a_source_io_enq_bits_param),
    .io_enq_bits_size(bundleOut_0_a_source_io_enq_bits_size),
    .io_enq_bits_source(bundleOut_0_a_source_io_enq_bits_source),
    .io_enq_bits_address(bundleOut_0_a_source_io_enq_bits_address),
    .io_enq_bits_mask(bundleOut_0_a_source_io_enq_bits_mask),
    .io_enq_bits_data(bundleOut_0_a_source_io_enq_bits_data),
    .io_enq_bits_corrupt(bundleOut_0_a_source_io_enq_bits_corrupt),
    .io_async_mem_0_opcode(bundleOut_0_a_source_io_async_mem_0_opcode),
    .io_async_mem_0_param(bundleOut_0_a_source_io_async_mem_0_param),
    .io_async_mem_0_size(bundleOut_0_a_source_io_async_mem_0_size),
    .io_async_mem_0_source(bundleOut_0_a_source_io_async_mem_0_source),
    .io_async_mem_0_address(bundleOut_0_a_source_io_async_mem_0_address),
    .io_async_mem_0_mask(bundleOut_0_a_source_io_async_mem_0_mask),
    .io_async_mem_0_data(bundleOut_0_a_source_io_async_mem_0_data),
    .io_async_mem_0_corrupt(bundleOut_0_a_source_io_async_mem_0_corrupt),
    .io_async_ridx(bundleOut_0_a_source_io_async_ridx),
    .io_async_widx(bundleOut_0_a_source_io_async_widx),
    .io_async_safe_ridx_valid(bundleOut_0_a_source_io_async_safe_ridx_valid),
    .io_async_safe_widx_valid(bundleOut_0_a_source_io_async_safe_widx_valid),
    .io_async_safe_source_reset_n(bundleOut_0_a_source_io_async_safe_source_reset_n),
    .io_async_safe_sink_reset_n(bundleOut_0_a_source_io_async_safe_sink_reset_n)
  );
  AsyncQueueSink bundleIn_0_d_sink ( // @[AsyncQueue.scala 207:22]
    .clock(bundleIn_0_d_sink_clock),
    .reset(bundleIn_0_d_sink_reset),
    .io_deq_ready(bundleIn_0_d_sink_io_deq_ready),
    .io_deq_valid(bundleIn_0_d_sink_io_deq_valid),
    .io_deq_bits_opcode(bundleIn_0_d_sink_io_deq_bits_opcode),
    .io_deq_bits_param(bundleIn_0_d_sink_io_deq_bits_param),
    .io_deq_bits_size(bundleIn_0_d_sink_io_deq_bits_size),
    .io_deq_bits_source(bundleIn_0_d_sink_io_deq_bits_source),
    .io_deq_bits_sink(bundleIn_0_d_sink_io_deq_bits_sink),
    .io_deq_bits_denied(bundleIn_0_d_sink_io_deq_bits_denied),
    .io_deq_bits_data(bundleIn_0_d_sink_io_deq_bits_data),
    .io_deq_bits_corrupt(bundleIn_0_d_sink_io_deq_bits_corrupt),
    .io_async_mem_0_opcode(bundleIn_0_d_sink_io_async_mem_0_opcode),
    .io_async_mem_0_param(bundleIn_0_d_sink_io_async_mem_0_param),
    .io_async_mem_0_size(bundleIn_0_d_sink_io_async_mem_0_size),
    .io_async_mem_0_source(bundleIn_0_d_sink_io_async_mem_0_source),
    .io_async_mem_0_sink(bundleIn_0_d_sink_io_async_mem_0_sink),
    .io_async_mem_0_denied(bundleIn_0_d_sink_io_async_mem_0_denied),
    .io_async_mem_0_data(bundleIn_0_d_sink_io_async_mem_0_data),
    .io_async_mem_0_corrupt(bundleIn_0_d_sink_io_async_mem_0_corrupt),
    .io_async_ridx(bundleIn_0_d_sink_io_async_ridx),
    .io_async_widx(bundleIn_0_d_sink_io_async_widx),
    .io_async_safe_ridx_valid(bundleIn_0_d_sink_io_async_safe_ridx_valid),
    .io_async_safe_widx_valid(bundleIn_0_d_sink_io_async_safe_widx_valid),
    .io_async_safe_source_reset_n(bundleIn_0_d_sink_io_async_safe_source_reset_n),
    .io_async_safe_sink_reset_n(bundleIn_0_d_sink_io_async_safe_sink_reset_n)
  );
  assign auto_in_a_ready = bundleOut_0_a_source_io_enq_ready; // @[Nodes.scala 1210:84 AsyncQueue.scala 217:19]
  assign auto_in_d_valid = bundleIn_0_d_sink_io_deq_valid; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
  assign auto_in_d_bits_opcode = bundleIn_0_d_sink_io_deq_bits_opcode; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
  assign auto_in_d_bits_param = bundleIn_0_d_sink_io_deq_bits_param; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
  assign auto_in_d_bits_size = bundleIn_0_d_sink_io_deq_bits_size; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
  assign auto_in_d_bits_source = bundleIn_0_d_sink_io_deq_bits_source; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
  assign auto_in_d_bits_sink = bundleIn_0_d_sink_io_deq_bits_sink; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
  assign auto_in_d_bits_denied = bundleIn_0_d_sink_io_deq_bits_denied; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
  assign auto_in_d_bits_data = bundleIn_0_d_sink_io_deq_bits_data; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
  assign auto_in_d_bits_corrupt = bundleIn_0_d_sink_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
  assign auto_out_a_mem_0_opcode = bundleOut_0_a_source_io_async_mem_0_opcode; // @[Nodes.scala 1207:84 AsyncCrossing.scala 25:13]
  assign auto_out_a_mem_0_param = bundleOut_0_a_source_io_async_mem_0_param; // @[Nodes.scala 1207:84 AsyncCrossing.scala 25:13]
  assign auto_out_a_mem_0_size = bundleOut_0_a_source_io_async_mem_0_size; // @[Nodes.scala 1207:84 AsyncCrossing.scala 25:13]
  assign auto_out_a_mem_0_source = bundleOut_0_a_source_io_async_mem_0_source; // @[Nodes.scala 1207:84 AsyncCrossing.scala 25:13]
  assign auto_out_a_mem_0_address = bundleOut_0_a_source_io_async_mem_0_address; // @[Nodes.scala 1207:84 AsyncCrossing.scala 25:13]
  assign auto_out_a_mem_0_mask = bundleOut_0_a_source_io_async_mem_0_mask; // @[Nodes.scala 1207:84 AsyncCrossing.scala 25:13]
  assign auto_out_a_mem_0_data = bundleOut_0_a_source_io_async_mem_0_data; // @[Nodes.scala 1207:84 AsyncCrossing.scala 25:13]
  assign auto_out_a_mem_0_corrupt = bundleOut_0_a_source_io_async_mem_0_corrupt; // @[Nodes.scala 1207:84 AsyncCrossing.scala 25:13]
  assign auto_out_a_widx = bundleOut_0_a_source_io_async_widx; // @[Nodes.scala 1207:84 AsyncCrossing.scala 25:13]
  assign auto_out_a_safe_widx_valid = bundleOut_0_a_source_io_async_safe_widx_valid; // @[Nodes.scala 1207:84 AsyncCrossing.scala 25:13]
  assign auto_out_a_safe_source_reset_n = bundleOut_0_a_source_io_async_safe_source_reset_n; // @[Nodes.scala 1207:84 AsyncCrossing.scala 25:13]
  assign auto_out_d_ridx = bundleIn_0_d_sink_io_async_ridx; // @[Nodes.scala 1207:84 AsyncQueue.scala 208:19]
  assign auto_out_d_safe_ridx_valid = bundleIn_0_d_sink_io_async_safe_ridx_valid; // @[Nodes.scala 1207:84 AsyncQueue.scala 208:19]
  assign auto_out_d_safe_sink_reset_n = bundleIn_0_d_sink_io_async_safe_sink_reset_n; // @[Nodes.scala 1207:84 AsyncQueue.scala 208:19]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = bundleOut_0_a_source_io_enq_ready; // @[Nodes.scala 1210:84 AsyncQueue.scala 217:19]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = bundleIn_0_d_sink_io_deq_valid; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
  assign monitor_io_in_d_bits_opcode = bundleIn_0_d_sink_io_deq_bits_opcode; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
  assign monitor_io_in_d_bits_param = bundleIn_0_d_sink_io_deq_bits_param; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
  assign monitor_io_in_d_bits_size = bundleIn_0_d_sink_io_deq_bits_size; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
  assign monitor_io_in_d_bits_source = bundleIn_0_d_sink_io_deq_bits_source; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
  assign monitor_io_in_d_bits_sink = bundleIn_0_d_sink_io_deq_bits_sink; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
  assign monitor_io_in_d_bits_denied = bundleIn_0_d_sink_io_deq_bits_denied; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
  assign monitor_io_in_d_bits_corrupt = bundleIn_0_d_sink_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
  assign bundleOut_0_a_source_clock = clock;
  assign bundleOut_0_a_source_reset = reset;
  assign bundleOut_0_a_source_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_source_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_source_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_source_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_source_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_source_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_source_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_source_io_enq_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_source_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_source_io_async_ridx = auto_out_a_ridx; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleOut_0_a_source_io_async_safe_ridx_valid = auto_out_a_safe_ridx_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleOut_0_a_source_io_async_safe_sink_reset_n = auto_out_a_safe_sink_reset_n; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_sink_clock = clock;
  assign bundleIn_0_d_sink_reset = reset;
  assign bundleIn_0_d_sink_io_deq_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleIn_0_d_sink_io_async_mem_0_opcode = auto_out_d_mem_0_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_sink_io_async_mem_0_param = auto_out_d_mem_0_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_sink_io_async_mem_0_size = auto_out_d_mem_0_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_sink_io_async_mem_0_source = auto_out_d_mem_0_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_sink_io_async_mem_0_sink = auto_out_d_mem_0_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_sink_io_async_mem_0_denied = auto_out_d_mem_0_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_sink_io_async_mem_0_data = auto_out_d_mem_0_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_sink_io_async_mem_0_corrupt = auto_out_d_mem_0_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_sink_io_async_widx = auto_out_d_widx; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_sink_io_async_safe_widx_valid = auto_out_d_safe_widx_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_sink_io_async_safe_source_reset_n = auto_out_d_safe_source_reset_n; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
endmodule
module TLMonitor_34(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [28:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_param,
  input  [2:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source,
  input         io_in_d_bits_sink,
  input         io_in_d_bits_denied,
  input         io_in_d_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
  wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
  wire [28:0] _GEN_71 = {{23'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [28:0] _T_45 = io_in_a_bits_address ^ 29'h10000000; // @[Parameters.scala 137:31]
  wire [29:0] _T_46 = {1'b0,$signed(_T_45)}; // @[Parameters.scala 137:49]
  wire [29:0] _T_48 = $signed(_T_46) & -30'sh1000; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 30'sh0; // @[Parameters.scala 137:67]
  wire  _T_59 = 3'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_60 = _source_ok_T & _T_59; // @[Mux.scala 27:73]
  wire  _T_76 = _T_60 & _T_49; // @[Monitor.scala 83:78]
  wire  _T_90 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_94 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_95 = _T_94 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_99 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_103 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_164 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_177 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_192 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
  wire  _T_200 = _T_192 & _T_49; // @[Parameters.scala 670:56]
  wire  _T_211 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_215 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_223 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_245 = source_ok & _T_200; // @[Monitor.scala 115:71]
  wire  _T_263 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_299 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_300 = io_in_a_bits_mask & _T_299; // @[Monitor.scala 127:31]
  wire  _T_301 = _T_300 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_305 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_334 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_342 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_371 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_379 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_408 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_420 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  _T_424 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_428 = io_in_d_bits_size >= 3'h2; // @[Monitor.scala 312:27]
  wire  _T_432 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
  wire  _T_436 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
  wire  _T_440 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
  wire  _T_444 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_455 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
  wire  _T_459 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
  wire  _T_472 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_492 = _T_440 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
  wire  _T_501 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_518 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_536 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [3:0] a_first_beats1_decode = is_aligned_mask[5:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] a_first_counter; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1 = a_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [28:0] address; // @[Monitor.scala 388:22]
  wire  _T_566 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_567 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_571 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_575 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_579 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_583 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
  wire [3:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [3:0] d_first_counter; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1 = d_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] param_1; // @[Monitor.scala 536:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  reg  sink; // @[Monitor.scala 539:22]
  reg  denied; // @[Monitor.scala 540:22]
  wire  _T_590 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_591 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_595 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
  wire  _T_599 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_603 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  wire  _T_607 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
  wire  _T_611 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [11:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [3:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1_1 = a_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  reg [3:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_1 = d_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [11:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _GEN_76 = {{4'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_76 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_617 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_620 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [34:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [34:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_622 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_624 = ~_T_622[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_16 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [34:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_628 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_630 = ~_T_424; // @[Monitor.scala 671:74]
  wire  _T_631 = io_in_d_valid & d_first_1 & ~_T_424; // @[Monitor.scala 671:71]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_424 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 671:90 672:22]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [3:0] _GEN_22 = _d_first_T & d_first_1 & _T_630 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_23 = _d_first_T & d_first_1 & _T_630 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_617 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_641 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_643 = _T_641[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_648 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_649 = io_in_d_bits_opcode == _GEN_32 | _T_648; // @[Monitor.scala 685:77]
  wire  _T_653 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_660 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_661 = io_in_d_bits_opcode == _GEN_48 | _T_660; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_665 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_675 = _T_628 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_630; // @[Monitor.scala 694:116]
  wire  _T_677 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set_wo_ready = _GEN_15[2:0];
  wire [2:0] d_clr_wo_ready = _GEN_21[2:0];
  wire  _T_684 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire [2:0] a_set = _GEN_16[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_22[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_19[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_23[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [11:0] a_sizes_set = _GEN_20[11:0];
  wire [11:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [11:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_693 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [2:0] inflight_1; // @[Monitor.scala 723:35]
  reg [11:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [3:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_2 = d_first_counter_2 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 4'h0; // @[Edges.scala 230:25]
  wire [11:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [15:0] _GEN_87 = {{4'd0}, _c_size_lookup_T_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_87 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_719 = io_in_d_valid & d_first_2 & _T_424; // @[Monitor.scala 779:71]
  wire [3:0] _GEN_67 = _d_first_T & d_first_2 & _T_424 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 783:90 784:21]
  wire [46:0] _GEN_68 = _d_first_T & d_first_2 & _T_424 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 785:21]
  wire [2:0] _T_727 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_737 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [2:0] d_clr_1 = _GEN_67[2:0];
  wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [2:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [11:0] d_opcodes_clr_1 = _GEN_68[11:0];
  wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [11:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_762 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 4'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 4'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 12'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 4'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 4'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 3'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 12'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 4'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_164 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_164) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_200 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_200) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_245 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_301 & (io_in_a_valid & _T_263 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_263 & ~reset & ~_T_301) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_334 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_334) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_305 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_305 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_371 & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~_T_371) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_342 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_342 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_408 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_408) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_379 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_379 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_420 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_420) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_432 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~_T_432) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_436 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~_T_436) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_440 & (io_in_d_valid & _T_424 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_424 & _T_2 & ~_T_440) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is denied (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_455 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~_T_455) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid cap param (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_459 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~_T_459) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries toN param (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_436 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~_T_436) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is corrupt (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_440 & (io_in_d_valid & _T_444 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_444 & _T_2 & ~_T_440) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is denied (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_428 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~_T_428) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_455 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~_T_455) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_459 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~_T_459) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries toN param (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_492 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~_T_492) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_440 & (io_in_d_valid & _T_472 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_472 & _T_2 & ~_T_440) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_501 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_501 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_432 & (io_in_d_valid & _T_501 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_501 & _T_2 & ~_T_432) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid param (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_436 & (io_in_d_valid & _T_501 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_501 & _T_2 & ~_T_436) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is corrupt (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_440 & (io_in_d_valid & _T_501 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_501 & _T_2 & ~_T_440) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is denied (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_518 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_518 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_432 & (io_in_d_valid & _T_518 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_518 & _T_2 & ~_T_432) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_492 & (io_in_d_valid & _T_518 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_518 & _T_2 & ~_T_492) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_440 & (io_in_d_valid & _T_518 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_518 & _T_2 & ~_T_440) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_536 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_536 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_432 & (io_in_d_valid & _T_536 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_536 & _T_2 & ~_T_432) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid param (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_436 & (io_in_d_valid & _T_536 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_536 & _T_2 & ~_T_436) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is corrupt (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_440 & (io_in_d_valid & _T_536 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_536 & _T_2 & ~_T_440) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is denied (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_567 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_567) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_571 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_571) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_575 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_575) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_579 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_579) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_583 & (_T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_566 & ~reset & ~_T_583) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_591 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_591) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_595 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_595) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel param changed within multibeat operation (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_599 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_599) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_603 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_603) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_607 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_607) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel sink changed with multibeat operation (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_611 & (_T_590 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & _T_2 & ~_T_611) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel denied changed with multibeat operation (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_624 & (_T_620 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_620 & ~reset & ~_T_624) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_643 & (_T_631 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & _T_2 & ~_T_643) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_649 & (_T_631 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & same_cycle_resp & _T_2 & ~_T_649) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_653 & (_T_631 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & same_cycle_resp & _T_2 & ~_T_653) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_661 & (_T_631 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & ~same_cycle_resp & _T_2 & ~_T_661) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_665 & (_T_631 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & ~same_cycle_resp & _T_2 & ~_T_665) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_677 & (_T_675 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_675 & _T_2 & ~_T_677) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_684 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_684) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 4 (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_693 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_693) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_727[0] & (_T_719 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_719 & _T_2 & ~_T_727[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_737 & (_T_719 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_719 & _T_2 & ~_T_737) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_762 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_762) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at MockAONPeriphery.scala:22:84)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[28:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  param_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  size_1 = _RAND_9[2:0];
  _RAND_10 = {1{`RANDOM}};
  source_1 = _RAND_10[1:0];
  _RAND_11 = {1{`RANDOM}};
  sink = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  denied = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  inflight = _RAND_13[2:0];
  _RAND_14 = {1{`RANDOM}};
  inflight_opcodes = _RAND_14[11:0];
  _RAND_15 = {1{`RANDOM}};
  inflight_sizes = _RAND_15[11:0];
  _RAND_16 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_16[3:0];
  _RAND_17 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_17[3:0];
  _RAND_18 = {1{`RANDOM}};
  watchdog = _RAND_18[31:0];
  _RAND_19 = {1{`RANDOM}};
  inflight_1 = _RAND_19[2:0];
  _RAND_20 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_20[11:0];
  _RAND_21 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_21[3:0];
  _RAND_22 = {1{`RANDOM}};
  watchdog_1 = _RAND_22[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLFragmenter_18(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [28:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [1:0]  auto_in_d_bits_param,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output        auto_in_d_bits_sink,
  output        auto_in_d_bits_denied,
  output [31:0] auto_in_d_bits_data,
  output        auto_in_d_bits_corrupt,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [1:0]  auto_out_a_bits_size,
  output [6:0]  auto_out_a_bits_source,
  output [28:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_param,
  input  [1:0]  auto_out_d_bits_size,
  input  [6:0]  auto_out_d_bits_source,
  input         auto_out_d_bits_sink,
  input         auto_out_d_bits_denied,
  input  [31:0] auto_out_d_bits_data,
  input         auto_out_d_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
  wire  repeater_clock; // @[Fragmenter.scala 262:30]
  wire  repeater_reset; // @[Fragmenter.scala 262:30]
  wire  repeater_io_repeat; // @[Fragmenter.scala 262:30]
  wire  repeater_io_full; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
  wire [28:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
  wire [28:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
  reg [3:0] acknum; // @[Fragmenter.scala 189:29]
  reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
  reg  dToggle; // @[Fragmenter.scala 191:30]
  wire [3:0] dFragnum = auto_out_d_bits_source[3:0]; // @[Fragmenter.scala 192:41]
  wire  dFirst = acknum == 4'h0; // @[Fragmenter.scala 193:29]
  wire  dLast = dFragnum == 4'h0; // @[Fragmenter.scala 194:30]
  wire [3:0] _dsizeOH_T = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 64:12]
  wire [2:0] dsizeOH = _dsizeOH_T[2:0]; // @[OneHot.scala 64:27]
  wire [4:0] _dsizeOH1_T_1 = 5'h3 << auto_out_d_bits_size; // @[package.scala 234:77]
  wire [1:0] dsizeOH1 = ~_dsizeOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  dHasData = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  _T_5 = ~reset; // @[Fragmenter.scala 202:16]
  wire  ack_decrement = dHasData | dsizeOH[2]; // @[Fragmenter.scala 204:32]
  wire [5:0] _dFirst_size_T = {dFragnum, 2'h0}; // @[Fragmenter.scala 206:47]
  wire [5:0] _GEN_7 = {{4'd0}, dsizeOH1}; // @[Fragmenter.scala 206:69]
  wire [5:0] _dFirst_size_T_1 = _dFirst_size_T | _GEN_7; // @[Fragmenter.scala 206:69]
  wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala 232:35]
  wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
  wire [6:0] _dFirst_size_T_4 = {1'h0,_dFirst_size_T_1}; // @[Cat.scala 31:58]
  wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
  wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
  wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
  wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
  wire [3:0] _GEN_8 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
  wire [3:0] _dFirst_size_T_8 = _GEN_8 | dFirst_size_lo; // @[OneHot.scala 32:28]
  wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
  wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
  wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
  wire  drop = ~dHasData & ~dLast; // @[Fragmenter.scala 222:30]
  wire  bundleOut_0_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  wire  _T_7 = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
  wire [3:0] _GEN_9 = {{3'd0}, ack_decrement}; // @[Fragmenter.scala 209:55]
  wire [3:0] _acknum_T_1 = acknum - _GEN_9; // @[Fragmenter.scala 209:55]
  wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h2 ? 3'h2 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
  wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
  wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
  wire [8:0] _aFragOH1_T_1 = 9'h3 << aFrag; // @[package.scala 234:77]
  wire [1:0] aFragOH1 = ~_aFragOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  aHasData = ~repeater_io_deq_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] gennum; // @[Fragmenter.scala 291:29]
  wire  aFirst = gennum == 4'h0; // @[Fragmenter.scala 292:29]
  wire [3:0] _old_gennum1_T_2 = gennum - 4'h1; // @[Fragmenter.scala 293:79]
  wire [3:0] old_gennum1 = aFirst ? aOrigOH1[5:2] : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
  wire [3:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
  wire [3:0] new_gennum = ~_new_gennum_T; // @[Fragmenter.scala 294:26]
  reg  aToggle_r; // @[Reg.scala 16:16]
  wire  _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
  wire  aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
  wire  bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  wire  _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
  wire  _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala 302:31]
  wire [5:0] _bundleOut_0_a_bits_address_T = {old_gennum1, 2'h0}; // @[Fragmenter.scala 304:65]
  wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
  wire [5:0] _bundleOut_0_a_bits_address_T_2 = _bundleOut_0_a_bits_address_T | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
  wire [5:0] _GEN_10 = {{4'd0}, aFragOH1}; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_10; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_4 = _bundleOut_0_a_bits_address_T_3 | 6'h3; // @[Fragmenter.scala 304:111]
  wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_4; // @[Fragmenter.scala 304:51]
  wire [28:0] _GEN_11 = {{23'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
  wire [2:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aToggle}; // @[Cat.scala 31:58]
  wire  _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
  TLMonitor_34 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_param(monitor_io_in_d_bits_param),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source),
    .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
    .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
    .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
  );
  Repeater repeater ( // @[Fragmenter.scala 262:30]
    .clock(repeater_clock),
    .reset(repeater_reset),
    .io_repeat(repeater_io_repeat),
    .io_full(repeater_io_full),
    .io_enq_ready(repeater_io_enq_ready),
    .io_enq_valid(repeater_io_enq_valid),
    .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
    .io_enq_bits_param(repeater_io_enq_bits_param),
    .io_enq_bits_size(repeater_io_enq_bits_size),
    .io_enq_bits_source(repeater_io_enq_bits_source),
    .io_enq_bits_address(repeater_io_enq_bits_address),
    .io_enq_bits_mask(repeater_io_enq_bits_mask),
    .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
    .io_deq_ready(repeater_io_deq_ready),
    .io_deq_valid(repeater_io_deq_valid),
    .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
    .io_deq_bits_param(repeater_io_deq_bits_param),
    .io_deq_bits_size(repeater_io_deq_bits_size),
    .io_deq_bits_source(repeater_io_deq_bits_source),
    .io_deq_bits_address(repeater_io_deq_bits_address),
    .io_deq_bits_mask(repeater_io_deq_bits_mask),
    .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
  );
  assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign auto_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign auto_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_size = aFrag[1:0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
  assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,new_gennum}; // @[Cat.scala 31:58]
  assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_11; // @[Fragmenter.scala 304:49]
  assign auto_out_a_bits_mask = repeater_io_full ? 4'hf : auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = repeater_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign monitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign repeater_clock = clock;
  assign repeater_reset = reset;
  assign repeater_io_repeat = ~aHasData & new_gennum != 4'h0; // @[Fragmenter.scala 302:41]
  assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  always @(posedge clock) begin
    if (reset) begin // @[Fragmenter.scala 189:29]
      acknum <= 4'h0; // @[Fragmenter.scala 189:29]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 209:24]
        acknum <= dFragnum;
      end else begin
        acknum <= _acknum_T_1;
      end
    end
    if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
      end
    end
    if (reset) begin // @[Fragmenter.scala 191:30]
      dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dToggle <= auto_out_d_bits_source[4]; // @[Fragmenter.scala 212:21]
      end
    end
    if (reset) begin // @[Fragmenter.scala 291:29]
      gennum <= 4'h0; // @[Fragmenter.scala 291:29]
    end else if (_T_8) begin // @[Fragmenter.scala 300:29]
      gennum <= new_gennum; // @[Fragmenter.scala 300:38]
    end
    if (aFirst) begin // @[Reg.scala 17:18]
      aToggle_r <= dToggle; // @[Reg.scala 17:22]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~repeater_io_full | _repeater_io_repeat_T) & _T_5) begin
          $fatal; // @[Fragmenter.scala 309:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(~repeater_io_full | _repeater_io_repeat_T)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Fragmenter.scala:309 assert (!repeater.io.full || !aHasData)\n"
            ); // @[Fragmenter.scala 309:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_9 | repeater_io_deq_bits_mask == 4'hf) & _T_5) begin
          $fatal; // @[Fragmenter.scala 312:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask == 4'hf)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
            ); // @[Fragmenter.scala 312:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  acknum = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  dOrig = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  dToggle = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  gennum = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  aToggle_r = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLInterconnectCoupler_24(
  input         clock,
  input         reset,
  output [2:0]  auto_asource_out_a_mem_0_opcode,
  output [2:0]  auto_asource_out_a_mem_0_param,
  output [1:0]  auto_asource_out_a_mem_0_size,
  output [6:0]  auto_asource_out_a_mem_0_source,
  output [28:0] auto_asource_out_a_mem_0_address,
  output [3:0]  auto_asource_out_a_mem_0_mask,
  output [31:0] auto_asource_out_a_mem_0_data,
  output        auto_asource_out_a_mem_0_corrupt,
  input         auto_asource_out_a_ridx,
  output        auto_asource_out_a_widx,
  input         auto_asource_out_a_safe_ridx_valid,
  output        auto_asource_out_a_safe_widx_valid,
  output        auto_asource_out_a_safe_source_reset_n,
  input         auto_asource_out_a_safe_sink_reset_n,
  input  [2:0]  auto_asource_out_d_mem_0_opcode,
  input  [1:0]  auto_asource_out_d_mem_0_param,
  input  [1:0]  auto_asource_out_d_mem_0_size,
  input  [6:0]  auto_asource_out_d_mem_0_source,
  input         auto_asource_out_d_mem_0_sink,
  input         auto_asource_out_d_mem_0_denied,
  input  [31:0] auto_asource_out_d_mem_0_data,
  input         auto_asource_out_d_mem_0_corrupt,
  output        auto_asource_out_d_ridx,
  input         auto_asource_out_d_widx,
  output        auto_asource_out_d_safe_ridx_valid,
  input         auto_asource_out_d_safe_widx_valid,
  input         auto_asource_out_d_safe_source_reset_n,
  output        auto_asource_out_d_safe_sink_reset_n,
  output        auto_tl_in_a_ready,
  input         auto_tl_in_a_valid,
  input  [2:0]  auto_tl_in_a_bits_opcode,
  input  [2:0]  auto_tl_in_a_bits_param,
  input  [2:0]  auto_tl_in_a_bits_size,
  input  [1:0]  auto_tl_in_a_bits_source,
  input  [28:0] auto_tl_in_a_bits_address,
  input  [3:0]  auto_tl_in_a_bits_mask,
  input  [31:0] auto_tl_in_a_bits_data,
  input         auto_tl_in_a_bits_corrupt,
  input         auto_tl_in_d_ready,
  output        auto_tl_in_d_valid,
  output [2:0]  auto_tl_in_d_bits_opcode,
  output [1:0]  auto_tl_in_d_bits_param,
  output [2:0]  auto_tl_in_d_bits_size,
  output [1:0]  auto_tl_in_d_bits_source,
  output        auto_tl_in_d_bits_sink,
  output        auto_tl_in_d_bits_denied,
  output [31:0] auto_tl_in_d_bits_data,
  output        auto_tl_in_d_bits_corrupt
);
  wire  asource_clock; // @[AsyncCrossing.scala 87:29]
  wire  asource_reset; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_in_a_ready; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_in_a_valid; // @[AsyncCrossing.scala 87:29]
  wire [2:0] asource_auto_in_a_bits_opcode; // @[AsyncCrossing.scala 87:29]
  wire [2:0] asource_auto_in_a_bits_param; // @[AsyncCrossing.scala 87:29]
  wire [1:0] asource_auto_in_a_bits_size; // @[AsyncCrossing.scala 87:29]
  wire [6:0] asource_auto_in_a_bits_source; // @[AsyncCrossing.scala 87:29]
  wire [28:0] asource_auto_in_a_bits_address; // @[AsyncCrossing.scala 87:29]
  wire [3:0] asource_auto_in_a_bits_mask; // @[AsyncCrossing.scala 87:29]
  wire [31:0] asource_auto_in_a_bits_data; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_in_a_bits_corrupt; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_in_d_ready; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_in_d_valid; // @[AsyncCrossing.scala 87:29]
  wire [2:0] asource_auto_in_d_bits_opcode; // @[AsyncCrossing.scala 87:29]
  wire [1:0] asource_auto_in_d_bits_param; // @[AsyncCrossing.scala 87:29]
  wire [1:0] asource_auto_in_d_bits_size; // @[AsyncCrossing.scala 87:29]
  wire [6:0] asource_auto_in_d_bits_source; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_in_d_bits_sink; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_in_d_bits_denied; // @[AsyncCrossing.scala 87:29]
  wire [31:0] asource_auto_in_d_bits_data; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_in_d_bits_corrupt; // @[AsyncCrossing.scala 87:29]
  wire [2:0] asource_auto_out_a_mem_0_opcode; // @[AsyncCrossing.scala 87:29]
  wire [2:0] asource_auto_out_a_mem_0_param; // @[AsyncCrossing.scala 87:29]
  wire [1:0] asource_auto_out_a_mem_0_size; // @[AsyncCrossing.scala 87:29]
  wire [6:0] asource_auto_out_a_mem_0_source; // @[AsyncCrossing.scala 87:29]
  wire [28:0] asource_auto_out_a_mem_0_address; // @[AsyncCrossing.scala 87:29]
  wire [3:0] asource_auto_out_a_mem_0_mask; // @[AsyncCrossing.scala 87:29]
  wire [31:0] asource_auto_out_a_mem_0_data; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_out_a_mem_0_corrupt; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_out_a_ridx; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_out_a_widx; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_out_a_safe_ridx_valid; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_out_a_safe_widx_valid; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_out_a_safe_source_reset_n; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_out_a_safe_sink_reset_n; // @[AsyncCrossing.scala 87:29]
  wire [2:0] asource_auto_out_d_mem_0_opcode; // @[AsyncCrossing.scala 87:29]
  wire [1:0] asource_auto_out_d_mem_0_param; // @[AsyncCrossing.scala 87:29]
  wire [1:0] asource_auto_out_d_mem_0_size; // @[AsyncCrossing.scala 87:29]
  wire [6:0] asource_auto_out_d_mem_0_source; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_out_d_mem_0_sink; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_out_d_mem_0_denied; // @[AsyncCrossing.scala 87:29]
  wire [31:0] asource_auto_out_d_mem_0_data; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_out_d_mem_0_corrupt; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_out_d_ridx; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_out_d_widx; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_out_d_safe_ridx_valid; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_out_d_safe_widx_valid; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_out_d_safe_source_reset_n; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_out_d_safe_sink_reset_n; // @[AsyncCrossing.scala 87:29]
  wire  fragmenter_clock; // @[Fragmenter.scala 333:34]
  wire  fragmenter_reset; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [28:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_d_bits_param; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_bits_sink; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_bits_denied; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [28:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_d_bits_param; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_bits_sink; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_bits_denied; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_bits_corrupt; // @[Fragmenter.scala 333:34]
  TLAsyncCrossingSource asource ( // @[AsyncCrossing.scala 87:29]
    .clock(asource_clock),
    .reset(asource_reset),
    .auto_in_a_ready(asource_auto_in_a_ready),
    .auto_in_a_valid(asource_auto_in_a_valid),
    .auto_in_a_bits_opcode(asource_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(asource_auto_in_a_bits_param),
    .auto_in_a_bits_size(asource_auto_in_a_bits_size),
    .auto_in_a_bits_source(asource_auto_in_a_bits_source),
    .auto_in_a_bits_address(asource_auto_in_a_bits_address),
    .auto_in_a_bits_mask(asource_auto_in_a_bits_mask),
    .auto_in_a_bits_data(asource_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(asource_auto_in_a_bits_corrupt),
    .auto_in_d_ready(asource_auto_in_d_ready),
    .auto_in_d_valid(asource_auto_in_d_valid),
    .auto_in_d_bits_opcode(asource_auto_in_d_bits_opcode),
    .auto_in_d_bits_param(asource_auto_in_d_bits_param),
    .auto_in_d_bits_size(asource_auto_in_d_bits_size),
    .auto_in_d_bits_source(asource_auto_in_d_bits_source),
    .auto_in_d_bits_sink(asource_auto_in_d_bits_sink),
    .auto_in_d_bits_denied(asource_auto_in_d_bits_denied),
    .auto_in_d_bits_data(asource_auto_in_d_bits_data),
    .auto_in_d_bits_corrupt(asource_auto_in_d_bits_corrupt),
    .auto_out_a_mem_0_opcode(asource_auto_out_a_mem_0_opcode),
    .auto_out_a_mem_0_param(asource_auto_out_a_mem_0_param),
    .auto_out_a_mem_0_size(asource_auto_out_a_mem_0_size),
    .auto_out_a_mem_0_source(asource_auto_out_a_mem_0_source),
    .auto_out_a_mem_0_address(asource_auto_out_a_mem_0_address),
    .auto_out_a_mem_0_mask(asource_auto_out_a_mem_0_mask),
    .auto_out_a_mem_0_data(asource_auto_out_a_mem_0_data),
    .auto_out_a_mem_0_corrupt(asource_auto_out_a_mem_0_corrupt),
    .auto_out_a_ridx(asource_auto_out_a_ridx),
    .auto_out_a_widx(asource_auto_out_a_widx),
    .auto_out_a_safe_ridx_valid(asource_auto_out_a_safe_ridx_valid),
    .auto_out_a_safe_widx_valid(asource_auto_out_a_safe_widx_valid),
    .auto_out_a_safe_source_reset_n(asource_auto_out_a_safe_source_reset_n),
    .auto_out_a_safe_sink_reset_n(asource_auto_out_a_safe_sink_reset_n),
    .auto_out_d_mem_0_opcode(asource_auto_out_d_mem_0_opcode),
    .auto_out_d_mem_0_param(asource_auto_out_d_mem_0_param),
    .auto_out_d_mem_0_size(asource_auto_out_d_mem_0_size),
    .auto_out_d_mem_0_source(asource_auto_out_d_mem_0_source),
    .auto_out_d_mem_0_sink(asource_auto_out_d_mem_0_sink),
    .auto_out_d_mem_0_denied(asource_auto_out_d_mem_0_denied),
    .auto_out_d_mem_0_data(asource_auto_out_d_mem_0_data),
    .auto_out_d_mem_0_corrupt(asource_auto_out_d_mem_0_corrupt),
    .auto_out_d_ridx(asource_auto_out_d_ridx),
    .auto_out_d_widx(asource_auto_out_d_widx),
    .auto_out_d_safe_ridx_valid(asource_auto_out_d_safe_ridx_valid),
    .auto_out_d_safe_widx_valid(asource_auto_out_d_safe_widx_valid),
    .auto_out_d_safe_source_reset_n(asource_auto_out_d_safe_source_reset_n),
    .auto_out_d_safe_sink_reset_n(asource_auto_out_d_safe_sink_reset_n)
  );
  TLFragmenter_18 fragmenter ( // @[Fragmenter.scala 333:34]
    .clock(fragmenter_clock),
    .reset(fragmenter_reset),
    .auto_in_a_ready(fragmenter_auto_in_a_ready),
    .auto_in_a_valid(fragmenter_auto_in_a_valid),
    .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
    .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
    .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
    .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
    .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
    .auto_in_a_bits_data(fragmenter_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
    .auto_in_d_ready(fragmenter_auto_in_d_ready),
    .auto_in_d_valid(fragmenter_auto_in_d_valid),
    .auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode),
    .auto_in_d_bits_param(fragmenter_auto_in_d_bits_param),
    .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
    .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
    .auto_in_d_bits_sink(fragmenter_auto_in_d_bits_sink),
    .auto_in_d_bits_denied(fragmenter_auto_in_d_bits_denied),
    .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
    .auto_in_d_bits_corrupt(fragmenter_auto_in_d_bits_corrupt),
    .auto_out_a_ready(fragmenter_auto_out_a_ready),
    .auto_out_a_valid(fragmenter_auto_out_a_valid),
    .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
    .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
    .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
    .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
    .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
    .auto_out_a_bits_data(fragmenter_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
    .auto_out_d_ready(fragmenter_auto_out_d_ready),
    .auto_out_d_valid(fragmenter_auto_out_d_valid),
    .auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode),
    .auto_out_d_bits_param(fragmenter_auto_out_d_bits_param),
    .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
    .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
    .auto_out_d_bits_sink(fragmenter_auto_out_d_bits_sink),
    .auto_out_d_bits_denied(fragmenter_auto_out_d_bits_denied),
    .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data),
    .auto_out_d_bits_corrupt(fragmenter_auto_out_d_bits_corrupt)
  );
  assign auto_asource_out_a_mem_0_opcode = asource_auto_out_a_mem_0_opcode; // @[LazyModule.scala 311:12]
  assign auto_asource_out_a_mem_0_param = asource_auto_out_a_mem_0_param; // @[LazyModule.scala 311:12]
  assign auto_asource_out_a_mem_0_size = asource_auto_out_a_mem_0_size; // @[LazyModule.scala 311:12]
  assign auto_asource_out_a_mem_0_source = asource_auto_out_a_mem_0_source; // @[LazyModule.scala 311:12]
  assign auto_asource_out_a_mem_0_address = asource_auto_out_a_mem_0_address; // @[LazyModule.scala 311:12]
  assign auto_asource_out_a_mem_0_mask = asource_auto_out_a_mem_0_mask; // @[LazyModule.scala 311:12]
  assign auto_asource_out_a_mem_0_data = asource_auto_out_a_mem_0_data; // @[LazyModule.scala 311:12]
  assign auto_asource_out_a_mem_0_corrupt = asource_auto_out_a_mem_0_corrupt; // @[LazyModule.scala 311:12]
  assign auto_asource_out_a_widx = asource_auto_out_a_widx; // @[LazyModule.scala 311:12]
  assign auto_asource_out_a_safe_widx_valid = asource_auto_out_a_safe_widx_valid; // @[LazyModule.scala 311:12]
  assign auto_asource_out_a_safe_source_reset_n = asource_auto_out_a_safe_source_reset_n; // @[LazyModule.scala 311:12]
  assign auto_asource_out_d_ridx = asource_auto_out_d_ridx; // @[LazyModule.scala 311:12]
  assign auto_asource_out_d_safe_ridx_valid = asource_auto_out_d_safe_ridx_valid; // @[LazyModule.scala 311:12]
  assign auto_asource_out_d_safe_sink_reset_n = asource_auto_out_d_safe_sink_reset_n; // @[LazyModule.scala 311:12]
  assign auto_tl_in_a_ready = fragmenter_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_valid = fragmenter_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_param = fragmenter_auto_in_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_size = fragmenter_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_source = fragmenter_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_sink = fragmenter_auto_in_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_denied = fragmenter_auto_in_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_data = fragmenter_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_corrupt = fragmenter_auto_in_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign asource_clock = clock;
  assign asource_reset = reset;
  assign asource_auto_in_a_valid = fragmenter_auto_out_a_valid; // @[LazyModule.scala 296:16]
  assign asource_auto_in_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign asource_auto_in_a_bits_param = fragmenter_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
  assign asource_auto_in_a_bits_size = fragmenter_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign asource_auto_in_a_bits_source = fragmenter_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign asource_auto_in_a_bits_address = fragmenter_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign asource_auto_in_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign asource_auto_in_a_bits_data = fragmenter_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign asource_auto_in_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
  assign asource_auto_in_d_ready = fragmenter_auto_out_d_ready; // @[LazyModule.scala 296:16]
  assign asource_auto_out_a_ridx = auto_asource_out_a_ridx; // @[LazyModule.scala 311:12]
  assign asource_auto_out_a_safe_ridx_valid = auto_asource_out_a_safe_ridx_valid; // @[LazyModule.scala 311:12]
  assign asource_auto_out_a_safe_sink_reset_n = auto_asource_out_a_safe_sink_reset_n; // @[LazyModule.scala 311:12]
  assign asource_auto_out_d_mem_0_opcode = auto_asource_out_d_mem_0_opcode; // @[LazyModule.scala 311:12]
  assign asource_auto_out_d_mem_0_param = auto_asource_out_d_mem_0_param; // @[LazyModule.scala 311:12]
  assign asource_auto_out_d_mem_0_size = auto_asource_out_d_mem_0_size; // @[LazyModule.scala 311:12]
  assign asource_auto_out_d_mem_0_source = auto_asource_out_d_mem_0_source; // @[LazyModule.scala 311:12]
  assign asource_auto_out_d_mem_0_sink = auto_asource_out_d_mem_0_sink; // @[LazyModule.scala 311:12]
  assign asource_auto_out_d_mem_0_denied = auto_asource_out_d_mem_0_denied; // @[LazyModule.scala 311:12]
  assign asource_auto_out_d_mem_0_data = auto_asource_out_d_mem_0_data; // @[LazyModule.scala 311:12]
  assign asource_auto_out_d_mem_0_corrupt = auto_asource_out_d_mem_0_corrupt; // @[LazyModule.scala 311:12]
  assign asource_auto_out_d_widx = auto_asource_out_d_widx; // @[LazyModule.scala 311:12]
  assign asource_auto_out_d_safe_widx_valid = auto_asource_out_d_safe_widx_valid; // @[LazyModule.scala 311:12]
  assign asource_auto_out_d_safe_source_reset_n = auto_asource_out_d_safe_source_reset_n; // @[LazyModule.scala 311:12]
  assign fragmenter_clock = clock;
  assign fragmenter_reset = reset;
  assign fragmenter_auto_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_data = auto_tl_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_out_a_ready = asource_auto_in_a_ready; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_out_d_valid = asource_auto_in_d_valid; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_out_d_bits_opcode = asource_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_out_d_bits_param = asource_auto_in_d_bits_param; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_out_d_bits_size = asource_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_out_d_bits_source = asource_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_out_d_bits_sink = asource_auto_in_d_bits_sink; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_out_d_bits_denied = asource_auto_in_d_bits_denied; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_out_d_bits_data = asource_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_out_d_bits_corrupt = asource_auto_in_d_bits_corrupt; // @[LazyModule.scala 296:16]
endmodule
module TLMonitor_35(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [16:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
  wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
  wire [16:0] _GEN_71 = {{11'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [16:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 17'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [16:0] _T_45 = io_in_a_bits_address ^ 17'h10000; // @[Parameters.scala 137:31]
  wire [17:0] _T_46 = {1'b0,$signed(_T_45)}; // @[Parameters.scala 137:49]
  wire [17:0] _T_48 = $signed(_T_46) & -18'sh10000; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 18'sh0; // @[Parameters.scala 137:67]
  wire  _T_59 = 3'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_60 = _source_ok_T & _T_59; // @[Mux.scala 27:73]
  wire  _T_76 = _T_60 & _T_49; // @[Monitor.scala 83:78]
  wire  _T_90 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_94 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_95 = _T_94 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_99 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_103 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_164 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_177 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_192 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
  wire  _T_200 = _T_192 & _T_49; // @[Parameters.scala 670:56]
  wire  _T_211 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_215 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_223 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_260 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_293 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_294 = io_in_a_bits_mask & _T_293; // @[Monitor.scala 127:31]
  wire  _T_295 = _T_294 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_299 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_328 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_336 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_365 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_373 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_402 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  reg [3:0] a_first_counter; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1 = a_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [16:0] address; // @[Monitor.scala 388:22]
  wire  _T_560 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_561 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_565 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_569 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_573 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_577 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
  wire [3:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:2]; // @[Edges.scala 219:59]
  reg [3:0] d_first_counter; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1 = d_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_584 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_593 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_597 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [11:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [3:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1_1 = a_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  reg [3:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_1 = d_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_73 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [11:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _GEN_76 = {{4'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_76 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_611 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_614 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [34:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [34:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_616 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_618 = ~_T_616[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [34:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_622 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [3:0] _GEN_22 = _d_first_T & d_first_1 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_23 = _d_first_T & d_first_1 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_611 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_635 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_637 = _T_635[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_642 = 3'h1 == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_643 = 3'h1 == _GEN_32 | _T_642; // @[Monitor.scala 685:77]
  wire  _T_647 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_654 = 3'h1 == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_655 = 3'h1 == _GEN_48 | _T_654; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_659 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_667 = _T_622 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2; // @[Monitor.scala 694:65]
  wire  _T_671 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set = _GEN_16[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_22[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_19[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_23[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [11:0] a_sizes_set = _GEN_20[11:0];
  wire [11:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [11:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_680 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 4'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= d_first_beats1_decode;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 12'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 4'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= d_first_beats1_decode;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (a_first_done | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_76 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_76) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_90 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_90) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_164 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_164) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_95 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_95) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_103 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_103 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_200 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_200) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_177 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_177 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_223 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_223 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_260 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_260 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_260 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_260 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_260 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_260 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_211 & (io_in_a_valid & _T_260 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_260 & ~reset & ~_T_211) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_295 & (io_in_a_valid & _T_260 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_260 & ~reset & ~_T_295) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_299 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_299 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_299 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_299 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_299 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_299 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_328 & (io_in_a_valid & _T_299 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_299 & ~reset & ~_T_328) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_299 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_299 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_336 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_336 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_336 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_336 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_336 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_336 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_365 & (io_in_a_valid & _T_336 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_336 & ~reset & ~_T_365) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_336 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_336 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_373 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_373 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_373 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_373 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_373 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_373 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_402 & (io_in_a_valid & _T_373 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_373 & ~reset & ~_T_402) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_215 & (io_in_a_valid & _T_373 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_373 & ~reset & ~_T_215) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_99 & (io_in_a_valid & _T_373 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_373 & ~reset & ~_T_99) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BootROM.scala:84:68)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_561 & (_T_560 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_560 & ~reset & ~_T_561) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_565 & (_T_560 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_560 & ~reset & ~_T_565) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_569 & (_T_560 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_560 & ~reset & ~_T_569) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_573 & (_T_560 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_560 & ~reset & ~_T_573) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_577 & (_T_560 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_560 & ~reset & ~_T_577) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_593 & (_T_584 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_584 & _T_2 & ~_T_593) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at BootROM.scala:84:68)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_597 & (_T_584 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_584 & _T_2 & ~_T_597) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at BootROM.scala:84:68)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_618 & (_T_614 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_614 & ~reset & ~_T_618) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_637 & (_T_622 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_622 & _T_2 & ~_T_637) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BootROM.scala:84:68)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_643 & (_T_622 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_622 & same_cycle_resp & _T_2 & ~_T_643) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at BootROM.scala:84:68)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_647 & (_T_622 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_622 & same_cycle_resp & _T_2 & ~_T_647) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at BootROM.scala:84:68)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_655 & (_T_622 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_622 & ~same_cycle_resp & _T_2 & ~_T_655) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at BootROM.scala:84:68)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_659 & (_T_622 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_622 & ~same_cycle_resp & _T_2 & ~_T_659) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at BootROM.scala:84:68)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_671 & (_T_667 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_667 & _T_2 & ~_T_671) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_680 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_680) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at BootROM.scala:84:68)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[16:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  size_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  source_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  inflight = _RAND_9[2:0];
  _RAND_10 = {1{`RANDOM}};
  inflight_opcodes = _RAND_10[11:0];
  _RAND_11 = {1{`RANDOM}};
  inflight_sizes = _RAND_11[11:0];
  _RAND_12 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_12[3:0];
  _RAND_13 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_13[3:0];
  _RAND_14 = {1{`RANDOM}};
  watchdog = _RAND_14[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Repeater_20(
  input         clock,
  input         reset,
  input         io_repeat,
  output        io_full,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [2:0]  io_enq_bits_opcode,
  input  [2:0]  io_enq_bits_param,
  input  [2:0]  io_enq_bits_size,
  input  [1:0]  io_enq_bits_source,
  input  [16:0] io_enq_bits_address,
  input  [3:0]  io_enq_bits_mask,
  input         io_enq_bits_corrupt,
  input         io_deq_ready,
  output        io_deq_valid,
  output [2:0]  io_deq_bits_opcode,
  output [2:0]  io_deq_bits_param,
  output [2:0]  io_deq_bits_size,
  output [1:0]  io_deq_bits_source,
  output [16:0] io_deq_bits_address,
  output [3:0]  io_deq_bits_mask,
  output        io_deq_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
`endif // RANDOMIZE_REG_INIT
  reg  full; // @[Repeater.scala 19:21]
  reg [2:0] saved_opcode; // @[Repeater.scala 20:18]
  reg [2:0] saved_param; // @[Repeater.scala 20:18]
  reg [2:0] saved_size; // @[Repeater.scala 20:18]
  reg [1:0] saved_source; // @[Repeater.scala 20:18]
  reg [16:0] saved_address; // @[Repeater.scala 20:18]
  reg [3:0] saved_mask; // @[Repeater.scala 20:18]
  reg  saved_corrupt; // @[Repeater.scala 20:18]
  wire  _T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
  wire  _GEN_0 = _T & io_repeat | full; // @[Repeater.scala 19:21 28:{38,45}]
  wire  _T_2 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
  assign io_full = full; // @[Repeater.scala 26:11]
  assign io_enq_ready = io_deq_ready & ~full; // @[Repeater.scala 24:32]
  assign io_deq_valid = io_enq_valid | full; // @[Repeater.scala 23:32]
  assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode; // @[Repeater.scala 25:21]
  assign io_deq_bits_param = full ? saved_param : io_enq_bits_param; // @[Repeater.scala 25:21]
  assign io_deq_bits_size = full ? saved_size : io_enq_bits_size; // @[Repeater.scala 25:21]
  assign io_deq_bits_source = full ? saved_source : io_enq_bits_source; // @[Repeater.scala 25:21]
  assign io_deq_bits_address = full ? saved_address : io_enq_bits_address; // @[Repeater.scala 25:21]
  assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask; // @[Repeater.scala 25:21]
  assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt; // @[Repeater.scala 25:21]
  always @(posedge clock) begin
    if (reset) begin // @[Repeater.scala 19:21]
      full <= 1'h0; // @[Repeater.scala 19:21]
    end else if (_T_2 & ~io_repeat) begin // @[Repeater.scala 29:38]
      full <= 1'h0; // @[Repeater.scala 29:45]
    end else begin
      full <= _GEN_0;
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_opcode <= io_enq_bits_opcode; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_param <= io_enq_bits_param; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_size <= io_enq_bits_size; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_source <= io_enq_bits_source; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_address <= io_enq_bits_address; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_mask <= io_enq_bits_mask; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_corrupt <= io_enq_bits_corrupt; // @[Repeater.scala 28:62]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  full = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  saved_opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  saved_param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  saved_size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  saved_source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  saved_address = _RAND_5[16:0];
  _RAND_6 = {1{`RANDOM}};
  saved_mask = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  saved_corrupt = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLFragmenter_19(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [16:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output [31:0] auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [1:0]  auto_out_a_bits_size,
  output [6:0]  auto_out_a_bits_source,
  output [16:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [1:0]  auto_out_d_bits_size,
  input  [6:0]  auto_out_d_bits_source,
  input  [31:0] auto_out_d_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [16:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  repeater_clock; // @[Fragmenter.scala 262:30]
  wire  repeater_reset; // @[Fragmenter.scala 262:30]
  wire  repeater_io_repeat; // @[Fragmenter.scala 262:30]
  wire  repeater_io_full; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
  wire [16:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
  wire [16:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
  reg [3:0] acknum; // @[Fragmenter.scala 189:29]
  reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
  reg  dToggle; // @[Fragmenter.scala 191:30]
  wire [3:0] dFragnum = auto_out_d_bits_source[3:0]; // @[Fragmenter.scala 192:41]
  wire  dFirst = acknum == 4'h0; // @[Fragmenter.scala 193:29]
  wire [4:0] _dsizeOH1_T_1 = 5'h3 << auto_out_d_bits_size; // @[package.scala 234:77]
  wire [1:0] dsizeOH1 = ~_dsizeOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  _T_5 = ~reset; // @[Fragmenter.scala 202:16]
  wire [5:0] _dFirst_size_T = {dFragnum, 2'h0}; // @[Fragmenter.scala 206:47]
  wire [5:0] _GEN_7 = {{4'd0}, dsizeOH1}; // @[Fragmenter.scala 206:69]
  wire [5:0] _dFirst_size_T_1 = _dFirst_size_T | _GEN_7; // @[Fragmenter.scala 206:69]
  wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala 232:35]
  wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
  wire [6:0] _dFirst_size_T_4 = {1'h0,_dFirst_size_T_1}; // @[Cat.scala 31:58]
  wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
  wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
  wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
  wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
  wire [3:0] _GEN_8 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
  wire [3:0] _dFirst_size_T_8 = _GEN_8 | dFirst_size_lo; // @[OneHot.scala 32:28]
  wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
  wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
  wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
  wire  _T_7 = auto_in_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
  wire [3:0] _acknum_T_1 = acknum - 4'h1; // @[Fragmenter.scala 209:55]
  wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h2 ? 3'h2 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
  wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
  wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
  wire [8:0] _aFragOH1_T_1 = 9'h3 << aFrag; // @[package.scala 234:77]
  wire [1:0] aFragOH1 = ~_aFragOH1_T_1[1:0]; // @[package.scala 234:46]
  reg [3:0] gennum; // @[Fragmenter.scala 291:29]
  wire  aFirst = gennum == 4'h0; // @[Fragmenter.scala 292:29]
  wire [3:0] _old_gennum1_T_2 = gennum - 4'h1; // @[Fragmenter.scala 293:79]
  wire [3:0] old_gennum1 = aFirst ? aOrigOH1[5:2] : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
  wire [3:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
  wire [3:0] new_gennum = ~_new_gennum_T; // @[Fragmenter.scala 294:26]
  reg  aToggle_r; // @[Reg.scala 16:16]
  wire  _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
  wire  aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
  wire  bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  wire  _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
  wire [5:0] _bundleOut_0_a_bits_address_T = {old_gennum1, 2'h0}; // @[Fragmenter.scala 304:65]
  wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
  wire [5:0] _bundleOut_0_a_bits_address_T_2 = _bundleOut_0_a_bits_address_T | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
  wire [5:0] _GEN_9 = {{4'd0}, aFragOH1}; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_9; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_4 = _bundleOut_0_a_bits_address_T_3 | 6'h3; // @[Fragmenter.scala 304:111]
  wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_4; // @[Fragmenter.scala 304:51]
  wire [16:0] _GEN_10 = {{11'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
  wire [2:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aToggle}; // @[Cat.scala 31:58]
  wire  _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
  TLMonitor_35 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  Repeater_20 repeater ( // @[Fragmenter.scala 262:30]
    .clock(repeater_clock),
    .reset(repeater_reset),
    .io_repeat(repeater_io_repeat),
    .io_full(repeater_io_full),
    .io_enq_ready(repeater_io_enq_ready),
    .io_enq_valid(repeater_io_enq_valid),
    .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
    .io_enq_bits_param(repeater_io_enq_bits_param),
    .io_enq_bits_size(repeater_io_enq_bits_size),
    .io_enq_bits_source(repeater_io_enq_bits_source),
    .io_enq_bits_address(repeater_io_enq_bits_address),
    .io_enq_bits_mask(repeater_io_enq_bits_mask),
    .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
    .io_deq_ready(repeater_io_deq_ready),
    .io_deq_valid(repeater_io_deq_valid),
    .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
    .io_deq_bits_param(repeater_io_deq_bits_param),
    .io_deq_bits_size(repeater_io_deq_bits_size),
    .io_deq_bits_source(repeater_io_deq_bits_source),
    .io_deq_bits_address(repeater_io_deq_bits_address),
    .io_deq_bits_mask(repeater_io_deq_bits_mask),
    .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
  );
  assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign auto_in_d_valid = auto_out_d_valid; // @[Fragmenter.scala 224:36]
  assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign auto_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_size = aFrag[1:0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
  assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,new_gennum}; // @[Cat.scala 31:58]
  assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_10; // @[Fragmenter.scala 304:49]
  assign auto_out_a_bits_mask = repeater_io_full ? 4'hf : auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
  assign auto_out_a_bits_corrupt = repeater_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_d_ready = auto_in_d_ready; // @[Fragmenter.scala 223:35]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid; // @[Fragmenter.scala 224:36]
  assign monitor_io_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source[6:5]; // @[Fragmenter.scala 226:47]
  assign repeater_clock = clock;
  assign repeater_reset = reset;
  assign repeater_io_repeat = new_gennum != 4'h0; // @[Fragmenter.scala 302:53]
  assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  always @(posedge clock) begin
    if (reset) begin // @[Fragmenter.scala 189:29]
      acknum <= 4'h0; // @[Fragmenter.scala 189:29]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 209:24]
        acknum <= dFragnum;
      end else begin
        acknum <= _acknum_T_1;
      end
    end
    if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
      end
    end
    if (reset) begin // @[Fragmenter.scala 191:30]
      dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dToggle <= auto_out_d_bits_source[4]; // @[Fragmenter.scala 212:21]
      end
    end
    if (reset) begin // @[Fragmenter.scala 291:29]
      gennum <= 4'h0; // @[Fragmenter.scala 291:29]
    end else if (_T_8) begin // @[Fragmenter.scala 300:29]
      gennum <= new_gennum; // @[Fragmenter.scala 300:38]
    end
    if (aFirst) begin // @[Reg.scala 17:18]
      aToggle_r <= dToggle; // @[Reg.scala 17:22]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_9 | repeater_io_deq_bits_mask == 4'hf) & _T_5) begin
          $fatal; // @[Fragmenter.scala 312:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask == 4'hf)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
            ); // @[Fragmenter.scala 312:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  acknum = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  dOrig = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  dToggle = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  gennum = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  aToggle_r = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLInterconnectCoupler_25(
  input         clock,
  input         reset,
  input         auto_fragmenter_out_a_ready,
  output        auto_fragmenter_out_a_valid,
  output [2:0]  auto_fragmenter_out_a_bits_opcode,
  output [2:0]  auto_fragmenter_out_a_bits_param,
  output [1:0]  auto_fragmenter_out_a_bits_size,
  output [6:0]  auto_fragmenter_out_a_bits_source,
  output [16:0] auto_fragmenter_out_a_bits_address,
  output [3:0]  auto_fragmenter_out_a_bits_mask,
  output        auto_fragmenter_out_a_bits_corrupt,
  output        auto_fragmenter_out_d_ready,
  input         auto_fragmenter_out_d_valid,
  input  [1:0]  auto_fragmenter_out_d_bits_size,
  input  [6:0]  auto_fragmenter_out_d_bits_source,
  input  [31:0] auto_fragmenter_out_d_bits_data,
  output        auto_tl_in_a_ready,
  input         auto_tl_in_a_valid,
  input  [2:0]  auto_tl_in_a_bits_opcode,
  input  [2:0]  auto_tl_in_a_bits_param,
  input  [2:0]  auto_tl_in_a_bits_size,
  input  [1:0]  auto_tl_in_a_bits_source,
  input  [16:0] auto_tl_in_a_bits_address,
  input  [3:0]  auto_tl_in_a_bits_mask,
  input         auto_tl_in_a_bits_corrupt,
  input         auto_tl_in_d_ready,
  output        auto_tl_in_d_valid,
  output [2:0]  auto_tl_in_d_bits_size,
  output [1:0]  auto_tl_in_d_bits_source,
  output [31:0] auto_tl_in_d_bits_data
);
  wire  fragmenter_clock; // @[Fragmenter.scala 333:34]
  wire  fragmenter_reset; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [16:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [16:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [6:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
  TLFragmenter_19 fragmenter ( // @[Fragmenter.scala 333:34]
    .clock(fragmenter_clock),
    .reset(fragmenter_reset),
    .auto_in_a_ready(fragmenter_auto_in_a_ready),
    .auto_in_a_valid(fragmenter_auto_in_a_valid),
    .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
    .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
    .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
    .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
    .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
    .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
    .auto_in_d_ready(fragmenter_auto_in_d_ready),
    .auto_in_d_valid(fragmenter_auto_in_d_valid),
    .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
    .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
    .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
    .auto_out_a_ready(fragmenter_auto_out_a_ready),
    .auto_out_a_valid(fragmenter_auto_out_a_valid),
    .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
    .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
    .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
    .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
    .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
    .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
    .auto_out_d_ready(fragmenter_auto_out_d_ready),
    .auto_out_d_valid(fragmenter_auto_out_d_valid),
    .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
    .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
    .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
  );
  assign auto_fragmenter_out_a_valid = fragmenter_auto_out_a_valid; // @[LazyModule.scala 311:12]
  assign auto_fragmenter_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[LazyModule.scala 311:12]
  assign auto_fragmenter_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[LazyModule.scala 311:12]
  assign auto_fragmenter_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[LazyModule.scala 311:12]
  assign auto_fragmenter_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[LazyModule.scala 311:12]
  assign auto_fragmenter_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[LazyModule.scala 311:12]
  assign auto_fragmenter_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[LazyModule.scala 311:12]
  assign auto_fragmenter_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
  assign auto_fragmenter_out_d_ready = fragmenter_auto_out_d_ready; // @[LazyModule.scala 311:12]
  assign auto_tl_in_a_ready = fragmenter_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_valid = fragmenter_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_size = fragmenter_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_source = fragmenter_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_data = fragmenter_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign fragmenter_clock = clock;
  assign fragmenter_reset = reset;
  assign fragmenter_auto_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign fragmenter_auto_out_a_ready = auto_fragmenter_out_a_ready; // @[LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_valid = auto_fragmenter_out_d_valid; // @[LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_size = auto_fragmenter_out_d_bits_size; // @[LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_source = auto_fragmenter_out_d_bits_source; // @[LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_data = auto_fragmenter_out_d_bits_data; // @[LazyModule.scala 311:12]
endmodule
module PeripheryBus_1(
  input         auto_coupler_to_bootrom_fragmenter_out_a_ready,
  output        auto_coupler_to_bootrom_fragmenter_out_a_valid,
  output [2:0]  auto_coupler_to_bootrom_fragmenter_out_a_bits_opcode,
  output [2:0]  auto_coupler_to_bootrom_fragmenter_out_a_bits_param,
  output [1:0]  auto_coupler_to_bootrom_fragmenter_out_a_bits_size,
  output [6:0]  auto_coupler_to_bootrom_fragmenter_out_a_bits_source,
  output [16:0] auto_coupler_to_bootrom_fragmenter_out_a_bits_address,
  output [3:0]  auto_coupler_to_bootrom_fragmenter_out_a_bits_mask,
  output        auto_coupler_to_bootrom_fragmenter_out_a_bits_corrupt,
  output        auto_coupler_to_bootrom_fragmenter_out_d_ready,
  input         auto_coupler_to_bootrom_fragmenter_out_d_valid,
  input  [1:0]  auto_coupler_to_bootrom_fragmenter_out_d_bits_size,
  input  [6:0]  auto_coupler_to_bootrom_fragmenter_out_d_bits_source,
  input  [31:0] auto_coupler_to_bootrom_fragmenter_out_d_bits_data,
  output [2:0]  auto_coupler_to_aon_asource_out_a_mem_0_opcode,
  output [2:0]  auto_coupler_to_aon_asource_out_a_mem_0_param,
  output [1:0]  auto_coupler_to_aon_asource_out_a_mem_0_size,
  output [6:0]  auto_coupler_to_aon_asource_out_a_mem_0_source,
  output [28:0] auto_coupler_to_aon_asource_out_a_mem_0_address,
  output [3:0]  auto_coupler_to_aon_asource_out_a_mem_0_mask,
  output [31:0] auto_coupler_to_aon_asource_out_a_mem_0_data,
  output        auto_coupler_to_aon_asource_out_a_mem_0_corrupt,
  input         auto_coupler_to_aon_asource_out_a_ridx,
  output        auto_coupler_to_aon_asource_out_a_widx,
  input         auto_coupler_to_aon_asource_out_a_safe_ridx_valid,
  output        auto_coupler_to_aon_asource_out_a_safe_widx_valid,
  output        auto_coupler_to_aon_asource_out_a_safe_source_reset_n,
  input         auto_coupler_to_aon_asource_out_a_safe_sink_reset_n,
  input  [2:0]  auto_coupler_to_aon_asource_out_d_mem_0_opcode,
  input  [1:0]  auto_coupler_to_aon_asource_out_d_mem_0_param,
  input  [1:0]  auto_coupler_to_aon_asource_out_d_mem_0_size,
  input  [6:0]  auto_coupler_to_aon_asource_out_d_mem_0_source,
  input         auto_coupler_to_aon_asource_out_d_mem_0_sink,
  input         auto_coupler_to_aon_asource_out_d_mem_0_denied,
  input  [31:0] auto_coupler_to_aon_asource_out_d_mem_0_data,
  input         auto_coupler_to_aon_asource_out_d_mem_0_corrupt,
  output        auto_coupler_to_aon_asource_out_d_ridx,
  input         auto_coupler_to_aon_asource_out_d_widx,
  output        auto_coupler_to_aon_asource_out_d_safe_ridx_valid,
  input         auto_coupler_to_aon_asource_out_d_safe_widx_valid,
  input         auto_coupler_to_aon_asource_out_d_safe_source_reset_n,
  output        auto_coupler_to_aon_asource_out_d_safe_sink_reset_n,
  input         auto_coupler_to_tile_tl_slave_clock_xing_out_a_ready,
  output        auto_coupler_to_tile_tl_slave_clock_xing_out_a_valid,
  output [2:0]  auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_opcode,
  output [2:0]  auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_param,
  output [2:0]  auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_size,
  output [1:0]  auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_source,
  output [27:0] auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_address,
  output [3:0]  auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_mask,
  output [31:0] auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_data,
  output        auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_corrupt,
  output        auto_coupler_to_tile_tl_slave_clock_xing_out_d_ready,
  input         auto_coupler_to_tile_tl_slave_clock_xing_out_d_valid,
  input  [2:0]  auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_opcode,
  input  [1:0]  auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_param,
  input  [2:0]  auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_size,
  input  [1:0]  auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_source,
  input         auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_sink,
  input         auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_denied,
  input  [31:0] auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_data,
  input         auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_corrupt,
  input         auto_coupler_to_debug_fragmenter_out_a_ready,
  output        auto_coupler_to_debug_fragmenter_out_a_valid,
  output [2:0]  auto_coupler_to_debug_fragmenter_out_a_bits_opcode,
  output [2:0]  auto_coupler_to_debug_fragmenter_out_a_bits_param,
  output [1:0]  auto_coupler_to_debug_fragmenter_out_a_bits_size,
  output [6:0]  auto_coupler_to_debug_fragmenter_out_a_bits_source,
  output [11:0] auto_coupler_to_debug_fragmenter_out_a_bits_address,
  output [3:0]  auto_coupler_to_debug_fragmenter_out_a_bits_mask,
  output [31:0] auto_coupler_to_debug_fragmenter_out_a_bits_data,
  output        auto_coupler_to_debug_fragmenter_out_a_bits_corrupt,
  output        auto_coupler_to_debug_fragmenter_out_d_ready,
  input         auto_coupler_to_debug_fragmenter_out_d_valid,
  input  [2:0]  auto_coupler_to_debug_fragmenter_out_d_bits_opcode,
  input  [1:0]  auto_coupler_to_debug_fragmenter_out_d_bits_size,
  input  [6:0]  auto_coupler_to_debug_fragmenter_out_d_bits_source,
  input  [31:0] auto_coupler_to_debug_fragmenter_out_d_bits_data,
  input         auto_coupler_to_clint_fragmenter_out_a_ready,
  output        auto_coupler_to_clint_fragmenter_out_a_valid,
  output [2:0]  auto_coupler_to_clint_fragmenter_out_a_bits_opcode,
  output [2:0]  auto_coupler_to_clint_fragmenter_out_a_bits_param,
  output [1:0]  auto_coupler_to_clint_fragmenter_out_a_bits_size,
  output [6:0]  auto_coupler_to_clint_fragmenter_out_a_bits_source,
  output [25:0] auto_coupler_to_clint_fragmenter_out_a_bits_address,
  output [3:0]  auto_coupler_to_clint_fragmenter_out_a_bits_mask,
  output [31:0] auto_coupler_to_clint_fragmenter_out_a_bits_data,
  output        auto_coupler_to_clint_fragmenter_out_a_bits_corrupt,
  output        auto_coupler_to_clint_fragmenter_out_d_ready,
  input         auto_coupler_to_clint_fragmenter_out_d_valid,
  input  [2:0]  auto_coupler_to_clint_fragmenter_out_d_bits_opcode,
  input  [1:0]  auto_coupler_to_clint_fragmenter_out_d_bits_size,
  input  [6:0]  auto_coupler_to_clint_fragmenter_out_d_bits_source,
  input  [31:0] auto_coupler_to_clint_fragmenter_out_d_bits_data,
  input         auto_coupler_to_plic_fragmenter_out_a_ready,
  output        auto_coupler_to_plic_fragmenter_out_a_valid,
  output [2:0]  auto_coupler_to_plic_fragmenter_out_a_bits_opcode,
  output [2:0]  auto_coupler_to_plic_fragmenter_out_a_bits_param,
  output [1:0]  auto_coupler_to_plic_fragmenter_out_a_bits_size,
  output [6:0]  auto_coupler_to_plic_fragmenter_out_a_bits_source,
  output [27:0] auto_coupler_to_plic_fragmenter_out_a_bits_address,
  output [3:0]  auto_coupler_to_plic_fragmenter_out_a_bits_mask,
  output [31:0] auto_coupler_to_plic_fragmenter_out_a_bits_data,
  output        auto_coupler_to_plic_fragmenter_out_a_bits_corrupt,
  output        auto_coupler_to_plic_fragmenter_out_d_ready,
  input         auto_coupler_to_plic_fragmenter_out_d_valid,
  input  [2:0]  auto_coupler_to_plic_fragmenter_out_d_bits_opcode,
  input  [1:0]  auto_coupler_to_plic_fragmenter_out_d_bits_size,
  input  [6:0]  auto_coupler_to_plic_fragmenter_out_d_bits_source,
  input  [31:0] auto_coupler_to_plic_fragmenter_out_d_bits_data,
  input         auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_ready,
  output        auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_valid,
  output [2:0]  auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_opcode,
  output [2:0]  auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_param,
  output [2:0]  auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_size,
  output [1:0]  auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_source,
  output [29:0] auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_address,
  output [3:0]  auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_mask,
  output [31:0] auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_data,
  output        auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_corrupt,
  output        auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_ready,
  input         auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_valid,
  input  [2:0]  auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_opcode,
  input  [1:0]  auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_param,
  input  [2:0]  auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_size,
  input  [1:0]  auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_source,
  input         auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_sink,
  input         auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_denied,
  input  [31:0] auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_data,
  input         auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_corrupt,
  output        auto_fixedClockNode_out_2_clock,
  output        auto_fixedClockNode_out_2_reset,
  output        auto_fixedClockNode_out_0_clock,
  output        auto_fixedClockNode_out_0_reset,
  input         auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_1_clock,
  input         auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_1_reset,
  input         auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_0_clock,
  input         auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_0_reset,
  output        auto_subsystem_cbus_clock_groups_out_member_subsystem_pbus_0_clock,
  output        auto_subsystem_cbus_clock_groups_out_member_subsystem_pbus_0_reset,
  output        auto_bus_xing_in_a_ready,
  input         auto_bus_xing_in_a_valid,
  input  [2:0]  auto_bus_xing_in_a_bits_opcode,
  input  [2:0]  auto_bus_xing_in_a_bits_param,
  input  [3:0]  auto_bus_xing_in_a_bits_size,
  input  [1:0]  auto_bus_xing_in_a_bits_source,
  input  [29:0] auto_bus_xing_in_a_bits_address,
  input  [3:0]  auto_bus_xing_in_a_bits_mask,
  input  [31:0] auto_bus_xing_in_a_bits_data,
  input         auto_bus_xing_in_a_bits_corrupt,
  input         auto_bus_xing_in_d_ready,
  output        auto_bus_xing_in_d_valid,
  output [2:0]  auto_bus_xing_in_d_bits_opcode,
  output [1:0]  auto_bus_xing_in_d_bits_param,
  output [3:0]  auto_bus_xing_in_d_bits_size,
  output [1:0]  auto_bus_xing_in_d_bits_source,
  output        auto_bus_xing_in_d_bits_sink,
  output        auto_bus_xing_in_d_bits_denied,
  output [31:0] auto_bus_xing_in_d_bits_data,
  output        auto_bus_xing_in_d_bits_corrupt,
  output        clock,
  output        reset
);
  wire  subsystem_cbus_clock_groups_auto_in_member_subsystem_cbus_1_clock; // @[BusWrapper.scala 40:48]
  wire  subsystem_cbus_clock_groups_auto_in_member_subsystem_cbus_1_reset; // @[BusWrapper.scala 40:48]
  wire  subsystem_cbus_clock_groups_auto_in_member_subsystem_cbus_0_clock; // @[BusWrapper.scala 40:48]
  wire  subsystem_cbus_clock_groups_auto_in_member_subsystem_cbus_0_reset; // @[BusWrapper.scala 40:48]
  wire  subsystem_cbus_clock_groups_auto_out_1_member_subsystem_pbus_0_clock; // @[BusWrapper.scala 40:48]
  wire  subsystem_cbus_clock_groups_auto_out_1_member_subsystem_pbus_0_reset; // @[BusWrapper.scala 40:48]
  wire  subsystem_cbus_clock_groups_auto_out_0_member_subsystem_cbus_0_clock; // @[BusWrapper.scala 40:48]
  wire  subsystem_cbus_clock_groups_auto_out_0_member_subsystem_cbus_0_reset; // @[BusWrapper.scala 40:48]
  wire  clockGroup_auto_in_member_subsystem_cbus_0_clock; // @[BusWrapper.scala 41:38]
  wire  clockGroup_auto_in_member_subsystem_cbus_0_reset; // @[BusWrapper.scala 41:38]
  wire  clockGroup_auto_out_clock; // @[BusWrapper.scala 41:38]
  wire  clockGroup_auto_out_reset; // @[BusWrapper.scala 41:38]
  wire  fixedClockNode_auto_in_clock; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_in_reset; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_3_clock; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_3_reset; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_1_clock; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_1_reset; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_0_clock; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_0_reset; // @[ClockGroup.scala 106:107]
  wire  fixer_clock; // @[PeripheryBus.scala 47:33]
  wire  fixer_reset; // @[PeripheryBus.scala 47:33]
  wire  fixer_auto_in_a_ready; // @[PeripheryBus.scala 47:33]
  wire  fixer_auto_in_a_valid; // @[PeripheryBus.scala 47:33]
  wire [2:0] fixer_auto_in_a_bits_opcode; // @[PeripheryBus.scala 47:33]
  wire [2:0] fixer_auto_in_a_bits_param; // @[PeripheryBus.scala 47:33]
  wire [3:0] fixer_auto_in_a_bits_size; // @[PeripheryBus.scala 47:33]
  wire [1:0] fixer_auto_in_a_bits_source; // @[PeripheryBus.scala 47:33]
  wire [29:0] fixer_auto_in_a_bits_address; // @[PeripheryBus.scala 47:33]
  wire [3:0] fixer_auto_in_a_bits_mask; // @[PeripheryBus.scala 47:33]
  wire [31:0] fixer_auto_in_a_bits_data; // @[PeripheryBus.scala 47:33]
  wire  fixer_auto_in_a_bits_corrupt; // @[PeripheryBus.scala 47:33]
  wire  fixer_auto_in_d_ready; // @[PeripheryBus.scala 47:33]
  wire  fixer_auto_in_d_valid; // @[PeripheryBus.scala 47:33]
  wire [2:0] fixer_auto_in_d_bits_opcode; // @[PeripheryBus.scala 47:33]
  wire [1:0] fixer_auto_in_d_bits_param; // @[PeripheryBus.scala 47:33]
  wire [3:0] fixer_auto_in_d_bits_size; // @[PeripheryBus.scala 47:33]
  wire [1:0] fixer_auto_in_d_bits_source; // @[PeripheryBus.scala 47:33]
  wire  fixer_auto_in_d_bits_sink; // @[PeripheryBus.scala 47:33]
  wire  fixer_auto_in_d_bits_denied; // @[PeripheryBus.scala 47:33]
  wire [31:0] fixer_auto_in_d_bits_data; // @[PeripheryBus.scala 47:33]
  wire  fixer_auto_in_d_bits_corrupt; // @[PeripheryBus.scala 47:33]
  wire  fixer_auto_out_a_ready; // @[PeripheryBus.scala 47:33]
  wire  fixer_auto_out_a_valid; // @[PeripheryBus.scala 47:33]
  wire [2:0] fixer_auto_out_a_bits_opcode; // @[PeripheryBus.scala 47:33]
  wire [2:0] fixer_auto_out_a_bits_param; // @[PeripheryBus.scala 47:33]
  wire [3:0] fixer_auto_out_a_bits_size; // @[PeripheryBus.scala 47:33]
  wire [1:0] fixer_auto_out_a_bits_source; // @[PeripheryBus.scala 47:33]
  wire [29:0] fixer_auto_out_a_bits_address; // @[PeripheryBus.scala 47:33]
  wire [3:0] fixer_auto_out_a_bits_mask; // @[PeripheryBus.scala 47:33]
  wire [31:0] fixer_auto_out_a_bits_data; // @[PeripheryBus.scala 47:33]
  wire  fixer_auto_out_a_bits_corrupt; // @[PeripheryBus.scala 47:33]
  wire  fixer_auto_out_d_ready; // @[PeripheryBus.scala 47:33]
  wire  fixer_auto_out_d_valid; // @[PeripheryBus.scala 47:33]
  wire [2:0] fixer_auto_out_d_bits_opcode; // @[PeripheryBus.scala 47:33]
  wire [1:0] fixer_auto_out_d_bits_param; // @[PeripheryBus.scala 47:33]
  wire [3:0] fixer_auto_out_d_bits_size; // @[PeripheryBus.scala 47:33]
  wire [1:0] fixer_auto_out_d_bits_source; // @[PeripheryBus.scala 47:33]
  wire  fixer_auto_out_d_bits_sink; // @[PeripheryBus.scala 47:33]
  wire  fixer_auto_out_d_bits_denied; // @[PeripheryBus.scala 47:33]
  wire [31:0] fixer_auto_out_d_bits_data; // @[PeripheryBus.scala 47:33]
  wire  fixer_auto_out_d_bits_corrupt; // @[PeripheryBus.scala 47:33]
  wire  in_xbar_auto_in_a_ready; // @[PeripheryBus.scala 49:29]
  wire  in_xbar_auto_in_a_valid; // @[PeripheryBus.scala 49:29]
  wire [2:0] in_xbar_auto_in_a_bits_opcode; // @[PeripheryBus.scala 49:29]
  wire [2:0] in_xbar_auto_in_a_bits_param; // @[PeripheryBus.scala 49:29]
  wire [3:0] in_xbar_auto_in_a_bits_size; // @[PeripheryBus.scala 49:29]
  wire [1:0] in_xbar_auto_in_a_bits_source; // @[PeripheryBus.scala 49:29]
  wire [29:0] in_xbar_auto_in_a_bits_address; // @[PeripheryBus.scala 49:29]
  wire [3:0] in_xbar_auto_in_a_bits_mask; // @[PeripheryBus.scala 49:29]
  wire [31:0] in_xbar_auto_in_a_bits_data; // @[PeripheryBus.scala 49:29]
  wire  in_xbar_auto_in_a_bits_corrupt; // @[PeripheryBus.scala 49:29]
  wire  in_xbar_auto_in_d_ready; // @[PeripheryBus.scala 49:29]
  wire  in_xbar_auto_in_d_valid; // @[PeripheryBus.scala 49:29]
  wire [2:0] in_xbar_auto_in_d_bits_opcode; // @[PeripheryBus.scala 49:29]
  wire [1:0] in_xbar_auto_in_d_bits_param; // @[PeripheryBus.scala 49:29]
  wire [3:0] in_xbar_auto_in_d_bits_size; // @[PeripheryBus.scala 49:29]
  wire [1:0] in_xbar_auto_in_d_bits_source; // @[PeripheryBus.scala 49:29]
  wire  in_xbar_auto_in_d_bits_sink; // @[PeripheryBus.scala 49:29]
  wire  in_xbar_auto_in_d_bits_denied; // @[PeripheryBus.scala 49:29]
  wire [31:0] in_xbar_auto_in_d_bits_data; // @[PeripheryBus.scala 49:29]
  wire  in_xbar_auto_in_d_bits_corrupt; // @[PeripheryBus.scala 49:29]
  wire  in_xbar_auto_out_a_ready; // @[PeripheryBus.scala 49:29]
  wire  in_xbar_auto_out_a_valid; // @[PeripheryBus.scala 49:29]
  wire [2:0] in_xbar_auto_out_a_bits_opcode; // @[PeripheryBus.scala 49:29]
  wire [2:0] in_xbar_auto_out_a_bits_param; // @[PeripheryBus.scala 49:29]
  wire [3:0] in_xbar_auto_out_a_bits_size; // @[PeripheryBus.scala 49:29]
  wire [1:0] in_xbar_auto_out_a_bits_source; // @[PeripheryBus.scala 49:29]
  wire [29:0] in_xbar_auto_out_a_bits_address; // @[PeripheryBus.scala 49:29]
  wire [3:0] in_xbar_auto_out_a_bits_mask; // @[PeripheryBus.scala 49:29]
  wire [31:0] in_xbar_auto_out_a_bits_data; // @[PeripheryBus.scala 49:29]
  wire  in_xbar_auto_out_a_bits_corrupt; // @[PeripheryBus.scala 49:29]
  wire  in_xbar_auto_out_d_ready; // @[PeripheryBus.scala 49:29]
  wire  in_xbar_auto_out_d_valid; // @[PeripheryBus.scala 49:29]
  wire [2:0] in_xbar_auto_out_d_bits_opcode; // @[PeripheryBus.scala 49:29]
  wire [1:0] in_xbar_auto_out_d_bits_param; // @[PeripheryBus.scala 49:29]
  wire [3:0] in_xbar_auto_out_d_bits_size; // @[PeripheryBus.scala 49:29]
  wire [1:0] in_xbar_auto_out_d_bits_source; // @[PeripheryBus.scala 49:29]
  wire  in_xbar_auto_out_d_bits_sink; // @[PeripheryBus.scala 49:29]
  wire  in_xbar_auto_out_d_bits_denied; // @[PeripheryBus.scala 49:29]
  wire [31:0] in_xbar_auto_out_d_bits_data; // @[PeripheryBus.scala 49:29]
  wire  in_xbar_auto_out_d_bits_corrupt; // @[PeripheryBus.scala 49:29]
  wire  out_xbar_clock; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_reset; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_in_a_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_in_a_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_in_a_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_in_a_bits_param; // @[PeripheryBus.scala 50:30]
  wire [3:0] out_xbar_auto_in_a_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_in_a_bits_source; // @[PeripheryBus.scala 50:30]
  wire [29:0] out_xbar_auto_in_a_bits_address; // @[PeripheryBus.scala 50:30]
  wire [3:0] out_xbar_auto_in_a_bits_mask; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_in_a_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_in_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_in_d_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_in_d_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_in_d_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_in_d_bits_param; // @[PeripheryBus.scala 50:30]
  wire [3:0] out_xbar_auto_in_d_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_in_d_bits_source; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_in_d_bits_sink; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_in_d_bits_denied; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_in_d_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_in_d_bits_corrupt; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_7_a_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_7_a_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_7_a_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_7_a_bits_param; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_7_a_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_7_a_bits_source; // @[PeripheryBus.scala 50:30]
  wire [16:0] out_xbar_auto_out_7_a_bits_address; // @[PeripheryBus.scala 50:30]
  wire [3:0] out_xbar_auto_out_7_a_bits_mask; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_7_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_7_d_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_7_d_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_7_d_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_7_d_bits_source; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_7_d_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_6_a_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_6_a_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_6_a_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_6_a_bits_param; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_6_a_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_6_a_bits_source; // @[PeripheryBus.scala 50:30]
  wire [28:0] out_xbar_auto_out_6_a_bits_address; // @[PeripheryBus.scala 50:30]
  wire [3:0] out_xbar_auto_out_6_a_bits_mask; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_6_a_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_6_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_6_d_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_6_d_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_6_d_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_6_d_bits_param; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_6_d_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_6_d_bits_source; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_6_d_bits_sink; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_6_d_bits_denied; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_6_d_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_6_d_bits_corrupt; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_5_a_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_5_a_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_5_a_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_5_a_bits_param; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_5_a_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_5_a_bits_source; // @[PeripheryBus.scala 50:30]
  wire [27:0] out_xbar_auto_out_5_a_bits_address; // @[PeripheryBus.scala 50:30]
  wire [3:0] out_xbar_auto_out_5_a_bits_mask; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_5_a_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_5_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_5_d_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_5_d_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_5_d_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_5_d_bits_param; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_5_d_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_5_d_bits_source; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_5_d_bits_sink; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_5_d_bits_denied; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_5_d_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_5_d_bits_corrupt; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_4_a_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_4_a_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_4_a_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_4_a_bits_param; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_4_a_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_4_a_bits_source; // @[PeripheryBus.scala 50:30]
  wire [11:0] out_xbar_auto_out_4_a_bits_address; // @[PeripheryBus.scala 50:30]
  wire [3:0] out_xbar_auto_out_4_a_bits_mask; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_4_a_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_4_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_4_d_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_4_d_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_4_d_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_4_d_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_4_d_bits_source; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_4_d_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_3_a_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_3_a_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_3_a_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_3_a_bits_param; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_3_a_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_3_a_bits_source; // @[PeripheryBus.scala 50:30]
  wire [25:0] out_xbar_auto_out_3_a_bits_address; // @[PeripheryBus.scala 50:30]
  wire [3:0] out_xbar_auto_out_3_a_bits_mask; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_3_a_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_3_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_3_d_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_3_d_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_3_d_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_3_d_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_3_d_bits_source; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_3_d_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_2_a_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_2_a_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_2_a_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_2_a_bits_param; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_2_a_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_2_a_bits_source; // @[PeripheryBus.scala 50:30]
  wire [27:0] out_xbar_auto_out_2_a_bits_address; // @[PeripheryBus.scala 50:30]
  wire [3:0] out_xbar_auto_out_2_a_bits_mask; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_2_a_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_2_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_2_d_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_2_d_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_2_d_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_2_d_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_2_d_bits_source; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_2_d_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_1_a_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_1_a_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_1_a_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_1_a_bits_param; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_1_a_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_1_a_bits_source; // @[PeripheryBus.scala 50:30]
  wire [29:0] out_xbar_auto_out_1_a_bits_address; // @[PeripheryBus.scala 50:30]
  wire [3:0] out_xbar_auto_out_1_a_bits_mask; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_1_a_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_1_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_1_d_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_1_d_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_1_d_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_1_d_bits_param; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_1_d_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_1_d_bits_source; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_1_d_bits_sink; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_1_d_bits_denied; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_1_d_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_1_d_bits_corrupt; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_0_a_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_0_a_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_0_a_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_0_a_bits_param; // @[PeripheryBus.scala 50:30]
  wire [3:0] out_xbar_auto_out_0_a_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_0_a_bits_source; // @[PeripheryBus.scala 50:30]
  wire [13:0] out_xbar_auto_out_0_a_bits_address; // @[PeripheryBus.scala 50:30]
  wire [3:0] out_xbar_auto_out_0_a_bits_mask; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_0_a_bits_corrupt; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_0_d_ready; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_0_d_valid; // @[PeripheryBus.scala 50:30]
  wire [2:0] out_xbar_auto_out_0_d_bits_opcode; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_0_d_bits_param; // @[PeripheryBus.scala 50:30]
  wire [3:0] out_xbar_auto_out_0_d_bits_size; // @[PeripheryBus.scala 50:30]
  wire [1:0] out_xbar_auto_out_0_d_bits_source; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_0_d_bits_sink; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_0_d_bits_denied; // @[PeripheryBus.scala 50:30]
  wire [31:0] out_xbar_auto_out_0_d_bits_data; // @[PeripheryBus.scala 50:30]
  wire  out_xbar_auto_out_0_d_bits_corrupt; // @[PeripheryBus.scala 50:30]
  wire  buffer_clock; // @[Buffer.scala 68:28]
  wire  buffer_reset; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
  wire [29:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_bits_sink; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_bits_denied; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
  wire [29:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_d_bits_param; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_bits_sink; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_bits_denied; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_bits_corrupt; // @[Buffer.scala 68:28]
  wire  atomics_clock; // @[AtomicAutomata.scala 283:29]
  wire  atomics_reset; // @[AtomicAutomata.scala 283:29]
  wire  atomics_auto_in_a_ready; // @[AtomicAutomata.scala 283:29]
  wire  atomics_auto_in_a_valid; // @[AtomicAutomata.scala 283:29]
  wire [2:0] atomics_auto_in_a_bits_opcode; // @[AtomicAutomata.scala 283:29]
  wire [2:0] atomics_auto_in_a_bits_param; // @[AtomicAutomata.scala 283:29]
  wire [3:0] atomics_auto_in_a_bits_size; // @[AtomicAutomata.scala 283:29]
  wire [1:0] atomics_auto_in_a_bits_source; // @[AtomicAutomata.scala 283:29]
  wire [29:0] atomics_auto_in_a_bits_address; // @[AtomicAutomata.scala 283:29]
  wire [3:0] atomics_auto_in_a_bits_mask; // @[AtomicAutomata.scala 283:29]
  wire [31:0] atomics_auto_in_a_bits_data; // @[AtomicAutomata.scala 283:29]
  wire  atomics_auto_in_a_bits_corrupt; // @[AtomicAutomata.scala 283:29]
  wire  atomics_auto_in_d_ready; // @[AtomicAutomata.scala 283:29]
  wire  atomics_auto_in_d_valid; // @[AtomicAutomata.scala 283:29]
  wire [2:0] atomics_auto_in_d_bits_opcode; // @[AtomicAutomata.scala 283:29]
  wire [1:0] atomics_auto_in_d_bits_param; // @[AtomicAutomata.scala 283:29]
  wire [3:0] atomics_auto_in_d_bits_size; // @[AtomicAutomata.scala 283:29]
  wire [1:0] atomics_auto_in_d_bits_source; // @[AtomicAutomata.scala 283:29]
  wire  atomics_auto_in_d_bits_sink; // @[AtomicAutomata.scala 283:29]
  wire  atomics_auto_in_d_bits_denied; // @[AtomicAutomata.scala 283:29]
  wire [31:0] atomics_auto_in_d_bits_data; // @[AtomicAutomata.scala 283:29]
  wire  atomics_auto_in_d_bits_corrupt; // @[AtomicAutomata.scala 283:29]
  wire  atomics_auto_out_a_ready; // @[AtomicAutomata.scala 283:29]
  wire  atomics_auto_out_a_valid; // @[AtomicAutomata.scala 283:29]
  wire [2:0] atomics_auto_out_a_bits_opcode; // @[AtomicAutomata.scala 283:29]
  wire [2:0] atomics_auto_out_a_bits_param; // @[AtomicAutomata.scala 283:29]
  wire [3:0] atomics_auto_out_a_bits_size; // @[AtomicAutomata.scala 283:29]
  wire [1:0] atomics_auto_out_a_bits_source; // @[AtomicAutomata.scala 283:29]
  wire [29:0] atomics_auto_out_a_bits_address; // @[AtomicAutomata.scala 283:29]
  wire [3:0] atomics_auto_out_a_bits_mask; // @[AtomicAutomata.scala 283:29]
  wire [31:0] atomics_auto_out_a_bits_data; // @[AtomicAutomata.scala 283:29]
  wire  atomics_auto_out_a_bits_corrupt; // @[AtomicAutomata.scala 283:29]
  wire  atomics_auto_out_d_ready; // @[AtomicAutomata.scala 283:29]
  wire  atomics_auto_out_d_valid; // @[AtomicAutomata.scala 283:29]
  wire [2:0] atomics_auto_out_d_bits_opcode; // @[AtomicAutomata.scala 283:29]
  wire [1:0] atomics_auto_out_d_bits_param; // @[AtomicAutomata.scala 283:29]
  wire [3:0] atomics_auto_out_d_bits_size; // @[AtomicAutomata.scala 283:29]
  wire [1:0] atomics_auto_out_d_bits_source; // @[AtomicAutomata.scala 283:29]
  wire  atomics_auto_out_d_bits_sink; // @[AtomicAutomata.scala 283:29]
  wire  atomics_auto_out_d_bits_denied; // @[AtomicAutomata.scala 283:29]
  wire [31:0] atomics_auto_out_d_bits_data; // @[AtomicAutomata.scala 283:29]
  wire  atomics_auto_out_d_bits_corrupt; // @[AtomicAutomata.scala 283:29]
  wire  wrapped_error_device_clock; // @[LazyModule.scala 432:27]
  wire  wrapped_error_device_reset; // @[LazyModule.scala 432:27]
  wire  wrapped_error_device_auto_buffer_in_a_ready; // @[LazyModule.scala 432:27]
  wire  wrapped_error_device_auto_buffer_in_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] wrapped_error_device_auto_buffer_in_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] wrapped_error_device_auto_buffer_in_a_bits_param; // @[LazyModule.scala 432:27]
  wire [3:0] wrapped_error_device_auto_buffer_in_a_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] wrapped_error_device_auto_buffer_in_a_bits_source; // @[LazyModule.scala 432:27]
  wire [13:0] wrapped_error_device_auto_buffer_in_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] wrapped_error_device_auto_buffer_in_a_bits_mask; // @[LazyModule.scala 432:27]
  wire  wrapped_error_device_auto_buffer_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  wrapped_error_device_auto_buffer_in_d_ready; // @[LazyModule.scala 432:27]
  wire  wrapped_error_device_auto_buffer_in_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] wrapped_error_device_auto_buffer_in_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [1:0] wrapped_error_device_auto_buffer_in_d_bits_param; // @[LazyModule.scala 432:27]
  wire [3:0] wrapped_error_device_auto_buffer_in_d_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] wrapped_error_device_auto_buffer_in_d_bits_source; // @[LazyModule.scala 432:27]
  wire  wrapped_error_device_auto_buffer_in_d_bits_sink; // @[LazyModule.scala 432:27]
  wire  wrapped_error_device_auto_buffer_in_d_bits_denied; // @[LazyModule.scala 432:27]
  wire [31:0] wrapped_error_device_auto_buffer_in_d_bits_data; // @[LazyModule.scala 432:27]
  wire  wrapped_error_device_auto_buffer_in_d_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  buffer_1_auto_in_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_in_a_bits_param; // @[Buffer.scala 68:28]
  wire [3:0] buffer_1_auto_in_a_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_1_auto_in_a_bits_source; // @[Buffer.scala 68:28]
  wire [29:0] buffer_1_auto_in_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_1_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_1_auto_in_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_1_auto_in_d_bits_param; // @[Buffer.scala 68:28]
  wire [3:0] buffer_1_auto_in_d_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_1_auto_in_d_bits_source; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_d_bits_sink; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_d_bits_denied; // @[Buffer.scala 68:28]
  wire [31:0] buffer_1_auto_in_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_d_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_out_a_bits_param; // @[Buffer.scala 68:28]
  wire [3:0] buffer_1_auto_out_a_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_1_auto_out_a_bits_source; // @[Buffer.scala 68:28]
  wire [29:0] buffer_1_auto_out_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_1_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_1_auto_out_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_1_auto_out_d_bits_param; // @[Buffer.scala 68:28]
  wire [3:0] buffer_1_auto_out_d_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_1_auto_out_d_bits_source; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_d_bits_sink; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_d_bits_denied; // @[Buffer.scala 68:28]
  wire [31:0] buffer_1_auto_out_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_d_bits_corrupt; // @[Buffer.scala 68:28]
  wire  coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_source; // @[LazyModule.scala 432:27]
  wire [29:0] coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_source; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_sink; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_denied; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_source; // @[LazyModule.scala 432:27]
  wire [29:0] coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_source; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_sink; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_denied; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_plic_clock; // @[LazyModule.scala 432:27]
  wire  coupler_to_plic_reset; // @[LazyModule.scala 432:27]
  wire  coupler_to_plic_auto_fragmenter_out_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_plic_auto_fragmenter_out_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_plic_auto_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_plic_auto_fragmenter_out_a_bits_param; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_plic_auto_fragmenter_out_a_bits_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_plic_auto_fragmenter_out_a_bits_source; // @[LazyModule.scala 432:27]
  wire [27:0] coupler_to_plic_auto_fragmenter_out_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_plic_auto_fragmenter_out_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_plic_auto_fragmenter_out_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_plic_auto_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_plic_auto_fragmenter_out_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_plic_auto_fragmenter_out_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_plic_auto_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_plic_auto_fragmenter_out_d_bits_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_plic_auto_fragmenter_out_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_plic_auto_fragmenter_out_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_plic_auto_tl_in_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_plic_auto_tl_in_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_plic_auto_tl_in_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_plic_auto_tl_in_a_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_plic_auto_tl_in_a_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_plic_auto_tl_in_a_bits_source; // @[LazyModule.scala 432:27]
  wire [27:0] coupler_to_plic_auto_tl_in_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_plic_auto_tl_in_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_plic_auto_tl_in_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_plic_auto_tl_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_plic_auto_tl_in_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_plic_auto_tl_in_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_plic_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_plic_auto_tl_in_d_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_plic_auto_tl_in_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_plic_auto_tl_in_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_clint_clock; // @[LazyModule.scala 432:27]
  wire  coupler_to_clint_reset; // @[LazyModule.scala 432:27]
  wire  coupler_to_clint_auto_fragmenter_out_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_clint_auto_fragmenter_out_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_clint_auto_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_clint_auto_fragmenter_out_a_bits_param; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_clint_auto_fragmenter_out_a_bits_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_clint_auto_fragmenter_out_a_bits_source; // @[LazyModule.scala 432:27]
  wire [25:0] coupler_to_clint_auto_fragmenter_out_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_clint_auto_fragmenter_out_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_clint_auto_fragmenter_out_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_clint_auto_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_clint_auto_fragmenter_out_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_clint_auto_fragmenter_out_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_clint_auto_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_clint_auto_fragmenter_out_d_bits_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_clint_auto_fragmenter_out_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_clint_auto_fragmenter_out_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_clint_auto_tl_in_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_clint_auto_tl_in_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_clint_auto_tl_in_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_clint_auto_tl_in_a_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_clint_auto_tl_in_a_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_clint_auto_tl_in_a_bits_source; // @[LazyModule.scala 432:27]
  wire [25:0] coupler_to_clint_auto_tl_in_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_clint_auto_tl_in_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_clint_auto_tl_in_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_clint_auto_tl_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_clint_auto_tl_in_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_clint_auto_tl_in_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_clint_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_clint_auto_tl_in_d_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_clint_auto_tl_in_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_clint_auto_tl_in_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_debug_clock; // @[LazyModule.scala 432:27]
  wire  coupler_to_debug_reset; // @[LazyModule.scala 432:27]
  wire  coupler_to_debug_auto_fragmenter_out_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_debug_auto_fragmenter_out_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_debug_auto_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_debug_auto_fragmenter_out_a_bits_param; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_debug_auto_fragmenter_out_a_bits_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_debug_auto_fragmenter_out_a_bits_source; // @[LazyModule.scala 432:27]
  wire [11:0] coupler_to_debug_auto_fragmenter_out_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_debug_auto_fragmenter_out_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_debug_auto_fragmenter_out_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_debug_auto_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_debug_auto_fragmenter_out_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_debug_auto_fragmenter_out_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_debug_auto_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_debug_auto_fragmenter_out_d_bits_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_debug_auto_fragmenter_out_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_debug_auto_fragmenter_out_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_debug_auto_tl_in_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_debug_auto_tl_in_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_debug_auto_tl_in_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_debug_auto_tl_in_a_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_debug_auto_tl_in_a_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_debug_auto_tl_in_a_bits_source; // @[LazyModule.scala 432:27]
  wire [11:0] coupler_to_debug_auto_tl_in_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_debug_auto_tl_in_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_debug_auto_tl_in_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_debug_auto_tl_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_debug_auto_tl_in_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_debug_auto_tl_in_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_debug_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_debug_auto_tl_in_d_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_debug_auto_tl_in_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_debug_auto_tl_in_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_tile_auto_tl_slave_clock_xing_out_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_tile_auto_tl_slave_clock_xing_out_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_source; // @[LazyModule.scala 432:27]
  wire [27:0] coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_tile_auto_tl_slave_clock_xing_out_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_tile_auto_tl_slave_clock_xing_out_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_source; // @[LazyModule.scala 432:27]
  wire  coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_sink; // @[LazyModule.scala 432:27]
  wire  coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_denied; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_tile_auto_tl_in_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_tile_auto_tl_in_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_tile_auto_tl_in_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_tile_auto_tl_in_a_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_tile_auto_tl_in_a_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_tile_auto_tl_in_a_bits_source; // @[LazyModule.scala 432:27]
  wire [27:0] coupler_to_tile_auto_tl_in_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_tile_auto_tl_in_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_tile_auto_tl_in_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_tile_auto_tl_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_tile_auto_tl_in_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_tile_auto_tl_in_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_tile_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_tile_auto_tl_in_d_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_tile_auto_tl_in_d_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_tile_auto_tl_in_d_bits_source; // @[LazyModule.scala 432:27]
  wire  coupler_to_tile_auto_tl_in_d_bits_sink; // @[LazyModule.scala 432:27]
  wire  coupler_to_tile_auto_tl_in_d_bits_denied; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_tile_auto_tl_in_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_tile_auto_tl_in_d_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_aon_clock; // @[LazyModule.scala 432:27]
  wire  coupler_to_aon_reset; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_aon_auto_asource_out_a_mem_0_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_aon_auto_asource_out_a_mem_0_param; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_aon_auto_asource_out_a_mem_0_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_aon_auto_asource_out_a_mem_0_source; // @[LazyModule.scala 432:27]
  wire [28:0] coupler_to_aon_auto_asource_out_a_mem_0_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_aon_auto_asource_out_a_mem_0_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_aon_auto_asource_out_a_mem_0_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_aon_auto_asource_out_a_mem_0_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_aon_auto_asource_out_a_ridx; // @[LazyModule.scala 432:27]
  wire  coupler_to_aon_auto_asource_out_a_widx; // @[LazyModule.scala 432:27]
  wire  coupler_to_aon_auto_asource_out_a_safe_ridx_valid; // @[LazyModule.scala 432:27]
  wire  coupler_to_aon_auto_asource_out_a_safe_widx_valid; // @[LazyModule.scala 432:27]
  wire  coupler_to_aon_auto_asource_out_a_safe_source_reset_n; // @[LazyModule.scala 432:27]
  wire  coupler_to_aon_auto_asource_out_a_safe_sink_reset_n; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_aon_auto_asource_out_d_mem_0_opcode; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_aon_auto_asource_out_d_mem_0_param; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_aon_auto_asource_out_d_mem_0_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_aon_auto_asource_out_d_mem_0_source; // @[LazyModule.scala 432:27]
  wire  coupler_to_aon_auto_asource_out_d_mem_0_sink; // @[LazyModule.scala 432:27]
  wire  coupler_to_aon_auto_asource_out_d_mem_0_denied; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_aon_auto_asource_out_d_mem_0_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_aon_auto_asource_out_d_mem_0_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_aon_auto_asource_out_d_ridx; // @[LazyModule.scala 432:27]
  wire  coupler_to_aon_auto_asource_out_d_widx; // @[LazyModule.scala 432:27]
  wire  coupler_to_aon_auto_asource_out_d_safe_ridx_valid; // @[LazyModule.scala 432:27]
  wire  coupler_to_aon_auto_asource_out_d_safe_widx_valid; // @[LazyModule.scala 432:27]
  wire  coupler_to_aon_auto_asource_out_d_safe_source_reset_n; // @[LazyModule.scala 432:27]
  wire  coupler_to_aon_auto_asource_out_d_safe_sink_reset_n; // @[LazyModule.scala 432:27]
  wire  coupler_to_aon_auto_tl_in_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_aon_auto_tl_in_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_aon_auto_tl_in_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_aon_auto_tl_in_a_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_aon_auto_tl_in_a_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_aon_auto_tl_in_a_bits_source; // @[LazyModule.scala 432:27]
  wire [28:0] coupler_to_aon_auto_tl_in_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_aon_auto_tl_in_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_aon_auto_tl_in_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_aon_auto_tl_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_aon_auto_tl_in_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_aon_auto_tl_in_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_aon_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_aon_auto_tl_in_d_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_aon_auto_tl_in_d_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_aon_auto_tl_in_d_bits_source; // @[LazyModule.scala 432:27]
  wire  coupler_to_aon_auto_tl_in_d_bits_sink; // @[LazyModule.scala 432:27]
  wire  coupler_to_aon_auto_tl_in_d_bits_denied; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_aon_auto_tl_in_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_aon_auto_tl_in_d_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_bootrom_clock; // @[LazyModule.scala 432:27]
  wire  coupler_to_bootrom_reset; // @[LazyModule.scala 432:27]
  wire  coupler_to_bootrom_auto_fragmenter_out_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_bootrom_auto_fragmenter_out_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bootrom_auto_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bootrom_auto_fragmenter_out_a_bits_param; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_bootrom_auto_fragmenter_out_a_bits_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_bootrom_auto_fragmenter_out_a_bits_source; // @[LazyModule.scala 432:27]
  wire [16:0] coupler_to_bootrom_auto_fragmenter_out_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_bootrom_auto_fragmenter_out_a_bits_mask; // @[LazyModule.scala 432:27]
  wire  coupler_to_bootrom_auto_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_bootrom_auto_fragmenter_out_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_bootrom_auto_fragmenter_out_d_valid; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_bootrom_auto_fragmenter_out_d_bits_size; // @[LazyModule.scala 432:27]
  wire [6:0] coupler_to_bootrom_auto_fragmenter_out_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_bootrom_auto_fragmenter_out_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_bootrom_auto_tl_in_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_bootrom_auto_tl_in_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bootrom_auto_tl_in_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bootrom_auto_tl_in_a_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bootrom_auto_tl_in_a_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_bootrom_auto_tl_in_a_bits_source; // @[LazyModule.scala 432:27]
  wire [16:0] coupler_to_bootrom_auto_tl_in_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_bootrom_auto_tl_in_a_bits_mask; // @[LazyModule.scala 432:27]
  wire  coupler_to_bootrom_auto_tl_in_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_bootrom_auto_tl_in_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_bootrom_auto_tl_in_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bootrom_auto_tl_in_d_bits_size; // @[LazyModule.scala 432:27]
  wire [1:0] coupler_to_bootrom_auto_tl_in_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_bootrom_auto_tl_in_d_bits_data; // @[LazyModule.scala 432:27]
  ClockGroupAggregator_3 subsystem_cbus_clock_groups ( // @[BusWrapper.scala 40:48]
    .auto_in_member_subsystem_cbus_1_clock(subsystem_cbus_clock_groups_auto_in_member_subsystem_cbus_1_clock),
    .auto_in_member_subsystem_cbus_1_reset(subsystem_cbus_clock_groups_auto_in_member_subsystem_cbus_1_reset),
    .auto_in_member_subsystem_cbus_0_clock(subsystem_cbus_clock_groups_auto_in_member_subsystem_cbus_0_clock),
    .auto_in_member_subsystem_cbus_0_reset(subsystem_cbus_clock_groups_auto_in_member_subsystem_cbus_0_reset),
    .auto_out_1_member_subsystem_pbus_0_clock(subsystem_cbus_clock_groups_auto_out_1_member_subsystem_pbus_0_clock),
    .auto_out_1_member_subsystem_pbus_0_reset(subsystem_cbus_clock_groups_auto_out_1_member_subsystem_pbus_0_reset),
    .auto_out_0_member_subsystem_cbus_0_clock(subsystem_cbus_clock_groups_auto_out_0_member_subsystem_cbus_0_clock),
    .auto_out_0_member_subsystem_cbus_0_reset(subsystem_cbus_clock_groups_auto_out_0_member_subsystem_cbus_0_reset)
  );
  ClockGroup_3 clockGroup ( // @[BusWrapper.scala 41:38]
    .auto_in_member_subsystem_cbus_0_clock(clockGroup_auto_in_member_subsystem_cbus_0_clock),
    .auto_in_member_subsystem_cbus_0_reset(clockGroup_auto_in_member_subsystem_cbus_0_reset),
    .auto_out_clock(clockGroup_auto_out_clock),
    .auto_out_reset(clockGroup_auto_out_reset)
  );
  FixedClockBroadcast_3 fixedClockNode ( // @[ClockGroup.scala 106:107]
    .auto_in_clock(fixedClockNode_auto_in_clock),
    .auto_in_reset(fixedClockNode_auto_in_reset),
    .auto_out_3_clock(fixedClockNode_auto_out_3_clock),
    .auto_out_3_reset(fixedClockNode_auto_out_3_reset),
    .auto_out_1_clock(fixedClockNode_auto_out_1_clock),
    .auto_out_1_reset(fixedClockNode_auto_out_1_reset),
    .auto_out_0_clock(fixedClockNode_auto_out_0_clock),
    .auto_out_0_reset(fixedClockNode_auto_out_0_reset)
  );
  TLFIFOFixer_2 fixer ( // @[PeripheryBus.scala 47:33]
    .clock(fixer_clock),
    .reset(fixer_reset),
    .auto_in_a_ready(fixer_auto_in_a_ready),
    .auto_in_a_valid(fixer_auto_in_a_valid),
    .auto_in_a_bits_opcode(fixer_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(fixer_auto_in_a_bits_param),
    .auto_in_a_bits_size(fixer_auto_in_a_bits_size),
    .auto_in_a_bits_source(fixer_auto_in_a_bits_source),
    .auto_in_a_bits_address(fixer_auto_in_a_bits_address),
    .auto_in_a_bits_mask(fixer_auto_in_a_bits_mask),
    .auto_in_a_bits_data(fixer_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(fixer_auto_in_a_bits_corrupt),
    .auto_in_d_ready(fixer_auto_in_d_ready),
    .auto_in_d_valid(fixer_auto_in_d_valid),
    .auto_in_d_bits_opcode(fixer_auto_in_d_bits_opcode),
    .auto_in_d_bits_param(fixer_auto_in_d_bits_param),
    .auto_in_d_bits_size(fixer_auto_in_d_bits_size),
    .auto_in_d_bits_source(fixer_auto_in_d_bits_source),
    .auto_in_d_bits_sink(fixer_auto_in_d_bits_sink),
    .auto_in_d_bits_denied(fixer_auto_in_d_bits_denied),
    .auto_in_d_bits_data(fixer_auto_in_d_bits_data),
    .auto_in_d_bits_corrupt(fixer_auto_in_d_bits_corrupt),
    .auto_out_a_ready(fixer_auto_out_a_ready),
    .auto_out_a_valid(fixer_auto_out_a_valid),
    .auto_out_a_bits_opcode(fixer_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(fixer_auto_out_a_bits_param),
    .auto_out_a_bits_size(fixer_auto_out_a_bits_size),
    .auto_out_a_bits_source(fixer_auto_out_a_bits_source),
    .auto_out_a_bits_address(fixer_auto_out_a_bits_address),
    .auto_out_a_bits_mask(fixer_auto_out_a_bits_mask),
    .auto_out_a_bits_data(fixer_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(fixer_auto_out_a_bits_corrupt),
    .auto_out_d_ready(fixer_auto_out_d_ready),
    .auto_out_d_valid(fixer_auto_out_d_valid),
    .auto_out_d_bits_opcode(fixer_auto_out_d_bits_opcode),
    .auto_out_d_bits_param(fixer_auto_out_d_bits_param),
    .auto_out_d_bits_size(fixer_auto_out_d_bits_size),
    .auto_out_d_bits_source(fixer_auto_out_d_bits_source),
    .auto_out_d_bits_sink(fixer_auto_out_d_bits_sink),
    .auto_out_d_bits_denied(fixer_auto_out_d_bits_denied),
    .auto_out_d_bits_data(fixer_auto_out_d_bits_data),
    .auto_out_d_bits_corrupt(fixer_auto_out_d_bits_corrupt)
  );
  TLXbar_4 in_xbar ( // @[PeripheryBus.scala 49:29]
    .auto_in_a_ready(in_xbar_auto_in_a_ready),
    .auto_in_a_valid(in_xbar_auto_in_a_valid),
    .auto_in_a_bits_opcode(in_xbar_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(in_xbar_auto_in_a_bits_param),
    .auto_in_a_bits_size(in_xbar_auto_in_a_bits_size),
    .auto_in_a_bits_source(in_xbar_auto_in_a_bits_source),
    .auto_in_a_bits_address(in_xbar_auto_in_a_bits_address),
    .auto_in_a_bits_mask(in_xbar_auto_in_a_bits_mask),
    .auto_in_a_bits_data(in_xbar_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(in_xbar_auto_in_a_bits_corrupt),
    .auto_in_d_ready(in_xbar_auto_in_d_ready),
    .auto_in_d_valid(in_xbar_auto_in_d_valid),
    .auto_in_d_bits_opcode(in_xbar_auto_in_d_bits_opcode),
    .auto_in_d_bits_param(in_xbar_auto_in_d_bits_param),
    .auto_in_d_bits_size(in_xbar_auto_in_d_bits_size),
    .auto_in_d_bits_source(in_xbar_auto_in_d_bits_source),
    .auto_in_d_bits_sink(in_xbar_auto_in_d_bits_sink),
    .auto_in_d_bits_denied(in_xbar_auto_in_d_bits_denied),
    .auto_in_d_bits_data(in_xbar_auto_in_d_bits_data),
    .auto_in_d_bits_corrupt(in_xbar_auto_in_d_bits_corrupt),
    .auto_out_a_ready(in_xbar_auto_out_a_ready),
    .auto_out_a_valid(in_xbar_auto_out_a_valid),
    .auto_out_a_bits_opcode(in_xbar_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(in_xbar_auto_out_a_bits_param),
    .auto_out_a_bits_size(in_xbar_auto_out_a_bits_size),
    .auto_out_a_bits_source(in_xbar_auto_out_a_bits_source),
    .auto_out_a_bits_address(in_xbar_auto_out_a_bits_address),
    .auto_out_a_bits_mask(in_xbar_auto_out_a_bits_mask),
    .auto_out_a_bits_data(in_xbar_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(in_xbar_auto_out_a_bits_corrupt),
    .auto_out_d_ready(in_xbar_auto_out_d_ready),
    .auto_out_d_valid(in_xbar_auto_out_d_valid),
    .auto_out_d_bits_opcode(in_xbar_auto_out_d_bits_opcode),
    .auto_out_d_bits_param(in_xbar_auto_out_d_bits_param),
    .auto_out_d_bits_size(in_xbar_auto_out_d_bits_size),
    .auto_out_d_bits_source(in_xbar_auto_out_d_bits_source),
    .auto_out_d_bits_sink(in_xbar_auto_out_d_bits_sink),
    .auto_out_d_bits_denied(in_xbar_auto_out_d_bits_denied),
    .auto_out_d_bits_data(in_xbar_auto_out_d_bits_data),
    .auto_out_d_bits_corrupt(in_xbar_auto_out_d_bits_corrupt)
  );
  TLXbar_5 out_xbar ( // @[PeripheryBus.scala 50:30]
    .clock(out_xbar_clock),
    .reset(out_xbar_reset),
    .auto_in_a_ready(out_xbar_auto_in_a_ready),
    .auto_in_a_valid(out_xbar_auto_in_a_valid),
    .auto_in_a_bits_opcode(out_xbar_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(out_xbar_auto_in_a_bits_param),
    .auto_in_a_bits_size(out_xbar_auto_in_a_bits_size),
    .auto_in_a_bits_source(out_xbar_auto_in_a_bits_source),
    .auto_in_a_bits_address(out_xbar_auto_in_a_bits_address),
    .auto_in_a_bits_mask(out_xbar_auto_in_a_bits_mask),
    .auto_in_a_bits_data(out_xbar_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(out_xbar_auto_in_a_bits_corrupt),
    .auto_in_d_ready(out_xbar_auto_in_d_ready),
    .auto_in_d_valid(out_xbar_auto_in_d_valid),
    .auto_in_d_bits_opcode(out_xbar_auto_in_d_bits_opcode),
    .auto_in_d_bits_param(out_xbar_auto_in_d_bits_param),
    .auto_in_d_bits_size(out_xbar_auto_in_d_bits_size),
    .auto_in_d_bits_source(out_xbar_auto_in_d_bits_source),
    .auto_in_d_bits_sink(out_xbar_auto_in_d_bits_sink),
    .auto_in_d_bits_denied(out_xbar_auto_in_d_bits_denied),
    .auto_in_d_bits_data(out_xbar_auto_in_d_bits_data),
    .auto_in_d_bits_corrupt(out_xbar_auto_in_d_bits_corrupt),
    .auto_out_7_a_ready(out_xbar_auto_out_7_a_ready),
    .auto_out_7_a_valid(out_xbar_auto_out_7_a_valid),
    .auto_out_7_a_bits_opcode(out_xbar_auto_out_7_a_bits_opcode),
    .auto_out_7_a_bits_param(out_xbar_auto_out_7_a_bits_param),
    .auto_out_7_a_bits_size(out_xbar_auto_out_7_a_bits_size),
    .auto_out_7_a_bits_source(out_xbar_auto_out_7_a_bits_source),
    .auto_out_7_a_bits_address(out_xbar_auto_out_7_a_bits_address),
    .auto_out_7_a_bits_mask(out_xbar_auto_out_7_a_bits_mask),
    .auto_out_7_a_bits_corrupt(out_xbar_auto_out_7_a_bits_corrupt),
    .auto_out_7_d_ready(out_xbar_auto_out_7_d_ready),
    .auto_out_7_d_valid(out_xbar_auto_out_7_d_valid),
    .auto_out_7_d_bits_size(out_xbar_auto_out_7_d_bits_size),
    .auto_out_7_d_bits_source(out_xbar_auto_out_7_d_bits_source),
    .auto_out_7_d_bits_data(out_xbar_auto_out_7_d_bits_data),
    .auto_out_6_a_ready(out_xbar_auto_out_6_a_ready),
    .auto_out_6_a_valid(out_xbar_auto_out_6_a_valid),
    .auto_out_6_a_bits_opcode(out_xbar_auto_out_6_a_bits_opcode),
    .auto_out_6_a_bits_param(out_xbar_auto_out_6_a_bits_param),
    .auto_out_6_a_bits_size(out_xbar_auto_out_6_a_bits_size),
    .auto_out_6_a_bits_source(out_xbar_auto_out_6_a_bits_source),
    .auto_out_6_a_bits_address(out_xbar_auto_out_6_a_bits_address),
    .auto_out_6_a_bits_mask(out_xbar_auto_out_6_a_bits_mask),
    .auto_out_6_a_bits_data(out_xbar_auto_out_6_a_bits_data),
    .auto_out_6_a_bits_corrupt(out_xbar_auto_out_6_a_bits_corrupt),
    .auto_out_6_d_ready(out_xbar_auto_out_6_d_ready),
    .auto_out_6_d_valid(out_xbar_auto_out_6_d_valid),
    .auto_out_6_d_bits_opcode(out_xbar_auto_out_6_d_bits_opcode),
    .auto_out_6_d_bits_param(out_xbar_auto_out_6_d_bits_param),
    .auto_out_6_d_bits_size(out_xbar_auto_out_6_d_bits_size),
    .auto_out_6_d_bits_source(out_xbar_auto_out_6_d_bits_source),
    .auto_out_6_d_bits_sink(out_xbar_auto_out_6_d_bits_sink),
    .auto_out_6_d_bits_denied(out_xbar_auto_out_6_d_bits_denied),
    .auto_out_6_d_bits_data(out_xbar_auto_out_6_d_bits_data),
    .auto_out_6_d_bits_corrupt(out_xbar_auto_out_6_d_bits_corrupt),
    .auto_out_5_a_ready(out_xbar_auto_out_5_a_ready),
    .auto_out_5_a_valid(out_xbar_auto_out_5_a_valid),
    .auto_out_5_a_bits_opcode(out_xbar_auto_out_5_a_bits_opcode),
    .auto_out_5_a_bits_param(out_xbar_auto_out_5_a_bits_param),
    .auto_out_5_a_bits_size(out_xbar_auto_out_5_a_bits_size),
    .auto_out_5_a_bits_source(out_xbar_auto_out_5_a_bits_source),
    .auto_out_5_a_bits_address(out_xbar_auto_out_5_a_bits_address),
    .auto_out_5_a_bits_mask(out_xbar_auto_out_5_a_bits_mask),
    .auto_out_5_a_bits_data(out_xbar_auto_out_5_a_bits_data),
    .auto_out_5_a_bits_corrupt(out_xbar_auto_out_5_a_bits_corrupt),
    .auto_out_5_d_ready(out_xbar_auto_out_5_d_ready),
    .auto_out_5_d_valid(out_xbar_auto_out_5_d_valid),
    .auto_out_5_d_bits_opcode(out_xbar_auto_out_5_d_bits_opcode),
    .auto_out_5_d_bits_param(out_xbar_auto_out_5_d_bits_param),
    .auto_out_5_d_bits_size(out_xbar_auto_out_5_d_bits_size),
    .auto_out_5_d_bits_source(out_xbar_auto_out_5_d_bits_source),
    .auto_out_5_d_bits_sink(out_xbar_auto_out_5_d_bits_sink),
    .auto_out_5_d_bits_denied(out_xbar_auto_out_5_d_bits_denied),
    .auto_out_5_d_bits_data(out_xbar_auto_out_5_d_bits_data),
    .auto_out_5_d_bits_corrupt(out_xbar_auto_out_5_d_bits_corrupt),
    .auto_out_4_a_ready(out_xbar_auto_out_4_a_ready),
    .auto_out_4_a_valid(out_xbar_auto_out_4_a_valid),
    .auto_out_4_a_bits_opcode(out_xbar_auto_out_4_a_bits_opcode),
    .auto_out_4_a_bits_param(out_xbar_auto_out_4_a_bits_param),
    .auto_out_4_a_bits_size(out_xbar_auto_out_4_a_bits_size),
    .auto_out_4_a_bits_source(out_xbar_auto_out_4_a_bits_source),
    .auto_out_4_a_bits_address(out_xbar_auto_out_4_a_bits_address),
    .auto_out_4_a_bits_mask(out_xbar_auto_out_4_a_bits_mask),
    .auto_out_4_a_bits_data(out_xbar_auto_out_4_a_bits_data),
    .auto_out_4_a_bits_corrupt(out_xbar_auto_out_4_a_bits_corrupt),
    .auto_out_4_d_ready(out_xbar_auto_out_4_d_ready),
    .auto_out_4_d_valid(out_xbar_auto_out_4_d_valid),
    .auto_out_4_d_bits_opcode(out_xbar_auto_out_4_d_bits_opcode),
    .auto_out_4_d_bits_size(out_xbar_auto_out_4_d_bits_size),
    .auto_out_4_d_bits_source(out_xbar_auto_out_4_d_bits_source),
    .auto_out_4_d_bits_data(out_xbar_auto_out_4_d_bits_data),
    .auto_out_3_a_ready(out_xbar_auto_out_3_a_ready),
    .auto_out_3_a_valid(out_xbar_auto_out_3_a_valid),
    .auto_out_3_a_bits_opcode(out_xbar_auto_out_3_a_bits_opcode),
    .auto_out_3_a_bits_param(out_xbar_auto_out_3_a_bits_param),
    .auto_out_3_a_bits_size(out_xbar_auto_out_3_a_bits_size),
    .auto_out_3_a_bits_source(out_xbar_auto_out_3_a_bits_source),
    .auto_out_3_a_bits_address(out_xbar_auto_out_3_a_bits_address),
    .auto_out_3_a_bits_mask(out_xbar_auto_out_3_a_bits_mask),
    .auto_out_3_a_bits_data(out_xbar_auto_out_3_a_bits_data),
    .auto_out_3_a_bits_corrupt(out_xbar_auto_out_3_a_bits_corrupt),
    .auto_out_3_d_ready(out_xbar_auto_out_3_d_ready),
    .auto_out_3_d_valid(out_xbar_auto_out_3_d_valid),
    .auto_out_3_d_bits_opcode(out_xbar_auto_out_3_d_bits_opcode),
    .auto_out_3_d_bits_size(out_xbar_auto_out_3_d_bits_size),
    .auto_out_3_d_bits_source(out_xbar_auto_out_3_d_bits_source),
    .auto_out_3_d_bits_data(out_xbar_auto_out_3_d_bits_data),
    .auto_out_2_a_ready(out_xbar_auto_out_2_a_ready),
    .auto_out_2_a_valid(out_xbar_auto_out_2_a_valid),
    .auto_out_2_a_bits_opcode(out_xbar_auto_out_2_a_bits_opcode),
    .auto_out_2_a_bits_param(out_xbar_auto_out_2_a_bits_param),
    .auto_out_2_a_bits_size(out_xbar_auto_out_2_a_bits_size),
    .auto_out_2_a_bits_source(out_xbar_auto_out_2_a_bits_source),
    .auto_out_2_a_bits_address(out_xbar_auto_out_2_a_bits_address),
    .auto_out_2_a_bits_mask(out_xbar_auto_out_2_a_bits_mask),
    .auto_out_2_a_bits_data(out_xbar_auto_out_2_a_bits_data),
    .auto_out_2_a_bits_corrupt(out_xbar_auto_out_2_a_bits_corrupt),
    .auto_out_2_d_ready(out_xbar_auto_out_2_d_ready),
    .auto_out_2_d_valid(out_xbar_auto_out_2_d_valid),
    .auto_out_2_d_bits_opcode(out_xbar_auto_out_2_d_bits_opcode),
    .auto_out_2_d_bits_size(out_xbar_auto_out_2_d_bits_size),
    .auto_out_2_d_bits_source(out_xbar_auto_out_2_d_bits_source),
    .auto_out_2_d_bits_data(out_xbar_auto_out_2_d_bits_data),
    .auto_out_1_a_ready(out_xbar_auto_out_1_a_ready),
    .auto_out_1_a_valid(out_xbar_auto_out_1_a_valid),
    .auto_out_1_a_bits_opcode(out_xbar_auto_out_1_a_bits_opcode),
    .auto_out_1_a_bits_param(out_xbar_auto_out_1_a_bits_param),
    .auto_out_1_a_bits_size(out_xbar_auto_out_1_a_bits_size),
    .auto_out_1_a_bits_source(out_xbar_auto_out_1_a_bits_source),
    .auto_out_1_a_bits_address(out_xbar_auto_out_1_a_bits_address),
    .auto_out_1_a_bits_mask(out_xbar_auto_out_1_a_bits_mask),
    .auto_out_1_a_bits_data(out_xbar_auto_out_1_a_bits_data),
    .auto_out_1_a_bits_corrupt(out_xbar_auto_out_1_a_bits_corrupt),
    .auto_out_1_d_ready(out_xbar_auto_out_1_d_ready),
    .auto_out_1_d_valid(out_xbar_auto_out_1_d_valid),
    .auto_out_1_d_bits_opcode(out_xbar_auto_out_1_d_bits_opcode),
    .auto_out_1_d_bits_param(out_xbar_auto_out_1_d_bits_param),
    .auto_out_1_d_bits_size(out_xbar_auto_out_1_d_bits_size),
    .auto_out_1_d_bits_source(out_xbar_auto_out_1_d_bits_source),
    .auto_out_1_d_bits_sink(out_xbar_auto_out_1_d_bits_sink),
    .auto_out_1_d_bits_denied(out_xbar_auto_out_1_d_bits_denied),
    .auto_out_1_d_bits_data(out_xbar_auto_out_1_d_bits_data),
    .auto_out_1_d_bits_corrupt(out_xbar_auto_out_1_d_bits_corrupt),
    .auto_out_0_a_ready(out_xbar_auto_out_0_a_ready),
    .auto_out_0_a_valid(out_xbar_auto_out_0_a_valid),
    .auto_out_0_a_bits_opcode(out_xbar_auto_out_0_a_bits_opcode),
    .auto_out_0_a_bits_param(out_xbar_auto_out_0_a_bits_param),
    .auto_out_0_a_bits_size(out_xbar_auto_out_0_a_bits_size),
    .auto_out_0_a_bits_source(out_xbar_auto_out_0_a_bits_source),
    .auto_out_0_a_bits_address(out_xbar_auto_out_0_a_bits_address),
    .auto_out_0_a_bits_mask(out_xbar_auto_out_0_a_bits_mask),
    .auto_out_0_a_bits_corrupt(out_xbar_auto_out_0_a_bits_corrupt),
    .auto_out_0_d_ready(out_xbar_auto_out_0_d_ready),
    .auto_out_0_d_valid(out_xbar_auto_out_0_d_valid),
    .auto_out_0_d_bits_opcode(out_xbar_auto_out_0_d_bits_opcode),
    .auto_out_0_d_bits_param(out_xbar_auto_out_0_d_bits_param),
    .auto_out_0_d_bits_size(out_xbar_auto_out_0_d_bits_size),
    .auto_out_0_d_bits_source(out_xbar_auto_out_0_d_bits_source),
    .auto_out_0_d_bits_sink(out_xbar_auto_out_0_d_bits_sink),
    .auto_out_0_d_bits_denied(out_xbar_auto_out_0_d_bits_denied),
    .auto_out_0_d_bits_data(out_xbar_auto_out_0_d_bits_data),
    .auto_out_0_d_bits_corrupt(out_xbar_auto_out_0_d_bits_corrupt)
  );
  TLBuffer_4 buffer ( // @[Buffer.scala 68:28]
    .clock(buffer_clock),
    .reset(buffer_reset),
    .auto_in_a_ready(buffer_auto_in_a_ready),
    .auto_in_a_valid(buffer_auto_in_a_valid),
    .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
    .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
    .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
    .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
    .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
    .auto_in_a_bits_data(buffer_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
    .auto_in_d_ready(buffer_auto_in_d_ready),
    .auto_in_d_valid(buffer_auto_in_d_valid),
    .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
    .auto_in_d_bits_param(buffer_auto_in_d_bits_param),
    .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
    .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
    .auto_in_d_bits_sink(buffer_auto_in_d_bits_sink),
    .auto_in_d_bits_denied(buffer_auto_in_d_bits_denied),
    .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
    .auto_in_d_bits_corrupt(buffer_auto_in_d_bits_corrupt),
    .auto_out_a_ready(buffer_auto_out_a_ready),
    .auto_out_a_valid(buffer_auto_out_a_valid),
    .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
    .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
    .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
    .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
    .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
    .auto_out_a_bits_data(buffer_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
    .auto_out_d_ready(buffer_auto_out_d_ready),
    .auto_out_d_valid(buffer_auto_out_d_valid),
    .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
    .auto_out_d_bits_param(buffer_auto_out_d_bits_param),
    .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
    .auto_out_d_bits_source(buffer_auto_out_d_bits_source),
    .auto_out_d_bits_sink(buffer_auto_out_d_bits_sink),
    .auto_out_d_bits_denied(buffer_auto_out_d_bits_denied),
    .auto_out_d_bits_data(buffer_auto_out_d_bits_data),
    .auto_out_d_bits_corrupt(buffer_auto_out_d_bits_corrupt)
  );
  TLAtomicAutomata_1 atomics ( // @[AtomicAutomata.scala 283:29]
    .clock(atomics_clock),
    .reset(atomics_reset),
    .auto_in_a_ready(atomics_auto_in_a_ready),
    .auto_in_a_valid(atomics_auto_in_a_valid),
    .auto_in_a_bits_opcode(atomics_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(atomics_auto_in_a_bits_param),
    .auto_in_a_bits_size(atomics_auto_in_a_bits_size),
    .auto_in_a_bits_source(atomics_auto_in_a_bits_source),
    .auto_in_a_bits_address(atomics_auto_in_a_bits_address),
    .auto_in_a_bits_mask(atomics_auto_in_a_bits_mask),
    .auto_in_a_bits_data(atomics_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(atomics_auto_in_a_bits_corrupt),
    .auto_in_d_ready(atomics_auto_in_d_ready),
    .auto_in_d_valid(atomics_auto_in_d_valid),
    .auto_in_d_bits_opcode(atomics_auto_in_d_bits_opcode),
    .auto_in_d_bits_param(atomics_auto_in_d_bits_param),
    .auto_in_d_bits_size(atomics_auto_in_d_bits_size),
    .auto_in_d_bits_source(atomics_auto_in_d_bits_source),
    .auto_in_d_bits_sink(atomics_auto_in_d_bits_sink),
    .auto_in_d_bits_denied(atomics_auto_in_d_bits_denied),
    .auto_in_d_bits_data(atomics_auto_in_d_bits_data),
    .auto_in_d_bits_corrupt(atomics_auto_in_d_bits_corrupt),
    .auto_out_a_ready(atomics_auto_out_a_ready),
    .auto_out_a_valid(atomics_auto_out_a_valid),
    .auto_out_a_bits_opcode(atomics_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(atomics_auto_out_a_bits_param),
    .auto_out_a_bits_size(atomics_auto_out_a_bits_size),
    .auto_out_a_bits_source(atomics_auto_out_a_bits_source),
    .auto_out_a_bits_address(atomics_auto_out_a_bits_address),
    .auto_out_a_bits_mask(atomics_auto_out_a_bits_mask),
    .auto_out_a_bits_data(atomics_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(atomics_auto_out_a_bits_corrupt),
    .auto_out_d_ready(atomics_auto_out_d_ready),
    .auto_out_d_valid(atomics_auto_out_d_valid),
    .auto_out_d_bits_opcode(atomics_auto_out_d_bits_opcode),
    .auto_out_d_bits_param(atomics_auto_out_d_bits_param),
    .auto_out_d_bits_size(atomics_auto_out_d_bits_size),
    .auto_out_d_bits_source(atomics_auto_out_d_bits_source),
    .auto_out_d_bits_sink(atomics_auto_out_d_bits_sink),
    .auto_out_d_bits_denied(atomics_auto_out_d_bits_denied),
    .auto_out_d_bits_data(atomics_auto_out_d_bits_data),
    .auto_out_d_bits_corrupt(atomics_auto_out_d_bits_corrupt)
  );
  ErrorDeviceWrapper wrapped_error_device ( // @[LazyModule.scala 432:27]
    .clock(wrapped_error_device_clock),
    .reset(wrapped_error_device_reset),
    .auto_buffer_in_a_ready(wrapped_error_device_auto_buffer_in_a_ready),
    .auto_buffer_in_a_valid(wrapped_error_device_auto_buffer_in_a_valid),
    .auto_buffer_in_a_bits_opcode(wrapped_error_device_auto_buffer_in_a_bits_opcode),
    .auto_buffer_in_a_bits_param(wrapped_error_device_auto_buffer_in_a_bits_param),
    .auto_buffer_in_a_bits_size(wrapped_error_device_auto_buffer_in_a_bits_size),
    .auto_buffer_in_a_bits_source(wrapped_error_device_auto_buffer_in_a_bits_source),
    .auto_buffer_in_a_bits_address(wrapped_error_device_auto_buffer_in_a_bits_address),
    .auto_buffer_in_a_bits_mask(wrapped_error_device_auto_buffer_in_a_bits_mask),
    .auto_buffer_in_a_bits_corrupt(wrapped_error_device_auto_buffer_in_a_bits_corrupt),
    .auto_buffer_in_d_ready(wrapped_error_device_auto_buffer_in_d_ready),
    .auto_buffer_in_d_valid(wrapped_error_device_auto_buffer_in_d_valid),
    .auto_buffer_in_d_bits_opcode(wrapped_error_device_auto_buffer_in_d_bits_opcode),
    .auto_buffer_in_d_bits_param(wrapped_error_device_auto_buffer_in_d_bits_param),
    .auto_buffer_in_d_bits_size(wrapped_error_device_auto_buffer_in_d_bits_size),
    .auto_buffer_in_d_bits_source(wrapped_error_device_auto_buffer_in_d_bits_source),
    .auto_buffer_in_d_bits_sink(wrapped_error_device_auto_buffer_in_d_bits_sink),
    .auto_buffer_in_d_bits_denied(wrapped_error_device_auto_buffer_in_d_bits_denied),
    .auto_buffer_in_d_bits_data(wrapped_error_device_auto_buffer_in_d_bits_data),
    .auto_buffer_in_d_bits_corrupt(wrapped_error_device_auto_buffer_in_d_bits_corrupt)
  );
  TLBuffer_6 buffer_1 ( // @[Buffer.scala 68:28]
    .auto_in_a_ready(buffer_1_auto_in_a_ready),
    .auto_in_a_valid(buffer_1_auto_in_a_valid),
    .auto_in_a_bits_opcode(buffer_1_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(buffer_1_auto_in_a_bits_param),
    .auto_in_a_bits_size(buffer_1_auto_in_a_bits_size),
    .auto_in_a_bits_source(buffer_1_auto_in_a_bits_source),
    .auto_in_a_bits_address(buffer_1_auto_in_a_bits_address),
    .auto_in_a_bits_mask(buffer_1_auto_in_a_bits_mask),
    .auto_in_a_bits_data(buffer_1_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(buffer_1_auto_in_a_bits_corrupt),
    .auto_in_d_ready(buffer_1_auto_in_d_ready),
    .auto_in_d_valid(buffer_1_auto_in_d_valid),
    .auto_in_d_bits_opcode(buffer_1_auto_in_d_bits_opcode),
    .auto_in_d_bits_param(buffer_1_auto_in_d_bits_param),
    .auto_in_d_bits_size(buffer_1_auto_in_d_bits_size),
    .auto_in_d_bits_source(buffer_1_auto_in_d_bits_source),
    .auto_in_d_bits_sink(buffer_1_auto_in_d_bits_sink),
    .auto_in_d_bits_denied(buffer_1_auto_in_d_bits_denied),
    .auto_in_d_bits_data(buffer_1_auto_in_d_bits_data),
    .auto_in_d_bits_corrupt(buffer_1_auto_in_d_bits_corrupt),
    .auto_out_a_ready(buffer_1_auto_out_a_ready),
    .auto_out_a_valid(buffer_1_auto_out_a_valid),
    .auto_out_a_bits_opcode(buffer_1_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(buffer_1_auto_out_a_bits_param),
    .auto_out_a_bits_size(buffer_1_auto_out_a_bits_size),
    .auto_out_a_bits_source(buffer_1_auto_out_a_bits_source),
    .auto_out_a_bits_address(buffer_1_auto_out_a_bits_address),
    .auto_out_a_bits_mask(buffer_1_auto_out_a_bits_mask),
    .auto_out_a_bits_data(buffer_1_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(buffer_1_auto_out_a_bits_corrupt),
    .auto_out_d_ready(buffer_1_auto_out_d_ready),
    .auto_out_d_valid(buffer_1_auto_out_d_valid),
    .auto_out_d_bits_opcode(buffer_1_auto_out_d_bits_opcode),
    .auto_out_d_bits_param(buffer_1_auto_out_d_bits_param),
    .auto_out_d_bits_size(buffer_1_auto_out_d_bits_size),
    .auto_out_d_bits_source(buffer_1_auto_out_d_bits_source),
    .auto_out_d_bits_sink(buffer_1_auto_out_d_bits_sink),
    .auto_out_d_bits_denied(buffer_1_auto_out_d_bits_denied),
    .auto_out_d_bits_data(buffer_1_auto_out_d_bits_data),
    .auto_out_d_bits_corrupt(buffer_1_auto_out_d_bits_corrupt)
  );
  TLInterconnectCoupler_19 coupler_to_bus_named_subsystem_pbus ( // @[LazyModule.scala 432:27]
    .auto_widget_in_a_ready(coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_ready),
    .auto_widget_in_a_valid(coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_valid),
    .auto_widget_in_a_bits_opcode(coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_opcode),
    .auto_widget_in_a_bits_param(coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_param),
    .auto_widget_in_a_bits_size(coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_size),
    .auto_widget_in_a_bits_source(coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_source),
    .auto_widget_in_a_bits_address(coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_address),
    .auto_widget_in_a_bits_mask(coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_mask),
    .auto_widget_in_a_bits_data(coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_data),
    .auto_widget_in_a_bits_corrupt(coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_corrupt),
    .auto_widget_in_d_ready(coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_ready),
    .auto_widget_in_d_valid(coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_valid),
    .auto_widget_in_d_bits_opcode(coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_opcode),
    .auto_widget_in_d_bits_param(coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_param),
    .auto_widget_in_d_bits_size(coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_size),
    .auto_widget_in_d_bits_source(coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_source),
    .auto_widget_in_d_bits_sink(coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_sink),
    .auto_widget_in_d_bits_denied(coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_denied),
    .auto_widget_in_d_bits_data(coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_data),
    .auto_widget_in_d_bits_corrupt(coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_corrupt),
    .auto_bus_xing_out_a_ready(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_ready),
    .auto_bus_xing_out_a_valid(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_valid),
    .auto_bus_xing_out_a_bits_opcode(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_opcode),
    .auto_bus_xing_out_a_bits_param(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_param),
    .auto_bus_xing_out_a_bits_size(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_size),
    .auto_bus_xing_out_a_bits_source(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_source),
    .auto_bus_xing_out_a_bits_address(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_address),
    .auto_bus_xing_out_a_bits_mask(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_mask),
    .auto_bus_xing_out_a_bits_data(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_data),
    .auto_bus_xing_out_a_bits_corrupt(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_corrupt),
    .auto_bus_xing_out_d_ready(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_ready),
    .auto_bus_xing_out_d_valid(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_valid),
    .auto_bus_xing_out_d_bits_opcode(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_opcode),
    .auto_bus_xing_out_d_bits_param(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_param),
    .auto_bus_xing_out_d_bits_size(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_size),
    .auto_bus_xing_out_d_bits_source(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_source),
    .auto_bus_xing_out_d_bits_sink(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_sink),
    .auto_bus_xing_out_d_bits_denied(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_denied),
    .auto_bus_xing_out_d_bits_data(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_data),
    .auto_bus_xing_out_d_bits_corrupt(coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_corrupt)
  );
  TLInterconnectCoupler_20 coupler_to_plic ( // @[LazyModule.scala 432:27]
    .clock(coupler_to_plic_clock),
    .reset(coupler_to_plic_reset),
    .auto_fragmenter_out_a_ready(coupler_to_plic_auto_fragmenter_out_a_ready),
    .auto_fragmenter_out_a_valid(coupler_to_plic_auto_fragmenter_out_a_valid),
    .auto_fragmenter_out_a_bits_opcode(coupler_to_plic_auto_fragmenter_out_a_bits_opcode),
    .auto_fragmenter_out_a_bits_param(coupler_to_plic_auto_fragmenter_out_a_bits_param),
    .auto_fragmenter_out_a_bits_size(coupler_to_plic_auto_fragmenter_out_a_bits_size),
    .auto_fragmenter_out_a_bits_source(coupler_to_plic_auto_fragmenter_out_a_bits_source),
    .auto_fragmenter_out_a_bits_address(coupler_to_plic_auto_fragmenter_out_a_bits_address),
    .auto_fragmenter_out_a_bits_mask(coupler_to_plic_auto_fragmenter_out_a_bits_mask),
    .auto_fragmenter_out_a_bits_data(coupler_to_plic_auto_fragmenter_out_a_bits_data),
    .auto_fragmenter_out_a_bits_corrupt(coupler_to_plic_auto_fragmenter_out_a_bits_corrupt),
    .auto_fragmenter_out_d_ready(coupler_to_plic_auto_fragmenter_out_d_ready),
    .auto_fragmenter_out_d_valid(coupler_to_plic_auto_fragmenter_out_d_valid),
    .auto_fragmenter_out_d_bits_opcode(coupler_to_plic_auto_fragmenter_out_d_bits_opcode),
    .auto_fragmenter_out_d_bits_size(coupler_to_plic_auto_fragmenter_out_d_bits_size),
    .auto_fragmenter_out_d_bits_source(coupler_to_plic_auto_fragmenter_out_d_bits_source),
    .auto_fragmenter_out_d_bits_data(coupler_to_plic_auto_fragmenter_out_d_bits_data),
    .auto_tl_in_a_ready(coupler_to_plic_auto_tl_in_a_ready),
    .auto_tl_in_a_valid(coupler_to_plic_auto_tl_in_a_valid),
    .auto_tl_in_a_bits_opcode(coupler_to_plic_auto_tl_in_a_bits_opcode),
    .auto_tl_in_a_bits_param(coupler_to_plic_auto_tl_in_a_bits_param),
    .auto_tl_in_a_bits_size(coupler_to_plic_auto_tl_in_a_bits_size),
    .auto_tl_in_a_bits_source(coupler_to_plic_auto_tl_in_a_bits_source),
    .auto_tl_in_a_bits_address(coupler_to_plic_auto_tl_in_a_bits_address),
    .auto_tl_in_a_bits_mask(coupler_to_plic_auto_tl_in_a_bits_mask),
    .auto_tl_in_a_bits_data(coupler_to_plic_auto_tl_in_a_bits_data),
    .auto_tl_in_a_bits_corrupt(coupler_to_plic_auto_tl_in_a_bits_corrupt),
    .auto_tl_in_d_ready(coupler_to_plic_auto_tl_in_d_ready),
    .auto_tl_in_d_valid(coupler_to_plic_auto_tl_in_d_valid),
    .auto_tl_in_d_bits_opcode(coupler_to_plic_auto_tl_in_d_bits_opcode),
    .auto_tl_in_d_bits_size(coupler_to_plic_auto_tl_in_d_bits_size),
    .auto_tl_in_d_bits_source(coupler_to_plic_auto_tl_in_d_bits_source),
    .auto_tl_in_d_bits_data(coupler_to_plic_auto_tl_in_d_bits_data)
  );
  TLInterconnectCoupler_21 coupler_to_clint ( // @[LazyModule.scala 432:27]
    .clock(coupler_to_clint_clock),
    .reset(coupler_to_clint_reset),
    .auto_fragmenter_out_a_ready(coupler_to_clint_auto_fragmenter_out_a_ready),
    .auto_fragmenter_out_a_valid(coupler_to_clint_auto_fragmenter_out_a_valid),
    .auto_fragmenter_out_a_bits_opcode(coupler_to_clint_auto_fragmenter_out_a_bits_opcode),
    .auto_fragmenter_out_a_bits_param(coupler_to_clint_auto_fragmenter_out_a_bits_param),
    .auto_fragmenter_out_a_bits_size(coupler_to_clint_auto_fragmenter_out_a_bits_size),
    .auto_fragmenter_out_a_bits_source(coupler_to_clint_auto_fragmenter_out_a_bits_source),
    .auto_fragmenter_out_a_bits_address(coupler_to_clint_auto_fragmenter_out_a_bits_address),
    .auto_fragmenter_out_a_bits_mask(coupler_to_clint_auto_fragmenter_out_a_bits_mask),
    .auto_fragmenter_out_a_bits_data(coupler_to_clint_auto_fragmenter_out_a_bits_data),
    .auto_fragmenter_out_a_bits_corrupt(coupler_to_clint_auto_fragmenter_out_a_bits_corrupt),
    .auto_fragmenter_out_d_ready(coupler_to_clint_auto_fragmenter_out_d_ready),
    .auto_fragmenter_out_d_valid(coupler_to_clint_auto_fragmenter_out_d_valid),
    .auto_fragmenter_out_d_bits_opcode(coupler_to_clint_auto_fragmenter_out_d_bits_opcode),
    .auto_fragmenter_out_d_bits_size(coupler_to_clint_auto_fragmenter_out_d_bits_size),
    .auto_fragmenter_out_d_bits_source(coupler_to_clint_auto_fragmenter_out_d_bits_source),
    .auto_fragmenter_out_d_bits_data(coupler_to_clint_auto_fragmenter_out_d_bits_data),
    .auto_tl_in_a_ready(coupler_to_clint_auto_tl_in_a_ready),
    .auto_tl_in_a_valid(coupler_to_clint_auto_tl_in_a_valid),
    .auto_tl_in_a_bits_opcode(coupler_to_clint_auto_tl_in_a_bits_opcode),
    .auto_tl_in_a_bits_param(coupler_to_clint_auto_tl_in_a_bits_param),
    .auto_tl_in_a_bits_size(coupler_to_clint_auto_tl_in_a_bits_size),
    .auto_tl_in_a_bits_source(coupler_to_clint_auto_tl_in_a_bits_source),
    .auto_tl_in_a_bits_address(coupler_to_clint_auto_tl_in_a_bits_address),
    .auto_tl_in_a_bits_mask(coupler_to_clint_auto_tl_in_a_bits_mask),
    .auto_tl_in_a_bits_data(coupler_to_clint_auto_tl_in_a_bits_data),
    .auto_tl_in_a_bits_corrupt(coupler_to_clint_auto_tl_in_a_bits_corrupt),
    .auto_tl_in_d_ready(coupler_to_clint_auto_tl_in_d_ready),
    .auto_tl_in_d_valid(coupler_to_clint_auto_tl_in_d_valid),
    .auto_tl_in_d_bits_opcode(coupler_to_clint_auto_tl_in_d_bits_opcode),
    .auto_tl_in_d_bits_size(coupler_to_clint_auto_tl_in_d_bits_size),
    .auto_tl_in_d_bits_source(coupler_to_clint_auto_tl_in_d_bits_source),
    .auto_tl_in_d_bits_data(coupler_to_clint_auto_tl_in_d_bits_data)
  );
  TLInterconnectCoupler_22 coupler_to_debug ( // @[LazyModule.scala 432:27]
    .clock(coupler_to_debug_clock),
    .reset(coupler_to_debug_reset),
    .auto_fragmenter_out_a_ready(coupler_to_debug_auto_fragmenter_out_a_ready),
    .auto_fragmenter_out_a_valid(coupler_to_debug_auto_fragmenter_out_a_valid),
    .auto_fragmenter_out_a_bits_opcode(coupler_to_debug_auto_fragmenter_out_a_bits_opcode),
    .auto_fragmenter_out_a_bits_param(coupler_to_debug_auto_fragmenter_out_a_bits_param),
    .auto_fragmenter_out_a_bits_size(coupler_to_debug_auto_fragmenter_out_a_bits_size),
    .auto_fragmenter_out_a_bits_source(coupler_to_debug_auto_fragmenter_out_a_bits_source),
    .auto_fragmenter_out_a_bits_address(coupler_to_debug_auto_fragmenter_out_a_bits_address),
    .auto_fragmenter_out_a_bits_mask(coupler_to_debug_auto_fragmenter_out_a_bits_mask),
    .auto_fragmenter_out_a_bits_data(coupler_to_debug_auto_fragmenter_out_a_bits_data),
    .auto_fragmenter_out_a_bits_corrupt(coupler_to_debug_auto_fragmenter_out_a_bits_corrupt),
    .auto_fragmenter_out_d_ready(coupler_to_debug_auto_fragmenter_out_d_ready),
    .auto_fragmenter_out_d_valid(coupler_to_debug_auto_fragmenter_out_d_valid),
    .auto_fragmenter_out_d_bits_opcode(coupler_to_debug_auto_fragmenter_out_d_bits_opcode),
    .auto_fragmenter_out_d_bits_size(coupler_to_debug_auto_fragmenter_out_d_bits_size),
    .auto_fragmenter_out_d_bits_source(coupler_to_debug_auto_fragmenter_out_d_bits_source),
    .auto_fragmenter_out_d_bits_data(coupler_to_debug_auto_fragmenter_out_d_bits_data),
    .auto_tl_in_a_ready(coupler_to_debug_auto_tl_in_a_ready),
    .auto_tl_in_a_valid(coupler_to_debug_auto_tl_in_a_valid),
    .auto_tl_in_a_bits_opcode(coupler_to_debug_auto_tl_in_a_bits_opcode),
    .auto_tl_in_a_bits_param(coupler_to_debug_auto_tl_in_a_bits_param),
    .auto_tl_in_a_bits_size(coupler_to_debug_auto_tl_in_a_bits_size),
    .auto_tl_in_a_bits_source(coupler_to_debug_auto_tl_in_a_bits_source),
    .auto_tl_in_a_bits_address(coupler_to_debug_auto_tl_in_a_bits_address),
    .auto_tl_in_a_bits_mask(coupler_to_debug_auto_tl_in_a_bits_mask),
    .auto_tl_in_a_bits_data(coupler_to_debug_auto_tl_in_a_bits_data),
    .auto_tl_in_a_bits_corrupt(coupler_to_debug_auto_tl_in_a_bits_corrupt),
    .auto_tl_in_d_ready(coupler_to_debug_auto_tl_in_d_ready),
    .auto_tl_in_d_valid(coupler_to_debug_auto_tl_in_d_valid),
    .auto_tl_in_d_bits_opcode(coupler_to_debug_auto_tl_in_d_bits_opcode),
    .auto_tl_in_d_bits_size(coupler_to_debug_auto_tl_in_d_bits_size),
    .auto_tl_in_d_bits_source(coupler_to_debug_auto_tl_in_d_bits_source),
    .auto_tl_in_d_bits_data(coupler_to_debug_auto_tl_in_d_bits_data)
  );
  TLInterconnectCoupler_23 coupler_to_tile ( // @[LazyModule.scala 432:27]
    .auto_tl_slave_clock_xing_out_a_ready(coupler_to_tile_auto_tl_slave_clock_xing_out_a_ready),
    .auto_tl_slave_clock_xing_out_a_valid(coupler_to_tile_auto_tl_slave_clock_xing_out_a_valid),
    .auto_tl_slave_clock_xing_out_a_bits_opcode(coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_opcode),
    .auto_tl_slave_clock_xing_out_a_bits_param(coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_param),
    .auto_tl_slave_clock_xing_out_a_bits_size(coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_size),
    .auto_tl_slave_clock_xing_out_a_bits_source(coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_source),
    .auto_tl_slave_clock_xing_out_a_bits_address(coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_address),
    .auto_tl_slave_clock_xing_out_a_bits_mask(coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_mask),
    .auto_tl_slave_clock_xing_out_a_bits_data(coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_data),
    .auto_tl_slave_clock_xing_out_a_bits_corrupt(coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_corrupt),
    .auto_tl_slave_clock_xing_out_d_ready(coupler_to_tile_auto_tl_slave_clock_xing_out_d_ready),
    .auto_tl_slave_clock_xing_out_d_valid(coupler_to_tile_auto_tl_slave_clock_xing_out_d_valid),
    .auto_tl_slave_clock_xing_out_d_bits_opcode(coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_opcode),
    .auto_tl_slave_clock_xing_out_d_bits_param(coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_param),
    .auto_tl_slave_clock_xing_out_d_bits_size(coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_size),
    .auto_tl_slave_clock_xing_out_d_bits_source(coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_source),
    .auto_tl_slave_clock_xing_out_d_bits_sink(coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_sink),
    .auto_tl_slave_clock_xing_out_d_bits_denied(coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_denied),
    .auto_tl_slave_clock_xing_out_d_bits_data(coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_data),
    .auto_tl_slave_clock_xing_out_d_bits_corrupt(coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_corrupt),
    .auto_tl_in_a_ready(coupler_to_tile_auto_tl_in_a_ready),
    .auto_tl_in_a_valid(coupler_to_tile_auto_tl_in_a_valid),
    .auto_tl_in_a_bits_opcode(coupler_to_tile_auto_tl_in_a_bits_opcode),
    .auto_tl_in_a_bits_param(coupler_to_tile_auto_tl_in_a_bits_param),
    .auto_tl_in_a_bits_size(coupler_to_tile_auto_tl_in_a_bits_size),
    .auto_tl_in_a_bits_source(coupler_to_tile_auto_tl_in_a_bits_source),
    .auto_tl_in_a_bits_address(coupler_to_tile_auto_tl_in_a_bits_address),
    .auto_tl_in_a_bits_mask(coupler_to_tile_auto_tl_in_a_bits_mask),
    .auto_tl_in_a_bits_data(coupler_to_tile_auto_tl_in_a_bits_data),
    .auto_tl_in_a_bits_corrupt(coupler_to_tile_auto_tl_in_a_bits_corrupt),
    .auto_tl_in_d_ready(coupler_to_tile_auto_tl_in_d_ready),
    .auto_tl_in_d_valid(coupler_to_tile_auto_tl_in_d_valid),
    .auto_tl_in_d_bits_opcode(coupler_to_tile_auto_tl_in_d_bits_opcode),
    .auto_tl_in_d_bits_param(coupler_to_tile_auto_tl_in_d_bits_param),
    .auto_tl_in_d_bits_size(coupler_to_tile_auto_tl_in_d_bits_size),
    .auto_tl_in_d_bits_source(coupler_to_tile_auto_tl_in_d_bits_source),
    .auto_tl_in_d_bits_sink(coupler_to_tile_auto_tl_in_d_bits_sink),
    .auto_tl_in_d_bits_denied(coupler_to_tile_auto_tl_in_d_bits_denied),
    .auto_tl_in_d_bits_data(coupler_to_tile_auto_tl_in_d_bits_data),
    .auto_tl_in_d_bits_corrupt(coupler_to_tile_auto_tl_in_d_bits_corrupt)
  );
  TLInterconnectCoupler_24 coupler_to_aon ( // @[LazyModule.scala 432:27]
    .clock(coupler_to_aon_clock),
    .reset(coupler_to_aon_reset),
    .auto_asource_out_a_mem_0_opcode(coupler_to_aon_auto_asource_out_a_mem_0_opcode),
    .auto_asource_out_a_mem_0_param(coupler_to_aon_auto_asource_out_a_mem_0_param),
    .auto_asource_out_a_mem_0_size(coupler_to_aon_auto_asource_out_a_mem_0_size),
    .auto_asource_out_a_mem_0_source(coupler_to_aon_auto_asource_out_a_mem_0_source),
    .auto_asource_out_a_mem_0_address(coupler_to_aon_auto_asource_out_a_mem_0_address),
    .auto_asource_out_a_mem_0_mask(coupler_to_aon_auto_asource_out_a_mem_0_mask),
    .auto_asource_out_a_mem_0_data(coupler_to_aon_auto_asource_out_a_mem_0_data),
    .auto_asource_out_a_mem_0_corrupt(coupler_to_aon_auto_asource_out_a_mem_0_corrupt),
    .auto_asource_out_a_ridx(coupler_to_aon_auto_asource_out_a_ridx),
    .auto_asource_out_a_widx(coupler_to_aon_auto_asource_out_a_widx),
    .auto_asource_out_a_safe_ridx_valid(coupler_to_aon_auto_asource_out_a_safe_ridx_valid),
    .auto_asource_out_a_safe_widx_valid(coupler_to_aon_auto_asource_out_a_safe_widx_valid),
    .auto_asource_out_a_safe_source_reset_n(coupler_to_aon_auto_asource_out_a_safe_source_reset_n),
    .auto_asource_out_a_safe_sink_reset_n(coupler_to_aon_auto_asource_out_a_safe_sink_reset_n),
    .auto_asource_out_d_mem_0_opcode(coupler_to_aon_auto_asource_out_d_mem_0_opcode),
    .auto_asource_out_d_mem_0_param(coupler_to_aon_auto_asource_out_d_mem_0_param),
    .auto_asource_out_d_mem_0_size(coupler_to_aon_auto_asource_out_d_mem_0_size),
    .auto_asource_out_d_mem_0_source(coupler_to_aon_auto_asource_out_d_mem_0_source),
    .auto_asource_out_d_mem_0_sink(coupler_to_aon_auto_asource_out_d_mem_0_sink),
    .auto_asource_out_d_mem_0_denied(coupler_to_aon_auto_asource_out_d_mem_0_denied),
    .auto_asource_out_d_mem_0_data(coupler_to_aon_auto_asource_out_d_mem_0_data),
    .auto_asource_out_d_mem_0_corrupt(coupler_to_aon_auto_asource_out_d_mem_0_corrupt),
    .auto_asource_out_d_ridx(coupler_to_aon_auto_asource_out_d_ridx),
    .auto_asource_out_d_widx(coupler_to_aon_auto_asource_out_d_widx),
    .auto_asource_out_d_safe_ridx_valid(coupler_to_aon_auto_asource_out_d_safe_ridx_valid),
    .auto_asource_out_d_safe_widx_valid(coupler_to_aon_auto_asource_out_d_safe_widx_valid),
    .auto_asource_out_d_safe_source_reset_n(coupler_to_aon_auto_asource_out_d_safe_source_reset_n),
    .auto_asource_out_d_safe_sink_reset_n(coupler_to_aon_auto_asource_out_d_safe_sink_reset_n),
    .auto_tl_in_a_ready(coupler_to_aon_auto_tl_in_a_ready),
    .auto_tl_in_a_valid(coupler_to_aon_auto_tl_in_a_valid),
    .auto_tl_in_a_bits_opcode(coupler_to_aon_auto_tl_in_a_bits_opcode),
    .auto_tl_in_a_bits_param(coupler_to_aon_auto_tl_in_a_bits_param),
    .auto_tl_in_a_bits_size(coupler_to_aon_auto_tl_in_a_bits_size),
    .auto_tl_in_a_bits_source(coupler_to_aon_auto_tl_in_a_bits_source),
    .auto_tl_in_a_bits_address(coupler_to_aon_auto_tl_in_a_bits_address),
    .auto_tl_in_a_bits_mask(coupler_to_aon_auto_tl_in_a_bits_mask),
    .auto_tl_in_a_bits_data(coupler_to_aon_auto_tl_in_a_bits_data),
    .auto_tl_in_a_bits_corrupt(coupler_to_aon_auto_tl_in_a_bits_corrupt),
    .auto_tl_in_d_ready(coupler_to_aon_auto_tl_in_d_ready),
    .auto_tl_in_d_valid(coupler_to_aon_auto_tl_in_d_valid),
    .auto_tl_in_d_bits_opcode(coupler_to_aon_auto_tl_in_d_bits_opcode),
    .auto_tl_in_d_bits_param(coupler_to_aon_auto_tl_in_d_bits_param),
    .auto_tl_in_d_bits_size(coupler_to_aon_auto_tl_in_d_bits_size),
    .auto_tl_in_d_bits_source(coupler_to_aon_auto_tl_in_d_bits_source),
    .auto_tl_in_d_bits_sink(coupler_to_aon_auto_tl_in_d_bits_sink),
    .auto_tl_in_d_bits_denied(coupler_to_aon_auto_tl_in_d_bits_denied),
    .auto_tl_in_d_bits_data(coupler_to_aon_auto_tl_in_d_bits_data),
    .auto_tl_in_d_bits_corrupt(coupler_to_aon_auto_tl_in_d_bits_corrupt)
  );
  TLInterconnectCoupler_25 coupler_to_bootrom ( // @[LazyModule.scala 432:27]
    .clock(coupler_to_bootrom_clock),
    .reset(coupler_to_bootrom_reset),
    .auto_fragmenter_out_a_ready(coupler_to_bootrom_auto_fragmenter_out_a_ready),
    .auto_fragmenter_out_a_valid(coupler_to_bootrom_auto_fragmenter_out_a_valid),
    .auto_fragmenter_out_a_bits_opcode(coupler_to_bootrom_auto_fragmenter_out_a_bits_opcode),
    .auto_fragmenter_out_a_bits_param(coupler_to_bootrom_auto_fragmenter_out_a_bits_param),
    .auto_fragmenter_out_a_bits_size(coupler_to_bootrom_auto_fragmenter_out_a_bits_size),
    .auto_fragmenter_out_a_bits_source(coupler_to_bootrom_auto_fragmenter_out_a_bits_source),
    .auto_fragmenter_out_a_bits_address(coupler_to_bootrom_auto_fragmenter_out_a_bits_address),
    .auto_fragmenter_out_a_bits_mask(coupler_to_bootrom_auto_fragmenter_out_a_bits_mask),
    .auto_fragmenter_out_a_bits_corrupt(coupler_to_bootrom_auto_fragmenter_out_a_bits_corrupt),
    .auto_fragmenter_out_d_ready(coupler_to_bootrom_auto_fragmenter_out_d_ready),
    .auto_fragmenter_out_d_valid(coupler_to_bootrom_auto_fragmenter_out_d_valid),
    .auto_fragmenter_out_d_bits_size(coupler_to_bootrom_auto_fragmenter_out_d_bits_size),
    .auto_fragmenter_out_d_bits_source(coupler_to_bootrom_auto_fragmenter_out_d_bits_source),
    .auto_fragmenter_out_d_bits_data(coupler_to_bootrom_auto_fragmenter_out_d_bits_data),
    .auto_tl_in_a_ready(coupler_to_bootrom_auto_tl_in_a_ready),
    .auto_tl_in_a_valid(coupler_to_bootrom_auto_tl_in_a_valid),
    .auto_tl_in_a_bits_opcode(coupler_to_bootrom_auto_tl_in_a_bits_opcode),
    .auto_tl_in_a_bits_param(coupler_to_bootrom_auto_tl_in_a_bits_param),
    .auto_tl_in_a_bits_size(coupler_to_bootrom_auto_tl_in_a_bits_size),
    .auto_tl_in_a_bits_source(coupler_to_bootrom_auto_tl_in_a_bits_source),
    .auto_tl_in_a_bits_address(coupler_to_bootrom_auto_tl_in_a_bits_address),
    .auto_tl_in_a_bits_mask(coupler_to_bootrom_auto_tl_in_a_bits_mask),
    .auto_tl_in_a_bits_corrupt(coupler_to_bootrom_auto_tl_in_a_bits_corrupt),
    .auto_tl_in_d_ready(coupler_to_bootrom_auto_tl_in_d_ready),
    .auto_tl_in_d_valid(coupler_to_bootrom_auto_tl_in_d_valid),
    .auto_tl_in_d_bits_size(coupler_to_bootrom_auto_tl_in_d_bits_size),
    .auto_tl_in_d_bits_source(coupler_to_bootrom_auto_tl_in_d_bits_source),
    .auto_tl_in_d_bits_data(coupler_to_bootrom_auto_tl_in_d_bits_data)
  );
  assign auto_coupler_to_bootrom_fragmenter_out_a_valid = coupler_to_bootrom_auto_fragmenter_out_a_valid; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bootrom_fragmenter_out_a_bits_opcode = coupler_to_bootrom_auto_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bootrom_fragmenter_out_a_bits_param = coupler_to_bootrom_auto_fragmenter_out_a_bits_param; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bootrom_fragmenter_out_a_bits_size = coupler_to_bootrom_auto_fragmenter_out_a_bits_size; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bootrom_fragmenter_out_a_bits_source = coupler_to_bootrom_auto_fragmenter_out_a_bits_source; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bootrom_fragmenter_out_a_bits_address = coupler_to_bootrom_auto_fragmenter_out_a_bits_address; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bootrom_fragmenter_out_a_bits_mask = coupler_to_bootrom_auto_fragmenter_out_a_bits_mask; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bootrom_fragmenter_out_a_bits_corrupt = coupler_to_bootrom_auto_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bootrom_fragmenter_out_d_ready = coupler_to_bootrom_auto_fragmenter_out_d_ready; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_aon_asource_out_a_mem_0_opcode = coupler_to_aon_auto_asource_out_a_mem_0_opcode; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_aon_asource_out_a_mem_0_param = coupler_to_aon_auto_asource_out_a_mem_0_param; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_aon_asource_out_a_mem_0_size = coupler_to_aon_auto_asource_out_a_mem_0_size; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_aon_asource_out_a_mem_0_source = coupler_to_aon_auto_asource_out_a_mem_0_source; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_aon_asource_out_a_mem_0_address = coupler_to_aon_auto_asource_out_a_mem_0_address; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_aon_asource_out_a_mem_0_mask = coupler_to_aon_auto_asource_out_a_mem_0_mask; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_aon_asource_out_a_mem_0_data = coupler_to_aon_auto_asource_out_a_mem_0_data; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_aon_asource_out_a_mem_0_corrupt = coupler_to_aon_auto_asource_out_a_mem_0_corrupt; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_aon_asource_out_a_widx = coupler_to_aon_auto_asource_out_a_widx; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_aon_asource_out_a_safe_widx_valid = coupler_to_aon_auto_asource_out_a_safe_widx_valid; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_aon_asource_out_a_safe_source_reset_n = coupler_to_aon_auto_asource_out_a_safe_source_reset_n; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_aon_asource_out_d_ridx = coupler_to_aon_auto_asource_out_d_ridx; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_aon_asource_out_d_safe_ridx_valid = coupler_to_aon_auto_asource_out_d_safe_ridx_valid; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_aon_asource_out_d_safe_sink_reset_n = coupler_to_aon_auto_asource_out_d_safe_sink_reset_n; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_tile_tl_slave_clock_xing_out_a_valid = coupler_to_tile_auto_tl_slave_clock_xing_out_a_valid; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_opcode =
    coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_opcode; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_param =
    coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_param; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_size =
    coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_size; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_source =
    coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_source; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_address =
    coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_address; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_mask =
    coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_mask; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_data =
    coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_data; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_corrupt =
    coupler_to_tile_auto_tl_slave_clock_xing_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_tile_tl_slave_clock_xing_out_d_ready = coupler_to_tile_auto_tl_slave_clock_xing_out_d_ready; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_debug_fragmenter_out_a_valid = coupler_to_debug_auto_fragmenter_out_a_valid; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_debug_fragmenter_out_a_bits_opcode = coupler_to_debug_auto_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_debug_fragmenter_out_a_bits_param = coupler_to_debug_auto_fragmenter_out_a_bits_param; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_debug_fragmenter_out_a_bits_size = coupler_to_debug_auto_fragmenter_out_a_bits_size; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_debug_fragmenter_out_a_bits_source = coupler_to_debug_auto_fragmenter_out_a_bits_source; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_debug_fragmenter_out_a_bits_address = coupler_to_debug_auto_fragmenter_out_a_bits_address; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_debug_fragmenter_out_a_bits_mask = coupler_to_debug_auto_fragmenter_out_a_bits_mask; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_debug_fragmenter_out_a_bits_data = coupler_to_debug_auto_fragmenter_out_a_bits_data; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_debug_fragmenter_out_a_bits_corrupt = coupler_to_debug_auto_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_debug_fragmenter_out_d_ready = coupler_to_debug_auto_fragmenter_out_d_ready; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_clint_fragmenter_out_a_valid = coupler_to_clint_auto_fragmenter_out_a_valid; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_clint_fragmenter_out_a_bits_opcode = coupler_to_clint_auto_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_clint_fragmenter_out_a_bits_param = coupler_to_clint_auto_fragmenter_out_a_bits_param; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_clint_fragmenter_out_a_bits_size = coupler_to_clint_auto_fragmenter_out_a_bits_size; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_clint_fragmenter_out_a_bits_source = coupler_to_clint_auto_fragmenter_out_a_bits_source; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_clint_fragmenter_out_a_bits_address = coupler_to_clint_auto_fragmenter_out_a_bits_address; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_clint_fragmenter_out_a_bits_mask = coupler_to_clint_auto_fragmenter_out_a_bits_mask; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_clint_fragmenter_out_a_bits_data = coupler_to_clint_auto_fragmenter_out_a_bits_data; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_clint_fragmenter_out_a_bits_corrupt = coupler_to_clint_auto_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_clint_fragmenter_out_d_ready = coupler_to_clint_auto_fragmenter_out_d_ready; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_plic_fragmenter_out_a_valid = coupler_to_plic_auto_fragmenter_out_a_valid; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_plic_fragmenter_out_a_bits_opcode = coupler_to_plic_auto_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_plic_fragmenter_out_a_bits_param = coupler_to_plic_auto_fragmenter_out_a_bits_param; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_plic_fragmenter_out_a_bits_size = coupler_to_plic_auto_fragmenter_out_a_bits_size; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_plic_fragmenter_out_a_bits_source = coupler_to_plic_auto_fragmenter_out_a_bits_source; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_plic_fragmenter_out_a_bits_address = coupler_to_plic_auto_fragmenter_out_a_bits_address; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_plic_fragmenter_out_a_bits_mask = coupler_to_plic_auto_fragmenter_out_a_bits_mask; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_plic_fragmenter_out_a_bits_data = coupler_to_plic_auto_fragmenter_out_a_bits_data; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_plic_fragmenter_out_a_bits_corrupt = coupler_to_plic_auto_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_plic_fragmenter_out_d_ready = coupler_to_plic_auto_fragmenter_out_d_ready; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_valid =
    coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_valid; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_opcode =
    coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_opcode; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_param =
    coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_param; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_size =
    coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_size; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_source =
    coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_source; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_address =
    coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_address; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_mask =
    coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_mask; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_data =
    coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_data; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_corrupt =
    coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_ready =
    coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_ready; // @[LazyModule.scala 311:12]
  assign auto_fixedClockNode_out_2_clock = fixedClockNode_auto_out_3_clock; // @[LazyModule.scala 311:12]
  assign auto_fixedClockNode_out_2_reset = fixedClockNode_auto_out_3_reset; // @[LazyModule.scala 311:12]
  assign auto_fixedClockNode_out_0_clock = fixedClockNode_auto_out_1_clock; // @[LazyModule.scala 311:12]
  assign auto_fixedClockNode_out_0_reset = fixedClockNode_auto_out_1_reset; // @[LazyModule.scala 311:12]
  assign auto_subsystem_cbus_clock_groups_out_member_subsystem_pbus_0_clock =
    subsystem_cbus_clock_groups_auto_out_1_member_subsystem_pbus_0_clock; // @[LazyModule.scala 311:12]
  assign auto_subsystem_cbus_clock_groups_out_member_subsystem_pbus_0_reset =
    subsystem_cbus_clock_groups_auto_out_1_member_subsystem_pbus_0_reset; // @[LazyModule.scala 311:12]
  assign auto_bus_xing_in_a_ready = buffer_1_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_bus_xing_in_d_valid = buffer_1_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_bus_xing_in_d_bits_opcode = buffer_1_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_bus_xing_in_d_bits_param = buffer_1_auto_in_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_bus_xing_in_d_bits_size = buffer_1_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_bus_xing_in_d_bits_source = buffer_1_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_bus_xing_in_d_bits_sink = buffer_1_auto_in_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_bus_xing_in_d_bits_denied = buffer_1_auto_in_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_bus_xing_in_d_bits_data = buffer_1_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_bus_xing_in_d_bits_corrupt = buffer_1_auto_in_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign subsystem_cbus_clock_groups_auto_in_member_subsystem_cbus_1_clock =
    auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_1_clock; // @[LazyModule.scala 309:16]
  assign subsystem_cbus_clock_groups_auto_in_member_subsystem_cbus_1_reset =
    auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_1_reset; // @[LazyModule.scala 309:16]
  assign subsystem_cbus_clock_groups_auto_in_member_subsystem_cbus_0_clock =
    auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_0_clock; // @[LazyModule.scala 309:16]
  assign subsystem_cbus_clock_groups_auto_in_member_subsystem_cbus_0_reset =
    auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_0_reset; // @[LazyModule.scala 309:16]
  assign clockGroup_auto_in_member_subsystem_cbus_0_clock =
    subsystem_cbus_clock_groups_auto_out_0_member_subsystem_cbus_0_clock; // @[LazyModule.scala 298:16]
  assign clockGroup_auto_in_member_subsystem_cbus_0_reset =
    subsystem_cbus_clock_groups_auto_out_0_member_subsystem_cbus_0_reset; // @[LazyModule.scala 298:16]
  assign fixedClockNode_auto_in_clock = clockGroup_auto_out_clock; // @[LazyModule.scala 298:16]
  assign fixedClockNode_auto_in_reset = clockGroup_auto_out_reset; // @[LazyModule.scala 298:16]
  assign fixer_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign fixer_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign fixer_auto_in_a_valid = buffer_auto_out_a_valid; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_param = buffer_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_size = buffer_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_source = buffer_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_address = buffer_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_data = buffer_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_d_ready = buffer_auto_out_d_ready; // @[LazyModule.scala 296:16]
  assign fixer_auto_out_a_ready = out_xbar_auto_in_a_ready; // @[LazyModule.scala 298:16]
  assign fixer_auto_out_d_valid = out_xbar_auto_in_d_valid; // @[LazyModule.scala 298:16]
  assign fixer_auto_out_d_bits_opcode = out_xbar_auto_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign fixer_auto_out_d_bits_param = out_xbar_auto_in_d_bits_param; // @[LazyModule.scala 298:16]
  assign fixer_auto_out_d_bits_size = out_xbar_auto_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign fixer_auto_out_d_bits_source = out_xbar_auto_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign fixer_auto_out_d_bits_sink = out_xbar_auto_in_d_bits_sink; // @[LazyModule.scala 298:16]
  assign fixer_auto_out_d_bits_denied = out_xbar_auto_in_d_bits_denied; // @[LazyModule.scala 298:16]
  assign fixer_auto_out_d_bits_data = out_xbar_auto_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign fixer_auto_out_d_bits_corrupt = out_xbar_auto_in_d_bits_corrupt; // @[LazyModule.scala 298:16]
  assign in_xbar_auto_in_a_valid = buffer_1_auto_out_a_valid; // @[LazyModule.scala 296:16]
  assign in_xbar_auto_in_a_bits_opcode = buffer_1_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign in_xbar_auto_in_a_bits_param = buffer_1_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
  assign in_xbar_auto_in_a_bits_size = buffer_1_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign in_xbar_auto_in_a_bits_source = buffer_1_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign in_xbar_auto_in_a_bits_address = buffer_1_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign in_xbar_auto_in_a_bits_mask = buffer_1_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign in_xbar_auto_in_a_bits_data = buffer_1_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign in_xbar_auto_in_a_bits_corrupt = buffer_1_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
  assign in_xbar_auto_in_d_ready = buffer_1_auto_out_d_ready; // @[LazyModule.scala 296:16]
  assign in_xbar_auto_out_a_ready = atomics_auto_in_a_ready; // @[LazyModule.scala 298:16]
  assign in_xbar_auto_out_d_valid = atomics_auto_in_d_valid; // @[LazyModule.scala 298:16]
  assign in_xbar_auto_out_d_bits_opcode = atomics_auto_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign in_xbar_auto_out_d_bits_param = atomics_auto_in_d_bits_param; // @[LazyModule.scala 298:16]
  assign in_xbar_auto_out_d_bits_size = atomics_auto_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign in_xbar_auto_out_d_bits_source = atomics_auto_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign in_xbar_auto_out_d_bits_sink = atomics_auto_in_d_bits_sink; // @[LazyModule.scala 298:16]
  assign in_xbar_auto_out_d_bits_denied = atomics_auto_in_d_bits_denied; // @[LazyModule.scala 298:16]
  assign in_xbar_auto_out_d_bits_data = atomics_auto_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign in_xbar_auto_out_d_bits_corrupt = atomics_auto_in_d_bits_corrupt; // @[LazyModule.scala 298:16]
  assign out_xbar_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign out_xbar_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign out_xbar_auto_in_a_valid = fixer_auto_out_a_valid; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_in_a_bits_opcode = fixer_auto_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_in_a_bits_param = fixer_auto_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_in_a_bits_size = fixer_auto_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_in_a_bits_source = fixer_auto_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_in_a_bits_address = fixer_auto_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_in_a_bits_mask = fixer_auto_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_in_a_bits_data = fixer_auto_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_in_a_bits_corrupt = fixer_auto_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_in_d_ready = fixer_auto_out_d_ready; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_7_a_ready = coupler_to_bootrom_auto_tl_in_a_ready; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_7_d_valid = coupler_to_bootrom_auto_tl_in_d_valid; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_7_d_bits_size = coupler_to_bootrom_auto_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_7_d_bits_source = coupler_to_bootrom_auto_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_7_d_bits_data = coupler_to_bootrom_auto_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_6_a_ready = coupler_to_aon_auto_tl_in_a_ready; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_6_d_valid = coupler_to_aon_auto_tl_in_d_valid; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_6_d_bits_opcode = coupler_to_aon_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_6_d_bits_param = coupler_to_aon_auto_tl_in_d_bits_param; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_6_d_bits_size = coupler_to_aon_auto_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_6_d_bits_source = coupler_to_aon_auto_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_6_d_bits_sink = coupler_to_aon_auto_tl_in_d_bits_sink; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_6_d_bits_denied = coupler_to_aon_auto_tl_in_d_bits_denied; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_6_d_bits_data = coupler_to_aon_auto_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_6_d_bits_corrupt = coupler_to_aon_auto_tl_in_d_bits_corrupt; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_5_a_ready = coupler_to_tile_auto_tl_in_a_ready; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_5_d_valid = coupler_to_tile_auto_tl_in_d_valid; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_5_d_bits_opcode = coupler_to_tile_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_5_d_bits_param = coupler_to_tile_auto_tl_in_d_bits_param; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_5_d_bits_size = coupler_to_tile_auto_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_5_d_bits_source = coupler_to_tile_auto_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_5_d_bits_sink = coupler_to_tile_auto_tl_in_d_bits_sink; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_5_d_bits_denied = coupler_to_tile_auto_tl_in_d_bits_denied; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_5_d_bits_data = coupler_to_tile_auto_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_5_d_bits_corrupt = coupler_to_tile_auto_tl_in_d_bits_corrupt; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_4_a_ready = coupler_to_debug_auto_tl_in_a_ready; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_4_d_valid = coupler_to_debug_auto_tl_in_d_valid; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_4_d_bits_opcode = coupler_to_debug_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_4_d_bits_size = coupler_to_debug_auto_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_4_d_bits_source = coupler_to_debug_auto_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_4_d_bits_data = coupler_to_debug_auto_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_3_a_ready = coupler_to_clint_auto_tl_in_a_ready; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_3_d_valid = coupler_to_clint_auto_tl_in_d_valid; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_3_d_bits_opcode = coupler_to_clint_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_3_d_bits_size = coupler_to_clint_auto_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_3_d_bits_source = coupler_to_clint_auto_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_3_d_bits_data = coupler_to_clint_auto_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_2_a_ready = coupler_to_plic_auto_tl_in_a_ready; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_2_d_valid = coupler_to_plic_auto_tl_in_d_valid; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_2_d_bits_opcode = coupler_to_plic_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_2_d_bits_size = coupler_to_plic_auto_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_2_d_bits_source = coupler_to_plic_auto_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_2_d_bits_data = coupler_to_plic_auto_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_1_a_ready = coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_ready; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_1_d_valid = coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_valid; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_1_d_bits_opcode = coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_1_d_bits_param = coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_param; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_1_d_bits_size = coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_1_d_bits_source = coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_1_d_bits_sink = coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_sink; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_1_d_bits_denied = coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_denied; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_1_d_bits_data = coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_1_d_bits_corrupt = coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_bits_corrupt; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_0_a_ready = wrapped_error_device_auto_buffer_in_a_ready; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_0_d_valid = wrapped_error_device_auto_buffer_in_d_valid; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_0_d_bits_opcode = wrapped_error_device_auto_buffer_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_0_d_bits_param = wrapped_error_device_auto_buffer_in_d_bits_param; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_0_d_bits_size = wrapped_error_device_auto_buffer_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_0_d_bits_source = wrapped_error_device_auto_buffer_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_0_d_bits_sink = wrapped_error_device_auto_buffer_in_d_bits_sink; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_0_d_bits_denied = wrapped_error_device_auto_buffer_in_d_bits_denied; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_0_d_bits_data = wrapped_error_device_auto_buffer_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign out_xbar_auto_out_0_d_bits_corrupt = wrapped_error_device_auto_buffer_in_d_bits_corrupt; // @[LazyModule.scala 298:16]
  assign buffer_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_in_a_valid = atomics_auto_out_a_valid; // @[LazyModule.scala 296:16]
  assign buffer_auto_in_a_bits_opcode = atomics_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign buffer_auto_in_a_bits_param = atomics_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
  assign buffer_auto_in_a_bits_size = atomics_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign buffer_auto_in_a_bits_source = atomics_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign buffer_auto_in_a_bits_address = atomics_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign buffer_auto_in_a_bits_mask = atomics_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign buffer_auto_in_a_bits_data = atomics_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign buffer_auto_in_a_bits_corrupt = atomics_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
  assign buffer_auto_in_d_ready = atomics_auto_out_d_ready; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_a_ready = fixer_auto_in_a_ready; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_valid = fixer_auto_in_d_valid; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_opcode = fixer_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_param = fixer_auto_in_d_bits_param; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_size = fixer_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_source = fixer_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_sink = fixer_auto_in_d_bits_sink; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_denied = fixer_auto_in_d_bits_denied; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_data = fixer_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_corrupt = fixer_auto_in_d_bits_corrupt; // @[LazyModule.scala 296:16]
  assign atomics_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign atomics_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign atomics_auto_in_a_valid = in_xbar_auto_out_a_valid; // @[LazyModule.scala 298:16]
  assign atomics_auto_in_a_bits_opcode = in_xbar_auto_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign atomics_auto_in_a_bits_param = in_xbar_auto_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign atomics_auto_in_a_bits_size = in_xbar_auto_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign atomics_auto_in_a_bits_source = in_xbar_auto_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign atomics_auto_in_a_bits_address = in_xbar_auto_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign atomics_auto_in_a_bits_mask = in_xbar_auto_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign atomics_auto_in_a_bits_data = in_xbar_auto_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign atomics_auto_in_a_bits_corrupt = in_xbar_auto_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign atomics_auto_in_d_ready = in_xbar_auto_out_d_ready; // @[LazyModule.scala 298:16]
  assign atomics_auto_out_a_ready = buffer_auto_in_a_ready; // @[LazyModule.scala 296:16]
  assign atomics_auto_out_d_valid = buffer_auto_in_d_valid; // @[LazyModule.scala 296:16]
  assign atomics_auto_out_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign atomics_auto_out_d_bits_param = buffer_auto_in_d_bits_param; // @[LazyModule.scala 296:16]
  assign atomics_auto_out_d_bits_size = buffer_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
  assign atomics_auto_out_d_bits_source = buffer_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
  assign atomics_auto_out_d_bits_sink = buffer_auto_in_d_bits_sink; // @[LazyModule.scala 296:16]
  assign atomics_auto_out_d_bits_denied = buffer_auto_in_d_bits_denied; // @[LazyModule.scala 296:16]
  assign atomics_auto_out_d_bits_data = buffer_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
  assign atomics_auto_out_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[LazyModule.scala 296:16]
  assign wrapped_error_device_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign wrapped_error_device_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign wrapped_error_device_auto_buffer_in_a_valid = out_xbar_auto_out_0_a_valid; // @[LazyModule.scala 298:16]
  assign wrapped_error_device_auto_buffer_in_a_bits_opcode = out_xbar_auto_out_0_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign wrapped_error_device_auto_buffer_in_a_bits_param = out_xbar_auto_out_0_a_bits_param; // @[LazyModule.scala 298:16]
  assign wrapped_error_device_auto_buffer_in_a_bits_size = out_xbar_auto_out_0_a_bits_size; // @[LazyModule.scala 298:16]
  assign wrapped_error_device_auto_buffer_in_a_bits_source = out_xbar_auto_out_0_a_bits_source; // @[LazyModule.scala 298:16]
  assign wrapped_error_device_auto_buffer_in_a_bits_address = out_xbar_auto_out_0_a_bits_address; // @[LazyModule.scala 298:16]
  assign wrapped_error_device_auto_buffer_in_a_bits_mask = out_xbar_auto_out_0_a_bits_mask; // @[LazyModule.scala 298:16]
  assign wrapped_error_device_auto_buffer_in_a_bits_corrupt = out_xbar_auto_out_0_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign wrapped_error_device_auto_buffer_in_d_ready = out_xbar_auto_out_0_d_ready; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_a_valid = auto_bus_xing_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_in_a_bits_opcode = auto_bus_xing_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_in_a_bits_param = auto_bus_xing_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_in_a_bits_size = auto_bus_xing_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_in_a_bits_source = auto_bus_xing_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_in_a_bits_address = auto_bus_xing_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_in_a_bits_mask = auto_bus_xing_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_in_a_bits_data = auto_bus_xing_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_in_a_bits_corrupt = auto_bus_xing_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_in_d_ready = auto_bus_xing_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_out_a_ready = in_xbar_auto_in_a_ready; // @[LazyModule.scala 296:16]
  assign buffer_1_auto_out_d_valid = in_xbar_auto_in_d_valid; // @[LazyModule.scala 296:16]
  assign buffer_1_auto_out_d_bits_opcode = in_xbar_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign buffer_1_auto_out_d_bits_param = in_xbar_auto_in_d_bits_param; // @[LazyModule.scala 296:16]
  assign buffer_1_auto_out_d_bits_size = in_xbar_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
  assign buffer_1_auto_out_d_bits_source = in_xbar_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
  assign buffer_1_auto_out_d_bits_sink = in_xbar_auto_in_d_bits_sink; // @[LazyModule.scala 296:16]
  assign buffer_1_auto_out_d_bits_denied = in_xbar_auto_in_d_bits_denied; // @[LazyModule.scala 296:16]
  assign buffer_1_auto_out_d_bits_data = in_xbar_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
  assign buffer_1_auto_out_d_bits_corrupt = in_xbar_auto_in_d_bits_corrupt; // @[LazyModule.scala 296:16]
  assign coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_valid = out_xbar_auto_out_1_a_valid; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_opcode = out_xbar_auto_out_1_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_param = out_xbar_auto_out_1_a_bits_param; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_size = out_xbar_auto_out_1_a_bits_size; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_source = out_xbar_auto_out_1_a_bits_source; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_address = out_xbar_auto_out_1_a_bits_address; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_mask = out_xbar_auto_out_1_a_bits_mask; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_data = out_xbar_auto_out_1_a_bits_data; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_pbus_auto_widget_in_a_bits_corrupt = out_xbar_auto_out_1_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_pbus_auto_widget_in_d_ready = out_xbar_auto_out_1_d_ready; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_a_ready =
    auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_ready; // @[LazyModule.scala 311:12]
  assign coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_valid =
    auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_valid; // @[LazyModule.scala 311:12]
  assign coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_opcode =
    auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_opcode; // @[LazyModule.scala 311:12]
  assign coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_param =
    auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_param; // @[LazyModule.scala 311:12]
  assign coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_size =
    auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_size; // @[LazyModule.scala 311:12]
  assign coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_source =
    auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_source; // @[LazyModule.scala 311:12]
  assign coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_sink =
    auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_sink; // @[LazyModule.scala 311:12]
  assign coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_denied =
    auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_denied; // @[LazyModule.scala 311:12]
  assign coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_data =
    auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_data; // @[LazyModule.scala 311:12]
  assign coupler_to_bus_named_subsystem_pbus_auto_bus_xing_out_d_bits_corrupt =
    auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_corrupt; // @[LazyModule.scala 311:12]
  assign coupler_to_plic_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_plic_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_plic_auto_fragmenter_out_a_ready = auto_coupler_to_plic_fragmenter_out_a_ready; // @[LazyModule.scala 311:12]
  assign coupler_to_plic_auto_fragmenter_out_d_valid = auto_coupler_to_plic_fragmenter_out_d_valid; // @[LazyModule.scala 311:12]
  assign coupler_to_plic_auto_fragmenter_out_d_bits_opcode = auto_coupler_to_plic_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 311:12]
  assign coupler_to_plic_auto_fragmenter_out_d_bits_size = auto_coupler_to_plic_fragmenter_out_d_bits_size; // @[LazyModule.scala 311:12]
  assign coupler_to_plic_auto_fragmenter_out_d_bits_source = auto_coupler_to_plic_fragmenter_out_d_bits_source; // @[LazyModule.scala 311:12]
  assign coupler_to_plic_auto_fragmenter_out_d_bits_data = auto_coupler_to_plic_fragmenter_out_d_bits_data; // @[LazyModule.scala 311:12]
  assign coupler_to_plic_auto_tl_in_a_valid = out_xbar_auto_out_2_a_valid; // @[LazyModule.scala 298:16]
  assign coupler_to_plic_auto_tl_in_a_bits_opcode = out_xbar_auto_out_2_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign coupler_to_plic_auto_tl_in_a_bits_param = out_xbar_auto_out_2_a_bits_param; // @[LazyModule.scala 298:16]
  assign coupler_to_plic_auto_tl_in_a_bits_size = out_xbar_auto_out_2_a_bits_size; // @[LazyModule.scala 298:16]
  assign coupler_to_plic_auto_tl_in_a_bits_source = out_xbar_auto_out_2_a_bits_source; // @[LazyModule.scala 298:16]
  assign coupler_to_plic_auto_tl_in_a_bits_address = out_xbar_auto_out_2_a_bits_address; // @[LazyModule.scala 298:16]
  assign coupler_to_plic_auto_tl_in_a_bits_mask = out_xbar_auto_out_2_a_bits_mask; // @[LazyModule.scala 298:16]
  assign coupler_to_plic_auto_tl_in_a_bits_data = out_xbar_auto_out_2_a_bits_data; // @[LazyModule.scala 298:16]
  assign coupler_to_plic_auto_tl_in_a_bits_corrupt = out_xbar_auto_out_2_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign coupler_to_plic_auto_tl_in_d_ready = out_xbar_auto_out_2_d_ready; // @[LazyModule.scala 298:16]
  assign coupler_to_clint_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_clint_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_clint_auto_fragmenter_out_a_ready = auto_coupler_to_clint_fragmenter_out_a_ready; // @[LazyModule.scala 311:12]
  assign coupler_to_clint_auto_fragmenter_out_d_valid = auto_coupler_to_clint_fragmenter_out_d_valid; // @[LazyModule.scala 311:12]
  assign coupler_to_clint_auto_fragmenter_out_d_bits_opcode = auto_coupler_to_clint_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 311:12]
  assign coupler_to_clint_auto_fragmenter_out_d_bits_size = auto_coupler_to_clint_fragmenter_out_d_bits_size; // @[LazyModule.scala 311:12]
  assign coupler_to_clint_auto_fragmenter_out_d_bits_source = auto_coupler_to_clint_fragmenter_out_d_bits_source; // @[LazyModule.scala 311:12]
  assign coupler_to_clint_auto_fragmenter_out_d_bits_data = auto_coupler_to_clint_fragmenter_out_d_bits_data; // @[LazyModule.scala 311:12]
  assign coupler_to_clint_auto_tl_in_a_valid = out_xbar_auto_out_3_a_valid; // @[LazyModule.scala 298:16]
  assign coupler_to_clint_auto_tl_in_a_bits_opcode = out_xbar_auto_out_3_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign coupler_to_clint_auto_tl_in_a_bits_param = out_xbar_auto_out_3_a_bits_param; // @[LazyModule.scala 298:16]
  assign coupler_to_clint_auto_tl_in_a_bits_size = out_xbar_auto_out_3_a_bits_size; // @[LazyModule.scala 298:16]
  assign coupler_to_clint_auto_tl_in_a_bits_source = out_xbar_auto_out_3_a_bits_source; // @[LazyModule.scala 298:16]
  assign coupler_to_clint_auto_tl_in_a_bits_address = out_xbar_auto_out_3_a_bits_address; // @[LazyModule.scala 298:16]
  assign coupler_to_clint_auto_tl_in_a_bits_mask = out_xbar_auto_out_3_a_bits_mask; // @[LazyModule.scala 298:16]
  assign coupler_to_clint_auto_tl_in_a_bits_data = out_xbar_auto_out_3_a_bits_data; // @[LazyModule.scala 298:16]
  assign coupler_to_clint_auto_tl_in_a_bits_corrupt = out_xbar_auto_out_3_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign coupler_to_clint_auto_tl_in_d_ready = out_xbar_auto_out_3_d_ready; // @[LazyModule.scala 298:16]
  assign coupler_to_debug_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_debug_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_debug_auto_fragmenter_out_a_ready = auto_coupler_to_debug_fragmenter_out_a_ready; // @[LazyModule.scala 311:12]
  assign coupler_to_debug_auto_fragmenter_out_d_valid = auto_coupler_to_debug_fragmenter_out_d_valid; // @[LazyModule.scala 311:12]
  assign coupler_to_debug_auto_fragmenter_out_d_bits_opcode = auto_coupler_to_debug_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 311:12]
  assign coupler_to_debug_auto_fragmenter_out_d_bits_size = auto_coupler_to_debug_fragmenter_out_d_bits_size; // @[LazyModule.scala 311:12]
  assign coupler_to_debug_auto_fragmenter_out_d_bits_source = auto_coupler_to_debug_fragmenter_out_d_bits_source; // @[LazyModule.scala 311:12]
  assign coupler_to_debug_auto_fragmenter_out_d_bits_data = auto_coupler_to_debug_fragmenter_out_d_bits_data; // @[LazyModule.scala 311:12]
  assign coupler_to_debug_auto_tl_in_a_valid = out_xbar_auto_out_4_a_valid; // @[LazyModule.scala 298:16]
  assign coupler_to_debug_auto_tl_in_a_bits_opcode = out_xbar_auto_out_4_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign coupler_to_debug_auto_tl_in_a_bits_param = out_xbar_auto_out_4_a_bits_param; // @[LazyModule.scala 298:16]
  assign coupler_to_debug_auto_tl_in_a_bits_size = out_xbar_auto_out_4_a_bits_size; // @[LazyModule.scala 298:16]
  assign coupler_to_debug_auto_tl_in_a_bits_source = out_xbar_auto_out_4_a_bits_source; // @[LazyModule.scala 298:16]
  assign coupler_to_debug_auto_tl_in_a_bits_address = out_xbar_auto_out_4_a_bits_address; // @[LazyModule.scala 298:16]
  assign coupler_to_debug_auto_tl_in_a_bits_mask = out_xbar_auto_out_4_a_bits_mask; // @[LazyModule.scala 298:16]
  assign coupler_to_debug_auto_tl_in_a_bits_data = out_xbar_auto_out_4_a_bits_data; // @[LazyModule.scala 298:16]
  assign coupler_to_debug_auto_tl_in_a_bits_corrupt = out_xbar_auto_out_4_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign coupler_to_debug_auto_tl_in_d_ready = out_xbar_auto_out_4_d_ready; // @[LazyModule.scala 298:16]
  assign coupler_to_tile_auto_tl_slave_clock_xing_out_a_ready = auto_coupler_to_tile_tl_slave_clock_xing_out_a_ready; // @[LazyModule.scala 311:12]
  assign coupler_to_tile_auto_tl_slave_clock_xing_out_d_valid = auto_coupler_to_tile_tl_slave_clock_xing_out_d_valid; // @[LazyModule.scala 311:12]
  assign coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_opcode =
    auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_opcode; // @[LazyModule.scala 311:12]
  assign coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_param =
    auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_param; // @[LazyModule.scala 311:12]
  assign coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_size =
    auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_size; // @[LazyModule.scala 311:12]
  assign coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_source =
    auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_source; // @[LazyModule.scala 311:12]
  assign coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_sink =
    auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_sink; // @[LazyModule.scala 311:12]
  assign coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_denied =
    auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_denied; // @[LazyModule.scala 311:12]
  assign coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_data =
    auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_data; // @[LazyModule.scala 311:12]
  assign coupler_to_tile_auto_tl_slave_clock_xing_out_d_bits_corrupt =
    auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_corrupt; // @[LazyModule.scala 311:12]
  assign coupler_to_tile_auto_tl_in_a_valid = out_xbar_auto_out_5_a_valid; // @[LazyModule.scala 298:16]
  assign coupler_to_tile_auto_tl_in_a_bits_opcode = out_xbar_auto_out_5_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign coupler_to_tile_auto_tl_in_a_bits_param = out_xbar_auto_out_5_a_bits_param; // @[LazyModule.scala 298:16]
  assign coupler_to_tile_auto_tl_in_a_bits_size = out_xbar_auto_out_5_a_bits_size; // @[LazyModule.scala 298:16]
  assign coupler_to_tile_auto_tl_in_a_bits_source = out_xbar_auto_out_5_a_bits_source; // @[LazyModule.scala 298:16]
  assign coupler_to_tile_auto_tl_in_a_bits_address = out_xbar_auto_out_5_a_bits_address; // @[LazyModule.scala 298:16]
  assign coupler_to_tile_auto_tl_in_a_bits_mask = out_xbar_auto_out_5_a_bits_mask; // @[LazyModule.scala 298:16]
  assign coupler_to_tile_auto_tl_in_a_bits_data = out_xbar_auto_out_5_a_bits_data; // @[LazyModule.scala 298:16]
  assign coupler_to_tile_auto_tl_in_a_bits_corrupt = out_xbar_auto_out_5_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign coupler_to_tile_auto_tl_in_d_ready = out_xbar_auto_out_5_d_ready; // @[LazyModule.scala 298:16]
  assign coupler_to_aon_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_aon_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_aon_auto_asource_out_a_ridx = auto_coupler_to_aon_asource_out_a_ridx; // @[LazyModule.scala 311:12]
  assign coupler_to_aon_auto_asource_out_a_safe_ridx_valid = auto_coupler_to_aon_asource_out_a_safe_ridx_valid; // @[LazyModule.scala 311:12]
  assign coupler_to_aon_auto_asource_out_a_safe_sink_reset_n = auto_coupler_to_aon_asource_out_a_safe_sink_reset_n; // @[LazyModule.scala 311:12]
  assign coupler_to_aon_auto_asource_out_d_mem_0_opcode = auto_coupler_to_aon_asource_out_d_mem_0_opcode; // @[LazyModule.scala 311:12]
  assign coupler_to_aon_auto_asource_out_d_mem_0_param = auto_coupler_to_aon_asource_out_d_mem_0_param; // @[LazyModule.scala 311:12]
  assign coupler_to_aon_auto_asource_out_d_mem_0_size = auto_coupler_to_aon_asource_out_d_mem_0_size; // @[LazyModule.scala 311:12]
  assign coupler_to_aon_auto_asource_out_d_mem_0_source = auto_coupler_to_aon_asource_out_d_mem_0_source; // @[LazyModule.scala 311:12]
  assign coupler_to_aon_auto_asource_out_d_mem_0_sink = auto_coupler_to_aon_asource_out_d_mem_0_sink; // @[LazyModule.scala 311:12]
  assign coupler_to_aon_auto_asource_out_d_mem_0_denied = auto_coupler_to_aon_asource_out_d_mem_0_denied; // @[LazyModule.scala 311:12]
  assign coupler_to_aon_auto_asource_out_d_mem_0_data = auto_coupler_to_aon_asource_out_d_mem_0_data; // @[LazyModule.scala 311:12]
  assign coupler_to_aon_auto_asource_out_d_mem_0_corrupt = auto_coupler_to_aon_asource_out_d_mem_0_corrupt; // @[LazyModule.scala 311:12]
  assign coupler_to_aon_auto_asource_out_d_widx = auto_coupler_to_aon_asource_out_d_widx; // @[LazyModule.scala 311:12]
  assign coupler_to_aon_auto_asource_out_d_safe_widx_valid = auto_coupler_to_aon_asource_out_d_safe_widx_valid; // @[LazyModule.scala 311:12]
  assign coupler_to_aon_auto_asource_out_d_safe_source_reset_n = auto_coupler_to_aon_asource_out_d_safe_source_reset_n; // @[LazyModule.scala 311:12]
  assign coupler_to_aon_auto_tl_in_a_valid = out_xbar_auto_out_6_a_valid; // @[LazyModule.scala 298:16]
  assign coupler_to_aon_auto_tl_in_a_bits_opcode = out_xbar_auto_out_6_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign coupler_to_aon_auto_tl_in_a_bits_param = out_xbar_auto_out_6_a_bits_param; // @[LazyModule.scala 298:16]
  assign coupler_to_aon_auto_tl_in_a_bits_size = out_xbar_auto_out_6_a_bits_size; // @[LazyModule.scala 298:16]
  assign coupler_to_aon_auto_tl_in_a_bits_source = out_xbar_auto_out_6_a_bits_source; // @[LazyModule.scala 298:16]
  assign coupler_to_aon_auto_tl_in_a_bits_address = out_xbar_auto_out_6_a_bits_address; // @[LazyModule.scala 298:16]
  assign coupler_to_aon_auto_tl_in_a_bits_mask = out_xbar_auto_out_6_a_bits_mask; // @[LazyModule.scala 298:16]
  assign coupler_to_aon_auto_tl_in_a_bits_data = out_xbar_auto_out_6_a_bits_data; // @[LazyModule.scala 298:16]
  assign coupler_to_aon_auto_tl_in_a_bits_corrupt = out_xbar_auto_out_6_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign coupler_to_aon_auto_tl_in_d_ready = out_xbar_auto_out_6_d_ready; // @[LazyModule.scala 298:16]
  assign coupler_to_bootrom_clock = fixedClockNode_auto_out_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_bootrom_reset = fixedClockNode_auto_out_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_bootrom_auto_fragmenter_out_a_ready = auto_coupler_to_bootrom_fragmenter_out_a_ready; // @[LazyModule.scala 311:12]
  assign coupler_to_bootrom_auto_fragmenter_out_d_valid = auto_coupler_to_bootrom_fragmenter_out_d_valid; // @[LazyModule.scala 311:12]
  assign coupler_to_bootrom_auto_fragmenter_out_d_bits_size = auto_coupler_to_bootrom_fragmenter_out_d_bits_size; // @[LazyModule.scala 311:12]
  assign coupler_to_bootrom_auto_fragmenter_out_d_bits_source = auto_coupler_to_bootrom_fragmenter_out_d_bits_source; // @[LazyModule.scala 311:12]
  assign coupler_to_bootrom_auto_fragmenter_out_d_bits_data = auto_coupler_to_bootrom_fragmenter_out_d_bits_data; // @[LazyModule.scala 311:12]
  assign coupler_to_bootrom_auto_tl_in_a_valid = out_xbar_auto_out_7_a_valid; // @[LazyModule.scala 298:16]
  assign coupler_to_bootrom_auto_tl_in_a_bits_opcode = out_xbar_auto_out_7_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign coupler_to_bootrom_auto_tl_in_a_bits_param = out_xbar_auto_out_7_a_bits_param; // @[LazyModule.scala 298:16]
  assign coupler_to_bootrom_auto_tl_in_a_bits_size = out_xbar_auto_out_7_a_bits_size; // @[LazyModule.scala 298:16]
  assign coupler_to_bootrom_auto_tl_in_a_bits_source = out_xbar_auto_out_7_a_bits_source; // @[LazyModule.scala 298:16]
  assign coupler_to_bootrom_auto_tl_in_a_bits_address = out_xbar_auto_out_7_a_bits_address; // @[LazyModule.scala 298:16]
  assign coupler_to_bootrom_auto_tl_in_a_bits_mask = out_xbar_auto_out_7_a_bits_mask; // @[LazyModule.scala 298:16]
  assign coupler_to_bootrom_auto_tl_in_a_bits_corrupt = out_xbar_auto_out_7_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign coupler_to_bootrom_auto_tl_in_d_ready = out_xbar_auto_out_7_d_ready; // @[LazyModule.scala 298:16]
endmodule
module ClockGroupAggregator_4(
  input   auto_in_member_subsystem_mbus_0_clock,
  input   auto_in_member_subsystem_mbus_0_reset,
  output  auto_out_member_subsystem_mbus_0_clock,
  output  auto_out_member_subsystem_mbus_0_reset
);
  assign auto_out_member_subsystem_mbus_0_clock = auto_in_member_subsystem_mbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_member_subsystem_mbus_0_reset = auto_in_member_subsystem_mbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module ClockGroup_4(
  input   auto_in_member_subsystem_mbus_0_clock,
  input   auto_in_member_subsystem_mbus_0_reset,
  output  auto_out_clock,
  output  auto_out_reset
);
  assign auto_out_clock = auto_in_member_subsystem_mbus_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_reset = auto_in_member_subsystem_mbus_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module TLXbar_6(
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [3:0]  auto_in_a_bits_source,
  input  [30:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [2:0]  auto_in_d_bits_size,
  output [3:0]  auto_in_d_bits_source,
  output [31:0] auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [2:0]  auto_out_a_bits_size,
  output [3:0]  auto_out_a_bits_source,
  output [30:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [2:0]  auto_out_d_bits_size,
  input  [3:0]  auto_out_d_bits_source,
  input  [31:0] auto_out_d_bits_data
);
  assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_valid = auto_out_d_valid; // @[ReadyValidCancel.scala 21:38]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Xbar.scala 228:69]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = auto_in_a_valid; // @[ReadyValidCancel.scala 21:38]
  assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
  assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module TLMonitor_36(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [3:0]  io_in_a_bits_source,
  input  [30:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [2:0]  io_in_d_bits_size,
  input  [3:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [63:0] _RAND_11;
  reg [63:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [63:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
  wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
  wire [30:0] _GEN_71 = {{25'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [30:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 31'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [30:0] _T_33 = io_in_a_bits_address ^ 31'h40000000; // @[Parameters.scala 137:31]
  wire [31:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_36 = $signed(_T_34) & -32'sh20000000; // @[Parameters.scala 137:52]
  wire  _T_37 = $signed(_T_36) == 32'sh0; // @[Parameters.scala 137:67]
  wire  _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_74 = _T_73 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_164 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
  wire  _T_172 = _T_164 & _T_37; // @[Parameters.scala 670:56]
  wire  _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_270 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_271 = io_in_a_bits_mask & _T_270; // @[Monitor.scala 127:31]
  wire  _T_272 = _T_271 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_276 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_306 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_314 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_344 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_352 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_382 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_394 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _T_398 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_402 = io_in_d_bits_size >= 3'h2; // @[Monitor.scala 312:27]
  wire  _T_418 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_446 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [3:0] a_first_beats1_decode = is_aligned_mask[5:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] a_first_counter; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1 = a_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [3:0] source; // @[Monitor.scala 387:22]
  reg [30:0] address; // @[Monitor.scala 388:22]
  wire  _T_540 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_541 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_545 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_549 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_553 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_557 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
  wire [3:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [3:0] d_first_counter; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1 = d_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [3:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_564 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_565 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_573 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_577 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [15:0] inflight; // @[Monitor.scala 611:27]
  reg [63:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [63:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [3:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1_1 = a_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  reg [3:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_1 = d_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  wire [5:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [6:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [63:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [63:0] _GEN_73 = {{48'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
  wire [63:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
  wire [63:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[63:1]}; // @[Monitor.scala 634:152]
  wire [63:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [63:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
  wire [63:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[63:1]}; // @[Monitor.scala 638:144]
  wire  _T_591 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [15:0] _a_set_wo_ready_T = 16'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [15:0] a_set_wo_ready = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 16'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_594 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [5:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [6:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [130:0] _GEN_1 = {{127'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [130:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [130:0] _GEN_2 = {{127'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [130:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [15:0] _T_596 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_598 = ~_T_596[0]; // @[Monitor.scala 658:17]
  wire [15:0] a_set = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 16'h0; // @[Monitor.scala 652:72 653:28]
  wire [130:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 131'h0; // @[Monitor.scala 652:72 656:28]
  wire [130:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 131'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_602 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_604 = ~_T_398; // @[Monitor.scala 671:74]
  wire  _T_605 = io_in_d_valid & d_first_1 & ~_T_398; // @[Monitor.scala 671:71]
  wire [15:0] _d_clr_wo_ready_T = 16'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [15:0] d_clr_wo_ready = io_in_d_valid & d_first_1 & ~_T_398 ? _d_clr_wo_ready_T : 16'h0; // @[Monitor.scala 671:90 672:22]
  wire [142:0] _GEN_3 = {{127'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [142:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [15:0] d_clr = _d_first_T & d_first_1 & _T_604 ? _d_clr_wo_ready_T : 16'h0; // @[Monitor.scala 675:91 676:21]
  wire [142:0] _GEN_23 = _d_first_T & d_first_1 & _T_604 ? _d_opcodes_clr_T_5 : 143'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_591 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [15:0] _T_615 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_617 = _T_615[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_622 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_623 = io_in_d_bits_opcode == _GEN_32 | _T_622; // @[Monitor.scala 685:77]
  wire  _T_627 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_634 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_635 = io_in_d_bits_opcode == _GEN_48 | _T_634; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_639 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_649 = _T_602 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_604; // @[Monitor.scala 694:116]
  wire  _T_651 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire  _T_658 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire [15:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [15:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [15:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [63:0] a_opcodes_set = _GEN_19[63:0];
  wire [63:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [63:0] d_opcodes_clr = _GEN_23[63:0];
  wire [63:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [63:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [63:0] a_sizes_set = _GEN_20[63:0];
  wire [63:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [63:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_667 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [15:0] inflight_1; // @[Monitor.scala 723:35]
  reg [63:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [3:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_2 = d_first_counter_2 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 4'h0; // @[Edges.scala 230:25]
  wire [63:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [63:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
  wire [63:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[63:1]}; // @[Monitor.scala 747:146]
  wire  _T_693 = io_in_d_valid & d_first_2 & _T_398; // @[Monitor.scala 779:71]
  wire [15:0] d_clr_1 = _d_first_T & d_first_2 & _T_398 ? _d_clr_wo_ready_T : 16'h0; // @[Monitor.scala 783:90 784:21]
  wire [142:0] _GEN_68 = _d_first_T & d_first_2 & _T_398 ? _d_opcodes_clr_T_5 : 143'h0; // @[Monitor.scala 783:90 785:21]
  wire [15:0] _T_701 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_711 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [15:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [15:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [63:0] d_opcodes_clr_1 = _GEN_68[63:0];
  wire [63:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [63:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_736 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 4'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 4'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 16'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 64'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 64'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 4'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 4'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 16'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 64'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 4'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_172 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_172) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_172 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_172) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_272 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_272) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_306 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_T_306) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_314 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_314 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_314 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_314 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_344 & (io_in_a_valid & _T_314 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_314 & ~reset & ~_T_344) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_314 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_314 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_352 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_352 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_352 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_352 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_382 & (io_in_a_valid & _T_352 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_352 & ~reset & ~_T_382) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_352 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_352 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_394 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_394) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_402 & (io_in_d_valid & _T_398 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_398 & _T_2 & ~_T_402) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_418 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_418 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_402 & (io_in_d_valid & _T_418 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_418 & _T_2 & ~_T_402) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_446 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_446 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_402 & (io_in_d_valid & _T_446 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_446 & _T_2 & ~_T_402) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_541 & (_T_540 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_540 & ~reset & ~_T_541) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_545 & (_T_540 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_540 & ~reset & ~_T_545) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_549 & (_T_540 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_540 & ~reset & ~_T_549) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_553 & (_T_540 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_540 & ~reset & ~_T_553) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_557 & (_T_540 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_540 & ~reset & ~_T_557) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_565 & (_T_564 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_564 & _T_2 & ~_T_565) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_573 & (_T_564 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_564 & _T_2 & ~_T_573) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_577 & (_T_564 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_564 & _T_2 & ~_T_577) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_598 & (_T_594 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_594 & ~reset & ~_T_598) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_617 & (_T_605 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_605 & _T_2 & ~_T_617) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_623 & (_T_605 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_605 & same_cycle_resp & _T_2 & ~_T_623) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_627 & (_T_605 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_605 & same_cycle_resp & _T_2 & ~_T_627) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_635 & (_T_605 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_605 & ~same_cycle_resp & _T_2 & ~_T_635) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_639 & (_T_605 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_605 & ~same_cycle_resp & _T_2 & ~_T_639) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_651 & (_T_649 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_649 & _T_2 & ~_T_651) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_658 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_658) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_667 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_667) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_701[0] & (_T_693 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_693 & _T_2 & ~_T_701[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_711 & (_T_693 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_693 & _T_2 & ~_T_711) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_736 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_736) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[3:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[30:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[2:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[3:0];
  _RAND_10 = {1{`RANDOM}};
  inflight = _RAND_10[15:0];
  _RAND_11 = {2{`RANDOM}};
  inflight_opcodes = _RAND_11[63:0];
  _RAND_12 = {2{`RANDOM}};
  inflight_sizes = _RAND_12[63:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[3:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[3:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  inflight_1 = _RAND_16[15:0];
  _RAND_17 = {2{`RANDOM}};
  inflight_sizes_1 = _RAND_17[63:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[3:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLFIFOFixer_3(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [3:0]  auto_in_a_bits_source,
  input  [30:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [2:0]  auto_in_d_bits_size,
  output [3:0]  auto_in_d_bits_source,
  output [31:0] auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [2:0]  auto_out_a_bits_size,
  output [3:0]  auto_out_a_bits_source,
  output [30:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [2:0]  auto_out_d_bits_size,
  input  [3:0]  auto_out_d_bits_source,
  input  [31:0] auto_out_d_bits_data
);
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [30:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  TLMonitor_36 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  assign auto_in_a_ready = auto_out_a_ready; // @[FIFOFixer.scala 88:33]
  assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = auto_in_a_valid; // @[FIFOFixer.scala 87:33]
  assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = auto_out_a_ready; // @[FIFOFixer.scala 88:33]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
endmodule
module TLMonitor_37(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [3:0]  io_in_a_bits_source,
  input  [30:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [2:0]  io_in_d_bits_size,
  input  [3:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [63:0] _RAND_11;
  reg [63:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [63:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
  wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
  wire [30:0] _GEN_71 = {{25'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [30:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 31'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [30:0] _T_33 = io_in_a_bits_address ^ 31'h40000000; // @[Parameters.scala 137:31]
  wire [31:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_36 = $signed(_T_34) & -32'sh20000000; // @[Parameters.scala 137:52]
  wire  _T_37 = $signed(_T_36) == 32'sh0; // @[Parameters.scala 137:67]
  wire  _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_74 = _T_73 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_164 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
  wire  _T_172 = _T_164 & _T_37; // @[Parameters.scala 670:56]
  wire  _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_270 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_271 = io_in_a_bits_mask & _T_270; // @[Monitor.scala 127:31]
  wire  _T_272 = _T_271 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_276 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_306 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_314 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_344 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_352 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_382 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_394 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _T_398 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_402 = io_in_d_bits_size >= 3'h2; // @[Monitor.scala 312:27]
  wire  _T_418 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_446 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [3:0] a_first_beats1_decode = is_aligned_mask[5:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] a_first_counter; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1 = a_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [3:0] source; // @[Monitor.scala 387:22]
  reg [30:0] address; // @[Monitor.scala 388:22]
  wire  _T_540 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_541 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_545 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_549 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_553 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_557 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
  wire [3:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [3:0] d_first_counter; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1 = d_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [3:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_564 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_565 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_573 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_577 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [15:0] inflight; // @[Monitor.scala 611:27]
  reg [63:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [63:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [3:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1_1 = a_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  reg [3:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_1 = d_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  wire [5:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [6:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [63:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [63:0] _GEN_73 = {{48'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
  wire [63:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
  wire [63:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[63:1]}; // @[Monitor.scala 634:152]
  wire [63:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [63:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
  wire [63:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[63:1]}; // @[Monitor.scala 638:144]
  wire  _T_591 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [15:0] _a_set_wo_ready_T = 16'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [15:0] a_set_wo_ready = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 16'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_594 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [5:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [6:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [130:0] _GEN_1 = {{127'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [130:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [130:0] _GEN_2 = {{127'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [130:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [15:0] _T_596 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_598 = ~_T_596[0]; // @[Monitor.scala 658:17]
  wire [15:0] a_set = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 16'h0; // @[Monitor.scala 652:72 653:28]
  wire [130:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 131'h0; // @[Monitor.scala 652:72 656:28]
  wire [130:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 131'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_602 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_604 = ~_T_398; // @[Monitor.scala 671:74]
  wire  _T_605 = io_in_d_valid & d_first_1 & ~_T_398; // @[Monitor.scala 671:71]
  wire [15:0] _d_clr_wo_ready_T = 16'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [15:0] d_clr_wo_ready = io_in_d_valid & d_first_1 & ~_T_398 ? _d_clr_wo_ready_T : 16'h0; // @[Monitor.scala 671:90 672:22]
  wire [142:0] _GEN_3 = {{127'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [142:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [15:0] d_clr = _d_first_T & d_first_1 & _T_604 ? _d_clr_wo_ready_T : 16'h0; // @[Monitor.scala 675:91 676:21]
  wire [142:0] _GEN_23 = _d_first_T & d_first_1 & _T_604 ? _d_opcodes_clr_T_5 : 143'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_591 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [15:0] _T_615 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_617 = _T_615[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_622 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_623 = io_in_d_bits_opcode == _GEN_32 | _T_622; // @[Monitor.scala 685:77]
  wire  _T_627 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_634 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_635 = io_in_d_bits_opcode == _GEN_48 | _T_634; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_639 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_649 = _T_602 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_604; // @[Monitor.scala 694:116]
  wire  _T_651 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire  _T_658 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire [15:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [15:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [15:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [63:0] a_opcodes_set = _GEN_19[63:0];
  wire [63:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [63:0] d_opcodes_clr = _GEN_23[63:0];
  wire [63:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [63:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [63:0] a_sizes_set = _GEN_20[63:0];
  wire [63:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [63:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_667 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [15:0] inflight_1; // @[Monitor.scala 723:35]
  reg [63:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [3:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_2 = d_first_counter_2 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 4'h0; // @[Edges.scala 230:25]
  wire [63:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [63:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
  wire [63:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[63:1]}; // @[Monitor.scala 747:146]
  wire  _T_693 = io_in_d_valid & d_first_2 & _T_398; // @[Monitor.scala 779:71]
  wire [15:0] d_clr_1 = _d_first_T & d_first_2 & _T_398 ? _d_clr_wo_ready_T : 16'h0; // @[Monitor.scala 783:90 784:21]
  wire [142:0] _GEN_68 = _d_first_T & d_first_2 & _T_398 ? _d_opcodes_clr_T_5 : 143'h0; // @[Monitor.scala 783:90 785:21]
  wire [15:0] _T_701 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_711 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [15:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [15:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [63:0] d_opcodes_clr_1 = _GEN_68[63:0];
  wire [63:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [63:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_736 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 4'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 4'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 16'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 64'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 64'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 4'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 4'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 16'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 64'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 4'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_172 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_172) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_172 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_172) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_272 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_272) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_306 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_T_306) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_314 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_314 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_314 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_314 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_344 & (io_in_a_valid & _T_314 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_314 & ~reset & ~_T_344) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_314 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_314 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_352 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_352 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_352 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_352 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_382 & (io_in_a_valid & _T_352 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_352 & ~reset & ~_T_382) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_352 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_352 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_394 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_394) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_402 & (io_in_d_valid & _T_398 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_398 & _T_2 & ~_T_402) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_418 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_418 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_402 & (io_in_d_valid & _T_418 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_418 & _T_2 & ~_T_402) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_446 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_446 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_402 & (io_in_d_valid & _T_446 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_446 & _T_2 & ~_T_402) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_541 & (_T_540 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_540 & ~reset & ~_T_541) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_545 & (_T_540 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_540 & ~reset & ~_T_545) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_549 & (_T_540 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_540 & ~reset & ~_T_549) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_553 & (_T_540 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_540 & ~reset & ~_T_553) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_557 & (_T_540 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_540 & ~reset & ~_T_557) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_565 & (_T_564 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_564 & _T_2 & ~_T_565) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_573 & (_T_564 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_564 & _T_2 & ~_T_573) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_577 & (_T_564 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_564 & _T_2 & ~_T_577) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_598 & (_T_594 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_594 & ~reset & ~_T_598) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_617 & (_T_605 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_605 & _T_2 & ~_T_617) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_623 & (_T_605 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_605 & same_cycle_resp & _T_2 & ~_T_623) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_627 & (_T_605 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_605 & same_cycle_resp & _T_2 & ~_T_627) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_635 & (_T_605 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_605 & ~same_cycle_resp & _T_2 & ~_T_635) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_639 & (_T_605 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_605 & ~same_cycle_resp & _T_2 & ~_T_639) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_651 & (_T_649 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_649 & _T_2 & ~_T_651) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_658 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_658) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_667 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_667) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_701[0] & (_T_693 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_693 & _T_2 & ~_T_701[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_711 & (_T_693 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_693 & _T_2 & ~_T_711) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_736 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_736) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at MemoryBus.scala:47:50)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[3:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[30:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[2:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[3:0];
  _RAND_10 = {1{`RANDOM}};
  inflight = _RAND_10[15:0];
  _RAND_11 = {2{`RANDOM}};
  inflight_opcodes = _RAND_11[63:0];
  _RAND_12 = {2{`RANDOM}};
  inflight_sizes = _RAND_12[63:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[3:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[3:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  inflight_1 = _RAND_16[15:0];
  _RAND_17 = {2{`RANDOM}};
  inflight_sizes_1 = _RAND_17[63:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[3:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ProbePicker(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [3:0]  auto_in_a_bits_source,
  input  [30:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [2:0]  auto_in_d_bits_size,
  output [3:0]  auto_in_d_bits_source,
  output [31:0] auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [2:0]  auto_out_a_bits_size,
  output [3:0]  auto_out_a_bits_source,
  output [30:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [2:0]  auto_out_d_bits_size,
  input  [3:0]  auto_out_d_bits_source,
  input  [31:0] auto_out_d_bits_data
);
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [30:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  TLMonitor_37 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
endmodule
module TLBuffer_7(
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [3:0]  auto_in_a_bits_source,
  input  [30:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [2:0]  auto_in_d_bits_size,
  output [3:0]  auto_in_d_bits_source,
  output [31:0] auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [2:0]  auto_out_a_bits_size,
  output [3:0]  auto_out_a_bits_source,
  output [30:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [2:0]  auto_out_d_bits_size,
  input  [3:0]  auto_out_d_bits_source,
  input  [31:0] auto_out_d_bits_data
);
  assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module TLMonitor_38(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [3:0]  io_in_a_bits_source,
  input  [30:0] io_in_a_bits_address,
  input         io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [2:0]  io_in_d_bits_size,
  input  [3:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [63:0] _RAND_11;
  reg [63:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [63:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
  wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
  wire [30:0] _GEN_71 = {{25'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [30:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 31'h0; // @[Edges.scala 20:24]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [30:0] _T_33 = io_in_a_bits_address ^ 31'h40000000; // @[Parameters.scala 137:31]
  wire [31:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_36 = $signed(_T_34) & -32'sh20000000; // @[Parameters.scala 137:52]
  wire  _T_37 = $signed(_T_36) == 32'sh0; // @[Parameters.scala 137:67]
  wire  _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire  _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_74 = ~(~io_in_a_bits_mask); // @[Monitor.scala 88:31]
  wire  _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_164 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
  wire  _T_172 = _T_164 & _T_37; // @[Parameters.scala 670:56]
  wire  _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire  _T_276 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_306 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_314 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_344 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_352 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_382 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_394 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _T_398 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_418 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_446 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [5:0] a_first_counter; // @[Edges.scala 228:27]
  wire [5:0] a_first_counter1 = a_first_counter - 6'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 6'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [3:0] source; // @[Monitor.scala 387:22]
  reg [30:0] address; // @[Monitor.scala 388:22]
  wire  _T_540 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_541 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_545 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_549 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_553 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_557 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
  wire [5:0] d_first_beats1_decode = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [5:0] d_first_counter; // @[Edges.scala 228:27]
  wire [5:0] d_first_counter1 = d_first_counter - 6'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 6'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [3:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_564 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_565 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_573 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_577 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [15:0] inflight; // @[Monitor.scala 611:27]
  reg [63:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [63:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [5:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [5:0] a_first_counter1_1 = a_first_counter_1 - 6'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 6'h0; // @[Edges.scala 230:25]
  reg [5:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [5:0] d_first_counter1_1 = d_first_counter_1 - 6'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 6'h0; // @[Edges.scala 230:25]
  wire [5:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [6:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [63:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [63:0] _GEN_73 = {{48'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
  wire [63:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
  wire [63:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[63:1]}; // @[Monitor.scala 634:152]
  wire [63:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [63:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
  wire [63:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[63:1]}; // @[Monitor.scala 638:144]
  wire  _T_591 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [15:0] _a_set_wo_ready_T = 16'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_594 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [5:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [6:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [130:0] _GEN_1 = {{127'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [130:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [130:0] _GEN_2 = {{127'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [130:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [15:0] _T_596 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_598 = ~_T_596[0]; // @[Monitor.scala 658:17]
  wire [15:0] a_set = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 16'h0; // @[Monitor.scala 652:72 653:28]
  wire [130:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 131'h0; // @[Monitor.scala 652:72 656:28]
  wire [130:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 131'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_602 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_604 = ~_T_398; // @[Monitor.scala 671:74]
  wire  _T_605 = io_in_d_valid & d_first_1 & ~_T_398; // @[Monitor.scala 671:71]
  wire [15:0] _d_clr_wo_ready_T = 16'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [142:0] _GEN_3 = {{127'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [142:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [15:0] d_clr = _d_first_T & d_first_1 & _T_604 ? _d_clr_wo_ready_T : 16'h0; // @[Monitor.scala 675:91 676:21]
  wire [142:0] _GEN_23 = _d_first_T & d_first_1 & _T_604 ? _d_opcodes_clr_T_5 : 143'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_591 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [15:0] _T_615 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_617 = _T_615[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_622 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_623 = io_in_d_bits_opcode == _GEN_32 | _T_622; // @[Monitor.scala 685:77]
  wire  _T_627 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_634 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_635 = io_in_d_bits_opcode == _GEN_48 | _T_634; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_639 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_649 = _T_602 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_604; // @[Monitor.scala 694:116]
  wire  _T_651 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [15:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [15:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [15:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [63:0] a_opcodes_set = _GEN_19[63:0];
  wire [63:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [63:0] d_opcodes_clr = _GEN_23[63:0];
  wire [63:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [63:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [63:0] a_sizes_set = _GEN_20[63:0];
  wire [63:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [63:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_660 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [15:0] inflight_1; // @[Monitor.scala 723:35]
  reg [63:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [5:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [5:0] d_first_counter1_2 = d_first_counter_2 - 6'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 6'h0; // @[Edges.scala 230:25]
  wire [63:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [63:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
  wire [63:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[63:1]}; // @[Monitor.scala 747:146]
  wire  _T_686 = io_in_d_valid & d_first_2 & _T_398; // @[Monitor.scala 779:71]
  wire [15:0] d_clr_1 = _d_first_T & d_first_2 & _T_398 ? _d_clr_wo_ready_T : 16'h0; // @[Monitor.scala 783:90 784:21]
  wire [142:0] _GEN_68 = _d_first_T & d_first_2 & _T_398 ? _d_opcodes_clr_T_5 : 143'h0; // @[Monitor.scala 783:90 785:21]
  wire [15:0] _T_694 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_704 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [15:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [15:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [63:0] d_opcodes_clr_1 = _GEN_68[63:0];
  wire [63:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [63:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_724 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 6'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= is_aligned_mask;
        end else begin
          a_first_counter <= 6'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 6'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 6'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 16'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 64'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 64'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 6'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= is_aligned_mask;
        end else begin
          a_first_counter_1 <= 6'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 6'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 6'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 16'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 64'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 6'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 6'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_172 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_172) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_73 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_73) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_172 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_172) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_73 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & _T_73) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_306 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_T_306) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_73 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & _T_73) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_314 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_314 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_314 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_314 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_344 & (io_in_a_valid & _T_314 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_314 & ~reset & ~_T_344) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_73 & (io_in_a_valid & _T_314 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_314 & ~reset & _T_73) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_352 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_352 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_352 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_352 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_382 & (io_in_a_valid & _T_352 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_352 & ~reset & ~_T_382) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_73 & (io_in_a_valid & _T_352 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_352 & ~reset & _T_73) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_352 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_352 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_394 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_394) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at SPI.scala:78:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_418 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_418 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at SPI.scala:78:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_446 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_446 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at SPI.scala:78:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_541 & (_T_540 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_540 & ~reset & ~_T_541) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_545 & (_T_540 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_540 & ~reset & ~_T_545) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_549 & (_T_540 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_540 & ~reset & ~_T_549) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_553 & (_T_540 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_540 & ~reset & ~_T_553) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_557 & (_T_540 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_540 & ~reset & ~_T_557) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_565 & (_T_564 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_564 & _T_2 & ~_T_565) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at SPI.scala:78:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_573 & (_T_564 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_564 & _T_2 & ~_T_573) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at SPI.scala:78:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_577 & (_T_564 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_564 & _T_2 & ~_T_577) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at SPI.scala:78:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_598 & (_T_594 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_594 & ~reset & ~_T_598) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_617 & (_T_605 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_605 & _T_2 & ~_T_617) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SPI.scala:78:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_623 & (_T_605 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_605 & same_cycle_resp & _T_2 & ~_T_623) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at SPI.scala:78:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_627 & (_T_605 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_605 & same_cycle_resp & _T_2 & ~_T_627) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:78:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_635 & (_T_605 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_605 & ~same_cycle_resp & _T_2 & ~_T_635) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at SPI.scala:78:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_639 & (_T_605 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_605 & ~same_cycle_resp & _T_2 & ~_T_639) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:78:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_651 & (_T_649 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_649 & _T_2 & ~_T_651) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_660 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_660) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_694[0] & (_T_686 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_686 & _T_2 & ~_T_694[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SPI.scala:78:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_704 & (_T_686 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_686 & _T_2 & ~_T_704) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:78:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_724 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_724) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at SPI.scala:78:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[5:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[3:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[30:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[5:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[2:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[3:0];
  _RAND_10 = {1{`RANDOM}};
  inflight = _RAND_10[15:0];
  _RAND_11 = {2{`RANDOM}};
  inflight_opcodes = _RAND_11[63:0];
  _RAND_12 = {2{`RANDOM}};
  inflight_sizes = _RAND_12[63:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[5:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[5:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  inflight_1 = _RAND_16[15:0];
  _RAND_17 = {2{`RANDOM}};
  inflight_sizes_1 = _RAND_17[63:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[5:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Repeater_21(
  input         clock,
  input         reset,
  input         io_repeat,
  output        io_full,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [2:0]  io_enq_bits_opcode,
  input  [2:0]  io_enq_bits_param,
  input  [2:0]  io_enq_bits_size,
  input  [3:0]  io_enq_bits_source,
  input  [30:0] io_enq_bits_address,
  input         io_enq_bits_mask,
  input         io_enq_bits_corrupt,
  input         io_deq_ready,
  output        io_deq_valid,
  output [2:0]  io_deq_bits_opcode,
  output [2:0]  io_deq_bits_param,
  output [2:0]  io_deq_bits_size,
  output [3:0]  io_deq_bits_source,
  output [30:0] io_deq_bits_address,
  output        io_deq_bits_mask,
  output        io_deq_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
`endif // RANDOMIZE_REG_INIT
  reg  full; // @[Repeater.scala 19:21]
  reg [2:0] saved_opcode; // @[Repeater.scala 20:18]
  reg [2:0] saved_param; // @[Repeater.scala 20:18]
  reg [2:0] saved_size; // @[Repeater.scala 20:18]
  reg [3:0] saved_source; // @[Repeater.scala 20:18]
  reg [30:0] saved_address; // @[Repeater.scala 20:18]
  reg  saved_mask; // @[Repeater.scala 20:18]
  reg  saved_corrupt; // @[Repeater.scala 20:18]
  wire  _T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
  wire  _GEN_0 = _T & io_repeat | full; // @[Repeater.scala 19:21 28:{38,45}]
  wire  _T_2 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
  assign io_full = full; // @[Repeater.scala 26:11]
  assign io_enq_ready = io_deq_ready & ~full; // @[Repeater.scala 24:32]
  assign io_deq_valid = io_enq_valid | full; // @[Repeater.scala 23:32]
  assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode; // @[Repeater.scala 25:21]
  assign io_deq_bits_param = full ? saved_param : io_enq_bits_param; // @[Repeater.scala 25:21]
  assign io_deq_bits_size = full ? saved_size : io_enq_bits_size; // @[Repeater.scala 25:21]
  assign io_deq_bits_source = full ? saved_source : io_enq_bits_source; // @[Repeater.scala 25:21]
  assign io_deq_bits_address = full ? saved_address : io_enq_bits_address; // @[Repeater.scala 25:21]
  assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask; // @[Repeater.scala 25:21]
  assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt; // @[Repeater.scala 25:21]
  always @(posedge clock) begin
    if (reset) begin // @[Repeater.scala 19:21]
      full <= 1'h0; // @[Repeater.scala 19:21]
    end else if (_T_2 & ~io_repeat) begin // @[Repeater.scala 29:38]
      full <= 1'h0; // @[Repeater.scala 29:45]
    end else begin
      full <= _GEN_0;
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_opcode <= io_enq_bits_opcode; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_param <= io_enq_bits_param; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_size <= io_enq_bits_size; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_source <= io_enq_bits_source; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_address <= io_enq_bits_address; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_mask <= io_enq_bits_mask; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_corrupt <= io_enq_bits_corrupt; // @[Repeater.scala 28:62]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  full = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  saved_opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  saved_param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  saved_size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  saved_source = _RAND_4[3:0];
  _RAND_5 = {1{`RANDOM}};
  saved_address = _RAND_5[30:0];
  _RAND_6 = {1{`RANDOM}};
  saved_mask = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  saved_corrupt = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLFragmenter_20(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [3:0]  auto_in_a_bits_source,
  input  [30:0] auto_in_a_bits_address,
  input         auto_in_a_bits_mask,
  input  [7:0]  auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [2:0]  auto_in_d_bits_size,
  output [3:0]  auto_in_d_bits_source,
  output [7:0]  auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output        auto_out_a_bits_size,
  output [10:0] auto_out_a_bits_source,
  output [30:0] auto_out_a_bits_address,
  output        auto_out_a_bits_mask,
  output [7:0]  auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input         auto_out_d_bits_size,
  input  [10:0] auto_out_d_bits_source,
  input  [7:0]  auto_out_d_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [30:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  repeater_clock; // @[Fragmenter.scala 262:30]
  wire  repeater_reset; // @[Fragmenter.scala 262:30]
  wire  repeater_io_repeat; // @[Fragmenter.scala 262:30]
  wire  repeater_io_full; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
  wire [30:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
  wire [30:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
  reg [5:0] acknum; // @[Fragmenter.scala 189:29]
  reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
  reg  dToggle; // @[Fragmenter.scala 191:30]
  wire [5:0] dFragnum = auto_out_d_bits_source[5:0]; // @[Fragmenter.scala 192:41]
  wire  dFirst = acknum == 6'h0; // @[Fragmenter.scala 193:29]
  wire  dLast = dFragnum == 6'h0; // @[Fragmenter.scala 194:30]
  wire [1:0] _dsizeOH1_T_1 = 2'h1 << auto_out_d_bits_size; // @[package.scala 234:77]
  wire  dsizeOH1 = ~_dsizeOH1_T_1[0]; // @[package.scala 234:46]
  wire  dHasData = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire [5:0] _GEN_7 = {{5'd0}, dsizeOH1}; // @[Fragmenter.scala 202:50]
  wire [5:0] _T_1 = dFragnum & _GEN_7; // @[Fragmenter.scala 202:50]
  wire  _T_5 = ~reset; // @[Fragmenter.scala 202:16]
  wire  _dFirst_acknum_T = dHasData & dsizeOH1; // @[Fragmenter.scala 203:50]
  wire [5:0] _GEN_8 = {{5'd0}, _dFirst_acknum_T}; // @[Fragmenter.scala 203:45]
  wire [5:0] dFirst_acknum = dFragnum | _GEN_8; // @[Fragmenter.scala 203:45]
  wire [5:0] _dFirst_size_T_1 = dFragnum | _GEN_7; // @[Fragmenter.scala 206:69]
  wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala 232:35]
  wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
  wire [6:0] _dFirst_size_T_4 = {1'h0,_dFirst_size_T_1}; // @[Cat.scala 31:58]
  wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
  wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
  wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
  wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
  wire [3:0] _GEN_10 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
  wire [3:0] _dFirst_size_T_8 = _GEN_10 | dFirst_size_lo; // @[OneHot.scala 32:28]
  wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
  wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
  wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
  wire  drop = ~dHasData & ~dLast; // @[Fragmenter.scala 222:30]
  wire  bundleOut_0_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  wire  _T_7 = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
  wire [5:0] _acknum_T_1 = acknum - 6'h1; // @[Fragmenter.scala 209:55]
  wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h0 ? 3'h0 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
  wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
  wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
  wire [7:0] _aFragOH1_T_1 = 8'h1 << aFrag; // @[package.scala 234:77]
  wire  aFragOH1 = ~_aFragOH1_T_1[0]; // @[package.scala 234:46]
  wire  aHasData = ~repeater_io_deq_bits_opcode[2]; // @[Edges.scala 91:28]
  wire  aMask = aHasData ? 1'h0 : aFragOH1; // @[Fragmenter.scala 289:24]
  reg [5:0] gennum; // @[Fragmenter.scala 291:29]
  wire  aFirst = gennum == 6'h0; // @[Fragmenter.scala 292:29]
  wire [5:0] _old_gennum1_T_2 = gennum - 6'h1; // @[Fragmenter.scala 293:79]
  wire [5:0] old_gennum1 = aFirst ? aOrigOH1 : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
  wire [5:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
  wire [5:0] _GEN_11 = {{5'd0}, aMask}; // @[Fragmenter.scala 294:41]
  wire [5:0] _new_gennum_T_2 = _new_gennum_T | _GEN_11; // @[Fragmenter.scala 294:41]
  wire [5:0] new_gennum = ~_new_gennum_T_2; // @[Fragmenter.scala 294:26]
  wire [5:0] _GEN_12 = {{5'd0}, aFragOH1}; // @[Fragmenter.scala 295:72]
  wire [5:0] _aFragnum_T_3 = _new_gennum_T | _GEN_12; // @[Fragmenter.scala 295:72]
  wire [5:0] aFragnum = ~_aFragnum_T_3; // @[Fragmenter.scala 295:24]
  reg  aToggle_r; // @[Reg.scala 16:16]
  wire  _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
  wire  aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
  wire  bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  wire  _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
  wire  _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala 302:31]
  wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
  wire [5:0] _bundleOut_0_a_bits_address_T_2 = old_gennum1 | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
  wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_12; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_3; // @[Fragmenter.scala 304:51]
  wire [30:0] _GEN_14 = {{25'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
  wire [4:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aToggle}; // @[Cat.scala 31:58]
  wire  _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
  TLMonitor_38 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  Repeater_21 repeater ( // @[Fragmenter.scala 262:30]
    .clock(repeater_clock),
    .reset(repeater_reset),
    .io_repeat(repeater_io_repeat),
    .io_full(repeater_io_full),
    .io_enq_ready(repeater_io_enq_ready),
    .io_enq_valid(repeater_io_enq_valid),
    .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
    .io_enq_bits_param(repeater_io_enq_bits_param),
    .io_enq_bits_size(repeater_io_enq_bits_size),
    .io_enq_bits_source(repeater_io_enq_bits_source),
    .io_enq_bits_address(repeater_io_enq_bits_address),
    .io_enq_bits_mask(repeater_io_enq_bits_mask),
    .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
    .io_deq_ready(repeater_io_deq_ready),
    .io_deq_valid(repeater_io_deq_valid),
    .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
    .io_deq_bits_param(repeater_io_deq_bits_param),
    .io_deq_bits_size(repeater_io_deq_bits_size),
    .io_deq_bits_source(repeater_io_deq_bits_source),
    .io_deq_bits_address(repeater_io_deq_bits_address),
    .io_deq_bits_mask(repeater_io_deq_bits_mask),
    .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
  );
  assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign auto_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign auto_in_d_bits_source = auto_out_d_bits_source[10:7]; // @[Fragmenter.scala 226:47]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_param = repeater_io_deq_bits_param; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_size = aFrag[0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
  assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,aFragnum}; // @[Cat.scala 31:58]
  assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_14; // @[Fragmenter.scala 304:49]
  assign auto_out_a_bits_mask = repeater_io_full | auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = repeater_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source[10:7]; // @[Fragmenter.scala 226:47]
  assign repeater_clock = clock;
  assign repeater_reset = reset;
  assign repeater_io_repeat = ~aHasData & aFragnum != 6'h0; // @[Fragmenter.scala 302:41]
  assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  always @(posedge clock) begin
    if (reset) begin // @[Fragmenter.scala 189:29]
      acknum <= 6'h0; // @[Fragmenter.scala 189:29]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 209:24]
        acknum <= dFirst_acknum;
      end else begin
        acknum <= _acknum_T_1;
      end
    end
    if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
      end
    end
    if (reset) begin // @[Fragmenter.scala 191:30]
      dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dToggle <= auto_out_d_bits_source[6]; // @[Fragmenter.scala 212:21]
      end
    end
    if (reset) begin // @[Fragmenter.scala 291:29]
      gennum <= 6'h0; // @[Fragmenter.scala 291:29]
    end else if (_T_8) begin // @[Fragmenter.scala 300:29]
      gennum <= new_gennum; // @[Fragmenter.scala 300:38]
    end
    if (aFirst) begin // @[Reg.scala 17:18]
      aToggle_r <= dToggle; // @[Reg.scala 17:22]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~auto_out_d_valid | _T_1 == 6'h0) & ~reset) begin
          $fatal; // @[Fragmenter.scala 202:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~auto_out_d_valid | _T_1 == 6'h0)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Fragmenter.scala:202 assert (!out.d.valid || (acknum_fragment & acknum_size) === UInt(0))\n"
            ); // @[Fragmenter.scala 202:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~repeater_io_full | _repeater_io_repeat_T) & _T_5) begin
          $fatal; // @[Fragmenter.scala 309:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(~repeater_io_full | _repeater_io_repeat_T)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Fragmenter.scala:309 assert (!repeater.io.full || !aHasData)\n"
            ); // @[Fragmenter.scala 309:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_9 | repeater_io_deq_bits_mask) & _T_5) begin
          $fatal; // @[Fragmenter.scala 312:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
            ); // @[Fragmenter.scala 312:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  acknum = _RAND_0[5:0];
  _RAND_1 = {1{`RANDOM}};
  dOrig = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  dToggle = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  gennum = _RAND_3[5:0];
  _RAND_4 = {1{`RANDOM}};
  aToggle_r = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLMonitor_39(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [3:0]  io_in_a_bits_source,
  input  [30:0] io_in_a_bits_address,
  input         io_in_a_bits_mask,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [2:0]  io_in_d_bits_size,
  input  [3:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [63:0] _RAND_11;
  reg [63:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [63:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
  wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
  wire [30:0] _GEN_71 = {{25'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [30:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 31'h0; // @[Edges.scala 20:24]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [30:0] _T_33 = io_in_a_bits_address ^ 31'h40000000; // @[Parameters.scala 137:31]
  wire [31:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_36 = $signed(_T_34) & -32'sh20000000; // @[Parameters.scala 137:52]
  wire  _T_37 = $signed(_T_36) == 32'sh0; // @[Parameters.scala 137:67]
  wire  _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire  _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_74 = ~(~io_in_a_bits_mask); // @[Monitor.scala 88:31]
  wire  _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_164 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
  wire  _T_172 = _T_164 & _T_37; // @[Parameters.scala 670:56]
  wire  _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire  _T_276 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_306 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_314 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_344 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_352 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_382 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_394 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _T_398 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_418 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_446 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [5:0] a_first_counter; // @[Edges.scala 228:27]
  wire [5:0] a_first_counter1 = a_first_counter - 6'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 6'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [3:0] source; // @[Monitor.scala 387:22]
  reg [30:0] address; // @[Monitor.scala 388:22]
  wire  _T_540 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_541 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_545 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_549 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_553 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_557 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
  wire [5:0] d_first_beats1_decode = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [5:0] d_first_counter; // @[Edges.scala 228:27]
  wire [5:0] d_first_counter1 = d_first_counter - 6'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 6'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [3:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_564 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_565 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_573 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_577 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [15:0] inflight; // @[Monitor.scala 611:27]
  reg [63:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [63:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [5:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [5:0] a_first_counter1_1 = a_first_counter_1 - 6'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 6'h0; // @[Edges.scala 230:25]
  reg [5:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [5:0] d_first_counter1_1 = d_first_counter_1 - 6'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 6'h0; // @[Edges.scala 230:25]
  wire [5:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [6:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [63:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [63:0] _GEN_73 = {{48'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
  wire [63:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
  wire [63:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[63:1]}; // @[Monitor.scala 634:152]
  wire [63:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [63:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
  wire [63:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[63:1]}; // @[Monitor.scala 638:144]
  wire  _T_591 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [15:0] _a_set_wo_ready_T = 16'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [15:0] a_set_wo_ready = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 16'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_594 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [5:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [6:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [130:0] _GEN_1 = {{127'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [130:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [130:0] _GEN_2 = {{127'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [130:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [15:0] _T_596 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_598 = ~_T_596[0]; // @[Monitor.scala 658:17]
  wire [15:0] a_set = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 16'h0; // @[Monitor.scala 652:72 653:28]
  wire [130:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 131'h0; // @[Monitor.scala 652:72 656:28]
  wire [130:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 131'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_602 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_604 = ~_T_398; // @[Monitor.scala 671:74]
  wire  _T_605 = io_in_d_valid & d_first_1 & ~_T_398; // @[Monitor.scala 671:71]
  wire [15:0] _d_clr_wo_ready_T = 16'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [15:0] d_clr_wo_ready = io_in_d_valid & d_first_1 & ~_T_398 ? _d_clr_wo_ready_T : 16'h0; // @[Monitor.scala 671:90 672:22]
  wire [142:0] _GEN_3 = {{127'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [142:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [15:0] d_clr = _d_first_T & d_first_1 & _T_604 ? _d_clr_wo_ready_T : 16'h0; // @[Monitor.scala 675:91 676:21]
  wire [142:0] _GEN_23 = _d_first_T & d_first_1 & _T_604 ? _d_opcodes_clr_T_5 : 143'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_591 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [15:0] _T_615 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_617 = _T_615[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_622 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_623 = io_in_d_bits_opcode == _GEN_32 | _T_622; // @[Monitor.scala 685:77]
  wire  _T_627 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_634 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_635 = io_in_d_bits_opcode == _GEN_48 | _T_634; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_639 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_649 = _T_602 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_604; // @[Monitor.scala 694:116]
  wire  _T_651 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire  _T_658 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire [15:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [15:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [15:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [63:0] a_opcodes_set = _GEN_19[63:0];
  wire [63:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [63:0] d_opcodes_clr = _GEN_23[63:0];
  wire [63:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [63:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [63:0] a_sizes_set = _GEN_20[63:0];
  wire [63:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [63:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_667 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [15:0] inflight_1; // @[Monitor.scala 723:35]
  reg [63:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [5:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [5:0] d_first_counter1_2 = d_first_counter_2 - 6'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 6'h0; // @[Edges.scala 230:25]
  wire [63:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [63:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
  wire [63:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[63:1]}; // @[Monitor.scala 747:146]
  wire  _T_693 = io_in_d_valid & d_first_2 & _T_398; // @[Monitor.scala 779:71]
  wire [15:0] d_clr_1 = _d_first_T & d_first_2 & _T_398 ? _d_clr_wo_ready_T : 16'h0; // @[Monitor.scala 783:90 784:21]
  wire [142:0] _GEN_68 = _d_first_T & d_first_2 & _T_398 ? _d_opcodes_clr_T_5 : 143'h0; // @[Monitor.scala 783:90 785:21]
  wire [15:0] _T_701 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_711 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [15:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [15:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [63:0] d_opcodes_clr_1 = _GEN_68[63:0];
  wire [63:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [63:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_736 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 6'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= is_aligned_mask;
        end else begin
          a_first_counter <= 6'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 6'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 6'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 16'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 64'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 64'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 6'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= is_aligned_mask;
        end else begin
          a_first_counter_1 <= 6'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 6'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 6'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 16'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 64'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 6'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 6'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_172 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_172) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_73 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_73) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_172 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_172) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_73 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & _T_73) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_306 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_T_306) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_73 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & _T_73) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_314 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_314 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_314 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_314 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_344 & (io_in_a_valid & _T_314 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_314 & ~reset & ~_T_344) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_73 & (io_in_a_valid & _T_314 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_314 & ~reset & _T_73) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_352 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_352 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_352 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_352 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_382 & (io_in_a_valid & _T_352 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_352 & ~reset & ~_T_382) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_73 & (io_in_a_valid & _T_352 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_352 & ~reset & _T_73) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_394 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_394) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at SPI.scala:79:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_418 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_418 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at SPI.scala:79:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_446 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_446 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at SPI.scala:79:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_541 & (_T_540 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_540 & ~reset & ~_T_541) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_545 & (_T_540 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_540 & ~reset & ~_T_545) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_549 & (_T_540 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_540 & ~reset & ~_T_549) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_553 & (_T_540 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_540 & ~reset & ~_T_553) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_557 & (_T_540 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_540 & ~reset & ~_T_557) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_565 & (_T_564 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_564 & _T_2 & ~_T_565) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at SPI.scala:79:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_573 & (_T_564 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_564 & _T_2 & ~_T_573) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at SPI.scala:79:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_577 & (_T_564 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_564 & _T_2 & ~_T_577) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at SPI.scala:79:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_598 & (_T_594 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_594 & ~reset & ~_T_598) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_617 & (_T_605 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_605 & _T_2 & ~_T_617) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SPI.scala:79:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_623 & (_T_605 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_605 & same_cycle_resp & _T_2 & ~_T_623) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at SPI.scala:79:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_627 & (_T_605 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_605 & same_cycle_resp & _T_2 & ~_T_627) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:79:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_635 & (_T_605 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_605 & ~same_cycle_resp & _T_2 & ~_T_635) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at SPI.scala:79:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_639 & (_T_605 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_605 & ~same_cycle_resp & _T_2 & ~_T_639) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:79:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_651 & (_T_649 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_649 & _T_2 & ~_T_651) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_658 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_658) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at SPI.scala:79:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_667 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_667) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_701[0] & (_T_693 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_693 & _T_2 & ~_T_701[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SPI.scala:79:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_711 & (_T_693 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_693 & _T_2 & ~_T_711) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:79:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_736 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_736) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at SPI.scala:79:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[5:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[3:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[30:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[5:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[2:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[3:0];
  _RAND_10 = {1{`RANDOM}};
  inflight = _RAND_10[15:0];
  _RAND_11 = {2{`RANDOM}};
  inflight_opcodes = _RAND_11[63:0];
  _RAND_12 = {2{`RANDOM}};
  inflight_sizes = _RAND_12[63:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[5:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[5:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  inflight_1 = _RAND_16[15:0];
  _RAND_17 = {2{`RANDOM}};
  inflight_sizes_1 = _RAND_17[63:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[5:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_10(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [2:0]  io_enq_bits_opcode,
  input  [2:0]  io_enq_bits_param,
  input  [2:0]  io_enq_bits_size,
  input  [3:0]  io_enq_bits_source,
  input  [30:0] io_enq_bits_address,
  input         io_enq_bits_mask,
  input  [7:0]  io_enq_bits_data,
  input         io_deq_ready,
  output        io_deq_valid,
  output [2:0]  io_deq_bits_opcode,
  output [2:0]  io_deq_bits_param,
  output [2:0]  io_deq_bits_size,
  output [3:0]  io_deq_bits_source,
  output [30:0] io_deq_bits_address,
  output        io_deq_bits_mask,
  output [7:0]  io_deq_bits_data,
  output        io_deq_bits_corrupt
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
`endif // RANDOMIZE_REG_INIT
  reg [2:0] ram_opcode [0:7]; // @[Decoupled.scala 259:95]
  wire  ram_opcode_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire [2:0] ram_opcode_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [2:0] ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_opcode_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_en; // @[Decoupled.scala 259:95]
  reg [2:0] ram_param [0:7]; // @[Decoupled.scala 259:95]
  wire  ram_param_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire [2:0] ram_param_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [2:0] ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_param_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_param_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_param_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_param_MPORT_en; // @[Decoupled.scala 259:95]
  reg [2:0] ram_size [0:7]; // @[Decoupled.scala 259:95]
  wire  ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire [2:0] ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [2:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_size_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_size_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_en; // @[Decoupled.scala 259:95]
  reg [3:0] ram_source [0:7]; // @[Decoupled.scala 259:95]
  wire  ram_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire [2:0] ram_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [3:0] ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [3:0] ram_source_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_source_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_en; // @[Decoupled.scala 259:95]
  reg [30:0] ram_address [0:7]; // @[Decoupled.scala 259:95]
  wire  ram_address_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire [2:0] ram_address_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [30:0] ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [30:0] ram_address_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_address_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_address_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_address_MPORT_en; // @[Decoupled.scala 259:95]
  reg  ram_mask [0:7]; // @[Decoupled.scala 259:95]
  wire  ram_mask_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire [2:0] ram_mask_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_mask_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_mask_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_mask_MPORT_en; // @[Decoupled.scala 259:95]
  reg [7:0] ram_data [0:7]; // @[Decoupled.scala 259:95]
  wire  ram_data_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire [2:0] ram_data_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [7:0] ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [7:0] ram_data_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_data_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_data_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_data_MPORT_en; // @[Decoupled.scala 259:95]
  reg  ram_corrupt [0:7]; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire [2:0] ram_corrupt_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_corrupt_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_en; // @[Decoupled.scala 259:95]
  reg [2:0] value; // @[Counter.scala 62:40]
  reg [2:0] value_1; // @[Counter.scala 62:40]
  reg  maybe_full; // @[Decoupled.scala 262:27]
  wire  ptr_match = value == value_1; // @[Decoupled.scala 263:33]
  wire  empty = ptr_match & ~maybe_full; // @[Decoupled.scala 264:25]
  wire  full = ptr_match & maybe_full; // @[Decoupled.scala 265:24]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
  wire  do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
  wire [2:0] _value_T_1 = value + 3'h1; // @[Counter.scala 78:24]
  wire [2:0] _value_T_3 = value_1 + 3'h1; // @[Counter.scala 78:24]
  assign ram_opcode_io_deq_bits_MPORT_en = 1'h1;
  assign ram_opcode_io_deq_bits_MPORT_addr = value_1;
  assign ram_opcode_io_deq_bits_MPORT_data = ram_opcode[ram_opcode_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_opcode_MPORT_data = io_enq_bits_opcode;
  assign ram_opcode_MPORT_addr = value;
  assign ram_opcode_MPORT_mask = 1'h1;
  assign ram_opcode_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_param_io_deq_bits_MPORT_en = 1'h1;
  assign ram_param_io_deq_bits_MPORT_addr = value_1;
  assign ram_param_io_deq_bits_MPORT_data = ram_param[ram_param_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_param_MPORT_data = io_enq_bits_param;
  assign ram_param_MPORT_addr = value;
  assign ram_param_MPORT_mask = 1'h1;
  assign ram_param_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_size_io_deq_bits_MPORT_en = 1'h1;
  assign ram_size_io_deq_bits_MPORT_addr = value_1;
  assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_size_MPORT_data = io_enq_bits_size;
  assign ram_size_MPORT_addr = value;
  assign ram_size_MPORT_mask = 1'h1;
  assign ram_size_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_source_io_deq_bits_MPORT_en = 1'h1;
  assign ram_source_io_deq_bits_MPORT_addr = value_1;
  assign ram_source_io_deq_bits_MPORT_data = ram_source[ram_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_source_MPORT_data = io_enq_bits_source;
  assign ram_source_MPORT_addr = value;
  assign ram_source_MPORT_mask = 1'h1;
  assign ram_source_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_address_io_deq_bits_MPORT_en = 1'h1;
  assign ram_address_io_deq_bits_MPORT_addr = value_1;
  assign ram_address_io_deq_bits_MPORT_data = ram_address[ram_address_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_address_MPORT_data = io_enq_bits_address;
  assign ram_address_MPORT_addr = value;
  assign ram_address_MPORT_mask = 1'h1;
  assign ram_address_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_mask_io_deq_bits_MPORT_en = 1'h1;
  assign ram_mask_io_deq_bits_MPORT_addr = value_1;
  assign ram_mask_io_deq_bits_MPORT_data = ram_mask[ram_mask_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_mask_MPORT_data = io_enq_bits_mask;
  assign ram_mask_MPORT_addr = value;
  assign ram_mask_MPORT_mask = 1'h1;
  assign ram_mask_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_data_io_deq_bits_MPORT_en = 1'h1;
  assign ram_data_io_deq_bits_MPORT_addr = value_1;
  assign ram_data_io_deq_bits_MPORT_data = ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_data_MPORT_data = io_enq_bits_data;
  assign ram_data_MPORT_addr = value;
  assign ram_data_MPORT_mask = 1'h1;
  assign ram_data_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_corrupt_io_deq_bits_MPORT_en = 1'h1;
  assign ram_corrupt_io_deq_bits_MPORT_addr = value_1;
  assign ram_corrupt_io_deq_bits_MPORT_data = ram_corrupt[ram_corrupt_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_corrupt_MPORT_data = 1'h0;
  assign ram_corrupt_MPORT_addr = value;
  assign ram_corrupt_MPORT_mask = 1'h1;
  assign ram_corrupt_MPORT_en = io_enq_ready & io_enq_valid;
  assign io_enq_ready = ~full; // @[Decoupled.scala 289:19]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 288:19]
  assign io_deq_bits_opcode = ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_param = ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_size = ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_source = ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_address = ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_mask = ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_data = ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_corrupt = ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  always @(posedge clock) begin
    if (ram_opcode_MPORT_en & ram_opcode_MPORT_mask) begin
      ram_opcode[ram_opcode_MPORT_addr] <= ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_param_MPORT_en & ram_param_MPORT_mask) begin
      ram_param[ram_param_MPORT_addr] <= ram_param_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
      ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_source_MPORT_en & ram_source_MPORT_mask) begin
      ram_source[ram_source_MPORT_addr] <= ram_source_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_address_MPORT_en & ram_address_MPORT_mask) begin
      ram_address[ram_address_MPORT_addr] <= ram_address_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_mask_MPORT_en & ram_mask_MPORT_mask) begin
      ram_mask[ram_mask_MPORT_addr] <= ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_data_MPORT_en & ram_data_MPORT_mask) begin
      ram_data[ram_data_MPORT_addr] <= ram_data_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_corrupt_MPORT_en & ram_corrupt_MPORT_mask) begin
      ram_corrupt[ram_corrupt_MPORT_addr] <= ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (reset) begin // @[Counter.scala 62:40]
      value <= 3'h0; // @[Counter.scala 62:40]
    end else if (do_enq) begin // @[Decoupled.scala 272:16]
      value <= _value_T_1; // @[Counter.scala 78:15]
    end
    if (reset) begin // @[Counter.scala 62:40]
      value_1 <= 3'h0; // @[Counter.scala 62:40]
    end else if (do_deq) begin // @[Decoupled.scala 276:16]
      value_1 <= _value_T_3; // @[Counter.scala 78:15]
    end
    if (reset) begin // @[Decoupled.scala 262:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 262:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 279:27]
      maybe_full <= do_enq; // @[Decoupled.scala 280:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 8; initvar = initvar+1)
    ram_opcode[initvar] = _RAND_0[2:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 8; initvar = initvar+1)
    ram_param[initvar] = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 8; initvar = initvar+1)
    ram_size[initvar] = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 8; initvar = initvar+1)
    ram_source[initvar] = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  for (initvar = 0; initvar < 8; initvar = initvar+1)
    ram_address[initvar] = _RAND_4[30:0];
  _RAND_5 = {1{`RANDOM}};
  for (initvar = 0; initvar < 8; initvar = initvar+1)
    ram_mask[initvar] = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  for (initvar = 0; initvar < 8; initvar = initvar+1)
    ram_data[initvar] = _RAND_6[7:0];
  _RAND_7 = {1{`RANDOM}};
  for (initvar = 0; initvar < 8; initvar = initvar+1)
    ram_corrupt[initvar] = _RAND_7[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_8 = {1{`RANDOM}};
  value = _RAND_8[2:0];
  _RAND_9 = {1{`RANDOM}};
  value_1 = _RAND_9[2:0];
  _RAND_10 = {1{`RANDOM}};
  maybe_full = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLBuffer_8(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [3:0]  auto_in_a_bits_source,
  input  [30:0] auto_in_a_bits_address,
  input         auto_in_a_bits_mask,
  input  [7:0]  auto_in_a_bits_data,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [2:0]  auto_in_d_bits_size,
  output [3:0]  auto_in_d_bits_source,
  output [7:0]  auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [2:0]  auto_out_a_bits_size,
  output [3:0]  auto_out_a_bits_source,
  output [30:0] auto_out_a_bits_address,
  output        auto_out_a_bits_mask,
  output [7:0]  auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [2:0]  auto_out_d_bits_size,
  input  [3:0]  auto_out_d_bits_source,
  input  [7:0]  auto_out_d_bits_data
);
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [30:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  bundleOut_0_a_q_clock; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_reset; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_enq_ready; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_enq_valid; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
  wire [3:0] bundleOut_0_a_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
  wire [30:0] bundleOut_0_a_q_io_enq_bits_address; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_enq_bits_mask; // @[Decoupled.scala 361:21]
  wire [7:0] bundleOut_0_a_q_io_enq_bits_data; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_deq_ready; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_deq_valid; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
  wire [3:0] bundleOut_0_a_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
  wire [30:0] bundleOut_0_a_q_io_deq_bits_address; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_deq_bits_mask; // @[Decoupled.scala 361:21]
  wire [7:0] bundleOut_0_a_q_io_deq_bits_data; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
  TLMonitor_39 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  Queue_10 bundleOut_0_a_q ( // @[Decoupled.scala 361:21]
    .clock(bundleOut_0_a_q_clock),
    .reset(bundleOut_0_a_q_reset),
    .io_enq_ready(bundleOut_0_a_q_io_enq_ready),
    .io_enq_valid(bundleOut_0_a_q_io_enq_valid),
    .io_enq_bits_opcode(bundleOut_0_a_q_io_enq_bits_opcode),
    .io_enq_bits_param(bundleOut_0_a_q_io_enq_bits_param),
    .io_enq_bits_size(bundleOut_0_a_q_io_enq_bits_size),
    .io_enq_bits_source(bundleOut_0_a_q_io_enq_bits_source),
    .io_enq_bits_address(bundleOut_0_a_q_io_enq_bits_address),
    .io_enq_bits_mask(bundleOut_0_a_q_io_enq_bits_mask),
    .io_enq_bits_data(bundleOut_0_a_q_io_enq_bits_data),
    .io_deq_ready(bundleOut_0_a_q_io_deq_ready),
    .io_deq_valid(bundleOut_0_a_q_io_deq_valid),
    .io_deq_bits_opcode(bundleOut_0_a_q_io_deq_bits_opcode),
    .io_deq_bits_param(bundleOut_0_a_q_io_deq_bits_param),
    .io_deq_bits_size(bundleOut_0_a_q_io_deq_bits_size),
    .io_deq_bits_source(bundleOut_0_a_q_io_deq_bits_source),
    .io_deq_bits_address(bundleOut_0_a_q_io_deq_bits_address),
    .io_deq_bits_mask(bundleOut_0_a_q_io_deq_bits_mask),
    .io_deq_bits_data(bundleOut_0_a_q_io_deq_bits_data),
    .io_deq_bits_corrupt(bundleOut_0_a_q_io_deq_bits_corrupt)
  );
  assign auto_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
  assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = bundleOut_0_a_q_io_deq_valid; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_opcode = bundleOut_0_a_q_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_param = bundleOut_0_a_q_io_deq_bits_param; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_size = bundleOut_0_a_q_io_deq_bits_size; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_source = bundleOut_0_a_q_io_deq_bits_source; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_address = bundleOut_0_a_q_io_deq_bits_address; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_mask = bundleOut_0_a_q_io_deq_bits_mask; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_data = bundleOut_0_a_q_io_deq_bits_data; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_corrupt = bundleOut_0_a_q_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleOut_0_a_q_clock = clock;
  assign bundleOut_0_a_q_reset = reset;
  assign bundleOut_0_a_q_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
endmodule
module TLMonitor_40(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [3:0]  io_in_a_bits_source,
  input  [30:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [2:0]  io_in_d_bits_size,
  input  [3:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [63:0] _RAND_11;
  reg [63:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [63:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
  wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
  wire [30:0] _GEN_71 = {{25'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [30:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 31'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [30:0] _T_33 = io_in_a_bits_address ^ 31'h40000000; // @[Parameters.scala 137:31]
  wire [31:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_36 = $signed(_T_34) & -32'sh20000000; // @[Parameters.scala 137:52]
  wire  _T_37 = $signed(_T_36) == 32'sh0; // @[Parameters.scala 137:67]
  wire  _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_74 = _T_73 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_164 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
  wire  _T_172 = _T_164 & _T_37; // @[Parameters.scala 670:56]
  wire  _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_270 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_271 = io_in_a_bits_mask & _T_270; // @[Monitor.scala 127:31]
  wire  _T_272 = _T_271 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_276 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_306 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_314 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_344 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_352 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_382 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_394 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _T_398 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_402 = io_in_d_bits_size >= 3'h2; // @[Monitor.scala 312:27]
  wire  _T_418 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_446 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [3:0] a_first_beats1_decode = is_aligned_mask[5:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] a_first_counter; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1 = a_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [3:0] source; // @[Monitor.scala 387:22]
  reg [30:0] address; // @[Monitor.scala 388:22]
  wire  _T_540 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_541 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_545 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_549 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_553 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_557 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
  wire [3:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [3:0] d_first_counter; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1 = d_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [3:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_564 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_565 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_573 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_577 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [15:0] inflight; // @[Monitor.scala 611:27]
  reg [63:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [63:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [3:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1_1 = a_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  reg [3:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_1 = d_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  wire [5:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [6:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [63:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [63:0] _GEN_73 = {{48'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
  wire [63:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
  wire [63:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[63:1]}; // @[Monitor.scala 634:152]
  wire [63:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [63:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
  wire [63:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[63:1]}; // @[Monitor.scala 638:144]
  wire  _T_591 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [15:0] _a_set_wo_ready_T = 16'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [15:0] a_set_wo_ready = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 16'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_594 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [5:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [6:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [130:0] _GEN_1 = {{127'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [130:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [130:0] _GEN_2 = {{127'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [130:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [15:0] _T_596 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_598 = ~_T_596[0]; // @[Monitor.scala 658:17]
  wire [15:0] a_set = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 16'h0; // @[Monitor.scala 652:72 653:28]
  wire [130:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 131'h0; // @[Monitor.scala 652:72 656:28]
  wire [130:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 131'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_602 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_604 = ~_T_398; // @[Monitor.scala 671:74]
  wire  _T_605 = io_in_d_valid & d_first_1 & ~_T_398; // @[Monitor.scala 671:71]
  wire [15:0] _d_clr_wo_ready_T = 16'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [15:0] d_clr_wo_ready = io_in_d_valid & d_first_1 & ~_T_398 ? _d_clr_wo_ready_T : 16'h0; // @[Monitor.scala 671:90 672:22]
  wire [142:0] _GEN_3 = {{127'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [142:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [15:0] d_clr = _d_first_T & d_first_1 & _T_604 ? _d_clr_wo_ready_T : 16'h0; // @[Monitor.scala 675:91 676:21]
  wire [142:0] _GEN_23 = _d_first_T & d_first_1 & _T_604 ? _d_opcodes_clr_T_5 : 143'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_591 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [15:0] _T_615 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_617 = _T_615[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_622 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_623 = io_in_d_bits_opcode == _GEN_32 | _T_622; // @[Monitor.scala 685:77]
  wire  _T_627 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_634 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_635 = io_in_d_bits_opcode == _GEN_48 | _T_634; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_639 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_649 = _T_602 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_604; // @[Monitor.scala 694:116]
  wire  _T_651 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire  _T_658 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire [15:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [15:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [15:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [63:0] a_opcodes_set = _GEN_19[63:0];
  wire [63:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [63:0] d_opcodes_clr = _GEN_23[63:0];
  wire [63:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [63:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [63:0] a_sizes_set = _GEN_20[63:0];
  wire [63:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [63:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_667 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [15:0] inflight_1; // @[Monitor.scala 723:35]
  reg [63:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [3:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_2 = d_first_counter_2 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 4'h0; // @[Edges.scala 230:25]
  wire [63:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [63:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
  wire [63:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[63:1]}; // @[Monitor.scala 747:146]
  wire  _T_693 = io_in_d_valid & d_first_2 & _T_398; // @[Monitor.scala 779:71]
  wire [15:0] d_clr_1 = _d_first_T & d_first_2 & _T_398 ? _d_clr_wo_ready_T : 16'h0; // @[Monitor.scala 783:90 784:21]
  wire [142:0] _GEN_68 = _d_first_T & d_first_2 & _T_398 ? _d_opcodes_clr_T_5 : 143'h0; // @[Monitor.scala 783:90 785:21]
  wire [15:0] _T_701 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_711 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [15:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [15:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [63:0] d_opcodes_clr_1 = _GEN_68[63:0];
  wire [63:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [63:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_736 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 4'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 4'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 16'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 64'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 64'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 4'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 4'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 16'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 64'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 4'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_172 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_172) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_172 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_172) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_272 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_272) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_306 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_T_306) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_314 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_314 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_314 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_314 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_344 & (io_in_a_valid & _T_314 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_314 & ~reset & ~_T_344) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_314 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_314 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_352 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_352 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_352 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_352 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_382 & (io_in_a_valid & _T_352 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_352 & ~reset & ~_T_382) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_352 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_352 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_394 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_394) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at SPI.scala:80:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_402 & (io_in_d_valid & _T_398 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_398 & _T_2 & ~_T_402) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at SPI.scala:80:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_418 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_418 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at SPI.scala:80:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_402 & (io_in_d_valid & _T_418 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_418 & _T_2 & ~_T_402) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at SPI.scala:80:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_446 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_446 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at SPI.scala:80:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_402 & (io_in_d_valid & _T_446 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_446 & _T_2 & ~_T_402) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at SPI.scala:80:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_541 & (_T_540 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_540 & ~reset & ~_T_541) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_545 & (_T_540 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_540 & ~reset & ~_T_545) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_549 & (_T_540 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_540 & ~reset & ~_T_549) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_553 & (_T_540 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_540 & ~reset & ~_T_553) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_557 & (_T_540 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_540 & ~reset & ~_T_557) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_565 & (_T_564 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_564 & _T_2 & ~_T_565) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at SPI.scala:80:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_573 & (_T_564 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_564 & _T_2 & ~_T_573) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at SPI.scala:80:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_577 & (_T_564 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_564 & _T_2 & ~_T_577) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at SPI.scala:80:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_598 & (_T_594 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_594 & ~reset & ~_T_598) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_617 & (_T_605 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_605 & _T_2 & ~_T_617) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SPI.scala:80:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_623 & (_T_605 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_605 & same_cycle_resp & _T_2 & ~_T_623) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at SPI.scala:80:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_627 & (_T_605 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_605 & same_cycle_resp & _T_2 & ~_T_627) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:80:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_635 & (_T_605 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_605 & ~same_cycle_resp & _T_2 & ~_T_635) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at SPI.scala:80:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_639 & (_T_605 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_605 & ~same_cycle_resp & _T_2 & ~_T_639) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:80:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_651 & (_T_649 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_649 & _T_2 & ~_T_651) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_658 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_658) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at SPI.scala:80:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_667 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_667) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_701[0] & (_T_693 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_693 & _T_2 & ~_T_701[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SPI.scala:80:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_711 & (_T_693 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_693 & _T_2 & ~_T_711) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at SPI.scala:80:9)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_736 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_736) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at SPI.scala:80:9)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[3:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[30:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[2:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[3:0];
  _RAND_10 = {1{`RANDOM}};
  inflight = _RAND_10[15:0];
  _RAND_11 = {2{`RANDOM}};
  inflight_opcodes = _RAND_11[63:0];
  _RAND_12 = {2{`RANDOM}};
  inflight_sizes = _RAND_12[63:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[3:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[3:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  inflight_1 = _RAND_16[15:0];
  _RAND_17 = {2{`RANDOM}};
  inflight_sizes_1 = _RAND_17[63:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[3:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Repeater_22(
  input         clock,
  input         reset,
  input         io_repeat,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [2:0]  io_enq_bits_opcode,
  input  [2:0]  io_enq_bits_param,
  input  [2:0]  io_enq_bits_size,
  input  [3:0]  io_enq_bits_source,
  input  [30:0] io_enq_bits_address,
  input  [3:0]  io_enq_bits_mask,
  input  [31:0] io_enq_bits_data,
  input         io_deq_ready,
  output        io_deq_valid,
  output [2:0]  io_deq_bits_opcode,
  output [2:0]  io_deq_bits_param,
  output [2:0]  io_deq_bits_size,
  output [3:0]  io_deq_bits_source,
  output [30:0] io_deq_bits_address,
  output [3:0]  io_deq_bits_mask,
  output [31:0] io_deq_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
`endif // RANDOMIZE_REG_INIT
  reg  full; // @[Repeater.scala 19:21]
  reg [2:0] saved_opcode; // @[Repeater.scala 20:18]
  reg [2:0] saved_param; // @[Repeater.scala 20:18]
  reg [2:0] saved_size; // @[Repeater.scala 20:18]
  reg [3:0] saved_source; // @[Repeater.scala 20:18]
  reg [30:0] saved_address; // @[Repeater.scala 20:18]
  reg [3:0] saved_mask; // @[Repeater.scala 20:18]
  reg [31:0] saved_data; // @[Repeater.scala 20:18]
  wire  _T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
  wire  _GEN_0 = _T & io_repeat | full; // @[Repeater.scala 19:21 28:{38,45}]
  wire  _T_2 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
  assign io_enq_ready = io_deq_ready & ~full; // @[Repeater.scala 24:32]
  assign io_deq_valid = io_enq_valid | full; // @[Repeater.scala 23:32]
  assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode; // @[Repeater.scala 25:21]
  assign io_deq_bits_param = full ? saved_param : io_enq_bits_param; // @[Repeater.scala 25:21]
  assign io_deq_bits_size = full ? saved_size : io_enq_bits_size; // @[Repeater.scala 25:21]
  assign io_deq_bits_source = full ? saved_source : io_enq_bits_source; // @[Repeater.scala 25:21]
  assign io_deq_bits_address = full ? saved_address : io_enq_bits_address; // @[Repeater.scala 25:21]
  assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask; // @[Repeater.scala 25:21]
  assign io_deq_bits_data = full ? saved_data : io_enq_bits_data; // @[Repeater.scala 25:21]
  always @(posedge clock) begin
    if (reset) begin // @[Repeater.scala 19:21]
      full <= 1'h0; // @[Repeater.scala 19:21]
    end else if (_T_2 & ~io_repeat) begin // @[Repeater.scala 29:38]
      full <= 1'h0; // @[Repeater.scala 29:45]
    end else begin
      full <= _GEN_0;
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_opcode <= io_enq_bits_opcode; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_param <= io_enq_bits_param; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_size <= io_enq_bits_size; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_source <= io_enq_bits_source; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_address <= io_enq_bits_address; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_mask <= io_enq_bits_mask; // @[Repeater.scala 28:62]
    end
    if (_T & io_repeat) begin // @[Repeater.scala 28:38]
      saved_data <= io_enq_bits_data; // @[Repeater.scala 28:62]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  full = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  saved_opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  saved_param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  saved_size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  saved_source = _RAND_4[3:0];
  _RAND_5 = {1{`RANDOM}};
  saved_address = _RAND_5[30:0];
  _RAND_6 = {1{`RANDOM}};
  saved_mask = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  saved_data = _RAND_7[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLWidthWidget_6(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [3:0]  auto_in_a_bits_source,
  input  [30:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [2:0]  auto_in_d_bits_size,
  output [3:0]  auto_in_d_bits_source,
  output [31:0] auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [2:0]  auto_out_a_bits_size,
  output [3:0]  auto_out_a_bits_source,
  output [30:0] auto_out_a_bits_address,
  output        auto_out_a_bits_mask,
  output [7:0]  auto_out_a_bits_data,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [2:0]  auto_out_d_bits_size,
  input  [3:0]  auto_out_d_bits_source,
  input  [7:0]  auto_out_d_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [30:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  repeated_repeater_clock; // @[Repeater.scala 35:26]
  wire  repeated_repeater_reset; // @[Repeater.scala 35:26]
  wire  repeated_repeater_io_repeat; // @[Repeater.scala 35:26]
  wire  repeated_repeater_io_enq_ready; // @[Repeater.scala 35:26]
  wire  repeated_repeater_io_enq_valid; // @[Repeater.scala 35:26]
  wire [2:0] repeated_repeater_io_enq_bits_opcode; // @[Repeater.scala 35:26]
  wire [2:0] repeated_repeater_io_enq_bits_param; // @[Repeater.scala 35:26]
  wire [2:0] repeated_repeater_io_enq_bits_size; // @[Repeater.scala 35:26]
  wire [3:0] repeated_repeater_io_enq_bits_source; // @[Repeater.scala 35:26]
  wire [30:0] repeated_repeater_io_enq_bits_address; // @[Repeater.scala 35:26]
  wire [3:0] repeated_repeater_io_enq_bits_mask; // @[Repeater.scala 35:26]
  wire [31:0] repeated_repeater_io_enq_bits_data; // @[Repeater.scala 35:26]
  wire  repeated_repeater_io_deq_ready; // @[Repeater.scala 35:26]
  wire  repeated_repeater_io_deq_valid; // @[Repeater.scala 35:26]
  wire [2:0] repeated_repeater_io_deq_bits_opcode; // @[Repeater.scala 35:26]
  wire [2:0] repeated_repeater_io_deq_bits_param; // @[Repeater.scala 35:26]
  wire [2:0] repeated_repeater_io_deq_bits_size; // @[Repeater.scala 35:26]
  wire [3:0] repeated_repeater_io_deq_bits_source; // @[Repeater.scala 35:26]
  wire [30:0] repeated_repeater_io_deq_bits_address; // @[Repeater.scala 35:26]
  wire [3:0] repeated_repeater_io_deq_bits_mask; // @[Repeater.scala 35:26]
  wire [31:0] repeated_repeater_io_deq_bits_data; // @[Repeater.scala 35:26]
  wire [31:0] cated_bits_data = {repeated_repeater_io_deq_bits_data[31:8],auto_in_a_bits_data[7:0]}; // @[Cat.scala 31:58]
  wire [2:0] cated_bits_opcode = repeated_repeater_io_deq_bits_opcode; // @[WidthWidget.scala 155:25 156:15]
  wire  repeat_hasData = ~cated_bits_opcode[2]; // @[Edges.scala 91:28]
  wire [2:0] cated_bits_size = repeated_repeater_io_deq_bits_size; // @[WidthWidget.scala 155:25 156:15]
  wire [8:0] _repeat_limit_T_1 = 9'h3 << cated_bits_size; // @[package.scala 234:77]
  wire [1:0] repeat_limit = ~_repeat_limit_T_1[1:0]; // @[package.scala 234:46]
  reg [1:0] repeat_count; // @[WidthWidget.scala 99:26]
  wire  repeat_last = repeat_count == repeat_limit | ~repeat_hasData; // @[WidthWidget.scala 101:35]
  wire  cated_valid = repeated_repeater_io_deq_valid; // @[WidthWidget.scala 155:25 156:15]
  wire  _repeat_T = auto_out_a_ready & cated_valid; // @[Decoupled.scala 50:35]
  wire [1:0] _repeat_count_T_1 = repeat_count + 2'h1; // @[WidthWidget.scala 104:24]
  wire [30:0] cated_bits_address = repeated_repeater_io_deq_bits_address; // @[WidthWidget.scala 155:25 156:15]
  wire [1:0] repeat_sel = cated_bits_address[1:0]; // @[WidthWidget.scala 110:39]
  wire [1:0] repeat_index = repeat_sel | repeat_count; // @[WidthWidget.scala 120:24]
  wire [7:0] repeat_bundleOut_0_a_bits_data_mux_0 = cated_bits_data[7:0]; // @[WidthWidget.scala 122:55]
  wire [7:0] repeat_bundleOut_0_a_bits_data_mux_1 = cated_bits_data[15:8]; // @[WidthWidget.scala 122:55]
  wire [7:0] repeat_bundleOut_0_a_bits_data_mux_2 = cated_bits_data[23:16]; // @[WidthWidget.scala 122:55]
  wire [7:0] repeat_bundleOut_0_a_bits_data_mux_3 = cated_bits_data[31:24]; // @[WidthWidget.scala 122:55]
  wire [7:0] _GEN_3 = 2'h1 == repeat_index ? repeat_bundleOut_0_a_bits_data_mux_1 : repeat_bundleOut_0_a_bits_data_mux_0
    ; // @[WidthWidget.scala 131:{30,30}]
  wire [7:0] _GEN_4 = 2'h2 == repeat_index ? repeat_bundleOut_0_a_bits_data_mux_2 : _GEN_3; // @[WidthWidget.scala 131:{30,30}]
  wire [3:0] cated_bits_mask = repeated_repeater_io_deq_bits_mask; // @[WidthWidget.scala 155:25 156:15]
  wire  repeat_bundleOut_0_a_bits_mask_mux_0 = cated_bits_mask[0]; // @[WidthWidget.scala 122:55]
  wire  repeat_bundleOut_0_a_bits_mask_mux_1 = cated_bits_mask[1]; // @[WidthWidget.scala 122:55]
  wire  repeat_bundleOut_0_a_bits_mask_mux_2 = cated_bits_mask[2]; // @[WidthWidget.scala 122:55]
  wire  repeat_bundleOut_0_a_bits_mask_mux_3 = cated_bits_mask[3]; // @[WidthWidget.scala 122:55]
  wire  _GEN_7 = 2'h1 == repeat_index ? repeat_bundleOut_0_a_bits_mask_mux_1 : repeat_bundleOut_0_a_bits_mask_mux_0; // @[WidthWidget.scala 134:{53,53}]
  wire  _GEN_8 = 2'h2 == repeat_index ? repeat_bundleOut_0_a_bits_mask_mux_2 : _GEN_7; // @[WidthWidget.scala 134:{53,53}]
  wire  hasData = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire [8:0] _limit_T_1 = 9'h3 << auto_out_d_bits_size; // @[package.scala 234:77]
  wire [1:0] limit = ~_limit_T_1[1:0]; // @[package.scala 234:46]
  reg [1:0] count; // @[WidthWidget.scala 34:27]
  wire  last = count == limit | ~hasData; // @[WidthWidget.scala 36:36]
  wire [1:0] _enable_T_1 = count & limit; // @[WidthWidget.scala 37:63]
  wire  enable_0 = ~(|_enable_T_1); // @[WidthWidget.scala 37:47]
  wire [1:0] _enable_T_3 = count ^ 2'h1; // @[WidthWidget.scala 37:56]
  wire [1:0] _enable_T_4 = _enable_T_3 & limit; // @[WidthWidget.scala 37:63]
  wire  enable_1 = ~(|_enable_T_4); // @[WidthWidget.scala 37:47]
  wire [1:0] _enable_T_6 = count ^ 2'h2; // @[WidthWidget.scala 37:56]
  wire [1:0] _enable_T_7 = _enable_T_6 & limit; // @[WidthWidget.scala 37:63]
  wire  enable_2 = ~(|_enable_T_7); // @[WidthWidget.scala 37:47]
  wire  _bundleOut_0_d_ready_T = ~last; // @[WidthWidget.scala 70:32]
  wire  bundleOut_0_d_ready = auto_in_d_ready | ~last; // @[WidthWidget.scala 70:29]
  wire  _T = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
  wire [1:0] _count_T_1 = count + 2'h1; // @[WidthWidget.scala 44:24]
  reg  bundleIn_0_d_bits_data_rdata_written_once; // @[WidthWidget.scala 56:41]
  wire  bundleIn_0_d_bits_data_masked_enable_0 = enable_0 | ~bundleIn_0_d_bits_data_rdata_written_once; // @[WidthWidget.scala 57:42]
  wire  bundleIn_0_d_bits_data_masked_enable_1 = enable_1 | ~bundleIn_0_d_bits_data_rdata_written_once; // @[WidthWidget.scala 57:42]
  wire  bundleIn_0_d_bits_data_masked_enable_2 = enable_2 | ~bundleIn_0_d_bits_data_rdata_written_once; // @[WidthWidget.scala 57:42]
  reg [7:0] bundleIn_0_d_bits_data_rdata_0; // @[WidthWidget.scala 60:24]
  reg [7:0] bundleIn_0_d_bits_data_rdata_1; // @[WidthWidget.scala 60:24]
  reg [7:0] bundleIn_0_d_bits_data_rdata_2; // @[WidthWidget.scala 60:24]
  wire [7:0] bundleIn_0_d_bits_data_mdata_0 = bundleIn_0_d_bits_data_masked_enable_0 ? auto_out_d_bits_data :
    bundleIn_0_d_bits_data_rdata_0; // @[WidthWidget.scala 62:88]
  wire [7:0] bundleIn_0_d_bits_data_mdata_1 = bundleIn_0_d_bits_data_masked_enable_1 ? auto_out_d_bits_data :
    bundleIn_0_d_bits_data_rdata_1; // @[WidthWidget.scala 62:88]
  wire [7:0] bundleIn_0_d_bits_data_mdata_2 = bundleIn_0_d_bits_data_masked_enable_2 ? auto_out_d_bits_data :
    bundleIn_0_d_bits_data_rdata_2; // @[WidthWidget.scala 62:88]
  wire  _GEN_14 = _T & _bundleOut_0_d_ready_T | bundleIn_0_d_bits_data_rdata_written_once; // @[WidthWidget.scala 63:35 64:30 56:41]
  wire [15:0] bundleIn_0_d_bits_data_lo = {bundleIn_0_d_bits_data_mdata_1,bundleIn_0_d_bits_data_mdata_0}; // @[Cat.scala 31:58]
  wire [15:0] bundleIn_0_d_bits_data_hi = {auto_out_d_bits_data,bundleIn_0_d_bits_data_mdata_2}; // @[Cat.scala 31:58]
  TLMonitor_40 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  Repeater_22 repeated_repeater ( // @[Repeater.scala 35:26]
    .clock(repeated_repeater_clock),
    .reset(repeated_repeater_reset),
    .io_repeat(repeated_repeater_io_repeat),
    .io_enq_ready(repeated_repeater_io_enq_ready),
    .io_enq_valid(repeated_repeater_io_enq_valid),
    .io_enq_bits_opcode(repeated_repeater_io_enq_bits_opcode),
    .io_enq_bits_param(repeated_repeater_io_enq_bits_param),
    .io_enq_bits_size(repeated_repeater_io_enq_bits_size),
    .io_enq_bits_source(repeated_repeater_io_enq_bits_source),
    .io_enq_bits_address(repeated_repeater_io_enq_bits_address),
    .io_enq_bits_mask(repeated_repeater_io_enq_bits_mask),
    .io_enq_bits_data(repeated_repeater_io_enq_bits_data),
    .io_deq_ready(repeated_repeater_io_deq_ready),
    .io_deq_valid(repeated_repeater_io_deq_valid),
    .io_deq_bits_opcode(repeated_repeater_io_deq_bits_opcode),
    .io_deq_bits_param(repeated_repeater_io_deq_bits_param),
    .io_deq_bits_size(repeated_repeater_io_deq_bits_size),
    .io_deq_bits_source(repeated_repeater_io_deq_bits_source),
    .io_deq_bits_address(repeated_repeater_io_deq_bits_address),
    .io_deq_bits_mask(repeated_repeater_io_deq_bits_mask),
    .io_deq_bits_data(repeated_repeater_io_deq_bits_data)
  );
  assign auto_in_a_ready = repeated_repeater_io_enq_ready; // @[Nodes.scala 1210:84 Repeater.scala 37:21]
  assign auto_in_d_valid = auto_out_d_valid & last; // @[WidthWidget.scala 71:29]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_data = {bundleIn_0_d_bits_data_hi,bundleIn_0_d_bits_data_lo}; // @[Cat.scala 31:58]
  assign auto_out_a_valid = repeated_repeater_io_deq_valid; // @[WidthWidget.scala 155:25 156:15]
  assign auto_out_a_bits_opcode = repeated_repeater_io_deq_bits_opcode; // @[WidthWidget.scala 155:25 156:15]
  assign auto_out_a_bits_param = repeated_repeater_io_deq_bits_param; // @[WidthWidget.scala 155:25 156:15]
  assign auto_out_a_bits_size = repeated_repeater_io_deq_bits_size; // @[WidthWidget.scala 155:25 156:15]
  assign auto_out_a_bits_source = repeated_repeater_io_deq_bits_source; // @[WidthWidget.scala 155:25 156:15]
  assign auto_out_a_bits_address = repeated_repeater_io_deq_bits_address; // @[WidthWidget.scala 155:25 156:15]
  assign auto_out_a_bits_mask = 2'h3 == repeat_index ? repeat_bundleOut_0_a_bits_mask_mux_3 : _GEN_8; // @[WidthWidget.scala 134:{53,53}]
  assign auto_out_a_bits_data = 2'h3 == repeat_index ? repeat_bundleOut_0_a_bits_data_mux_3 : _GEN_4; // @[WidthWidget.scala 131:{30,30}]
  assign auto_out_d_ready = auto_in_d_ready | ~last; // @[WidthWidget.scala 70:29]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = repeated_repeater_io_enq_ready; // @[Nodes.scala 1210:84 Repeater.scala 37:21]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid & last; // @[WidthWidget.scala 71:29]
  assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign repeated_repeater_clock = clock;
  assign repeated_repeater_reset = reset;
  assign repeated_repeater_io_repeat = ~repeat_last; // @[WidthWidget.scala 142:7]
  assign repeated_repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeated_repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeated_repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeated_repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeated_repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeated_repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeated_repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeated_repeater_io_enq_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeated_repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  always @(posedge clock) begin
    if (reset) begin // @[WidthWidget.scala 99:26]
      repeat_count <= 2'h0; // @[WidthWidget.scala 99:26]
    end else if (_repeat_T) begin // @[WidthWidget.scala 103:25]
      if (repeat_last) begin // @[WidthWidget.scala 105:21]
        repeat_count <= 2'h0; // @[WidthWidget.scala 105:29]
      end else begin
        repeat_count <= _repeat_count_T_1; // @[WidthWidget.scala 104:15]
      end
    end
    if (reset) begin // @[WidthWidget.scala 34:27]
      count <= 2'h0; // @[WidthWidget.scala 34:27]
    end else if (_T) begin // @[WidthWidget.scala 43:24]
      if (last) begin // @[WidthWidget.scala 46:21]
        count <= 2'h0; // @[WidthWidget.scala 47:17]
      end else begin
        count <= _count_T_1; // @[WidthWidget.scala 44:15]
      end
    end
    if (reset) begin // @[WidthWidget.scala 56:41]
      bundleIn_0_d_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala 56:41]
    end else begin
      bundleIn_0_d_bits_data_rdata_written_once <= _GEN_14;
    end
    if (_T & _bundleOut_0_d_ready_T) begin // @[WidthWidget.scala 63:35]
      if (bundleIn_0_d_bits_data_masked_enable_0) begin // @[WidthWidget.scala 62:88]
        bundleIn_0_d_bits_data_rdata_0 <= auto_out_d_bits_data;
      end
    end
    if (_T & _bundleOut_0_d_ready_T) begin // @[WidthWidget.scala 63:35]
      if (bundleIn_0_d_bits_data_masked_enable_1) begin // @[WidthWidget.scala 62:88]
        bundleIn_0_d_bits_data_rdata_1 <= auto_out_d_bits_data;
      end
    end
    if (_T & _bundleOut_0_d_ready_T) begin // @[WidthWidget.scala 63:35]
      if (bundleIn_0_d_bits_data_masked_enable_2) begin // @[WidthWidget.scala 62:88]
        bundleIn_0_d_bits_data_rdata_2 <= auto_out_d_bits_data;
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  repeat_count = _RAND_0[1:0];
  _RAND_1 = {1{`RANDOM}};
  count = _RAND_1[1:0];
  _RAND_2 = {1{`RANDOM}};
  bundleIn_0_d_bits_data_rdata_written_once = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  bundleIn_0_d_bits_data_rdata_0 = _RAND_3[7:0];
  _RAND_4 = {1{`RANDOM}};
  bundleIn_0_d_bits_data_rdata_1 = _RAND_4[7:0];
  _RAND_5 = {1{`RANDOM}};
  bundleIn_0_d_bits_data_rdata_2 = _RAND_5[7:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLInterconnectCoupler_26(
  input         clock,
  input         reset,
  input         auto_mem_xing_out_a_ready,
  output        auto_mem_xing_out_a_valid,
  output [2:0]  auto_mem_xing_out_a_bits_opcode,
  output [2:0]  auto_mem_xing_out_a_bits_param,
  output        auto_mem_xing_out_a_bits_size,
  output [10:0] auto_mem_xing_out_a_bits_source,
  output [30:0] auto_mem_xing_out_a_bits_address,
  output        auto_mem_xing_out_a_bits_mask,
  output [7:0]  auto_mem_xing_out_a_bits_data,
  output        auto_mem_xing_out_a_bits_corrupt,
  output        auto_mem_xing_out_d_ready,
  input         auto_mem_xing_out_d_valid,
  input  [2:0]  auto_mem_xing_out_d_bits_opcode,
  input         auto_mem_xing_out_d_bits_size,
  input  [10:0] auto_mem_xing_out_d_bits_source,
  input  [7:0]  auto_mem_xing_out_d_bits_data,
  output        auto_tl_in_a_ready,
  input         auto_tl_in_a_valid,
  input  [2:0]  auto_tl_in_a_bits_opcode,
  input  [2:0]  auto_tl_in_a_bits_param,
  input  [2:0]  auto_tl_in_a_bits_size,
  input  [3:0]  auto_tl_in_a_bits_source,
  input  [30:0] auto_tl_in_a_bits_address,
  input  [3:0]  auto_tl_in_a_bits_mask,
  input  [31:0] auto_tl_in_a_bits_data,
  input         auto_tl_in_d_ready,
  output        auto_tl_in_d_valid,
  output [2:0]  auto_tl_in_d_bits_opcode,
  output [2:0]  auto_tl_in_d_bits_size,
  output [3:0]  auto_tl_in_d_bits_source,
  output [31:0] auto_tl_in_d_bits_data
);
  wire  fragmenter_clock; // @[Fragmenter.scala 333:34]
  wire  fragmenter_reset; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [30:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [7:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [7:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [10:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [30:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [7:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [10:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [7:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
  wire  buffer_clock; // @[Buffer.scala 68:28]
  wire  buffer_reset; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
  wire [30:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
  wire [7:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
  wire [7:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
  wire [30:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
  wire [7:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 68:28]
  wire [7:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
  wire  widget_clock; // @[WidthWidget.scala 219:28]
  wire  widget_reset; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_a_ready; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_a_valid; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_a_bits_opcode; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_a_bits_param; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_a_bits_size; // @[WidthWidget.scala 219:28]
  wire [3:0] widget_auto_in_a_bits_source; // @[WidthWidget.scala 219:28]
  wire [30:0] widget_auto_in_a_bits_address; // @[WidthWidget.scala 219:28]
  wire [3:0] widget_auto_in_a_bits_mask; // @[WidthWidget.scala 219:28]
  wire [31:0] widget_auto_in_a_bits_data; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_d_ready; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_d_valid; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_d_bits_opcode; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_d_bits_size; // @[WidthWidget.scala 219:28]
  wire [3:0] widget_auto_in_d_bits_source; // @[WidthWidget.scala 219:28]
  wire [31:0] widget_auto_in_d_bits_data; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_a_ready; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_a_valid; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_a_bits_opcode; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_a_bits_param; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_a_bits_size; // @[WidthWidget.scala 219:28]
  wire [3:0] widget_auto_out_a_bits_source; // @[WidthWidget.scala 219:28]
  wire [30:0] widget_auto_out_a_bits_address; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_a_bits_mask; // @[WidthWidget.scala 219:28]
  wire [7:0] widget_auto_out_a_bits_data; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_d_ready; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_d_valid; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_d_bits_opcode; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_d_bits_size; // @[WidthWidget.scala 219:28]
  wire [3:0] widget_auto_out_d_bits_source; // @[WidthWidget.scala 219:28]
  wire [7:0] widget_auto_out_d_bits_data; // @[WidthWidget.scala 219:28]
  TLFragmenter_20 fragmenter ( // @[Fragmenter.scala 333:34]
    .clock(fragmenter_clock),
    .reset(fragmenter_reset),
    .auto_in_a_ready(fragmenter_auto_in_a_ready),
    .auto_in_a_valid(fragmenter_auto_in_a_valid),
    .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
    .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
    .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
    .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
    .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
    .auto_in_a_bits_data(fragmenter_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
    .auto_in_d_ready(fragmenter_auto_in_d_ready),
    .auto_in_d_valid(fragmenter_auto_in_d_valid),
    .auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
    .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
    .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
    .auto_out_a_ready(fragmenter_auto_out_a_ready),
    .auto_out_a_valid(fragmenter_auto_out_a_valid),
    .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
    .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
    .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
    .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
    .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
    .auto_out_a_bits_data(fragmenter_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
    .auto_out_d_ready(fragmenter_auto_out_d_ready),
    .auto_out_d_valid(fragmenter_auto_out_d_valid),
    .auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
    .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
    .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
  );
  TLBuffer_8 buffer ( // @[Buffer.scala 68:28]
    .clock(buffer_clock),
    .reset(buffer_reset),
    .auto_in_a_ready(buffer_auto_in_a_ready),
    .auto_in_a_valid(buffer_auto_in_a_valid),
    .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
    .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
    .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
    .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
    .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
    .auto_in_a_bits_data(buffer_auto_in_a_bits_data),
    .auto_in_d_ready(buffer_auto_in_d_ready),
    .auto_in_d_valid(buffer_auto_in_d_valid),
    .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
    .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
    .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
    .auto_out_a_ready(buffer_auto_out_a_ready),
    .auto_out_a_valid(buffer_auto_out_a_valid),
    .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
    .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
    .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
    .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
    .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
    .auto_out_a_bits_data(buffer_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
    .auto_out_d_ready(buffer_auto_out_d_ready),
    .auto_out_d_valid(buffer_auto_out_d_valid),
    .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
    .auto_out_d_bits_source(buffer_auto_out_d_bits_source),
    .auto_out_d_bits_data(buffer_auto_out_d_bits_data)
  );
  TLWidthWidget_6 widget ( // @[WidthWidget.scala 219:28]
    .clock(widget_clock),
    .reset(widget_reset),
    .auto_in_a_ready(widget_auto_in_a_ready),
    .auto_in_a_valid(widget_auto_in_a_valid),
    .auto_in_a_bits_opcode(widget_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(widget_auto_in_a_bits_param),
    .auto_in_a_bits_size(widget_auto_in_a_bits_size),
    .auto_in_a_bits_source(widget_auto_in_a_bits_source),
    .auto_in_a_bits_address(widget_auto_in_a_bits_address),
    .auto_in_a_bits_mask(widget_auto_in_a_bits_mask),
    .auto_in_a_bits_data(widget_auto_in_a_bits_data),
    .auto_in_d_ready(widget_auto_in_d_ready),
    .auto_in_d_valid(widget_auto_in_d_valid),
    .auto_in_d_bits_opcode(widget_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(widget_auto_in_d_bits_size),
    .auto_in_d_bits_source(widget_auto_in_d_bits_source),
    .auto_in_d_bits_data(widget_auto_in_d_bits_data),
    .auto_out_a_ready(widget_auto_out_a_ready),
    .auto_out_a_valid(widget_auto_out_a_valid),
    .auto_out_a_bits_opcode(widget_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(widget_auto_out_a_bits_param),
    .auto_out_a_bits_size(widget_auto_out_a_bits_size),
    .auto_out_a_bits_source(widget_auto_out_a_bits_source),
    .auto_out_a_bits_address(widget_auto_out_a_bits_address),
    .auto_out_a_bits_mask(widget_auto_out_a_bits_mask),
    .auto_out_a_bits_data(widget_auto_out_a_bits_data),
    .auto_out_d_ready(widget_auto_out_d_ready),
    .auto_out_d_valid(widget_auto_out_d_valid),
    .auto_out_d_bits_opcode(widget_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(widget_auto_out_d_bits_size),
    .auto_out_d_bits_source(widget_auto_out_d_bits_source),
    .auto_out_d_bits_data(widget_auto_out_d_bits_data)
  );
  assign auto_mem_xing_out_a_valid = fragmenter_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_mem_xing_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_mem_xing_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_mem_xing_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_mem_xing_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_mem_xing_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_mem_xing_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_mem_xing_out_a_bits_data = fragmenter_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_mem_xing_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_mem_xing_out_d_ready = fragmenter_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_in_a_ready = widget_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_valid = widget_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_opcode = widget_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_size = widget_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_source = widget_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_in_d_bits_data = widget_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign fragmenter_clock = clock;
  assign fragmenter_reset = reset;
  assign fragmenter_auto_in_a_valid = buffer_auto_out_a_valid; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_in_a_bits_param = buffer_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_in_a_bits_size = buffer_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_in_a_bits_source = buffer_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_in_a_bits_address = buffer_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_in_a_bits_data = buffer_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_in_d_ready = buffer_auto_out_d_ready; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_out_a_ready = auto_mem_xing_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_valid = auto_mem_xing_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_opcode = auto_mem_xing_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_size = auto_mem_xing_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_source = auto_mem_xing_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign fragmenter_auto_out_d_bits_data = auto_mem_xing_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign buffer_clock = clock;
  assign buffer_reset = reset;
  assign buffer_auto_in_a_valid = widget_auto_out_a_valid; // @[LazyModule.scala 296:16]
  assign buffer_auto_in_a_bits_opcode = widget_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign buffer_auto_in_a_bits_param = widget_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
  assign buffer_auto_in_a_bits_size = widget_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign buffer_auto_in_a_bits_source = widget_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign buffer_auto_in_a_bits_address = widget_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign buffer_auto_in_a_bits_mask = widget_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign buffer_auto_in_a_bits_data = widget_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign buffer_auto_in_d_ready = widget_auto_out_d_ready; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_a_ready = fragmenter_auto_in_a_ready; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_valid = fragmenter_auto_in_d_valid; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_size = fragmenter_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_source = fragmenter_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_data = fragmenter_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
  assign widget_clock = clock;
  assign widget_reset = reset;
  assign widget_auto_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_data = auto_tl_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign widget_auto_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign widget_auto_out_a_ready = buffer_auto_in_a_ready; // @[LazyModule.scala 296:16]
  assign widget_auto_out_d_valid = buffer_auto_in_d_valid; // @[LazyModule.scala 296:16]
  assign widget_auto_out_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign widget_auto_out_d_bits_size = buffer_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
  assign widget_auto_out_d_bits_source = buffer_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
  assign widget_auto_out_d_bits_data = buffer_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
endmodule
module MemoryBus(
  input         auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_ready,
  output        auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_valid,
  output [2:0]  auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_opcode,
  output [2:0]  auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_param,
  output        auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_size,
  output [10:0] auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_source,
  output [30:0] auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_address,
  output        auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_mask,
  output [7:0]  auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_data,
  output        auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_corrupt,
  output        auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_d_ready,
  input         auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_d_valid,
  input  [2:0]  auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_d_bits_opcode,
  input         auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_d_bits_size,
  input  [10:0] auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_d_bits_source,
  input  [7:0]  auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_d_bits_data,
  input         auto_subsystem_mbus_clock_groups_in_member_subsystem_mbus_0_clock,
  input         auto_subsystem_mbus_clock_groups_in_member_subsystem_mbus_0_reset,
  output        auto_bus_xing_in_a_ready,
  input         auto_bus_xing_in_a_valid,
  input  [2:0]  auto_bus_xing_in_a_bits_opcode,
  input  [2:0]  auto_bus_xing_in_a_bits_param,
  input  [2:0]  auto_bus_xing_in_a_bits_size,
  input  [3:0]  auto_bus_xing_in_a_bits_source,
  input  [30:0] auto_bus_xing_in_a_bits_address,
  input  [3:0]  auto_bus_xing_in_a_bits_mask,
  input  [31:0] auto_bus_xing_in_a_bits_data,
  input         auto_bus_xing_in_d_ready,
  output        auto_bus_xing_in_d_valid,
  output [2:0]  auto_bus_xing_in_d_bits_opcode,
  output [2:0]  auto_bus_xing_in_d_bits_size,
  output [3:0]  auto_bus_xing_in_d_bits_source,
  output [31:0] auto_bus_xing_in_d_bits_data
);
  wire  subsystem_mbus_clock_groups_auto_in_member_subsystem_mbus_0_clock; // @[BusWrapper.scala 40:48]
  wire  subsystem_mbus_clock_groups_auto_in_member_subsystem_mbus_0_reset; // @[BusWrapper.scala 40:48]
  wire  subsystem_mbus_clock_groups_auto_out_member_subsystem_mbus_0_clock; // @[BusWrapper.scala 40:48]
  wire  subsystem_mbus_clock_groups_auto_out_member_subsystem_mbus_0_reset; // @[BusWrapper.scala 40:48]
  wire  clockGroup_auto_in_member_subsystem_mbus_0_clock; // @[BusWrapper.scala 41:38]
  wire  clockGroup_auto_in_member_subsystem_mbus_0_reset; // @[BusWrapper.scala 41:38]
  wire  clockGroup_auto_out_clock; // @[BusWrapper.scala 41:38]
  wire  clockGroup_auto_out_reset; // @[BusWrapper.scala 41:38]
  wire  fixedClockNode_auto_in_clock; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_in_reset; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_clock; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_reset; // @[ClockGroup.scala 106:107]
  wire  subsystem_mbus_xbar_auto_in_a_ready; // @[MemoryBus.scala 42:32]
  wire  subsystem_mbus_xbar_auto_in_a_valid; // @[MemoryBus.scala 42:32]
  wire [2:0] subsystem_mbus_xbar_auto_in_a_bits_opcode; // @[MemoryBus.scala 42:32]
  wire [2:0] subsystem_mbus_xbar_auto_in_a_bits_param; // @[MemoryBus.scala 42:32]
  wire [2:0] subsystem_mbus_xbar_auto_in_a_bits_size; // @[MemoryBus.scala 42:32]
  wire [3:0] subsystem_mbus_xbar_auto_in_a_bits_source; // @[MemoryBus.scala 42:32]
  wire [30:0] subsystem_mbus_xbar_auto_in_a_bits_address; // @[MemoryBus.scala 42:32]
  wire [3:0] subsystem_mbus_xbar_auto_in_a_bits_mask; // @[MemoryBus.scala 42:32]
  wire [31:0] subsystem_mbus_xbar_auto_in_a_bits_data; // @[MemoryBus.scala 42:32]
  wire  subsystem_mbus_xbar_auto_in_d_ready; // @[MemoryBus.scala 42:32]
  wire  subsystem_mbus_xbar_auto_in_d_valid; // @[MemoryBus.scala 42:32]
  wire [2:0] subsystem_mbus_xbar_auto_in_d_bits_opcode; // @[MemoryBus.scala 42:32]
  wire [2:0] subsystem_mbus_xbar_auto_in_d_bits_size; // @[MemoryBus.scala 42:32]
  wire [3:0] subsystem_mbus_xbar_auto_in_d_bits_source; // @[MemoryBus.scala 42:32]
  wire [31:0] subsystem_mbus_xbar_auto_in_d_bits_data; // @[MemoryBus.scala 42:32]
  wire  subsystem_mbus_xbar_auto_out_a_ready; // @[MemoryBus.scala 42:32]
  wire  subsystem_mbus_xbar_auto_out_a_valid; // @[MemoryBus.scala 42:32]
  wire [2:0] subsystem_mbus_xbar_auto_out_a_bits_opcode; // @[MemoryBus.scala 42:32]
  wire [2:0] subsystem_mbus_xbar_auto_out_a_bits_param; // @[MemoryBus.scala 42:32]
  wire [2:0] subsystem_mbus_xbar_auto_out_a_bits_size; // @[MemoryBus.scala 42:32]
  wire [3:0] subsystem_mbus_xbar_auto_out_a_bits_source; // @[MemoryBus.scala 42:32]
  wire [30:0] subsystem_mbus_xbar_auto_out_a_bits_address; // @[MemoryBus.scala 42:32]
  wire [3:0] subsystem_mbus_xbar_auto_out_a_bits_mask; // @[MemoryBus.scala 42:32]
  wire [31:0] subsystem_mbus_xbar_auto_out_a_bits_data; // @[MemoryBus.scala 42:32]
  wire  subsystem_mbus_xbar_auto_out_d_ready; // @[MemoryBus.scala 42:32]
  wire  subsystem_mbus_xbar_auto_out_d_valid; // @[MemoryBus.scala 42:32]
  wire [2:0] subsystem_mbus_xbar_auto_out_d_bits_opcode; // @[MemoryBus.scala 42:32]
  wire [2:0] subsystem_mbus_xbar_auto_out_d_bits_size; // @[MemoryBus.scala 42:32]
  wire [3:0] subsystem_mbus_xbar_auto_out_d_bits_source; // @[MemoryBus.scala 42:32]
  wire [31:0] subsystem_mbus_xbar_auto_out_d_bits_data; // @[MemoryBus.scala 42:32]
  wire  fixer_clock; // @[FIFOFixer.scala 144:27]
  wire  fixer_reset; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_in_a_ready; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_in_a_valid; // @[FIFOFixer.scala 144:27]
  wire [2:0] fixer_auto_in_a_bits_opcode; // @[FIFOFixer.scala 144:27]
  wire [2:0] fixer_auto_in_a_bits_param; // @[FIFOFixer.scala 144:27]
  wire [2:0] fixer_auto_in_a_bits_size; // @[FIFOFixer.scala 144:27]
  wire [3:0] fixer_auto_in_a_bits_source; // @[FIFOFixer.scala 144:27]
  wire [30:0] fixer_auto_in_a_bits_address; // @[FIFOFixer.scala 144:27]
  wire [3:0] fixer_auto_in_a_bits_mask; // @[FIFOFixer.scala 144:27]
  wire [31:0] fixer_auto_in_a_bits_data; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_in_d_ready; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_in_d_valid; // @[FIFOFixer.scala 144:27]
  wire [2:0] fixer_auto_in_d_bits_opcode; // @[FIFOFixer.scala 144:27]
  wire [2:0] fixer_auto_in_d_bits_size; // @[FIFOFixer.scala 144:27]
  wire [3:0] fixer_auto_in_d_bits_source; // @[FIFOFixer.scala 144:27]
  wire [31:0] fixer_auto_in_d_bits_data; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_out_a_ready; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_out_a_valid; // @[FIFOFixer.scala 144:27]
  wire [2:0] fixer_auto_out_a_bits_opcode; // @[FIFOFixer.scala 144:27]
  wire [2:0] fixer_auto_out_a_bits_param; // @[FIFOFixer.scala 144:27]
  wire [2:0] fixer_auto_out_a_bits_size; // @[FIFOFixer.scala 144:27]
  wire [3:0] fixer_auto_out_a_bits_source; // @[FIFOFixer.scala 144:27]
  wire [30:0] fixer_auto_out_a_bits_address; // @[FIFOFixer.scala 144:27]
  wire [3:0] fixer_auto_out_a_bits_mask; // @[FIFOFixer.scala 144:27]
  wire [31:0] fixer_auto_out_a_bits_data; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_out_d_ready; // @[FIFOFixer.scala 144:27]
  wire  fixer_auto_out_d_valid; // @[FIFOFixer.scala 144:27]
  wire [2:0] fixer_auto_out_d_bits_opcode; // @[FIFOFixer.scala 144:27]
  wire [2:0] fixer_auto_out_d_bits_size; // @[FIFOFixer.scala 144:27]
  wire [3:0] fixer_auto_out_d_bits_source; // @[FIFOFixer.scala 144:27]
  wire [31:0] fixer_auto_out_d_bits_data; // @[FIFOFixer.scala 144:27]
  wire  picker_clock; // @[ProbePicker.scala 65:28]
  wire  picker_reset; // @[ProbePicker.scala 65:28]
  wire  picker_auto_in_a_ready; // @[ProbePicker.scala 65:28]
  wire  picker_auto_in_a_valid; // @[ProbePicker.scala 65:28]
  wire [2:0] picker_auto_in_a_bits_opcode; // @[ProbePicker.scala 65:28]
  wire [2:0] picker_auto_in_a_bits_param; // @[ProbePicker.scala 65:28]
  wire [2:0] picker_auto_in_a_bits_size; // @[ProbePicker.scala 65:28]
  wire [3:0] picker_auto_in_a_bits_source; // @[ProbePicker.scala 65:28]
  wire [30:0] picker_auto_in_a_bits_address; // @[ProbePicker.scala 65:28]
  wire [3:0] picker_auto_in_a_bits_mask; // @[ProbePicker.scala 65:28]
  wire [31:0] picker_auto_in_a_bits_data; // @[ProbePicker.scala 65:28]
  wire  picker_auto_in_d_ready; // @[ProbePicker.scala 65:28]
  wire  picker_auto_in_d_valid; // @[ProbePicker.scala 65:28]
  wire [2:0] picker_auto_in_d_bits_opcode; // @[ProbePicker.scala 65:28]
  wire [2:0] picker_auto_in_d_bits_size; // @[ProbePicker.scala 65:28]
  wire [3:0] picker_auto_in_d_bits_source; // @[ProbePicker.scala 65:28]
  wire [31:0] picker_auto_in_d_bits_data; // @[ProbePicker.scala 65:28]
  wire  picker_auto_out_a_ready; // @[ProbePicker.scala 65:28]
  wire  picker_auto_out_a_valid; // @[ProbePicker.scala 65:28]
  wire [2:0] picker_auto_out_a_bits_opcode; // @[ProbePicker.scala 65:28]
  wire [2:0] picker_auto_out_a_bits_param; // @[ProbePicker.scala 65:28]
  wire [2:0] picker_auto_out_a_bits_size; // @[ProbePicker.scala 65:28]
  wire [3:0] picker_auto_out_a_bits_source; // @[ProbePicker.scala 65:28]
  wire [30:0] picker_auto_out_a_bits_address; // @[ProbePicker.scala 65:28]
  wire [3:0] picker_auto_out_a_bits_mask; // @[ProbePicker.scala 65:28]
  wire [31:0] picker_auto_out_a_bits_data; // @[ProbePicker.scala 65:28]
  wire  picker_auto_out_d_ready; // @[ProbePicker.scala 65:28]
  wire  picker_auto_out_d_valid; // @[ProbePicker.scala 65:28]
  wire [2:0] picker_auto_out_d_bits_opcode; // @[ProbePicker.scala 65:28]
  wire [2:0] picker_auto_out_d_bits_size; // @[ProbePicker.scala 65:28]
  wire [3:0] picker_auto_out_d_bits_source; // @[ProbePicker.scala 65:28]
  wire [31:0] picker_auto_out_d_bits_data; // @[ProbePicker.scala 65:28]
  wire  buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
  wire [30:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
  wire [30:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
  wire  coupler_to_device_named_qspi_ram_0_clock; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_ram_0_reset; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_a_bits_param; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_a_bits_size; // @[LazyModule.scala 432:27]
  wire [10:0] coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_a_bits_source; // @[LazyModule.scala 432:27]
  wire [30:0] coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_a_bits_address; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [7:0] coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_a_bits_corrupt; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_d_bits_size; // @[LazyModule.scala 432:27]
  wire [10:0] coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_d_bits_source; // @[LazyModule.scala 432:27]
  wire [7:0] coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_ram_0_auto_tl_in_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_ram_0_auto_tl_in_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_size; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_source; // @[LazyModule.scala 432:27]
  wire [30:0] coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_ram_0_auto_tl_in_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_device_named_qspi_ram_0_auto_tl_in_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_qspi_ram_0_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_device_named_qspi_ram_0_auto_tl_in_d_bits_size; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_device_named_qspi_ram_0_auto_tl_in_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_device_named_qspi_ram_0_auto_tl_in_d_bits_data; // @[LazyModule.scala 432:27]
  ClockGroupAggregator_4 subsystem_mbus_clock_groups ( // @[BusWrapper.scala 40:48]
    .auto_in_member_subsystem_mbus_0_clock(subsystem_mbus_clock_groups_auto_in_member_subsystem_mbus_0_clock),
    .auto_in_member_subsystem_mbus_0_reset(subsystem_mbus_clock_groups_auto_in_member_subsystem_mbus_0_reset),
    .auto_out_member_subsystem_mbus_0_clock(subsystem_mbus_clock_groups_auto_out_member_subsystem_mbus_0_clock),
    .auto_out_member_subsystem_mbus_0_reset(subsystem_mbus_clock_groups_auto_out_member_subsystem_mbus_0_reset)
  );
  ClockGroup_4 clockGroup ( // @[BusWrapper.scala 41:38]
    .auto_in_member_subsystem_mbus_0_clock(clockGroup_auto_in_member_subsystem_mbus_0_clock),
    .auto_in_member_subsystem_mbus_0_reset(clockGroup_auto_in_member_subsystem_mbus_0_reset),
    .auto_out_clock(clockGroup_auto_out_clock),
    .auto_out_reset(clockGroup_auto_out_reset)
  );
  FixedClockBroadcast_2 fixedClockNode ( // @[ClockGroup.scala 106:107]
    .auto_in_clock(fixedClockNode_auto_in_clock),
    .auto_in_reset(fixedClockNode_auto_in_reset),
    .auto_out_clock(fixedClockNode_auto_out_clock),
    .auto_out_reset(fixedClockNode_auto_out_reset)
  );
  TLXbar_6 subsystem_mbus_xbar ( // @[MemoryBus.scala 42:32]
    .auto_in_a_ready(subsystem_mbus_xbar_auto_in_a_ready),
    .auto_in_a_valid(subsystem_mbus_xbar_auto_in_a_valid),
    .auto_in_a_bits_opcode(subsystem_mbus_xbar_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(subsystem_mbus_xbar_auto_in_a_bits_param),
    .auto_in_a_bits_size(subsystem_mbus_xbar_auto_in_a_bits_size),
    .auto_in_a_bits_source(subsystem_mbus_xbar_auto_in_a_bits_source),
    .auto_in_a_bits_address(subsystem_mbus_xbar_auto_in_a_bits_address),
    .auto_in_a_bits_mask(subsystem_mbus_xbar_auto_in_a_bits_mask),
    .auto_in_a_bits_data(subsystem_mbus_xbar_auto_in_a_bits_data),
    .auto_in_d_ready(subsystem_mbus_xbar_auto_in_d_ready),
    .auto_in_d_valid(subsystem_mbus_xbar_auto_in_d_valid),
    .auto_in_d_bits_opcode(subsystem_mbus_xbar_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(subsystem_mbus_xbar_auto_in_d_bits_size),
    .auto_in_d_bits_source(subsystem_mbus_xbar_auto_in_d_bits_source),
    .auto_in_d_bits_data(subsystem_mbus_xbar_auto_in_d_bits_data),
    .auto_out_a_ready(subsystem_mbus_xbar_auto_out_a_ready),
    .auto_out_a_valid(subsystem_mbus_xbar_auto_out_a_valid),
    .auto_out_a_bits_opcode(subsystem_mbus_xbar_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(subsystem_mbus_xbar_auto_out_a_bits_param),
    .auto_out_a_bits_size(subsystem_mbus_xbar_auto_out_a_bits_size),
    .auto_out_a_bits_source(subsystem_mbus_xbar_auto_out_a_bits_source),
    .auto_out_a_bits_address(subsystem_mbus_xbar_auto_out_a_bits_address),
    .auto_out_a_bits_mask(subsystem_mbus_xbar_auto_out_a_bits_mask),
    .auto_out_a_bits_data(subsystem_mbus_xbar_auto_out_a_bits_data),
    .auto_out_d_ready(subsystem_mbus_xbar_auto_out_d_ready),
    .auto_out_d_valid(subsystem_mbus_xbar_auto_out_d_valid),
    .auto_out_d_bits_opcode(subsystem_mbus_xbar_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(subsystem_mbus_xbar_auto_out_d_bits_size),
    .auto_out_d_bits_source(subsystem_mbus_xbar_auto_out_d_bits_source),
    .auto_out_d_bits_data(subsystem_mbus_xbar_auto_out_d_bits_data)
  );
  TLFIFOFixer_3 fixer ( // @[FIFOFixer.scala 144:27]
    .clock(fixer_clock),
    .reset(fixer_reset),
    .auto_in_a_ready(fixer_auto_in_a_ready),
    .auto_in_a_valid(fixer_auto_in_a_valid),
    .auto_in_a_bits_opcode(fixer_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(fixer_auto_in_a_bits_param),
    .auto_in_a_bits_size(fixer_auto_in_a_bits_size),
    .auto_in_a_bits_source(fixer_auto_in_a_bits_source),
    .auto_in_a_bits_address(fixer_auto_in_a_bits_address),
    .auto_in_a_bits_mask(fixer_auto_in_a_bits_mask),
    .auto_in_a_bits_data(fixer_auto_in_a_bits_data),
    .auto_in_d_ready(fixer_auto_in_d_ready),
    .auto_in_d_valid(fixer_auto_in_d_valid),
    .auto_in_d_bits_opcode(fixer_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(fixer_auto_in_d_bits_size),
    .auto_in_d_bits_source(fixer_auto_in_d_bits_source),
    .auto_in_d_bits_data(fixer_auto_in_d_bits_data),
    .auto_out_a_ready(fixer_auto_out_a_ready),
    .auto_out_a_valid(fixer_auto_out_a_valid),
    .auto_out_a_bits_opcode(fixer_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(fixer_auto_out_a_bits_param),
    .auto_out_a_bits_size(fixer_auto_out_a_bits_size),
    .auto_out_a_bits_source(fixer_auto_out_a_bits_source),
    .auto_out_a_bits_address(fixer_auto_out_a_bits_address),
    .auto_out_a_bits_mask(fixer_auto_out_a_bits_mask),
    .auto_out_a_bits_data(fixer_auto_out_a_bits_data),
    .auto_out_d_ready(fixer_auto_out_d_ready),
    .auto_out_d_valid(fixer_auto_out_d_valid),
    .auto_out_d_bits_opcode(fixer_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(fixer_auto_out_d_bits_size),
    .auto_out_d_bits_source(fixer_auto_out_d_bits_source),
    .auto_out_d_bits_data(fixer_auto_out_d_bits_data)
  );
  ProbePicker picker ( // @[ProbePicker.scala 65:28]
    .clock(picker_clock),
    .reset(picker_reset),
    .auto_in_a_ready(picker_auto_in_a_ready),
    .auto_in_a_valid(picker_auto_in_a_valid),
    .auto_in_a_bits_opcode(picker_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(picker_auto_in_a_bits_param),
    .auto_in_a_bits_size(picker_auto_in_a_bits_size),
    .auto_in_a_bits_source(picker_auto_in_a_bits_source),
    .auto_in_a_bits_address(picker_auto_in_a_bits_address),
    .auto_in_a_bits_mask(picker_auto_in_a_bits_mask),
    .auto_in_a_bits_data(picker_auto_in_a_bits_data),
    .auto_in_d_ready(picker_auto_in_d_ready),
    .auto_in_d_valid(picker_auto_in_d_valid),
    .auto_in_d_bits_opcode(picker_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(picker_auto_in_d_bits_size),
    .auto_in_d_bits_source(picker_auto_in_d_bits_source),
    .auto_in_d_bits_data(picker_auto_in_d_bits_data),
    .auto_out_a_ready(picker_auto_out_a_ready),
    .auto_out_a_valid(picker_auto_out_a_valid),
    .auto_out_a_bits_opcode(picker_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(picker_auto_out_a_bits_param),
    .auto_out_a_bits_size(picker_auto_out_a_bits_size),
    .auto_out_a_bits_source(picker_auto_out_a_bits_source),
    .auto_out_a_bits_address(picker_auto_out_a_bits_address),
    .auto_out_a_bits_mask(picker_auto_out_a_bits_mask),
    .auto_out_a_bits_data(picker_auto_out_a_bits_data),
    .auto_out_d_ready(picker_auto_out_d_ready),
    .auto_out_d_valid(picker_auto_out_d_valid),
    .auto_out_d_bits_opcode(picker_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(picker_auto_out_d_bits_size),
    .auto_out_d_bits_source(picker_auto_out_d_bits_source),
    .auto_out_d_bits_data(picker_auto_out_d_bits_data)
  );
  TLBuffer_7 buffer ( // @[Buffer.scala 68:28]
    .auto_in_a_ready(buffer_auto_in_a_ready),
    .auto_in_a_valid(buffer_auto_in_a_valid),
    .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
    .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
    .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
    .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
    .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
    .auto_in_a_bits_data(buffer_auto_in_a_bits_data),
    .auto_in_d_ready(buffer_auto_in_d_ready),
    .auto_in_d_valid(buffer_auto_in_d_valid),
    .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
    .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
    .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
    .auto_out_a_ready(buffer_auto_out_a_ready),
    .auto_out_a_valid(buffer_auto_out_a_valid),
    .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
    .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
    .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
    .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
    .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
    .auto_out_a_bits_data(buffer_auto_out_a_bits_data),
    .auto_out_d_ready(buffer_auto_out_d_ready),
    .auto_out_d_valid(buffer_auto_out_d_valid),
    .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
    .auto_out_d_bits_source(buffer_auto_out_d_bits_source),
    .auto_out_d_bits_data(buffer_auto_out_d_bits_data)
  );
  TLInterconnectCoupler_26 coupler_to_device_named_qspi_ram_0 ( // @[LazyModule.scala 432:27]
    .clock(coupler_to_device_named_qspi_ram_0_clock),
    .reset(coupler_to_device_named_qspi_ram_0_reset),
    .auto_mem_xing_out_a_ready(coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_a_ready),
    .auto_mem_xing_out_a_valid(coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_a_valid),
    .auto_mem_xing_out_a_bits_opcode(coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_a_bits_opcode),
    .auto_mem_xing_out_a_bits_param(coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_a_bits_param),
    .auto_mem_xing_out_a_bits_size(coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_a_bits_size),
    .auto_mem_xing_out_a_bits_source(coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_a_bits_source),
    .auto_mem_xing_out_a_bits_address(coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_a_bits_address),
    .auto_mem_xing_out_a_bits_mask(coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_a_bits_mask),
    .auto_mem_xing_out_a_bits_data(coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_a_bits_data),
    .auto_mem_xing_out_a_bits_corrupt(coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_a_bits_corrupt),
    .auto_mem_xing_out_d_ready(coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_d_ready),
    .auto_mem_xing_out_d_valid(coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_d_valid),
    .auto_mem_xing_out_d_bits_opcode(coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_d_bits_opcode),
    .auto_mem_xing_out_d_bits_size(coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_d_bits_size),
    .auto_mem_xing_out_d_bits_source(coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_d_bits_source),
    .auto_mem_xing_out_d_bits_data(coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_d_bits_data),
    .auto_tl_in_a_ready(coupler_to_device_named_qspi_ram_0_auto_tl_in_a_ready),
    .auto_tl_in_a_valid(coupler_to_device_named_qspi_ram_0_auto_tl_in_a_valid),
    .auto_tl_in_a_bits_opcode(coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_opcode),
    .auto_tl_in_a_bits_param(coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_param),
    .auto_tl_in_a_bits_size(coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_size),
    .auto_tl_in_a_bits_source(coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_source),
    .auto_tl_in_a_bits_address(coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_address),
    .auto_tl_in_a_bits_mask(coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_mask),
    .auto_tl_in_a_bits_data(coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_data),
    .auto_tl_in_d_ready(coupler_to_device_named_qspi_ram_0_auto_tl_in_d_ready),
    .auto_tl_in_d_valid(coupler_to_device_named_qspi_ram_0_auto_tl_in_d_valid),
    .auto_tl_in_d_bits_opcode(coupler_to_device_named_qspi_ram_0_auto_tl_in_d_bits_opcode),
    .auto_tl_in_d_bits_size(coupler_to_device_named_qspi_ram_0_auto_tl_in_d_bits_size),
    .auto_tl_in_d_bits_source(coupler_to_device_named_qspi_ram_0_auto_tl_in_d_bits_source),
    .auto_tl_in_d_bits_data(coupler_to_device_named_qspi_ram_0_auto_tl_in_d_bits_data)
  );
  assign auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_valid =
    coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_a_valid; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_opcode =
    coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_a_bits_opcode; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_param =
    coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_a_bits_param; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_size =
    coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_a_bits_size; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_source =
    coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_a_bits_source; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_address =
    coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_a_bits_address; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_mask =
    coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_a_bits_mask; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_data =
    coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_a_bits_data; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_corrupt =
    coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_a_bits_corrupt; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_d_ready =
    coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_d_ready; // @[LazyModule.scala 311:12]
  assign auto_bus_xing_in_a_ready = buffer_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_bus_xing_in_d_valid = buffer_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_bus_xing_in_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_bus_xing_in_d_bits_size = buffer_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_bus_xing_in_d_bits_source = buffer_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_bus_xing_in_d_bits_data = buffer_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign subsystem_mbus_clock_groups_auto_in_member_subsystem_mbus_0_clock =
    auto_subsystem_mbus_clock_groups_in_member_subsystem_mbus_0_clock; // @[LazyModule.scala 309:16]
  assign subsystem_mbus_clock_groups_auto_in_member_subsystem_mbus_0_reset =
    auto_subsystem_mbus_clock_groups_in_member_subsystem_mbus_0_reset; // @[LazyModule.scala 309:16]
  assign clockGroup_auto_in_member_subsystem_mbus_0_clock =
    subsystem_mbus_clock_groups_auto_out_member_subsystem_mbus_0_clock; // @[LazyModule.scala 298:16]
  assign clockGroup_auto_in_member_subsystem_mbus_0_reset =
    subsystem_mbus_clock_groups_auto_out_member_subsystem_mbus_0_reset; // @[LazyModule.scala 298:16]
  assign fixedClockNode_auto_in_clock = clockGroup_auto_out_clock; // @[LazyModule.scala 298:16]
  assign fixedClockNode_auto_in_reset = clockGroup_auto_out_reset; // @[LazyModule.scala 298:16]
  assign subsystem_mbus_xbar_auto_in_a_valid = fixer_auto_out_a_valid; // @[LazyModule.scala 296:16]
  assign subsystem_mbus_xbar_auto_in_a_bits_opcode = fixer_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign subsystem_mbus_xbar_auto_in_a_bits_param = fixer_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
  assign subsystem_mbus_xbar_auto_in_a_bits_size = fixer_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign subsystem_mbus_xbar_auto_in_a_bits_source = fixer_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign subsystem_mbus_xbar_auto_in_a_bits_address = fixer_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign subsystem_mbus_xbar_auto_in_a_bits_mask = fixer_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign subsystem_mbus_xbar_auto_in_a_bits_data = fixer_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign subsystem_mbus_xbar_auto_in_d_ready = fixer_auto_out_d_ready; // @[LazyModule.scala 296:16]
  assign subsystem_mbus_xbar_auto_out_a_ready = picker_auto_in_a_ready; // @[LazyModule.scala 298:16]
  assign subsystem_mbus_xbar_auto_out_d_valid = picker_auto_in_d_valid; // @[LazyModule.scala 298:16]
  assign subsystem_mbus_xbar_auto_out_d_bits_opcode = picker_auto_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign subsystem_mbus_xbar_auto_out_d_bits_size = picker_auto_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign subsystem_mbus_xbar_auto_out_d_bits_source = picker_auto_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign subsystem_mbus_xbar_auto_out_d_bits_data = picker_auto_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign fixer_clock = fixedClockNode_auto_out_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign fixer_reset = fixedClockNode_auto_out_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign fixer_auto_in_a_valid = buffer_auto_out_a_valid; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_param = buffer_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_size = buffer_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_source = buffer_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_address = buffer_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_a_bits_data = buffer_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign fixer_auto_in_d_ready = buffer_auto_out_d_ready; // @[LazyModule.scala 296:16]
  assign fixer_auto_out_a_ready = subsystem_mbus_xbar_auto_in_a_ready; // @[LazyModule.scala 296:16]
  assign fixer_auto_out_d_valid = subsystem_mbus_xbar_auto_in_d_valid; // @[LazyModule.scala 296:16]
  assign fixer_auto_out_d_bits_opcode = subsystem_mbus_xbar_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign fixer_auto_out_d_bits_size = subsystem_mbus_xbar_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
  assign fixer_auto_out_d_bits_source = subsystem_mbus_xbar_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
  assign fixer_auto_out_d_bits_data = subsystem_mbus_xbar_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
  assign picker_clock = fixedClockNode_auto_out_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign picker_reset = fixedClockNode_auto_out_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign picker_auto_in_a_valid = subsystem_mbus_xbar_auto_out_a_valid; // @[LazyModule.scala 298:16]
  assign picker_auto_in_a_bits_opcode = subsystem_mbus_xbar_auto_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign picker_auto_in_a_bits_param = subsystem_mbus_xbar_auto_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign picker_auto_in_a_bits_size = subsystem_mbus_xbar_auto_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign picker_auto_in_a_bits_source = subsystem_mbus_xbar_auto_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign picker_auto_in_a_bits_address = subsystem_mbus_xbar_auto_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign picker_auto_in_a_bits_mask = subsystem_mbus_xbar_auto_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign picker_auto_in_a_bits_data = subsystem_mbus_xbar_auto_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign picker_auto_in_d_ready = subsystem_mbus_xbar_auto_out_d_ready; // @[LazyModule.scala 298:16]
  assign picker_auto_out_a_ready = coupler_to_device_named_qspi_ram_0_auto_tl_in_a_ready; // @[LazyModule.scala 298:16]
  assign picker_auto_out_d_valid = coupler_to_device_named_qspi_ram_0_auto_tl_in_d_valid; // @[LazyModule.scala 298:16]
  assign picker_auto_out_d_bits_opcode = coupler_to_device_named_qspi_ram_0_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign picker_auto_out_d_bits_size = coupler_to_device_named_qspi_ram_0_auto_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign picker_auto_out_d_bits_source = coupler_to_device_named_qspi_ram_0_auto_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign picker_auto_out_d_bits_data = coupler_to_device_named_qspi_ram_0_auto_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign buffer_auto_in_a_valid = auto_bus_xing_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_opcode = auto_bus_xing_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_param = auto_bus_xing_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_size = auto_bus_xing_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_source = auto_bus_xing_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_address = auto_bus_xing_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_mask = auto_bus_xing_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_data = auto_bus_xing_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_d_ready = auto_bus_xing_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_out_a_ready = fixer_auto_in_a_ready; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_valid = fixer_auto_in_d_valid; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_opcode = fixer_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_size = fixer_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_source = fixer_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_data = fixer_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
  assign coupler_to_device_named_qspi_ram_0_clock = fixedClockNode_auto_out_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_device_named_qspi_ram_0_reset = fixedClockNode_auto_out_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_a_ready =
    auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_ready; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_d_valid =
    auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_d_valid; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_d_bits_opcode =
    auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_d_bits_opcode; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_d_bits_size =
    auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_d_bits_size; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_d_bits_source =
    auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_d_bits_source; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_qspi_ram_0_auto_mem_xing_out_d_bits_data =
    auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_d_bits_data; // @[LazyModule.scala 311:12]
  assign coupler_to_device_named_qspi_ram_0_auto_tl_in_a_valid = picker_auto_out_a_valid; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_opcode = picker_auto_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_param = picker_auto_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_size = picker_auto_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_source = picker_auto_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_address = picker_auto_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_mask = picker_auto_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_ram_0_auto_tl_in_a_bits_data = picker_auto_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign coupler_to_device_named_qspi_ram_0_auto_tl_in_d_ready = picker_auto_out_d_ready; // @[LazyModule.scala 298:16]
endmodule
module ClockGroupAggregator_5(
  input   auto_in_member_subsystem_l2_1_clock,
  input   auto_in_member_subsystem_l2_1_reset,
  input   auto_in_member_subsystem_l2_0_clock,
  input   auto_in_member_subsystem_l2_0_reset,
  output  auto_out_1_member_subsystem_mbus_0_clock,
  output  auto_out_1_member_subsystem_mbus_0_reset,
  output  auto_out_0_member_subsystem_l2_0_clock,
  output  auto_out_0_member_subsystem_l2_0_reset
);
  assign auto_out_1_member_subsystem_mbus_0_clock = auto_in_member_subsystem_l2_1_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_member_subsystem_mbus_0_reset = auto_in_member_subsystem_l2_1_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_0_member_subsystem_l2_0_clock = auto_in_member_subsystem_l2_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_0_member_subsystem_l2_0_reset = auto_in_member_subsystem_l2_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module ClockGroup_5(
  input   auto_in_member_subsystem_l2_0_clock,
  input   auto_in_member_subsystem_l2_0_reset,
  output  auto_out_clock,
  output  auto_out_reset
);
  assign auto_out_clock = auto_in_member_subsystem_l2_0_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_reset = auto_in_member_subsystem_l2_0_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module TLMonitor_41(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [30:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_b_ready,
  input         io_in_b_valid,
  input  [1:0]  io_in_b_bits_param,
  input  [30:0] io_in_b_bits_address,
  input         io_in_c_ready,
  input         io_in_c_valid,
  input  [2:0]  io_in_c_bits_opcode,
  input  [2:0]  io_in_c_bits_param,
  input  [2:0]  io_in_c_bits_size,
  input  [1:0]  io_in_c_bits_source,
  input  [30:0] io_in_c_bits_address,
  input         io_in_c_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_param,
  input  [2:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source,
  input  [1:0]  io_in_d_bits_sink,
  input         io_in_e_valid,
  input  [1:0]  io_in_e_bits_sink
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [31:0] _RAND_33;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
  wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
  wire [30:0] _GEN_86 = {{25'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [30:0] _is_aligned_T = io_in_a_bits_address & _GEN_86; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 31'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire  _T_45 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
  wire [30:0] _T_48 = io_in_a_bits_address ^ 31'h40000000; // @[Parameters.scala 137:31]
  wire [31:0] _T_49 = {1'b0,$signed(_T_48)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_51 = $signed(_T_49) & -32'sh20000000; // @[Parameters.scala 137:52]
  wire  _T_52 = $signed(_T_51) == 32'sh0; // @[Parameters.scala 137:67]
  wire  _T_53 = _T_45 & _T_52; // @[Parameters.scala 670:56]
  wire  _T_55 = source_ok & _T_53; // @[Monitor.scala 82:72]
  wire  _T_62 = 3'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_63 = _source_ok_T & _T_62; // @[Mux.scala 27:73]
  wire  _T_79 = _T_63 & _T_52; // @[Monitor.scala 83:78]
  wire  _T_93 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_97 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_98 = _T_97 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_102 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_106 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_170 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_183 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_217 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_221 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_229 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_269 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_302 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_303 = io_in_a_bits_mask & _T_302; // @[Monitor.scala 127:31]
  wire  _T_304 = _T_303 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_308 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_337 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_345 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_374 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_382 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_411 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_423 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  _T_427 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_431 = io_in_d_bits_size >= 3'h2; // @[Monitor.scala 312:27]
  wire  _T_435 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
  wire  _T_447 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_458 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
  wire  _T_462 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
  wire  _T_475 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_504 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_521 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_539 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire [30:0] _address_ok_T = io_in_b_bits_address ^ 31'h40000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_1 = {1'b0,$signed(_address_ok_T)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_3 = $signed(_address_ok_T_1) & -32'sh20000000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_4 = $signed(_address_ok_T_3) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _is_aligned_T_1 = io_in_b_bits_address & 31'h3f; // @[Edges.scala 20:16]
  wire  is_aligned_1 = _is_aligned_T_1 == 31'h0; // @[Edges.scala 20:24]
  wire  _T_623 = io_in_b_bits_param <= 2'h2; // @[Bundles.scala 102:26]
  wire  _source_ok_T_8 = io_in_c_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_9 = io_in_c_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_10 = io_in_c_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_2 = _source_ok_T_8 | _source_ok_T_9 | _source_ok_T_10; // @[Parameters.scala 1125:46]
  wire [12:0] _is_aligned_mask_T_7 = 13'h3f << io_in_c_bits_size; // @[package.scala 234:77]
  wire [5:0] is_aligned_mask_2 = ~_is_aligned_mask_T_7[5:0]; // @[package.scala 234:46]
  wire [30:0] _GEN_87 = {{25'd0}, is_aligned_mask_2}; // @[Edges.scala 20:16]
  wire [30:0] _is_aligned_T_2 = io_in_c_bits_address & _GEN_87; // @[Edges.scala 20:16]
  wire  is_aligned_2 = _is_aligned_T_2 == 31'h0; // @[Edges.scala 20:24]
  wire [30:0] _address_ok_T_5 = io_in_c_bits_address ^ 31'h40000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_6 = {1'b0,$signed(_address_ok_T_5)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_8 = $signed(_address_ok_T_6) & -32'sh20000000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_9 = $signed(_address_ok_T_8) == 32'sh0; // @[Parameters.scala 137:67]
  wire  _T_872 = io_in_c_bits_opcode == 3'h4; // @[Monitor.scala 242:25]
  wire  _T_879 = io_in_c_bits_size >= 3'h2; // @[Monitor.scala 245:30]
  wire  _T_886 = io_in_c_bits_param <= 3'h5; // @[Bundles.scala 120:29]
  wire  _T_890 = ~io_in_c_bits_corrupt; // @[Monitor.scala 248:18]
  wire  _T_894 = io_in_c_bits_opcode == 3'h5; // @[Monitor.scala 251:25]
  wire  _T_912 = io_in_c_bits_opcode == 3'h6; // @[Monitor.scala 259:25]
  wire  _T_924 = io_in_c_bits_size <= 3'h6; // @[Parameters.scala 92:42]
  wire  _T_932 = _T_924 & _address_ok_T_9; // @[Parameters.scala 670:56]
  wire  _T_934 = source_ok_2 & _T_932; // @[Monitor.scala 260:78]
  wire  _T_941 = 3'h6 == io_in_c_bits_size; // @[Parameters.scala 91:48]
  wire  _T_942 = _source_ok_T_8 & _T_941; // @[Mux.scala 27:73]
  wire  _T_958 = _T_942 & _address_ok_T_9; // @[Monitor.scala 261:78]
  wire  _T_980 = io_in_c_bits_opcode == 3'h7; // @[Monitor.scala 269:25]
  wire  _T_1044 = io_in_c_bits_opcode == 3'h0; // @[Monitor.scala 278:25]
  wire  _T_1054 = io_in_c_bits_param == 3'h0; // @[Monitor.scala 282:31]
  wire  _T_1062 = io_in_c_bits_opcode == 3'h1; // @[Monitor.scala 286:25]
  wire  _T_1076 = io_in_c_bits_opcode == 3'h2; // @[Monitor.scala 293:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [3:0] a_first_beats1_decode = is_aligned_mask[5:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] a_first_counter; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1 = a_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [30:0] address; // @[Monitor.scala 388:22]
  wire  _T_1098 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_1099 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_1103 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_1107 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_1111 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_1115 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
  wire [3:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [3:0] d_first_counter; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1 = d_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] param_1; // @[Monitor.scala 536:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  reg [1:0] sink; // @[Monitor.scala 539:22]
  wire  _T_1122 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_1123 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_1127 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
  wire  _T_1131 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_1135 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  wire  _T_1139 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
  wire  b_first_done = io_in_b_ready & io_in_b_valid; // @[Decoupled.scala 50:35]
  reg [3:0] b_first_counter; // @[Edges.scala 228:27]
  wire [3:0] b_first_counter1 = b_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  b_first = b_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [1:0] param_2; // @[Monitor.scala 408:22]
  reg [30:0] address_1; // @[Monitor.scala 411:22]
  wire  _T_1150 = io_in_b_valid & ~b_first; // @[Monitor.scala 412:19]
  wire  _T_1155 = io_in_b_bits_param == param_2; // @[Monitor.scala 414:32]
  wire  _T_1167 = io_in_b_bits_address == address_1; // @[Monitor.scala 417:32]
  wire  _c_first_T = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala 50:35]
  wire [3:0] c_first_beats1_decode = is_aligned_mask_2[5:2]; // @[Edges.scala 219:59]
  wire  c_first_beats1_opdata = io_in_c_bits_opcode[0]; // @[Edges.scala 101:36]
  reg [3:0] c_first_counter; // @[Edges.scala 228:27]
  wire [3:0] c_first_counter1 = c_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  c_first = c_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_3; // @[Monitor.scala 512:22]
  reg [2:0] param_3; // @[Monitor.scala 513:22]
  reg [2:0] size_3; // @[Monitor.scala 514:22]
  reg [1:0] source_3; // @[Monitor.scala 515:22]
  reg [30:0] address_2; // @[Monitor.scala 516:22]
  wire  _T_1174 = io_in_c_valid & ~c_first; // @[Monitor.scala 517:19]
  wire  _T_1175 = io_in_c_bits_opcode == opcode_3; // @[Monitor.scala 518:32]
  wire  _T_1179 = io_in_c_bits_param == param_3; // @[Monitor.scala 519:32]
  wire  _T_1183 = io_in_c_bits_size == size_3; // @[Monitor.scala 520:32]
  wire  _T_1187 = io_in_c_bits_source == source_3; // @[Monitor.scala 521:32]
  wire  _T_1191 = io_in_c_bits_address == address_2; // @[Monitor.scala 522:32]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [11:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [3:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1_1 = a_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  reg [3:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_1 = d_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_88 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_88}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_89 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_89 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [11:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _GEN_92 = {{4'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_92 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_1197 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _GEN_27 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_1200 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_94 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_94}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [34:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [34:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_1202 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_1204 = ~_T_1202[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_28 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_31 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [34:0] _GEN_32 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_1208 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_1210 = ~_T_427; // @[Monitor.scala 671:74]
  wire  _T_1211 = io_in_d_valid & d_first_1 & ~_T_427; // @[Monitor.scala 671:71]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _GEN_33 = io_in_d_valid & d_first_1 & ~_T_427 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 671:90 672:22]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [3:0] _GEN_34 = _d_first_T & d_first_1 & _T_1210 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_35 = _d_first_T & d_first_1 & _T_1210 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_1197 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_1221 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_1223 = _T_1221[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_39 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_40 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_39; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_41 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_40; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_42 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_41; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_43 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_42; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_44 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_43; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_51 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_42; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_52 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_51; // @[Monitor.scala 686:{39,39}]
  wire  _T_1228 = io_in_d_bits_opcode == _GEN_52; // @[Monitor.scala 686:39]
  wire  _T_1229 = io_in_d_bits_opcode == _GEN_44 | _T_1228; // @[Monitor.scala 685:77]
  wire  _T_1233 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_55 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_56 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_55; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_57 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_56; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_58 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_57; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_59 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_58; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_60 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_59; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_67 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_58; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_68 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_67; // @[Monitor.scala 690:{38,38}]
  wire  _T_1240 = io_in_d_bits_opcode == _GEN_68; // @[Monitor.scala 690:38]
  wire  _T_1241 = io_in_d_bits_opcode == _GEN_60 | _T_1240; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_98 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_1245 = _GEN_98 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_1255 = _T_1208 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_1210; // @[Monitor.scala 694:116]
  wire  _T_1256 = ~io_in_d_ready; // @[Monitor.scala 695:15]
  wire  _T_1257 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set_wo_ready = _GEN_27[2:0];
  wire [2:0] d_clr_wo_ready = _GEN_33[2:0];
  wire  _T_1264 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire [2:0] a_set = _GEN_28[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_34[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_31[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_35[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [11:0] a_sizes_set = _GEN_32[11:0];
  wire [11:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [11:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_1273 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [2:0] inflight_1; // @[Monitor.scala 723:35]
  reg [11:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [3:0] c_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] c_first_counter1_1 = c_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  c_first_1 = c_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  reg [3:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_2 = d_first_counter_2 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 4'h0; // @[Edges.scala 230:25]
  wire [11:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [15:0] _GEN_103 = {{4'd0}, _c_size_lookup_T_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_103 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_1283 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala 67:40]
  wire  _T_1284 = io_in_c_valid & c_first_1 & _T_1283; // @[Monitor.scala 756:37]
  wire [3:0] _c_set_wo_ready_T = 4'h1 << io_in_c_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _GEN_72 = io_in_c_valid & c_first_1 & _T_1283 ? _c_set_wo_ready_T : 4'h0; // @[Monitor.scala 756:71 757:22]
  wire  _T_1290 = _c_first_T & c_first_1 & _T_1283; // @[Monitor.scala 760:38]
  wire [3:0] _c_sizes_set_interm_T = {io_in_c_bits_size, 1'h0}; // @[Monitor.scala 763:51]
  wire [3:0] _c_sizes_set_interm_T_1 = _c_sizes_set_interm_T | 4'h1; // @[Monitor.scala 763:59]
  wire [3:0] _GEN_105 = {io_in_c_bits_source, 2'h0}; // @[Monitor.scala 764:79]
  wire [4:0] _c_opcodes_set_T = {{1'd0}, _GEN_105}; // @[Monitor.scala 764:79]
  wire [3:0] c_sizes_set_interm = _c_first_T & c_first_1 & _T_1283 ? _c_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 760:72 763:28]
  wire [34:0] _GEN_4 = {{31'd0}, c_sizes_set_interm}; // @[Monitor.scala 765:52]
  wire [34:0] _c_sizes_set_T_1 = _GEN_4 << _c_opcodes_set_T; // @[Monitor.scala 765:52]
  wire [2:0] _T_1291 = inflight_1 >> io_in_c_bits_source; // @[Monitor.scala 766:26]
  wire  _T_1293 = ~_T_1291[0]; // @[Monitor.scala 766:17]
  wire [3:0] _GEN_73 = _c_first_T & c_first_1 & _T_1283 ? _c_set_wo_ready_T : 4'h0; // @[Monitor.scala 760:72 761:28]
  wire [34:0] _GEN_77 = _c_first_T & c_first_1 & _T_1283 ? _c_sizes_set_T_1 : 35'h0; // @[Monitor.scala 760:72 765:28]
  wire  _T_1297 = io_in_d_valid & d_first_2; // @[Monitor.scala 779:26]
  wire  _T_1299 = io_in_d_valid & d_first_2 & _T_427; // @[Monitor.scala 779:71]
  wire [3:0] _GEN_78 = io_in_d_valid & d_first_2 & _T_427 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 779:89 780:22]
  wire [3:0] _GEN_79 = _d_first_T & d_first_2 & _T_427 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 783:90 784:21]
  wire [46:0] _GEN_80 = _d_first_T & d_first_2 & _T_427 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 785:21]
  wire  _same_cycle_resp_T_8 = io_in_c_bits_source == io_in_d_bits_source; // @[Monitor.scala 790:113]
  wire  same_cycle_resp_1 = _T_1284 & io_in_c_bits_source == io_in_d_bits_source; // @[Monitor.scala 790:88]
  wire [2:0] _T_1307 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire  _T_1309 = _T_1307[0] | same_cycle_resp_1; // @[Monitor.scala 791:49]
  wire  _T_1313 = io_in_d_bits_size == io_in_c_bits_size; // @[Monitor.scala 793:36]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_1317 = _GEN_98 == c_size_lookup; // @[Monitor.scala 795:36]
  wire  _T_1326 = _T_1297 & c_first_1 & io_in_c_valid & _same_cycle_resp_T_8 & _T_427; // @[Monitor.scala 799:116]
  wire  _T_1328 = _T_1256 | io_in_c_ready; // @[Monitor.scala 800:32]
  wire [2:0] c_set_wo_ready = _GEN_72[2:0];
  wire  _T_1332 = |c_set_wo_ready; // @[Monitor.scala 804:28]
  wire [2:0] d_clr_wo_ready_1 = _GEN_78[2:0];
  wire  _T_1333 = c_set_wo_ready != d_clr_wo_ready_1; // @[Monitor.scala 805:31]
  wire [2:0] c_set = _GEN_73[2:0];
  wire [2:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala 809:35]
  wire [2:0] d_clr_1 = _GEN_79[2:0];
  wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [2:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [11:0] d_opcodes_clr_1 = _GEN_80[11:0];
  wire [11:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [11:0] c_sizes_set = _GEN_77[11:0];
  wire [11:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala 811:41]
  wire [11:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_1342 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  reg [3:0] inflight_2; // @[Monitor.scala 823:27]
  reg [3:0] d_first_counter_3; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_3 = d_first_counter_3 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_3 = d_first_counter_3 == 4'h0; // @[Edges.scala 230:25]
  wire  _T_1354 = io_in_d_bits_opcode[2] & ~io_in_d_bits_opcode[1]; // @[Edges.scala 70:40]
  wire  _T_1355 = _d_first_T & d_first_3 & _T_1354; // @[Monitor.scala 829:38]
  wire [3:0] _d_set_T = 4'h1 << io_in_d_bits_sink; // @[OneHot.scala 57:35]
  wire [3:0] _T_1356 = inflight_2 >> io_in_d_bits_sink; // @[Monitor.scala 831:23]
  wire  _T_1358 = ~_T_1356[0]; // @[Monitor.scala 831:14]
  wire [3:0] d_set = _d_first_T & d_first_3 & _T_1354 ? _d_set_T : 4'h0; // @[Monitor.scala 829:72 830:13]
  wire [3:0] _e_clr_T = 4'h1 << io_in_e_bits_sink; // @[OneHot.scala 57:35]
  wire [3:0] _T_1365 = d_set | inflight_2; // @[Monitor.scala 837:24]
  wire [3:0] _T_1366 = _T_1365 >> io_in_e_bits_sink; // @[Monitor.scala 837:35]
  wire [3:0] e_clr = io_in_e_valid ? _e_clr_T : 4'h0; // @[Monitor.scala 835:73 836:13]
  wire [3:0] _inflight_T_6 = inflight_2 | d_set; // @[Monitor.scala 842:27]
  wire [3:0] _inflight_T_7 = ~e_clr; // @[Monitor.scala 842:38]
  wire [3:0] _inflight_T_8 = _inflight_T_6 & _inflight_T_7; // @[Monitor.scala 842:36]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 4'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 4'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      b_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (b_first_done) begin // @[Edges.scala 234:17]
      if (b_first) begin // @[Edges.scala 235:21]
        b_first_counter <= 4'h0;
      end else begin
        b_first_counter <= b_first_counter1;
      end
    end
    if (b_first_done & b_first) begin // @[Monitor.scala 419:32]
      param_2 <= io_in_b_bits_param; // @[Monitor.scala 421:15]
    end
    if (b_first_done & b_first) begin // @[Monitor.scala 419:32]
      address_1 <= io_in_b_bits_address; // @[Monitor.scala 424:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      c_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_c_first_T) begin // @[Edges.scala 234:17]
      if (c_first) begin // @[Edges.scala 235:21]
        if (c_first_beats1_opdata) begin // @[Edges.scala 220:14]
          c_first_counter <= c_first_beats1_decode;
        end else begin
          c_first_counter <= 4'h0;
        end
      end else begin
        c_first_counter <= c_first_counter1;
      end
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      opcode_3 <= io_in_c_bits_opcode; // @[Monitor.scala 525:15]
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      param_3 <= io_in_c_bits_param; // @[Monitor.scala 526:15]
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      size_3 <= io_in_c_bits_size; // @[Monitor.scala 527:15]
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      source_3 <= io_in_c_bits_source; // @[Monitor.scala 528:15]
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      address_2 <= io_in_c_bits_address; // @[Monitor.scala 529:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 12'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 4'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 4'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 3'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 12'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      c_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_c_first_T) begin // @[Edges.scala 234:17]
      if (c_first_1) begin // @[Edges.scala 235:21]
        if (c_first_beats1_opdata) begin // @[Edges.scala 220:14]
          c_first_counter_1 <= c_first_beats1_decode;
        end else begin
          c_first_counter_1 <= 4'h0;
        end
      end else begin
        c_first_counter_1 <= c_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 4'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_c_first_T | _d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    if (reset) begin // @[Monitor.scala 823:27]
      inflight_2 <= 4'h0; // @[Monitor.scala 823:27]
    end else begin
      inflight_2 <= _inflight_T_8; // @[Monitor.scala 842:14]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_3 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_3) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_3 <= d_first_beats1_decode;
        end else begin
          d_first_counter_3 <= 4'h0;
        end
      end else begin
        d_first_counter_3 <= d_first_counter1_3;
      end
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_55 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_55) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_79 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_79) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_93 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_93) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_98 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_98) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_102 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_102) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_55 & (io_in_a_valid & _T_106 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_106 & ~reset & ~_T_55) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_79 & (io_in_a_valid & _T_106 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_106 & ~reset & ~_T_79) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_106 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_106 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_106 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_106 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_106 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_106 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_93 & (io_in_a_valid & _T_106 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_106 & ~reset & ~_T_93) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_170 & (io_in_a_valid & _T_106 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_106 & ~reset & ~_T_170) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_98 & (io_in_a_valid & _T_106 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_106 & ~reset & ~_T_98) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_102 & (io_in_a_valid & _T_106 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_106 & ~reset & ~_T_102) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_183 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_183 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_53 & (io_in_a_valid & _T_183 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_183 & ~reset & ~_T_53) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_183 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_183 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_183 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_183 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_217 & (io_in_a_valid & _T_183 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_183 & ~reset & ~_T_217) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_221 & (io_in_a_valid & _T_183 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_183 & ~reset & ~_T_221) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_102 & (io_in_a_valid & _T_183 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_183 & ~reset & ~_T_102) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_55 & (io_in_a_valid & _T_229 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_229 & ~reset & ~_T_55) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_229 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_229 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_229 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_229 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_217 & (io_in_a_valid & _T_229 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_229 & ~reset & ~_T_217) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_221 & (io_in_a_valid & _T_229 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_229 & ~reset & ~_T_221) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_269 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_269 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_269 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_269 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_269 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_269 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_217 & (io_in_a_valid & _T_269 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_269 & ~reset & ~_T_217) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_304 & (io_in_a_valid & _T_269 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_269 & ~reset & ~_T_304) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_308 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_308 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_308 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_308 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_308 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_308 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_337 & (io_in_a_valid & _T_308 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_308 & ~reset & ~_T_337) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_221 & (io_in_a_valid & _T_308 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_308 & ~reset & ~_T_221) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_374 & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~_T_374) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_221 & (io_in_a_valid & _T_345 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_345 & ~reset & ~_T_221) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_382 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_382 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_382 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_382 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_382 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_382 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_411 & (io_in_a_valid & _T_382 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_382 & ~reset & ~_T_411) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_221 & (io_in_a_valid & _T_382 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_382 & ~reset & ~_T_221) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_102 & (io_in_a_valid & _T_382 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_382 & ~reset & ~_T_102) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_423 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_423) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_427 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_427 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_431 & (io_in_d_valid & _T_427 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_427 & _T_2 & ~_T_431) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_435 & (io_in_d_valid & _T_427 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_427 & _T_2 & ~_T_435) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_447 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_447 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_431 & (io_in_d_valid & _T_447 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_447 & _T_2 & ~_T_431) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_458 & (io_in_d_valid & _T_447 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_447 & _T_2 & ~_T_458) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid cap param (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_462 & (io_in_d_valid & _T_447 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_447 & _T_2 & ~_T_462) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries toN param (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_475 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_475 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_431 & (io_in_d_valid & _T_475 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_475 & _T_2 & ~_T_431) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_458 & (io_in_d_valid & _T_475 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_475 & _T_2 & ~_T_458) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_462 & (io_in_d_valid & _T_475 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_475 & _T_2 & ~_T_462) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries toN param (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_504 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_504 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_435 & (io_in_d_valid & _T_504 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_504 & _T_2 & ~_T_435) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid param (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_521 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_521 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_435 & (io_in_d_valid & _T_521 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_521 & _T_2 & ~_T_435) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_539 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_539 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_435 & (io_in_d_valid & _T_539 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_539 & _T_2 & ~_T_435) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid param (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_4 & (io_in_b_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2 & ~_address_ok_T_4) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_4 & (io_in_b_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2 & ~_address_ok_T_4) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Probe carries unmanaged address (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_1 & (io_in_b_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2 & ~is_aligned_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Probe address not aligned to size (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_623 & (io_in_b_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2 & ~_T_623) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Probe carries invalid cap param (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_9 & (io_in_c_valid & _T_872 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_872 & ~reset & ~_address_ok_T_9) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_2 & (io_in_c_valid & _T_872 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_872 & ~reset & ~source_ok_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_879 & (io_in_c_valid & _T_872 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_872 & ~reset & ~_T_879) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_872 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_872 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_886 & (io_in_c_valid & _T_872 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_872 & ~reset & ~_T_886) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_890 & (io_in_c_valid & _T_872 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_872 & ~reset & ~_T_890) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck is corrupt (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_9 & (io_in_c_valid & _T_894 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_894 & ~reset & ~_address_ok_T_9) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_2 & (io_in_c_valid & _T_894 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_894 & ~reset & ~source_ok_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_879 & (io_in_c_valid & _T_894 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_894 & ~reset & ~_T_879) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_894 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_894 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_886 & (io_in_c_valid & _T_894 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_894 & ~reset & ~_T_886) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_934 & (io_in_c_valid & _T_912 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_912 & ~reset & ~_T_934) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_958 & (io_in_c_valid & _T_912 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_912 & ~reset & ~_T_958) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_2 & (io_in_c_valid & _T_912 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_912 & ~reset & ~source_ok_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release carries invalid source ID (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_879 & (io_in_c_valid & _T_912 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_912 & ~reset & ~_T_879) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release smaller than a beat (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_912 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_912 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release address not aligned to size (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_886 & (io_in_c_valid & _T_912 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_912 & ~reset & ~_T_886) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release carries invalid report param (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_890 & (io_in_c_valid & _T_912 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_912 & ~reset & ~_T_890) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release is corrupt (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_934 & (io_in_c_valid & _T_980 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_980 & ~reset & ~_T_934) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_958 & (io_in_c_valid & _T_980 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_980 & ~reset & ~_T_958) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_2 & (io_in_c_valid & _T_980 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_980 & ~reset & ~source_ok_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_879 & (io_in_c_valid & _T_980 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_980 & ~reset & ~_T_879) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_980 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_980 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_886 & (io_in_c_valid & _T_980 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_980 & ~reset & ~_T_886) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_9 & (io_in_c_valid & _T_1044 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1044 & ~reset & ~_address_ok_T_9) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_2 & (io_in_c_valid & _T_1044 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1044 & ~reset & ~source_ok_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_1044 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1044 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1054 & (io_in_c_valid & _T_1044 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1044 & ~reset & ~_T_1054) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck carries invalid param (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_890 & (io_in_c_valid & _T_1044 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1044 & ~reset & ~_T_890) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck is corrupt (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_9 & (io_in_c_valid & _T_1062 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1062 & ~reset & ~_address_ok_T_9) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_2 & (io_in_c_valid & _T_1062 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1062 & ~reset & ~source_ok_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_1062 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1062 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1054 & (io_in_c_valid & _T_1062 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1062 & ~reset & ~_T_1054) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_address_ok_T_9 & (io_in_c_valid & _T_1076 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1076 & ~reset & ~_address_ok_T_9) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_2 & (io_in_c_valid & _T_1076 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1076 & ~reset & ~source_ok_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_1076 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1076 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck address not aligned to size (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1054 & (io_in_c_valid & _T_1076 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1076 & ~reset & ~_T_1054) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck carries invalid param (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_890 & (io_in_c_valid & _T_1076 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_1076 & ~reset & ~_T_890) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck is corrupt (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1099 & (_T_1098 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1098 & ~reset & ~_T_1099) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1103 & (_T_1098 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1098 & ~reset & ~_T_1103) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1107 & (_T_1098 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1098 & ~reset & ~_T_1107) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1111 & (_T_1098 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1098 & ~reset & ~_T_1111) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1115 & (_T_1098 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1098 & ~reset & ~_T_1115) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1123 & (_T_1122 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1122 & _T_2 & ~_T_1123) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1127 & (_T_1122 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1122 & _T_2 & ~_T_1127) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel param changed within multibeat operation (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1131 & (_T_1122 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1122 & _T_2 & ~_T_1131) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1135 & (_T_1122 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1122 & _T_2 & ~_T_1135) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1139 & (_T_1122 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1122 & _T_2 & ~_T_1139) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel sink changed with multibeat operation (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1155 & (_T_1150 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1150 & ~reset & ~_T_1155) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel param changed within multibeat operation (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1167 & (_T_1150 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1150 & ~reset & ~_T_1167) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1175 & (_T_1174 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1174 & ~reset & ~_T_1175) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1179 & (_T_1174 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1174 & ~reset & ~_T_1179) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel param changed within multibeat operation (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1183 & (_T_1174 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1174 & ~reset & ~_T_1183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel size changed within multibeat operation (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1187 & (_T_1174 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1174 & ~reset & ~_T_1187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel source changed within multibeat operation (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1191 & (_T_1174 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1174 & ~reset & ~_T_1191) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel address changed with multibeat operation (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1204 & (_T_1200 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1200 & ~reset & ~_T_1204) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1223 & (_T_1211 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1211 & _T_2 & ~_T_1223) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1229 & (_T_1211 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1211 & same_cycle_resp & _T_2 & ~_T_1229) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1233 & (_T_1211 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1211 & same_cycle_resp & _T_2 & ~_T_1233) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1241 & (_T_1211 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1211 & ~same_cycle_resp & _T_2 & ~_T_1241) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1245 & (_T_1211 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1211 & ~same_cycle_resp & _T_2 & ~_T_1245) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1257 & (_T_1255 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1255 & _T_2 & ~_T_1257) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1264 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_1264) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1273 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_1273) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1293 & (_T_1290 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1290 & ~reset & ~_T_1293) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel re-used a source ID (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1309 & (_T_1299 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1299 & _T_2 & ~_T_1309) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1313 & (_T_1299 & same_cycle_resp_1 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1299 & same_cycle_resp_1 & _T_2 & ~_T_1313) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1317 & (_T_1299 & ~same_cycle_resp_1 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1299 & ~same_cycle_resp_1 & _T_2 & ~_T_1317) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1328 & (_T_1326 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1326 & _T_2 & ~_T_1328) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1333 & (_T_1332 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1332 & _T_2 & ~_T_1333) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' and 'D' concurrent, despite minlatency 1 (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1342 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_1342) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1358 & (_T_1355 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1355 & _T_2 & ~_T_1358) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel re-used a sink ID (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1366[0] & (io_in_e_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_e_valid & ~reset & ~_T_1366[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at BankedL2Params.scala:60:27)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[30:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  param_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  size_1 = _RAND_9[2:0];
  _RAND_10 = {1{`RANDOM}};
  source_1 = _RAND_10[1:0];
  _RAND_11 = {1{`RANDOM}};
  sink = _RAND_11[1:0];
  _RAND_12 = {1{`RANDOM}};
  b_first_counter = _RAND_12[3:0];
  _RAND_13 = {1{`RANDOM}};
  param_2 = _RAND_13[1:0];
  _RAND_14 = {1{`RANDOM}};
  address_1 = _RAND_14[30:0];
  _RAND_15 = {1{`RANDOM}};
  c_first_counter = _RAND_15[3:0];
  _RAND_16 = {1{`RANDOM}};
  opcode_3 = _RAND_16[2:0];
  _RAND_17 = {1{`RANDOM}};
  param_3 = _RAND_17[2:0];
  _RAND_18 = {1{`RANDOM}};
  size_3 = _RAND_18[2:0];
  _RAND_19 = {1{`RANDOM}};
  source_3 = _RAND_19[1:0];
  _RAND_20 = {1{`RANDOM}};
  address_2 = _RAND_20[30:0];
  _RAND_21 = {1{`RANDOM}};
  inflight = _RAND_21[2:0];
  _RAND_22 = {1{`RANDOM}};
  inflight_opcodes = _RAND_22[11:0];
  _RAND_23 = {1{`RANDOM}};
  inflight_sizes = _RAND_23[11:0];
  _RAND_24 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_24[3:0];
  _RAND_25 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_25[3:0];
  _RAND_26 = {1{`RANDOM}};
  watchdog = _RAND_26[31:0];
  _RAND_27 = {1{`RANDOM}};
  inflight_1 = _RAND_27[2:0];
  _RAND_28 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_28[11:0];
  _RAND_29 = {1{`RANDOM}};
  c_first_counter_1 = _RAND_29[3:0];
  _RAND_30 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_30[3:0];
  _RAND_31 = {1{`RANDOM}};
  watchdog_1 = _RAND_31[31:0];
  _RAND_32 = {1{`RANDOM}};
  inflight_2 = _RAND_32[3:0];
  _RAND_33 = {1{`RANDOM}};
  d_first_counter_3 = _RAND_33[3:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module BroadcastFilter(
  output        io_request_ready,
  input         io_request_valid,
  input  [1:0]  io_request_bits_mshr,
  input  [30:0] io_request_bits_address,
  input         io_request_bits_allocOH,
  input         io_request_bits_needT,
  input         io_response_ready,
  output        io_response_valid,
  output [1:0]  io_response_bits_mshr,
  output [30:0] io_response_bits_address,
  output        io_response_bits_allocOH,
  output        io_response_bits_needT
);
  assign io_request_ready = io_response_ready; // @[Broadcast.scala 362:20]
  assign io_response_valid = io_request_valid; // @[Broadcast.scala 363:21]
  assign io_response_bits_mshr = io_request_bits_mshr; // @[Broadcast.scala 365:28]
  assign io_response_bits_address = io_request_bits_address; // @[Broadcast.scala 366:28]
  assign io_response_bits_allocOH = io_request_bits_allocOH; // @[Broadcast.scala 368:28]
  assign io_response_bits_needT = io_request_bits_needT; // @[Broadcast.scala 367:28]
endmodule
module Queue_11(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [3:0]  io_enq_bits_mask,
  input  [31:0] io_enq_bits_data,
  input         io_deq_ready,
  output        io_deq_valid,
  output [3:0]  io_deq_bits_mask,
  output [31:0] io_deq_bits_data
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
  reg [3:0] ram_mask [0:15]; // @[Decoupled.scala 259:95]
  wire  ram_mask_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire [3:0] ram_mask_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [3:0] ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [3:0] ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
  wire [3:0] ram_mask_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_mask_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_mask_MPORT_en; // @[Decoupled.scala 259:95]
  reg [31:0] ram_data [0:15]; // @[Decoupled.scala 259:95]
  wire  ram_data_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire [3:0] ram_data_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [31:0] ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [31:0] ram_data_MPORT_data; // @[Decoupled.scala 259:95]
  wire [3:0] ram_data_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_data_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_data_MPORT_en; // @[Decoupled.scala 259:95]
  reg [3:0] value; // @[Counter.scala 62:40]
  reg [3:0] value_1; // @[Counter.scala 62:40]
  reg  maybe_full; // @[Decoupled.scala 262:27]
  wire  ptr_match = value == value_1; // @[Decoupled.scala 263:33]
  wire  empty = ptr_match & ~maybe_full; // @[Decoupled.scala 264:25]
  wire  full = ptr_match & maybe_full; // @[Decoupled.scala 265:24]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
  wire  do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
  wire [3:0] _value_T_1 = value + 4'h1; // @[Counter.scala 78:24]
  wire [3:0] _value_T_3 = value_1 + 4'h1; // @[Counter.scala 78:24]
  assign ram_mask_io_deq_bits_MPORT_en = 1'h1;
  assign ram_mask_io_deq_bits_MPORT_addr = value_1;
  assign ram_mask_io_deq_bits_MPORT_data = ram_mask[ram_mask_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_mask_MPORT_data = io_enq_bits_mask;
  assign ram_mask_MPORT_addr = value;
  assign ram_mask_MPORT_mask = 1'h1;
  assign ram_mask_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_data_io_deq_bits_MPORT_en = 1'h1;
  assign ram_data_io_deq_bits_MPORT_addr = value_1;
  assign ram_data_io_deq_bits_MPORT_data = ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_data_MPORT_data = io_enq_bits_data;
  assign ram_data_MPORT_addr = value;
  assign ram_data_MPORT_mask = 1'h1;
  assign ram_data_MPORT_en = io_enq_ready & io_enq_valid;
  assign io_enq_ready = ~full; // @[Decoupled.scala 289:19]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 288:19]
  assign io_deq_bits_mask = ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_data = ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  always @(posedge clock) begin
    if (ram_mask_MPORT_en & ram_mask_MPORT_mask) begin
      ram_mask[ram_mask_MPORT_addr] <= ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_data_MPORT_en & ram_data_MPORT_mask) begin
      ram_data[ram_data_MPORT_addr] <= ram_data_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (reset) begin // @[Counter.scala 62:40]
      value <= 4'h0; // @[Counter.scala 62:40]
    end else if (do_enq) begin // @[Decoupled.scala 272:16]
      value <= _value_T_1; // @[Counter.scala 78:15]
    end
    if (reset) begin // @[Counter.scala 62:40]
      value_1 <= 4'h0; // @[Counter.scala 62:40]
    end else if (do_deq) begin // @[Decoupled.scala 276:16]
      value_1 <= _value_T_3; // @[Counter.scala 78:15]
    end
    if (reset) begin // @[Decoupled.scala 262:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 262:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 279:27]
      maybe_full <= do_enq; // @[Decoupled.scala 280:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 16; initvar = initvar+1)
    ram_mask[initvar] = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 16; initvar = initvar+1)
    ram_data[initvar] = _RAND_1[31:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_2 = {1{`RANDOM}};
  value = _RAND_2[3:0];
  _RAND_3 = {1{`RANDOM}};
  value_1 = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  maybe_full = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLBroadcastTracker(
  input         clock,
  input         reset,
  input         io_in_a_first,
  output        io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [30:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input  [31:0] io_in_a_bits_data,
  input         io_out_a_ready,
  output        io_out_a_valid,
  output [2:0]  io_out_a_bits_opcode,
  output [2:0]  io_out_a_bits_param,
  output [2:0]  io_out_a_bits_size,
  output [3:0]  io_out_a_bits_source,
  output [30:0] io_out_a_bits_address,
  output [3:0]  io_out_a_bits_mask,
  output [31:0] io_out_a_bits_data,
  input         io_probe_valid,
  input         io_probe_bits_count,
  input         io_probenack,
  input         io_probedack,
  input         io_probesack,
  input         io_d_last,
  input         io_e_last,
  output [1:0]  io_source,
  output [24:0] io_line,
  output        io_idle,
  output        io_need_d
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
`endif // RANDOMIZE_REG_INIT
  wire  o_data_clock; // @[Decoupled.scala 361:21]
  wire  o_data_reset; // @[Decoupled.scala 361:21]
  wire  o_data_io_enq_ready; // @[Decoupled.scala 361:21]
  wire  o_data_io_enq_valid; // @[Decoupled.scala 361:21]
  wire [3:0] o_data_io_enq_bits_mask; // @[Decoupled.scala 361:21]
  wire [31:0] o_data_io_enq_bits_data; // @[Decoupled.scala 361:21]
  wire  o_data_io_deq_ready; // @[Decoupled.scala 361:21]
  wire  o_data_io_deq_valid; // @[Decoupled.scala 361:21]
  wire [3:0] o_data_io_deq_bits_mask; // @[Decoupled.scala 361:21]
  wire [31:0] o_data_io_deq_bits_data; // @[Decoupled.scala 361:21]
  reg  got_e; // @[Broadcast.scala 423:24]
  reg  sent_d; // @[Broadcast.scala 424:24]
  reg  shared; // @[Broadcast.scala 425:20]
  reg [2:0] opcode; // @[Broadcast.scala 426:20]
  reg [2:0] param; // @[Broadcast.scala 427:20]
  reg [2:0] size; // @[Broadcast.scala 428:20]
  reg [1:0] source; // @[Broadcast.scala 429:20]
  reg [30:0] address; // @[Broadcast.scala 432:24]
  reg  count; // @[Broadcast.scala 433:20]
  wire  idle = got_e & sent_d; // @[Broadcast.scala 435:23]
  wire  _T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire  _T_1 = _T & io_in_a_first; // @[Broadcast.scala 437:24]
  wire  _T_3 = ~reset; // @[Broadcast.scala 438:12]
  wire  _GEN_0 = _T & io_in_a_first ? 1'h0 : sent_d; // @[Broadcast.scala 437:42 439:13 424:24]
  wire  _GEN_1 = _T & io_in_a_first ? 1'h0 : shared; // @[Broadcast.scala 437:42 440:13 425:20]
  wire  _GEN_2 = _T & io_in_a_first ? io_in_a_bits_opcode != 3'h6 & io_in_a_bits_opcode != 3'h7 : got_e; // @[Broadcast.scala 437:42 441:13 423:24]
  wire  _GEN_8 = _T & io_in_a_first | count; // @[Broadcast.scala 437:42 449:13 433:20]
  wire  _GEN_9 = io_probe_valid ? io_probe_bits_count : _GEN_8; // @[Broadcast.scala 453:25 454:13]
  wire  _GEN_11 = io_d_last | _GEN_0; // @[Broadcast.scala 458:20 460:12]
  wire  _GEN_12 = io_e_last | _GEN_2; // @[Broadcast.scala 462:20 464:11]
  wire  _T_13 = io_probenack | io_probedack; // @[Broadcast.scala 467:22]
  wire [1:0] _count_T_1 = io_probenack & io_probedack ? 2'h2 : 2'h1; // @[Broadcast.scala 469:25]
  wire [1:0] _GEN_15 = {{1'd0}, count}; // @[Broadcast.scala 469:20]
  wire [1:0] _count_T_3 = _GEN_15 - _count_T_1; // @[Broadcast.scala 469:20]
  wire [1:0] _GEN_13 = io_probenack | io_probedack ? _count_T_3 : {{1'd0}, _GEN_9}; // @[Broadcast.scala 467:39 469:11]
  wire  _io_in_a_ready_T_1 = idle | ~io_in_a_first; // @[Broadcast.scala 485:26]
  wire  i_data_ready = o_data_io_enq_ready; // @[Broadcast.scala 482:20 Decoupled.scala 365:17]
  wire  probe_done = ~count; // @[Broadcast.scala 490:26]
  wire  acquire = opcode == 3'h6 | opcode == 3'h7; // @[Broadcast.scala 491:52]
  wire [1:0] transform = shared ? 2'h2 : 2'h3; // @[Broadcast.scala 493:22]
  wire [1:0] _io_out_a_bits_source_T = acquire ? transform : 2'h0; // @[Broadcast.scala 500:35]
  Queue_11 o_data ( // @[Decoupled.scala 361:21]
    .clock(o_data_clock),
    .reset(o_data_reset),
    .io_enq_ready(o_data_io_enq_ready),
    .io_enq_valid(o_data_io_enq_valid),
    .io_enq_bits_mask(o_data_io_enq_bits_mask),
    .io_enq_bits_data(o_data_io_enq_bits_data),
    .io_deq_ready(o_data_io_deq_ready),
    .io_deq_valid(o_data_io_deq_valid),
    .io_deq_bits_mask(o_data_io_deq_bits_mask),
    .io_deq_bits_data(o_data_io_deq_bits_data)
  );
  assign io_in_a_ready = (idle | ~io_in_a_first) & i_data_ready; // @[Broadcast.scala 485:45]
  assign io_out_a_valid = o_data_io_deq_valid & probe_done; // @[Broadcast.scala 496:34]
  assign io_out_a_bits_opcode = acquire ? 3'h4 : opcode; // @[Broadcast.scala 497:31]
  assign io_out_a_bits_param = acquire ? 3'h0 : param; // @[Broadcast.scala 498:31]
  assign io_out_a_bits_size = size; // @[Broadcast.scala 499:25]
  assign io_out_a_bits_source = {_io_out_a_bits_source_T,source}; // @[Cat.scala 31:58]
  assign io_out_a_bits_address = address; // @[Broadcast.scala 501:25]
  assign io_out_a_bits_mask = o_data_io_deq_bits_mask; // @[Broadcast.scala 502:25]
  assign io_out_a_bits_data = o_data_io_deq_bits_data; // @[Broadcast.scala 503:25]
  assign io_source = source; // @[Broadcast.scala 478:13]
  assign io_line = address[30:6]; // @[Broadcast.scala 479:22]
  assign io_idle = got_e & sent_d; // @[Broadcast.scala 435:23]
  assign io_need_d = ~sent_d; // @[Broadcast.scala 477:16]
  assign o_data_clock = clock;
  assign o_data_reset = reset;
  assign o_data_io_enq_valid = _io_in_a_ready_T_1 & io_in_a_valid; // @[Broadcast.scala 486:44]
  assign o_data_io_enq_bits_mask = io_in_a_bits_mask; // @[Broadcast.scala 482:20 487:20]
  assign o_data_io_enq_bits_data = io_in_a_bits_data; // @[Broadcast.scala 482:20 488:20]
  assign o_data_io_deq_ready = io_out_a_ready & probe_done; // @[Broadcast.scala 495:34]
  always @(posedge clock) begin
    got_e <= reset | _GEN_12; // @[Broadcast.scala 423:{24,24}]
    sent_d <= reset | _GEN_11; // @[Broadcast.scala 424:{24,24}]
    shared <= io_probesack | _GEN_1; // @[Broadcast.scala 472:23 473:12]
    if (_T & io_in_a_first) begin // @[Broadcast.scala 437:42]
      opcode <= io_in_a_bits_opcode; // @[Broadcast.scala 442:13]
    end
    if (_T & io_in_a_first) begin // @[Broadcast.scala 437:42]
      param <= io_in_a_bits_param; // @[Broadcast.scala 443:13]
    end
    if (_T & io_in_a_first) begin // @[Broadcast.scala 437:42]
      size <= io_in_a_bits_size; // @[Broadcast.scala 444:13]
    end
    if (_T & io_in_a_first) begin // @[Broadcast.scala 437:42]
      source <= io_in_a_bits_source; // @[Broadcast.scala 445:13]
    end
    if (reset) begin // @[Broadcast.scala 432:24]
      address <= 31'h0; // @[Broadcast.scala 432:24]
    end else if (_T & io_in_a_first) begin // @[Broadcast.scala 437:42]
      address <= io_in_a_bits_address; // @[Broadcast.scala 448:13]
    end
    count <= _GEN_13[0];
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~idle & (_T_1 & ~reset)) begin
          $fatal; // @[Broadcast.scala 438:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1 & ~reset & ~idle) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Broadcast.scala:438 assert (idle)\n"); // @[Broadcast.scala 438:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~sent_d) & (io_d_last & _T_3)) begin
          $fatal; // @[Broadcast.scala 459:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_d_last & _T_3 & ~(~sent_d)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Broadcast.scala:459 assert (!sent_d)\n"); // @[Broadcast.scala 459:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~got_e) & (io_e_last & _T_3)) begin
          $fatal; // @[Broadcast.scala 463:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_e_last & _T_3 & ~(~got_e)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Broadcast.scala:463 assert (!got_e)\n"); // @[Broadcast.scala 463:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(count > 1'h0) & (_T_13 & _T_3)) begin
          $fatal; // @[Broadcast.scala 468:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_13 & _T_3 & ~(count > 1'h0)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Broadcast.scala:468 assert (count > 0.U)\n"); // @[Broadcast.scala 468:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  got_e = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  sent_d = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  shared = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  opcode = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  param = _RAND_4[2:0];
  _RAND_5 = {1{`RANDOM}};
  size = _RAND_5[2:0];
  _RAND_6 = {1{`RANDOM}};
  source = _RAND_6[1:0];
  _RAND_7 = {1{`RANDOM}};
  address = _RAND_7[30:0];
  _RAND_8 = {1{`RANDOM}};
  count = _RAND_8[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLBroadcastTracker_1(
  input         clock,
  input         reset,
  input         io_in_a_first,
  output        io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [30:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input  [31:0] io_in_a_bits_data,
  input         io_out_a_ready,
  output        io_out_a_valid,
  output [2:0]  io_out_a_bits_opcode,
  output [2:0]  io_out_a_bits_param,
  output [2:0]  io_out_a_bits_size,
  output [3:0]  io_out_a_bits_source,
  output [30:0] io_out_a_bits_address,
  output [3:0]  io_out_a_bits_mask,
  output [31:0] io_out_a_bits_data,
  input         io_probe_valid,
  input         io_probe_bits_count,
  input         io_probenack,
  input         io_probedack,
  input         io_probesack,
  input         io_d_last,
  input         io_e_last,
  output [1:0]  io_source,
  output [24:0] io_line,
  output        io_idle,
  output        io_need_d
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
`endif // RANDOMIZE_REG_INIT
  wire  o_data_clock; // @[Decoupled.scala 361:21]
  wire  o_data_reset; // @[Decoupled.scala 361:21]
  wire  o_data_io_enq_ready; // @[Decoupled.scala 361:21]
  wire  o_data_io_enq_valid; // @[Decoupled.scala 361:21]
  wire [3:0] o_data_io_enq_bits_mask; // @[Decoupled.scala 361:21]
  wire [31:0] o_data_io_enq_bits_data; // @[Decoupled.scala 361:21]
  wire  o_data_io_deq_ready; // @[Decoupled.scala 361:21]
  wire  o_data_io_deq_valid; // @[Decoupled.scala 361:21]
  wire [3:0] o_data_io_deq_bits_mask; // @[Decoupled.scala 361:21]
  wire [31:0] o_data_io_deq_bits_data; // @[Decoupled.scala 361:21]
  reg  got_e; // @[Broadcast.scala 423:24]
  reg  sent_d; // @[Broadcast.scala 424:24]
  reg  shared; // @[Broadcast.scala 425:20]
  reg [2:0] opcode; // @[Broadcast.scala 426:20]
  reg [2:0] param; // @[Broadcast.scala 427:20]
  reg [2:0] size; // @[Broadcast.scala 428:20]
  reg [1:0] source; // @[Broadcast.scala 429:20]
  reg [30:0] address; // @[Broadcast.scala 432:24]
  reg  count; // @[Broadcast.scala 433:20]
  wire  idle = got_e & sent_d; // @[Broadcast.scala 435:23]
  wire  _T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire  _T_1 = _T & io_in_a_first; // @[Broadcast.scala 437:24]
  wire  _T_3 = ~reset; // @[Broadcast.scala 438:12]
  wire  _GEN_0 = _T & io_in_a_first ? 1'h0 : sent_d; // @[Broadcast.scala 437:42 439:13 424:24]
  wire  _GEN_1 = _T & io_in_a_first ? 1'h0 : shared; // @[Broadcast.scala 437:42 440:13 425:20]
  wire  _GEN_2 = _T & io_in_a_first ? io_in_a_bits_opcode != 3'h6 & io_in_a_bits_opcode != 3'h7 : got_e; // @[Broadcast.scala 437:42 441:13 423:24]
  wire  _GEN_8 = _T & io_in_a_first | count; // @[Broadcast.scala 437:42 449:13 433:20]
  wire  _GEN_9 = io_probe_valid ? io_probe_bits_count : _GEN_8; // @[Broadcast.scala 453:25 454:13]
  wire  _GEN_11 = io_d_last | _GEN_0; // @[Broadcast.scala 458:20 460:12]
  wire  _GEN_12 = io_e_last | _GEN_2; // @[Broadcast.scala 462:20 464:11]
  wire  _T_13 = io_probenack | io_probedack; // @[Broadcast.scala 467:22]
  wire [1:0] _count_T_1 = io_probenack & io_probedack ? 2'h2 : 2'h1; // @[Broadcast.scala 469:25]
  wire [1:0] _GEN_15 = {{1'd0}, count}; // @[Broadcast.scala 469:20]
  wire [1:0] _count_T_3 = _GEN_15 - _count_T_1; // @[Broadcast.scala 469:20]
  wire [1:0] _GEN_13 = io_probenack | io_probedack ? _count_T_3 : {{1'd0}, _GEN_9}; // @[Broadcast.scala 467:39 469:11]
  wire  _io_in_a_ready_T_1 = idle | ~io_in_a_first; // @[Broadcast.scala 485:26]
  wire  i_data_ready = o_data_io_enq_ready; // @[Broadcast.scala 482:20 Decoupled.scala 365:17]
  wire  probe_done = ~count; // @[Broadcast.scala 490:26]
  wire  acquire = opcode == 3'h6 | opcode == 3'h7; // @[Broadcast.scala 491:52]
  wire [1:0] transform = shared ? 2'h2 : 2'h3; // @[Broadcast.scala 493:22]
  wire [1:0] _io_out_a_bits_source_T = acquire ? transform : 2'h0; // @[Broadcast.scala 500:35]
  Queue_11 o_data ( // @[Decoupled.scala 361:21]
    .clock(o_data_clock),
    .reset(o_data_reset),
    .io_enq_ready(o_data_io_enq_ready),
    .io_enq_valid(o_data_io_enq_valid),
    .io_enq_bits_mask(o_data_io_enq_bits_mask),
    .io_enq_bits_data(o_data_io_enq_bits_data),
    .io_deq_ready(o_data_io_deq_ready),
    .io_deq_valid(o_data_io_deq_valid),
    .io_deq_bits_mask(o_data_io_deq_bits_mask),
    .io_deq_bits_data(o_data_io_deq_bits_data)
  );
  assign io_in_a_ready = (idle | ~io_in_a_first) & i_data_ready; // @[Broadcast.scala 485:45]
  assign io_out_a_valid = o_data_io_deq_valid & probe_done; // @[Broadcast.scala 496:34]
  assign io_out_a_bits_opcode = acquire ? 3'h4 : opcode; // @[Broadcast.scala 497:31]
  assign io_out_a_bits_param = acquire ? 3'h0 : param; // @[Broadcast.scala 498:31]
  assign io_out_a_bits_size = size; // @[Broadcast.scala 499:25]
  assign io_out_a_bits_source = {_io_out_a_bits_source_T,source}; // @[Cat.scala 31:58]
  assign io_out_a_bits_address = address; // @[Broadcast.scala 501:25]
  assign io_out_a_bits_mask = o_data_io_deq_bits_mask; // @[Broadcast.scala 502:25]
  assign io_out_a_bits_data = o_data_io_deq_bits_data; // @[Broadcast.scala 503:25]
  assign io_source = source; // @[Broadcast.scala 478:13]
  assign io_line = address[30:6]; // @[Broadcast.scala 479:22]
  assign io_idle = got_e & sent_d; // @[Broadcast.scala 435:23]
  assign io_need_d = ~sent_d; // @[Broadcast.scala 477:16]
  assign o_data_clock = clock;
  assign o_data_reset = reset;
  assign o_data_io_enq_valid = _io_in_a_ready_T_1 & io_in_a_valid; // @[Broadcast.scala 486:44]
  assign o_data_io_enq_bits_mask = io_in_a_bits_mask; // @[Broadcast.scala 482:20 487:20]
  assign o_data_io_enq_bits_data = io_in_a_bits_data; // @[Broadcast.scala 482:20 488:20]
  assign o_data_io_deq_ready = io_out_a_ready & probe_done; // @[Broadcast.scala 495:34]
  always @(posedge clock) begin
    got_e <= reset | _GEN_12; // @[Broadcast.scala 423:{24,24}]
    sent_d <= reset | _GEN_11; // @[Broadcast.scala 424:{24,24}]
    shared <= io_probesack | _GEN_1; // @[Broadcast.scala 472:23 473:12]
    if (_T & io_in_a_first) begin // @[Broadcast.scala 437:42]
      opcode <= io_in_a_bits_opcode; // @[Broadcast.scala 442:13]
    end
    if (_T & io_in_a_first) begin // @[Broadcast.scala 437:42]
      param <= io_in_a_bits_param; // @[Broadcast.scala 443:13]
    end
    if (_T & io_in_a_first) begin // @[Broadcast.scala 437:42]
      size <= io_in_a_bits_size; // @[Broadcast.scala 444:13]
    end
    if (_T & io_in_a_first) begin // @[Broadcast.scala 437:42]
      source <= io_in_a_bits_source; // @[Broadcast.scala 445:13]
    end
    if (reset) begin // @[Broadcast.scala 432:24]
      address <= 31'h40; // @[Broadcast.scala 432:24]
    end else if (_T & io_in_a_first) begin // @[Broadcast.scala 437:42]
      address <= io_in_a_bits_address; // @[Broadcast.scala 448:13]
    end
    count <= _GEN_13[0];
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~idle & (_T_1 & ~reset)) begin
          $fatal; // @[Broadcast.scala 438:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1 & ~reset & ~idle) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Broadcast.scala:438 assert (idle)\n"); // @[Broadcast.scala 438:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~sent_d) & (io_d_last & _T_3)) begin
          $fatal; // @[Broadcast.scala 459:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_d_last & _T_3 & ~(~sent_d)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Broadcast.scala:459 assert (!sent_d)\n"); // @[Broadcast.scala 459:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~got_e) & (io_e_last & _T_3)) begin
          $fatal; // @[Broadcast.scala 463:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_e_last & _T_3 & ~(~got_e)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Broadcast.scala:463 assert (!got_e)\n"); // @[Broadcast.scala 463:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(count > 1'h0) & (_T_13 & _T_3)) begin
          $fatal; // @[Broadcast.scala 468:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_13 & _T_3 & ~(count > 1'h0)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Broadcast.scala:468 assert (count > 0.U)\n"); // @[Broadcast.scala 468:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  got_e = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  sent_d = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  shared = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  opcode = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  param = _RAND_4[2:0];
  _RAND_5 = {1{`RANDOM}};
  size = _RAND_5[2:0];
  _RAND_6 = {1{`RANDOM}};
  source = _RAND_6[1:0];
  _RAND_7 = {1{`RANDOM}};
  address = _RAND_7[30:0];
  _RAND_8 = {1{`RANDOM}};
  count = _RAND_8[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLBroadcastTracker_2(
  input         clock,
  input         reset,
  input         io_in_a_first,
  output        io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [30:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input  [31:0] io_in_a_bits_data,
  input         io_out_a_ready,
  output        io_out_a_valid,
  output [2:0]  io_out_a_bits_opcode,
  output [2:0]  io_out_a_bits_param,
  output [2:0]  io_out_a_bits_size,
  output [3:0]  io_out_a_bits_source,
  output [30:0] io_out_a_bits_address,
  output [3:0]  io_out_a_bits_mask,
  output [31:0] io_out_a_bits_data,
  input         io_probe_valid,
  input         io_probe_bits_count,
  input         io_probenack,
  input         io_probedack,
  input         io_probesack,
  input         io_d_last,
  input         io_e_last,
  output [1:0]  io_source,
  output [24:0] io_line,
  output        io_idle,
  output        io_need_d
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
`endif // RANDOMIZE_REG_INIT
  wire  o_data_clock; // @[Decoupled.scala 361:21]
  wire  o_data_reset; // @[Decoupled.scala 361:21]
  wire  o_data_io_enq_ready; // @[Decoupled.scala 361:21]
  wire  o_data_io_enq_valid; // @[Decoupled.scala 361:21]
  wire [3:0] o_data_io_enq_bits_mask; // @[Decoupled.scala 361:21]
  wire [31:0] o_data_io_enq_bits_data; // @[Decoupled.scala 361:21]
  wire  o_data_io_deq_ready; // @[Decoupled.scala 361:21]
  wire  o_data_io_deq_valid; // @[Decoupled.scala 361:21]
  wire [3:0] o_data_io_deq_bits_mask; // @[Decoupled.scala 361:21]
  wire [31:0] o_data_io_deq_bits_data; // @[Decoupled.scala 361:21]
  reg  got_e; // @[Broadcast.scala 423:24]
  reg  sent_d; // @[Broadcast.scala 424:24]
  reg  shared; // @[Broadcast.scala 425:20]
  reg [2:0] opcode; // @[Broadcast.scala 426:20]
  reg [2:0] param; // @[Broadcast.scala 427:20]
  reg [2:0] size; // @[Broadcast.scala 428:20]
  reg [1:0] source; // @[Broadcast.scala 429:20]
  reg [30:0] address; // @[Broadcast.scala 432:24]
  reg  count; // @[Broadcast.scala 433:20]
  wire  idle = got_e & sent_d; // @[Broadcast.scala 435:23]
  wire  _T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire  _T_1 = _T & io_in_a_first; // @[Broadcast.scala 437:24]
  wire  _T_3 = ~reset; // @[Broadcast.scala 438:12]
  wire  _GEN_0 = _T & io_in_a_first ? 1'h0 : sent_d; // @[Broadcast.scala 437:42 439:13 424:24]
  wire  _GEN_1 = _T & io_in_a_first ? 1'h0 : shared; // @[Broadcast.scala 437:42 440:13 425:20]
  wire  _GEN_2 = _T & io_in_a_first ? io_in_a_bits_opcode != 3'h6 & io_in_a_bits_opcode != 3'h7 : got_e; // @[Broadcast.scala 437:42 441:13 423:24]
  wire  _GEN_8 = _T & io_in_a_first | count; // @[Broadcast.scala 437:42 449:13 433:20]
  wire  _GEN_9 = io_probe_valid ? io_probe_bits_count : _GEN_8; // @[Broadcast.scala 453:25 454:13]
  wire  _GEN_11 = io_d_last | _GEN_0; // @[Broadcast.scala 458:20 460:12]
  wire  _GEN_12 = io_e_last | _GEN_2; // @[Broadcast.scala 462:20 464:11]
  wire  _T_13 = io_probenack | io_probedack; // @[Broadcast.scala 467:22]
  wire [1:0] _count_T_1 = io_probenack & io_probedack ? 2'h2 : 2'h1; // @[Broadcast.scala 469:25]
  wire [1:0] _GEN_15 = {{1'd0}, count}; // @[Broadcast.scala 469:20]
  wire [1:0] _count_T_3 = _GEN_15 - _count_T_1; // @[Broadcast.scala 469:20]
  wire [1:0] _GEN_13 = io_probenack | io_probedack ? _count_T_3 : {{1'd0}, _GEN_9}; // @[Broadcast.scala 467:39 469:11]
  wire  _io_in_a_ready_T_1 = idle | ~io_in_a_first; // @[Broadcast.scala 485:26]
  wire  i_data_ready = o_data_io_enq_ready; // @[Broadcast.scala 482:20 Decoupled.scala 365:17]
  wire  probe_done = ~count; // @[Broadcast.scala 490:26]
  wire  acquire = opcode == 3'h6 | opcode == 3'h7; // @[Broadcast.scala 491:52]
  wire [1:0] transform = shared ? 2'h2 : 2'h3; // @[Broadcast.scala 493:22]
  wire [1:0] _io_out_a_bits_source_T = acquire ? transform : 2'h0; // @[Broadcast.scala 500:35]
  Queue_11 o_data ( // @[Decoupled.scala 361:21]
    .clock(o_data_clock),
    .reset(o_data_reset),
    .io_enq_ready(o_data_io_enq_ready),
    .io_enq_valid(o_data_io_enq_valid),
    .io_enq_bits_mask(o_data_io_enq_bits_mask),
    .io_enq_bits_data(o_data_io_enq_bits_data),
    .io_deq_ready(o_data_io_deq_ready),
    .io_deq_valid(o_data_io_deq_valid),
    .io_deq_bits_mask(o_data_io_deq_bits_mask),
    .io_deq_bits_data(o_data_io_deq_bits_data)
  );
  assign io_in_a_ready = (idle | ~io_in_a_first) & i_data_ready; // @[Broadcast.scala 485:45]
  assign io_out_a_valid = o_data_io_deq_valid & probe_done; // @[Broadcast.scala 496:34]
  assign io_out_a_bits_opcode = acquire ? 3'h4 : opcode; // @[Broadcast.scala 497:31]
  assign io_out_a_bits_param = acquire ? 3'h0 : param; // @[Broadcast.scala 498:31]
  assign io_out_a_bits_size = size; // @[Broadcast.scala 499:25]
  assign io_out_a_bits_source = {_io_out_a_bits_source_T,source}; // @[Cat.scala 31:58]
  assign io_out_a_bits_address = address; // @[Broadcast.scala 501:25]
  assign io_out_a_bits_mask = o_data_io_deq_bits_mask; // @[Broadcast.scala 502:25]
  assign io_out_a_bits_data = o_data_io_deq_bits_data; // @[Broadcast.scala 503:25]
  assign io_source = source; // @[Broadcast.scala 478:13]
  assign io_line = address[30:6]; // @[Broadcast.scala 479:22]
  assign io_idle = got_e & sent_d; // @[Broadcast.scala 435:23]
  assign io_need_d = ~sent_d; // @[Broadcast.scala 477:16]
  assign o_data_clock = clock;
  assign o_data_reset = reset;
  assign o_data_io_enq_valid = _io_in_a_ready_T_1 & io_in_a_valid; // @[Broadcast.scala 486:44]
  assign o_data_io_enq_bits_mask = io_in_a_bits_mask; // @[Broadcast.scala 482:20 487:20]
  assign o_data_io_enq_bits_data = io_in_a_bits_data; // @[Broadcast.scala 482:20 488:20]
  assign o_data_io_deq_ready = io_out_a_ready & probe_done; // @[Broadcast.scala 495:34]
  always @(posedge clock) begin
    got_e <= reset | _GEN_12; // @[Broadcast.scala 423:{24,24}]
    sent_d <= reset | _GEN_11; // @[Broadcast.scala 424:{24,24}]
    shared <= io_probesack | _GEN_1; // @[Broadcast.scala 472:23 473:12]
    if (_T & io_in_a_first) begin // @[Broadcast.scala 437:42]
      opcode <= io_in_a_bits_opcode; // @[Broadcast.scala 442:13]
    end
    if (_T & io_in_a_first) begin // @[Broadcast.scala 437:42]
      param <= io_in_a_bits_param; // @[Broadcast.scala 443:13]
    end
    if (_T & io_in_a_first) begin // @[Broadcast.scala 437:42]
      size <= io_in_a_bits_size; // @[Broadcast.scala 444:13]
    end
    if (_T & io_in_a_first) begin // @[Broadcast.scala 437:42]
      source <= io_in_a_bits_source; // @[Broadcast.scala 445:13]
    end
    if (reset) begin // @[Broadcast.scala 432:24]
      address <= 31'h80; // @[Broadcast.scala 432:24]
    end else if (_T & io_in_a_first) begin // @[Broadcast.scala 437:42]
      address <= io_in_a_bits_address; // @[Broadcast.scala 448:13]
    end
    count <= _GEN_13[0];
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~idle & (_T_1 & ~reset)) begin
          $fatal; // @[Broadcast.scala 438:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1 & ~reset & ~idle) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Broadcast.scala:438 assert (idle)\n"); // @[Broadcast.scala 438:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~sent_d) & (io_d_last & _T_3)) begin
          $fatal; // @[Broadcast.scala 459:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_d_last & _T_3 & ~(~sent_d)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Broadcast.scala:459 assert (!sent_d)\n"); // @[Broadcast.scala 459:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~got_e) & (io_e_last & _T_3)) begin
          $fatal; // @[Broadcast.scala 463:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_e_last & _T_3 & ~(~got_e)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Broadcast.scala:463 assert (!got_e)\n"); // @[Broadcast.scala 463:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(count > 1'h0) & (_T_13 & _T_3)) begin
          $fatal; // @[Broadcast.scala 468:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_13 & _T_3 & ~(count > 1'h0)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Broadcast.scala:468 assert (count > 0.U)\n"); // @[Broadcast.scala 468:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  got_e = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  sent_d = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  shared = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  opcode = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  param = _RAND_4[2:0];
  _RAND_5 = {1{`RANDOM}};
  size = _RAND_5[2:0];
  _RAND_6 = {1{`RANDOM}};
  source = _RAND_6[1:0];
  _RAND_7 = {1{`RANDOM}};
  address = _RAND_7[30:0];
  _RAND_8 = {1{`RANDOM}};
  count = _RAND_8[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLBroadcastTracker_3(
  input         clock,
  input         reset,
  input         io_in_a_first,
  output        io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [30:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input  [31:0] io_in_a_bits_data,
  input         io_out_a_ready,
  output        io_out_a_valid,
  output [2:0]  io_out_a_bits_opcode,
  output [2:0]  io_out_a_bits_param,
  output [2:0]  io_out_a_bits_size,
  output [3:0]  io_out_a_bits_source,
  output [30:0] io_out_a_bits_address,
  output [3:0]  io_out_a_bits_mask,
  output [31:0] io_out_a_bits_data,
  input         io_probe_valid,
  input         io_probe_bits_count,
  input         io_probenack,
  input         io_probedack,
  input         io_probesack,
  input         io_d_last,
  input         io_e_last,
  output [1:0]  io_source,
  output [24:0] io_line,
  output        io_idle,
  output        io_need_d
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
`endif // RANDOMIZE_REG_INIT
  wire  o_data_clock; // @[Decoupled.scala 361:21]
  wire  o_data_reset; // @[Decoupled.scala 361:21]
  wire  o_data_io_enq_ready; // @[Decoupled.scala 361:21]
  wire  o_data_io_enq_valid; // @[Decoupled.scala 361:21]
  wire [3:0] o_data_io_enq_bits_mask; // @[Decoupled.scala 361:21]
  wire [31:0] o_data_io_enq_bits_data; // @[Decoupled.scala 361:21]
  wire  o_data_io_deq_ready; // @[Decoupled.scala 361:21]
  wire  o_data_io_deq_valid; // @[Decoupled.scala 361:21]
  wire [3:0] o_data_io_deq_bits_mask; // @[Decoupled.scala 361:21]
  wire [31:0] o_data_io_deq_bits_data; // @[Decoupled.scala 361:21]
  reg  got_e; // @[Broadcast.scala 423:24]
  reg  sent_d; // @[Broadcast.scala 424:24]
  reg  shared; // @[Broadcast.scala 425:20]
  reg [2:0] opcode; // @[Broadcast.scala 426:20]
  reg [2:0] param; // @[Broadcast.scala 427:20]
  reg [2:0] size; // @[Broadcast.scala 428:20]
  reg [1:0] source; // @[Broadcast.scala 429:20]
  reg [30:0] address; // @[Broadcast.scala 432:24]
  reg  count; // @[Broadcast.scala 433:20]
  wire  idle = got_e & sent_d; // @[Broadcast.scala 435:23]
  wire  _T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire  _T_1 = _T & io_in_a_first; // @[Broadcast.scala 437:24]
  wire  _T_3 = ~reset; // @[Broadcast.scala 438:12]
  wire  _GEN_0 = _T & io_in_a_first ? 1'h0 : sent_d; // @[Broadcast.scala 437:42 439:13 424:24]
  wire  _GEN_1 = _T & io_in_a_first ? 1'h0 : shared; // @[Broadcast.scala 437:42 440:13 425:20]
  wire  _GEN_2 = _T & io_in_a_first ? io_in_a_bits_opcode != 3'h6 & io_in_a_bits_opcode != 3'h7 : got_e; // @[Broadcast.scala 437:42 441:13 423:24]
  wire  _GEN_8 = _T & io_in_a_first | count; // @[Broadcast.scala 437:42 449:13 433:20]
  wire  _GEN_9 = io_probe_valid ? io_probe_bits_count : _GEN_8; // @[Broadcast.scala 453:25 454:13]
  wire  _GEN_11 = io_d_last | _GEN_0; // @[Broadcast.scala 458:20 460:12]
  wire  _GEN_12 = io_e_last | _GEN_2; // @[Broadcast.scala 462:20 464:11]
  wire  _T_13 = io_probenack | io_probedack; // @[Broadcast.scala 467:22]
  wire [1:0] _count_T_1 = io_probenack & io_probedack ? 2'h2 : 2'h1; // @[Broadcast.scala 469:25]
  wire [1:0] _GEN_15 = {{1'd0}, count}; // @[Broadcast.scala 469:20]
  wire [1:0] _count_T_3 = _GEN_15 - _count_T_1; // @[Broadcast.scala 469:20]
  wire [1:0] _GEN_13 = io_probenack | io_probedack ? _count_T_3 : {{1'd0}, _GEN_9}; // @[Broadcast.scala 467:39 469:11]
  wire  _io_in_a_ready_T_1 = idle | ~io_in_a_first; // @[Broadcast.scala 485:26]
  wire  i_data_ready = o_data_io_enq_ready; // @[Broadcast.scala 482:20 Decoupled.scala 365:17]
  wire  probe_done = ~count; // @[Broadcast.scala 490:26]
  wire  acquire = opcode == 3'h6 | opcode == 3'h7; // @[Broadcast.scala 491:52]
  wire [1:0] transform = shared ? 2'h2 : 2'h3; // @[Broadcast.scala 493:22]
  wire [1:0] _io_out_a_bits_source_T = acquire ? transform : 2'h0; // @[Broadcast.scala 500:35]
  Queue_11 o_data ( // @[Decoupled.scala 361:21]
    .clock(o_data_clock),
    .reset(o_data_reset),
    .io_enq_ready(o_data_io_enq_ready),
    .io_enq_valid(o_data_io_enq_valid),
    .io_enq_bits_mask(o_data_io_enq_bits_mask),
    .io_enq_bits_data(o_data_io_enq_bits_data),
    .io_deq_ready(o_data_io_deq_ready),
    .io_deq_valid(o_data_io_deq_valid),
    .io_deq_bits_mask(o_data_io_deq_bits_mask),
    .io_deq_bits_data(o_data_io_deq_bits_data)
  );
  assign io_in_a_ready = (idle | ~io_in_a_first) & i_data_ready; // @[Broadcast.scala 485:45]
  assign io_out_a_valid = o_data_io_deq_valid & probe_done; // @[Broadcast.scala 496:34]
  assign io_out_a_bits_opcode = acquire ? 3'h4 : opcode; // @[Broadcast.scala 497:31]
  assign io_out_a_bits_param = acquire ? 3'h0 : param; // @[Broadcast.scala 498:31]
  assign io_out_a_bits_size = size; // @[Broadcast.scala 499:25]
  assign io_out_a_bits_source = {_io_out_a_bits_source_T,source}; // @[Cat.scala 31:58]
  assign io_out_a_bits_address = address; // @[Broadcast.scala 501:25]
  assign io_out_a_bits_mask = o_data_io_deq_bits_mask; // @[Broadcast.scala 502:25]
  assign io_out_a_bits_data = o_data_io_deq_bits_data; // @[Broadcast.scala 503:25]
  assign io_source = source; // @[Broadcast.scala 478:13]
  assign io_line = address[30:6]; // @[Broadcast.scala 479:22]
  assign io_idle = got_e & sent_d; // @[Broadcast.scala 435:23]
  assign io_need_d = ~sent_d; // @[Broadcast.scala 477:16]
  assign o_data_clock = clock;
  assign o_data_reset = reset;
  assign o_data_io_enq_valid = _io_in_a_ready_T_1 & io_in_a_valid; // @[Broadcast.scala 486:44]
  assign o_data_io_enq_bits_mask = io_in_a_bits_mask; // @[Broadcast.scala 482:20 487:20]
  assign o_data_io_enq_bits_data = io_in_a_bits_data; // @[Broadcast.scala 482:20 488:20]
  assign o_data_io_deq_ready = io_out_a_ready & probe_done; // @[Broadcast.scala 495:34]
  always @(posedge clock) begin
    got_e <= reset | _GEN_12; // @[Broadcast.scala 423:{24,24}]
    sent_d <= reset | _GEN_11; // @[Broadcast.scala 424:{24,24}]
    shared <= io_probesack | _GEN_1; // @[Broadcast.scala 472:23 473:12]
    if (_T & io_in_a_first) begin // @[Broadcast.scala 437:42]
      opcode <= io_in_a_bits_opcode; // @[Broadcast.scala 442:13]
    end
    if (_T & io_in_a_first) begin // @[Broadcast.scala 437:42]
      param <= io_in_a_bits_param; // @[Broadcast.scala 443:13]
    end
    if (_T & io_in_a_first) begin // @[Broadcast.scala 437:42]
      size <= io_in_a_bits_size; // @[Broadcast.scala 444:13]
    end
    if (_T & io_in_a_first) begin // @[Broadcast.scala 437:42]
      source <= io_in_a_bits_source; // @[Broadcast.scala 445:13]
    end
    if (reset) begin // @[Broadcast.scala 432:24]
      address <= 31'hc0; // @[Broadcast.scala 432:24]
    end else if (_T & io_in_a_first) begin // @[Broadcast.scala 437:42]
      address <= io_in_a_bits_address; // @[Broadcast.scala 448:13]
    end
    count <= _GEN_13[0];
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~idle & (_T_1 & ~reset)) begin
          $fatal; // @[Broadcast.scala 438:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1 & ~reset & ~idle) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Broadcast.scala:438 assert (idle)\n"); // @[Broadcast.scala 438:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~sent_d) & (io_d_last & _T_3)) begin
          $fatal; // @[Broadcast.scala 459:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_d_last & _T_3 & ~(~sent_d)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Broadcast.scala:459 assert (!sent_d)\n"); // @[Broadcast.scala 459:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~got_e) & (io_e_last & _T_3)) begin
          $fatal; // @[Broadcast.scala 463:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_e_last & _T_3 & ~(~got_e)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Broadcast.scala:463 assert (!got_e)\n"); // @[Broadcast.scala 463:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(count > 1'h0) & (_T_13 & _T_3)) begin
          $fatal; // @[Broadcast.scala 468:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_13 & _T_3 & ~(count > 1'h0)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Broadcast.scala:468 assert (count > 0.U)\n"); // @[Broadcast.scala 468:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  got_e = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  sent_d = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  shared = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  opcode = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  param = _RAND_4[2:0];
  _RAND_5 = {1{`RANDOM}};
  size = _RAND_5[2:0];
  _RAND_6 = {1{`RANDOM}};
  source = _RAND_6[1:0];
  _RAND_7 = {1{`RANDOM}};
  address = _RAND_7[30:0];
  _RAND_8 = {1{`RANDOM}};
  count = _RAND_8[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLBroadcast(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [30:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_b_ready,
  output        auto_in_b_valid,
  output [1:0]  auto_in_b_bits_param,
  output [30:0] auto_in_b_bits_address,
  output        auto_in_c_ready,
  input         auto_in_c_valid,
  input  [2:0]  auto_in_c_bits_opcode,
  input  [2:0]  auto_in_c_bits_param,
  input  [2:0]  auto_in_c_bits_size,
  input  [1:0]  auto_in_c_bits_source,
  input  [30:0] auto_in_c_bits_address,
  input  [31:0] auto_in_c_bits_data,
  input         auto_in_c_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [1:0]  auto_in_d_bits_param,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output [1:0]  auto_in_d_bits_sink,
  output [31:0] auto_in_d_bits_data,
  input         auto_in_e_valid,
  input  [1:0]  auto_in_e_bits_sink,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [2:0]  auto_out_a_bits_size,
  output [3:0]  auto_out_a_bits_source,
  output [30:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [2:0]  auto_out_d_bits_size,
  input  [3:0]  auto_out_d_bits_source,
  input  [31:0] auto_out_d_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [30:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_b_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_b_valid; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_b_bits_param; // @[Nodes.scala 24:25]
  wire [30:0] monitor_io_in_b_bits_address; // @[Nodes.scala 24:25]
  wire  monitor_io_in_c_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_c_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_c_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_c_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_c_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_c_bits_source; // @[Nodes.scala 24:25]
  wire [30:0] monitor_io_in_c_bits_address; // @[Nodes.scala 24:25]
  wire  monitor_io_in_c_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
  wire  monitor_io_in_e_valid; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_e_bits_sink; // @[Nodes.scala 24:25]
  wire  BroadcastFilter_io_request_ready; // @[Broadcast.scala 99:26]
  wire  BroadcastFilter_io_request_valid; // @[Broadcast.scala 99:26]
  wire [1:0] BroadcastFilter_io_request_bits_mshr; // @[Broadcast.scala 99:26]
  wire [30:0] BroadcastFilter_io_request_bits_address; // @[Broadcast.scala 99:26]
  wire  BroadcastFilter_io_request_bits_allocOH; // @[Broadcast.scala 99:26]
  wire  BroadcastFilter_io_request_bits_needT; // @[Broadcast.scala 99:26]
  wire  BroadcastFilter_io_response_ready; // @[Broadcast.scala 99:26]
  wire  BroadcastFilter_io_response_valid; // @[Broadcast.scala 99:26]
  wire [1:0] BroadcastFilter_io_response_bits_mshr; // @[Broadcast.scala 99:26]
  wire [30:0] BroadcastFilter_io_response_bits_address; // @[Broadcast.scala 99:26]
  wire  BroadcastFilter_io_response_bits_allocOH; // @[Broadcast.scala 99:26]
  wire  BroadcastFilter_io_response_bits_needT; // @[Broadcast.scala 99:26]
  wire  TLBroadcastTracker_clock; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_reset; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_io_in_a_first; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_io_in_a_ready; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_io_in_a_valid; // @[Broadcast.scala 107:15]
  wire [2:0] TLBroadcastTracker_io_in_a_bits_opcode; // @[Broadcast.scala 107:15]
  wire [2:0] TLBroadcastTracker_io_in_a_bits_param; // @[Broadcast.scala 107:15]
  wire [2:0] TLBroadcastTracker_io_in_a_bits_size; // @[Broadcast.scala 107:15]
  wire [1:0] TLBroadcastTracker_io_in_a_bits_source; // @[Broadcast.scala 107:15]
  wire [30:0] TLBroadcastTracker_io_in_a_bits_address; // @[Broadcast.scala 107:15]
  wire [3:0] TLBroadcastTracker_io_in_a_bits_mask; // @[Broadcast.scala 107:15]
  wire [31:0] TLBroadcastTracker_io_in_a_bits_data; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_io_out_a_ready; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_io_out_a_valid; // @[Broadcast.scala 107:15]
  wire [2:0] TLBroadcastTracker_io_out_a_bits_opcode; // @[Broadcast.scala 107:15]
  wire [2:0] TLBroadcastTracker_io_out_a_bits_param; // @[Broadcast.scala 107:15]
  wire [2:0] TLBroadcastTracker_io_out_a_bits_size; // @[Broadcast.scala 107:15]
  wire [3:0] TLBroadcastTracker_io_out_a_bits_source; // @[Broadcast.scala 107:15]
  wire [30:0] TLBroadcastTracker_io_out_a_bits_address; // @[Broadcast.scala 107:15]
  wire [3:0] TLBroadcastTracker_io_out_a_bits_mask; // @[Broadcast.scala 107:15]
  wire [31:0] TLBroadcastTracker_io_out_a_bits_data; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_io_probe_valid; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_io_probe_bits_count; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_io_probenack; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_io_probedack; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_io_probesack; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_io_d_last; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_io_e_last; // @[Broadcast.scala 107:15]
  wire [1:0] TLBroadcastTracker_io_source; // @[Broadcast.scala 107:15]
  wire [24:0] TLBroadcastTracker_io_line; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_io_idle; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_io_need_d; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_1_clock; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_1_reset; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_1_io_in_a_first; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_1_io_in_a_ready; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_1_io_in_a_valid; // @[Broadcast.scala 107:15]
  wire [2:0] TLBroadcastTracker_1_io_in_a_bits_opcode; // @[Broadcast.scala 107:15]
  wire [2:0] TLBroadcastTracker_1_io_in_a_bits_param; // @[Broadcast.scala 107:15]
  wire [2:0] TLBroadcastTracker_1_io_in_a_bits_size; // @[Broadcast.scala 107:15]
  wire [1:0] TLBroadcastTracker_1_io_in_a_bits_source; // @[Broadcast.scala 107:15]
  wire [30:0] TLBroadcastTracker_1_io_in_a_bits_address; // @[Broadcast.scala 107:15]
  wire [3:0] TLBroadcastTracker_1_io_in_a_bits_mask; // @[Broadcast.scala 107:15]
  wire [31:0] TLBroadcastTracker_1_io_in_a_bits_data; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_1_io_out_a_ready; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_1_io_out_a_valid; // @[Broadcast.scala 107:15]
  wire [2:0] TLBroadcastTracker_1_io_out_a_bits_opcode; // @[Broadcast.scala 107:15]
  wire [2:0] TLBroadcastTracker_1_io_out_a_bits_param; // @[Broadcast.scala 107:15]
  wire [2:0] TLBroadcastTracker_1_io_out_a_bits_size; // @[Broadcast.scala 107:15]
  wire [3:0] TLBroadcastTracker_1_io_out_a_bits_source; // @[Broadcast.scala 107:15]
  wire [30:0] TLBroadcastTracker_1_io_out_a_bits_address; // @[Broadcast.scala 107:15]
  wire [3:0] TLBroadcastTracker_1_io_out_a_bits_mask; // @[Broadcast.scala 107:15]
  wire [31:0] TLBroadcastTracker_1_io_out_a_bits_data; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_1_io_probe_valid; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_1_io_probe_bits_count; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_1_io_probenack; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_1_io_probedack; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_1_io_probesack; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_1_io_d_last; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_1_io_e_last; // @[Broadcast.scala 107:15]
  wire [1:0] TLBroadcastTracker_1_io_source; // @[Broadcast.scala 107:15]
  wire [24:0] TLBroadcastTracker_1_io_line; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_1_io_idle; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_1_io_need_d; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_2_clock; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_2_reset; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_2_io_in_a_first; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_2_io_in_a_ready; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_2_io_in_a_valid; // @[Broadcast.scala 107:15]
  wire [2:0] TLBroadcastTracker_2_io_in_a_bits_opcode; // @[Broadcast.scala 107:15]
  wire [2:0] TLBroadcastTracker_2_io_in_a_bits_param; // @[Broadcast.scala 107:15]
  wire [2:0] TLBroadcastTracker_2_io_in_a_bits_size; // @[Broadcast.scala 107:15]
  wire [1:0] TLBroadcastTracker_2_io_in_a_bits_source; // @[Broadcast.scala 107:15]
  wire [30:0] TLBroadcastTracker_2_io_in_a_bits_address; // @[Broadcast.scala 107:15]
  wire [3:0] TLBroadcastTracker_2_io_in_a_bits_mask; // @[Broadcast.scala 107:15]
  wire [31:0] TLBroadcastTracker_2_io_in_a_bits_data; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_2_io_out_a_ready; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_2_io_out_a_valid; // @[Broadcast.scala 107:15]
  wire [2:0] TLBroadcastTracker_2_io_out_a_bits_opcode; // @[Broadcast.scala 107:15]
  wire [2:0] TLBroadcastTracker_2_io_out_a_bits_param; // @[Broadcast.scala 107:15]
  wire [2:0] TLBroadcastTracker_2_io_out_a_bits_size; // @[Broadcast.scala 107:15]
  wire [3:0] TLBroadcastTracker_2_io_out_a_bits_source; // @[Broadcast.scala 107:15]
  wire [30:0] TLBroadcastTracker_2_io_out_a_bits_address; // @[Broadcast.scala 107:15]
  wire [3:0] TLBroadcastTracker_2_io_out_a_bits_mask; // @[Broadcast.scala 107:15]
  wire [31:0] TLBroadcastTracker_2_io_out_a_bits_data; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_2_io_probe_valid; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_2_io_probe_bits_count; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_2_io_probenack; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_2_io_probedack; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_2_io_probesack; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_2_io_d_last; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_2_io_e_last; // @[Broadcast.scala 107:15]
  wire [1:0] TLBroadcastTracker_2_io_source; // @[Broadcast.scala 107:15]
  wire [24:0] TLBroadcastTracker_2_io_line; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_2_io_idle; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_2_io_need_d; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_3_clock; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_3_reset; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_3_io_in_a_first; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_3_io_in_a_ready; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_3_io_in_a_valid; // @[Broadcast.scala 107:15]
  wire [2:0] TLBroadcastTracker_3_io_in_a_bits_opcode; // @[Broadcast.scala 107:15]
  wire [2:0] TLBroadcastTracker_3_io_in_a_bits_param; // @[Broadcast.scala 107:15]
  wire [2:0] TLBroadcastTracker_3_io_in_a_bits_size; // @[Broadcast.scala 107:15]
  wire [1:0] TLBroadcastTracker_3_io_in_a_bits_source; // @[Broadcast.scala 107:15]
  wire [30:0] TLBroadcastTracker_3_io_in_a_bits_address; // @[Broadcast.scala 107:15]
  wire [3:0] TLBroadcastTracker_3_io_in_a_bits_mask; // @[Broadcast.scala 107:15]
  wire [31:0] TLBroadcastTracker_3_io_in_a_bits_data; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_3_io_out_a_ready; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_3_io_out_a_valid; // @[Broadcast.scala 107:15]
  wire [2:0] TLBroadcastTracker_3_io_out_a_bits_opcode; // @[Broadcast.scala 107:15]
  wire [2:0] TLBroadcastTracker_3_io_out_a_bits_param; // @[Broadcast.scala 107:15]
  wire [2:0] TLBroadcastTracker_3_io_out_a_bits_size; // @[Broadcast.scala 107:15]
  wire [3:0] TLBroadcastTracker_3_io_out_a_bits_source; // @[Broadcast.scala 107:15]
  wire [30:0] TLBroadcastTracker_3_io_out_a_bits_address; // @[Broadcast.scala 107:15]
  wire [3:0] TLBroadcastTracker_3_io_out_a_bits_mask; // @[Broadcast.scala 107:15]
  wire [31:0] TLBroadcastTracker_3_io_out_a_bits_data; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_3_io_probe_valid; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_3_io_probe_bits_count; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_3_io_probenack; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_3_io_probedack; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_3_io_probesack; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_3_io_d_last; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_3_io_e_last; // @[Broadcast.scala 107:15]
  wire [1:0] TLBroadcastTracker_3_io_source; // @[Broadcast.scala 107:15]
  wire [24:0] TLBroadcastTracker_3_io_line; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_3_io_idle; // @[Broadcast.scala 107:15]
  wire  TLBroadcastTracker_3_io_need_d; // @[Broadcast.scala 107:15]
  wire [3:0] _T = 4'h1 << auto_in_e_bits_sink; // @[OneHot.scala 57:35]
  wire  _T_14 = auto_out_d_bits_source[3:2] == 2'h1; // @[Broadcast.scala 119:27]
  wire  opdata = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [3:0] beatsLeft; // @[Arbiter.scala 87:30]
  wire  idle = beatsLeft == 4'h0; // @[Arbiter.scala 88:28]
  wire  _T_56 = opdata | ~auto_out_d_bits_source[3]; // @[Broadcast.scala 140:34]
  reg [3:0] counter; // @[Edges.scala 228:27]
  wire [2:0] _T_38 = opdata ? 3'h5 : 3'h6; // @[Broadcast.scala 132:36]
  wire [2:0] out_1_bits_opcode = auto_out_d_bits_source[3] ? _T_38 : auto_out_d_bits_opcode; // @[Broadcast.scala 130:21 131:24 132:30]
  wire  beats1_opdata = out_1_bits_opcode[0]; // @[Edges.scala 105:36]
  wire [12:0] _beats1_decode_T_1 = 13'h3f << auto_out_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _beats1_decode_T_3 = ~_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
  wire [3:0] beats1_decode = _beats1_decode_T_3[5:2]; // @[Edges.scala 219:59]
  wire [3:0] beats1 = beats1_opdata ? beats1_decode : 4'h0; // @[Edges.scala 220:14]
  wire  last = counter == 4'h1 | beats1 == 4'h0; // @[Edges.scala 231:37]
  wire  _T_35 = ~_T_14; // @[Broadcast.scala 129:51]
  wire  out_1_earlyValid = auto_out_d_valid & ~_T_14; // @[Broadcast.scala 129:48]
  wire  _T_113 = auto_in_c_bits_opcode == 3'h6; // @[Broadcast.scala 161:45]
  wire  out_earlyValid = auto_in_c_valid & _T_113; // @[Broadcast.scala 192:79]
  wire [1:0] _readys_T = {out_1_earlyValid,out_earlyValid}; // @[Cat.scala 31:58]
  wire [2:0] _readys_T_1 = {_readys_T, 1'h0}; // @[package.scala 244:48]
  wire [1:0] _readys_T_3 = _readys_T | _readys_T_1[1:0]; // @[package.scala 244:43]
  wire [2:0] _readys_T_5 = {_readys_T_3, 1'h0}; // @[Arbiter.scala 16:78]
  wire [1:0] _readys_T_7 = ~_readys_T_5[1:0]; // @[Arbiter.scala 16:61]
  wire  readys__1 = _readys_T_7[1]; // @[Arbiter.scala 95:86]
  reg  state__1; // @[Arbiter.scala 116:26]
  wire  allowed__1 = idle ? readys__1 : state__1; // @[Arbiter.scala 121:24]
  wire  out_1_ready = auto_in_d_ready & allowed__1; // @[Arbiter.scala 123:31]
  wire  _T_15 = out_1_ready & out_1_earlyValid; // @[Decoupled.scala 50:35]
  wire [3:0] counter1 = counter - 4'h1; // @[Edges.scala 229:28]
  wire  first = counter == 4'h0; // @[Edges.scala 230:25]
  wire [1:0] out_1_bits_source = auto_out_d_bits_source[1:0]; // @[Broadcast.scala 121:26 130:21]
  wire  _T_17 = TLBroadcastTracker_io_need_d & TLBroadcastTracker_io_source == out_1_bits_source; // @[Broadcast.scala 123:62]
  wire  _T_19 = TLBroadcastTracker_1_io_need_d & TLBroadcastTracker_1_io_source == out_1_bits_source; // @[Broadcast.scala 123:62]
  wire  _T_21 = TLBroadcastTracker_2_io_need_d & TLBroadcastTracker_2_io_source == out_1_bits_source; // @[Broadcast.scala 123:62]
  wire  _T_23 = TLBroadcastTracker_3_io_need_d & TLBroadcastTracker_3_io_source == out_1_bits_source; // @[Broadcast.scala 123:62]
  wire [3:0] _T_24 = {_T_23,_T_21,_T_19,_T_17}; // @[Broadcast.scala 123:102]
  reg [3:0] r; // @[Reg.scala 16:16]
  wire [3:0] _GEN_1 = first ? _T_24 : r; // @[Reg.scala 16:16 17:{18,22}]
  wire  _T_32 = ~reset; // @[Broadcast.scala 125:14]
  wire  bundleOut_0_d_ready = out_1_ready | _T_14; // @[Broadcast.scala 128:50]
  wire [1:0] _T_40 = auto_out_d_bits_source[2] ? 2'h0 : 2'h1; // @[Broadcast.scala 133:51]
  wire [1:0] _T_41 = opdata ? _T_40 : 2'h0; // @[Broadcast.scala 133:36]
  wire [1:0] out_1_bits_param = auto_out_d_bits_source[3] ? _T_41 : 2'h0; // @[Broadcast.scala 130:21 131:24 133:30]
  wire [1:0] hi_1 = _GEN_1[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] lo_1 = _GEN_1[1:0]; // @[OneHot.scala 31:18]
  wire  _T_42 = |hi_1; // @[OneHot.scala 32:14]
  wire [1:0] _T_43 = hi_1 | lo_1; // @[OneHot.scala 32:28]
  wire [1:0] out_1_bits_sink = {_T_42,_T_43[1]}; // @[Cat.scala 31:58]
  wire  _T_65 = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
  wire  _T_110 = auto_in_c_bits_opcode == 3'h4; // @[Broadcast.scala 158:45]
  wire  _T_111 = auto_in_c_bits_opcode == 3'h5; // @[Broadcast.scala 159:45]
  wire  _T_112 = auto_in_c_bits_opcode == 3'h7; // @[Broadcast.scala 160:45]
  wire  _T_115 = TLBroadcastTracker_io_line == auto_in_c_bits_address[30:6]; // @[Broadcast.scala 162:55]
  wire  _T_117 = TLBroadcastTracker_1_io_line == auto_in_c_bits_address[30:6]; // @[Broadcast.scala 162:55]
  wire  _T_119 = TLBroadcastTracker_2_io_line == auto_in_c_bits_address[30:6]; // @[Broadcast.scala 162:55]
  wire  _T_121 = TLBroadcastTracker_3_io_line == auto_in_c_bits_address[30:6]; // @[Broadcast.scala 162:55]
  wire [1:0] _T_122 = _T_115 ? TLBroadcastTracker_io_source : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_123 = _T_117 ? TLBroadcastTracker_1_io_source : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_124 = _T_119 ? TLBroadcastTracker_2_io_source : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_125 = _T_121 ? TLBroadcastTracker_3_io_source : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_126 = _T_122 | _T_123; // @[Mux.scala 27:73]
  wire [1:0] _T_127 = _T_126 | _T_124; // @[Mux.scala 27:73]
  wire [1:0] _T_128 = _T_127 | _T_125; // @[Mux.scala 27:73]
  wire  readys__0 = _readys_T_7[0]; // @[Arbiter.scala 95:86]
  reg  state__0; // @[Arbiter.scala 116:26]
  wire  allowed__0 = idle ? readys__0 : state__0; // @[Arbiter.scala 121:24]
  wire  out_ready = auto_in_d_ready & allowed__0; // @[Arbiter.scala 123:31]
  reg [3:0] beatsLeft_1; // @[Arbiter.scala 87:30]
  wire  idle_1 = beatsLeft_1 == 4'h0; // @[Arbiter.scala 88:28]
  wire  out_7_earlyValid = TLBroadcastTracker_3_io_out_a_valid; // @[ReadyValidCancel.scala 68:19 69:20]
  wire  out_6_earlyValid = TLBroadcastTracker_2_io_out_a_valid; // @[ReadyValidCancel.scala 68:19 69:20]
  wire  out_5_earlyValid = TLBroadcastTracker_1_io_out_a_valid; // @[ReadyValidCancel.scala 68:19 69:20]
  wire  out_4_earlyValid = TLBroadcastTracker_io_out_a_valid; // @[ReadyValidCancel.scala 68:19 69:20]
  wire  out_3_earlyValid = auto_in_c_valid & (_T_111 | _T_112); // @[Broadcast.scala 197:35]
  wire [4:0] _readys_T_10 = {out_7_earlyValid,out_6_earlyValid,out_5_earlyValid,out_4_earlyValid,out_3_earlyValid}; // @[Cat.scala 31:58]
  wire [5:0] _readys_T_11 = {_readys_T_10, 1'h0}; // @[package.scala 244:48]
  wire [4:0] _readys_T_13 = _readys_T_10 | _readys_T_11[4:0]; // @[package.scala 244:43]
  wire [6:0] _readys_T_14 = {_readys_T_13, 2'h0}; // @[package.scala 244:48]
  wire [4:0] _readys_T_16 = _readys_T_13 | _readys_T_14[4:0]; // @[package.scala 244:43]
  wire [8:0] _readys_T_17 = {_readys_T_16, 4'h0}; // @[package.scala 244:48]
  wire [4:0] _readys_T_19 = _readys_T_16 | _readys_T_17[4:0]; // @[package.scala 244:43]
  wire [5:0] _readys_T_21 = {_readys_T_19, 1'h0}; // @[Arbiter.scala 16:78]
  wire [4:0] _readys_T_23 = ~_readys_T_21[4:0]; // @[Arbiter.scala 16:61]
  wire  readys_1_0 = _readys_T_23[0]; // @[Arbiter.scala 95:86]
  reg  state_1_0; // @[Arbiter.scala 116:26]
  wire  allowed_1_0 = idle_1 ? readys_1_0 : state_1_0; // @[Arbiter.scala 121:24]
  wire  out_3_ready = auto_out_a_ready & allowed_1_0; // @[Arbiter.scala 123:31]
  wire  _bundleIn_0_c_ready_T = _T_113 ? out_ready : out_3_ready; // @[Broadcast.scala 184:38]
  wire  bundleIn_0_c_ready = _T_110 | _bundleIn_0_c_ready_T; // @[Broadcast.scala 184:32]
  wire  _T_135 = bundleIn_0_c_ready & auto_in_c_valid; // @[Decoupled.scala 50:35]
  wire  _T_136 = _T_110 | _T_111; // @[Broadcast.scala 170:52]
  wire  _T_149 = auto_in_c_bits_param == 3'h4; // @[Broadcast.scala 178:27]
  wire  _T_150 = auto_in_c_bits_param == 3'h0 | _T_149; // @[Broadcast.scala 177:50]
  wire [12:0] _beats1_decode_T_5 = 13'h3f << auto_in_c_bits_size; // @[package.scala 234:77]
  wire [5:0] _beats1_decode_T_7 = ~_beats1_decode_T_5[5:0]; // @[package.scala 234:46]
  wire [3:0] beats1_decode_1 = _beats1_decode_T_7[5:2]; // @[Edges.scala 219:59]
  wire [1:0] _T_197 = _T_112 ? 2'h2 : 2'h1; // @[Broadcast.scala 195:25]
  wire [1:0] _T_198 = _T_112 ? auto_in_c_bits_source : _T_128; // @[Broadcast.scala 196:25]
  wire [3:0] a_source = {_T_197,_T_198}; // @[Cat.scala 31:58]
  wire  a_mask_sizeOH_shiftAmount = auto_in_c_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _a_mask_sizeOH_T_1 = 2'h1 << a_mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] a_mask_sizeOH = _a_mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _a_mask_T = auto_in_c_bits_size >= 3'h2; // @[Misc.scala 205:21]
  wire  a_mask_size = a_mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  a_mask_bit = auto_in_c_bits_address[1]; // @[Misc.scala 209:26]
  wire  a_mask_nbit = ~a_mask_bit; // @[Misc.scala 210:20]
  wire  a_mask_acc = _a_mask_T | a_mask_size & a_mask_nbit; // @[Misc.scala 214:29]
  wire  a_mask_acc_1 = _a_mask_T | a_mask_size & a_mask_bit; // @[Misc.scala 214:29]
  wire  a_mask_size_1 = a_mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  a_mask_bit_1 = auto_in_c_bits_address[0]; // @[Misc.scala 209:26]
  wire  a_mask_nbit_1 = ~a_mask_bit_1; // @[Misc.scala 210:20]
  wire  a_mask_eq_2 = a_mask_nbit & a_mask_nbit_1; // @[Misc.scala 213:27]
  wire  a_mask_acc_2 = a_mask_acc | a_mask_size_1 & a_mask_eq_2; // @[Misc.scala 214:29]
  wire  a_mask_eq_3 = a_mask_nbit & a_mask_bit_1; // @[Misc.scala 213:27]
  wire  a_mask_acc_3 = a_mask_acc | a_mask_size_1 & a_mask_eq_3; // @[Misc.scala 214:29]
  wire  a_mask_eq_4 = a_mask_bit & a_mask_nbit_1; // @[Misc.scala 213:27]
  wire  a_mask_acc_4 = a_mask_acc_1 | a_mask_size_1 & a_mask_eq_4; // @[Misc.scala 214:29]
  wire  a_mask_eq_5 = a_mask_bit & a_mask_bit_1; // @[Misc.scala 213:27]
  wire  a_mask_acc_5 = a_mask_acc_1 | a_mask_size_1 & a_mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] a_mask = {a_mask_acc_5,a_mask_acc_4,a_mask_acc_3,a_mask_acc_2}; // @[Cat.scala 31:58]
  wire  latch = idle & auto_in_d_ready; // @[Arbiter.scala 89:24]
  wire  earlyWinner__0 = readys__0 & out_earlyValid; // @[Arbiter.scala 97:79]
  wire  earlyWinner__1 = readys__1 & out_1_earlyValid; // @[Arbiter.scala 97:79]
  wire  _prefixOR_T = earlyWinner__0 | earlyWinner__1; // @[Arbiter.scala 104:53]
  wire  _T_217 = out_earlyValid | out_1_earlyValid; // @[Arbiter.scala 107:36]
  wire  _T_218 = ~(out_earlyValid | out_1_earlyValid); // @[Arbiter.scala 107:15]
  wire  muxStateEarly__0 = idle ? earlyWinner__0 : state__0; // @[Arbiter.scala 117:30]
  wire  muxStateEarly__1 = idle ? earlyWinner__1 : state__1; // @[Arbiter.scala 117:30]
  wire  _sink_ACancel_earlyValid_T_3 = state__0 & out_earlyValid | state__1 & out_1_earlyValid; // @[Mux.scala 27:73]
  wire  sink_ACancel_earlyValid = idle ? _T_217 : _sink_ACancel_earlyValid_T_3; // @[Arbiter.scala 125:29]
  wire  _beatsLeft_T_2 = auto_in_d_ready & sink_ACancel_earlyValid; // @[ReadyValidCancel.scala 49:33]
  wire [3:0] _GEN_14 = {{3'd0}, _beatsLeft_T_2}; // @[Arbiter.scala 113:52]
  wire [3:0] _beatsLeft_T_4 = beatsLeft - _GEN_14; // @[Arbiter.scala 113:52]
  wire [1:0] _T_243 = muxStateEarly__0 ? auto_in_c_bits_source : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_244 = muxStateEarly__1 ? out_1_bits_source : 2'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_246 = muxStateEarly__0 ? auto_in_c_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_247 = muxStateEarly__1 ? auto_out_d_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_252 = muxStateEarly__0 ? 3'h6 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_253 = muxStateEarly__1 ? out_1_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [12:0] _decode_T_13 = 13'h3f << TLBroadcastTracker_io_out_a_bits_size; // @[package.scala 234:77]
  wire [5:0] _decode_T_15 = ~_decode_T_13[5:0]; // @[package.scala 234:46]
  wire [3:0] decode_3 = _decode_T_15[5:2]; // @[Edges.scala 219:59]
  wire  opdata_4 = ~TLBroadcastTracker_io_out_a_bits_opcode[2]; // @[Edges.scala 91:28]
  wire [3:0] _T_256 = opdata_4 ? decode_3 : 4'h0; // @[Edges.scala 220:14]
  wire [12:0] _decode_T_17 = 13'h3f << TLBroadcastTracker_1_io_out_a_bits_size; // @[package.scala 234:77]
  wire [5:0] _decode_T_19 = ~_decode_T_17[5:0]; // @[package.scala 234:46]
  wire [3:0] decode_4 = _decode_T_19[5:2]; // @[Edges.scala 219:59]
  wire  opdata_5 = ~TLBroadcastTracker_1_io_out_a_bits_opcode[2]; // @[Edges.scala 91:28]
  wire [3:0] _T_257 = opdata_5 ? decode_4 : 4'h0; // @[Edges.scala 220:14]
  wire [12:0] _decode_T_21 = 13'h3f << TLBroadcastTracker_2_io_out_a_bits_size; // @[package.scala 234:77]
  wire [5:0] _decode_T_23 = ~_decode_T_21[5:0]; // @[package.scala 234:46]
  wire [3:0] decode_5 = _decode_T_23[5:2]; // @[Edges.scala 219:59]
  wire  opdata_6 = ~TLBroadcastTracker_2_io_out_a_bits_opcode[2]; // @[Edges.scala 91:28]
  wire [3:0] _T_258 = opdata_6 ? decode_5 : 4'h0; // @[Edges.scala 220:14]
  wire [12:0] _decode_T_25 = 13'h3f << TLBroadcastTracker_3_io_out_a_bits_size; // @[package.scala 234:77]
  wire [5:0] _decode_T_27 = ~_decode_T_25[5:0]; // @[package.scala 234:46]
  wire [3:0] decode_6 = _decode_T_27[5:2]; // @[Edges.scala 219:59]
  wire  opdata_7 = ~TLBroadcastTracker_3_io_out_a_bits_opcode[2]; // @[Edges.scala 91:28]
  wire [3:0] _T_259 = opdata_7 ? decode_6 : 4'h0; // @[Edges.scala 220:14]
  wire  latch_1 = idle_1 & auto_out_a_ready; // @[Arbiter.scala 89:24]
  wire  readys_1_1 = _readys_T_23[1]; // @[Arbiter.scala 95:86]
  wire  readys_1_2 = _readys_T_23[2]; // @[Arbiter.scala 95:86]
  wire  readys_1_3 = _readys_T_23[3]; // @[Arbiter.scala 95:86]
  wire  readys_1_4 = _readys_T_23[4]; // @[Arbiter.scala 95:86]
  wire  earlyWinner_1_0 = readys_1_0 & out_3_earlyValid; // @[Arbiter.scala 97:79]
  wire  earlyWinner_1_1 = readys_1_1 & out_4_earlyValid; // @[Arbiter.scala 97:79]
  wire  earlyWinner_1_2 = readys_1_2 & out_5_earlyValid; // @[Arbiter.scala 97:79]
  wire  earlyWinner_1_3 = readys_1_3 & out_6_earlyValid; // @[Arbiter.scala 97:79]
  wire  earlyWinner_1_4 = readys_1_4 & out_7_earlyValid; // @[Arbiter.scala 97:79]
  wire  prefixOR_2 = earlyWinner_1_0 | earlyWinner_1_1; // @[Arbiter.scala 104:53]
  wire  prefixOR_3 = prefixOR_2 | earlyWinner_1_2; // @[Arbiter.scala 104:53]
  wire  prefixOR_4 = prefixOR_3 | earlyWinner_1_3; // @[Arbiter.scala 104:53]
  wire  _prefixOR_T_1 = prefixOR_4 | earlyWinner_1_4; // @[Arbiter.scala 104:53]
  wire  _T_285 = out_3_earlyValid | out_4_earlyValid | out_5_earlyValid | out_6_earlyValid | out_7_earlyValid; // @[Arbiter.scala 107:36]
  wire  _T_286 = ~(out_3_earlyValid | out_4_earlyValid | out_5_earlyValid | out_6_earlyValid | out_7_earlyValid); // @[Arbiter.scala 107:15]
  wire [3:0] maskedBeats_0_1 = earlyWinner_1_0 ? beats1_decode_1 : 4'h0; // @[Arbiter.scala 111:73]
  wire [3:0] maskedBeats_1_1 = earlyWinner_1_1 ? _T_256 : 4'h0; // @[Arbiter.scala 111:73]
  wire [3:0] maskedBeats_2 = earlyWinner_1_2 ? _T_257 : 4'h0; // @[Arbiter.scala 111:73]
  wire [3:0] maskedBeats_3 = earlyWinner_1_3 ? _T_258 : 4'h0; // @[Arbiter.scala 111:73]
  wire [3:0] maskedBeats_4 = earlyWinner_1_4 ? _T_259 : 4'h0; // @[Arbiter.scala 111:73]
  wire [3:0] _initBeats_T = maskedBeats_0_1 | maskedBeats_1_1; // @[Arbiter.scala 112:44]
  wire [3:0] _initBeats_T_1 = _initBeats_T | maskedBeats_2; // @[Arbiter.scala 112:44]
  wire [3:0] _initBeats_T_2 = _initBeats_T_1 | maskedBeats_3; // @[Arbiter.scala 112:44]
  wire [3:0] initBeats_1 = _initBeats_T_2 | maskedBeats_4; // @[Arbiter.scala 112:44]
  wire  muxStateEarly_1_0 = idle_1 ? earlyWinner_1_0 : state_1_0; // @[Arbiter.scala 117:30]
  reg  state_1_1; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_1_1 = idle_1 ? earlyWinner_1_1 : state_1_1; // @[Arbiter.scala 117:30]
  reg  state_1_2; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_1_2 = idle_1 ? earlyWinner_1_2 : state_1_2; // @[Arbiter.scala 117:30]
  reg  state_1_3; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_1_3 = idle_1 ? earlyWinner_1_3 : state_1_3; // @[Arbiter.scala 117:30]
  reg  state_1_4; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_1_4 = idle_1 ? earlyWinner_1_4 : state_1_4; // @[Arbiter.scala 117:30]
  wire  _sink_ACancel_earlyValid_T_17 = state_1_0 & out_3_earlyValid | state_1_1 & out_4_earlyValid | state_1_2 &
    out_5_earlyValid | state_1_3 & out_6_earlyValid | state_1_4 & out_7_earlyValid; // @[Mux.scala 27:73]
  wire  sink_ACancel_1_earlyValid = idle_1 ? _T_285 : _sink_ACancel_earlyValid_T_17; // @[Arbiter.scala 125:29]
  wire  _beatsLeft_T_8 = auto_out_a_ready & sink_ACancel_1_earlyValid; // @[ReadyValidCancel.scala 49:33]
  wire [3:0] _GEN_15 = {{3'd0}, _beatsLeft_T_8}; // @[Arbiter.scala 113:52]
  wire [3:0] _beatsLeft_T_10 = beatsLeft_1 - _GEN_15; // @[Arbiter.scala 113:52]
  wire  allowed_1_1 = idle_1 ? readys_1_1 : state_1_1; // @[Arbiter.scala 121:24]
  wire  allowed_1_2 = idle_1 ? readys_1_2 : state_1_2; // @[Arbiter.scala 121:24]
  wire  allowed_1_3 = idle_1 ? readys_1_3 : state_1_3; // @[Arbiter.scala 121:24]
  wire  allowed_1_4 = idle_1 ? readys_1_4 : state_1_4; // @[Arbiter.scala 121:24]
  wire [31:0] _T_317 = muxStateEarly_1_0 ? auto_in_c_bits_data : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] out_4_bits_data = TLBroadcastTracker_io_out_a_bits_data; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [31:0] _T_318 = muxStateEarly_1_1 ? out_4_bits_data : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] out_5_bits_data = TLBroadcastTracker_1_io_out_a_bits_data; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [31:0] _T_319 = muxStateEarly_1_2 ? out_5_bits_data : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] out_6_bits_data = TLBroadcastTracker_2_io_out_a_bits_data; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [31:0] _T_320 = muxStateEarly_1_3 ? out_6_bits_data : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] out_7_bits_data = TLBroadcastTracker_3_io_out_a_bits_data; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [31:0] _T_321 = muxStateEarly_1_4 ? out_7_bits_data : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_322 = _T_317 | _T_318; // @[Mux.scala 27:73]
  wire [31:0] _T_323 = _T_322 | _T_319; // @[Mux.scala 27:73]
  wire [31:0] _T_324 = _T_323 | _T_320; // @[Mux.scala 27:73]
  wire [3:0] _T_326 = muxStateEarly_1_0 ? a_mask : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] out_4_bits_mask = TLBroadcastTracker_io_out_a_bits_mask; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [3:0] _T_327 = muxStateEarly_1_1 ? out_4_bits_mask : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] out_5_bits_mask = TLBroadcastTracker_1_io_out_a_bits_mask; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [3:0] _T_328 = muxStateEarly_1_2 ? out_5_bits_mask : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] out_6_bits_mask = TLBroadcastTracker_2_io_out_a_bits_mask; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [3:0] _T_329 = muxStateEarly_1_3 ? out_6_bits_mask : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] out_7_bits_mask = TLBroadcastTracker_3_io_out_a_bits_mask; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [3:0] _T_330 = muxStateEarly_1_4 ? out_7_bits_mask : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _T_331 = _T_326 | _T_327; // @[Mux.scala 27:73]
  wire [3:0] _T_332 = _T_331 | _T_328; // @[Mux.scala 27:73]
  wire [3:0] _T_333 = _T_332 | _T_329; // @[Mux.scala 27:73]
  wire [30:0] _T_335 = muxStateEarly_1_0 ? auto_in_c_bits_address : 31'h0; // @[Mux.scala 27:73]
  wire [30:0] out_4_bits_address = TLBroadcastTracker_io_out_a_bits_address; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [30:0] _T_336 = muxStateEarly_1_1 ? out_4_bits_address : 31'h0; // @[Mux.scala 27:73]
  wire [30:0] out_5_bits_address = TLBroadcastTracker_1_io_out_a_bits_address; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [30:0] _T_337 = muxStateEarly_1_2 ? out_5_bits_address : 31'h0; // @[Mux.scala 27:73]
  wire [30:0] out_6_bits_address = TLBroadcastTracker_2_io_out_a_bits_address; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [30:0] _T_338 = muxStateEarly_1_3 ? out_6_bits_address : 31'h0; // @[Mux.scala 27:73]
  wire [30:0] out_7_bits_address = TLBroadcastTracker_3_io_out_a_bits_address; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [30:0] _T_339 = muxStateEarly_1_4 ? out_7_bits_address : 31'h0; // @[Mux.scala 27:73]
  wire [30:0] _T_340 = _T_335 | _T_336; // @[Mux.scala 27:73]
  wire [30:0] _T_341 = _T_340 | _T_337; // @[Mux.scala 27:73]
  wire [30:0] _T_342 = _T_341 | _T_338; // @[Mux.scala 27:73]
  wire [3:0] _T_344 = muxStateEarly_1_0 ? a_source : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] out_4_bits_source = TLBroadcastTracker_io_out_a_bits_source; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [3:0] _T_345 = muxStateEarly_1_1 ? out_4_bits_source : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] out_5_bits_source = TLBroadcastTracker_1_io_out_a_bits_source; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [3:0] _T_346 = muxStateEarly_1_2 ? out_5_bits_source : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] out_6_bits_source = TLBroadcastTracker_2_io_out_a_bits_source; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [3:0] _T_347 = muxStateEarly_1_3 ? out_6_bits_source : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] out_7_bits_source = TLBroadcastTracker_3_io_out_a_bits_source; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [3:0] _T_348 = muxStateEarly_1_4 ? out_7_bits_source : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _T_349 = _T_344 | _T_345; // @[Mux.scala 27:73]
  wire [3:0] _T_350 = _T_349 | _T_346; // @[Mux.scala 27:73]
  wire [3:0] _T_351 = _T_350 | _T_347; // @[Mux.scala 27:73]
  wire [2:0] _T_353 = muxStateEarly_1_0 ? auto_in_c_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] out_4_bits_size = TLBroadcastTracker_io_out_a_bits_size; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [2:0] _T_354 = muxStateEarly_1_1 ? out_4_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] out_5_bits_size = TLBroadcastTracker_1_io_out_a_bits_size; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [2:0] _T_355 = muxStateEarly_1_2 ? out_5_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] out_6_bits_size = TLBroadcastTracker_2_io_out_a_bits_size; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [2:0] _T_356 = muxStateEarly_1_3 ? out_6_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] out_7_bits_size = TLBroadcastTracker_3_io_out_a_bits_size; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [2:0] _T_357 = muxStateEarly_1_4 ? out_7_bits_size : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_358 = _T_353 | _T_354; // @[Mux.scala 27:73]
  wire [2:0] _T_359 = _T_358 | _T_355; // @[Mux.scala 27:73]
  wire [2:0] _T_360 = _T_359 | _T_356; // @[Mux.scala 27:73]
  wire [2:0] out_4_bits_param = TLBroadcastTracker_io_out_a_bits_param; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [2:0] _T_363 = muxStateEarly_1_1 ? out_4_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] out_5_bits_param = TLBroadcastTracker_1_io_out_a_bits_param; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [2:0] _T_364 = muxStateEarly_1_2 ? out_5_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] out_6_bits_param = TLBroadcastTracker_2_io_out_a_bits_param; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [2:0] _T_365 = muxStateEarly_1_3 ? out_6_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] out_7_bits_param = TLBroadcastTracker_3_io_out_a_bits_param; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [2:0] _T_366 = muxStateEarly_1_4 ? out_7_bits_param : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_368 = _T_363 | _T_364; // @[Mux.scala 27:73]
  wire [2:0] _T_369 = _T_368 | _T_365; // @[Mux.scala 27:73]
  wire [2:0] out_4_bits_opcode = TLBroadcastTracker_io_out_a_bits_opcode; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [2:0] _T_372 = muxStateEarly_1_1 ? out_4_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] out_5_bits_opcode = TLBroadcastTracker_1_io_out_a_bits_opcode; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [2:0] _T_373 = muxStateEarly_1_2 ? out_5_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] out_6_bits_opcode = TLBroadcastTracker_2_io_out_a_bits_opcode; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [2:0] _T_374 = muxStateEarly_1_3 ? out_6_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] out_7_bits_opcode = TLBroadcastTracker_3_io_out_a_bits_opcode; // @[ReadyValidCancel.scala 68:19 71:14]
  wire [2:0] _T_375 = muxStateEarly_1_4 ? out_7_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_377 = _T_372 | _T_373; // @[Mux.scala 27:73]
  wire [2:0] _T_378 = _T_377 | _T_374; // @[Mux.scala 27:73]
  reg  REG; // @[Broadcast.scala 215:31]
  reg [24:0] REG_1; // @[Broadcast.scala 216:27]
  reg [1:0] REG_2; // @[Broadcast.scala 217:28]
  wire [1:0] _T_381 = {REG, 1'h0}; // @[Broadcast.scala 218:58]
  wire [1:0] _T_382 = ~_T_381; // @[Broadcast.scala 218:37]
  wire [1:0] _GEN_16 = {{1'd0}, REG}; // @[Broadcast.scala 218:35]
  wire [1:0] _T_383 = _GEN_16 & _T_382; // @[Broadcast.scala 218:35]
  wire  bundleIn_0_b_valid = |REG; // @[Broadcast.scala 219:38]
  wire  _T_386 = auto_in_b_ready & bundleIn_0_b_valid; // @[Decoupled.scala 50:35]
  wire [1:0] _T_387 = ~_T_383; // @[Broadcast.scala 227:55]
  wire [1:0] _T_388 = _GEN_16 & _T_387; // @[Broadcast.scala 227:53]
  wire [1:0] _GEN_5 = _T_386 ? _T_388 : {{1'd0}, REG}; // @[Broadcast.scala 227:26 215:31 227:39]
  reg [3:0] counter_2; // @[Edges.scala 228:27]
  wire  first_2 = counter_2 == 4'h0; // @[Edges.scala 230:25]
  wire  _bundleIn_0_a_ready_T_1 = ~first_2 | BroadcastFilter_io_request_ready; // @[Broadcast.scala 243:31]
  wire [3:0] _T_401 = {TLBroadcastTracker_3_io_line == auto_in_a_bits_address[30:6],TLBroadcastTracker_2_io_line ==
    auto_in_a_bits_address[30:6],TLBroadcastTracker_1_io_line == auto_in_a_bits_address[30:6],TLBroadcastTracker_io_line
     == auto_in_a_bits_address[30:6]}; // @[Broadcast.scala 236:100]
  wire  _T_402 = |_T_401; // @[Broadcast.scala 237:43]
  wire  _WIRE_30_3 = TLBroadcastTracker_3_io_idle; // @[Broadcast.scala 234:{33,33}]
  wire  _WIRE_30_2 = TLBroadcastTracker_2_io_idle; // @[Broadcast.scala 234:{33,33}]
  wire  _WIRE_30_1 = TLBroadcastTracker_1_io_idle; // @[Broadcast.scala 234:{33,33}]
  wire  _WIRE_30_0 = TLBroadcastTracker_io_idle; // @[Broadcast.scala 234:{33,33}]
  wire [3:0] _T_391 = {_WIRE_30_3,_WIRE_30_2,_WIRE_30_1,_WIRE_30_0}; // @[Broadcast.scala 234:64]
  wire [4:0] _T_403 = {_T_391, 1'h0}; // @[package.scala 244:48]
  wire [3:0] _T_405 = _T_391 | _T_403[3:0]; // @[package.scala 244:43]
  wire [5:0] _T_406 = {_T_405, 2'h0}; // @[package.scala 244:48]
  wire [3:0] _T_408 = _T_405 | _T_406[3:0]; // @[package.scala 244:43]
  wire [4:0] _T_410 = {_T_408, 1'h0}; // @[Broadcast.scala 238:64]
  wire [4:0] _T_411 = ~_T_410; // @[Broadcast.scala 238:41]
  wire [4:0] _GEN_18 = {{1'd0}, _T_391}; // @[Broadcast.scala 238:39]
  wire [4:0] _T_412 = _GEN_18 & _T_411; // @[Broadcast.scala 238:39]
  wire [4:0] _T_413 = _T_402 ? {{1'd0}, _T_401} : _T_412; // @[Broadcast.scala 239:30]
  wire  _WIRE_32_3 = TLBroadcastTracker_3_io_in_a_ready; // @[Broadcast.scala 240:{34,34}]
  wire  _WIRE_32_2 = TLBroadcastTracker_2_io_in_a_ready; // @[Broadcast.scala 240:{34,34}]
  wire  _WIRE_32_1 = TLBroadcastTracker_1_io_in_a_ready; // @[Broadcast.scala 240:{34,34}]
  wire  _WIRE_32_0 = TLBroadcastTracker_io_in_a_ready; // @[Broadcast.scala 240:{34,34}]
  wire [3:0] _T_414 = {_WIRE_32_3,_WIRE_32_2,_WIRE_32_1,_WIRE_32_0}; // @[Broadcast.scala 240:63]
  wire [4:0] _GEN_19 = {{1'd0}, _T_414}; // @[Broadcast.scala 241:41]
  wire [4:0] _T_415 = _T_413 & _GEN_19; // @[Broadcast.scala 241:41]
  wire  _T_416 = |_T_415; // @[Broadcast.scala 241:61]
  wire  bundleIn_0_a_ready = (~first_2 | BroadcastFilter_io_request_ready) & _T_416; // @[Broadcast.scala 243:59]
  wire  _T_390 = bundleIn_0_a_ready & auto_in_a_valid; // @[Decoupled.scala 50:35]
  wire [12:0] _beats1_decode_T_9 = 13'h3f << auto_in_a_bits_size; // @[package.scala 234:77]
  wire [5:0] _beats1_decode_T_11 = ~_beats1_decode_T_9[5:0]; // @[package.scala 234:46]
  wire [3:0] beats1_decode_2 = _beats1_decode_T_11[5:2]; // @[Edges.scala 219:59]
  wire  beats1_opdata_2 = ~auto_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  wire [3:0] counter1_2 = counter_2 - 4'h1; // @[Edges.scala 229:28]
  wire [3:0] lo_5 = _T_413[3:0]; // @[OneHot.scala 31:18]
  wire  _T_440 = |_T_413[4]; // @[OneHot.scala 32:14]
  wire [3:0] _GEN_20 = {{3'd0}, _T_413[4]}; // @[OneHot.scala 32:28]
  wire [3:0] _T_441 = _GEN_20 | lo_5; // @[OneHot.scala 32:28]
  wire [1:0] hi_6 = _T_441[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] lo_6 = _T_441[1:0]; // @[OneHot.scala 31:18]
  wire  _T_442 = |hi_6; // @[OneHot.scala 32:14]
  wire [1:0] _T_443 = hi_6 | lo_6; // @[OneHot.scala 32:28]
  wire [2:0] _T_446 = {_T_440,_T_442,_T_443[1]}; // @[Cat.scala 31:58]
  wire  acq_needT = 3'h2 == auto_in_a_bits_param | 3'h1 == auto_in_a_bits_param; // @[Mux.scala 81:58]
  wire  _T_458 = 3'h4 == auto_in_a_bits_opcode ? 1'h0 : 1'h1; // @[Mux.scala 81:58]
  wire  _T_460 = 3'h5 == auto_in_a_bits_opcode ? 3'h1 == auto_in_a_bits_param : _T_458; // @[Mux.scala 81:58]
  wire  _T_462 = 3'h6 == auto_in_a_bits_opcode ? acq_needT : _T_460; // @[Mux.scala 81:58]
  wire  _T_468 = ~BroadcastFilter_io_response_bits_allocOH; // @[Broadcast.scala 257:54]
  wire  _T_472 = BroadcastFilter_io_response_ready & BroadcastFilter_io_response_valid; // @[Decoupled.scala 50:35]
  wire [1:0] _GEN_7 = _T_472 ? {{1'd0}, _T_468} : _GEN_5; // @[Broadcast.scala 260:40 261:21]
  wire [1:0] shiftAmount = BroadcastFilter_io_response_bits_mshr; // @[OneHot.scala 63:49]
  wire [3:0] _T_477 = 4'h1 << shiftAmount; // @[OneHot.scala 64:12]
  TLMonitor_41 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_b_ready(monitor_io_in_b_ready),
    .io_in_b_valid(monitor_io_in_b_valid),
    .io_in_b_bits_param(monitor_io_in_b_bits_param),
    .io_in_b_bits_address(monitor_io_in_b_bits_address),
    .io_in_c_ready(monitor_io_in_c_ready),
    .io_in_c_valid(monitor_io_in_c_valid),
    .io_in_c_bits_opcode(monitor_io_in_c_bits_opcode),
    .io_in_c_bits_param(monitor_io_in_c_bits_param),
    .io_in_c_bits_size(monitor_io_in_c_bits_size),
    .io_in_c_bits_source(monitor_io_in_c_bits_source),
    .io_in_c_bits_address(monitor_io_in_c_bits_address),
    .io_in_c_bits_corrupt(monitor_io_in_c_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_param(monitor_io_in_d_bits_param),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source),
    .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
    .io_in_e_valid(monitor_io_in_e_valid),
    .io_in_e_bits_sink(monitor_io_in_e_bits_sink)
  );
  BroadcastFilter BroadcastFilter ( // @[Broadcast.scala 99:26]
    .io_request_ready(BroadcastFilter_io_request_ready),
    .io_request_valid(BroadcastFilter_io_request_valid),
    .io_request_bits_mshr(BroadcastFilter_io_request_bits_mshr),
    .io_request_bits_address(BroadcastFilter_io_request_bits_address),
    .io_request_bits_allocOH(BroadcastFilter_io_request_bits_allocOH),
    .io_request_bits_needT(BroadcastFilter_io_request_bits_needT),
    .io_response_ready(BroadcastFilter_io_response_ready),
    .io_response_valid(BroadcastFilter_io_response_valid),
    .io_response_bits_mshr(BroadcastFilter_io_response_bits_mshr),
    .io_response_bits_address(BroadcastFilter_io_response_bits_address),
    .io_response_bits_allocOH(BroadcastFilter_io_response_bits_allocOH),
    .io_response_bits_needT(BroadcastFilter_io_response_bits_needT)
  );
  TLBroadcastTracker TLBroadcastTracker ( // @[Broadcast.scala 107:15]
    .clock(TLBroadcastTracker_clock),
    .reset(TLBroadcastTracker_reset),
    .io_in_a_first(TLBroadcastTracker_io_in_a_first),
    .io_in_a_ready(TLBroadcastTracker_io_in_a_ready),
    .io_in_a_valid(TLBroadcastTracker_io_in_a_valid),
    .io_in_a_bits_opcode(TLBroadcastTracker_io_in_a_bits_opcode),
    .io_in_a_bits_param(TLBroadcastTracker_io_in_a_bits_param),
    .io_in_a_bits_size(TLBroadcastTracker_io_in_a_bits_size),
    .io_in_a_bits_source(TLBroadcastTracker_io_in_a_bits_source),
    .io_in_a_bits_address(TLBroadcastTracker_io_in_a_bits_address),
    .io_in_a_bits_mask(TLBroadcastTracker_io_in_a_bits_mask),
    .io_in_a_bits_data(TLBroadcastTracker_io_in_a_bits_data),
    .io_out_a_ready(TLBroadcastTracker_io_out_a_ready),
    .io_out_a_valid(TLBroadcastTracker_io_out_a_valid),
    .io_out_a_bits_opcode(TLBroadcastTracker_io_out_a_bits_opcode),
    .io_out_a_bits_param(TLBroadcastTracker_io_out_a_bits_param),
    .io_out_a_bits_size(TLBroadcastTracker_io_out_a_bits_size),
    .io_out_a_bits_source(TLBroadcastTracker_io_out_a_bits_source),
    .io_out_a_bits_address(TLBroadcastTracker_io_out_a_bits_address),
    .io_out_a_bits_mask(TLBroadcastTracker_io_out_a_bits_mask),
    .io_out_a_bits_data(TLBroadcastTracker_io_out_a_bits_data),
    .io_probe_valid(TLBroadcastTracker_io_probe_valid),
    .io_probe_bits_count(TLBroadcastTracker_io_probe_bits_count),
    .io_probenack(TLBroadcastTracker_io_probenack),
    .io_probedack(TLBroadcastTracker_io_probedack),
    .io_probesack(TLBroadcastTracker_io_probesack),
    .io_d_last(TLBroadcastTracker_io_d_last),
    .io_e_last(TLBroadcastTracker_io_e_last),
    .io_source(TLBroadcastTracker_io_source),
    .io_line(TLBroadcastTracker_io_line),
    .io_idle(TLBroadcastTracker_io_idle),
    .io_need_d(TLBroadcastTracker_io_need_d)
  );
  TLBroadcastTracker_1 TLBroadcastTracker_1 ( // @[Broadcast.scala 107:15]
    .clock(TLBroadcastTracker_1_clock),
    .reset(TLBroadcastTracker_1_reset),
    .io_in_a_first(TLBroadcastTracker_1_io_in_a_first),
    .io_in_a_ready(TLBroadcastTracker_1_io_in_a_ready),
    .io_in_a_valid(TLBroadcastTracker_1_io_in_a_valid),
    .io_in_a_bits_opcode(TLBroadcastTracker_1_io_in_a_bits_opcode),
    .io_in_a_bits_param(TLBroadcastTracker_1_io_in_a_bits_param),
    .io_in_a_bits_size(TLBroadcastTracker_1_io_in_a_bits_size),
    .io_in_a_bits_source(TLBroadcastTracker_1_io_in_a_bits_source),
    .io_in_a_bits_address(TLBroadcastTracker_1_io_in_a_bits_address),
    .io_in_a_bits_mask(TLBroadcastTracker_1_io_in_a_bits_mask),
    .io_in_a_bits_data(TLBroadcastTracker_1_io_in_a_bits_data),
    .io_out_a_ready(TLBroadcastTracker_1_io_out_a_ready),
    .io_out_a_valid(TLBroadcastTracker_1_io_out_a_valid),
    .io_out_a_bits_opcode(TLBroadcastTracker_1_io_out_a_bits_opcode),
    .io_out_a_bits_param(TLBroadcastTracker_1_io_out_a_bits_param),
    .io_out_a_bits_size(TLBroadcastTracker_1_io_out_a_bits_size),
    .io_out_a_bits_source(TLBroadcastTracker_1_io_out_a_bits_source),
    .io_out_a_bits_address(TLBroadcastTracker_1_io_out_a_bits_address),
    .io_out_a_bits_mask(TLBroadcastTracker_1_io_out_a_bits_mask),
    .io_out_a_bits_data(TLBroadcastTracker_1_io_out_a_bits_data),
    .io_probe_valid(TLBroadcastTracker_1_io_probe_valid),
    .io_probe_bits_count(TLBroadcastTracker_1_io_probe_bits_count),
    .io_probenack(TLBroadcastTracker_1_io_probenack),
    .io_probedack(TLBroadcastTracker_1_io_probedack),
    .io_probesack(TLBroadcastTracker_1_io_probesack),
    .io_d_last(TLBroadcastTracker_1_io_d_last),
    .io_e_last(TLBroadcastTracker_1_io_e_last),
    .io_source(TLBroadcastTracker_1_io_source),
    .io_line(TLBroadcastTracker_1_io_line),
    .io_idle(TLBroadcastTracker_1_io_idle),
    .io_need_d(TLBroadcastTracker_1_io_need_d)
  );
  TLBroadcastTracker_2 TLBroadcastTracker_2 ( // @[Broadcast.scala 107:15]
    .clock(TLBroadcastTracker_2_clock),
    .reset(TLBroadcastTracker_2_reset),
    .io_in_a_first(TLBroadcastTracker_2_io_in_a_first),
    .io_in_a_ready(TLBroadcastTracker_2_io_in_a_ready),
    .io_in_a_valid(TLBroadcastTracker_2_io_in_a_valid),
    .io_in_a_bits_opcode(TLBroadcastTracker_2_io_in_a_bits_opcode),
    .io_in_a_bits_param(TLBroadcastTracker_2_io_in_a_bits_param),
    .io_in_a_bits_size(TLBroadcastTracker_2_io_in_a_bits_size),
    .io_in_a_bits_source(TLBroadcastTracker_2_io_in_a_bits_source),
    .io_in_a_bits_address(TLBroadcastTracker_2_io_in_a_bits_address),
    .io_in_a_bits_mask(TLBroadcastTracker_2_io_in_a_bits_mask),
    .io_in_a_bits_data(TLBroadcastTracker_2_io_in_a_bits_data),
    .io_out_a_ready(TLBroadcastTracker_2_io_out_a_ready),
    .io_out_a_valid(TLBroadcastTracker_2_io_out_a_valid),
    .io_out_a_bits_opcode(TLBroadcastTracker_2_io_out_a_bits_opcode),
    .io_out_a_bits_param(TLBroadcastTracker_2_io_out_a_bits_param),
    .io_out_a_bits_size(TLBroadcastTracker_2_io_out_a_bits_size),
    .io_out_a_bits_source(TLBroadcastTracker_2_io_out_a_bits_source),
    .io_out_a_bits_address(TLBroadcastTracker_2_io_out_a_bits_address),
    .io_out_a_bits_mask(TLBroadcastTracker_2_io_out_a_bits_mask),
    .io_out_a_bits_data(TLBroadcastTracker_2_io_out_a_bits_data),
    .io_probe_valid(TLBroadcastTracker_2_io_probe_valid),
    .io_probe_bits_count(TLBroadcastTracker_2_io_probe_bits_count),
    .io_probenack(TLBroadcastTracker_2_io_probenack),
    .io_probedack(TLBroadcastTracker_2_io_probedack),
    .io_probesack(TLBroadcastTracker_2_io_probesack),
    .io_d_last(TLBroadcastTracker_2_io_d_last),
    .io_e_last(TLBroadcastTracker_2_io_e_last),
    .io_source(TLBroadcastTracker_2_io_source),
    .io_line(TLBroadcastTracker_2_io_line),
    .io_idle(TLBroadcastTracker_2_io_idle),
    .io_need_d(TLBroadcastTracker_2_io_need_d)
  );
  TLBroadcastTracker_3 TLBroadcastTracker_3 ( // @[Broadcast.scala 107:15]
    .clock(TLBroadcastTracker_3_clock),
    .reset(TLBroadcastTracker_3_reset),
    .io_in_a_first(TLBroadcastTracker_3_io_in_a_first),
    .io_in_a_ready(TLBroadcastTracker_3_io_in_a_ready),
    .io_in_a_valid(TLBroadcastTracker_3_io_in_a_valid),
    .io_in_a_bits_opcode(TLBroadcastTracker_3_io_in_a_bits_opcode),
    .io_in_a_bits_param(TLBroadcastTracker_3_io_in_a_bits_param),
    .io_in_a_bits_size(TLBroadcastTracker_3_io_in_a_bits_size),
    .io_in_a_bits_source(TLBroadcastTracker_3_io_in_a_bits_source),
    .io_in_a_bits_address(TLBroadcastTracker_3_io_in_a_bits_address),
    .io_in_a_bits_mask(TLBroadcastTracker_3_io_in_a_bits_mask),
    .io_in_a_bits_data(TLBroadcastTracker_3_io_in_a_bits_data),
    .io_out_a_ready(TLBroadcastTracker_3_io_out_a_ready),
    .io_out_a_valid(TLBroadcastTracker_3_io_out_a_valid),
    .io_out_a_bits_opcode(TLBroadcastTracker_3_io_out_a_bits_opcode),
    .io_out_a_bits_param(TLBroadcastTracker_3_io_out_a_bits_param),
    .io_out_a_bits_size(TLBroadcastTracker_3_io_out_a_bits_size),
    .io_out_a_bits_source(TLBroadcastTracker_3_io_out_a_bits_source),
    .io_out_a_bits_address(TLBroadcastTracker_3_io_out_a_bits_address),
    .io_out_a_bits_mask(TLBroadcastTracker_3_io_out_a_bits_mask),
    .io_out_a_bits_data(TLBroadcastTracker_3_io_out_a_bits_data),
    .io_probe_valid(TLBroadcastTracker_3_io_probe_valid),
    .io_probe_bits_count(TLBroadcastTracker_3_io_probe_bits_count),
    .io_probenack(TLBroadcastTracker_3_io_probenack),
    .io_probedack(TLBroadcastTracker_3_io_probedack),
    .io_probesack(TLBroadcastTracker_3_io_probesack),
    .io_d_last(TLBroadcastTracker_3_io_d_last),
    .io_e_last(TLBroadcastTracker_3_io_e_last),
    .io_source(TLBroadcastTracker_3_io_source),
    .io_line(TLBroadcastTracker_3_io_line),
    .io_idle(TLBroadcastTracker_3_io_idle),
    .io_need_d(TLBroadcastTracker_3_io_need_d)
  );
  assign auto_in_a_ready = (~first_2 | BroadcastFilter_io_request_ready) & _T_416; // @[Broadcast.scala 243:59]
  assign auto_in_b_valid = |REG; // @[Broadcast.scala 219:38]
  assign auto_in_b_bits_param = REG_2; // @[Edges.scala 600:17 602:15]
  assign auto_in_b_bits_address = {REG_1, 6'h0}; // @[Broadcast.scala 225:46]
  assign auto_in_c_ready = _T_110 | _bundleIn_0_c_ready_T; // @[Broadcast.scala 184:32]
  assign auto_in_d_valid = idle ? _T_217 : _sink_ACancel_earlyValid_T_3; // @[Arbiter.scala 125:29]
  assign auto_in_d_bits_opcode = _T_252 | _T_253; // @[Mux.scala 27:73]
  assign auto_in_d_bits_param = muxStateEarly__1 ? out_1_bits_param : 2'h0; // @[Mux.scala 27:73]
  assign auto_in_d_bits_size = _T_246 | _T_247; // @[Mux.scala 27:73]
  assign auto_in_d_bits_source = _T_243 | _T_244; // @[Mux.scala 27:73]
  assign auto_in_d_bits_sink = muxStateEarly__1 ? out_1_bits_sink : 2'h0; // @[Mux.scala 27:73]
  assign auto_in_d_bits_data = muxStateEarly__1 ? auto_out_d_bits_data : 32'h0; // @[Mux.scala 27:73]
  assign auto_out_a_valid = idle_1 ? _T_285 : _sink_ACancel_earlyValid_T_17; // @[Arbiter.scala 125:29]
  assign auto_out_a_bits_opcode = _T_378 | _T_375; // @[Mux.scala 27:73]
  assign auto_out_a_bits_param = _T_369 | _T_366; // @[Mux.scala 27:73]
  assign auto_out_a_bits_size = _T_360 | _T_357; // @[Mux.scala 27:73]
  assign auto_out_a_bits_source = _T_351 | _T_348; // @[Mux.scala 27:73]
  assign auto_out_a_bits_address = _T_342 | _T_339; // @[Mux.scala 27:73]
  assign auto_out_a_bits_mask = _T_333 | _T_330; // @[Mux.scala 27:73]
  assign auto_out_a_bits_data = _T_324 | _T_321; // @[Mux.scala 27:73]
  assign auto_out_d_ready = out_1_ready | _T_14; // @[Broadcast.scala 128:50]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = (~first_2 | BroadcastFilter_io_request_ready) & _T_416; // @[Broadcast.scala 243:59]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_b_ready = auto_in_b_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_b_valid = |REG; // @[Broadcast.scala 219:38]
  assign monitor_io_in_b_bits_param = REG_2; // @[Edges.scala 600:17 602:15]
  assign monitor_io_in_b_bits_address = {REG_1, 6'h0}; // @[Broadcast.scala 225:46]
  assign monitor_io_in_c_ready = _T_110 | _bundleIn_0_c_ready_T; // @[Broadcast.scala 184:32]
  assign monitor_io_in_c_valid = auto_in_c_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_opcode = auto_in_c_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_param = auto_in_c_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_size = auto_in_c_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_source = auto_in_c_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_address = auto_in_c_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_corrupt = auto_in_c_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = idle ? _T_217 : _sink_ACancel_earlyValid_T_3; // @[Arbiter.scala 125:29]
  assign monitor_io_in_d_bits_opcode = _T_252 | _T_253; // @[Mux.scala 27:73]
  assign monitor_io_in_d_bits_param = muxStateEarly__1 ? out_1_bits_param : 2'h0; // @[Mux.scala 27:73]
  assign monitor_io_in_d_bits_size = _T_246 | _T_247; // @[Mux.scala 27:73]
  assign monitor_io_in_d_bits_source = _T_243 | _T_244; // @[Mux.scala 27:73]
  assign monitor_io_in_d_bits_sink = muxStateEarly__1 ? out_1_bits_sink : 2'h0; // @[Mux.scala 27:73]
  assign monitor_io_in_e_valid = auto_in_e_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_e_bits_sink = auto_in_e_bits_sink; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign BroadcastFilter_io_request_valid = auto_in_a_valid & first_2 & _T_416; // @[Broadcast.scala 250:56]
  assign BroadcastFilter_io_request_bits_mshr = _T_446[1:0]; // @[Broadcast.scala 251:38]
  assign BroadcastFilter_io_request_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign BroadcastFilter_io_request_bits_allocOH = auto_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  assign BroadcastFilter_io_request_bits_needT = 3'h7 == auto_in_a_bits_opcode ? acq_needT : _T_462; // @[Mux.scala 81:58]
  assign BroadcastFilter_io_response_ready = ~bundleIn_0_b_valid; // @[Broadcast.scala 259:35]
  assign TLBroadcastTracker_clock = clock;
  assign TLBroadcastTracker_reset = reset;
  assign TLBroadcastTracker_io_in_a_first = counter_2 == 4'h0; // @[Edges.scala 230:25]
  assign TLBroadcastTracker_io_in_a_valid = auto_in_a_valid & _T_413[0] & _bundleIn_0_a_ready_T_1; // @[Broadcast.scala 245:46]
  assign TLBroadcastTracker_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign TLBroadcastTracker_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign TLBroadcastTracker_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign TLBroadcastTracker_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign TLBroadcastTracker_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign TLBroadcastTracker_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign TLBroadcastTracker_io_in_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign TLBroadcastTracker_io_out_a_ready = auto_out_a_ready & allowed_1_1; // @[Arbiter.scala 123:31]
  assign TLBroadcastTracker_io_probe_valid = _T_472 & _T_477[0]; // @[Broadcast.scala 272:58]
  assign TLBroadcastTracker_io_probe_bits_count = ~BroadcastFilter_io_response_bits_allocOH; // @[Broadcast.scala 257:54]
  assign TLBroadcastTracker_io_probenack = _T_135 & _T_110 & _T_115; // @[Broadcast.scala 175:56]
  assign TLBroadcastTracker_io_probedack = _GEN_1[0] & _T_65 & _T_14; // @[Broadcast.scala 143:53]
  assign TLBroadcastTracker_io_probesack = _T_135 & _T_115 & _T_136 & _T_150; // @[Broadcast.scala 176:86]
  assign TLBroadcastTracker_io_d_last = _GEN_1[0] & _T_15 & _T_56 & last; // @[Broadcast.scala 142:67]
  assign TLBroadcastTracker_io_e_last = _T[0] & auto_in_e_valid; // @[Broadcast.scala 113:34]
  assign TLBroadcastTracker_1_clock = clock;
  assign TLBroadcastTracker_1_reset = reset;
  assign TLBroadcastTracker_1_io_in_a_first = counter_2 == 4'h0; // @[Edges.scala 230:25]
  assign TLBroadcastTracker_1_io_in_a_valid = auto_in_a_valid & _T_413[1] & _bundleIn_0_a_ready_T_1; // @[Broadcast.scala 245:46]
  assign TLBroadcastTracker_1_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign TLBroadcastTracker_1_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign TLBroadcastTracker_1_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign TLBroadcastTracker_1_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign TLBroadcastTracker_1_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign TLBroadcastTracker_1_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign TLBroadcastTracker_1_io_in_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign TLBroadcastTracker_1_io_out_a_ready = auto_out_a_ready & allowed_1_2; // @[Arbiter.scala 123:31]
  assign TLBroadcastTracker_1_io_probe_valid = _T_472 & _T_477[1]; // @[Broadcast.scala 272:58]
  assign TLBroadcastTracker_1_io_probe_bits_count = ~BroadcastFilter_io_response_bits_allocOH; // @[Broadcast.scala 257:54]
  assign TLBroadcastTracker_1_io_probenack = _T_135 & _T_110 & _T_117; // @[Broadcast.scala 175:56]
  assign TLBroadcastTracker_1_io_probedack = _GEN_1[1] & _T_65 & _T_14; // @[Broadcast.scala 143:53]
  assign TLBroadcastTracker_1_io_probesack = _T_135 & _T_117 & _T_136 & _T_150; // @[Broadcast.scala 176:86]
  assign TLBroadcastTracker_1_io_d_last = _GEN_1[1] & _T_15 & _T_56 & last; // @[Broadcast.scala 142:67]
  assign TLBroadcastTracker_1_io_e_last = _T[1] & auto_in_e_valid; // @[Broadcast.scala 113:34]
  assign TLBroadcastTracker_2_clock = clock;
  assign TLBroadcastTracker_2_reset = reset;
  assign TLBroadcastTracker_2_io_in_a_first = counter_2 == 4'h0; // @[Edges.scala 230:25]
  assign TLBroadcastTracker_2_io_in_a_valid = auto_in_a_valid & _T_413[2] & _bundleIn_0_a_ready_T_1; // @[Broadcast.scala 245:46]
  assign TLBroadcastTracker_2_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign TLBroadcastTracker_2_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign TLBroadcastTracker_2_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign TLBroadcastTracker_2_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign TLBroadcastTracker_2_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign TLBroadcastTracker_2_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign TLBroadcastTracker_2_io_in_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign TLBroadcastTracker_2_io_out_a_ready = auto_out_a_ready & allowed_1_3; // @[Arbiter.scala 123:31]
  assign TLBroadcastTracker_2_io_probe_valid = _T_472 & _T_477[2]; // @[Broadcast.scala 272:58]
  assign TLBroadcastTracker_2_io_probe_bits_count = ~BroadcastFilter_io_response_bits_allocOH; // @[Broadcast.scala 257:54]
  assign TLBroadcastTracker_2_io_probenack = _T_135 & _T_110 & _T_119; // @[Broadcast.scala 175:56]
  assign TLBroadcastTracker_2_io_probedack = _GEN_1[2] & _T_65 & _T_14; // @[Broadcast.scala 143:53]
  assign TLBroadcastTracker_2_io_probesack = _T_135 & _T_119 & _T_136 & _T_150; // @[Broadcast.scala 176:86]
  assign TLBroadcastTracker_2_io_d_last = _GEN_1[2] & _T_15 & _T_56 & last; // @[Broadcast.scala 142:67]
  assign TLBroadcastTracker_2_io_e_last = _T[2] & auto_in_e_valid; // @[Broadcast.scala 113:34]
  assign TLBroadcastTracker_3_clock = clock;
  assign TLBroadcastTracker_3_reset = reset;
  assign TLBroadcastTracker_3_io_in_a_first = counter_2 == 4'h0; // @[Edges.scala 230:25]
  assign TLBroadcastTracker_3_io_in_a_valid = auto_in_a_valid & _T_413[3] & _bundleIn_0_a_ready_T_1; // @[Broadcast.scala 245:46]
  assign TLBroadcastTracker_3_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign TLBroadcastTracker_3_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign TLBroadcastTracker_3_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign TLBroadcastTracker_3_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign TLBroadcastTracker_3_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign TLBroadcastTracker_3_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign TLBroadcastTracker_3_io_in_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign TLBroadcastTracker_3_io_out_a_ready = auto_out_a_ready & allowed_1_4; // @[Arbiter.scala 123:31]
  assign TLBroadcastTracker_3_io_probe_valid = _T_472 & _T_477[3]; // @[Broadcast.scala 272:58]
  assign TLBroadcastTracker_3_io_probe_bits_count = ~BroadcastFilter_io_response_bits_allocOH; // @[Broadcast.scala 257:54]
  assign TLBroadcastTracker_3_io_probenack = _T_135 & _T_110 & _T_121; // @[Broadcast.scala 175:56]
  assign TLBroadcastTracker_3_io_probedack = _GEN_1[3] & _T_65 & _T_14; // @[Broadcast.scala 143:53]
  assign TLBroadcastTracker_3_io_probesack = _T_135 & _T_121 & _T_136 & _T_150; // @[Broadcast.scala 176:86]
  assign TLBroadcastTracker_3_io_d_last = _GEN_1[3] & _T_15 & _T_56 & last; // @[Broadcast.scala 142:67]
  assign TLBroadcastTracker_3_io_e_last = _T[3] & auto_in_e_valid; // @[Broadcast.scala 113:34]
  always @(posedge clock) begin
    if (reset) begin // @[Arbiter.scala 87:30]
      beatsLeft <= 4'h0; // @[Arbiter.scala 87:30]
    end else if (latch) begin // @[Arbiter.scala 113:23]
      if (earlyWinner__1) begin // @[Arbiter.scala 111:73]
        if (beats1_opdata) begin // @[Edges.scala 220:14]
          beatsLeft <= beats1_decode;
        end else begin
          beatsLeft <= 4'h0;
        end
      end else begin
        beatsLeft <= 4'h0;
      end
    end else begin
      beatsLeft <= _beatsLeft_T_4;
    end
    if (reset) begin // @[Edges.scala 228:27]
      counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_T_15) begin // @[Edges.scala 234:17]
      if (first) begin // @[Edges.scala 235:21]
        if (beats1_opdata) begin // @[Edges.scala 220:14]
          counter <= beats1_decode;
        end else begin
          counter <= 4'h0;
        end
      end else begin
        counter <= counter1;
      end
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state__1 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state__1 <= earlyWinner__1;
    end
    if (first) begin // @[Reg.scala 17:18]
      r <= _T_24; // @[Reg.scala 17:22]
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state__0 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state__0 <= earlyWinner__0;
    end
    if (reset) begin // @[Arbiter.scala 87:30]
      beatsLeft_1 <= 4'h0; // @[Arbiter.scala 87:30]
    end else if (latch_1) begin // @[Arbiter.scala 113:23]
      beatsLeft_1 <= initBeats_1;
    end else begin
      beatsLeft_1 <= _beatsLeft_T_10;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_1_0 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle_1) begin // @[Arbiter.scala 117:30]
      state_1_0 <= earlyWinner_1_0;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_1_1 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle_1) begin // @[Arbiter.scala 117:30]
      state_1_1 <= earlyWinner_1_1;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_1_2 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle_1) begin // @[Arbiter.scala 117:30]
      state_1_2 <= earlyWinner_1_2;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_1_3 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle_1) begin // @[Arbiter.scala 117:30]
      state_1_3 <= earlyWinner_1_3;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_1_4 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle_1) begin // @[Arbiter.scala 117:30]
      state_1_4 <= earlyWinner_1_4;
    end
    if (reset) begin // @[Broadcast.scala 215:31]
      REG <= 1'h0; // @[Broadcast.scala 215:31]
    end else begin
      REG <= _GEN_7[0];
    end
    if (_T_472) begin // @[Broadcast.scala 260:40]
      REG_1 <= BroadcastFilter_io_response_bits_address[30:6]; // @[Broadcast.scala 262:21]
    end
    if (_T_472) begin // @[Broadcast.scala 260:40]
      if (BroadcastFilter_io_response_bits_needT) begin // @[Broadcast.scala 263:27]
        REG_2 <= 2'h2;
      end else begin
        REG_2 <= 2'h1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      counter_2 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_T_390) begin // @[Edges.scala 234:17]
      if (first_2) begin // @[Edges.scala 235:21]
        if (beats1_opdata_2) begin // @[Edges.scala 220:14]
          counter_2 <= beats1_decode_2;
        end else begin
          counter_2 <= 4'h0;
        end
      end else begin
        counter_2 <= counter1_2;
      end
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~auto_out_d_valid | _T_35 | auto_out_d_bits_opcode == 3'h0) & ~reset) begin
          $fatal; // @[Broadcast.scala 125:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~auto_out_d_valid | _T_35 | auto_out_d_bits_opcode == 3'h0)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Broadcast.scala:125 assert (!out.d.valid || !d_drop || out.d.bits.opcode === TLMessages.AccessAck)\n"
            ); // @[Broadcast.scala 125:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~out_1_earlyValid | (|_GEN_1 | out_1_bits_opcode == 3'h6)) & _T_32) begin
          $fatal; // @[Broadcast.scala 137:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_32 & ~(~out_1_earlyValid | (|_GEN_1 | out_1_bits_opcode == 3'h6))) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Broadcast.scala:137 assert (!d_normal.valid || (d_trackerOH.orR() || d_normal.bits.opcode === TLMessages.ReleaseAck))\n"
            ); // @[Broadcast.scala 137:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~earlyWinner__0 | ~earlyWinner__1) & _T_32) begin
          $fatal; // @[Arbiter.scala 105:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_32 & ~(~earlyWinner__0 | ~earlyWinner__1)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:105 assert((prefixOR zip earlyWinner) map { case (p,w) => !p || !w } reduce {_ && _})\n"
            ); // @[Arbiter.scala 105:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(out_earlyValid | out_1_earlyValid) | _prefixOR_T) & _T_32) begin
          $fatal; // @[Arbiter.scala 107:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_32 & ~(~(out_earlyValid | out_1_earlyValid) | _prefixOR_T)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:107 assert (!earlyValids.reduce(_||_) || earlyWinner.reduce(_||_))\n"
            ); // @[Arbiter.scala 107:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_218 | _T_217) & _T_32) begin
          $fatal; // @[Arbiter.scala 108:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_32 & ~(_T_218 | _T_217)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:108 assert (!validQuals .reduce(_||_) || validQuals .reduce(_||_))\n"
            ); // @[Arbiter.scala 108:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~((~earlyWinner_1_0 | ~earlyWinner_1_1) & (~prefixOR_2 | ~earlyWinner_1_2) & (~prefixOR_3 | ~earlyWinner_1_3
          ) & (~prefixOR_4 | ~earlyWinner_1_4)) & _T_32) begin
          $fatal; // @[Arbiter.scala 105:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_32 & ~((~earlyWinner_1_0 | ~earlyWinner_1_1) & (~prefixOR_2 | ~earlyWinner_1_2) & (~prefixOR_3 | ~
          earlyWinner_1_3) & (~prefixOR_4 | ~earlyWinner_1_4))) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:105 assert((prefixOR zip earlyWinner) map { case (p,w) => !p || !w } reduce {_ && _})\n"
            ); // @[Arbiter.scala 105:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(out_3_earlyValid | out_4_earlyValid | out_5_earlyValid | out_6_earlyValid | out_7_earlyValid) |
          _prefixOR_T_1) & _T_32) begin
          $fatal; // @[Arbiter.scala 107:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_32 & ~(~(out_3_earlyValid | out_4_earlyValid | out_5_earlyValid | out_6_earlyValid | out_7_earlyValid) |
          _prefixOR_T_1)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:107 assert (!earlyValids.reduce(_||_) || earlyWinner.reduce(_||_))\n"
            ); // @[Arbiter.scala 107:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_286 | _T_285) & _T_32) begin
          $fatal; // @[Arbiter.scala 108:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_32 & ~(_T_286 | _T_285)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:108 assert (!validQuals .reduce(_||_) || validQuals .reduce(_||_))\n"
            ); // @[Arbiter.scala 108:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  beatsLeft = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  counter = _RAND_1[3:0];
  _RAND_2 = {1{`RANDOM}};
  state__1 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  r = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  state__0 = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  beatsLeft_1 = _RAND_5[3:0];
  _RAND_6 = {1{`RANDOM}};
  state_1_0 = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  state_1_1 = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  state_1_2 = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  state_1_3 = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  state_1_4 = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  REG = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  REG_1 = _RAND_12[24:0];
  _RAND_13 = {1{`RANDOM}};
  REG_2 = _RAND_13[1:0];
  _RAND_14 = {1{`RANDOM}};
  counter_2 = _RAND_14[3:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLJbar(
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [30:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_b_ready,
  output        auto_in_b_valid,
  output [1:0]  auto_in_b_bits_param,
  output [30:0] auto_in_b_bits_address,
  output        auto_in_c_ready,
  input         auto_in_c_valid,
  input  [2:0]  auto_in_c_bits_opcode,
  input  [2:0]  auto_in_c_bits_param,
  input  [2:0]  auto_in_c_bits_size,
  input  [1:0]  auto_in_c_bits_source,
  input  [30:0] auto_in_c_bits_address,
  input  [31:0] auto_in_c_bits_data,
  input         auto_in_c_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [1:0]  auto_in_d_bits_param,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output [1:0]  auto_in_d_bits_sink,
  output [31:0] auto_in_d_bits_data,
  input         auto_in_e_valid,
  input  [1:0]  auto_in_e_bits_sink,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [2:0]  auto_out_a_bits_size,
  output [1:0]  auto_out_a_bits_source,
  output [30:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_b_ready,
  input         auto_out_b_valid,
  input  [1:0]  auto_out_b_bits_param,
  input  [30:0] auto_out_b_bits_address,
  input         auto_out_c_ready,
  output        auto_out_c_valid,
  output [2:0]  auto_out_c_bits_opcode,
  output [2:0]  auto_out_c_bits_param,
  output [2:0]  auto_out_c_bits_size,
  output [1:0]  auto_out_c_bits_source,
  output [30:0] auto_out_c_bits_address,
  output [31:0] auto_out_c_bits_data,
  output        auto_out_c_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_param,
  input  [2:0]  auto_out_d_bits_size,
  input  [1:0]  auto_out_d_bits_source,
  input  [1:0]  auto_out_d_bits_sink,
  input  [31:0] auto_out_d_bits_data,
  output        auto_out_e_valid,
  output [1:0]  auto_out_e_bits_sink
);
  assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_b_valid = auto_out_b_valid; // @[ReadyValidCancel.scala 21:38]
  assign auto_in_b_bits_param = auto_out_b_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_b_bits_address = auto_out_b_bits_address; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_c_ready = auto_out_c_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_valid = auto_out_d_valid; // @[ReadyValidCancel.scala 21:38]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Xbar.scala 228:69]
  assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[Xbar.scala 323:53]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = auto_in_a_valid; // @[ReadyValidCancel.scala 21:38]
  assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
  assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_b_ready = auto_in_b_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_valid = auto_in_c_valid; // @[ReadyValidCancel.scala 21:38]
  assign auto_out_c_bits_opcode = auto_in_c_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_bits_param = auto_in_c_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_bits_size = auto_in_c_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_bits_source = auto_in_c_bits_source; // @[Xbar.scala 259:55]
  assign auto_out_c_bits_address = auto_in_c_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_bits_data = auto_in_c_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_bits_corrupt = auto_in_c_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_e_valid = auto_in_e_valid; // @[ReadyValidCancel.scala 21:38]
  assign auto_out_e_bits_sink = auto_in_e_bits_sink; // @[Xbar.scala 228:69]
endmodule
module TLMonitor_42(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [2:0]  io_in_a_bits_size,
  input  [3:0]  io_in_a_bits_source,
  input  [30:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [2:0]  io_in_d_bits_size,
  input  [3:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [63:0] _RAND_11;
  reg [63:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [63:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire [12:0] _is_aligned_mask_T_1 = 13'h3f << io_in_a_bits_size; // @[package.scala 234:77]
  wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1[5:0]; // @[package.scala 234:46]
  wire [30:0] _GEN_71 = {{25'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [30:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 31'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 3'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [30:0] _T_33 = io_in_a_bits_address ^ 31'h40000000; // @[Parameters.scala 137:31]
  wire [31:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_36 = $signed(_T_34) & -32'sh20000000; // @[Parameters.scala 137:52]
  wire  _T_37 = $signed(_T_36) == 32'sh0; // @[Parameters.scala 137:67]
  wire  _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_74 = _T_73 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_164 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 92:42]
  wire  _T_172 = _T_164 & _T_37; // @[Parameters.scala 670:56]
  wire  _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_270 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_271 = io_in_a_bits_mask & _T_270; // @[Monitor.scala 127:31]
  wire  _T_272 = _T_271 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_276 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_306 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_314 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_344 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_352 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_382 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_394 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _T_398 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_402 = io_in_d_bits_size >= 3'h2; // @[Monitor.scala 312:27]
  wire  _T_418 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_446 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [3:0] a_first_beats1_decode = is_aligned_mask[5:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] a_first_counter; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1 = a_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [2:0] size; // @[Monitor.scala 386:22]
  reg [3:0] source; // @[Monitor.scala 387:22]
  reg [30:0] address; // @[Monitor.scala 388:22]
  wire  _T_540 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_541 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_545 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_549 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_553 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_557 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [12:0] _d_first_beats1_decode_T_1 = 13'h3f << io_in_d_bits_size; // @[package.scala 234:77]
  wire [5:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[5:0]; // @[package.scala 234:46]
  wire [3:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[5:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [3:0] d_first_counter; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1 = d_first_counter - 4'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 4'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [2:0] size_1; // @[Monitor.scala 537:22]
  reg [3:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_564 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_565 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_573 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_577 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [15:0] inflight; // @[Monitor.scala 611:27]
  reg [63:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [63:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [3:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] a_first_counter1_1 = a_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  reg [3:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_1 = d_first_counter_1 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 4'h0; // @[Edges.scala 230:25]
  wire [5:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [6:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [63:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [63:0] _GEN_73 = {{48'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
  wire [63:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
  wire [63:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[63:1]}; // @[Monitor.scala 634:152]
  wire [63:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [63:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
  wire [63:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[63:1]}; // @[Monitor.scala 638:144]
  wire  _T_591 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [15:0] _a_set_wo_ready_T = 16'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [15:0] a_set_wo_ready = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 16'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_594 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [3:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 4'h1; // @[Monitor.scala 655:59]
  wire [5:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [6:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [130:0] _GEN_1 = {{127'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [130:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 655:28]
  wire [130:0] _GEN_2 = {{127'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [130:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [15:0] _T_596 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_598 = ~_T_596[0]; // @[Monitor.scala 658:17]
  wire [15:0] a_set = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 16'h0; // @[Monitor.scala 652:72 653:28]
  wire [130:0] _GEN_19 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 131'h0; // @[Monitor.scala 652:72 656:28]
  wire [130:0] _GEN_20 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 131'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_602 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_604 = ~_T_398; // @[Monitor.scala 671:74]
  wire  _T_605 = io_in_d_valid & d_first_1 & ~_T_398; // @[Monitor.scala 671:71]
  wire [15:0] _d_clr_wo_ready_T = 16'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [15:0] d_clr_wo_ready = io_in_d_valid & d_first_1 & ~_T_398 ? _d_clr_wo_ready_T : 16'h0; // @[Monitor.scala 671:90 672:22]
  wire [142:0] _GEN_3 = {{127'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [142:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [15:0] d_clr = _d_first_T & d_first_1 & _T_604 ? _d_clr_wo_ready_T : 16'h0; // @[Monitor.scala 675:91 676:21]
  wire [142:0] _GEN_23 = _d_first_T & d_first_1 & _T_604 ? _d_opcodes_clr_T_5 : 143'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_591 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [15:0] _T_615 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_617 = _T_615[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_622 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_623 = io_in_d_bits_opcode == _GEN_32 | _T_622; // @[Monitor.scala 685:77]
  wire  _T_627 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_634 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_635 = io_in_d_bits_opcode == _GEN_48 | _T_634; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_639 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_649 = _T_602 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_604; // @[Monitor.scala 694:116]
  wire  _T_651 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire  _T_658 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire [15:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [15:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [15:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [63:0] a_opcodes_set = _GEN_19[63:0];
  wire [63:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [63:0] d_opcodes_clr = _GEN_23[63:0];
  wire [63:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [63:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [63:0] a_sizes_set = _GEN_20[63:0];
  wire [63:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [63:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_667 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [15:0] inflight_1; // @[Monitor.scala 723:35]
  reg [63:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [3:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [3:0] d_first_counter1_2 = d_first_counter_2 - 4'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 4'h0; // @[Edges.scala 230:25]
  wire [63:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [63:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
  wire [63:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[63:1]}; // @[Monitor.scala 747:146]
  wire  _T_693 = io_in_d_valid & d_first_2 & _T_398; // @[Monitor.scala 779:71]
  wire [15:0] d_clr_1 = _d_first_T & d_first_2 & _T_398 ? _d_clr_wo_ready_T : 16'h0; // @[Monitor.scala 783:90 784:21]
  wire [142:0] _GEN_68 = _d_first_T & d_first_2 & _T_398 ? _d_opcodes_clr_T_5 : 143'h0; // @[Monitor.scala 783:90 785:21]
  wire [15:0] _T_701 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_711 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [15:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [15:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [63:0] d_opcodes_clr_1 = _GEN_68[63:0];
  wire [63:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [63:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_736 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 4'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 4'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 16'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 64'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 64'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 4'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 4'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 16'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 64'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 4'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 4'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_172 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_172) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_172 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_172) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_272 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_272) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_306 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_T_306) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_314 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_314 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_314 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_314 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_344 & (io_in_a_valid & _T_314 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_314 & ~reset & ~_T_344) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_314 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_314 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_352 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_352 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_352 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_352 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_382 & (io_in_a_valid & _T_352 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_352 & ~reset & ~_T_382) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_352 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_352 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_394 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_394) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_402 & (io_in_d_valid & _T_398 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_398 & _T_2 & ~_T_402) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_418 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_418 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_402 & (io_in_d_valid & _T_418 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_418 & _T_2 & ~_T_402) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_446 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_446 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_402 & (io_in_d_valid & _T_446 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_446 & _T_2 & ~_T_402) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_541 & (_T_540 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_540 & ~reset & ~_T_541) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_545 & (_T_540 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_540 & ~reset & ~_T_545) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_549 & (_T_540 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_540 & ~reset & ~_T_549) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_553 & (_T_540 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_540 & ~reset & ~_T_553) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_557 & (_T_540 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_540 & ~reset & ~_T_557) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_565 & (_T_564 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_564 & _T_2 & ~_T_565) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_573 & (_T_564 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_564 & _T_2 & ~_T_573) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_577 & (_T_564 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_564 & _T_2 & ~_T_577) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_598 & (_T_594 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_594 & ~reset & ~_T_598) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_617 & (_T_605 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_605 & _T_2 & ~_T_617) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_623 & (_T_605 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_605 & same_cycle_resp & _T_2 & ~_T_623) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_627 & (_T_605 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_605 & same_cycle_resp & _T_2 & ~_T_627) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_635 & (_T_605 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_605 & ~same_cycle_resp & _T_2 & ~_T_635) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_639 & (_T_605 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_605 & ~same_cycle_resp & _T_2 & ~_T_639) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_651 & (_T_649 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_649 & _T_2 & ~_T_651) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_658 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_658) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_667 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_667) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_701[0] & (_T_693 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_693 & _T_2 & ~_T_701[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_711 & (_T_693 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_693 & _T_2 & ~_T_711) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_736 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_736) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at BankedL2Params.scala:65:103)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[3:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[30:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[2:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[3:0];
  _RAND_10 = {1{`RANDOM}};
  inflight = _RAND_10[15:0];
  _RAND_11 = {2{`RANDOM}};
  inflight_opcodes = _RAND_11[63:0];
  _RAND_12 = {2{`RANDOM}};
  inflight_sizes = _RAND_12[63:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[3:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[3:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  inflight_1 = _RAND_16[15:0];
  _RAND_17 = {2{`RANDOM}};
  inflight_sizes_1 = _RAND_17[63:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[3:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module BankBinder(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [3:0]  auto_in_a_bits_source,
  input  [30:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [2:0]  auto_in_d_bits_size,
  output [3:0]  auto_in_d_bits_source,
  output [31:0] auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [2:0]  auto_out_a_bits_size,
  output [3:0]  auto_out_a_bits_source,
  output [30:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [2:0]  auto_out_d_bits_size,
  input  [3:0]  auto_out_d_bits_source,
  input  [31:0] auto_out_d_bits_data
);
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [30:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  TLMonitor_42 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
endmodule
module TLWidthWidget_7(
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [3:0]  auto_in_a_bits_source,
  input  [30:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [2:0]  auto_in_d_bits_size,
  output [3:0]  auto_in_d_bits_source,
  output [31:0] auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [2:0]  auto_out_a_bits_size,
  output [3:0]  auto_out_a_bits_source,
  output [30:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [2:0]  auto_out_d_bits_size,
  input  [3:0]  auto_out_d_bits_source,
  input  [31:0] auto_out_d_bits_data
);
  assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module TLInterconnectCoupler_27(
  output        auto_widget_in_a_ready,
  input         auto_widget_in_a_valid,
  input  [2:0]  auto_widget_in_a_bits_opcode,
  input  [2:0]  auto_widget_in_a_bits_param,
  input  [2:0]  auto_widget_in_a_bits_size,
  input  [3:0]  auto_widget_in_a_bits_source,
  input  [30:0] auto_widget_in_a_bits_address,
  input  [3:0]  auto_widget_in_a_bits_mask,
  input  [31:0] auto_widget_in_a_bits_data,
  input         auto_widget_in_d_ready,
  output        auto_widget_in_d_valid,
  output [2:0]  auto_widget_in_d_bits_opcode,
  output [2:0]  auto_widget_in_d_bits_size,
  output [3:0]  auto_widget_in_d_bits_source,
  output [31:0] auto_widget_in_d_bits_data,
  input         auto_bus_xing_out_a_ready,
  output        auto_bus_xing_out_a_valid,
  output [2:0]  auto_bus_xing_out_a_bits_opcode,
  output [2:0]  auto_bus_xing_out_a_bits_param,
  output [2:0]  auto_bus_xing_out_a_bits_size,
  output [3:0]  auto_bus_xing_out_a_bits_source,
  output [30:0] auto_bus_xing_out_a_bits_address,
  output [3:0]  auto_bus_xing_out_a_bits_mask,
  output [31:0] auto_bus_xing_out_a_bits_data,
  output        auto_bus_xing_out_d_ready,
  input         auto_bus_xing_out_d_valid,
  input  [2:0]  auto_bus_xing_out_d_bits_opcode,
  input  [2:0]  auto_bus_xing_out_d_bits_size,
  input  [3:0]  auto_bus_xing_out_d_bits_source,
  input  [31:0] auto_bus_xing_out_d_bits_data
);
  wire  widget_auto_in_a_ready; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_a_valid; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_a_bits_opcode; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_a_bits_param; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_a_bits_size; // @[WidthWidget.scala 219:28]
  wire [3:0] widget_auto_in_a_bits_source; // @[WidthWidget.scala 219:28]
  wire [30:0] widget_auto_in_a_bits_address; // @[WidthWidget.scala 219:28]
  wire [3:0] widget_auto_in_a_bits_mask; // @[WidthWidget.scala 219:28]
  wire [31:0] widget_auto_in_a_bits_data; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_d_ready; // @[WidthWidget.scala 219:28]
  wire  widget_auto_in_d_valid; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_d_bits_opcode; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_in_d_bits_size; // @[WidthWidget.scala 219:28]
  wire [3:0] widget_auto_in_d_bits_source; // @[WidthWidget.scala 219:28]
  wire [31:0] widget_auto_in_d_bits_data; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_a_ready; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_a_valid; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_a_bits_opcode; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_a_bits_param; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_a_bits_size; // @[WidthWidget.scala 219:28]
  wire [3:0] widget_auto_out_a_bits_source; // @[WidthWidget.scala 219:28]
  wire [30:0] widget_auto_out_a_bits_address; // @[WidthWidget.scala 219:28]
  wire [3:0] widget_auto_out_a_bits_mask; // @[WidthWidget.scala 219:28]
  wire [31:0] widget_auto_out_a_bits_data; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_d_ready; // @[WidthWidget.scala 219:28]
  wire  widget_auto_out_d_valid; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_d_bits_opcode; // @[WidthWidget.scala 219:28]
  wire [2:0] widget_auto_out_d_bits_size; // @[WidthWidget.scala 219:28]
  wire [3:0] widget_auto_out_d_bits_source; // @[WidthWidget.scala 219:28]
  wire [31:0] widget_auto_out_d_bits_data; // @[WidthWidget.scala 219:28]
  TLWidthWidget_7 widget ( // @[WidthWidget.scala 219:28]
    .auto_in_a_ready(widget_auto_in_a_ready),
    .auto_in_a_valid(widget_auto_in_a_valid),
    .auto_in_a_bits_opcode(widget_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(widget_auto_in_a_bits_param),
    .auto_in_a_bits_size(widget_auto_in_a_bits_size),
    .auto_in_a_bits_source(widget_auto_in_a_bits_source),
    .auto_in_a_bits_address(widget_auto_in_a_bits_address),
    .auto_in_a_bits_mask(widget_auto_in_a_bits_mask),
    .auto_in_a_bits_data(widget_auto_in_a_bits_data),
    .auto_in_d_ready(widget_auto_in_d_ready),
    .auto_in_d_valid(widget_auto_in_d_valid),
    .auto_in_d_bits_opcode(widget_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(widget_auto_in_d_bits_size),
    .auto_in_d_bits_source(widget_auto_in_d_bits_source),
    .auto_in_d_bits_data(widget_auto_in_d_bits_data),
    .auto_out_a_ready(widget_auto_out_a_ready),
    .auto_out_a_valid(widget_auto_out_a_valid),
    .auto_out_a_bits_opcode(widget_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(widget_auto_out_a_bits_param),
    .auto_out_a_bits_size(widget_auto_out_a_bits_size),
    .auto_out_a_bits_source(widget_auto_out_a_bits_source),
    .auto_out_a_bits_address(widget_auto_out_a_bits_address),
    .auto_out_a_bits_mask(widget_auto_out_a_bits_mask),
    .auto_out_a_bits_data(widget_auto_out_a_bits_data),
    .auto_out_d_ready(widget_auto_out_d_ready),
    .auto_out_d_valid(widget_auto_out_d_valid),
    .auto_out_d_bits_opcode(widget_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(widget_auto_out_d_bits_size),
    .auto_out_d_bits_source(widget_auto_out_d_bits_source),
    .auto_out_d_bits_data(widget_auto_out_d_bits_data)
  );
  assign auto_widget_in_a_ready = widget_auto_in_a_ready; // @[LazyModule.scala 309:16]
  assign auto_widget_in_d_valid = widget_auto_in_d_valid; // @[LazyModule.scala 309:16]
  assign auto_widget_in_d_bits_opcode = widget_auto_in_d_bits_opcode; // @[LazyModule.scala 309:16]
  assign auto_widget_in_d_bits_size = widget_auto_in_d_bits_size; // @[LazyModule.scala 309:16]
  assign auto_widget_in_d_bits_source = widget_auto_in_d_bits_source; // @[LazyModule.scala 309:16]
  assign auto_widget_in_d_bits_data = widget_auto_in_d_bits_data; // @[LazyModule.scala 309:16]
  assign auto_bus_xing_out_a_valid = widget_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_bus_xing_out_a_bits_opcode = widget_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_bus_xing_out_a_bits_param = widget_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_bus_xing_out_a_bits_size = widget_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_bus_xing_out_a_bits_source = widget_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_bus_xing_out_a_bits_address = widget_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_bus_xing_out_a_bits_mask = widget_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_bus_xing_out_a_bits_data = widget_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_bus_xing_out_d_ready = widget_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign widget_auto_in_a_valid = auto_widget_in_a_valid; // @[LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_opcode = auto_widget_in_a_bits_opcode; // @[LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_param = auto_widget_in_a_bits_param; // @[LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_size = auto_widget_in_a_bits_size; // @[LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_source = auto_widget_in_a_bits_source; // @[LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_address = auto_widget_in_a_bits_address; // @[LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_mask = auto_widget_in_a_bits_mask; // @[LazyModule.scala 309:16]
  assign widget_auto_in_a_bits_data = auto_widget_in_a_bits_data; // @[LazyModule.scala 309:16]
  assign widget_auto_in_d_ready = auto_widget_in_d_ready; // @[LazyModule.scala 309:16]
  assign widget_auto_out_a_ready = auto_bus_xing_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign widget_auto_out_d_valid = auto_bus_xing_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign widget_auto_out_d_bits_opcode = auto_bus_xing_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign widget_auto_out_d_bits_size = auto_bus_xing_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign widget_auto_out_d_bits_source = auto_bus_xing_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign widget_auto_out_d_bits_data = auto_bus_xing_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
endmodule
module CoherenceManagerWrapper(
  input         auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_ready,
  output        auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_valid,
  output [2:0]  auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_opcode,
  output [2:0]  auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_param,
  output [2:0]  auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_size,
  output [3:0]  auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_source,
  output [30:0] auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_address,
  output [3:0]  auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_mask,
  output [31:0] auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_data,
  output        auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_ready,
  input         auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_valid,
  input  [2:0]  auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_bits_opcode,
  input  [2:0]  auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_bits_size,
  input  [3:0]  auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_bits_source,
  input  [31:0] auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_bits_data,
  output        auto_coherent_jbar_in_a_ready,
  input         auto_coherent_jbar_in_a_valid,
  input  [2:0]  auto_coherent_jbar_in_a_bits_opcode,
  input  [2:0]  auto_coherent_jbar_in_a_bits_param,
  input  [2:0]  auto_coherent_jbar_in_a_bits_size,
  input  [1:0]  auto_coherent_jbar_in_a_bits_source,
  input  [30:0] auto_coherent_jbar_in_a_bits_address,
  input  [3:0]  auto_coherent_jbar_in_a_bits_mask,
  input  [31:0] auto_coherent_jbar_in_a_bits_data,
  input         auto_coherent_jbar_in_a_bits_corrupt,
  input         auto_coherent_jbar_in_b_ready,
  output        auto_coherent_jbar_in_b_valid,
  output [1:0]  auto_coherent_jbar_in_b_bits_param,
  output [30:0] auto_coherent_jbar_in_b_bits_address,
  output        auto_coherent_jbar_in_c_ready,
  input         auto_coherent_jbar_in_c_valid,
  input  [2:0]  auto_coherent_jbar_in_c_bits_opcode,
  input  [2:0]  auto_coherent_jbar_in_c_bits_param,
  input  [2:0]  auto_coherent_jbar_in_c_bits_size,
  input  [1:0]  auto_coherent_jbar_in_c_bits_source,
  input  [30:0] auto_coherent_jbar_in_c_bits_address,
  input  [31:0] auto_coherent_jbar_in_c_bits_data,
  input         auto_coherent_jbar_in_c_bits_corrupt,
  input         auto_coherent_jbar_in_d_ready,
  output        auto_coherent_jbar_in_d_valid,
  output [2:0]  auto_coherent_jbar_in_d_bits_opcode,
  output [1:0]  auto_coherent_jbar_in_d_bits_param,
  output [2:0]  auto_coherent_jbar_in_d_bits_size,
  output [1:0]  auto_coherent_jbar_in_d_bits_source,
  output [1:0]  auto_coherent_jbar_in_d_bits_sink,
  output [31:0] auto_coherent_jbar_in_d_bits_data,
  input         auto_coherent_jbar_in_e_valid,
  input  [1:0]  auto_coherent_jbar_in_e_bits_sink,
  input         auto_subsystem_l2_clock_groups_in_member_subsystem_l2_1_clock,
  input         auto_subsystem_l2_clock_groups_in_member_subsystem_l2_1_reset,
  input         auto_subsystem_l2_clock_groups_in_member_subsystem_l2_0_clock,
  input         auto_subsystem_l2_clock_groups_in_member_subsystem_l2_0_reset,
  output        auto_subsystem_l2_clock_groups_out_member_subsystem_mbus_0_clock,
  output        auto_subsystem_l2_clock_groups_out_member_subsystem_mbus_0_reset
);
  wire  subsystem_l2_clock_groups_auto_in_member_subsystem_l2_1_clock; // @[BusWrapper.scala 40:48]
  wire  subsystem_l2_clock_groups_auto_in_member_subsystem_l2_1_reset; // @[BusWrapper.scala 40:48]
  wire  subsystem_l2_clock_groups_auto_in_member_subsystem_l2_0_clock; // @[BusWrapper.scala 40:48]
  wire  subsystem_l2_clock_groups_auto_in_member_subsystem_l2_0_reset; // @[BusWrapper.scala 40:48]
  wire  subsystem_l2_clock_groups_auto_out_1_member_subsystem_mbus_0_clock; // @[BusWrapper.scala 40:48]
  wire  subsystem_l2_clock_groups_auto_out_1_member_subsystem_mbus_0_reset; // @[BusWrapper.scala 40:48]
  wire  subsystem_l2_clock_groups_auto_out_0_member_subsystem_l2_0_clock; // @[BusWrapper.scala 40:48]
  wire  subsystem_l2_clock_groups_auto_out_0_member_subsystem_l2_0_reset; // @[BusWrapper.scala 40:48]
  wire  clockGroup_auto_in_member_subsystem_l2_0_clock; // @[BusWrapper.scala 41:38]
  wire  clockGroup_auto_in_member_subsystem_l2_0_reset; // @[BusWrapper.scala 41:38]
  wire  clockGroup_auto_out_clock; // @[BusWrapper.scala 41:38]
  wire  clockGroup_auto_out_reset; // @[BusWrapper.scala 41:38]
  wire  fixedClockNode_auto_in_clock; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_in_reset; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_clock; // @[ClockGroup.scala 106:107]
  wire  fixedClockNode_auto_out_reset; // @[ClockGroup.scala 106:107]
  wire  broadcast_1_clock; // @[BankedL2Params.scala 81:24]
  wire  broadcast_1_reset; // @[BankedL2Params.scala 81:24]
  wire  broadcast_1_auto_in_a_ready; // @[BankedL2Params.scala 81:24]
  wire  broadcast_1_auto_in_a_valid; // @[BankedL2Params.scala 81:24]
  wire [2:0] broadcast_1_auto_in_a_bits_opcode; // @[BankedL2Params.scala 81:24]
  wire [2:0] broadcast_1_auto_in_a_bits_param; // @[BankedL2Params.scala 81:24]
  wire [2:0] broadcast_1_auto_in_a_bits_size; // @[BankedL2Params.scala 81:24]
  wire [1:0] broadcast_1_auto_in_a_bits_source; // @[BankedL2Params.scala 81:24]
  wire [30:0] broadcast_1_auto_in_a_bits_address; // @[BankedL2Params.scala 81:24]
  wire [3:0] broadcast_1_auto_in_a_bits_mask; // @[BankedL2Params.scala 81:24]
  wire [31:0] broadcast_1_auto_in_a_bits_data; // @[BankedL2Params.scala 81:24]
  wire  broadcast_1_auto_in_a_bits_corrupt; // @[BankedL2Params.scala 81:24]
  wire  broadcast_1_auto_in_b_ready; // @[BankedL2Params.scala 81:24]
  wire  broadcast_1_auto_in_b_valid; // @[BankedL2Params.scala 81:24]
  wire [1:0] broadcast_1_auto_in_b_bits_param; // @[BankedL2Params.scala 81:24]
  wire [30:0] broadcast_1_auto_in_b_bits_address; // @[BankedL2Params.scala 81:24]
  wire  broadcast_1_auto_in_c_ready; // @[BankedL2Params.scala 81:24]
  wire  broadcast_1_auto_in_c_valid; // @[BankedL2Params.scala 81:24]
  wire [2:0] broadcast_1_auto_in_c_bits_opcode; // @[BankedL2Params.scala 81:24]
  wire [2:0] broadcast_1_auto_in_c_bits_param; // @[BankedL2Params.scala 81:24]
  wire [2:0] broadcast_1_auto_in_c_bits_size; // @[BankedL2Params.scala 81:24]
  wire [1:0] broadcast_1_auto_in_c_bits_source; // @[BankedL2Params.scala 81:24]
  wire [30:0] broadcast_1_auto_in_c_bits_address; // @[BankedL2Params.scala 81:24]
  wire [31:0] broadcast_1_auto_in_c_bits_data; // @[BankedL2Params.scala 81:24]
  wire  broadcast_1_auto_in_c_bits_corrupt; // @[BankedL2Params.scala 81:24]
  wire  broadcast_1_auto_in_d_ready; // @[BankedL2Params.scala 81:24]
  wire  broadcast_1_auto_in_d_valid; // @[BankedL2Params.scala 81:24]
  wire [2:0] broadcast_1_auto_in_d_bits_opcode; // @[BankedL2Params.scala 81:24]
  wire [1:0] broadcast_1_auto_in_d_bits_param; // @[BankedL2Params.scala 81:24]
  wire [2:0] broadcast_1_auto_in_d_bits_size; // @[BankedL2Params.scala 81:24]
  wire [1:0] broadcast_1_auto_in_d_bits_source; // @[BankedL2Params.scala 81:24]
  wire [1:0] broadcast_1_auto_in_d_bits_sink; // @[BankedL2Params.scala 81:24]
  wire [31:0] broadcast_1_auto_in_d_bits_data; // @[BankedL2Params.scala 81:24]
  wire  broadcast_1_auto_in_e_valid; // @[BankedL2Params.scala 81:24]
  wire [1:0] broadcast_1_auto_in_e_bits_sink; // @[BankedL2Params.scala 81:24]
  wire  broadcast_1_auto_out_a_ready; // @[BankedL2Params.scala 81:24]
  wire  broadcast_1_auto_out_a_valid; // @[BankedL2Params.scala 81:24]
  wire [2:0] broadcast_1_auto_out_a_bits_opcode; // @[BankedL2Params.scala 81:24]
  wire [2:0] broadcast_1_auto_out_a_bits_param; // @[BankedL2Params.scala 81:24]
  wire [2:0] broadcast_1_auto_out_a_bits_size; // @[BankedL2Params.scala 81:24]
  wire [3:0] broadcast_1_auto_out_a_bits_source; // @[BankedL2Params.scala 81:24]
  wire [30:0] broadcast_1_auto_out_a_bits_address; // @[BankedL2Params.scala 81:24]
  wire [3:0] broadcast_1_auto_out_a_bits_mask; // @[BankedL2Params.scala 81:24]
  wire [31:0] broadcast_1_auto_out_a_bits_data; // @[BankedL2Params.scala 81:24]
  wire  broadcast_1_auto_out_d_ready; // @[BankedL2Params.scala 81:24]
  wire  broadcast_1_auto_out_d_valid; // @[BankedL2Params.scala 81:24]
  wire [2:0] broadcast_1_auto_out_d_bits_opcode; // @[BankedL2Params.scala 81:24]
  wire [2:0] broadcast_1_auto_out_d_bits_size; // @[BankedL2Params.scala 81:24]
  wire [3:0] broadcast_1_auto_out_d_bits_source; // @[BankedL2Params.scala 81:24]
  wire [31:0] broadcast_1_auto_out_d_bits_data; // @[BankedL2Params.scala 81:24]
  wire  coherent_jbar_auto_in_a_ready; // @[BankedL2Params.scala 58:41]
  wire  coherent_jbar_auto_in_a_valid; // @[BankedL2Params.scala 58:41]
  wire [2:0] coherent_jbar_auto_in_a_bits_opcode; // @[BankedL2Params.scala 58:41]
  wire [2:0] coherent_jbar_auto_in_a_bits_param; // @[BankedL2Params.scala 58:41]
  wire [2:0] coherent_jbar_auto_in_a_bits_size; // @[BankedL2Params.scala 58:41]
  wire [1:0] coherent_jbar_auto_in_a_bits_source; // @[BankedL2Params.scala 58:41]
  wire [30:0] coherent_jbar_auto_in_a_bits_address; // @[BankedL2Params.scala 58:41]
  wire [3:0] coherent_jbar_auto_in_a_bits_mask; // @[BankedL2Params.scala 58:41]
  wire [31:0] coherent_jbar_auto_in_a_bits_data; // @[BankedL2Params.scala 58:41]
  wire  coherent_jbar_auto_in_a_bits_corrupt; // @[BankedL2Params.scala 58:41]
  wire  coherent_jbar_auto_in_b_ready; // @[BankedL2Params.scala 58:41]
  wire  coherent_jbar_auto_in_b_valid; // @[BankedL2Params.scala 58:41]
  wire [1:0] coherent_jbar_auto_in_b_bits_param; // @[BankedL2Params.scala 58:41]
  wire [30:0] coherent_jbar_auto_in_b_bits_address; // @[BankedL2Params.scala 58:41]
  wire  coherent_jbar_auto_in_c_ready; // @[BankedL2Params.scala 58:41]
  wire  coherent_jbar_auto_in_c_valid; // @[BankedL2Params.scala 58:41]
  wire [2:0] coherent_jbar_auto_in_c_bits_opcode; // @[BankedL2Params.scala 58:41]
  wire [2:0] coherent_jbar_auto_in_c_bits_param; // @[BankedL2Params.scala 58:41]
  wire [2:0] coherent_jbar_auto_in_c_bits_size; // @[BankedL2Params.scala 58:41]
  wire [1:0] coherent_jbar_auto_in_c_bits_source; // @[BankedL2Params.scala 58:41]
  wire [30:0] coherent_jbar_auto_in_c_bits_address; // @[BankedL2Params.scala 58:41]
  wire [31:0] coherent_jbar_auto_in_c_bits_data; // @[BankedL2Params.scala 58:41]
  wire  coherent_jbar_auto_in_c_bits_corrupt; // @[BankedL2Params.scala 58:41]
  wire  coherent_jbar_auto_in_d_ready; // @[BankedL2Params.scala 58:41]
  wire  coherent_jbar_auto_in_d_valid; // @[BankedL2Params.scala 58:41]
  wire [2:0] coherent_jbar_auto_in_d_bits_opcode; // @[BankedL2Params.scala 58:41]
  wire [1:0] coherent_jbar_auto_in_d_bits_param; // @[BankedL2Params.scala 58:41]
  wire [2:0] coherent_jbar_auto_in_d_bits_size; // @[BankedL2Params.scala 58:41]
  wire [1:0] coherent_jbar_auto_in_d_bits_source; // @[BankedL2Params.scala 58:41]
  wire [1:0] coherent_jbar_auto_in_d_bits_sink; // @[BankedL2Params.scala 58:41]
  wire [31:0] coherent_jbar_auto_in_d_bits_data; // @[BankedL2Params.scala 58:41]
  wire  coherent_jbar_auto_in_e_valid; // @[BankedL2Params.scala 58:41]
  wire [1:0] coherent_jbar_auto_in_e_bits_sink; // @[BankedL2Params.scala 58:41]
  wire  coherent_jbar_auto_out_a_ready; // @[BankedL2Params.scala 58:41]
  wire  coherent_jbar_auto_out_a_valid; // @[BankedL2Params.scala 58:41]
  wire [2:0] coherent_jbar_auto_out_a_bits_opcode; // @[BankedL2Params.scala 58:41]
  wire [2:0] coherent_jbar_auto_out_a_bits_param; // @[BankedL2Params.scala 58:41]
  wire [2:0] coherent_jbar_auto_out_a_bits_size; // @[BankedL2Params.scala 58:41]
  wire [1:0] coherent_jbar_auto_out_a_bits_source; // @[BankedL2Params.scala 58:41]
  wire [30:0] coherent_jbar_auto_out_a_bits_address; // @[BankedL2Params.scala 58:41]
  wire [3:0] coherent_jbar_auto_out_a_bits_mask; // @[BankedL2Params.scala 58:41]
  wire [31:0] coherent_jbar_auto_out_a_bits_data; // @[BankedL2Params.scala 58:41]
  wire  coherent_jbar_auto_out_a_bits_corrupt; // @[BankedL2Params.scala 58:41]
  wire  coherent_jbar_auto_out_b_ready; // @[BankedL2Params.scala 58:41]
  wire  coherent_jbar_auto_out_b_valid; // @[BankedL2Params.scala 58:41]
  wire [1:0] coherent_jbar_auto_out_b_bits_param; // @[BankedL2Params.scala 58:41]
  wire [30:0] coherent_jbar_auto_out_b_bits_address; // @[BankedL2Params.scala 58:41]
  wire  coherent_jbar_auto_out_c_ready; // @[BankedL2Params.scala 58:41]
  wire  coherent_jbar_auto_out_c_valid; // @[BankedL2Params.scala 58:41]
  wire [2:0] coherent_jbar_auto_out_c_bits_opcode; // @[BankedL2Params.scala 58:41]
  wire [2:0] coherent_jbar_auto_out_c_bits_param; // @[BankedL2Params.scala 58:41]
  wire [2:0] coherent_jbar_auto_out_c_bits_size; // @[BankedL2Params.scala 58:41]
  wire [1:0] coherent_jbar_auto_out_c_bits_source; // @[BankedL2Params.scala 58:41]
  wire [30:0] coherent_jbar_auto_out_c_bits_address; // @[BankedL2Params.scala 58:41]
  wire [31:0] coherent_jbar_auto_out_c_bits_data; // @[BankedL2Params.scala 58:41]
  wire  coherent_jbar_auto_out_c_bits_corrupt; // @[BankedL2Params.scala 58:41]
  wire  coherent_jbar_auto_out_d_ready; // @[BankedL2Params.scala 58:41]
  wire  coherent_jbar_auto_out_d_valid; // @[BankedL2Params.scala 58:41]
  wire [2:0] coherent_jbar_auto_out_d_bits_opcode; // @[BankedL2Params.scala 58:41]
  wire [1:0] coherent_jbar_auto_out_d_bits_param; // @[BankedL2Params.scala 58:41]
  wire [2:0] coherent_jbar_auto_out_d_bits_size; // @[BankedL2Params.scala 58:41]
  wire [1:0] coherent_jbar_auto_out_d_bits_source; // @[BankedL2Params.scala 58:41]
  wire [1:0] coherent_jbar_auto_out_d_bits_sink; // @[BankedL2Params.scala 58:41]
  wire [31:0] coherent_jbar_auto_out_d_bits_data; // @[BankedL2Params.scala 58:41]
  wire  coherent_jbar_auto_out_e_valid; // @[BankedL2Params.scala 58:41]
  wire [1:0] coherent_jbar_auto_out_e_bits_sink; // @[BankedL2Params.scala 58:41]
  wire  binder_clock; // @[BankBinder.scala 67:28]
  wire  binder_reset; // @[BankBinder.scala 67:28]
  wire  binder_auto_in_a_ready; // @[BankBinder.scala 67:28]
  wire  binder_auto_in_a_valid; // @[BankBinder.scala 67:28]
  wire [2:0] binder_auto_in_a_bits_opcode; // @[BankBinder.scala 67:28]
  wire [2:0] binder_auto_in_a_bits_param; // @[BankBinder.scala 67:28]
  wire [2:0] binder_auto_in_a_bits_size; // @[BankBinder.scala 67:28]
  wire [3:0] binder_auto_in_a_bits_source; // @[BankBinder.scala 67:28]
  wire [30:0] binder_auto_in_a_bits_address; // @[BankBinder.scala 67:28]
  wire [3:0] binder_auto_in_a_bits_mask; // @[BankBinder.scala 67:28]
  wire [31:0] binder_auto_in_a_bits_data; // @[BankBinder.scala 67:28]
  wire  binder_auto_in_d_ready; // @[BankBinder.scala 67:28]
  wire  binder_auto_in_d_valid; // @[BankBinder.scala 67:28]
  wire [2:0] binder_auto_in_d_bits_opcode; // @[BankBinder.scala 67:28]
  wire [2:0] binder_auto_in_d_bits_size; // @[BankBinder.scala 67:28]
  wire [3:0] binder_auto_in_d_bits_source; // @[BankBinder.scala 67:28]
  wire [31:0] binder_auto_in_d_bits_data; // @[BankBinder.scala 67:28]
  wire  binder_auto_out_a_ready; // @[BankBinder.scala 67:28]
  wire  binder_auto_out_a_valid; // @[BankBinder.scala 67:28]
  wire [2:0] binder_auto_out_a_bits_opcode; // @[BankBinder.scala 67:28]
  wire [2:0] binder_auto_out_a_bits_param; // @[BankBinder.scala 67:28]
  wire [2:0] binder_auto_out_a_bits_size; // @[BankBinder.scala 67:28]
  wire [3:0] binder_auto_out_a_bits_source; // @[BankBinder.scala 67:28]
  wire [30:0] binder_auto_out_a_bits_address; // @[BankBinder.scala 67:28]
  wire [3:0] binder_auto_out_a_bits_mask; // @[BankBinder.scala 67:28]
  wire [31:0] binder_auto_out_a_bits_data; // @[BankBinder.scala 67:28]
  wire  binder_auto_out_d_ready; // @[BankBinder.scala 67:28]
  wire  binder_auto_out_d_valid; // @[BankBinder.scala 67:28]
  wire [2:0] binder_auto_out_d_bits_opcode; // @[BankBinder.scala 67:28]
  wire [2:0] binder_auto_out_d_bits_size; // @[BankBinder.scala 67:28]
  wire [3:0] binder_auto_out_d_bits_source; // @[BankBinder.scala 67:28]
  wire [31:0] binder_auto_out_d_bits_data; // @[BankBinder.scala 67:28]
  wire  coupler_to_bus_named_subsystem_mbus_auto_widget_in_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_mbus_auto_widget_in_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_mbus_auto_widget_in_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_mbus_auto_widget_in_a_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_mbus_auto_widget_in_a_bits_size; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_bus_named_subsystem_mbus_auto_widget_in_a_bits_source; // @[LazyModule.scala 432:27]
  wire [30:0] coupler_to_bus_named_subsystem_mbus_auto_widget_in_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_bus_named_subsystem_mbus_auto_widget_in_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_bus_named_subsystem_mbus_auto_widget_in_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_mbus_auto_widget_in_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_mbus_auto_widget_in_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_mbus_auto_widget_in_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_mbus_auto_widget_in_d_bits_size; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_bus_named_subsystem_mbus_auto_widget_in_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_bus_named_subsystem_mbus_auto_widget_in_d_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_a_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_a_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_a_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_a_bits_param; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_a_bits_size; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_a_bits_source; // @[LazyModule.scala 432:27]
  wire [30:0] coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_a_bits_address; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_a_bits_mask; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_a_bits_data; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_d_ready; // @[LazyModule.scala 432:27]
  wire  coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_d_valid; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_d_bits_opcode; // @[LazyModule.scala 432:27]
  wire [2:0] coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_d_bits_size; // @[LazyModule.scala 432:27]
  wire [3:0] coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_d_bits_source; // @[LazyModule.scala 432:27]
  wire [31:0] coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_d_bits_data; // @[LazyModule.scala 432:27]
  ClockGroupAggregator_5 subsystem_l2_clock_groups ( // @[BusWrapper.scala 40:48]
    .auto_in_member_subsystem_l2_1_clock(subsystem_l2_clock_groups_auto_in_member_subsystem_l2_1_clock),
    .auto_in_member_subsystem_l2_1_reset(subsystem_l2_clock_groups_auto_in_member_subsystem_l2_1_reset),
    .auto_in_member_subsystem_l2_0_clock(subsystem_l2_clock_groups_auto_in_member_subsystem_l2_0_clock),
    .auto_in_member_subsystem_l2_0_reset(subsystem_l2_clock_groups_auto_in_member_subsystem_l2_0_reset),
    .auto_out_1_member_subsystem_mbus_0_clock(subsystem_l2_clock_groups_auto_out_1_member_subsystem_mbus_0_clock),
    .auto_out_1_member_subsystem_mbus_0_reset(subsystem_l2_clock_groups_auto_out_1_member_subsystem_mbus_0_reset),
    .auto_out_0_member_subsystem_l2_0_clock(subsystem_l2_clock_groups_auto_out_0_member_subsystem_l2_0_clock),
    .auto_out_0_member_subsystem_l2_0_reset(subsystem_l2_clock_groups_auto_out_0_member_subsystem_l2_0_reset)
  );
  ClockGroup_5 clockGroup ( // @[BusWrapper.scala 41:38]
    .auto_in_member_subsystem_l2_0_clock(clockGroup_auto_in_member_subsystem_l2_0_clock),
    .auto_in_member_subsystem_l2_0_reset(clockGroup_auto_in_member_subsystem_l2_0_reset),
    .auto_out_clock(clockGroup_auto_out_clock),
    .auto_out_reset(clockGroup_auto_out_reset)
  );
  FixedClockBroadcast_2 fixedClockNode ( // @[ClockGroup.scala 106:107]
    .auto_in_clock(fixedClockNode_auto_in_clock),
    .auto_in_reset(fixedClockNode_auto_in_reset),
    .auto_out_clock(fixedClockNode_auto_out_clock),
    .auto_out_reset(fixedClockNode_auto_out_reset)
  );
  TLBroadcast broadcast_1 ( // @[BankedL2Params.scala 81:24]
    .clock(broadcast_1_clock),
    .reset(broadcast_1_reset),
    .auto_in_a_ready(broadcast_1_auto_in_a_ready),
    .auto_in_a_valid(broadcast_1_auto_in_a_valid),
    .auto_in_a_bits_opcode(broadcast_1_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(broadcast_1_auto_in_a_bits_param),
    .auto_in_a_bits_size(broadcast_1_auto_in_a_bits_size),
    .auto_in_a_bits_source(broadcast_1_auto_in_a_bits_source),
    .auto_in_a_bits_address(broadcast_1_auto_in_a_bits_address),
    .auto_in_a_bits_mask(broadcast_1_auto_in_a_bits_mask),
    .auto_in_a_bits_data(broadcast_1_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(broadcast_1_auto_in_a_bits_corrupt),
    .auto_in_b_ready(broadcast_1_auto_in_b_ready),
    .auto_in_b_valid(broadcast_1_auto_in_b_valid),
    .auto_in_b_bits_param(broadcast_1_auto_in_b_bits_param),
    .auto_in_b_bits_address(broadcast_1_auto_in_b_bits_address),
    .auto_in_c_ready(broadcast_1_auto_in_c_ready),
    .auto_in_c_valid(broadcast_1_auto_in_c_valid),
    .auto_in_c_bits_opcode(broadcast_1_auto_in_c_bits_opcode),
    .auto_in_c_bits_param(broadcast_1_auto_in_c_bits_param),
    .auto_in_c_bits_size(broadcast_1_auto_in_c_bits_size),
    .auto_in_c_bits_source(broadcast_1_auto_in_c_bits_source),
    .auto_in_c_bits_address(broadcast_1_auto_in_c_bits_address),
    .auto_in_c_bits_data(broadcast_1_auto_in_c_bits_data),
    .auto_in_c_bits_corrupt(broadcast_1_auto_in_c_bits_corrupt),
    .auto_in_d_ready(broadcast_1_auto_in_d_ready),
    .auto_in_d_valid(broadcast_1_auto_in_d_valid),
    .auto_in_d_bits_opcode(broadcast_1_auto_in_d_bits_opcode),
    .auto_in_d_bits_param(broadcast_1_auto_in_d_bits_param),
    .auto_in_d_bits_size(broadcast_1_auto_in_d_bits_size),
    .auto_in_d_bits_source(broadcast_1_auto_in_d_bits_source),
    .auto_in_d_bits_sink(broadcast_1_auto_in_d_bits_sink),
    .auto_in_d_bits_data(broadcast_1_auto_in_d_bits_data),
    .auto_in_e_valid(broadcast_1_auto_in_e_valid),
    .auto_in_e_bits_sink(broadcast_1_auto_in_e_bits_sink),
    .auto_out_a_ready(broadcast_1_auto_out_a_ready),
    .auto_out_a_valid(broadcast_1_auto_out_a_valid),
    .auto_out_a_bits_opcode(broadcast_1_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(broadcast_1_auto_out_a_bits_param),
    .auto_out_a_bits_size(broadcast_1_auto_out_a_bits_size),
    .auto_out_a_bits_source(broadcast_1_auto_out_a_bits_source),
    .auto_out_a_bits_address(broadcast_1_auto_out_a_bits_address),
    .auto_out_a_bits_mask(broadcast_1_auto_out_a_bits_mask),
    .auto_out_a_bits_data(broadcast_1_auto_out_a_bits_data),
    .auto_out_d_ready(broadcast_1_auto_out_d_ready),
    .auto_out_d_valid(broadcast_1_auto_out_d_valid),
    .auto_out_d_bits_opcode(broadcast_1_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(broadcast_1_auto_out_d_bits_size),
    .auto_out_d_bits_source(broadcast_1_auto_out_d_bits_source),
    .auto_out_d_bits_data(broadcast_1_auto_out_d_bits_data)
  );
  TLJbar coherent_jbar ( // @[BankedL2Params.scala 58:41]
    .auto_in_a_ready(coherent_jbar_auto_in_a_ready),
    .auto_in_a_valid(coherent_jbar_auto_in_a_valid),
    .auto_in_a_bits_opcode(coherent_jbar_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(coherent_jbar_auto_in_a_bits_param),
    .auto_in_a_bits_size(coherent_jbar_auto_in_a_bits_size),
    .auto_in_a_bits_source(coherent_jbar_auto_in_a_bits_source),
    .auto_in_a_bits_address(coherent_jbar_auto_in_a_bits_address),
    .auto_in_a_bits_mask(coherent_jbar_auto_in_a_bits_mask),
    .auto_in_a_bits_data(coherent_jbar_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(coherent_jbar_auto_in_a_bits_corrupt),
    .auto_in_b_ready(coherent_jbar_auto_in_b_ready),
    .auto_in_b_valid(coherent_jbar_auto_in_b_valid),
    .auto_in_b_bits_param(coherent_jbar_auto_in_b_bits_param),
    .auto_in_b_bits_address(coherent_jbar_auto_in_b_bits_address),
    .auto_in_c_ready(coherent_jbar_auto_in_c_ready),
    .auto_in_c_valid(coherent_jbar_auto_in_c_valid),
    .auto_in_c_bits_opcode(coherent_jbar_auto_in_c_bits_opcode),
    .auto_in_c_bits_param(coherent_jbar_auto_in_c_bits_param),
    .auto_in_c_bits_size(coherent_jbar_auto_in_c_bits_size),
    .auto_in_c_bits_source(coherent_jbar_auto_in_c_bits_source),
    .auto_in_c_bits_address(coherent_jbar_auto_in_c_bits_address),
    .auto_in_c_bits_data(coherent_jbar_auto_in_c_bits_data),
    .auto_in_c_bits_corrupt(coherent_jbar_auto_in_c_bits_corrupt),
    .auto_in_d_ready(coherent_jbar_auto_in_d_ready),
    .auto_in_d_valid(coherent_jbar_auto_in_d_valid),
    .auto_in_d_bits_opcode(coherent_jbar_auto_in_d_bits_opcode),
    .auto_in_d_bits_param(coherent_jbar_auto_in_d_bits_param),
    .auto_in_d_bits_size(coherent_jbar_auto_in_d_bits_size),
    .auto_in_d_bits_source(coherent_jbar_auto_in_d_bits_source),
    .auto_in_d_bits_sink(coherent_jbar_auto_in_d_bits_sink),
    .auto_in_d_bits_data(coherent_jbar_auto_in_d_bits_data),
    .auto_in_e_valid(coherent_jbar_auto_in_e_valid),
    .auto_in_e_bits_sink(coherent_jbar_auto_in_e_bits_sink),
    .auto_out_a_ready(coherent_jbar_auto_out_a_ready),
    .auto_out_a_valid(coherent_jbar_auto_out_a_valid),
    .auto_out_a_bits_opcode(coherent_jbar_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(coherent_jbar_auto_out_a_bits_param),
    .auto_out_a_bits_size(coherent_jbar_auto_out_a_bits_size),
    .auto_out_a_bits_source(coherent_jbar_auto_out_a_bits_source),
    .auto_out_a_bits_address(coherent_jbar_auto_out_a_bits_address),
    .auto_out_a_bits_mask(coherent_jbar_auto_out_a_bits_mask),
    .auto_out_a_bits_data(coherent_jbar_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(coherent_jbar_auto_out_a_bits_corrupt),
    .auto_out_b_ready(coherent_jbar_auto_out_b_ready),
    .auto_out_b_valid(coherent_jbar_auto_out_b_valid),
    .auto_out_b_bits_param(coherent_jbar_auto_out_b_bits_param),
    .auto_out_b_bits_address(coherent_jbar_auto_out_b_bits_address),
    .auto_out_c_ready(coherent_jbar_auto_out_c_ready),
    .auto_out_c_valid(coherent_jbar_auto_out_c_valid),
    .auto_out_c_bits_opcode(coherent_jbar_auto_out_c_bits_opcode),
    .auto_out_c_bits_param(coherent_jbar_auto_out_c_bits_param),
    .auto_out_c_bits_size(coherent_jbar_auto_out_c_bits_size),
    .auto_out_c_bits_source(coherent_jbar_auto_out_c_bits_source),
    .auto_out_c_bits_address(coherent_jbar_auto_out_c_bits_address),
    .auto_out_c_bits_data(coherent_jbar_auto_out_c_bits_data),
    .auto_out_c_bits_corrupt(coherent_jbar_auto_out_c_bits_corrupt),
    .auto_out_d_ready(coherent_jbar_auto_out_d_ready),
    .auto_out_d_valid(coherent_jbar_auto_out_d_valid),
    .auto_out_d_bits_opcode(coherent_jbar_auto_out_d_bits_opcode),
    .auto_out_d_bits_param(coherent_jbar_auto_out_d_bits_param),
    .auto_out_d_bits_size(coherent_jbar_auto_out_d_bits_size),
    .auto_out_d_bits_source(coherent_jbar_auto_out_d_bits_source),
    .auto_out_d_bits_sink(coherent_jbar_auto_out_d_bits_sink),
    .auto_out_d_bits_data(coherent_jbar_auto_out_d_bits_data),
    .auto_out_e_valid(coherent_jbar_auto_out_e_valid),
    .auto_out_e_bits_sink(coherent_jbar_auto_out_e_bits_sink)
  );
  BankBinder binder ( // @[BankBinder.scala 67:28]
    .clock(binder_clock),
    .reset(binder_reset),
    .auto_in_a_ready(binder_auto_in_a_ready),
    .auto_in_a_valid(binder_auto_in_a_valid),
    .auto_in_a_bits_opcode(binder_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(binder_auto_in_a_bits_param),
    .auto_in_a_bits_size(binder_auto_in_a_bits_size),
    .auto_in_a_bits_source(binder_auto_in_a_bits_source),
    .auto_in_a_bits_address(binder_auto_in_a_bits_address),
    .auto_in_a_bits_mask(binder_auto_in_a_bits_mask),
    .auto_in_a_bits_data(binder_auto_in_a_bits_data),
    .auto_in_d_ready(binder_auto_in_d_ready),
    .auto_in_d_valid(binder_auto_in_d_valid),
    .auto_in_d_bits_opcode(binder_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(binder_auto_in_d_bits_size),
    .auto_in_d_bits_source(binder_auto_in_d_bits_source),
    .auto_in_d_bits_data(binder_auto_in_d_bits_data),
    .auto_out_a_ready(binder_auto_out_a_ready),
    .auto_out_a_valid(binder_auto_out_a_valid),
    .auto_out_a_bits_opcode(binder_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(binder_auto_out_a_bits_param),
    .auto_out_a_bits_size(binder_auto_out_a_bits_size),
    .auto_out_a_bits_source(binder_auto_out_a_bits_source),
    .auto_out_a_bits_address(binder_auto_out_a_bits_address),
    .auto_out_a_bits_mask(binder_auto_out_a_bits_mask),
    .auto_out_a_bits_data(binder_auto_out_a_bits_data),
    .auto_out_d_ready(binder_auto_out_d_ready),
    .auto_out_d_valid(binder_auto_out_d_valid),
    .auto_out_d_bits_opcode(binder_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(binder_auto_out_d_bits_size),
    .auto_out_d_bits_source(binder_auto_out_d_bits_source),
    .auto_out_d_bits_data(binder_auto_out_d_bits_data)
  );
  TLInterconnectCoupler_27 coupler_to_bus_named_subsystem_mbus ( // @[LazyModule.scala 432:27]
    .auto_widget_in_a_ready(coupler_to_bus_named_subsystem_mbus_auto_widget_in_a_ready),
    .auto_widget_in_a_valid(coupler_to_bus_named_subsystem_mbus_auto_widget_in_a_valid),
    .auto_widget_in_a_bits_opcode(coupler_to_bus_named_subsystem_mbus_auto_widget_in_a_bits_opcode),
    .auto_widget_in_a_bits_param(coupler_to_bus_named_subsystem_mbus_auto_widget_in_a_bits_param),
    .auto_widget_in_a_bits_size(coupler_to_bus_named_subsystem_mbus_auto_widget_in_a_bits_size),
    .auto_widget_in_a_bits_source(coupler_to_bus_named_subsystem_mbus_auto_widget_in_a_bits_source),
    .auto_widget_in_a_bits_address(coupler_to_bus_named_subsystem_mbus_auto_widget_in_a_bits_address),
    .auto_widget_in_a_bits_mask(coupler_to_bus_named_subsystem_mbus_auto_widget_in_a_bits_mask),
    .auto_widget_in_a_bits_data(coupler_to_bus_named_subsystem_mbus_auto_widget_in_a_bits_data),
    .auto_widget_in_d_ready(coupler_to_bus_named_subsystem_mbus_auto_widget_in_d_ready),
    .auto_widget_in_d_valid(coupler_to_bus_named_subsystem_mbus_auto_widget_in_d_valid),
    .auto_widget_in_d_bits_opcode(coupler_to_bus_named_subsystem_mbus_auto_widget_in_d_bits_opcode),
    .auto_widget_in_d_bits_size(coupler_to_bus_named_subsystem_mbus_auto_widget_in_d_bits_size),
    .auto_widget_in_d_bits_source(coupler_to_bus_named_subsystem_mbus_auto_widget_in_d_bits_source),
    .auto_widget_in_d_bits_data(coupler_to_bus_named_subsystem_mbus_auto_widget_in_d_bits_data),
    .auto_bus_xing_out_a_ready(coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_a_ready),
    .auto_bus_xing_out_a_valid(coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_a_valid),
    .auto_bus_xing_out_a_bits_opcode(coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_a_bits_opcode),
    .auto_bus_xing_out_a_bits_param(coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_a_bits_param),
    .auto_bus_xing_out_a_bits_size(coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_a_bits_size),
    .auto_bus_xing_out_a_bits_source(coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_a_bits_source),
    .auto_bus_xing_out_a_bits_address(coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_a_bits_address),
    .auto_bus_xing_out_a_bits_mask(coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_a_bits_mask),
    .auto_bus_xing_out_a_bits_data(coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_a_bits_data),
    .auto_bus_xing_out_d_ready(coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_d_ready),
    .auto_bus_xing_out_d_valid(coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_d_valid),
    .auto_bus_xing_out_d_bits_opcode(coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_d_bits_opcode),
    .auto_bus_xing_out_d_bits_size(coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_d_bits_size),
    .auto_bus_xing_out_d_bits_source(coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_d_bits_source),
    .auto_bus_xing_out_d_bits_data(coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_d_bits_data)
  );
  assign auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_valid =
    coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_a_valid; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_opcode =
    coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_a_bits_opcode; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_param =
    coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_a_bits_param; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_size =
    coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_a_bits_size; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_source =
    coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_a_bits_source; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_address =
    coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_a_bits_address; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_mask =
    coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_a_bits_mask; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_data =
    coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_a_bits_data; // @[LazyModule.scala 311:12]
  assign auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_ready =
    coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_d_ready; // @[LazyModule.scala 311:12]
  assign auto_coherent_jbar_in_a_ready = coherent_jbar_auto_in_a_ready; // @[LazyModule.scala 309:16]
  assign auto_coherent_jbar_in_b_valid = coherent_jbar_auto_in_b_valid; // @[LazyModule.scala 309:16]
  assign auto_coherent_jbar_in_b_bits_param = coherent_jbar_auto_in_b_bits_param; // @[LazyModule.scala 309:16]
  assign auto_coherent_jbar_in_b_bits_address = coherent_jbar_auto_in_b_bits_address; // @[LazyModule.scala 309:16]
  assign auto_coherent_jbar_in_c_ready = coherent_jbar_auto_in_c_ready; // @[LazyModule.scala 309:16]
  assign auto_coherent_jbar_in_d_valid = coherent_jbar_auto_in_d_valid; // @[LazyModule.scala 309:16]
  assign auto_coherent_jbar_in_d_bits_opcode = coherent_jbar_auto_in_d_bits_opcode; // @[LazyModule.scala 309:16]
  assign auto_coherent_jbar_in_d_bits_param = coherent_jbar_auto_in_d_bits_param; // @[LazyModule.scala 309:16]
  assign auto_coherent_jbar_in_d_bits_size = coherent_jbar_auto_in_d_bits_size; // @[LazyModule.scala 309:16]
  assign auto_coherent_jbar_in_d_bits_source = coherent_jbar_auto_in_d_bits_source; // @[LazyModule.scala 309:16]
  assign auto_coherent_jbar_in_d_bits_sink = coherent_jbar_auto_in_d_bits_sink; // @[LazyModule.scala 309:16]
  assign auto_coherent_jbar_in_d_bits_data = coherent_jbar_auto_in_d_bits_data; // @[LazyModule.scala 309:16]
  assign auto_subsystem_l2_clock_groups_out_member_subsystem_mbus_0_clock =
    subsystem_l2_clock_groups_auto_out_1_member_subsystem_mbus_0_clock; // @[LazyModule.scala 311:12]
  assign auto_subsystem_l2_clock_groups_out_member_subsystem_mbus_0_reset =
    subsystem_l2_clock_groups_auto_out_1_member_subsystem_mbus_0_reset; // @[LazyModule.scala 311:12]
  assign subsystem_l2_clock_groups_auto_in_member_subsystem_l2_1_clock =
    auto_subsystem_l2_clock_groups_in_member_subsystem_l2_1_clock; // @[LazyModule.scala 309:16]
  assign subsystem_l2_clock_groups_auto_in_member_subsystem_l2_1_reset =
    auto_subsystem_l2_clock_groups_in_member_subsystem_l2_1_reset; // @[LazyModule.scala 309:16]
  assign subsystem_l2_clock_groups_auto_in_member_subsystem_l2_0_clock =
    auto_subsystem_l2_clock_groups_in_member_subsystem_l2_0_clock; // @[LazyModule.scala 309:16]
  assign subsystem_l2_clock_groups_auto_in_member_subsystem_l2_0_reset =
    auto_subsystem_l2_clock_groups_in_member_subsystem_l2_0_reset; // @[LazyModule.scala 309:16]
  assign clockGroup_auto_in_member_subsystem_l2_0_clock =
    subsystem_l2_clock_groups_auto_out_0_member_subsystem_l2_0_clock; // @[LazyModule.scala 298:16]
  assign clockGroup_auto_in_member_subsystem_l2_0_reset =
    subsystem_l2_clock_groups_auto_out_0_member_subsystem_l2_0_reset; // @[LazyModule.scala 298:16]
  assign fixedClockNode_auto_in_clock = clockGroup_auto_out_clock; // @[LazyModule.scala 298:16]
  assign fixedClockNode_auto_in_reset = clockGroup_auto_out_reset; // @[LazyModule.scala 298:16]
  assign broadcast_1_clock = fixedClockNode_auto_out_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign broadcast_1_reset = fixedClockNode_auto_out_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign broadcast_1_auto_in_a_valid = coherent_jbar_auto_out_a_valid; // @[LazyModule.scala 296:16]
  assign broadcast_1_auto_in_a_bits_opcode = coherent_jbar_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign broadcast_1_auto_in_a_bits_param = coherent_jbar_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
  assign broadcast_1_auto_in_a_bits_size = coherent_jbar_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign broadcast_1_auto_in_a_bits_source = coherent_jbar_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign broadcast_1_auto_in_a_bits_address = coherent_jbar_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign broadcast_1_auto_in_a_bits_mask = coherent_jbar_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign broadcast_1_auto_in_a_bits_data = coherent_jbar_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign broadcast_1_auto_in_a_bits_corrupt = coherent_jbar_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
  assign broadcast_1_auto_in_b_ready = coherent_jbar_auto_out_b_ready; // @[LazyModule.scala 296:16]
  assign broadcast_1_auto_in_c_valid = coherent_jbar_auto_out_c_valid; // @[LazyModule.scala 296:16]
  assign broadcast_1_auto_in_c_bits_opcode = coherent_jbar_auto_out_c_bits_opcode; // @[LazyModule.scala 296:16]
  assign broadcast_1_auto_in_c_bits_param = coherent_jbar_auto_out_c_bits_param; // @[LazyModule.scala 296:16]
  assign broadcast_1_auto_in_c_bits_size = coherent_jbar_auto_out_c_bits_size; // @[LazyModule.scala 296:16]
  assign broadcast_1_auto_in_c_bits_source = coherent_jbar_auto_out_c_bits_source; // @[LazyModule.scala 296:16]
  assign broadcast_1_auto_in_c_bits_address = coherent_jbar_auto_out_c_bits_address; // @[LazyModule.scala 296:16]
  assign broadcast_1_auto_in_c_bits_data = coherent_jbar_auto_out_c_bits_data; // @[LazyModule.scala 296:16]
  assign broadcast_1_auto_in_c_bits_corrupt = coherent_jbar_auto_out_c_bits_corrupt; // @[LazyModule.scala 296:16]
  assign broadcast_1_auto_in_d_ready = coherent_jbar_auto_out_d_ready; // @[LazyModule.scala 296:16]
  assign broadcast_1_auto_in_e_valid = coherent_jbar_auto_out_e_valid; // @[LazyModule.scala 296:16]
  assign broadcast_1_auto_in_e_bits_sink = coherent_jbar_auto_out_e_bits_sink; // @[LazyModule.scala 296:16]
  assign broadcast_1_auto_out_a_ready = binder_auto_in_a_ready; // @[LazyModule.scala 298:16]
  assign broadcast_1_auto_out_d_valid = binder_auto_in_d_valid; // @[LazyModule.scala 298:16]
  assign broadcast_1_auto_out_d_bits_opcode = binder_auto_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign broadcast_1_auto_out_d_bits_size = binder_auto_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign broadcast_1_auto_out_d_bits_source = binder_auto_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign broadcast_1_auto_out_d_bits_data = binder_auto_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign coherent_jbar_auto_in_a_valid = auto_coherent_jbar_in_a_valid; // @[LazyModule.scala 309:16]
  assign coherent_jbar_auto_in_a_bits_opcode = auto_coherent_jbar_in_a_bits_opcode; // @[LazyModule.scala 309:16]
  assign coherent_jbar_auto_in_a_bits_param = auto_coherent_jbar_in_a_bits_param; // @[LazyModule.scala 309:16]
  assign coherent_jbar_auto_in_a_bits_size = auto_coherent_jbar_in_a_bits_size; // @[LazyModule.scala 309:16]
  assign coherent_jbar_auto_in_a_bits_source = auto_coherent_jbar_in_a_bits_source; // @[LazyModule.scala 309:16]
  assign coherent_jbar_auto_in_a_bits_address = auto_coherent_jbar_in_a_bits_address; // @[LazyModule.scala 309:16]
  assign coherent_jbar_auto_in_a_bits_mask = auto_coherent_jbar_in_a_bits_mask; // @[LazyModule.scala 309:16]
  assign coherent_jbar_auto_in_a_bits_data = auto_coherent_jbar_in_a_bits_data; // @[LazyModule.scala 309:16]
  assign coherent_jbar_auto_in_a_bits_corrupt = auto_coherent_jbar_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
  assign coherent_jbar_auto_in_b_ready = auto_coherent_jbar_in_b_ready; // @[LazyModule.scala 309:16]
  assign coherent_jbar_auto_in_c_valid = auto_coherent_jbar_in_c_valid; // @[LazyModule.scala 309:16]
  assign coherent_jbar_auto_in_c_bits_opcode = auto_coherent_jbar_in_c_bits_opcode; // @[LazyModule.scala 309:16]
  assign coherent_jbar_auto_in_c_bits_param = auto_coherent_jbar_in_c_bits_param; // @[LazyModule.scala 309:16]
  assign coherent_jbar_auto_in_c_bits_size = auto_coherent_jbar_in_c_bits_size; // @[LazyModule.scala 309:16]
  assign coherent_jbar_auto_in_c_bits_source = auto_coherent_jbar_in_c_bits_source; // @[LazyModule.scala 309:16]
  assign coherent_jbar_auto_in_c_bits_address = auto_coherent_jbar_in_c_bits_address; // @[LazyModule.scala 309:16]
  assign coherent_jbar_auto_in_c_bits_data = auto_coherent_jbar_in_c_bits_data; // @[LazyModule.scala 309:16]
  assign coherent_jbar_auto_in_c_bits_corrupt = auto_coherent_jbar_in_c_bits_corrupt; // @[LazyModule.scala 309:16]
  assign coherent_jbar_auto_in_d_ready = auto_coherent_jbar_in_d_ready; // @[LazyModule.scala 309:16]
  assign coherent_jbar_auto_in_e_valid = auto_coherent_jbar_in_e_valid; // @[LazyModule.scala 309:16]
  assign coherent_jbar_auto_in_e_bits_sink = auto_coherent_jbar_in_e_bits_sink; // @[LazyModule.scala 309:16]
  assign coherent_jbar_auto_out_a_ready = broadcast_1_auto_in_a_ready; // @[LazyModule.scala 296:16]
  assign coherent_jbar_auto_out_b_valid = broadcast_1_auto_in_b_valid; // @[LazyModule.scala 296:16]
  assign coherent_jbar_auto_out_b_bits_param = broadcast_1_auto_in_b_bits_param; // @[LazyModule.scala 296:16]
  assign coherent_jbar_auto_out_b_bits_address = broadcast_1_auto_in_b_bits_address; // @[LazyModule.scala 296:16]
  assign coherent_jbar_auto_out_c_ready = broadcast_1_auto_in_c_ready; // @[LazyModule.scala 296:16]
  assign coherent_jbar_auto_out_d_valid = broadcast_1_auto_in_d_valid; // @[LazyModule.scala 296:16]
  assign coherent_jbar_auto_out_d_bits_opcode = broadcast_1_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign coherent_jbar_auto_out_d_bits_param = broadcast_1_auto_in_d_bits_param; // @[LazyModule.scala 296:16]
  assign coherent_jbar_auto_out_d_bits_size = broadcast_1_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
  assign coherent_jbar_auto_out_d_bits_source = broadcast_1_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
  assign coherent_jbar_auto_out_d_bits_sink = broadcast_1_auto_in_d_bits_sink; // @[LazyModule.scala 296:16]
  assign coherent_jbar_auto_out_d_bits_data = broadcast_1_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
  assign binder_clock = fixedClockNode_auto_out_clock; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign binder_reset = fixedClockNode_auto_out_reset; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign binder_auto_in_a_valid = broadcast_1_auto_out_a_valid; // @[LazyModule.scala 298:16]
  assign binder_auto_in_a_bits_opcode = broadcast_1_auto_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign binder_auto_in_a_bits_param = broadcast_1_auto_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign binder_auto_in_a_bits_size = broadcast_1_auto_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign binder_auto_in_a_bits_source = broadcast_1_auto_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign binder_auto_in_a_bits_address = broadcast_1_auto_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign binder_auto_in_a_bits_mask = broadcast_1_auto_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign binder_auto_in_a_bits_data = broadcast_1_auto_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign binder_auto_in_d_ready = broadcast_1_auto_out_d_ready; // @[LazyModule.scala 298:16]
  assign binder_auto_out_a_ready = coupler_to_bus_named_subsystem_mbus_auto_widget_in_a_ready; // @[LazyModule.scala 298:16]
  assign binder_auto_out_d_valid = coupler_to_bus_named_subsystem_mbus_auto_widget_in_d_valid; // @[LazyModule.scala 298:16]
  assign binder_auto_out_d_bits_opcode = coupler_to_bus_named_subsystem_mbus_auto_widget_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign binder_auto_out_d_bits_size = coupler_to_bus_named_subsystem_mbus_auto_widget_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign binder_auto_out_d_bits_source = coupler_to_bus_named_subsystem_mbus_auto_widget_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign binder_auto_out_d_bits_data = coupler_to_bus_named_subsystem_mbus_auto_widget_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_mbus_auto_widget_in_a_valid = binder_auto_out_a_valid; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_mbus_auto_widget_in_a_bits_opcode = binder_auto_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_mbus_auto_widget_in_a_bits_param = binder_auto_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_mbus_auto_widget_in_a_bits_size = binder_auto_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_mbus_auto_widget_in_a_bits_source = binder_auto_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_mbus_auto_widget_in_a_bits_address = binder_auto_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_mbus_auto_widget_in_a_bits_mask = binder_auto_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_mbus_auto_widget_in_a_bits_data = binder_auto_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_mbus_auto_widget_in_d_ready = binder_auto_out_d_ready; // @[LazyModule.scala 298:16]
  assign coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_a_ready =
    auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_ready; // @[LazyModule.scala 311:12]
  assign coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_d_valid =
    auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_valid; // @[LazyModule.scala 311:12]
  assign coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_d_bits_opcode =
    auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_bits_opcode; // @[LazyModule.scala 311:12]
  assign coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_d_bits_size =
    auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_bits_size; // @[LazyModule.scala 311:12]
  assign coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_d_bits_source =
    auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_bits_source; // @[LazyModule.scala 311:12]
  assign coupler_to_bus_named_subsystem_mbus_auto_bus_xing_out_d_bits_data =
    auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_bits_data; // @[LazyModule.scala 311:12]
endmodule
module TLMonitor_43(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [3:0]  io_in_a_bits_size,
  input         io_in_a_bits_source,
  input  [30:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_b_ready,
  input         io_in_b_valid,
  input  [2:0]  io_in_b_bits_opcode,
  input  [1:0]  io_in_b_bits_param,
  input  [3:0]  io_in_b_bits_size,
  input         io_in_b_bits_source,
  input  [30:0] io_in_b_bits_address,
  input  [3:0]  io_in_b_bits_mask,
  input         io_in_b_bits_corrupt,
  input         io_in_c_ready,
  input         io_in_c_valid,
  input  [2:0]  io_in_c_bits_opcode,
  input  [2:0]  io_in_c_bits_param,
  input  [3:0]  io_in_c_bits_size,
  input         io_in_c_bits_source,
  input  [30:0] io_in_c_bits_address,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_param,
  input  [3:0]  io_in_d_bits_size,
  input         io_in_d_bits_source,
  input  [1:0]  io_in_d_bits_sink,
  input         io_in_d_bits_denied,
  input         io_in_d_bits_corrupt,
  input         io_in_e_ready,
  input         io_in_e_valid,
  input  [1:0]  io_in_e_bits_sink
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [31:0] _RAND_33;
  reg [31:0] _RAND_34;
  reg [31:0] _RAND_35;
  reg [31:0] _RAND_36;
  reg [31:0] _RAND_37;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = ~io_in_a_bits_source; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | io_in_a_bits_source; // @[Parameters.scala 1125:46]
  wire [26:0] _is_aligned_mask_T_1 = 27'hfff << io_in_a_bits_size; // @[package.scala 234:77]
  wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1[11:0]; // @[package.scala 234:46]
  wire [30:0] _GEN_86 = {{19'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [30:0] _is_aligned_T = io_in_a_bits_address & _GEN_86; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 31'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 4'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire [31:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
  wire  _T_24 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire  _T_26 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42]
  wire  _T_31 = _T_26 & source_ok; // @[Parameters.scala 1160:30]
  wire [31:0] _T_37 = $signed(_T_7) & -32'sh10001000; // @[Parameters.scala 137:52]
  wire  _T_38 = $signed(_T_37) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_39 = io_in_a_bits_address ^ 31'h3000; // @[Parameters.scala 137:31]
  wire [31:0] _T_40 = {1'b0,$signed(_T_39)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_42 = $signed(_T_40) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _T_43 = $signed(_T_42) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_44 = io_in_a_bits_address ^ 31'h10000; // @[Parameters.scala 137:31]
  wire [31:0] _T_45 = {1'b0,$signed(_T_44)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_47 = $signed(_T_45) & -32'sh10000; // @[Parameters.scala 137:52]
  wire  _T_48 = $signed(_T_47) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_49 = io_in_a_bits_address ^ 31'h2000000; // @[Parameters.scala 137:31]
  wire [31:0] _T_50 = {1'b0,$signed(_T_49)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_52 = $signed(_T_50) & -32'sh10000; // @[Parameters.scala 137:52]
  wire  _T_53 = $signed(_T_52) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_54 = io_in_a_bits_address ^ 31'h8000000; // @[Parameters.scala 137:31]
  wire [31:0] _T_55 = {1'b0,$signed(_T_54)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_57 = $signed(_T_55) & -32'sh4000; // @[Parameters.scala 137:52]
  wire  _T_58 = $signed(_T_57) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_59 = io_in_a_bits_address ^ 31'hc000000; // @[Parameters.scala 137:31]
  wire [31:0] _T_60 = {1'b0,$signed(_T_59)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_62 = $signed(_T_60) & -32'sh4000000; // @[Parameters.scala 137:52]
  wire  _T_63 = $signed(_T_62) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_64 = io_in_a_bits_address ^ 31'h10012000; // @[Parameters.scala 137:31]
  wire [31:0] _T_65 = {1'b0,$signed(_T_64)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_67 = $signed(_T_65) & -32'sh2000; // @[Parameters.scala 137:52]
  wire  _T_68 = $signed(_T_67) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_69 = io_in_a_bits_address ^ 31'h10014000; // @[Parameters.scala 137:31]
  wire [31:0] _T_70 = {1'b0,$signed(_T_69)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_72 = $signed(_T_70) & -32'sh2000; // @[Parameters.scala 137:52]
  wire  _T_73 = $signed(_T_72) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_74 = io_in_a_bits_address ^ 31'h10016000; // @[Parameters.scala 137:31]
  wire [31:0] _T_75 = {1'b0,$signed(_T_74)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_77 = $signed(_T_75) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _T_78 = $signed(_T_77) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_79 = io_in_a_bits_address ^ 31'h10023000; // @[Parameters.scala 137:31]
  wire [31:0] _T_80 = {1'b0,$signed(_T_79)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_82 = $signed(_T_80) & -32'sh11000; // @[Parameters.scala 137:52]
  wire  _T_83 = $signed(_T_82) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_84 = io_in_a_bits_address ^ 31'h10024000; // @[Parameters.scala 137:31]
  wire [31:0] _T_85 = {1'b0,$signed(_T_84)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_87 = $signed(_T_85) & -32'sh12000; // @[Parameters.scala 137:52]
  wire  _T_88 = $signed(_T_87) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_89 = io_in_a_bits_address ^ 31'h10026000; // @[Parameters.scala 137:31]
  wire [31:0] _T_90 = {1'b0,$signed(_T_89)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_92 = $signed(_T_90) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _T_93 = $signed(_T_92) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_94 = io_in_a_bits_address ^ 31'h10043000; // @[Parameters.scala 137:31]
  wire [31:0] _T_95 = {1'b0,$signed(_T_94)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_97 = $signed(_T_95) & -32'sh11000; // @[Parameters.scala 137:52]
  wire  _T_98 = $signed(_T_97) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_99 = io_in_a_bits_address ^ 31'h20000000; // @[Parameters.scala 137:31]
  wire [31:0] _T_100 = {1'b0,$signed(_T_99)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_102 = $signed(_T_100) & -32'sh20000000; // @[Parameters.scala 137:52]
  wire  _T_103 = $signed(_T_102) == 32'sh0; // @[Parameters.scala 137:67]
  wire  _T_119 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42]
  wire [30:0] _T_122 = io_in_a_bits_address ^ 31'h40000000; // @[Parameters.scala 137:31]
  wire [31:0] _T_123 = {1'b0,$signed(_T_122)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_125 = $signed(_T_123) & -32'sh20000000; // @[Parameters.scala 137:52]
  wire  _T_126 = $signed(_T_125) == 32'sh0; // @[Parameters.scala 137:67]
  wire  _T_127 = _T_119 & _T_126; // @[Parameters.scala 670:56]
  wire  _T_130 = _T_31 & _T_127; // @[Monitor.scala 82:72]
  wire  _T_136 = 4'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_137 = _source_ok_T & _T_136; // @[Mux.scala 27:73]
  wire  _T_232 = _T_38 | _T_43 | _T_48 | _T_53 | _T_58 | _T_63 | _T_68 | _T_73 | _T_78 | _T_83 | _T_88 | _T_93 | _T_98
     | _T_103 | _T_126; // @[Parameters.scala 671:42]
  wire  _T_233 = _T_26 & _T_232; // @[Parameters.scala 670:56]
  wire  _T_235 = _T_137 & _T_233; // @[Monitor.scala 83:78]
  wire  _T_249 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_253 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_254 = _T_253 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_262 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_491 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_504 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_525 = _T_26 & _T_43; // @[Parameters.scala 670:56]
  wire  _T_612 = _T_38 | _T_48 | _T_53 | _T_58 | _T_63 | _T_68 | _T_73 | _T_78 | _T_83 | _T_88 | _T_93 | _T_98 | _T_103
     | _T_126; // @[Parameters.scala 671:42]
  wire  _T_613 = _T_119 & _T_612; // @[Parameters.scala 670:56]
  wire  _T_615 = _T_525 | _T_613; // @[Parameters.scala 672:30]
  wire  _T_625 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_629 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_637 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_729 = _T_38 | _T_53 | _T_58 | _T_63 | _T_68 | _T_73 | _T_78 | _T_83 | _T_88 | _T_93 | _T_98; // @[Parameters.scala 671:42]
  wire  _T_730 = _T_38 | _T_53 | _T_58 | _T_63 | _T_68 | _T_73 | _T_78 | _T_83 | _T_88 | _T_93 | _T_98 | _T_126; // @[Parameters.scala 671:42]
  wire  _T_731 = _T_119 & _T_730; // @[Parameters.scala 670:56]
  wire  _T_746 = _T_525 | _T_731; // @[Parameters.scala 672:30]
  wire  _T_748 = _T_31 & _T_746; // @[Monitor.scala 115:71]
  wire  _T_766 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire  _T_854 = _T_119 & _T_729; // @[Parameters.scala 670:56]
  wire  _T_875 = _T_525 | _T_854; // @[Parameters.scala 672:30]
  wire  _T_877 = _T_31 & _T_875; // @[Monitor.scala 123:74]
  wire [3:0] _T_891 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_892 = io_in_a_bits_mask & _T_891; // @[Monitor.scala 127:31]
  wire  _T_893 = _T_892 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_897 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_907 = io_in_a_bits_size <= 4'h2; // @[Parameters.scala 92:42]
  wire  _T_980 = _T_38 | _T_43 | _T_53 | _T_58 | _T_63 | _T_68 | _T_73 | _T_78 | _T_83 | _T_88 | _T_93 | _T_98; // @[Parameters.scala 671:42]
  wire  _T_981 = _T_907 & _T_980; // @[Parameters.scala 670:56]
  wire  _T_1003 = _T_31 & _T_981; // @[Monitor.scala 131:74]
  wire  _T_1013 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_1021 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_1137 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_1145 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_1251 = _T_31 & _T_525; // @[Monitor.scala 147:68]
  wire  _T_1261 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_1273 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_2 = ~io_in_d_bits_source; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_2 | io_in_d_bits_source; // @[Parameters.scala 1125:46]
  wire  _T_1277 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_1281 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 312:27]
  wire  _T_1285 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
  wire  _T_1289 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
  wire  _T_1293 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
  wire  _T_1297 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_1308 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
  wire  _T_1312 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
  wire  _T_1325 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_1345 = _T_1293 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
  wire  _T_1354 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_1371 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_1389 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _T_1406 = io_in_b_bits_opcode <= 3'h6; // @[Bundles.scala 40:24]
  wire  _T_1410 = ~io_in_b_bits_source; // @[Parameters.scala 46:9]
  wire [31:0] _T_1413 = {1'b0,$signed(io_in_b_bits_address)}; // @[Parameters.scala 137:49]
  wire [30:0] _address_ok_T = io_in_b_bits_address ^ 31'h3000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_1 = {1'b0,$signed(_address_ok_T)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_3 = $signed(_address_ok_T_1) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_4 = $signed(_address_ok_T_3) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_5 = io_in_b_bits_address ^ 31'h10013000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_6 = {1'b0,$signed(_address_ok_T_5)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_8 = $signed(_address_ok_T_6) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_9 = $signed(_address_ok_T_8) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_10 = io_in_b_bits_address ^ 31'h10023000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_11 = {1'b0,$signed(_address_ok_T_10)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_13 = $signed(_address_ok_T_11) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_14 = $signed(_address_ok_T_13) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_15 = io_in_b_bits_address ^ 31'h10033000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_16 = {1'b0,$signed(_address_ok_T_15)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_18 = $signed(_address_ok_T_16) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_19 = $signed(_address_ok_T_18) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_20 = io_in_b_bits_address ^ 31'h10043000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_21 = {1'b0,$signed(_address_ok_T_20)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_23 = $signed(_address_ok_T_21) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_24 = $signed(_address_ok_T_23) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_25 = io_in_b_bits_address ^ 31'h10053000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_26 = {1'b0,$signed(_address_ok_T_25)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_28 = $signed(_address_ok_T_26) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_29 = $signed(_address_ok_T_28) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_30 = io_in_b_bits_address ^ 31'h10014000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_31 = {1'b0,$signed(_address_ok_T_30)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_33 = $signed(_address_ok_T_31) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_34 = $signed(_address_ok_T_33) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_35 = io_in_b_bits_address ^ 31'h20000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_36 = {1'b0,$signed(_address_ok_T_35)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_38 = $signed(_address_ok_T_36) & -32'sh20000000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_39 = $signed(_address_ok_T_38) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_40 = io_in_b_bits_address ^ 31'h10034000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_41 = {1'b0,$signed(_address_ok_T_40)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_43 = $signed(_address_ok_T_41) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_44 = $signed(_address_ok_T_43) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_45 = io_in_b_bits_address ^ 31'h10024000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_46 = {1'b0,$signed(_address_ok_T_45)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_48 = $signed(_address_ok_T_46) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_49 = $signed(_address_ok_T_48) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_50 = io_in_b_bits_address ^ 31'h10012000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_51 = {1'b0,$signed(_address_ok_T_50)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_53 = $signed(_address_ok_T_51) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_54 = $signed(_address_ok_T_53) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_55 = io_in_b_bits_address ^ 31'h10015000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_56 = {1'b0,$signed(_address_ok_T_55)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_58 = $signed(_address_ok_T_56) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_59 = $signed(_address_ok_T_58) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_60 = io_in_b_bits_address ^ 31'h10025000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_61 = {1'b0,$signed(_address_ok_T_60)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_63 = $signed(_address_ok_T_61) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_64 = $signed(_address_ok_T_63) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_65 = io_in_b_bits_address ^ 31'h10035000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_66 = {1'b0,$signed(_address_ok_T_65)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_68 = $signed(_address_ok_T_66) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_69 = $signed(_address_ok_T_68) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_70 = io_in_b_bits_address ^ 31'h10016000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_71 = {1'b0,$signed(_address_ok_T_70)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_73 = $signed(_address_ok_T_71) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_74 = $signed(_address_ok_T_73) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_75 = io_in_b_bits_address ^ 31'h10026000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_76 = {1'b0,$signed(_address_ok_T_75)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_78 = $signed(_address_ok_T_76) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_79 = $signed(_address_ok_T_78) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_80 = io_in_b_bits_address ^ 31'hc000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_81 = {1'b0,$signed(_address_ok_T_80)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_83 = $signed(_address_ok_T_81) & -32'sh4000000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_84 = $signed(_address_ok_T_83) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_85 = io_in_b_bits_address ^ 31'h2000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_86 = {1'b0,$signed(_address_ok_T_85)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_88 = $signed(_address_ok_T_86) & -32'sh10000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_89 = $signed(_address_ok_T_88) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _address_ok_T_93 = $signed(_T_1413) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_94 = $signed(_address_ok_T_93) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_95 = io_in_b_bits_address ^ 31'h8000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_96 = {1'b0,$signed(_address_ok_T_95)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_98 = $signed(_address_ok_T_96) & -32'sh4000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_99 = $signed(_address_ok_T_98) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_100 = io_in_b_bits_address ^ 31'h10000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_101 = {1'b0,$signed(_address_ok_T_100)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_103 = $signed(_address_ok_T_101) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_104 = $signed(_address_ok_T_103) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_105 = io_in_b_bits_address ^ 31'h10000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_106 = {1'b0,$signed(_address_ok_T_105)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_108 = $signed(_address_ok_T_106) & -32'sh10000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_109 = $signed(_address_ok_T_108) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_110 = io_in_b_bits_address ^ 31'h40000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_111 = {1'b0,$signed(_address_ok_T_110)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_113 = $signed(_address_ok_T_111) & -32'sh20000000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_114 = $signed(_address_ok_T_113) == 32'sh0; // @[Parameters.scala 137:67]
  wire  address_ok = _address_ok_T_4 | _address_ok_T_9 | _address_ok_T_14 | _address_ok_T_19 | _address_ok_T_24 |
    _address_ok_T_29 | _address_ok_T_34 | _address_ok_T_39 | _address_ok_T_44 | _address_ok_T_49 | _address_ok_T_54 |
    _address_ok_T_59 | _address_ok_T_64 | _address_ok_T_69 | _address_ok_T_74 | _address_ok_T_79 | _address_ok_T_84 |
    _address_ok_T_89 | _address_ok_T_94 | _address_ok_T_99 | _address_ok_T_104 | _address_ok_T_109 | _address_ok_T_114; // @[Parameters.scala 622:64]
  wire [26:0] _is_aligned_mask_T_4 = 27'hfff << io_in_b_bits_size; // @[package.scala 234:77]
  wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_4[11:0]; // @[package.scala 234:46]
  wire [30:0] _GEN_87 = {{19'd0}, is_aligned_mask_1}; // @[Edges.scala 20:16]
  wire [30:0] _is_aligned_T_1 = io_in_b_bits_address & _GEN_87; // @[Edges.scala 20:16]
  wire  is_aligned_1 = _is_aligned_T_1 == 31'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount_1 = io_in_b_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_4 = 2'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH_1 = _mask_sizeOH_T_4 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T_1 = io_in_b_bits_size >= 4'h2; // @[Misc.scala 205:21]
  wire  mask_size_2 = mask_sizeOH_1[1]; // @[Misc.scala 208:26]
  wire  mask_bit_2 = io_in_b_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
  wire  mask_acc_6 = _mask_T_1 | mask_size_2 & mask_nbit_2; // @[Misc.scala 214:29]
  wire  mask_acc_7 = _mask_T_1 | mask_size_2 & mask_bit_2; // @[Misc.scala 214:29]
  wire  mask_size_3 = mask_sizeOH_1[0]; // @[Misc.scala 208:26]
  wire  mask_bit_3 = io_in_b_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_3 = ~mask_bit_3; // @[Misc.scala 210:20]
  wire  mask_eq_8 = mask_nbit_2 & mask_nbit_3; // @[Misc.scala 213:27]
  wire  mask_acc_8 = mask_acc_6 | mask_size_3 & mask_eq_8; // @[Misc.scala 214:29]
  wire  mask_eq_9 = mask_nbit_2 & mask_bit_3; // @[Misc.scala 213:27]
  wire  mask_acc_9 = mask_acc_6 | mask_size_3 & mask_eq_9; // @[Misc.scala 214:29]
  wire  mask_eq_10 = mask_bit_2 & mask_nbit_3; // @[Misc.scala 213:27]
  wire  mask_acc_10 = mask_acc_7 | mask_size_3 & mask_eq_10; // @[Misc.scala 214:29]
  wire  mask_eq_11 = mask_bit_2 & mask_bit_3; // @[Misc.scala 213:27]
  wire  mask_acc_11 = mask_acc_7 | mask_size_3 & mask_eq_11; // @[Misc.scala 214:29]
  wire [3:0] mask_1 = {mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8}; // @[Cat.scala 31:58]
  wire  _T_1430 = io_in_b_bits_opcode == 3'h6; // @[Monitor.scala 167:25]
  wire  _T_1433 = 4'h6 == io_in_b_bits_size; // @[Parameters.scala 91:48]
  wire  _T_1434 = _T_1410 & _T_1433; // @[Mux.scala 27:73]
  wire  _T_1438 = io_in_b_bits_size <= 4'hc; // @[Parameters.scala 92:42]
  wire [31:0] _T_1444 = $signed(_T_1413) & -32'sh10001000; // @[Parameters.scala 137:52]
  wire  _T_1445 = $signed(_T_1444) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_1474 = $signed(_address_ok_T_51) & -32'sh2000; // @[Parameters.scala 137:52]
  wire  _T_1475 = $signed(_T_1474) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_1479 = $signed(_address_ok_T_31) & -32'sh2000; // @[Parameters.scala 137:52]
  wire  _T_1480 = $signed(_T_1479) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_1489 = $signed(_address_ok_T_11) & -32'sh11000; // @[Parameters.scala 137:52]
  wire  _T_1490 = $signed(_T_1489) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_1494 = $signed(_address_ok_T_46) & -32'sh12000; // @[Parameters.scala 137:52]
  wire  _T_1495 = $signed(_T_1494) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_1504 = $signed(_address_ok_T_21) & -32'sh11000; // @[Parameters.scala 137:52]
  wire  _T_1505 = $signed(_T_1504) == 32'sh0; // @[Parameters.scala 137:67]
  wire  _T_1529 = _T_1445 | _address_ok_T_4 | _address_ok_T_109 | _address_ok_T_89 | _address_ok_T_99 | _address_ok_T_84
     | _T_1475 | _T_1480 | _address_ok_T_74 | _T_1490 | _T_1495 | _address_ok_T_79 | _T_1505 | _address_ok_T_39 |
    _address_ok_T_114; // @[Parameters.scala 671:42]
  wire  _T_1530 = _T_1438 & _T_1529; // @[Parameters.scala 670:56]
  wire  _T_1532 = _T_1434 & _T_1530; // @[Monitor.scala 168:75]
  wire  _T_1538 = ~address_ok; // @[Monitor.scala 49:11]
  wire  _T_1544 = ~is_aligned_1; // @[Monitor.scala 49:11]
  wire  _T_1545 = io_in_b_bits_param <= 2'h2; // @[Bundles.scala 102:26]
  wire  _T_1549 = io_in_b_bits_mask == mask_1; // @[Monitor.scala 173:27]
  wire  _T_1552 = ~_T_1549; // @[Monitor.scala 49:11]
  wire  _T_1553 = ~io_in_b_bits_corrupt; // @[Monitor.scala 174:15]
  wire  _T_1556 = ~_T_1553; // @[Monitor.scala 49:11]
  wire  _T_1557 = io_in_b_bits_opcode == 3'h4; // @[Monitor.scala 177:25]
  wire  _T_1666 = io_in_b_bits_param == 2'h0; // @[Monitor.scala 182:31]
  wire  _T_1678 = io_in_b_bits_opcode == 3'h0; // @[Monitor.scala 187:25]
  wire  _T_1795 = io_in_b_bits_opcode == 3'h1; // @[Monitor.scala 196:25]
  wire [3:0] _T_1908 = ~mask_1; // @[Monitor.scala 202:33]
  wire [3:0] _T_1909 = io_in_b_bits_mask & _T_1908; // @[Monitor.scala 202:31]
  wire  _T_1910 = _T_1909 == 4'h0; // @[Monitor.scala 202:40]
  wire  _T_1914 = io_in_b_bits_opcode == 3'h2; // @[Monitor.scala 205:25]
  wire  _T_2031 = io_in_b_bits_opcode == 3'h3; // @[Monitor.scala 214:25]
  wire  _T_2148 = io_in_b_bits_opcode == 3'h5; // @[Monitor.scala 223:25]
  wire  _source_ok_T_4 = ~io_in_c_bits_source; // @[Parameters.scala 46:9]
  wire  source_ok_2 = _source_ok_T_4 | io_in_c_bits_source; // @[Parameters.scala 1125:46]
  wire [26:0] _is_aligned_mask_T_7 = 27'hfff << io_in_c_bits_size; // @[package.scala 234:77]
  wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_7[11:0]; // @[package.scala 234:46]
  wire [30:0] _GEN_88 = {{19'd0}, is_aligned_mask_2}; // @[Edges.scala 20:16]
  wire [30:0] _is_aligned_T_2 = io_in_c_bits_address & _GEN_88; // @[Edges.scala 20:16]
  wire  is_aligned_2 = _is_aligned_T_2 == 31'h0; // @[Edges.scala 20:24]
  wire [30:0] _address_ok_T_136 = io_in_c_bits_address ^ 31'h3000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_137 = {1'b0,$signed(_address_ok_T_136)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_139 = $signed(_address_ok_T_137) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_140 = $signed(_address_ok_T_139) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_141 = io_in_c_bits_address ^ 31'h10013000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_142 = {1'b0,$signed(_address_ok_T_141)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_144 = $signed(_address_ok_T_142) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_145 = $signed(_address_ok_T_144) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_146 = io_in_c_bits_address ^ 31'h10023000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_147 = {1'b0,$signed(_address_ok_T_146)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_149 = $signed(_address_ok_T_147) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_150 = $signed(_address_ok_T_149) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_151 = io_in_c_bits_address ^ 31'h10033000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_152 = {1'b0,$signed(_address_ok_T_151)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_154 = $signed(_address_ok_T_152) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_155 = $signed(_address_ok_T_154) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_156 = io_in_c_bits_address ^ 31'h10043000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_157 = {1'b0,$signed(_address_ok_T_156)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_159 = $signed(_address_ok_T_157) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_160 = $signed(_address_ok_T_159) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_161 = io_in_c_bits_address ^ 31'h10053000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_162 = {1'b0,$signed(_address_ok_T_161)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_164 = $signed(_address_ok_T_162) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_165 = $signed(_address_ok_T_164) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_166 = io_in_c_bits_address ^ 31'h10014000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_167 = {1'b0,$signed(_address_ok_T_166)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_169 = $signed(_address_ok_T_167) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_170 = $signed(_address_ok_T_169) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_171 = io_in_c_bits_address ^ 31'h20000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_172 = {1'b0,$signed(_address_ok_T_171)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_174 = $signed(_address_ok_T_172) & -32'sh20000000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_175 = $signed(_address_ok_T_174) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_176 = io_in_c_bits_address ^ 31'h10034000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_177 = {1'b0,$signed(_address_ok_T_176)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_179 = $signed(_address_ok_T_177) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_180 = $signed(_address_ok_T_179) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_181 = io_in_c_bits_address ^ 31'h10024000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_182 = {1'b0,$signed(_address_ok_T_181)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_184 = $signed(_address_ok_T_182) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_185 = $signed(_address_ok_T_184) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_186 = io_in_c_bits_address ^ 31'h10012000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_187 = {1'b0,$signed(_address_ok_T_186)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_189 = $signed(_address_ok_T_187) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_190 = $signed(_address_ok_T_189) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_191 = io_in_c_bits_address ^ 31'h10015000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_192 = {1'b0,$signed(_address_ok_T_191)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_194 = $signed(_address_ok_T_192) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_195 = $signed(_address_ok_T_194) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_196 = io_in_c_bits_address ^ 31'h10025000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_197 = {1'b0,$signed(_address_ok_T_196)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_199 = $signed(_address_ok_T_197) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_200 = $signed(_address_ok_T_199) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_201 = io_in_c_bits_address ^ 31'h10035000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_202 = {1'b0,$signed(_address_ok_T_201)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_204 = $signed(_address_ok_T_202) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_205 = $signed(_address_ok_T_204) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_206 = io_in_c_bits_address ^ 31'h10016000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_207 = {1'b0,$signed(_address_ok_T_206)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_209 = $signed(_address_ok_T_207) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_210 = $signed(_address_ok_T_209) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_211 = io_in_c_bits_address ^ 31'h10026000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_212 = {1'b0,$signed(_address_ok_T_211)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_214 = $signed(_address_ok_T_212) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_215 = $signed(_address_ok_T_214) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_216 = io_in_c_bits_address ^ 31'hc000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_217 = {1'b0,$signed(_address_ok_T_216)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_219 = $signed(_address_ok_T_217) & -32'sh4000000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_220 = $signed(_address_ok_T_219) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_221 = io_in_c_bits_address ^ 31'h2000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_222 = {1'b0,$signed(_address_ok_T_221)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_224 = $signed(_address_ok_T_222) & -32'sh10000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_225 = $signed(_address_ok_T_224) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _address_ok_T_227 = {1'b0,$signed(io_in_c_bits_address)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_229 = $signed(_address_ok_T_227) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_230 = $signed(_address_ok_T_229) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_231 = io_in_c_bits_address ^ 31'h8000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_232 = {1'b0,$signed(_address_ok_T_231)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_234 = $signed(_address_ok_T_232) & -32'sh4000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_235 = $signed(_address_ok_T_234) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_236 = io_in_c_bits_address ^ 31'h10000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_237 = {1'b0,$signed(_address_ok_T_236)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_239 = $signed(_address_ok_T_237) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_240 = $signed(_address_ok_T_239) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_241 = io_in_c_bits_address ^ 31'h10000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_242 = {1'b0,$signed(_address_ok_T_241)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_244 = $signed(_address_ok_T_242) & -32'sh10000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_245 = $signed(_address_ok_T_244) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_246 = io_in_c_bits_address ^ 31'h40000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_247 = {1'b0,$signed(_address_ok_T_246)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_249 = $signed(_address_ok_T_247) & -32'sh20000000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_250 = $signed(_address_ok_T_249) == 32'sh0; // @[Parameters.scala 137:67]
  wire  address_ok_1 = _address_ok_T_140 | _address_ok_T_145 | _address_ok_T_150 | _address_ok_T_155 | _address_ok_T_160
     | _address_ok_T_165 | _address_ok_T_170 | _address_ok_T_175 | _address_ok_T_180 | _address_ok_T_185 |
    _address_ok_T_190 | _address_ok_T_195 | _address_ok_T_200 | _address_ok_T_205 | _address_ok_T_210 |
    _address_ok_T_215 | _address_ok_T_220 | _address_ok_T_225 | _address_ok_T_230 | _address_ok_T_235 |
    _address_ok_T_240 | _address_ok_T_245 | _address_ok_T_250; // @[Parameters.scala 622:64]
  wire  _T_2289 = io_in_c_bits_opcode == 3'h4; // @[Monitor.scala 242:25]
  wire  _T_2296 = io_in_c_bits_size >= 4'h2; // @[Monitor.scala 245:30]
  wire  _T_2303 = io_in_c_bits_param <= 3'h5; // @[Bundles.scala 120:29]
  wire  _T_2311 = io_in_c_bits_opcode == 3'h5; // @[Monitor.scala 251:25]
  wire  _T_2329 = io_in_c_bits_opcode == 3'h6; // @[Monitor.scala 259:25]
  wire  _T_2331 = io_in_c_bits_size <= 4'hc; // @[Parameters.scala 92:42]
  wire  _T_2336 = _T_2331 & source_ok_2; // @[Parameters.scala 1160:30]
  wire [31:0] _T_2342 = $signed(_address_ok_T_227) & -32'sh10001000; // @[Parameters.scala 137:52]
  wire  _T_2343 = $signed(_T_2342) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_2372 = $signed(_address_ok_T_187) & -32'sh2000; // @[Parameters.scala 137:52]
  wire  _T_2373 = $signed(_T_2372) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_2377 = $signed(_address_ok_T_167) & -32'sh2000; // @[Parameters.scala 137:52]
  wire  _T_2378 = $signed(_T_2377) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_2387 = $signed(_address_ok_T_147) & -32'sh11000; // @[Parameters.scala 137:52]
  wire  _T_2388 = $signed(_T_2387) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_2392 = $signed(_address_ok_T_182) & -32'sh12000; // @[Parameters.scala 137:52]
  wire  _T_2393 = $signed(_T_2392) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_2402 = $signed(_address_ok_T_157) & -32'sh11000; // @[Parameters.scala 137:52]
  wire  _T_2403 = $signed(_T_2402) == 32'sh0; // @[Parameters.scala 137:67]
  wire  _T_2424 = io_in_c_bits_size <= 4'h6; // @[Parameters.scala 92:42]
  wire  _T_2432 = _T_2424 & _address_ok_T_250; // @[Parameters.scala 670:56]
  wire  _T_2435 = _T_2336 & _T_2432; // @[Monitor.scala 260:78]
  wire  _T_2441 = 4'h6 == io_in_c_bits_size; // @[Parameters.scala 91:48]
  wire  _T_2442 = _source_ok_T_4 & _T_2441; // @[Mux.scala 27:73]
  wire  _T_2537 = _T_2343 | _address_ok_T_140 | _address_ok_T_245 | _address_ok_T_225 | _address_ok_T_235 |
    _address_ok_T_220 | _T_2373 | _T_2378 | _address_ok_T_210 | _T_2388 | _T_2393 | _address_ok_T_215 | _T_2403 |
    _address_ok_T_175 | _address_ok_T_250; // @[Parameters.scala 671:42]
  wire  _T_2538 = _T_2331 & _T_2537; // @[Parameters.scala 670:56]
  wire  _T_2540 = _T_2442 & _T_2538; // @[Monitor.scala 261:78]
  wire  _T_2562 = io_in_c_bits_opcode == 3'h7; // @[Monitor.scala 269:25]
  wire  _T_2791 = io_in_c_bits_opcode == 3'h0; // @[Monitor.scala 278:25]
  wire  _T_2801 = io_in_c_bits_param == 3'h0; // @[Monitor.scala 282:31]
  wire  _T_2809 = io_in_c_bits_opcode == 3'h1; // @[Monitor.scala 286:25]
  wire  _T_2823 = io_in_c_bits_opcode == 3'h2; // @[Monitor.scala 293:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [9:0] a_first_beats1_decode = is_aligned_mask[11:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [9:0] a_first_counter; // @[Edges.scala 228:27]
  wire [9:0] a_first_counter1 = a_first_counter - 10'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 10'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [3:0] size; // @[Monitor.scala 386:22]
  reg  source; // @[Monitor.scala 387:22]
  reg [30:0] address; // @[Monitor.scala 388:22]
  wire  _T_2845 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_2846 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_2850 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_2854 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_2858 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_2862 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [26:0] _d_first_beats1_decode_T_1 = 27'hfff << io_in_d_bits_size; // @[package.scala 234:77]
  wire [11:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
  wire [9:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[11:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [9:0] d_first_counter; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1 = d_first_counter - 10'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 10'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] param_1; // @[Monitor.scala 536:22]
  reg [3:0] size_1; // @[Monitor.scala 537:22]
  reg  source_1; // @[Monitor.scala 538:22]
  reg [1:0] sink; // @[Monitor.scala 539:22]
  reg  denied; // @[Monitor.scala 540:22]
  wire  _T_2869 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_2870 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_2874 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
  wire  _T_2878 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_2882 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  wire  _T_2886 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
  wire  _T_2890 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
  wire  b_first_done = io_in_b_ready & io_in_b_valid; // @[Decoupled.scala 50:35]
  reg [9:0] b_first_counter; // @[Edges.scala 228:27]
  wire [9:0] b_first_counter1 = b_first_counter - 10'h1; // @[Edges.scala 229:28]
  wire  b_first = b_first_counter == 10'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_2; // @[Monitor.scala 407:22]
  reg [1:0] param_2; // @[Monitor.scala 408:22]
  reg [3:0] size_2; // @[Monitor.scala 409:22]
  reg  source_2; // @[Monitor.scala 410:22]
  reg [30:0] address_1; // @[Monitor.scala 411:22]
  wire  _T_2897 = io_in_b_valid & ~b_first; // @[Monitor.scala 412:19]
  wire  _T_2898 = io_in_b_bits_opcode == opcode_2; // @[Monitor.scala 413:32]
  wire  _T_2902 = io_in_b_bits_param == param_2; // @[Monitor.scala 414:32]
  wire  _T_2906 = io_in_b_bits_size == size_2; // @[Monitor.scala 415:32]
  wire  _T_2910 = io_in_b_bits_source == source_2; // @[Monitor.scala 416:32]
  wire  _T_2914 = io_in_b_bits_address == address_1; // @[Monitor.scala 417:32]
  wire  _c_first_T = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala 50:35]
  wire [9:0] c_first_beats1_decode = is_aligned_mask_2[11:2]; // @[Edges.scala 219:59]
  wire  c_first_beats1_opdata = io_in_c_bits_opcode[0]; // @[Edges.scala 101:36]
  reg [9:0] c_first_counter; // @[Edges.scala 228:27]
  wire [9:0] c_first_counter1 = c_first_counter - 10'h1; // @[Edges.scala 229:28]
  wire  c_first = c_first_counter == 10'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_3; // @[Monitor.scala 512:22]
  reg [2:0] param_3; // @[Monitor.scala 513:22]
  reg [3:0] size_3; // @[Monitor.scala 514:22]
  reg  source_3; // @[Monitor.scala 515:22]
  reg [30:0] address_2; // @[Monitor.scala 516:22]
  wire  _T_2921 = io_in_c_valid & ~c_first; // @[Monitor.scala 517:19]
  wire  _T_2922 = io_in_c_bits_opcode == opcode_3; // @[Monitor.scala 518:32]
  wire  _T_2926 = io_in_c_bits_param == param_3; // @[Monitor.scala 519:32]
  wire  _T_2930 = io_in_c_bits_size == size_3; // @[Monitor.scala 520:32]
  wire  _T_2934 = io_in_c_bits_source == source_3; // @[Monitor.scala 521:32]
  wire  _T_2938 = io_in_c_bits_address == address_2; // @[Monitor.scala 522:32]
  reg [1:0] inflight; // @[Monitor.scala 611:27]
  reg [7:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [15:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [9:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [9:0] a_first_counter1_1 = a_first_counter_1 - 10'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 10'h0; // @[Edges.scala 230:25]
  reg [9:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1_1 = d_first_counter_1 - 10'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 10'h0; // @[Edges.scala 230:25]
  wire [2:0] _GEN_89 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [3:0] _a_opcode_lookup_T = {{1'd0}, _GEN_89}; // @[Monitor.scala 634:69]
  wire [7:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_90 = {{8'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_90 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [3:0] _a_size_lookup_T = {io_in_d_bits_source, 3'h0}; // @[Monitor.scala 638:65]
  wire [15:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _a_size_lookup_T_5 = 16'h100 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _a_size_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_2944 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [1:0] _a_set_wo_ready_T = 2'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [1:0] a_set_wo_ready = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 2'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_2947 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [4:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 5'h1; // @[Monitor.scala 655:59]
  wire [2:0] _GEN_93 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [3:0] _a_opcodes_set_T = {{1'd0}, _GEN_93}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [18:0] _GEN_1 = {{15'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [18:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [3:0] _a_sizes_set_T = {io_in_a_bits_source, 3'h0}; // @[Monitor.scala 657:77]
  wire [4:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala 652:72 655:28]
  wire [19:0] _GEN_2 = {{15'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [19:0] _a_sizes_set_T_1 = _GEN_2 << _a_sizes_set_T; // @[Monitor.scala 657:52]
  wire [1:0] _T_2949 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_2951 = ~_T_2949[0]; // @[Monitor.scala 658:17]
  wire [1:0] a_set = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 2'h0; // @[Monitor.scala 652:72 653:28]
  wire [18:0] _GEN_31 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 656:28]
  wire [19:0] _GEN_32 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 20'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_2955 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_2957 = ~_T_1277; // @[Monitor.scala 671:74]
  wire  _T_2958 = io_in_d_valid & d_first_1 & ~_T_1277; // @[Monitor.scala 671:71]
  wire [1:0] _d_clr_wo_ready_T = 2'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [1:0] d_clr_wo_ready = io_in_d_valid & d_first_1 & ~_T_1277 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 671:90 672:22]
  wire [30:0] _GEN_3 = {{15'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [30:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [30:0] _GEN_4 = {{15'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 678:74]
  wire [30:0] _d_sizes_clr_T_5 = _GEN_4 << _a_size_lookup_T; // @[Monitor.scala 678:74]
  wire [1:0] d_clr = _d_first_T & d_first_1 & _T_2957 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 675:91 676:21]
  wire [30:0] _GEN_35 = _d_first_T & d_first_1 & _T_2957 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 677:21]
  wire [30:0] _GEN_36 = _d_first_T & d_first_1 & _T_2957 ? _d_sizes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 678:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_2944 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [1:0] _T_2968 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_2970 = _T_2968[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_39 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_40 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_39; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_41 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_40; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_42 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_41; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_43 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_42; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_44 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_43; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_51 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_42; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_52 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_51; // @[Monitor.scala 686:{39,39}]
  wire  _T_2975 = io_in_d_bits_opcode == _GEN_52; // @[Monitor.scala 686:39]
  wire  _T_2976 = io_in_d_bits_opcode == _GEN_44 | _T_2975; // @[Monitor.scala 685:77]
  wire  _T_2980 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_55 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_56 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_55; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_57 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_56; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_58 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_57; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_59 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_58; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_60 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_59; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_67 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_58; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_68 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_67; // @[Monitor.scala 690:{38,38}]
  wire  _T_2987 = io_in_d_bits_opcode == _GEN_68; // @[Monitor.scala 690:38]
  wire  _T_2988 = io_in_d_bits_opcode == _GEN_60 | _T_2987; // @[Monitor.scala 689:72]
  wire [7:0] a_size_lookup = _a_size_lookup_T_7[7:0];
  wire [7:0] _GEN_95 = {{4'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_2992 = _GEN_95 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_3002 = _T_2955 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_2957; // @[Monitor.scala 694:116]
  wire  _T_3003 = ~io_in_d_ready; // @[Monitor.scala 695:15]
  wire  _T_3004 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire  _T_3011 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire [1:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [1:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [1:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [7:0] a_opcodes_set = _GEN_31[7:0];
  wire [7:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [7:0] d_opcodes_clr = _GEN_35[7:0];
  wire [7:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [7:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [15:0] a_sizes_set = _GEN_32[15:0];
  wire [15:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [15:0] d_sizes_clr = _GEN_36[15:0];
  wire [15:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala 704:56]
  wire [15:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_3020 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [1:0] inflight_1; // @[Monitor.scala 723:35]
  reg [15:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [9:0] c_first_counter_1; // @[Edges.scala 228:27]
  wire [9:0] c_first_counter1_1 = c_first_counter_1 - 10'h1; // @[Edges.scala 229:28]
  wire  c_first_1 = c_first_counter_1 == 10'h0; // @[Edges.scala 230:25]
  reg [9:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1_2 = d_first_counter_2 - 10'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 10'h0; // @[Edges.scala 230:25]
  wire [15:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_size_lookup_T; // @[Monitor.scala 747:42]
  wire [15:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _a_size_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_3030 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala 67:40]
  wire  _T_3031 = io_in_c_valid & c_first_1 & _T_3030; // @[Monitor.scala 756:37]
  wire [1:0] _c_set_wo_ready_T = 2'h1 << io_in_c_bits_source; // @[OneHot.scala 57:35]
  wire [1:0] c_set_wo_ready = io_in_c_valid & c_first_1 & _T_3030 ? _c_set_wo_ready_T : 2'h0; // @[Monitor.scala 756:71 757:22]
  wire  _T_3037 = _c_first_T & c_first_1 & _T_3030; // @[Monitor.scala 760:38]
  wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size, 1'h0}; // @[Monitor.scala 763:51]
  wire [4:0] _c_sizes_set_interm_T_1 = _c_sizes_set_interm_T | 5'h1; // @[Monitor.scala 763:59]
  wire [3:0] _c_sizes_set_T = {io_in_c_bits_source, 3'h0}; // @[Monitor.scala 765:77]
  wire [4:0] c_sizes_set_interm = _c_first_T & c_first_1 & _T_3030 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala 760:72 763:28]
  wire [19:0] _GEN_5 = {{15'd0}, c_sizes_set_interm}; // @[Monitor.scala 765:52]
  wire [19:0] _c_sizes_set_T_1 = _GEN_5 << _c_sizes_set_T; // @[Monitor.scala 765:52]
  wire [1:0] _T_3038 = inflight_1 >> io_in_c_bits_source; // @[Monitor.scala 766:26]
  wire  _T_3040 = ~_T_3038[0]; // @[Monitor.scala 766:17]
  wire [1:0] c_set = _c_first_T & c_first_1 & _T_3030 ? _c_set_wo_ready_T : 2'h0; // @[Monitor.scala 760:72 761:28]
  wire [19:0] _GEN_77 = _c_first_T & c_first_1 & _T_3030 ? _c_sizes_set_T_1 : 20'h0; // @[Monitor.scala 760:72 765:28]
  wire  _T_3044 = io_in_d_valid & d_first_2; // @[Monitor.scala 779:26]
  wire  _T_3046 = io_in_d_valid & d_first_2 & _T_1277; // @[Monitor.scala 779:71]
  wire [1:0] d_clr_wo_ready_1 = io_in_d_valid & d_first_2 & _T_1277 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 779:89 780:22]
  wire [1:0] d_clr_1 = _d_first_T & d_first_2 & _T_1277 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 783:90 784:21]
  wire [30:0] _GEN_81 = _d_first_T & d_first_2 & _T_1277 ? _d_sizes_clr_T_5 : 31'h0; // @[Monitor.scala 783:90 786:21]
  wire  _same_cycle_resp_T_8 = io_in_c_bits_source == io_in_d_bits_source; // @[Monitor.scala 790:113]
  wire  same_cycle_resp_1 = _T_3031 & io_in_c_bits_source == io_in_d_bits_source; // @[Monitor.scala 790:88]
  wire [1:0] _T_3054 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire  _T_3056 = _T_3054[0] | same_cycle_resp_1; // @[Monitor.scala 791:49]
  wire  _T_3060 = io_in_d_bits_size == io_in_c_bits_size; // @[Monitor.scala 793:36]
  wire [7:0] c_size_lookup = _c_size_lookup_T_7[7:0];
  wire  _T_3064 = _GEN_95 == c_size_lookup; // @[Monitor.scala 795:36]
  wire  _T_3073 = _T_3044 & c_first_1 & io_in_c_valid & _same_cycle_resp_T_8 & _T_1277; // @[Monitor.scala 799:116]
  wire  _T_3075 = _T_3003 | io_in_c_ready; // @[Monitor.scala 800:32]
  wire  _T_3079 = |c_set_wo_ready; // @[Monitor.scala 804:28]
  wire  _T_3080 = c_set_wo_ready != d_clr_wo_ready_1; // @[Monitor.scala 805:31]
  wire [1:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala 809:35]
  wire [1:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [1:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [15:0] c_sizes_set = _GEN_77[15:0];
  wire [15:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala 811:41]
  wire [15:0] d_sizes_clr_1 = _GEN_81[15:0];
  wire [15:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
  wire [15:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_3089 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  reg [3:0] inflight_2; // @[Monitor.scala 823:27]
  reg [9:0] d_first_counter_3; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1_3 = d_first_counter_3 - 10'h1; // @[Edges.scala 229:28]
  wire  d_first_3 = d_first_counter_3 == 10'h0; // @[Edges.scala 230:25]
  wire  _T_3101 = io_in_d_bits_opcode[2] & ~io_in_d_bits_opcode[1]; // @[Edges.scala 70:40]
  wire  _T_3102 = _d_first_T & d_first_3 & _T_3101; // @[Monitor.scala 829:38]
  wire [3:0] _d_set_T = 4'h1 << io_in_d_bits_sink; // @[OneHot.scala 57:35]
  wire [3:0] _T_3103 = inflight_2 >> io_in_d_bits_sink; // @[Monitor.scala 831:23]
  wire  _T_3105 = ~_T_3103[0]; // @[Monitor.scala 831:14]
  wire [3:0] d_set = _d_first_T & d_first_3 & _T_3101 ? _d_set_T : 4'h0; // @[Monitor.scala 829:72 830:13]
  wire  _T_3109 = io_in_e_ready & io_in_e_valid; // @[Decoupled.scala 50:35]
  wire [3:0] _e_clr_T = 4'h1 << io_in_e_bits_sink; // @[OneHot.scala 57:35]
  wire [3:0] _T_3112 = d_set | inflight_2; // @[Monitor.scala 837:24]
  wire [3:0] _T_3113 = _T_3112 >> io_in_e_bits_sink; // @[Monitor.scala 837:35]
  wire [3:0] e_clr = _T_3109 ? _e_clr_T : 4'h0; // @[Monitor.scala 835:73 836:13]
  wire [3:0] _inflight_T_6 = inflight_2 | d_set; // @[Monitor.scala 842:27]
  wire [3:0] _inflight_T_7 = ~e_clr; // @[Monitor.scala 842:38]
  wire [3:0] _inflight_T_8 = _inflight_T_6 & _inflight_T_7; // @[Monitor.scala 842:36]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 10'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 10'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 10'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      b_first_counter <= 10'h0; // @[Edges.scala 228:27]
    end else if (b_first_done) begin // @[Edges.scala 234:17]
      if (b_first) begin // @[Edges.scala 235:21]
        b_first_counter <= 10'h0;
      end else begin
        b_first_counter <= b_first_counter1;
      end
    end
    if (b_first_done & b_first) begin // @[Monitor.scala 419:32]
      opcode_2 <= io_in_b_bits_opcode; // @[Monitor.scala 420:15]
    end
    if (b_first_done & b_first) begin // @[Monitor.scala 419:32]
      param_2 <= io_in_b_bits_param; // @[Monitor.scala 421:15]
    end
    if (b_first_done & b_first) begin // @[Monitor.scala 419:32]
      size_2 <= io_in_b_bits_size; // @[Monitor.scala 422:15]
    end
    if (b_first_done & b_first) begin // @[Monitor.scala 419:32]
      source_2 <= io_in_b_bits_source; // @[Monitor.scala 423:15]
    end
    if (b_first_done & b_first) begin // @[Monitor.scala 419:32]
      address_1 <= io_in_b_bits_address; // @[Monitor.scala 424:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      c_first_counter <= 10'h0; // @[Edges.scala 228:27]
    end else if (_c_first_T) begin // @[Edges.scala 234:17]
      if (c_first) begin // @[Edges.scala 235:21]
        if (c_first_beats1_opdata) begin // @[Edges.scala 220:14]
          c_first_counter <= c_first_beats1_decode;
        end else begin
          c_first_counter <= 10'h0;
        end
      end else begin
        c_first_counter <= c_first_counter1;
      end
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      opcode_3 <= io_in_c_bits_opcode; // @[Monitor.scala 525:15]
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      param_3 <= io_in_c_bits_param; // @[Monitor.scala 526:15]
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      size_3 <= io_in_c_bits_size; // @[Monitor.scala 527:15]
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      source_3 <= io_in_c_bits_source; // @[Monitor.scala 528:15]
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      address_2 <= io_in_c_bits_address; // @[Monitor.scala 529:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 2'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 8'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 16'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 10'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 10'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 2'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 16'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      c_first_counter_1 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_c_first_T) begin // @[Edges.scala 234:17]
      if (c_first_1) begin // @[Edges.scala 235:21]
        if (c_first_beats1_opdata) begin // @[Edges.scala 220:14]
          c_first_counter_1 <= c_first_beats1_decode;
        end else begin
          c_first_counter_1 <= 10'h0;
        end
      end else begin
        c_first_counter_1 <= c_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 10'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_c_first_T | _d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    if (reset) begin // @[Monitor.scala 823:27]
      inflight_2 <= 4'h0; // @[Monitor.scala 823:27]
    end else begin
      inflight_2 <= _inflight_T_8; // @[Monitor.scala 842:14]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_3 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_3) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_3 <= d_first_beats1_decode;
        end else begin
          d_first_counter_3 <= 10'h0;
        end
      end else begin
        d_first_counter_3 <= d_first_counter1_3;
      end
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_130 & (io_in_a_valid & _T_24 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_24 & ~reset & ~_T_130) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_235 & (io_in_a_valid & _T_24 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_24 & ~reset & ~_T_235) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_24 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_24 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_24 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_24 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_24 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_24 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_249 & (io_in_a_valid & _T_24 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_24 & ~reset & ~_T_249) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_254 & (io_in_a_valid & _T_24 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_24 & ~reset & ~_T_254) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_130 & (io_in_a_valid & _T_262 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_262 & ~reset & ~_T_130) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_235 & (io_in_a_valid & _T_262 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_262 & ~reset & ~_T_235) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_262 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_262 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_262 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_262 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_262 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_262 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_249 & (io_in_a_valid & _T_262 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_262 & ~reset & ~_T_249) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_491 & (io_in_a_valid & _T_262 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_262 & ~reset & ~_T_491) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_254 & (io_in_a_valid & _T_262 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_262 & ~reset & ~_T_254) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_31 & (io_in_a_valid & _T_504 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_504 & ~reset & ~_T_31) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_615 & (io_in_a_valid & _T_504 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_504 & ~reset & ~_T_615) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_504 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_504 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_504 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_504 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_625 & (io_in_a_valid & _T_504 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_504 & ~reset & ~_T_625) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_629 & (io_in_a_valid & _T_504 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_504 & ~reset & ~_T_629) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_748 & (io_in_a_valid & _T_637 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_637 & ~reset & ~_T_748) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_637 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_637 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_637 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_637 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_625 & (io_in_a_valid & _T_637 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_637 & ~reset & ~_T_625) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_629 & (io_in_a_valid & _T_637 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_637 & ~reset & ~_T_629) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_877 & (io_in_a_valid & _T_766 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_766 & ~reset & ~_T_877) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_766 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_766 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_766 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_766 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_625 & (io_in_a_valid & _T_766 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_766 & ~reset & ~_T_625) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_893 & (io_in_a_valid & _T_766 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_766 & ~reset & ~_T_893) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1003 & (io_in_a_valid & _T_897 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_897 & ~reset & ~_T_1003) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_897 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_897 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_897 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_897 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1013 & (io_in_a_valid & _T_897 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_897 & ~reset & ~_T_1013) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_629 & (io_in_a_valid & _T_897 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_897 & ~reset & ~_T_629) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1003 & (io_in_a_valid & _T_1021 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1021 & ~reset & ~_T_1003) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_1021 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1021 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_1021 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1021 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1137 & (io_in_a_valid & _T_1021 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1021 & ~reset & ~_T_1137) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_629 & (io_in_a_valid & _T_1021 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1021 & ~reset & ~_T_629) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1251 & (io_in_a_valid & _T_1145 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1145 & ~reset & ~_T_1251) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_1145 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1145 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_1145 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1145 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1261 & (io_in_a_valid & _T_1145 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1145 & ~reset & ~_T_1261) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_629 & (io_in_a_valid & _T_1145 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1145 & ~reset & ~_T_629) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1273 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_1273) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1277 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1277 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1281 & (io_in_d_valid & _T_1277 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1277 & _T_2 & ~_T_1281) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1285 & (io_in_d_valid & _T_1277 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1277 & _T_2 & ~_T_1285) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1289 & (io_in_d_valid & _T_1277 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1277 & _T_2 & ~_T_1289) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1293 & (io_in_d_valid & _T_1277 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1277 & _T_2 & ~_T_1293) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is denied (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1297 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1297 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1281 & (io_in_d_valid & _T_1297 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1297 & _T_2 & ~_T_1281) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1308 & (io_in_d_valid & _T_1297 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1297 & _T_2 & ~_T_1308) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid cap param (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1312 & (io_in_d_valid & _T_1297 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1297 & _T_2 & ~_T_1312) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries toN param (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1289 & (io_in_d_valid & _T_1297 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1297 & _T_2 & ~_T_1289) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is corrupt (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1325 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1325 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1281 & (io_in_d_valid & _T_1325 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1325 & _T_2 & ~_T_1281) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1308 & (io_in_d_valid & _T_1325 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1325 & _T_2 & ~_T_1308) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1312 & (io_in_d_valid & _T_1325 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1325 & _T_2 & ~_T_1312) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries toN param (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1345 & (io_in_d_valid & _T_1325 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1325 & _T_2 & ~_T_1345) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1354 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1354 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1285 & (io_in_d_valid & _T_1354 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1354 & _T_2 & ~_T_1285) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid param (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1289 & (io_in_d_valid & _T_1354 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1354 & _T_2 & ~_T_1289) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is corrupt (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1371 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1371 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1285 & (io_in_d_valid & _T_1371 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1371 & _T_2 & ~_T_1285) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1345 & (io_in_d_valid & _T_1371 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1371 & _T_2 & ~_T_1345) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1389 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1389 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1285 & (io_in_d_valid & _T_1389 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1389 & _T_2 & ~_T_1285) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid param (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1289 & (io_in_d_valid & _T_1389 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1389 & _T_2 & ~_T_1289) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is corrupt (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1406 & (io_in_b_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & ~reset & ~_T_1406) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel has invalid opcode (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1532 & (io_in_b_valid & _T_1430 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1430 & _T_2 & ~_T_1532) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~address_ok & (io_in_b_valid & _T_1430 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1430 & _T_2 & ~address_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Probe carries unmanaged address (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_1 & (io_in_b_valid & _T_1430 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1430 & _T_2 & ~is_aligned_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Probe address not aligned to size (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1545 & (io_in_b_valid & _T_1430 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1430 & _T_2 & ~_T_1545) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Probe carries invalid cap param (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1549 & (io_in_b_valid & _T_1430 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1430 & _T_2 & ~_T_1549) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Probe contains invalid mask (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1553 & (io_in_b_valid & _T_1430 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1430 & _T_2 & ~_T_1553) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Probe is corrupt (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_b_valid & _T_1557 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1557 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1538 & (io_in_b_valid & _T_1557 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1557 & ~reset & _T_1538) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Get carries unmanaged address (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1544 & (io_in_b_valid & _T_1557 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1557 & ~reset & _T_1544) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Get address not aligned to size (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1666 & (io_in_b_valid & _T_1557 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1557 & ~reset & ~_T_1666) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Get carries invalid param (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1552 & (io_in_b_valid & _T_1557 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1557 & ~reset & _T_1552) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Get contains invalid mask (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1556 & (io_in_b_valid & _T_1557 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1557 & ~reset & _T_1556) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Get is corrupt (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_b_valid & _T_1678 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1678 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1538 & (io_in_b_valid & _T_1678 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1678 & ~reset & _T_1538) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1544 & (io_in_b_valid & _T_1678 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1678 & ~reset & _T_1544) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel PutFull address not aligned to size (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1666 & (io_in_b_valid & _T_1678 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1678 & ~reset & ~_T_1666) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel PutFull carries invalid param (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1552 & (io_in_b_valid & _T_1678 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1678 & ~reset & _T_1552) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel PutFull contains invalid mask (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_b_valid & _T_1795 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1795 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1538 & (io_in_b_valid & _T_1795 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1795 & ~reset & _T_1538) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1544 & (io_in_b_valid & _T_1795 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1795 & ~reset & _T_1544) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1666 & (io_in_b_valid & _T_1795 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1795 & ~reset & ~_T_1666) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel PutPartial carries invalid param (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1910 & (io_in_b_valid & _T_1795 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1795 & ~reset & ~_T_1910) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_b_valid & _T_1914 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1914 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1538 & (io_in_b_valid & _T_1914 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1914 & ~reset & _T_1538) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1544 & (io_in_b_valid & _T_1914 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1914 & ~reset & _T_1544) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1552 & (io_in_b_valid & _T_1914 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1914 & ~reset & _T_1552) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_b_valid & _T_2031 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2031 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1538 & (io_in_b_valid & _T_2031 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2031 & ~reset & _T_1538) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Logical carries unmanaged address (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1544 & (io_in_b_valid & _T_2031 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2031 & ~reset & _T_1544) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Logical address not aligned to size (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1552 & (io_in_b_valid & _T_2031 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2031 & ~reset & _T_1552) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Logical contains invalid mask (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_b_valid & _T_2148 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2148 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1538 & (io_in_b_valid & _T_2148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2148 & ~reset & _T_1538) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Hint carries unmanaged address (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1544 & (io_in_b_valid & _T_2148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2148 & ~reset & _T_1544) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Hint address not aligned to size (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1552 & (io_in_b_valid & _T_2148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2148 & ~reset & _T_1552) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Hint contains invalid mask (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1556 & (io_in_b_valid & _T_2148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2148 & ~reset & _T_1556) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Hint is corrupt (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~address_ok_1 & (io_in_c_valid & _T_2289 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2289 & ~reset & ~address_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_2 & (io_in_c_valid & _T_2289 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2289 & ~reset & ~source_ok_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2296 & (io_in_c_valid & _T_2289 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2289 & ~reset & ~_T_2296) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_2289 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2289 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2303 & (io_in_c_valid & _T_2289 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2289 & ~reset & ~_T_2303) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~address_ok_1 & (io_in_c_valid & _T_2311 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2311 & ~reset & ~address_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_2 & (io_in_c_valid & _T_2311 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2311 & ~reset & ~source_ok_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2296 & (io_in_c_valid & _T_2311 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2311 & ~reset & ~_T_2296) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_2311 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2311 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2303 & (io_in_c_valid & _T_2311 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2311 & ~reset & ~_T_2303) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2435 & (io_in_c_valid & _T_2329 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2329 & ~reset & ~_T_2435) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2540 & (io_in_c_valid & _T_2329 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2329 & ~reset & ~_T_2540) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_2 & (io_in_c_valid & _T_2329 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2329 & ~reset & ~source_ok_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release carries invalid source ID (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2296 & (io_in_c_valid & _T_2329 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2329 & ~reset & ~_T_2296) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release smaller than a beat (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_2329 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2329 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release address not aligned to size (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2303 & (io_in_c_valid & _T_2329 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2329 & ~reset & ~_T_2303) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release carries invalid report param (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2435 & (io_in_c_valid & _T_2562 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2562 & ~reset & ~_T_2435) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2540 & (io_in_c_valid & _T_2562 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2562 & ~reset & ~_T_2540) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_2 & (io_in_c_valid & _T_2562 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2562 & ~reset & ~source_ok_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2296 & (io_in_c_valid & _T_2562 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2562 & ~reset & ~_T_2296) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_2562 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2562 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2303 & (io_in_c_valid & _T_2562 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2562 & ~reset & ~_T_2303) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~address_ok_1 & (io_in_c_valid & _T_2791 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2791 & ~reset & ~address_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_2 & (io_in_c_valid & _T_2791 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2791 & ~reset & ~source_ok_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_2791 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2791 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2801 & (io_in_c_valid & _T_2791 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2791 & ~reset & ~_T_2801) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck carries invalid param (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~address_ok_1 & (io_in_c_valid & _T_2809 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2809 & ~reset & ~address_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_2 & (io_in_c_valid & _T_2809 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2809 & ~reset & ~source_ok_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_2809 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2809 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2801 & (io_in_c_valid & _T_2809 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2809 & ~reset & ~_T_2801) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~address_ok_1 & (io_in_c_valid & _T_2823 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2823 & ~reset & ~address_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_2 & (io_in_c_valid & _T_2823 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2823 & ~reset & ~source_ok_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_2823 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2823 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck address not aligned to size (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2801 & (io_in_c_valid & _T_2823 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2823 & ~reset & ~_T_2801) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck carries invalid param (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2846 & (_T_2845 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2845 & ~reset & ~_T_2846) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2850 & (_T_2845 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2845 & ~reset & ~_T_2850) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2854 & (_T_2845 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2845 & ~reset & ~_T_2854) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2858 & (_T_2845 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2845 & ~reset & ~_T_2858) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2862 & (_T_2845 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2845 & ~reset & ~_T_2862) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2870 & (_T_2869 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2869 & _T_2 & ~_T_2870) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2874 & (_T_2869 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2869 & _T_2 & ~_T_2874) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel param changed within multibeat operation (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2878 & (_T_2869 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2869 & _T_2 & ~_T_2878) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2882 & (_T_2869 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2869 & _T_2 & ~_T_2882) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2886 & (_T_2869 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2869 & _T_2 & ~_T_2886) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel sink changed with multibeat operation (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2890 & (_T_2869 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2869 & _T_2 & ~_T_2890) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel denied changed with multibeat operation (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2898 & (_T_2897 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2897 & ~reset & ~_T_2898) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2902 & (_T_2897 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2897 & ~reset & ~_T_2902) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel param changed within multibeat operation (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2906 & (_T_2897 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2897 & ~reset & ~_T_2906) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel size changed within multibeat operation (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2910 & (_T_2897 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2897 & ~reset & ~_T_2910) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel source changed within multibeat operation (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2914 & (_T_2897 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2897 & ~reset & ~_T_2914) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2922 & (_T_2921 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2921 & ~reset & ~_T_2922) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2926 & (_T_2921 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2921 & ~reset & ~_T_2926) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel param changed within multibeat operation (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2930 & (_T_2921 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2921 & ~reset & ~_T_2930) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel size changed within multibeat operation (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2934 & (_T_2921 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2921 & ~reset & ~_T_2934) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel source changed within multibeat operation (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2938 & (_T_2921 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2921 & ~reset & ~_T_2938) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel address changed with multibeat operation (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2951 & (_T_2947 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2947 & ~reset & ~_T_2951) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2970 & (_T_2958 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2958 & _T_2 & ~_T_2970) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2976 & (_T_2958 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2958 & same_cycle_resp & _T_2 & ~_T_2976) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2980 & (_T_2958 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2958 & same_cycle_resp & _T_2 & ~_T_2980) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2988 & (_T_2958 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2958 & ~same_cycle_resp & _T_2 & ~_T_2988) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2992 & (_T_2958 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2958 & ~same_cycle_resp & _T_2 & ~_T_2992) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3004 & (_T_3002 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3002 & _T_2 & ~_T_3004) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3011 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_3011) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 3 (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3020 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_3020) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3040 & (_T_3037 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3037 & ~reset & ~_T_3040) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel re-used a source ID (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3056 & (_T_3046 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3046 & _T_2 & ~_T_3056) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3060 & (_T_3046 & same_cycle_resp_1 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3046 & same_cycle_resp_1 & _T_2 & ~_T_3060) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3064 & (_T_3046 & ~same_cycle_resp_1 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3046 & ~same_cycle_resp_1 & _T_2 & ~_T_3064) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3075 & (_T_3073 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3073 & _T_2 & ~_T_3075) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3080 & (_T_3079 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3079 & _T_2 & ~_T_3080) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' and 'D' concurrent, despite minlatency 3 (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3089 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_3089) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3105 & (_T_3102 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3102 & _T_2 & ~_T_3105) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel re-used a sink ID (connected at HellaCache.scala:271:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3113[0] & (_T_3109 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3109 & ~reset & ~_T_3113[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at HellaCache.scala:271:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[9:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[30:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[9:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  param_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  size_1 = _RAND_9[3:0];
  _RAND_10 = {1{`RANDOM}};
  source_1 = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  sink = _RAND_11[1:0];
  _RAND_12 = {1{`RANDOM}};
  denied = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  b_first_counter = _RAND_13[9:0];
  _RAND_14 = {1{`RANDOM}};
  opcode_2 = _RAND_14[2:0];
  _RAND_15 = {1{`RANDOM}};
  param_2 = _RAND_15[1:0];
  _RAND_16 = {1{`RANDOM}};
  size_2 = _RAND_16[3:0];
  _RAND_17 = {1{`RANDOM}};
  source_2 = _RAND_17[0:0];
  _RAND_18 = {1{`RANDOM}};
  address_1 = _RAND_18[30:0];
  _RAND_19 = {1{`RANDOM}};
  c_first_counter = _RAND_19[9:0];
  _RAND_20 = {1{`RANDOM}};
  opcode_3 = _RAND_20[2:0];
  _RAND_21 = {1{`RANDOM}};
  param_3 = _RAND_21[2:0];
  _RAND_22 = {1{`RANDOM}};
  size_3 = _RAND_22[3:0];
  _RAND_23 = {1{`RANDOM}};
  source_3 = _RAND_23[0:0];
  _RAND_24 = {1{`RANDOM}};
  address_2 = _RAND_24[30:0];
  _RAND_25 = {1{`RANDOM}};
  inflight = _RAND_25[1:0];
  _RAND_26 = {1{`RANDOM}};
  inflight_opcodes = _RAND_26[7:0];
  _RAND_27 = {1{`RANDOM}};
  inflight_sizes = _RAND_27[15:0];
  _RAND_28 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_28[9:0];
  _RAND_29 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_29[9:0];
  _RAND_30 = {1{`RANDOM}};
  watchdog = _RAND_30[31:0];
  _RAND_31 = {1{`RANDOM}};
  inflight_1 = _RAND_31[1:0];
  _RAND_32 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_32[15:0];
  _RAND_33 = {1{`RANDOM}};
  c_first_counter_1 = _RAND_33[9:0];
  _RAND_34 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_34[9:0];
  _RAND_35 = {1{`RANDOM}};
  watchdog_1 = _RAND_35[31:0];
  _RAND_36 = {1{`RANDOM}};
  inflight_2 = _RAND_36[3:0];
  _RAND_37 = {1{`RANDOM}};
  d_first_counter_3 = _RAND_37[9:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLMonitor_44(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [30:0] io_in_a_bits_address,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_param,
  input  [3:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_sink,
  input         io_in_d_bits_denied,
  input         io_in_d_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire [30:0] _is_aligned_T = io_in_a_bits_address & 31'h3f; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 31'h0; // @[Edges.scala 20:24]
  wire [31:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_26 = $signed(_T_7) & -32'sh10001000; // @[Parameters.scala 137:52]
  wire  _T_27 = $signed(_T_26) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_28 = io_in_a_bits_address ^ 31'h3000; // @[Parameters.scala 137:31]
  wire [31:0] _T_29 = {1'b0,$signed(_T_28)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_31 = $signed(_T_29) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _T_32 = $signed(_T_31) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_33 = io_in_a_bits_address ^ 31'h10000; // @[Parameters.scala 137:31]
  wire [31:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_36 = $signed(_T_34) & -32'sh10000; // @[Parameters.scala 137:52]
  wire  _T_37 = $signed(_T_36) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_38 = io_in_a_bits_address ^ 31'h2000000; // @[Parameters.scala 137:31]
  wire [31:0] _T_39 = {1'b0,$signed(_T_38)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_41 = $signed(_T_39) & -32'sh10000; // @[Parameters.scala 137:52]
  wire  _T_42 = $signed(_T_41) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_43 = io_in_a_bits_address ^ 31'h8000000; // @[Parameters.scala 137:31]
  wire [31:0] _T_44 = {1'b0,$signed(_T_43)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_46 = $signed(_T_44) & -32'sh4000; // @[Parameters.scala 137:52]
  wire  _T_47 = $signed(_T_46) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_48 = io_in_a_bits_address ^ 31'hc000000; // @[Parameters.scala 137:31]
  wire [31:0] _T_49 = {1'b0,$signed(_T_48)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_51 = $signed(_T_49) & -32'sh4000000; // @[Parameters.scala 137:52]
  wire  _T_52 = $signed(_T_51) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_53 = io_in_a_bits_address ^ 31'h10012000; // @[Parameters.scala 137:31]
  wire [31:0] _T_54 = {1'b0,$signed(_T_53)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_56 = $signed(_T_54) & -32'sh2000; // @[Parameters.scala 137:52]
  wire  _T_57 = $signed(_T_56) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_58 = io_in_a_bits_address ^ 31'h10014000; // @[Parameters.scala 137:31]
  wire [31:0] _T_59 = {1'b0,$signed(_T_58)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_61 = $signed(_T_59) & -32'sh2000; // @[Parameters.scala 137:52]
  wire  _T_62 = $signed(_T_61) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_63 = io_in_a_bits_address ^ 31'h10016000; // @[Parameters.scala 137:31]
  wire [31:0] _T_64 = {1'b0,$signed(_T_63)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_66 = $signed(_T_64) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _T_67 = $signed(_T_66) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_68 = io_in_a_bits_address ^ 31'h10023000; // @[Parameters.scala 137:31]
  wire [31:0] _T_69 = {1'b0,$signed(_T_68)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_71 = $signed(_T_69) & -32'sh11000; // @[Parameters.scala 137:52]
  wire  _T_72 = $signed(_T_71) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_73 = io_in_a_bits_address ^ 31'h10024000; // @[Parameters.scala 137:31]
  wire [31:0] _T_74 = {1'b0,$signed(_T_73)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_76 = $signed(_T_74) & -32'sh12000; // @[Parameters.scala 137:52]
  wire  _T_77 = $signed(_T_76) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_78 = io_in_a_bits_address ^ 31'h10026000; // @[Parameters.scala 137:31]
  wire [31:0] _T_79 = {1'b0,$signed(_T_78)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_81 = $signed(_T_79) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _T_82 = $signed(_T_81) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_83 = io_in_a_bits_address ^ 31'h10043000; // @[Parameters.scala 137:31]
  wire [31:0] _T_84 = {1'b0,$signed(_T_83)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_86 = $signed(_T_84) & -32'sh11000; // @[Parameters.scala 137:52]
  wire  _T_87 = $signed(_T_86) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_88 = io_in_a_bits_address ^ 31'h20000000; // @[Parameters.scala 137:31]
  wire [31:0] _T_89 = {1'b0,$signed(_T_88)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_91 = $signed(_T_89) & -32'sh20000000; // @[Parameters.scala 137:52]
  wire  _T_92 = $signed(_T_91) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_111 = io_in_a_bits_address ^ 31'h40000000; // @[Parameters.scala 137:31]
  wire [31:0] _T_112 = {1'b0,$signed(_T_111)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_114 = $signed(_T_112) & -32'sh20000000; // @[Parameters.scala 137:52]
  wire  _T_115 = $signed(_T_114) == 32'sh0; // @[Parameters.scala 137:67]
  wire  _T_585 = _T_27 | _T_37 | _T_42 | _T_47 | _T_52 | _T_57 | _T_62 | _T_67 | _T_72 | _T_77 | _T_82 | _T_87 | _T_92
     | _T_115; // @[Parameters.scala 671:42]
  wire  _T_588 = _T_32 | _T_585; // @[Parameters.scala 672:30]
  wire  _T_1236 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _T_1240 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_1244 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 312:27]
  wire  _T_1248 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
  wire  _T_1252 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
  wire  _T_1256 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
  wire  _T_1260 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_1271 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
  wire  _T_1275 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
  wire  _T_1288 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_1308 = _T_1256 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
  wire  _T_1317 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_1334 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_1352 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  reg [9:0] a_first_counter; // @[Edges.scala 228:27]
  wire [9:0] a_first_counter1 = a_first_counter - 10'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 10'h0; // @[Edges.scala 230:25]
  reg [30:0] address; // @[Monitor.scala 388:22]
  wire  _T_1382 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_1399 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [26:0] _d_first_beats1_decode_T_1 = 27'hfff << io_in_d_bits_size; // @[package.scala 234:77]
  wire [11:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
  wire [9:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[11:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [9:0] d_first_counter; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1 = d_first_counter - 10'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 10'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] param_1; // @[Monitor.scala 536:22]
  reg [3:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] sink; // @[Monitor.scala 539:22]
  reg  denied; // @[Monitor.scala 540:22]
  wire  _T_1406 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_1407 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_1411 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
  wire  _T_1415 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_1423 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
  wire  _T_1427 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
  reg  inflight; // @[Monitor.scala 611:27]
  reg [3:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [7:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [9:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [9:0] a_first_counter1_1 = a_first_counter_1 - 10'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 10'h0; // @[Edges.scala 230:25]
  reg [9:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1_1 = d_first_counter_1 - 10'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 10'h0; // @[Edges.scala 230:25]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_71 = {{12'd0}, inflight_opcodes}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_71 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [15:0] _a_size_lookup_T_5 = 16'h100 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_73 = {{8'd0}, inflight_sizes}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_73 & _a_size_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_1433 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [1:0] _GEN_15 = io_in_a_valid & a_first_1 ? 2'h1 : 2'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_1436 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? 4'h9 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [18:0] _a_opcodes_set_T_1 = {{15'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [4:0] a_sizes_set_interm = a_first_done & a_first_1 ? 5'hd : 5'h0; // @[Monitor.scala 652:72 655:28]
  wire [19:0] _a_sizes_set_T_1 = {{15'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire  _T_1440 = ~inflight; // @[Monitor.scala 658:17]
  wire [1:0] _GEN_16 = a_first_done & a_first_1 ? 2'h1 : 2'h0; // @[Monitor.scala 652:72 653:28]
  wire [18:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 656:28]
  wire [19:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 20'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_1444 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_1446 = ~_T_1240; // @[Monitor.scala 671:74]
  wire  _T_1447 = io_in_d_valid & d_first_1 & ~_T_1240; // @[Monitor.scala 671:71]
  wire [1:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_1240 ? 2'h1 : 2'h0; // @[Monitor.scala 671:90 672:22]
  wire [30:0] _d_opcodes_clr_T_5 = {{15'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [30:0] _d_sizes_clr_T_5 = {{15'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 678:74]
  wire [1:0] _GEN_22 = _d_first_T & d_first_1 & _T_1446 ? 2'h1 : 2'h0; // @[Monitor.scala 675:91 676:21]
  wire [30:0] _GEN_23 = _d_first_T & d_first_1 & _T_1446 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 677:21]
  wire [30:0] _GEN_24 = _d_first_T & d_first_1 & _T_1446 ? _d_sizes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 678:21]
  wire  _T_1459 = inflight | _T_1433; // @[Monitor.scala 682:49]
  wire  _T_1465 = _T_1334 | _T_1334; // @[Monitor.scala 685:77]
  wire  _T_1469 = 4'h6 == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_1476 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_1477 = io_in_d_bits_opcode == _GEN_48 | _T_1476; // @[Monitor.scala 689:72]
  wire [7:0] a_size_lookup = _a_size_lookup_T_7[7:0];
  wire [7:0] _GEN_75 = {{4'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_1481 = _GEN_75 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_1491 = _T_1444 & a_first_1 & io_in_a_valid & _T_1446; // @[Monitor.scala 694:116]
  wire  _T_1493 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire  a_set_wo_ready = _GEN_15[0];
  wire  d_clr_wo_ready = _GEN_21[0];
  wire  _T_1500 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire  a_set = _GEN_16[0];
  wire  d_clr = _GEN_22[0];
  wire [3:0] a_opcodes_set = _GEN_19[3:0];
  wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [3:0] d_opcodes_clr = _GEN_23[3:0];
  wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [7:0] a_sizes_set = _GEN_20[7:0];
  wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [7:0] d_sizes_clr = _GEN_24[7:0];
  wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala 704:56]
  wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_1509 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [7:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [9:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1_2 = d_first_counter_2 - 10'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 10'h0; // @[Edges.scala 230:25]
  wire [15:0] _GEN_78 = {{8'd0}, inflight_sizes_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_78 & _a_size_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_1535 = io_in_d_valid & d_first_2 & _T_1240; // @[Monitor.scala 779:71]
  wire [30:0] _GEN_69 = _d_first_T & d_first_2 & _T_1240 ? _d_sizes_clr_T_5 : 31'h0; // @[Monitor.scala 783:90 786:21]
  wire [7:0] c_size_lookup = _c_size_lookup_T_7[7:0];
  wire  _T_1553 = _GEN_75 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [7:0] d_sizes_clr_1 = _GEN_69[7:0];
  wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
  wire [7:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 10'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 10'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 10'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 1'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= (inflight | a_set) & ~d_clr; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 4'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 8'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 10'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 10'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 10'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (a_first_done | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 8'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 10'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_588 & (io_in_a_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & ~reset & ~_T_588) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at Frontend.scala:372:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at Frontend.scala:372:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1236 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_1236) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at Frontend.scala:372:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1244 & (io_in_d_valid & _T_1240 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1240 & _T_2 & ~_T_1244) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Frontend.scala:372:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1248 & (io_in_d_valid & _T_1240 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1240 & _T_2 & ~_T_1248) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Frontend.scala:372:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1252 & (io_in_d_valid & _T_1240 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1240 & _T_2 & ~_T_1252) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at Frontend.scala:372:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1256 & (io_in_d_valid & _T_1240 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1240 & _T_2 & ~_T_1256) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is denied (connected at Frontend.scala:372:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1244 & (io_in_d_valid & _T_1260 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1260 & _T_2 & ~_T_1244) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at Frontend.scala:372:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1271 & (io_in_d_valid & _T_1260 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1260 & _T_2 & ~_T_1271) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid cap param (connected at Frontend.scala:372:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1275 & (io_in_d_valid & _T_1260 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1260 & _T_2 & ~_T_1275) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries toN param (connected at Frontend.scala:372:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1252 & (io_in_d_valid & _T_1260 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1260 & _T_2 & ~_T_1252) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is corrupt (connected at Frontend.scala:372:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1244 & (io_in_d_valid & _T_1288 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1288 & _T_2 & ~_T_1244) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Frontend.scala:372:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1271 & (io_in_d_valid & _T_1288 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1288 & _T_2 & ~_T_1271) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Frontend.scala:372:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1275 & (io_in_d_valid & _T_1288 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1288 & _T_2 & ~_T_1275) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries toN param (connected at Frontend.scala:372:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1308 & (io_in_d_valid & _T_1288 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1288 & _T_2 & ~_T_1308) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at Frontend.scala:372:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1248 & (io_in_d_valid & _T_1317 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1317 & _T_2 & ~_T_1248) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid param (connected at Frontend.scala:372:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1252 & (io_in_d_valid & _T_1317 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1317 & _T_2 & ~_T_1252) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is corrupt (connected at Frontend.scala:372:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1248 & (io_in_d_valid & _T_1334 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1334 & _T_2 & ~_T_1248) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Frontend.scala:372:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1308 & (io_in_d_valid & _T_1334 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1334 & _T_2 & ~_T_1308) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at Frontend.scala:372:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1248 & (io_in_d_valid & _T_1352 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1352 & _T_2 & ~_T_1248) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid param (connected at Frontend.scala:372:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1252 & (io_in_d_valid & _T_1352 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1352 & _T_2 & ~_T_1252) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is corrupt (connected at Frontend.scala:372:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1399 & (_T_1382 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1382 & ~reset & ~_T_1399) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at Frontend.scala:372:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1407 & (_T_1406 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1406 & _T_2 & ~_T_1407) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Frontend.scala:372:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1411 & (_T_1406 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1406 & _T_2 & ~_T_1411) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel param changed within multibeat operation (connected at Frontend.scala:372:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1415 & (_T_1406 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1406 & _T_2 & ~_T_1415) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at Frontend.scala:372:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1423 & (_T_1406 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1406 & _T_2 & ~_T_1423) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel sink changed with multibeat operation (connected at Frontend.scala:372:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1427 & (_T_1406 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1406 & _T_2 & ~_T_1427) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel denied changed with multibeat operation (connected at Frontend.scala:372:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1440 & (_T_1436 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1436 & ~reset & ~_T_1440) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at Frontend.scala:372:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1459 & (_T_1447 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1447 & _T_2 & ~_T_1459) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Frontend.scala:372:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1465 & (_T_1447 & _T_1433 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1447 & _T_1433 & _T_2 & ~_T_1465) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Frontend.scala:372:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1469 & (_T_1447 & _T_1433 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1447 & _T_1433 & _T_2 & ~_T_1469) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Frontend.scala:372:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1477 & (_T_1447 & ~_T_1433 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1447 & ~_T_1433 & _T_2 & ~_T_1477) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Frontend.scala:372:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1481 & (_T_1447 & ~_T_1433 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1447 & ~_T_1433 & _T_2 & ~_T_1481) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Frontend.scala:372:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1493 & (_T_1491 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1491 & _T_2 & ~_T_1493) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1500 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_1500) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 3 (connected at Frontend.scala:372:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1509 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_1509) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Frontend.scala:372:21)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1535 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1535 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Frontend.scala:372:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1553 & (_T_1535 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_1535 & _T_2 & ~_T_1553) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Frontend.scala:372:21)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[9:0];
  _RAND_1 = {1{`RANDOM}};
  address = _RAND_1[30:0];
  _RAND_2 = {1{`RANDOM}};
  d_first_counter = _RAND_2[9:0];
  _RAND_3 = {1{`RANDOM}};
  opcode_1 = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  param_1 = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  size_1 = _RAND_5[3:0];
  _RAND_6 = {1{`RANDOM}};
  sink = _RAND_6[1:0];
  _RAND_7 = {1{`RANDOM}};
  denied = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  inflight = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  inflight_opcodes = _RAND_9[3:0];
  _RAND_10 = {1{`RANDOM}};
  inflight_sizes = _RAND_10[7:0];
  _RAND_11 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_11[9:0];
  _RAND_12 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_12[9:0];
  _RAND_13 = {1{`RANDOM}};
  watchdog = _RAND_13[31:0];
  _RAND_14 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_14[7:0];
  _RAND_15 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_15[9:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLXbar_7(
  input         clock,
  input         reset,
  output        auto_in_1_a_ready,
  input         auto_in_1_a_valid,
  input  [30:0] auto_in_1_a_bits_address,
  input         auto_in_1_d_ready,
  output        auto_in_1_d_valid,
  output [2:0]  auto_in_1_d_bits_opcode,
  output [3:0]  auto_in_1_d_bits_size,
  output [31:0] auto_in_1_d_bits_data,
  output        auto_in_1_d_bits_corrupt,
  output        auto_in_0_a_ready,
  input         auto_in_0_a_valid,
  input  [2:0]  auto_in_0_a_bits_opcode,
  input  [2:0]  auto_in_0_a_bits_param,
  input  [3:0]  auto_in_0_a_bits_size,
  input         auto_in_0_a_bits_source,
  input  [30:0] auto_in_0_a_bits_address,
  input  [3:0]  auto_in_0_a_bits_mask,
  input  [31:0] auto_in_0_a_bits_data,
  input         auto_in_0_b_ready,
  output        auto_in_0_b_valid,
  output [1:0]  auto_in_0_b_bits_param,
  output [3:0]  auto_in_0_b_bits_size,
  output        auto_in_0_b_bits_source,
  output [30:0] auto_in_0_b_bits_address,
  output        auto_in_0_c_ready,
  input         auto_in_0_c_valid,
  input  [2:0]  auto_in_0_c_bits_opcode,
  input  [2:0]  auto_in_0_c_bits_param,
  input  [3:0]  auto_in_0_c_bits_size,
  input         auto_in_0_c_bits_source,
  input  [30:0] auto_in_0_c_bits_address,
  input  [31:0] auto_in_0_c_bits_data,
  input         auto_in_0_d_ready,
  output        auto_in_0_d_valid,
  output [2:0]  auto_in_0_d_bits_opcode,
  output [1:0]  auto_in_0_d_bits_param,
  output [3:0]  auto_in_0_d_bits_size,
  output        auto_in_0_d_bits_source,
  output [1:0]  auto_in_0_d_bits_sink,
  output        auto_in_0_d_bits_denied,
  output [31:0] auto_in_0_d_bits_data,
  output        auto_in_0_e_ready,
  input         auto_in_0_e_valid,
  input  [1:0]  auto_in_0_e_bits_sink,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [3:0]  auto_out_a_bits_size,
  output [1:0]  auto_out_a_bits_source,
  output [30:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_b_ready,
  input         auto_out_b_valid,
  input  [2:0]  auto_out_b_bits_opcode,
  input  [1:0]  auto_out_b_bits_param,
  input  [3:0]  auto_out_b_bits_size,
  input  [1:0]  auto_out_b_bits_source,
  input  [30:0] auto_out_b_bits_address,
  input  [3:0]  auto_out_b_bits_mask,
  input         auto_out_b_bits_corrupt,
  input         auto_out_c_ready,
  output        auto_out_c_valid,
  output [2:0]  auto_out_c_bits_opcode,
  output [2:0]  auto_out_c_bits_param,
  output [3:0]  auto_out_c_bits_size,
  output [1:0]  auto_out_c_bits_source,
  output [30:0] auto_out_c_bits_address,
  output [31:0] auto_out_c_bits_data,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_param,
  input  [3:0]  auto_out_d_bits_size,
  input  [1:0]  auto_out_d_bits_source,
  input  [1:0]  auto_out_d_bits_sink,
  input         auto_out_d_bits_denied,
  input  [31:0] auto_out_d_bits_data,
  input         auto_out_d_bits_corrupt,
  input         auto_out_e_ready,
  output        auto_out_e_valid,
  output [1:0]  auto_out_e_bits_sink
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [30:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_b_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_b_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_b_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_b_bits_param; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_b_bits_size; // @[Nodes.scala 24:25]
  wire  monitor_io_in_b_bits_source; // @[Nodes.scala 24:25]
  wire [30:0] monitor_io_in_b_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_b_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_b_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_c_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_c_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_c_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_c_bits_param; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_c_bits_size; // @[Nodes.scala 24:25]
  wire  monitor_io_in_c_bits_source; // @[Nodes.scala 24:25]
  wire [30:0] monitor_io_in_c_bits_address; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_e_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_e_valid; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_e_bits_sink; // @[Nodes.scala 24:25]
  wire  monitor_1_clock; // @[Nodes.scala 24:25]
  wire  monitor_1_reset; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [30:0] monitor_1_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_1_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_1_io_in_d_bits_param; // @[Nodes.scala 24:25]
  wire [3:0] monitor_1_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_1_io_in_d_bits_sink; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_d_bits_denied; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
  wire  requestBOI_0_0 = ~auto_out_b_bits_source[1]; // @[Parameters.scala 54:32]
  wire  requestDOI_0_0 = ~auto_out_d_bits_source[1]; // @[Parameters.scala 54:32]
  wire  requestDOI_0_1 = auto_out_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire [26:0] _beatsAI_decode_T_1 = 27'hfff << auto_in_0_a_bits_size; // @[package.scala 234:77]
  wire [11:0] _beatsAI_decode_T_3 = ~_beatsAI_decode_T_1[11:0]; // @[package.scala 234:46]
  wire [9:0] beatsAI_decode = _beatsAI_decode_T_3[11:2]; // @[Edges.scala 219:59]
  wire  beatsAI_opdata = ~auto_in_0_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [9:0] beatsLeft; // @[Arbiter.scala 87:30]
  wire  idle = beatsLeft == 10'h0; // @[Arbiter.scala 88:28]
  wire  latch = idle & auto_out_a_ready; // @[Arbiter.scala 89:24]
  wire [1:0] readys_valid = {auto_in_1_a_valid,auto_in_0_a_valid}; // @[Cat.scala 31:58]
  wire  _readys_T_3 = ~reset; // @[Arbiter.scala 22:12]
  reg [1:0] readys_mask; // @[Arbiter.scala 23:23]
  wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala 24:30]
  wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala 24:28]
  wire [3:0] readys_filter = {_readys_filter_T_1,auto_in_1_a_valid,auto_in_0_a_valid}; // @[Cat.scala 31:58]
  wire [3:0] _GEN_1 = {{1'd0}, readys_filter[3:1]}; // @[package.scala 253:43]
  wire [3:0] _readys_unready_T_1 = readys_filter | _GEN_1; // @[package.scala 253:43]
  wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala 25:66]
  wire [3:0] _GEN_2 = {{1'd0}, _readys_unready_T_1[3:1]}; // @[Arbiter.scala 25:58]
  wire [3:0] readys_unready = _GEN_2 | _readys_unready_T_4; // @[Arbiter.scala 25:58]
  wire [1:0] _readys_readys_T_2 = readys_unready[3:2] & readys_unready[1:0]; // @[Arbiter.scala 26:39]
  wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala 26:18]
  wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala 28:29]
  wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala 244:48]
  wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_1[1:0]; // @[package.scala 244:43]
  wire  readys_0 = readys_readys[0]; // @[Arbiter.scala 95:86]
  wire  readys_1 = readys_readys[1]; // @[Arbiter.scala 95:86]
  wire  earlyWinner_0 = readys_0 & auto_in_0_a_valid; // @[Arbiter.scala 97:79]
  wire  earlyWinner_1 = readys_1 & auto_in_1_a_valid; // @[Arbiter.scala 97:79]
  wire  _prefixOR_T = earlyWinner_0 | earlyWinner_1; // @[Arbiter.scala 104:53]
  wire  _T_11 = auto_in_0_a_valid | auto_in_1_a_valid; // @[Arbiter.scala 107:36]
  wire  _T_12 = ~(auto_in_0_a_valid | auto_in_1_a_valid); // @[Arbiter.scala 107:15]
  reg  state_0; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_0 = idle ? earlyWinner_0 : state_0; // @[Arbiter.scala 117:30]
  reg  state_1; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_1 = idle ? earlyWinner_1 : state_1; // @[Arbiter.scala 117:30]
  wire  _out_0_a_earlyValid_T_3 = state_0 & auto_in_0_a_valid | state_1 & auto_in_1_a_valid; // @[Mux.scala 27:73]
  wire  out_2_0_a_earlyValid = idle ? _T_11 : _out_0_a_earlyValid_T_3; // @[Arbiter.scala 125:29]
  wire  _beatsLeft_T_2 = auto_out_a_ready & out_2_0_a_earlyValid; // @[ReadyValidCancel.scala 49:33]
  wire [9:0] _GEN_3 = {{9'd0}, _beatsLeft_T_2}; // @[Arbiter.scala 113:52]
  wire [9:0] _beatsLeft_T_4 = beatsLeft - _GEN_3; // @[Arbiter.scala 113:52]
  wire  allowed_0 = idle ? readys_0 : state_0; // @[Arbiter.scala 121:24]
  wire  allowed_1 = idle ? readys_1 : state_1; // @[Arbiter.scala 121:24]
  wire [3:0] _T_31 = muxStateEarly_0 ? auto_in_0_a_bits_mask : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _T_32 = muxStateEarly_1 ? 4'hf : 4'h0; // @[Mux.scala 27:73]
  wire [30:0] _T_34 = muxStateEarly_0 ? auto_in_0_a_bits_address : 31'h0; // @[Mux.scala 27:73]
  wire [30:0] _T_35 = muxStateEarly_1 ? auto_in_1_a_bits_address : 31'h0; // @[Mux.scala 27:73]
  wire [1:0] in_0_a_bits_source = {{1'd0}, auto_in_0_a_bits_source}; // @[Xbar.scala 231:18 237:29]
  wire [1:0] _T_37 = muxStateEarly_0 ? in_0_a_bits_source : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_38 = muxStateEarly_1 ? 2'h2 : 2'h0; // @[Mux.scala 27:73]
  wire [3:0] _T_40 = muxStateEarly_0 ? auto_in_0_a_bits_size : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _T_41 = muxStateEarly_1 ? 4'h6 : 4'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_46 = muxStateEarly_0 ? auto_in_0_a_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_47 = muxStateEarly_1 ? 3'h4 : 3'h0; // @[Mux.scala 27:73]
  TLMonitor_43 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_b_ready(monitor_io_in_b_ready),
    .io_in_b_valid(monitor_io_in_b_valid),
    .io_in_b_bits_opcode(monitor_io_in_b_bits_opcode),
    .io_in_b_bits_param(monitor_io_in_b_bits_param),
    .io_in_b_bits_size(monitor_io_in_b_bits_size),
    .io_in_b_bits_source(monitor_io_in_b_bits_source),
    .io_in_b_bits_address(monitor_io_in_b_bits_address),
    .io_in_b_bits_mask(monitor_io_in_b_bits_mask),
    .io_in_b_bits_corrupt(monitor_io_in_b_bits_corrupt),
    .io_in_c_ready(monitor_io_in_c_ready),
    .io_in_c_valid(monitor_io_in_c_valid),
    .io_in_c_bits_opcode(monitor_io_in_c_bits_opcode),
    .io_in_c_bits_param(monitor_io_in_c_bits_param),
    .io_in_c_bits_size(monitor_io_in_c_bits_size),
    .io_in_c_bits_source(monitor_io_in_c_bits_source),
    .io_in_c_bits_address(monitor_io_in_c_bits_address),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_param(monitor_io_in_d_bits_param),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source),
    .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
    .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
    .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt),
    .io_in_e_ready(monitor_io_in_e_ready),
    .io_in_e_valid(monitor_io_in_e_valid),
    .io_in_e_bits_sink(monitor_io_in_e_bits_sink)
  );
  TLMonitor_44 monitor_1 ( // @[Nodes.scala 24:25]
    .clock(monitor_1_clock),
    .reset(monitor_1_reset),
    .io_in_a_ready(monitor_1_io_in_a_ready),
    .io_in_a_valid(monitor_1_io_in_a_valid),
    .io_in_a_bits_address(monitor_1_io_in_a_bits_address),
    .io_in_d_ready(monitor_1_io_in_d_ready),
    .io_in_d_valid(monitor_1_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_1_io_in_d_bits_opcode),
    .io_in_d_bits_param(monitor_1_io_in_d_bits_param),
    .io_in_d_bits_size(monitor_1_io_in_d_bits_size),
    .io_in_d_bits_sink(monitor_1_io_in_d_bits_sink),
    .io_in_d_bits_denied(monitor_1_io_in_d_bits_denied),
    .io_in_d_bits_corrupt(monitor_1_io_in_d_bits_corrupt)
  );
  assign auto_in_1_a_ready = auto_out_a_ready & allowed_1; // @[Arbiter.scala 123:31]
  assign auto_in_1_d_valid = auto_out_d_valid & requestDOI_0_1; // @[Xbar.scala 179:40]
  assign auto_in_1_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_1_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_1_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_1_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_0_a_ready = auto_out_a_ready & allowed_0; // @[Arbiter.scala 123:31]
  assign auto_in_0_b_valid = auto_out_b_valid & requestBOI_0_0; // @[Xbar.scala 179:40]
  assign auto_in_0_b_bits_param = auto_out_b_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_0_b_bits_size = auto_out_b_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_0_b_bits_source = auto_out_b_bits_source[0]; // @[Xbar.scala 228:69]
  assign auto_in_0_b_bits_address = auto_out_b_bits_address; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_0_c_ready = auto_out_c_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_0_d_valid = auto_out_d_valid & requestDOI_0_0; // @[Xbar.scala 179:40]
  assign auto_in_0_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_0_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_0_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_0_d_bits_source = auto_out_d_bits_source[0]; // @[Xbar.scala 228:69]
  assign auto_in_0_d_bits_sink = auto_out_d_bits_sink; // @[Xbar.scala 323:53]
  assign auto_in_0_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_0_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_0_e_ready = auto_out_e_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = idle ? _T_11 : _out_0_a_earlyValid_T_3; // @[Arbiter.scala 125:29]
  assign auto_out_a_bits_opcode = _T_46 | _T_47; // @[Mux.scala 27:73]
  assign auto_out_a_bits_param = muxStateEarly_0 ? auto_in_0_a_bits_param : 3'h0; // @[Mux.scala 27:73]
  assign auto_out_a_bits_size = _T_40 | _T_41; // @[Mux.scala 27:73]
  assign auto_out_a_bits_source = _T_37 | _T_38; // @[Mux.scala 27:73]
  assign auto_out_a_bits_address = _T_34 | _T_35; // @[Mux.scala 27:73]
  assign auto_out_a_bits_mask = _T_31 | _T_32; // @[Mux.scala 27:73]
  assign auto_out_a_bits_data = muxStateEarly_0 ? auto_in_0_a_bits_data : 32'h0; // @[Mux.scala 27:73]
  assign auto_out_b_ready = requestBOI_0_0 & auto_in_0_b_ready; // @[Mux.scala 27:73]
  assign auto_out_c_valid = auto_in_0_c_valid; // @[ReadyValidCancel.scala 21:38]
  assign auto_out_c_bits_opcode = auto_in_0_c_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_bits_param = auto_in_0_c_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_bits_size = auto_in_0_c_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_bits_source = {{1'd0}, auto_in_0_c_bits_source}; // @[Xbar.scala 231:18 259:29]
  assign auto_out_c_bits_address = auto_in_0_c_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_bits_data = auto_in_0_c_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_d_ready = requestDOI_0_0 & auto_in_0_d_ready | requestDOI_0_1 & auto_in_1_d_ready; // @[Mux.scala 27:73]
  assign auto_out_e_valid = auto_in_0_e_valid; // @[ReadyValidCancel.scala 21:38]
  assign auto_out_e_bits_sink = auto_in_0_e_bits_sink; // @[Xbar.scala 228:69]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = auto_out_a_ready & allowed_0; // @[Arbiter.scala 123:31]
  assign monitor_io_in_a_valid = auto_in_0_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_0_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_0_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_0_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_0_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_0_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_0_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_b_ready = auto_in_0_b_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_b_valid = auto_out_b_valid & requestBOI_0_0; // @[Xbar.scala 179:40]
  assign monitor_io_in_b_bits_opcode = auto_out_b_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_b_bits_param = auto_out_b_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_b_bits_size = auto_out_b_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_b_bits_source = auto_out_b_bits_source[0]; // @[Xbar.scala 228:69]
  assign monitor_io_in_b_bits_address = auto_out_b_bits_address; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_b_bits_mask = auto_out_b_bits_mask; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_b_bits_corrupt = auto_out_b_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_c_ready = auto_out_c_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_c_valid = auto_in_0_c_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_opcode = auto_in_0_c_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_param = auto_in_0_c_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_size = auto_in_0_c_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_source = auto_in_0_c_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_address = auto_in_0_c_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_0_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_out_d_valid & requestDOI_0_0; // @[Xbar.scala 179:40]
  assign monitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_source = auto_out_d_bits_source[0]; // @[Xbar.scala 228:69]
  assign monitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Xbar.scala 323:53]
  assign monitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_e_ready = auto_out_e_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_io_in_e_valid = auto_in_0_e_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_e_bits_sink = auto_in_0_e_bits_sink; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_clock = clock;
  assign monitor_1_reset = reset;
  assign monitor_1_io_in_a_ready = auto_out_a_ready & allowed_1; // @[Arbiter.scala 123:31]
  assign monitor_1_io_in_a_valid = auto_in_1_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_a_bits_address = auto_in_1_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_d_ready = auto_in_1_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_d_valid = auto_out_d_valid & requestDOI_0_1; // @[Xbar.scala 179:40]
  assign monitor_1_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_1_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_1_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_1_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Xbar.scala 323:53]
  assign monitor_1_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign monitor_1_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  always @(posedge clock) begin
    if (reset) begin // @[Arbiter.scala 87:30]
      beatsLeft <= 10'h0; // @[Arbiter.scala 87:30]
    end else if (latch) begin // @[Arbiter.scala 113:23]
      if (earlyWinner_0) begin // @[Arbiter.scala 111:73]
        if (beatsAI_opdata) begin // @[Edges.scala 220:14]
          beatsLeft <= beatsAI_decode;
        end else begin
          beatsLeft <= 10'h0;
        end
      end else begin
        beatsLeft <= 10'h0;
      end
    end else begin
      beatsLeft <= _beatsLeft_T_4;
    end
    if (reset) begin // @[Arbiter.scala 23:23]
      readys_mask <= 2'h3; // @[Arbiter.scala 23:23]
    end else if (latch & |readys_valid) begin // @[Arbiter.scala 27:32]
      readys_mask <= _readys_mask_T_3; // @[Arbiter.scala 28:12]
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_0 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_0 <= earlyWinner_0;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_1 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_1 <= earlyWinner_1;
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~earlyWinner_0 | ~earlyWinner_1) & _readys_T_3) begin
          $fatal; // @[Arbiter.scala 105:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_readys_T_3 & ~(~earlyWinner_0 | ~earlyWinner_1)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:105 assert((prefixOR zip earlyWinner) map { case (p,w) => !p || !w } reduce {_ && _})\n"
            ); // @[Arbiter.scala 105:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(auto_in_0_a_valid | auto_in_1_a_valid) | _prefixOR_T) & _readys_T_3) begin
          $fatal; // @[Arbiter.scala 107:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_readys_T_3 & ~(~(auto_in_0_a_valid | auto_in_1_a_valid) | _prefixOR_T)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:107 assert (!earlyValids.reduce(_||_) || earlyWinner.reduce(_||_))\n"
            ); // @[Arbiter.scala 107:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_12 | _T_11) & _readys_T_3) begin
          $fatal; // @[Arbiter.scala 108:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_readys_T_3 & ~(_T_12 | _T_11)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:108 assert (!validQuals .reduce(_||_) || validQuals .reduce(_||_))\n"
            ); // @[Arbiter.scala 108:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  beatsLeft = _RAND_0[9:0];
  _RAND_1 = {1{`RANDOM}};
  readys_mask = _RAND_1[1:0];
  _RAND_2 = {1{`RANDOM}};
  state_0 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  state_1 = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLXbar_8(
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [27:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output [31:0] auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [2:0]  auto_out_a_bits_size,
  output [1:0]  auto_out_a_bits_source,
  output [27:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [2:0]  auto_out_d_bits_size,
  input  [1:0]  auto_out_d_bits_source,
  input  [31:0] auto_out_d_bits_data
);
  assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_valid = auto_out_d_valid; // @[ReadyValidCancel.scala 21:38]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Xbar.scala 228:69]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = auto_in_a_valid; // @[ReadyValidCancel.scala 21:38]
  assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Xbar.scala 237:55]
  assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module IntXbar_1(
  input   auto_int_in_3_0,
  input   auto_int_in_2_0,
  input   auto_int_in_1_0,
  input   auto_int_in_1_1,
  input   auto_int_in_0_0,
  output  auto_int_out_0,
  output  auto_int_out_1,
  output  auto_int_out_2,
  output  auto_int_out_3,
  output  auto_int_out_4
);
  assign auto_int_out_0 = auto_int_in_0_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_1 = auto_int_in_1_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_2 = auto_int_in_1_1; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_3 = auto_int_in_2_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_int_out_4 = auto_int_in_3_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module BundleBridgeNexus_6(
  input   auto_in,
  output  auto_out_0
);
  assign auto_out_0 = auto_in; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module PMPChecker(
  input  [1:0]  io_prv,
  input         io_pmp_0_cfg_l,
  input  [1:0]  io_pmp_0_cfg_a,
  input         io_pmp_0_cfg_x,
  input         io_pmp_0_cfg_w,
  input         io_pmp_0_cfg_r,
  input  [28:0] io_pmp_0_addr,
  input  [30:0] io_pmp_0_mask,
  input         io_pmp_1_cfg_l,
  input  [1:0]  io_pmp_1_cfg_a,
  input         io_pmp_1_cfg_x,
  input         io_pmp_1_cfg_w,
  input         io_pmp_1_cfg_r,
  input  [28:0] io_pmp_1_addr,
  input  [30:0] io_pmp_1_mask,
  input         io_pmp_2_cfg_l,
  input  [1:0]  io_pmp_2_cfg_a,
  input         io_pmp_2_cfg_x,
  input         io_pmp_2_cfg_w,
  input         io_pmp_2_cfg_r,
  input  [28:0] io_pmp_2_addr,
  input  [30:0] io_pmp_2_mask,
  input         io_pmp_3_cfg_l,
  input  [1:0]  io_pmp_3_cfg_a,
  input         io_pmp_3_cfg_x,
  input         io_pmp_3_cfg_w,
  input         io_pmp_3_cfg_r,
  input  [28:0] io_pmp_3_addr,
  input  [30:0] io_pmp_3_mask,
  input         io_pmp_4_cfg_l,
  input  [1:0]  io_pmp_4_cfg_a,
  input         io_pmp_4_cfg_x,
  input         io_pmp_4_cfg_w,
  input         io_pmp_4_cfg_r,
  input  [28:0] io_pmp_4_addr,
  input  [30:0] io_pmp_4_mask,
  input         io_pmp_5_cfg_l,
  input  [1:0]  io_pmp_5_cfg_a,
  input         io_pmp_5_cfg_x,
  input         io_pmp_5_cfg_w,
  input         io_pmp_5_cfg_r,
  input  [28:0] io_pmp_5_addr,
  input  [30:0] io_pmp_5_mask,
  input         io_pmp_6_cfg_l,
  input  [1:0]  io_pmp_6_cfg_a,
  input         io_pmp_6_cfg_x,
  input         io_pmp_6_cfg_w,
  input         io_pmp_6_cfg_r,
  input  [28:0] io_pmp_6_addr,
  input  [30:0] io_pmp_6_mask,
  input         io_pmp_7_cfg_l,
  input  [1:0]  io_pmp_7_cfg_a,
  input         io_pmp_7_cfg_x,
  input         io_pmp_7_cfg_w,
  input         io_pmp_7_cfg_r,
  input  [28:0] io_pmp_7_addr,
  input  [30:0] io_pmp_7_mask,
  input  [30:0] io_addr,
  output        io_r,
  output        io_w,
  output        io_x
);
  wire  default_ = io_prv > 2'h1; // @[PMP.scala 156:56]
  wire [30:0] _res_hit_T_1 = {io_pmp_7_addr, 2'h0}; // @[PMP.scala 61:36]
  wire [30:0] _res_hit_T_2 = ~_res_hit_T_1; // @[PMP.scala 61:29]
  wire [30:0] _res_hit_T_3 = _res_hit_T_2 | 31'h3; // @[PMP.scala 61:48]
  wire [30:0] _res_hit_T_4 = ~_res_hit_T_3; // @[PMP.scala 61:27]
  wire [30:0] _res_hit_T_5 = io_addr ^ _res_hit_T_4; // @[PMP.scala 64:47]
  wire [30:0] _res_hit_T_6 = ~io_pmp_7_mask; // @[PMP.scala 64:54]
  wire [30:0] _res_hit_T_7 = _res_hit_T_5 & _res_hit_T_6; // @[PMP.scala 64:52]
  wire  _res_hit_T_8 = _res_hit_T_7 == 31'h0; // @[PMP.scala 64:58]
  wire [30:0] _res_hit_T_14 = {io_pmp_6_addr, 2'h0}; // @[PMP.scala 61:36]
  wire [30:0] _res_hit_T_15 = ~_res_hit_T_14; // @[PMP.scala 61:29]
  wire [30:0] _res_hit_T_16 = _res_hit_T_15 | 31'h3; // @[PMP.scala 61:48]
  wire [30:0] _res_hit_T_17 = ~_res_hit_T_16; // @[PMP.scala 61:27]
  wire  _res_hit_T_18 = io_addr < _res_hit_T_17; // @[PMP.scala 78:9]
  wire  _res_hit_T_19 = ~_res_hit_T_18; // @[PMP.scala 89:5]
  wire  _res_hit_T_24 = io_addr < _res_hit_T_4; // @[PMP.scala 78:9]
  wire  _res_hit_T_25 = _res_hit_T_19 & _res_hit_T_24; // @[PMP.scala 95:48]
  wire  res_hit = io_pmp_7_cfg_a[1] ? _res_hit_T_8 : io_pmp_7_cfg_a[0] & _res_hit_T_25; // @[PMP.scala 133:8]
  wire  res_ignore = default_ & ~io_pmp_7_cfg_l; // @[PMP.scala 164:26]
  wire  res_cur_cfg_r = io_pmp_7_cfg_r | res_ignore; // @[PMP.scala 182:40]
  wire  res_cur_cfg_w = io_pmp_7_cfg_w | res_ignore; // @[PMP.scala 183:40]
  wire  res_cur_cfg_x = io_pmp_7_cfg_x | res_ignore; // @[PMP.scala 184:40]
  wire  _res_T_44_cfg_x = res_hit ? res_cur_cfg_x : default_; // @[PMP.scala 185:8]
  wire  _res_T_44_cfg_w = res_hit ? res_cur_cfg_w : default_; // @[PMP.scala 185:8]
  wire  _res_T_44_cfg_r = res_hit ? res_cur_cfg_r : default_; // @[PMP.scala 185:8]
  wire [30:0] _res_hit_T_32 = io_addr ^ _res_hit_T_17; // @[PMP.scala 64:47]
  wire [30:0] _res_hit_T_33 = ~io_pmp_6_mask; // @[PMP.scala 64:54]
  wire [30:0] _res_hit_T_34 = _res_hit_T_32 & _res_hit_T_33; // @[PMP.scala 64:52]
  wire  _res_hit_T_35 = _res_hit_T_34 == 31'h0; // @[PMP.scala 64:58]
  wire [30:0] _res_hit_T_41 = {io_pmp_5_addr, 2'h0}; // @[PMP.scala 61:36]
  wire [30:0] _res_hit_T_42 = ~_res_hit_T_41; // @[PMP.scala 61:29]
  wire [30:0] _res_hit_T_43 = _res_hit_T_42 | 31'h3; // @[PMP.scala 61:48]
  wire [30:0] _res_hit_T_44 = ~_res_hit_T_43; // @[PMP.scala 61:27]
  wire  _res_hit_T_45 = io_addr < _res_hit_T_44; // @[PMP.scala 78:9]
  wire  _res_hit_T_46 = ~_res_hit_T_45; // @[PMP.scala 89:5]
  wire  _res_hit_T_52 = _res_hit_T_46 & _res_hit_T_18; // @[PMP.scala 95:48]
  wire  res_hit_1 = io_pmp_6_cfg_a[1] ? _res_hit_T_35 : io_pmp_6_cfg_a[0] & _res_hit_T_52; // @[PMP.scala 133:8]
  wire  res_ignore_1 = default_ & ~io_pmp_6_cfg_l; // @[PMP.scala 164:26]
  wire  res_cur_1_cfg_r = io_pmp_6_cfg_r | res_ignore_1; // @[PMP.scala 182:40]
  wire  res_cur_1_cfg_w = io_pmp_6_cfg_w | res_ignore_1; // @[PMP.scala 183:40]
  wire  res_cur_1_cfg_x = io_pmp_6_cfg_x | res_ignore_1; // @[PMP.scala 184:40]
  wire  _res_T_89_cfg_x = res_hit_1 ? res_cur_1_cfg_x : _res_T_44_cfg_x; // @[PMP.scala 185:8]
  wire  _res_T_89_cfg_w = res_hit_1 ? res_cur_1_cfg_w : _res_T_44_cfg_w; // @[PMP.scala 185:8]
  wire  _res_T_89_cfg_r = res_hit_1 ? res_cur_1_cfg_r : _res_T_44_cfg_r; // @[PMP.scala 185:8]
  wire [30:0] _res_hit_T_59 = io_addr ^ _res_hit_T_44; // @[PMP.scala 64:47]
  wire [30:0] _res_hit_T_60 = ~io_pmp_5_mask; // @[PMP.scala 64:54]
  wire [30:0] _res_hit_T_61 = _res_hit_T_59 & _res_hit_T_60; // @[PMP.scala 64:52]
  wire  _res_hit_T_62 = _res_hit_T_61 == 31'h0; // @[PMP.scala 64:58]
  wire [30:0] _res_hit_T_68 = {io_pmp_4_addr, 2'h0}; // @[PMP.scala 61:36]
  wire [30:0] _res_hit_T_69 = ~_res_hit_T_68; // @[PMP.scala 61:29]
  wire [30:0] _res_hit_T_70 = _res_hit_T_69 | 31'h3; // @[PMP.scala 61:48]
  wire [30:0] _res_hit_T_71 = ~_res_hit_T_70; // @[PMP.scala 61:27]
  wire  _res_hit_T_72 = io_addr < _res_hit_T_71; // @[PMP.scala 78:9]
  wire  _res_hit_T_73 = ~_res_hit_T_72; // @[PMP.scala 89:5]
  wire  _res_hit_T_79 = _res_hit_T_73 & _res_hit_T_45; // @[PMP.scala 95:48]
  wire  res_hit_2 = io_pmp_5_cfg_a[1] ? _res_hit_T_62 : io_pmp_5_cfg_a[0] & _res_hit_T_79; // @[PMP.scala 133:8]
  wire  res_ignore_2 = default_ & ~io_pmp_5_cfg_l; // @[PMP.scala 164:26]
  wire  res_cur_2_cfg_r = io_pmp_5_cfg_r | res_ignore_2; // @[PMP.scala 182:40]
  wire  res_cur_2_cfg_w = io_pmp_5_cfg_w | res_ignore_2; // @[PMP.scala 183:40]
  wire  res_cur_2_cfg_x = io_pmp_5_cfg_x | res_ignore_2; // @[PMP.scala 184:40]
  wire  _res_T_134_cfg_x = res_hit_2 ? res_cur_2_cfg_x : _res_T_89_cfg_x; // @[PMP.scala 185:8]
  wire  _res_T_134_cfg_w = res_hit_2 ? res_cur_2_cfg_w : _res_T_89_cfg_w; // @[PMP.scala 185:8]
  wire  _res_T_134_cfg_r = res_hit_2 ? res_cur_2_cfg_r : _res_T_89_cfg_r; // @[PMP.scala 185:8]
  wire [30:0] _res_hit_T_86 = io_addr ^ _res_hit_T_71; // @[PMP.scala 64:47]
  wire [30:0] _res_hit_T_87 = ~io_pmp_4_mask; // @[PMP.scala 64:54]
  wire [30:0] _res_hit_T_88 = _res_hit_T_86 & _res_hit_T_87; // @[PMP.scala 64:52]
  wire  _res_hit_T_89 = _res_hit_T_88 == 31'h0; // @[PMP.scala 64:58]
  wire [30:0] _res_hit_T_95 = {io_pmp_3_addr, 2'h0}; // @[PMP.scala 61:36]
  wire [30:0] _res_hit_T_96 = ~_res_hit_T_95; // @[PMP.scala 61:29]
  wire [30:0] _res_hit_T_97 = _res_hit_T_96 | 31'h3; // @[PMP.scala 61:48]
  wire [30:0] _res_hit_T_98 = ~_res_hit_T_97; // @[PMP.scala 61:27]
  wire  _res_hit_T_99 = io_addr < _res_hit_T_98; // @[PMP.scala 78:9]
  wire  _res_hit_T_100 = ~_res_hit_T_99; // @[PMP.scala 89:5]
  wire  _res_hit_T_106 = _res_hit_T_100 & _res_hit_T_72; // @[PMP.scala 95:48]
  wire  res_hit_3 = io_pmp_4_cfg_a[1] ? _res_hit_T_89 : io_pmp_4_cfg_a[0] & _res_hit_T_106; // @[PMP.scala 133:8]
  wire  res_ignore_3 = default_ & ~io_pmp_4_cfg_l; // @[PMP.scala 164:26]
  wire  res_cur_3_cfg_r = io_pmp_4_cfg_r | res_ignore_3; // @[PMP.scala 182:40]
  wire  res_cur_3_cfg_w = io_pmp_4_cfg_w | res_ignore_3; // @[PMP.scala 183:40]
  wire  res_cur_3_cfg_x = io_pmp_4_cfg_x | res_ignore_3; // @[PMP.scala 184:40]
  wire  _res_T_179_cfg_x = res_hit_3 ? res_cur_3_cfg_x : _res_T_134_cfg_x; // @[PMP.scala 185:8]
  wire  _res_T_179_cfg_w = res_hit_3 ? res_cur_3_cfg_w : _res_T_134_cfg_w; // @[PMP.scala 185:8]
  wire  _res_T_179_cfg_r = res_hit_3 ? res_cur_3_cfg_r : _res_T_134_cfg_r; // @[PMP.scala 185:8]
  wire [30:0] _res_hit_T_113 = io_addr ^ _res_hit_T_98; // @[PMP.scala 64:47]
  wire [30:0] _res_hit_T_114 = ~io_pmp_3_mask; // @[PMP.scala 64:54]
  wire [30:0] _res_hit_T_115 = _res_hit_T_113 & _res_hit_T_114; // @[PMP.scala 64:52]
  wire  _res_hit_T_116 = _res_hit_T_115 == 31'h0; // @[PMP.scala 64:58]
  wire [30:0] _res_hit_T_122 = {io_pmp_2_addr, 2'h0}; // @[PMP.scala 61:36]
  wire [30:0] _res_hit_T_123 = ~_res_hit_T_122; // @[PMP.scala 61:29]
  wire [30:0] _res_hit_T_124 = _res_hit_T_123 | 31'h3; // @[PMP.scala 61:48]
  wire [30:0] _res_hit_T_125 = ~_res_hit_T_124; // @[PMP.scala 61:27]
  wire  _res_hit_T_126 = io_addr < _res_hit_T_125; // @[PMP.scala 78:9]
  wire  _res_hit_T_127 = ~_res_hit_T_126; // @[PMP.scala 89:5]
  wire  _res_hit_T_133 = _res_hit_T_127 & _res_hit_T_99; // @[PMP.scala 95:48]
  wire  res_hit_4 = io_pmp_3_cfg_a[1] ? _res_hit_T_116 : io_pmp_3_cfg_a[0] & _res_hit_T_133; // @[PMP.scala 133:8]
  wire  res_ignore_4 = default_ & ~io_pmp_3_cfg_l; // @[PMP.scala 164:26]
  wire  res_cur_4_cfg_r = io_pmp_3_cfg_r | res_ignore_4; // @[PMP.scala 182:40]
  wire  res_cur_4_cfg_w = io_pmp_3_cfg_w | res_ignore_4; // @[PMP.scala 183:40]
  wire  res_cur_4_cfg_x = io_pmp_3_cfg_x | res_ignore_4; // @[PMP.scala 184:40]
  wire  _res_T_224_cfg_x = res_hit_4 ? res_cur_4_cfg_x : _res_T_179_cfg_x; // @[PMP.scala 185:8]
  wire  _res_T_224_cfg_w = res_hit_4 ? res_cur_4_cfg_w : _res_T_179_cfg_w; // @[PMP.scala 185:8]
  wire  _res_T_224_cfg_r = res_hit_4 ? res_cur_4_cfg_r : _res_T_179_cfg_r; // @[PMP.scala 185:8]
  wire [30:0] _res_hit_T_140 = io_addr ^ _res_hit_T_125; // @[PMP.scala 64:47]
  wire [30:0] _res_hit_T_141 = ~io_pmp_2_mask; // @[PMP.scala 64:54]
  wire [30:0] _res_hit_T_142 = _res_hit_T_140 & _res_hit_T_141; // @[PMP.scala 64:52]
  wire  _res_hit_T_143 = _res_hit_T_142 == 31'h0; // @[PMP.scala 64:58]
  wire [30:0] _res_hit_T_149 = {io_pmp_1_addr, 2'h0}; // @[PMP.scala 61:36]
  wire [30:0] _res_hit_T_150 = ~_res_hit_T_149; // @[PMP.scala 61:29]
  wire [30:0] _res_hit_T_151 = _res_hit_T_150 | 31'h3; // @[PMP.scala 61:48]
  wire [30:0] _res_hit_T_152 = ~_res_hit_T_151; // @[PMP.scala 61:27]
  wire  _res_hit_T_153 = io_addr < _res_hit_T_152; // @[PMP.scala 78:9]
  wire  _res_hit_T_154 = ~_res_hit_T_153; // @[PMP.scala 89:5]
  wire  _res_hit_T_160 = _res_hit_T_154 & _res_hit_T_126; // @[PMP.scala 95:48]
  wire  res_hit_5 = io_pmp_2_cfg_a[1] ? _res_hit_T_143 : io_pmp_2_cfg_a[0] & _res_hit_T_160; // @[PMP.scala 133:8]
  wire  res_ignore_5 = default_ & ~io_pmp_2_cfg_l; // @[PMP.scala 164:26]
  wire  res_cur_5_cfg_r = io_pmp_2_cfg_r | res_ignore_5; // @[PMP.scala 182:40]
  wire  res_cur_5_cfg_w = io_pmp_2_cfg_w | res_ignore_5; // @[PMP.scala 183:40]
  wire  res_cur_5_cfg_x = io_pmp_2_cfg_x | res_ignore_5; // @[PMP.scala 184:40]
  wire  _res_T_269_cfg_x = res_hit_5 ? res_cur_5_cfg_x : _res_T_224_cfg_x; // @[PMP.scala 185:8]
  wire  _res_T_269_cfg_w = res_hit_5 ? res_cur_5_cfg_w : _res_T_224_cfg_w; // @[PMP.scala 185:8]
  wire  _res_T_269_cfg_r = res_hit_5 ? res_cur_5_cfg_r : _res_T_224_cfg_r; // @[PMP.scala 185:8]
  wire [30:0] _res_hit_T_167 = io_addr ^ _res_hit_T_152; // @[PMP.scala 64:47]
  wire [30:0] _res_hit_T_168 = ~io_pmp_1_mask; // @[PMP.scala 64:54]
  wire [30:0] _res_hit_T_169 = _res_hit_T_167 & _res_hit_T_168; // @[PMP.scala 64:52]
  wire  _res_hit_T_170 = _res_hit_T_169 == 31'h0; // @[PMP.scala 64:58]
  wire [30:0] _res_hit_T_176 = {io_pmp_0_addr, 2'h0}; // @[PMP.scala 61:36]
  wire [30:0] _res_hit_T_177 = ~_res_hit_T_176; // @[PMP.scala 61:29]
  wire [30:0] _res_hit_T_178 = _res_hit_T_177 | 31'h3; // @[PMP.scala 61:48]
  wire [30:0] _res_hit_T_179 = ~_res_hit_T_178; // @[PMP.scala 61:27]
  wire  _res_hit_T_180 = io_addr < _res_hit_T_179; // @[PMP.scala 78:9]
  wire  _res_hit_T_181 = ~_res_hit_T_180; // @[PMP.scala 89:5]
  wire  _res_hit_T_187 = _res_hit_T_181 & _res_hit_T_153; // @[PMP.scala 95:48]
  wire  res_hit_6 = io_pmp_1_cfg_a[1] ? _res_hit_T_170 : io_pmp_1_cfg_a[0] & _res_hit_T_187; // @[PMP.scala 133:8]
  wire  res_ignore_6 = default_ & ~io_pmp_1_cfg_l; // @[PMP.scala 164:26]
  wire  res_cur_6_cfg_r = io_pmp_1_cfg_r | res_ignore_6; // @[PMP.scala 182:40]
  wire  res_cur_6_cfg_w = io_pmp_1_cfg_w | res_ignore_6; // @[PMP.scala 183:40]
  wire  res_cur_6_cfg_x = io_pmp_1_cfg_x | res_ignore_6; // @[PMP.scala 184:40]
  wire  _res_T_314_cfg_x = res_hit_6 ? res_cur_6_cfg_x : _res_T_269_cfg_x; // @[PMP.scala 185:8]
  wire  _res_T_314_cfg_w = res_hit_6 ? res_cur_6_cfg_w : _res_T_269_cfg_w; // @[PMP.scala 185:8]
  wire  _res_T_314_cfg_r = res_hit_6 ? res_cur_6_cfg_r : _res_T_269_cfg_r; // @[PMP.scala 185:8]
  wire [30:0] _res_hit_T_194 = io_addr ^ _res_hit_T_179; // @[PMP.scala 64:47]
  wire [30:0] _res_hit_T_195 = ~io_pmp_0_mask; // @[PMP.scala 64:54]
  wire [30:0] _res_hit_T_196 = _res_hit_T_194 & _res_hit_T_195; // @[PMP.scala 64:52]
  wire  _res_hit_T_197 = _res_hit_T_196 == 31'h0; // @[PMP.scala 64:58]
  wire  res_hit_7 = io_pmp_0_cfg_a[1] ? _res_hit_T_197 : io_pmp_0_cfg_a[0] & _res_hit_T_180; // @[PMP.scala 133:8]
  wire  res_ignore_7 = default_ & ~io_pmp_0_cfg_l; // @[PMP.scala 164:26]
  wire  res_cur_7_cfg_r = io_pmp_0_cfg_r | res_ignore_7; // @[PMP.scala 182:40]
  wire  res_cur_7_cfg_w = io_pmp_0_cfg_w | res_ignore_7; // @[PMP.scala 183:40]
  wire  res_cur_7_cfg_x = io_pmp_0_cfg_x | res_ignore_7; // @[PMP.scala 184:40]
  assign io_r = res_hit_7 ? res_cur_7_cfg_r : _res_T_314_cfg_r; // @[PMP.scala 185:8]
  assign io_w = res_hit_7 ? res_cur_7_cfg_w : _res_T_314_cfg_w; // @[PMP.scala 185:8]
  assign io_x = res_hit_7 ? res_cur_7_cfg_x : _res_T_314_cfg_x; // @[PMP.scala 185:8]
endmodule
module TLB(
  input         io_req_valid,
  input  [31:0] io_req_bits_vaddr,
  input  [1:0]  io_req_bits_size,
  input  [4:0]  io_req_bits_cmd,
  input  [1:0]  io_req_bits_prv,
  output [30:0] io_resp_paddr,
  output        io_resp_pf_ld,
  output        io_resp_pf_st,
  output        io_resp_ae_ld,
  output        io_resp_ae_st,
  output        io_resp_ma_ld,
  output        io_resp_ma_st,
  output        io_resp_cacheable,
  input         io_ptw_status_debug,
  input         io_ptw_pmp_0_cfg_l,
  input  [1:0]  io_ptw_pmp_0_cfg_a,
  input         io_ptw_pmp_0_cfg_x,
  input         io_ptw_pmp_0_cfg_w,
  input         io_ptw_pmp_0_cfg_r,
  input  [28:0] io_ptw_pmp_0_addr,
  input  [30:0] io_ptw_pmp_0_mask,
  input         io_ptw_pmp_1_cfg_l,
  input  [1:0]  io_ptw_pmp_1_cfg_a,
  input         io_ptw_pmp_1_cfg_x,
  input         io_ptw_pmp_1_cfg_w,
  input         io_ptw_pmp_1_cfg_r,
  input  [28:0] io_ptw_pmp_1_addr,
  input  [30:0] io_ptw_pmp_1_mask,
  input         io_ptw_pmp_2_cfg_l,
  input  [1:0]  io_ptw_pmp_2_cfg_a,
  input         io_ptw_pmp_2_cfg_x,
  input         io_ptw_pmp_2_cfg_w,
  input         io_ptw_pmp_2_cfg_r,
  input  [28:0] io_ptw_pmp_2_addr,
  input  [30:0] io_ptw_pmp_2_mask,
  input         io_ptw_pmp_3_cfg_l,
  input  [1:0]  io_ptw_pmp_3_cfg_a,
  input         io_ptw_pmp_3_cfg_x,
  input         io_ptw_pmp_3_cfg_w,
  input         io_ptw_pmp_3_cfg_r,
  input  [28:0] io_ptw_pmp_3_addr,
  input  [30:0] io_ptw_pmp_3_mask,
  input         io_ptw_pmp_4_cfg_l,
  input  [1:0]  io_ptw_pmp_4_cfg_a,
  input         io_ptw_pmp_4_cfg_x,
  input         io_ptw_pmp_4_cfg_w,
  input         io_ptw_pmp_4_cfg_r,
  input  [28:0] io_ptw_pmp_4_addr,
  input  [30:0] io_ptw_pmp_4_mask,
  input         io_ptw_pmp_5_cfg_l,
  input  [1:0]  io_ptw_pmp_5_cfg_a,
  input         io_ptw_pmp_5_cfg_x,
  input         io_ptw_pmp_5_cfg_w,
  input         io_ptw_pmp_5_cfg_r,
  input  [28:0] io_ptw_pmp_5_addr,
  input  [30:0] io_ptw_pmp_5_mask,
  input         io_ptw_pmp_6_cfg_l,
  input  [1:0]  io_ptw_pmp_6_cfg_a,
  input         io_ptw_pmp_6_cfg_x,
  input         io_ptw_pmp_6_cfg_w,
  input         io_ptw_pmp_6_cfg_r,
  input  [28:0] io_ptw_pmp_6_addr,
  input  [30:0] io_ptw_pmp_6_mask,
  input         io_ptw_pmp_7_cfg_l,
  input  [1:0]  io_ptw_pmp_7_cfg_a,
  input         io_ptw_pmp_7_cfg_x,
  input         io_ptw_pmp_7_cfg_w,
  input         io_ptw_pmp_7_cfg_r,
  input  [28:0] io_ptw_pmp_7_addr,
  input  [30:0] io_ptw_pmp_7_mask
);
  wire [1:0] pmp_io_prv; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_0_cfg_l; // @[TLB.scala 233:19]
  wire [1:0] pmp_io_pmp_0_cfg_a; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_0_cfg_x; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_0_cfg_w; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_0_cfg_r; // @[TLB.scala 233:19]
  wire [28:0] pmp_io_pmp_0_addr; // @[TLB.scala 233:19]
  wire [30:0] pmp_io_pmp_0_mask; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_1_cfg_l; // @[TLB.scala 233:19]
  wire [1:0] pmp_io_pmp_1_cfg_a; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_1_cfg_x; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_1_cfg_w; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_1_cfg_r; // @[TLB.scala 233:19]
  wire [28:0] pmp_io_pmp_1_addr; // @[TLB.scala 233:19]
  wire [30:0] pmp_io_pmp_1_mask; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_2_cfg_l; // @[TLB.scala 233:19]
  wire [1:0] pmp_io_pmp_2_cfg_a; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_2_cfg_x; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_2_cfg_w; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_2_cfg_r; // @[TLB.scala 233:19]
  wire [28:0] pmp_io_pmp_2_addr; // @[TLB.scala 233:19]
  wire [30:0] pmp_io_pmp_2_mask; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_3_cfg_l; // @[TLB.scala 233:19]
  wire [1:0] pmp_io_pmp_3_cfg_a; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_3_cfg_x; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_3_cfg_w; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_3_cfg_r; // @[TLB.scala 233:19]
  wire [28:0] pmp_io_pmp_3_addr; // @[TLB.scala 233:19]
  wire [30:0] pmp_io_pmp_3_mask; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_4_cfg_l; // @[TLB.scala 233:19]
  wire [1:0] pmp_io_pmp_4_cfg_a; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_4_cfg_x; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_4_cfg_w; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_4_cfg_r; // @[TLB.scala 233:19]
  wire [28:0] pmp_io_pmp_4_addr; // @[TLB.scala 233:19]
  wire [30:0] pmp_io_pmp_4_mask; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_5_cfg_l; // @[TLB.scala 233:19]
  wire [1:0] pmp_io_pmp_5_cfg_a; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_5_cfg_x; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_5_cfg_w; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_5_cfg_r; // @[TLB.scala 233:19]
  wire [28:0] pmp_io_pmp_5_addr; // @[TLB.scala 233:19]
  wire [30:0] pmp_io_pmp_5_mask; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_6_cfg_l; // @[TLB.scala 233:19]
  wire [1:0] pmp_io_pmp_6_cfg_a; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_6_cfg_x; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_6_cfg_w; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_6_cfg_r; // @[TLB.scala 233:19]
  wire [28:0] pmp_io_pmp_6_addr; // @[TLB.scala 233:19]
  wire [30:0] pmp_io_pmp_6_mask; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_7_cfg_l; // @[TLB.scala 233:19]
  wire [1:0] pmp_io_pmp_7_cfg_a; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_7_cfg_x; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_7_cfg_w; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_7_cfg_r; // @[TLB.scala 233:19]
  wire [28:0] pmp_io_pmp_7_addr; // @[TLB.scala 233:19]
  wire [30:0] pmp_io_pmp_7_mask; // @[TLB.scala 233:19]
  wire [30:0] pmp_io_addr; // @[TLB.scala 233:19]
  wire  pmp_io_r; // @[TLB.scala 233:19]
  wire  pmp_io_w; // @[TLB.scala 233:19]
  wire  pmp_io_x; // @[TLB.scala 233:19]
  wire [19:0] vpn = io_req_bits_vaddr[31:12]; // @[TLB.scala 187:30]
  wire [19:0] mpu_ppn = io_req_bits_vaddr[31:12]; // @[TLB.scala 230:144]
  wire [31:0] mpu_physaddr = {mpu_ppn,io_req_bits_vaddr[11:0]}; // @[Cat.scala 31:58]
  wire [2:0] mpu_priv = {io_ptw_status_debug,io_req_bits_prv}; // @[Cat.scala 31:58]
  wire [31:0] _legal_address_T = mpu_physaddr ^ 32'h3000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_1 = {1'b0,$signed(_legal_address_T)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_3 = $signed(_legal_address_T_1) & -33'sh1000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_4 = $signed(_legal_address_T_3) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_5 = mpu_physaddr ^ 32'h10013000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_6 = {1'b0,$signed(_legal_address_T_5)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_8 = $signed(_legal_address_T_6) & -33'sh1000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_9 = $signed(_legal_address_T_8) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_10 = mpu_physaddr ^ 32'h10023000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_11 = {1'b0,$signed(_legal_address_T_10)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_13 = $signed(_legal_address_T_11) & -33'sh1000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_14 = $signed(_legal_address_T_13) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_15 = mpu_physaddr ^ 32'h10033000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_16 = {1'b0,$signed(_legal_address_T_15)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_18 = $signed(_legal_address_T_16) & -33'sh1000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_19 = $signed(_legal_address_T_18) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_20 = mpu_physaddr ^ 32'h10043000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_21 = {1'b0,$signed(_legal_address_T_20)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_23 = $signed(_legal_address_T_21) & -33'sh1000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_24 = $signed(_legal_address_T_23) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_25 = mpu_physaddr ^ 32'h10053000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_26 = {1'b0,$signed(_legal_address_T_25)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_28 = $signed(_legal_address_T_26) & -33'sh1000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_29 = $signed(_legal_address_T_28) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_30 = mpu_physaddr ^ 32'h10014000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_31 = {1'b0,$signed(_legal_address_T_30)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_33 = $signed(_legal_address_T_31) & -33'sh1000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_34 = $signed(_legal_address_T_33) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_35 = mpu_physaddr ^ 32'h20000000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_36 = {1'b0,$signed(_legal_address_T_35)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_38 = $signed(_legal_address_T_36) & -33'sh20000000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_39 = $signed(_legal_address_T_38) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_40 = mpu_physaddr ^ 32'h10034000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_41 = {1'b0,$signed(_legal_address_T_40)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_43 = $signed(_legal_address_T_41) & -33'sh1000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_44 = $signed(_legal_address_T_43) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_45 = mpu_physaddr ^ 32'h10024000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_46 = {1'b0,$signed(_legal_address_T_45)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_48 = $signed(_legal_address_T_46) & -33'sh1000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_49 = $signed(_legal_address_T_48) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_50 = mpu_physaddr ^ 32'h10012000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_51 = {1'b0,$signed(_legal_address_T_50)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_53 = $signed(_legal_address_T_51) & -33'sh1000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_54 = $signed(_legal_address_T_53) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_55 = mpu_physaddr ^ 32'h10015000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_56 = {1'b0,$signed(_legal_address_T_55)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_58 = $signed(_legal_address_T_56) & -33'sh1000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_59 = $signed(_legal_address_T_58) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_60 = mpu_physaddr ^ 32'h10025000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_61 = {1'b0,$signed(_legal_address_T_60)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_63 = $signed(_legal_address_T_61) & -33'sh1000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_64 = $signed(_legal_address_T_63) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_65 = mpu_physaddr ^ 32'h10035000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_66 = {1'b0,$signed(_legal_address_T_65)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_68 = $signed(_legal_address_T_66) & -33'sh1000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_69 = $signed(_legal_address_T_68) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_70 = mpu_physaddr ^ 32'h10016000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_71 = {1'b0,$signed(_legal_address_T_70)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_73 = $signed(_legal_address_T_71) & -33'sh1000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_74 = $signed(_legal_address_T_73) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_75 = mpu_physaddr ^ 32'h10026000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_76 = {1'b0,$signed(_legal_address_T_75)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_78 = $signed(_legal_address_T_76) & -33'sh1000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_79 = $signed(_legal_address_T_78) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_80 = mpu_physaddr ^ 32'hc000000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_81 = {1'b0,$signed(_legal_address_T_80)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_83 = $signed(_legal_address_T_81) & -33'sh4000000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_84 = $signed(_legal_address_T_83) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_85 = mpu_physaddr ^ 32'h2000000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_86 = {1'b0,$signed(_legal_address_T_85)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_88 = $signed(_legal_address_T_86) & -33'sh10000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_89 = $signed(_legal_address_T_88) == 33'sh0; // @[Parameters.scala 137:67]
  wire [32:0] _legal_address_T_91 = {1'b0,$signed(mpu_physaddr)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_93 = $signed(_legal_address_T_91) & -33'sh1000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_94 = $signed(_legal_address_T_93) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_95 = mpu_physaddr ^ 32'h8000000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_96 = {1'b0,$signed(_legal_address_T_95)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_98 = $signed(_legal_address_T_96) & -33'sh4000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_99 = $signed(_legal_address_T_98) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_100 = mpu_physaddr ^ 32'h10000000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_101 = {1'b0,$signed(_legal_address_T_100)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_103 = $signed(_legal_address_T_101) & -33'sh1000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_104 = $signed(_legal_address_T_103) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_105 = mpu_physaddr ^ 32'h10000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_106 = {1'b0,$signed(_legal_address_T_105)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_108 = $signed(_legal_address_T_106) & -33'sh10000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_109 = $signed(_legal_address_T_108) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_110 = mpu_physaddr ^ 32'h40000000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_111 = {1'b0,$signed(_legal_address_T_110)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_113 = $signed(_legal_address_T_111) & -33'sh20000000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_114 = $signed(_legal_address_T_113) == 33'sh0; // @[Parameters.scala 137:67]
  wire  legal_address = _legal_address_T_4 | _legal_address_T_9 | _legal_address_T_14 | _legal_address_T_19 |
    _legal_address_T_24 | _legal_address_T_29 | _legal_address_T_34 | _legal_address_T_39 | _legal_address_T_44 |
    _legal_address_T_49 | _legal_address_T_54 | _legal_address_T_59 | _legal_address_T_64 | _legal_address_T_69 |
    _legal_address_T_74 | _legal_address_T_79 | _legal_address_T_84 | _legal_address_T_89 | _legal_address_T_94 |
    _legal_address_T_99 | _legal_address_T_104 | _legal_address_T_109 | _legal_address_T_114; // @[TLB.scala 238:67]
  wire [32:0] _cacheable_T_8 = $signed(_legal_address_T_111) & 33'sh40000000; // @[Parameters.scala 137:52]
  wire  _cacheable_T_9 = $signed(_cacheable_T_8) == 33'sh0; // @[Parameters.scala 137:67]
  wire  cacheable = legal_address & _cacheable_T_9; // @[TLB.scala 240:19]
  wire [32:0] _homogeneous_T_116 = $signed(_legal_address_T_111) & 33'sh60000000; // @[Parameters.scala 137:52]
  wire  _homogeneous_T_117 = $signed(_homogeneous_T_116) == 33'sh0; // @[Parameters.scala 137:67]
  wire  deny_access_to_debug = mpu_priv <= 3'h3 & _legal_address_T_94; // @[TLB.scala 243:48]
  wire  _prot_r_T_6 = ~deny_access_to_debug; // @[TLB.scala 244:44]
  wire  prot_r = legal_address & ~deny_access_to_debug & pmp_io_r; // @[TLB.scala 244:66]
  wire [32:0] _prot_w_T_3 = $signed(_legal_address_T_91) & 33'sh74010000; // @[Parameters.scala 137:52]
  wire  _prot_w_T_4 = $signed(_prot_w_T_3) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _prot_w_T_5 = mpu_physaddr ^ 32'h4000000; // @[Parameters.scala 137:31]
  wire [32:0] _prot_w_T_6 = {1'b0,$signed(_prot_w_T_5)}; // @[Parameters.scala 137:49]
  wire [32:0] _prot_w_T_8 = $signed(_prot_w_T_6) & 33'sh74000000; // @[Parameters.scala 137:52]
  wire  _prot_w_T_9 = $signed(_prot_w_T_8) == 33'sh0; // @[Parameters.scala 137:67]
  wire [32:0] _prot_w_T_13 = $signed(_legal_address_T_101) & 33'sh74000000; // @[Parameters.scala 137:52]
  wire  _prot_w_T_14 = $signed(_prot_w_T_13) == 33'sh0; // @[Parameters.scala 137:67]
  wire  _prot_w_T_21 = _prot_w_T_4 | _prot_w_T_9 | _prot_w_T_14; // @[Parameters.scala 615:89]
  wire  _prot_w_T_22 = _prot_w_T_4 | _prot_w_T_9 | _prot_w_T_14 | _homogeneous_T_117; // @[Parameters.scala 615:89]
  wire  _prot_w_T_37 = legal_address & _prot_w_T_22; // @[TLB.scala 240:19]
  wire  prot_w = _prot_w_T_37 & _prot_r_T_6 & pmp_io_w; // @[TLB.scala 245:70]
  wire  prot_pp = legal_address & _prot_w_T_21; // @[TLB.scala 240:19]
  wire [31:0] _prot_x_T_32 = mpu_physaddr ^ 32'h10042000; // @[Parameters.scala 137:31]
  wire [32:0] _prot_x_T_33 = {1'b0,$signed(_prot_x_T_32)}; // @[Parameters.scala 137:49]
  wire [32:0] _prot_eff_T_32 = $signed(_legal_address_T_91) & 33'sh6e072000; // @[Parameters.scala 137:52]
  wire  _prot_eff_T_33 = $signed(_prot_eff_T_32) == 33'sh0; // @[Parameters.scala 137:67]
  wire [32:0] _prot_eff_T_37 = $signed(_legal_address_T_86) & 33'sh7e070000; // @[Parameters.scala 137:52]
  wire  _prot_eff_T_38 = $signed(_prot_eff_T_37) == 33'sh0; // @[Parameters.scala 137:67]
  wire [32:0] _prot_eff_T_42 = $signed(_legal_address_T_81) & 33'sh7c000000; // @[Parameters.scala 137:52]
  wire  _prot_eff_T_43 = $signed(_prot_eff_T_42) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _prot_eff_T_44 = mpu_physaddr ^ 32'h10010000; // @[Parameters.scala 137:31]
  wire [32:0] _prot_eff_T_45 = {1'b0,$signed(_prot_eff_T_44)}; // @[Parameters.scala 137:49]
  wire [32:0] _prot_eff_T_47 = $signed(_prot_eff_T_45) & 33'sh7e070000; // @[Parameters.scala 137:52]
  wire  _prot_eff_T_48 = $signed(_prot_eff_T_47) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _prot_eff_T_49 = mpu_physaddr ^ 32'h10020000; // @[Parameters.scala 137:31]
  wire [32:0] _prot_eff_T_50 = {1'b0,$signed(_prot_eff_T_49)}; // @[Parameters.scala 137:49]
  wire [32:0] _prot_eff_T_52 = $signed(_prot_eff_T_50) & 33'sh7e060000; // @[Parameters.scala 137:52]
  wire  _prot_eff_T_53 = $signed(_prot_eff_T_52) == 33'sh0; // @[Parameters.scala 137:67]
  wire [32:0] _prot_eff_T_57 = $signed(_prot_x_T_33) & 33'sh7e062000; // @[Parameters.scala 137:52]
  wire  _prot_eff_T_58 = $signed(_prot_eff_T_57) == 33'sh0; // @[Parameters.scala 137:67]
  wire  _prot_eff_T_63 = _prot_eff_T_33 | _prot_eff_T_38 | _prot_eff_T_43 | _prot_eff_T_48 | _prot_eff_T_53 |
    _prot_eff_T_58; // @[Parameters.scala 615:89]
  wire  prot_eff = legal_address & _prot_eff_T_63; // @[TLB.scala 240:19]
  wire [18:0] ppn = vpn[18:0]; // @[TLB.scala 310:125]
  wire [1:0] _pr_array_T_1 = prot_r ? 2'h3 : 2'h0; // @[Bitwise.scala 74:12]
  wire [6:0] pr_array = {_pr_array_T_1,5'h0}; // @[Cat.scala 31:58]
  wire [1:0] _pw_array_T_1 = prot_w ? 2'h3 : 2'h0; // @[Bitwise.scala 74:12]
  wire [6:0] pw_array = {_pw_array_T_1,5'h0}; // @[Cat.scala 31:58]
  wire [1:0] _eff_array_T_1 = prot_eff ? 2'h3 : 2'h0; // @[Bitwise.scala 74:12]
  wire [6:0] eff_array = {_eff_array_T_1,5'h0}; // @[Cat.scala 31:58]
  wire [1:0] _c_array_T_1 = cacheable ? 2'h3 : 2'h0; // @[Bitwise.scala 74:12]
  wire [6:0] c_array = {_c_array_T_1,5'h0}; // @[Cat.scala 31:58]
  wire [1:0] _ppp_array_T_1 = prot_pp ? 2'h3 : 2'h0; // @[Bitwise.scala 74:12]
  wire [6:0] ppp_array = {_ppp_array_T_1,5'h0}; // @[Cat.scala 31:58]
  wire [6:0] ppp_array_if_cached = ppp_array | c_array; // @[TLB.scala 336:39]
  wire [3:0] _misaligned_T = 4'h1 << io_req_bits_size; // @[OneHot.scala 57:35]
  wire [3:0] _misaligned_T_2 = _misaligned_T - 4'h1; // @[TLB.scala 341:69]
  wire [31:0] _GEN_144 = {{28'd0}, _misaligned_T_2}; // @[TLB.scala 341:39]
  wire [31:0] _misaligned_T_3 = io_req_bits_vaddr & _GEN_144; // @[TLB.scala 341:39]
  wire  misaligned = |_misaligned_T_3; // @[TLB.scala 341:75]
  wire  _cmd_lrsc_T = io_req_bits_cmd == 5'h6; // @[package.scala 15:47]
  wire  _cmd_lrsc_T_1 = io_req_bits_cmd == 5'h7; // @[package.scala 15:47]
  wire  cmd_lrsc = _cmd_lrsc_T | _cmd_lrsc_T_1; // @[package.scala 72:59]
  wire  _cmd_amo_logical_T = io_req_bits_cmd == 5'h4; // @[package.scala 15:47]
  wire  _cmd_amo_logical_T_1 = io_req_bits_cmd == 5'h9; // @[package.scala 15:47]
  wire  _cmd_amo_logical_T_2 = io_req_bits_cmd == 5'ha; // @[package.scala 15:47]
  wire  _cmd_amo_logical_T_3 = io_req_bits_cmd == 5'hb; // @[package.scala 15:47]
  wire  cmd_amo_logical = _cmd_amo_logical_T | _cmd_amo_logical_T_1 | _cmd_amo_logical_T_2 | _cmd_amo_logical_T_3; // @[package.scala 72:59]
  wire  _cmd_amo_arithmetic_T = io_req_bits_cmd == 5'h8; // @[package.scala 15:47]
  wire  _cmd_amo_arithmetic_T_1 = io_req_bits_cmd == 5'hc; // @[package.scala 15:47]
  wire  _cmd_amo_arithmetic_T_2 = io_req_bits_cmd == 5'hd; // @[package.scala 15:47]
  wire  _cmd_amo_arithmetic_T_3 = io_req_bits_cmd == 5'he; // @[package.scala 15:47]
  wire  _cmd_amo_arithmetic_T_4 = io_req_bits_cmd == 5'hf; // @[package.scala 15:47]
  wire  cmd_amo_arithmetic = _cmd_amo_arithmetic_T | _cmd_amo_arithmetic_T_1 | _cmd_amo_arithmetic_T_2 |
    _cmd_amo_arithmetic_T_3 | _cmd_amo_arithmetic_T_4; // @[package.scala 72:59]
  wire  cmd_put_partial = io_req_bits_cmd == 5'h11; // @[TLB.scala 364:41]
  wire  _cmd_read_T = io_req_bits_cmd == 5'h0; // @[package.scala 15:47]
  wire  _cmd_read_T_1 = io_req_bits_cmd == 5'h10; // @[package.scala 15:47]
  wire  _cmd_read_T_6 = _cmd_read_T | _cmd_read_T_1 | _cmd_lrsc_T | _cmd_lrsc_T_1; // @[package.scala 72:59]
  wire  _cmd_read_T_23 = cmd_amo_logical | cmd_amo_arithmetic; // @[Consts.scala 82:44]
  wire  cmd_read = _cmd_read_T_6 | _cmd_read_T_23; // @[Consts.scala 84:68]
  wire  cmd_write = io_req_bits_cmd == 5'h1 | cmd_put_partial | _cmd_lrsc_T_1 | _cmd_read_T_23; // @[Consts.scala 85:76]
  wire  _cmd_write_perms_T = io_req_bits_cmd == 5'h5; // @[package.scala 15:47]
  wire  _cmd_write_perms_T_1 = io_req_bits_cmd == 5'h17; // @[package.scala 15:47]
  wire  _cmd_write_perms_T_2 = _cmd_write_perms_T | _cmd_write_perms_T_1; // @[package.scala 72:59]
  wire  cmd_write_perms = cmd_write | _cmd_write_perms_T_2; // @[TLB.scala 368:35]
  wire [6:0] _ae_array_T = misaligned ? eff_array : 7'h0; // @[TLB.scala 373:8]
  wire [6:0] _ae_array_T_1 = ~c_array; // @[TLB.scala 374:19]
  wire [6:0] _ae_array_T_2 = cmd_lrsc ? _ae_array_T_1 : 7'h0; // @[TLB.scala 374:8]
  wire [6:0] ae_array = _ae_array_T | _ae_array_T_2; // @[TLB.scala 373:37]
  wire [6:0] _ae_ld_array_T = ~pr_array; // @[TLB.scala 375:46]
  wire [6:0] _ae_ld_array_T_1 = ae_array | _ae_ld_array_T; // @[TLB.scala 375:44]
  wire [6:0] ae_ld_array = cmd_read ? _ae_ld_array_T_1 : 7'h0; // @[TLB.scala 375:24]
  wire [6:0] _ae_st_array_T = ~pw_array; // @[TLB.scala 377:37]
  wire [6:0] _ae_st_array_T_1 = ae_array | _ae_st_array_T; // @[TLB.scala 377:35]
  wire [6:0] _ae_st_array_T_2 = cmd_write_perms ? _ae_st_array_T_1 : 7'h0; // @[TLB.scala 377:8]
  wire [6:0] _ae_st_array_T_3 = ~ppp_array_if_cached; // @[TLB.scala 378:26]
  wire [6:0] _ae_st_array_T_4 = cmd_put_partial ? _ae_st_array_T_3 : 7'h0; // @[TLB.scala 378:8]
  wire [6:0] _ae_st_array_T_5 = _ae_st_array_T_2 | _ae_st_array_T_4; // @[TLB.scala 377:53]
  wire [6:0] _ae_st_array_T_7 = cmd_amo_logical ? _ae_st_array_T_3 : 7'h0; // @[TLB.scala 379:8]
  wire [6:0] _ae_st_array_T_8 = _ae_st_array_T_5 | _ae_st_array_T_7; // @[TLB.scala 378:53]
  wire [6:0] _ae_st_array_T_10 = cmd_amo_arithmetic ? _ae_st_array_T_3 : 7'h0; // @[TLB.scala 380:8]
  wire [6:0] ae_st_array = _ae_st_array_T_8 | _ae_st_array_T_10; // @[TLB.scala 379:53]
  wire [6:0] pf_ld_array = cmd_read ? 7'h3f : 7'h0; // @[TLB.scala 386:24]
  wire [6:0] pf_st_array = cmd_write_perms ? 7'h3f : 7'h0; // @[TLB.scala 387:24]
  wire [6:0] _io_resp_pf_ld_T_1 = pf_ld_array & 7'h40; // @[TLB.scala 419:57]
  wire [6:0] _io_resp_pf_st_T_1 = pf_st_array & 7'h40; // @[TLB.scala 420:64]
  wire [6:0] _io_resp_ae_ld_T = ae_ld_array & 7'h40; // @[TLB.scala 425:33]
  wire [6:0] _io_resp_ae_st_T = ae_st_array & 7'h40; // @[TLB.scala 426:33]
  wire [6:0] _io_resp_cacheable_T = c_array & 7'h40; // @[TLB.scala 431:33]
  PMPChecker pmp ( // @[TLB.scala 233:19]
    .io_prv(pmp_io_prv),
    .io_pmp_0_cfg_l(pmp_io_pmp_0_cfg_l),
    .io_pmp_0_cfg_a(pmp_io_pmp_0_cfg_a),
    .io_pmp_0_cfg_x(pmp_io_pmp_0_cfg_x),
    .io_pmp_0_cfg_w(pmp_io_pmp_0_cfg_w),
    .io_pmp_0_cfg_r(pmp_io_pmp_0_cfg_r),
    .io_pmp_0_addr(pmp_io_pmp_0_addr),
    .io_pmp_0_mask(pmp_io_pmp_0_mask),
    .io_pmp_1_cfg_l(pmp_io_pmp_1_cfg_l),
    .io_pmp_1_cfg_a(pmp_io_pmp_1_cfg_a),
    .io_pmp_1_cfg_x(pmp_io_pmp_1_cfg_x),
    .io_pmp_1_cfg_w(pmp_io_pmp_1_cfg_w),
    .io_pmp_1_cfg_r(pmp_io_pmp_1_cfg_r),
    .io_pmp_1_addr(pmp_io_pmp_1_addr),
    .io_pmp_1_mask(pmp_io_pmp_1_mask),
    .io_pmp_2_cfg_l(pmp_io_pmp_2_cfg_l),
    .io_pmp_2_cfg_a(pmp_io_pmp_2_cfg_a),
    .io_pmp_2_cfg_x(pmp_io_pmp_2_cfg_x),
    .io_pmp_2_cfg_w(pmp_io_pmp_2_cfg_w),
    .io_pmp_2_cfg_r(pmp_io_pmp_2_cfg_r),
    .io_pmp_2_addr(pmp_io_pmp_2_addr),
    .io_pmp_2_mask(pmp_io_pmp_2_mask),
    .io_pmp_3_cfg_l(pmp_io_pmp_3_cfg_l),
    .io_pmp_3_cfg_a(pmp_io_pmp_3_cfg_a),
    .io_pmp_3_cfg_x(pmp_io_pmp_3_cfg_x),
    .io_pmp_3_cfg_w(pmp_io_pmp_3_cfg_w),
    .io_pmp_3_cfg_r(pmp_io_pmp_3_cfg_r),
    .io_pmp_3_addr(pmp_io_pmp_3_addr),
    .io_pmp_3_mask(pmp_io_pmp_3_mask),
    .io_pmp_4_cfg_l(pmp_io_pmp_4_cfg_l),
    .io_pmp_4_cfg_a(pmp_io_pmp_4_cfg_a),
    .io_pmp_4_cfg_x(pmp_io_pmp_4_cfg_x),
    .io_pmp_4_cfg_w(pmp_io_pmp_4_cfg_w),
    .io_pmp_4_cfg_r(pmp_io_pmp_4_cfg_r),
    .io_pmp_4_addr(pmp_io_pmp_4_addr),
    .io_pmp_4_mask(pmp_io_pmp_4_mask),
    .io_pmp_5_cfg_l(pmp_io_pmp_5_cfg_l),
    .io_pmp_5_cfg_a(pmp_io_pmp_5_cfg_a),
    .io_pmp_5_cfg_x(pmp_io_pmp_5_cfg_x),
    .io_pmp_5_cfg_w(pmp_io_pmp_5_cfg_w),
    .io_pmp_5_cfg_r(pmp_io_pmp_5_cfg_r),
    .io_pmp_5_addr(pmp_io_pmp_5_addr),
    .io_pmp_5_mask(pmp_io_pmp_5_mask),
    .io_pmp_6_cfg_l(pmp_io_pmp_6_cfg_l),
    .io_pmp_6_cfg_a(pmp_io_pmp_6_cfg_a),
    .io_pmp_6_cfg_x(pmp_io_pmp_6_cfg_x),
    .io_pmp_6_cfg_w(pmp_io_pmp_6_cfg_w),
    .io_pmp_6_cfg_r(pmp_io_pmp_6_cfg_r),
    .io_pmp_6_addr(pmp_io_pmp_6_addr),
    .io_pmp_6_mask(pmp_io_pmp_6_mask),
    .io_pmp_7_cfg_l(pmp_io_pmp_7_cfg_l),
    .io_pmp_7_cfg_a(pmp_io_pmp_7_cfg_a),
    .io_pmp_7_cfg_x(pmp_io_pmp_7_cfg_x),
    .io_pmp_7_cfg_w(pmp_io_pmp_7_cfg_w),
    .io_pmp_7_cfg_r(pmp_io_pmp_7_cfg_r),
    .io_pmp_7_addr(pmp_io_pmp_7_addr),
    .io_pmp_7_mask(pmp_io_pmp_7_mask),
    .io_addr(pmp_io_addr),
    .io_r(pmp_io_r),
    .io_w(pmp_io_w),
    .io_x(pmp_io_x)
  );
  assign io_resp_paddr = {ppn,io_req_bits_vaddr[11:0]}; // @[Cat.scala 31:58]
  assign io_resp_pf_ld = |_io_resp_pf_ld_T_1; // @[TLB.scala 419:65]
  assign io_resp_pf_st = |_io_resp_pf_st_T_1; // @[TLB.scala 420:72]
  assign io_resp_ae_ld = |_io_resp_ae_ld_T; // @[TLB.scala 425:41]
  assign io_resp_ae_st = |_io_resp_ae_st_T; // @[TLB.scala 426:41]
  assign io_resp_ma_ld = misaligned & cmd_read; // @[TLB.scala 428:31]
  assign io_resp_ma_st = misaligned & cmd_write; // @[TLB.scala 429:31]
  assign io_resp_cacheable = |_io_resp_cacheable_T; // @[TLB.scala 431:41]
  assign pmp_io_prv = mpu_priv[1:0]; // @[TLB.scala 237:14]
  assign pmp_io_pmp_0_cfg_l = io_ptw_pmp_0_cfg_l; // @[TLB.scala 236:14]
  assign pmp_io_pmp_0_cfg_a = io_ptw_pmp_0_cfg_a; // @[TLB.scala 236:14]
  assign pmp_io_pmp_0_cfg_x = io_ptw_pmp_0_cfg_x; // @[TLB.scala 236:14]
  assign pmp_io_pmp_0_cfg_w = io_ptw_pmp_0_cfg_w; // @[TLB.scala 236:14]
  assign pmp_io_pmp_0_cfg_r = io_ptw_pmp_0_cfg_r; // @[TLB.scala 236:14]
  assign pmp_io_pmp_0_addr = io_ptw_pmp_0_addr; // @[TLB.scala 236:14]
  assign pmp_io_pmp_0_mask = io_ptw_pmp_0_mask; // @[TLB.scala 236:14]
  assign pmp_io_pmp_1_cfg_l = io_ptw_pmp_1_cfg_l; // @[TLB.scala 236:14]
  assign pmp_io_pmp_1_cfg_a = io_ptw_pmp_1_cfg_a; // @[TLB.scala 236:14]
  assign pmp_io_pmp_1_cfg_x = io_ptw_pmp_1_cfg_x; // @[TLB.scala 236:14]
  assign pmp_io_pmp_1_cfg_w = io_ptw_pmp_1_cfg_w; // @[TLB.scala 236:14]
  assign pmp_io_pmp_1_cfg_r = io_ptw_pmp_1_cfg_r; // @[TLB.scala 236:14]
  assign pmp_io_pmp_1_addr = io_ptw_pmp_1_addr; // @[TLB.scala 236:14]
  assign pmp_io_pmp_1_mask = io_ptw_pmp_1_mask; // @[TLB.scala 236:14]
  assign pmp_io_pmp_2_cfg_l = io_ptw_pmp_2_cfg_l; // @[TLB.scala 236:14]
  assign pmp_io_pmp_2_cfg_a = io_ptw_pmp_2_cfg_a; // @[TLB.scala 236:14]
  assign pmp_io_pmp_2_cfg_x = io_ptw_pmp_2_cfg_x; // @[TLB.scala 236:14]
  assign pmp_io_pmp_2_cfg_w = io_ptw_pmp_2_cfg_w; // @[TLB.scala 236:14]
  assign pmp_io_pmp_2_cfg_r = io_ptw_pmp_2_cfg_r; // @[TLB.scala 236:14]
  assign pmp_io_pmp_2_addr = io_ptw_pmp_2_addr; // @[TLB.scala 236:14]
  assign pmp_io_pmp_2_mask = io_ptw_pmp_2_mask; // @[TLB.scala 236:14]
  assign pmp_io_pmp_3_cfg_l = io_ptw_pmp_3_cfg_l; // @[TLB.scala 236:14]
  assign pmp_io_pmp_3_cfg_a = io_ptw_pmp_3_cfg_a; // @[TLB.scala 236:14]
  assign pmp_io_pmp_3_cfg_x = io_ptw_pmp_3_cfg_x; // @[TLB.scala 236:14]
  assign pmp_io_pmp_3_cfg_w = io_ptw_pmp_3_cfg_w; // @[TLB.scala 236:14]
  assign pmp_io_pmp_3_cfg_r = io_ptw_pmp_3_cfg_r; // @[TLB.scala 236:14]
  assign pmp_io_pmp_3_addr = io_ptw_pmp_3_addr; // @[TLB.scala 236:14]
  assign pmp_io_pmp_3_mask = io_ptw_pmp_3_mask; // @[TLB.scala 236:14]
  assign pmp_io_pmp_4_cfg_l = io_ptw_pmp_4_cfg_l; // @[TLB.scala 236:14]
  assign pmp_io_pmp_4_cfg_a = io_ptw_pmp_4_cfg_a; // @[TLB.scala 236:14]
  assign pmp_io_pmp_4_cfg_x = io_ptw_pmp_4_cfg_x; // @[TLB.scala 236:14]
  assign pmp_io_pmp_4_cfg_w = io_ptw_pmp_4_cfg_w; // @[TLB.scala 236:14]
  assign pmp_io_pmp_4_cfg_r = io_ptw_pmp_4_cfg_r; // @[TLB.scala 236:14]
  assign pmp_io_pmp_4_addr = io_ptw_pmp_4_addr; // @[TLB.scala 236:14]
  assign pmp_io_pmp_4_mask = io_ptw_pmp_4_mask; // @[TLB.scala 236:14]
  assign pmp_io_pmp_5_cfg_l = io_ptw_pmp_5_cfg_l; // @[TLB.scala 236:14]
  assign pmp_io_pmp_5_cfg_a = io_ptw_pmp_5_cfg_a; // @[TLB.scala 236:14]
  assign pmp_io_pmp_5_cfg_x = io_ptw_pmp_5_cfg_x; // @[TLB.scala 236:14]
  assign pmp_io_pmp_5_cfg_w = io_ptw_pmp_5_cfg_w; // @[TLB.scala 236:14]
  assign pmp_io_pmp_5_cfg_r = io_ptw_pmp_5_cfg_r; // @[TLB.scala 236:14]
  assign pmp_io_pmp_5_addr = io_ptw_pmp_5_addr; // @[TLB.scala 236:14]
  assign pmp_io_pmp_5_mask = io_ptw_pmp_5_mask; // @[TLB.scala 236:14]
  assign pmp_io_pmp_6_cfg_l = io_ptw_pmp_6_cfg_l; // @[TLB.scala 236:14]
  assign pmp_io_pmp_6_cfg_a = io_ptw_pmp_6_cfg_a; // @[TLB.scala 236:14]
  assign pmp_io_pmp_6_cfg_x = io_ptw_pmp_6_cfg_x; // @[TLB.scala 236:14]
  assign pmp_io_pmp_6_cfg_w = io_ptw_pmp_6_cfg_w; // @[TLB.scala 236:14]
  assign pmp_io_pmp_6_cfg_r = io_ptw_pmp_6_cfg_r; // @[TLB.scala 236:14]
  assign pmp_io_pmp_6_addr = io_ptw_pmp_6_addr; // @[TLB.scala 236:14]
  assign pmp_io_pmp_6_mask = io_ptw_pmp_6_mask; // @[TLB.scala 236:14]
  assign pmp_io_pmp_7_cfg_l = io_ptw_pmp_7_cfg_l; // @[TLB.scala 236:14]
  assign pmp_io_pmp_7_cfg_a = io_ptw_pmp_7_cfg_a; // @[TLB.scala 236:14]
  assign pmp_io_pmp_7_cfg_x = io_ptw_pmp_7_cfg_x; // @[TLB.scala 236:14]
  assign pmp_io_pmp_7_cfg_w = io_ptw_pmp_7_cfg_w; // @[TLB.scala 236:14]
  assign pmp_io_pmp_7_cfg_r = io_ptw_pmp_7_cfg_r; // @[TLB.scala 236:14]
  assign pmp_io_pmp_7_addr = io_ptw_pmp_7_addr; // @[TLB.scala 236:14]
  assign pmp_io_pmp_7_mask = io_ptw_pmp_7_mask; // @[TLB.scala 236:14]
  assign pmp_io_addr = mpu_physaddr[30:0]; // @[TLB.scala 234:15]
endmodule
module MaxPeriodFibonacciLFSR(
  input   clock,
  input   reset,
  input   io_increment,
  output  io_out_0,
  output  io_out_1,
  output  io_out_2,
  output  io_out_3,
  output  io_out_4,
  output  io_out_5,
  output  io_out_6,
  output  io_out_7,
  output  io_out_8,
  output  io_out_9,
  output  io_out_10,
  output  io_out_11,
  output  io_out_12,
  output  io_out_13,
  output  io_out_14,
  output  io_out_15
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
`endif // RANDOMIZE_REG_INIT
  reg  state_0; // @[PRNG.scala 55:49]
  reg  state_1; // @[PRNG.scala 55:49]
  reg  state_2; // @[PRNG.scala 55:49]
  reg  state_3; // @[PRNG.scala 55:49]
  reg  state_4; // @[PRNG.scala 55:49]
  reg  state_5; // @[PRNG.scala 55:49]
  reg  state_6; // @[PRNG.scala 55:49]
  reg  state_7; // @[PRNG.scala 55:49]
  reg  state_8; // @[PRNG.scala 55:49]
  reg  state_9; // @[PRNG.scala 55:49]
  reg  state_10; // @[PRNG.scala 55:49]
  reg  state_11; // @[PRNG.scala 55:49]
  reg  state_12; // @[PRNG.scala 55:49]
  reg  state_13; // @[PRNG.scala 55:49]
  reg  state_14; // @[PRNG.scala 55:49]
  reg  state_15; // @[PRNG.scala 55:49]
  wire  _T_2 = state_15 ^ state_13 ^ state_12 ^ state_10; // @[LFSR.scala 15:41]
  wire  _GEN_0 = io_increment ? _T_2 : state_0; // @[PRNG.scala 69:22 70:11 55:49]
  assign io_out_0 = state_0; // @[PRNG.scala 78:10]
  assign io_out_1 = state_1; // @[PRNG.scala 78:10]
  assign io_out_2 = state_2; // @[PRNG.scala 78:10]
  assign io_out_3 = state_3; // @[PRNG.scala 78:10]
  assign io_out_4 = state_4; // @[PRNG.scala 78:10]
  assign io_out_5 = state_5; // @[PRNG.scala 78:10]
  assign io_out_6 = state_6; // @[PRNG.scala 78:10]
  assign io_out_7 = state_7; // @[PRNG.scala 78:10]
  assign io_out_8 = state_8; // @[PRNG.scala 78:10]
  assign io_out_9 = state_9; // @[PRNG.scala 78:10]
  assign io_out_10 = state_10; // @[PRNG.scala 78:10]
  assign io_out_11 = state_11; // @[PRNG.scala 78:10]
  assign io_out_12 = state_12; // @[PRNG.scala 78:10]
  assign io_out_13 = state_13; // @[PRNG.scala 78:10]
  assign io_out_14 = state_14; // @[PRNG.scala 78:10]
  assign io_out_15 = state_15; // @[PRNG.scala 78:10]
  always @(posedge clock) begin
    state_0 <= reset | _GEN_0; // @[PRNG.scala 55:{49,49}]
    if (reset) begin // @[PRNG.scala 55:49]
      state_1 <= 1'h0; // @[PRNG.scala 55:49]
    end else if (io_increment) begin // @[PRNG.scala 69:22]
      state_1 <= state_0; // @[PRNG.scala 70:11]
    end
    if (reset) begin // @[PRNG.scala 55:49]
      state_2 <= 1'h0; // @[PRNG.scala 55:49]
    end else if (io_increment) begin // @[PRNG.scala 69:22]
      state_2 <= state_1; // @[PRNG.scala 70:11]
    end
    if (reset) begin // @[PRNG.scala 55:49]
      state_3 <= 1'h0; // @[PRNG.scala 55:49]
    end else if (io_increment) begin // @[PRNG.scala 69:22]
      state_3 <= state_2; // @[PRNG.scala 70:11]
    end
    if (reset) begin // @[PRNG.scala 55:49]
      state_4 <= 1'h0; // @[PRNG.scala 55:49]
    end else if (io_increment) begin // @[PRNG.scala 69:22]
      state_4 <= state_3; // @[PRNG.scala 70:11]
    end
    if (reset) begin // @[PRNG.scala 55:49]
      state_5 <= 1'h0; // @[PRNG.scala 55:49]
    end else if (io_increment) begin // @[PRNG.scala 69:22]
      state_5 <= state_4; // @[PRNG.scala 70:11]
    end
    if (reset) begin // @[PRNG.scala 55:49]
      state_6 <= 1'h0; // @[PRNG.scala 55:49]
    end else if (io_increment) begin // @[PRNG.scala 69:22]
      state_6 <= state_5; // @[PRNG.scala 70:11]
    end
    if (reset) begin // @[PRNG.scala 55:49]
      state_7 <= 1'h0; // @[PRNG.scala 55:49]
    end else if (io_increment) begin // @[PRNG.scala 69:22]
      state_7 <= state_6; // @[PRNG.scala 70:11]
    end
    if (reset) begin // @[PRNG.scala 55:49]
      state_8 <= 1'h0; // @[PRNG.scala 55:49]
    end else if (io_increment) begin // @[PRNG.scala 69:22]
      state_8 <= state_7; // @[PRNG.scala 70:11]
    end
    if (reset) begin // @[PRNG.scala 55:49]
      state_9 <= 1'h0; // @[PRNG.scala 55:49]
    end else if (io_increment) begin // @[PRNG.scala 69:22]
      state_9 <= state_8; // @[PRNG.scala 70:11]
    end
    if (reset) begin // @[PRNG.scala 55:49]
      state_10 <= 1'h0; // @[PRNG.scala 55:49]
    end else if (io_increment) begin // @[PRNG.scala 69:22]
      state_10 <= state_9; // @[PRNG.scala 70:11]
    end
    if (reset) begin // @[PRNG.scala 55:49]
      state_11 <= 1'h0; // @[PRNG.scala 55:49]
    end else if (io_increment) begin // @[PRNG.scala 69:22]
      state_11 <= state_10; // @[PRNG.scala 70:11]
    end
    if (reset) begin // @[PRNG.scala 55:49]
      state_12 <= 1'h0; // @[PRNG.scala 55:49]
    end else if (io_increment) begin // @[PRNG.scala 69:22]
      state_12 <= state_11; // @[PRNG.scala 70:11]
    end
    if (reset) begin // @[PRNG.scala 55:49]
      state_13 <= 1'h0; // @[PRNG.scala 55:49]
    end else if (io_increment) begin // @[PRNG.scala 69:22]
      state_13 <= state_12; // @[PRNG.scala 70:11]
    end
    if (reset) begin // @[PRNG.scala 55:49]
      state_14 <= 1'h0; // @[PRNG.scala 55:49]
    end else if (io_increment) begin // @[PRNG.scala 69:22]
      state_14 <= state_13; // @[PRNG.scala 70:11]
    end
    if (reset) begin // @[PRNG.scala 55:49]
      state_15 <= 1'h0; // @[PRNG.scala 55:49]
    end else if (io_increment) begin // @[PRNG.scala 69:22]
      state_15 <= state_14; // @[PRNG.scala 70:11]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  state_0 = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  state_1 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  state_2 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  state_3 = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  state_4 = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  state_5 = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  state_6 = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  state_7 = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  state_8 = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  state_9 = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  state_10 = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  state_11 = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  state_12 = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  state_13 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  state_14 = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  state_15 = _RAND_15[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module DCacheModuleImpl_Anon_1(
  input         io_in_0_valid,
  input  [31:0] io_in_0_bits_addr,
  input  [5:0]  io_in_0_bits_idx,
  input         io_in_2_valid,
  input  [31:0] io_in_2_bits_addr,
  input  [5:0]  io_in_2_bits_idx,
  input  [1:0]  io_in_2_bits_way_en,
  input  [20:0] io_in_2_bits_data,
  input         io_in_3_valid,
  input  [31:0] io_in_3_bits_addr,
  input  [5:0]  io_in_3_bits_idx,
  input  [1:0]  io_in_3_bits_way_en,
  input  [20:0] io_in_3_bits_data,
  output        io_in_4_ready,
  input         io_in_4_valid,
  input  [31:0] io_in_4_bits_addr,
  input  [5:0]  io_in_4_bits_idx,
  input  [1:0]  io_in_4_bits_way_en,
  input  [20:0] io_in_4_bits_data,
  output        io_in_5_ready,
  input         io_in_5_valid,
  input  [31:0] io_in_5_bits_addr,
  input  [5:0]  io_in_5_bits_idx,
  output        io_in_6_ready,
  input         io_in_6_valid,
  input  [31:0] io_in_6_bits_addr,
  input  [5:0]  io_in_6_bits_idx,
  input  [1:0]  io_in_6_bits_way_en,
  input  [20:0] io_in_6_bits_data,
  output        io_in_7_ready,
  input         io_in_7_valid,
  input  [31:0] io_in_7_bits_addr,
  input  [5:0]  io_in_7_bits_idx,
  input  [1:0]  io_in_7_bits_way_en,
  input  [20:0] io_in_7_bits_data,
  output        io_out_valid,
  output        io_out_bits_write,
  output [31:0] io_out_bits_addr,
  output [5:0]  io_out_bits_idx,
  output [1:0]  io_out_bits_way_en,
  output [20:0] io_out_bits_data
);
  wire [20:0] _GEN_1 = io_in_6_valid ? io_in_6_bits_data : io_in_7_bits_data; // @[Arbiter.scala 139:15 141:26 143:19]
  wire [1:0] _GEN_2 = io_in_6_valid ? io_in_6_bits_way_en : io_in_7_bits_way_en; // @[Arbiter.scala 139:15 141:26 143:19]
  wire [5:0] _GEN_3 = io_in_6_valid ? io_in_6_bits_idx : io_in_7_bits_idx; // @[Arbiter.scala 139:15 141:26 143:19]
  wire [31:0] _GEN_4 = io_in_6_valid ? io_in_6_bits_addr : io_in_7_bits_addr; // @[Arbiter.scala 139:15 141:26 143:19]
  wire [20:0] _GEN_13 = io_in_4_valid ? io_in_4_bits_data : _GEN_1; // @[Arbiter.scala 141:26 143:19]
  wire [1:0] _GEN_14 = io_in_4_valid ? io_in_4_bits_way_en : _GEN_2; // @[Arbiter.scala 141:26 143:19]
  wire [5:0] _GEN_15 = io_in_4_valid ? io_in_4_bits_idx : _GEN_3; // @[Arbiter.scala 141:26 143:19]
  wire [31:0] _GEN_16 = io_in_4_valid ? io_in_4_bits_addr : _GEN_4; // @[Arbiter.scala 141:26 143:19]
  wire [20:0] _GEN_19 = io_in_3_valid ? io_in_3_bits_data : _GEN_13; // @[Arbiter.scala 141:26 143:19]
  wire [1:0] _GEN_20 = io_in_3_valid ? io_in_3_bits_way_en : _GEN_14; // @[Arbiter.scala 141:26 143:19]
  wire [5:0] _GEN_21 = io_in_3_valid ? io_in_3_bits_idx : _GEN_15; // @[Arbiter.scala 141:26 143:19]
  wire [31:0] _GEN_22 = io_in_3_valid ? io_in_3_bits_addr : _GEN_16; // @[Arbiter.scala 141:26 143:19]
  wire [20:0] _GEN_25 = io_in_2_valid ? io_in_2_bits_data : _GEN_19; // @[Arbiter.scala 141:26 143:19]
  wire [1:0] _GEN_26 = io_in_2_valid ? io_in_2_bits_way_en : _GEN_20; // @[Arbiter.scala 141:26 143:19]
  wire [5:0] _GEN_27 = io_in_2_valid ? io_in_2_bits_idx : _GEN_21; // @[Arbiter.scala 141:26 143:19]
  wire [31:0] _GEN_28 = io_in_2_valid ? io_in_2_bits_addr : _GEN_22; // @[Arbiter.scala 141:26 143:19]
  wire  grant_7 = ~(io_in_0_valid | io_in_2_valid | io_in_3_valid | io_in_4_valid | io_in_6_valid); // @[Arbiter.scala 46:78]
  assign io_in_4_ready = ~(io_in_0_valid | io_in_2_valid | io_in_3_valid); // @[Arbiter.scala 46:78]
  assign io_in_5_ready = ~(io_in_0_valid | io_in_2_valid | io_in_3_valid | io_in_4_valid); // @[Arbiter.scala 46:78]
  assign io_in_6_ready = ~(io_in_0_valid | io_in_2_valid | io_in_3_valid | io_in_4_valid); // @[Arbiter.scala 46:78]
  assign io_in_7_ready = ~(io_in_0_valid | io_in_2_valid | io_in_3_valid | io_in_4_valid | io_in_6_valid); // @[Arbiter.scala 46:78]
  assign io_out_valid = ~grant_7 | io_in_7_valid; // @[Arbiter.scala 150:31]
  assign io_out_bits_write = io_in_0_valid | (io_in_2_valid | (io_in_3_valid | io_in_4_valid)); // @[Arbiter.scala 141:26 143:19]
  assign io_out_bits_addr = io_in_0_valid ? io_in_0_bits_addr : _GEN_28; // @[Arbiter.scala 141:26 143:19]
  assign io_out_bits_idx = io_in_0_valid ? io_in_0_bits_idx : _GEN_27; // @[Arbiter.scala 141:26 143:19]
  assign io_out_bits_way_en = io_in_0_valid ? 2'h3 : _GEN_26; // @[Arbiter.scala 141:26 143:19]
  assign io_out_bits_data = io_in_0_valid ? 21'h0 : _GEN_25; // @[Arbiter.scala 141:26 143:19]
endmodule
module DCacheDataArray(
  input         clock,
  input         io_req_valid,
  input  [11:0] io_req_bits_addr,
  input         io_req_bits_write,
  input  [31:0] io_req_bits_wdata,
  input  [3:0]  io_req_bits_eccMask,
  input  [1:0]  io_req_bits_way_en,
  output [31:0] io_resp_0,
  output [31:0] io_resp_1
);
  wire [9:0] data_arrays_0_RW0_addr; // @[DescribedSRAM.scala 19:26]
  wire  data_arrays_0_RW0_en; // @[DescribedSRAM.scala 19:26]
  wire  data_arrays_0_RW0_clk; // @[DescribedSRAM.scala 19:26]
  wire  data_arrays_0_RW0_wmode; // @[DescribedSRAM.scala 19:26]
  wire [7:0] data_arrays_0_RW0_wdata_0; // @[DescribedSRAM.scala 19:26]
  wire [7:0] data_arrays_0_RW0_wdata_1; // @[DescribedSRAM.scala 19:26]
  wire [7:0] data_arrays_0_RW0_wdata_2; // @[DescribedSRAM.scala 19:26]
  wire [7:0] data_arrays_0_RW0_wdata_3; // @[DescribedSRAM.scala 19:26]
  wire [7:0] data_arrays_0_RW0_wdata_4; // @[DescribedSRAM.scala 19:26]
  wire [7:0] data_arrays_0_RW0_wdata_5; // @[DescribedSRAM.scala 19:26]
  wire [7:0] data_arrays_0_RW0_wdata_6; // @[DescribedSRAM.scala 19:26]
  wire [7:0] data_arrays_0_RW0_wdata_7; // @[DescribedSRAM.scala 19:26]
  wire [7:0] data_arrays_0_RW0_rdata_0; // @[DescribedSRAM.scala 19:26]
  wire [7:0] data_arrays_0_RW0_rdata_1; // @[DescribedSRAM.scala 19:26]
  wire [7:0] data_arrays_0_RW0_rdata_2; // @[DescribedSRAM.scala 19:26]
  wire [7:0] data_arrays_0_RW0_rdata_3; // @[DescribedSRAM.scala 19:26]
  wire [7:0] data_arrays_0_RW0_rdata_4; // @[DescribedSRAM.scala 19:26]
  wire [7:0] data_arrays_0_RW0_rdata_5; // @[DescribedSRAM.scala 19:26]
  wire [7:0] data_arrays_0_RW0_rdata_6; // @[DescribedSRAM.scala 19:26]
  wire [7:0] data_arrays_0_RW0_rdata_7; // @[DescribedSRAM.scala 19:26]
  wire  data_arrays_0_RW0_wmask_0; // @[DescribedSRAM.scala 19:26]
  wire  data_arrays_0_RW0_wmask_1; // @[DescribedSRAM.scala 19:26]
  wire  data_arrays_0_RW0_wmask_2; // @[DescribedSRAM.scala 19:26]
  wire  data_arrays_0_RW0_wmask_3; // @[DescribedSRAM.scala 19:26]
  wire  data_arrays_0_RW0_wmask_4; // @[DescribedSRAM.scala 19:26]
  wire  data_arrays_0_RW0_wmask_5; // @[DescribedSRAM.scala 19:26]
  wire  data_arrays_0_RW0_wmask_6; // @[DescribedSRAM.scala 19:26]
  wire  data_arrays_0_RW0_wmask_7; // @[DescribedSRAM.scala 19:26]
  wire  eccMask_0 = io_req_bits_eccMask[0]; // @[DCache.scala 50:82]
  wire  eccMask_1 = io_req_bits_eccMask[1]; // @[DCache.scala 50:82]
  wire  eccMask_2 = io_req_bits_eccMask[2]; // @[DCache.scala 50:82]
  wire  eccMask_3 = io_req_bits_eccMask[3]; // @[DCache.scala 50:82]
  wire  _rdata_T = io_req_valid & io_req_bits_write; // @[DCache.scala 66:17]
  wire  _rdata_data_T_1 = io_req_valid & ~io_req_bits_write; // @[DCache.scala 71:39]
  wire [15:0] rdata_lo = {data_arrays_0_RW0_rdata_1,data_arrays_0_RW0_rdata_0}; // @[Cat.scala 31:58]
  wire [15:0] rdata_hi = {data_arrays_0_RW0_rdata_3,data_arrays_0_RW0_rdata_2}; // @[Cat.scala 31:58]
  wire [15:0] lo = {data_arrays_0_RW0_rdata_5,data_arrays_0_RW0_rdata_4}; // @[Cat.scala 31:58]
  wire [15:0] hi = {data_arrays_0_RW0_rdata_7,data_arrays_0_RW0_rdata_6}; // @[Cat.scala 31:58]
  data_arrays_0 data_arrays_0 ( // @[DescribedSRAM.scala 19:26]
    .RW0_addr(data_arrays_0_RW0_addr),
    .RW0_en(data_arrays_0_RW0_en),
    .RW0_clk(data_arrays_0_RW0_clk),
    .RW0_wmode(data_arrays_0_RW0_wmode),
    .RW0_wdata_0(data_arrays_0_RW0_wdata_0),
    .RW0_wdata_1(data_arrays_0_RW0_wdata_1),
    .RW0_wdata_2(data_arrays_0_RW0_wdata_2),
    .RW0_wdata_3(data_arrays_0_RW0_wdata_3),
    .RW0_wdata_4(data_arrays_0_RW0_wdata_4),
    .RW0_wdata_5(data_arrays_0_RW0_wdata_5),
    .RW0_wdata_6(data_arrays_0_RW0_wdata_6),
    .RW0_wdata_7(data_arrays_0_RW0_wdata_7),
    .RW0_rdata_0(data_arrays_0_RW0_rdata_0),
    .RW0_rdata_1(data_arrays_0_RW0_rdata_1),
    .RW0_rdata_2(data_arrays_0_RW0_rdata_2),
    .RW0_rdata_3(data_arrays_0_RW0_rdata_3),
    .RW0_rdata_4(data_arrays_0_RW0_rdata_4),
    .RW0_rdata_5(data_arrays_0_RW0_rdata_5),
    .RW0_rdata_6(data_arrays_0_RW0_rdata_6),
    .RW0_rdata_7(data_arrays_0_RW0_rdata_7),
    .RW0_wmask_0(data_arrays_0_RW0_wmask_0),
    .RW0_wmask_1(data_arrays_0_RW0_wmask_1),
    .RW0_wmask_2(data_arrays_0_RW0_wmask_2),
    .RW0_wmask_3(data_arrays_0_RW0_wmask_3),
    .RW0_wmask_4(data_arrays_0_RW0_wmask_4),
    .RW0_wmask_5(data_arrays_0_RW0_wmask_5),
    .RW0_wmask_6(data_arrays_0_RW0_wmask_6),
    .RW0_wmask_7(data_arrays_0_RW0_wmask_7)
  );
  assign io_resp_0 = {rdata_hi,rdata_lo}; // @[Cat.scala 31:58]
  assign io_resp_1 = {hi,lo}; // @[Cat.scala 31:58]
  assign data_arrays_0_RW0_clk = clock; // @[DCache.scala 66:39]
  assign data_arrays_0_RW0_wdata_0 = io_req_bits_wdata[7:0]; // @[package.scala 202:50]
  assign data_arrays_0_RW0_wdata_1 = io_req_bits_wdata[15:8]; // @[package.scala 202:50]
  assign data_arrays_0_RW0_wdata_2 = io_req_bits_wdata[23:16]; // @[package.scala 202:50]
  assign data_arrays_0_RW0_wdata_3 = io_req_bits_wdata[31:24]; // @[package.scala 202:50]
  assign data_arrays_0_RW0_wdata_4 = io_req_bits_wdata[7:0]; // @[package.scala 202:50]
  assign data_arrays_0_RW0_wdata_5 = io_req_bits_wdata[15:8]; // @[package.scala 202:50]
  assign data_arrays_0_RW0_wdata_6 = io_req_bits_wdata[23:16]; // @[package.scala 202:50]
  assign data_arrays_0_RW0_wdata_7 = io_req_bits_wdata[31:24]; // @[package.scala 202:50]
  assign data_arrays_0_RW0_wmask_0 = eccMask_0 & io_req_bits_way_en[0]; // @[DCache.scala 51:87]
  assign data_arrays_0_RW0_wmask_1 = eccMask_1 & io_req_bits_way_en[0]; // @[DCache.scala 51:87]
  assign data_arrays_0_RW0_wmask_2 = eccMask_2 & io_req_bits_way_en[0]; // @[DCache.scala 51:87]
  assign data_arrays_0_RW0_wmask_3 = eccMask_3 & io_req_bits_way_en[0]; // @[DCache.scala 51:87]
  assign data_arrays_0_RW0_wmask_4 = eccMask_0 & io_req_bits_way_en[1]; // @[DCache.scala 51:87]
  assign data_arrays_0_RW0_wmask_5 = eccMask_1 & io_req_bits_way_en[1]; // @[DCache.scala 51:87]
  assign data_arrays_0_RW0_wmask_6 = eccMask_2 & io_req_bits_way_en[1]; // @[DCache.scala 51:87]
  assign data_arrays_0_RW0_wmask_7 = eccMask_3 & io_req_bits_way_en[1]; // @[DCache.scala 51:87]
  assign data_arrays_0_RW0_en = _rdata_data_T_1 | _rdata_T;
  assign data_arrays_0_RW0_wmode = io_req_bits_write;
  assign data_arrays_0_RW0_addr = io_req_bits_addr[11:2]; // @[DCache.scala 53:31]
endmodule
module DCacheModuleImpl_Anon_2(
  input         io_in_0_valid,
  input  [11:0] io_in_0_bits_addr,
  input         io_in_0_bits_write,
  input  [31:0] io_in_0_bits_wdata,
  input  [3:0]  io_in_0_bits_eccMask,
  input  [1:0]  io_in_0_bits_way_en,
  output        io_in_1_ready,
  input         io_in_1_valid,
  input  [11:0] io_in_1_bits_addr,
  input         io_in_1_bits_write,
  input  [31:0] io_in_1_bits_wdata,
  input  [1:0]  io_in_1_bits_way_en,
  output        io_in_2_ready,
  input         io_in_2_valid,
  input  [11:0] io_in_2_bits_addr,
  input  [31:0] io_in_2_bits_wdata,
  output        io_in_3_ready,
  input         io_in_3_valid,
  input  [11:0] io_in_3_bits_addr,
  input  [31:0] io_in_3_bits_wdata,
  input         io_in_3_bits_wordMask,
  output        io_out_valid,
  output [11:0] io_out_bits_addr,
  output        io_out_bits_write,
  output [31:0] io_out_bits_wdata,
  output [3:0]  io_out_bits_eccMask,
  output [1:0]  io_out_bits_way_en
);
  wire [31:0] _GEN_4 = io_in_2_valid ? io_in_2_bits_wdata : io_in_3_bits_wdata; // @[Arbiter.scala 139:15 141:26 143:19]
  wire [11:0] _GEN_6 = io_in_2_valid ? io_in_2_bits_addr : io_in_3_bits_addr; // @[Arbiter.scala 139:15 141:26 143:19]
  wire [1:0] _GEN_8 = io_in_1_valid ? io_in_1_bits_way_en : 2'h3; // @[Arbiter.scala 141:26 143:19]
  wire [31:0] _GEN_11 = io_in_1_valid ? io_in_1_bits_wdata : _GEN_4; // @[Arbiter.scala 141:26 143:19]
  wire [11:0] _GEN_13 = io_in_1_valid ? io_in_1_bits_addr : _GEN_6; // @[Arbiter.scala 141:26 143:19]
  wire  grant_3 = ~(io_in_0_valid | io_in_1_valid | io_in_2_valid); // @[Arbiter.scala 46:78]
  assign io_in_1_ready = ~io_in_0_valid; // @[Arbiter.scala 46:78]
  assign io_in_2_ready = ~(io_in_0_valid | io_in_1_valid); // @[Arbiter.scala 46:78]
  assign io_in_3_ready = ~(io_in_0_valid | io_in_1_valid | io_in_2_valid); // @[Arbiter.scala 46:78]
  assign io_out_valid = ~grant_3 | io_in_3_valid; // @[Arbiter.scala 150:31]
  assign io_out_bits_addr = io_in_0_valid ? io_in_0_bits_addr : _GEN_13; // @[Arbiter.scala 141:26 143:19]
  assign io_out_bits_write = io_in_0_valid ? io_in_0_bits_write : io_in_1_valid & io_in_1_bits_write; // @[Arbiter.scala 141:26 143:19]
  assign io_out_bits_wdata = io_in_0_valid ? io_in_0_bits_wdata : _GEN_11; // @[Arbiter.scala 141:26 143:19]
  assign io_out_bits_eccMask = io_in_0_valid ? io_in_0_bits_eccMask : 4'hf; // @[Arbiter.scala 141:26 143:19]
  assign io_out_bits_way_en = io_in_0_valid ? io_in_0_bits_way_en : _GEN_8; // @[Arbiter.scala 141:26 143:19]
endmodule
module AMOALU(
  input  [3:0]  io_mask,
  input  [4:0]  io_cmd,
  input  [31:0] io_lhs,
  input  [31:0] io_rhs,
  output [31:0] io_out
);
  wire  max = io_cmd == 5'hd | io_cmd == 5'hf; // @[AMOALU.scala 64:33]
  wire  min = io_cmd == 5'hc | io_cmd == 5'he; // @[AMOALU.scala 65:33]
  wire  add = io_cmd == 5'h8; // @[AMOALU.scala 66:20]
  wire  _logic_and_T = io_cmd == 5'ha; // @[AMOALU.scala 67:26]
  wire  logic_and = io_cmd == 5'ha | io_cmd == 5'hb; // @[AMOALU.scala 67:38]
  wire  logic_xor = io_cmd == 5'h9 | _logic_and_T; // @[AMOALU.scala 68:39]
  wire [31:0] adder_out = io_lhs + io_rhs; // @[AMOALU.scala 73:21]
  wire [4:0] _less_signed_T = io_cmd & 5'h2; // @[AMOALU.scala 86:17]
  wire  less_signed = _less_signed_T == 5'h0; // @[AMOALU.scala 86:25]
  wire  _less_T_6 = io_lhs < io_rhs; // @[AMOALU.scala 79:35]
  wire  _less_T_9 = less_signed ? io_lhs[31] : io_rhs[31]; // @[AMOALU.scala 88:58]
  wire  less = io_lhs[31] == io_rhs[31] ? _less_T_6 : _less_T_9; // @[AMOALU.scala 88:10]
  wire  _minmax_T = less ? min : max; // @[AMOALU.scala 94:23]
  wire [31:0] minmax = _minmax_T ? io_lhs : io_rhs; // @[AMOALU.scala 94:19]
  wire [31:0] _logic_T = io_lhs & io_rhs; // @[AMOALU.scala 96:27]
  wire [31:0] _logic_T_1 = logic_and ? _logic_T : 32'h0; // @[AMOALU.scala 96:8]
  wire [31:0] _logic_T_2 = io_lhs ^ io_rhs; // @[AMOALU.scala 97:27]
  wire [31:0] _logic_T_3 = logic_xor ? _logic_T_2 : 32'h0; // @[AMOALU.scala 97:8]
  wire [31:0] logic_ = _logic_T_1 | _logic_T_3; // @[AMOALU.scala 96:42]
  wire [31:0] _out_T_1 = logic_and | logic_xor ? logic_ : minmax; // @[AMOALU.scala 100:8]
  wire [31:0] out = add ? adder_out : _out_T_1; // @[AMOALU.scala 99:8]
  wire [7:0] _wmask_T_5 = io_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _wmask_T_7 = io_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _wmask_T_9 = io_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _wmask_T_11 = io_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [31:0] wmask = {_wmask_T_11,_wmask_T_9,_wmask_T_7,_wmask_T_5}; // @[Cat.scala 31:58]
  wire [31:0] _io_out_T = wmask & out; // @[AMOALU.scala 104:19]
  wire [31:0] _io_out_T_1 = ~wmask; // @[AMOALU.scala 104:27]
  wire [31:0] _io_out_T_2 = _io_out_T_1 & io_lhs; // @[AMOALU.scala 104:34]
  assign io_out = _io_out_T | _io_out_T_2; // @[AMOALU.scala 104:25]
endmodule
module DCache(
  input         clock,
  input         reset,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [3:0]  auto_out_a_bits_size,
  output        auto_out_a_bits_source,
  output [30:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_b_ready,
  input         auto_out_b_valid,
  input  [1:0]  auto_out_b_bits_param,
  input  [3:0]  auto_out_b_bits_size,
  input         auto_out_b_bits_source,
  input  [30:0] auto_out_b_bits_address,
  input         auto_out_c_ready,
  output        auto_out_c_valid,
  output [2:0]  auto_out_c_bits_opcode,
  output [2:0]  auto_out_c_bits_param,
  output [3:0]  auto_out_c_bits_size,
  output        auto_out_c_bits_source,
  output [30:0] auto_out_c_bits_address,
  output [31:0] auto_out_c_bits_data,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_param,
  input  [3:0]  auto_out_d_bits_size,
  input         auto_out_d_bits_source,
  input  [1:0]  auto_out_d_bits_sink,
  input         auto_out_d_bits_denied,
  input  [31:0] auto_out_d_bits_data,
  input         auto_out_e_ready,
  output        auto_out_e_valid,
  output [1:0]  auto_out_e_bits_sink,
  output        io_cpu_req_ready,
  input         io_cpu_req_valid,
  input  [31:0] io_cpu_req_bits_addr,
  input  [5:0]  io_cpu_req_bits_tag,
  input  [4:0]  io_cpu_req_bits_cmd,
  input  [1:0]  io_cpu_req_bits_size,
  input         io_cpu_req_bits_signed,
  input  [1:0]  io_cpu_req_bits_dprv,
  input         io_cpu_s1_kill,
  input  [31:0] io_cpu_s1_data_data,
  input  [3:0]  io_cpu_s1_data_mask,
  output        io_cpu_s2_nack,
  output        io_cpu_resp_valid,
  output [31:0] io_cpu_resp_bits_addr,
  output [5:0]  io_cpu_resp_bits_tag,
  output [4:0]  io_cpu_resp_bits_cmd,
  output [1:0]  io_cpu_resp_bits_size,
  output        io_cpu_resp_bits_signed,
  output [1:0]  io_cpu_resp_bits_dprv,
  output        io_cpu_resp_bits_dv,
  output [31:0] io_cpu_resp_bits_data,
  output [3:0]  io_cpu_resp_bits_mask,
  output        io_cpu_resp_bits_replay,
  output        io_cpu_resp_bits_has_data,
  output [31:0] io_cpu_resp_bits_data_word_bypass,
  output [31:0] io_cpu_resp_bits_data_raw,
  output [31:0] io_cpu_resp_bits_store_data,
  output        io_cpu_replay_next,
  output        io_cpu_s2_xcpt_ma_ld,
  output        io_cpu_s2_xcpt_ma_st,
  output        io_cpu_s2_xcpt_pf_ld,
  output        io_cpu_s2_xcpt_pf_st,
  output        io_cpu_s2_xcpt_gf_ld,
  output        io_cpu_s2_xcpt_gf_st,
  output        io_cpu_s2_xcpt_ae_ld,
  output        io_cpu_s2_xcpt_ae_st,
  output        io_cpu_ordered,
  output        io_cpu_perf_release,
  output        io_cpu_perf_grant,
  input         io_ptw_status_debug,
  input         io_ptw_pmp_0_cfg_l,
  input  [1:0]  io_ptw_pmp_0_cfg_a,
  input         io_ptw_pmp_0_cfg_x,
  input         io_ptw_pmp_0_cfg_w,
  input         io_ptw_pmp_0_cfg_r,
  input  [28:0] io_ptw_pmp_0_addr,
  input  [30:0] io_ptw_pmp_0_mask,
  input         io_ptw_pmp_1_cfg_l,
  input  [1:0]  io_ptw_pmp_1_cfg_a,
  input         io_ptw_pmp_1_cfg_x,
  input         io_ptw_pmp_1_cfg_w,
  input         io_ptw_pmp_1_cfg_r,
  input  [28:0] io_ptw_pmp_1_addr,
  input  [30:0] io_ptw_pmp_1_mask,
  input         io_ptw_pmp_2_cfg_l,
  input  [1:0]  io_ptw_pmp_2_cfg_a,
  input         io_ptw_pmp_2_cfg_x,
  input         io_ptw_pmp_2_cfg_w,
  input         io_ptw_pmp_2_cfg_r,
  input  [28:0] io_ptw_pmp_2_addr,
  input  [30:0] io_ptw_pmp_2_mask,
  input         io_ptw_pmp_3_cfg_l,
  input  [1:0]  io_ptw_pmp_3_cfg_a,
  input         io_ptw_pmp_3_cfg_x,
  input         io_ptw_pmp_3_cfg_w,
  input         io_ptw_pmp_3_cfg_r,
  input  [28:0] io_ptw_pmp_3_addr,
  input  [30:0] io_ptw_pmp_3_mask,
  input         io_ptw_pmp_4_cfg_l,
  input  [1:0]  io_ptw_pmp_4_cfg_a,
  input         io_ptw_pmp_4_cfg_x,
  input         io_ptw_pmp_4_cfg_w,
  input         io_ptw_pmp_4_cfg_r,
  input  [28:0] io_ptw_pmp_4_addr,
  input  [30:0] io_ptw_pmp_4_mask,
  input         io_ptw_pmp_5_cfg_l,
  input  [1:0]  io_ptw_pmp_5_cfg_a,
  input         io_ptw_pmp_5_cfg_x,
  input         io_ptw_pmp_5_cfg_w,
  input         io_ptw_pmp_5_cfg_r,
  input  [28:0] io_ptw_pmp_5_addr,
  input  [30:0] io_ptw_pmp_5_mask,
  input         io_ptw_pmp_6_cfg_l,
  input  [1:0]  io_ptw_pmp_6_cfg_a,
  input         io_ptw_pmp_6_cfg_x,
  input         io_ptw_pmp_6_cfg_w,
  input         io_ptw_pmp_6_cfg_r,
  input  [28:0] io_ptw_pmp_6_addr,
  input  [30:0] io_ptw_pmp_6_mask,
  input         io_ptw_pmp_7_cfg_l,
  input  [1:0]  io_ptw_pmp_7_cfg_a,
  input         io_ptw_pmp_7_cfg_x,
  input         io_ptw_pmp_7_cfg_w,
  input         io_ptw_pmp_7_cfg_r,
  input  [28:0] io_ptw_pmp_7_addr,
  input  [30:0] io_ptw_pmp_7_mask
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [31:0] _RAND_33;
  reg [31:0] _RAND_34;
  reg [31:0] _RAND_35;
  reg [31:0] _RAND_36;
  reg [31:0] _RAND_37;
  reg [31:0] _RAND_38;
  reg [31:0] _RAND_39;
  reg [31:0] _RAND_40;
  reg [31:0] _RAND_41;
  reg [31:0] _RAND_42;
  reg [31:0] _RAND_43;
  reg [31:0] _RAND_44;
  reg [31:0] _RAND_45;
  reg [31:0] _RAND_46;
  reg [31:0] _RAND_47;
  reg [31:0] _RAND_48;
  reg [31:0] _RAND_49;
  reg [31:0] _RAND_50;
  reg [31:0] _RAND_51;
  reg [31:0] _RAND_52;
  reg [31:0] _RAND_53;
  reg [31:0] _RAND_54;
  reg [31:0] _RAND_55;
  reg [31:0] _RAND_56;
  reg [31:0] _RAND_57;
  reg [31:0] _RAND_58;
  reg [31:0] _RAND_59;
  reg [31:0] _RAND_60;
  reg [31:0] _RAND_61;
  reg [31:0] _RAND_62;
  reg [31:0] _RAND_63;
  reg [31:0] _RAND_64;
  reg [31:0] _RAND_65;
  reg [31:0] _RAND_66;
  reg [31:0] _RAND_67;
  reg [31:0] _RAND_68;
  reg [31:0] _RAND_69;
  reg [31:0] _RAND_70;
  reg [31:0] _RAND_71;
  reg [31:0] _RAND_72;
  reg [31:0] _RAND_73;
  reg [31:0] _RAND_74;
  reg [31:0] _RAND_75;
  reg [31:0] _RAND_76;
  reg [31:0] _RAND_77;
  reg [31:0] _RAND_78;
  reg [31:0] _RAND_79;
  reg [31:0] _RAND_80;
  reg [31:0] _RAND_81;
  reg [31:0] _RAND_82;
  reg [31:0] _RAND_83;
  reg [31:0] _RAND_84;
  reg [31:0] _RAND_85;
  reg [31:0] _RAND_86;
`endif // RANDOMIZE_REG_INIT
  wire  tlb_io_req_valid; // @[DCache.scala 117:19]
  wire [31:0] tlb_io_req_bits_vaddr; // @[DCache.scala 117:19]
  wire [1:0] tlb_io_req_bits_size; // @[DCache.scala 117:19]
  wire [4:0] tlb_io_req_bits_cmd; // @[DCache.scala 117:19]
  wire [1:0] tlb_io_req_bits_prv; // @[DCache.scala 117:19]
  wire [30:0] tlb_io_resp_paddr; // @[DCache.scala 117:19]
  wire  tlb_io_resp_pf_ld; // @[DCache.scala 117:19]
  wire  tlb_io_resp_pf_st; // @[DCache.scala 117:19]
  wire  tlb_io_resp_ae_ld; // @[DCache.scala 117:19]
  wire  tlb_io_resp_ae_st; // @[DCache.scala 117:19]
  wire  tlb_io_resp_ma_ld; // @[DCache.scala 117:19]
  wire  tlb_io_resp_ma_st; // @[DCache.scala 117:19]
  wire  tlb_io_resp_cacheable; // @[DCache.scala 117:19]
  wire  tlb_io_ptw_status_debug; // @[DCache.scala 117:19]
  wire  tlb_io_ptw_pmp_0_cfg_l; // @[DCache.scala 117:19]
  wire [1:0] tlb_io_ptw_pmp_0_cfg_a; // @[DCache.scala 117:19]
  wire  tlb_io_ptw_pmp_0_cfg_x; // @[DCache.scala 117:19]
  wire  tlb_io_ptw_pmp_0_cfg_w; // @[DCache.scala 117:19]
  wire  tlb_io_ptw_pmp_0_cfg_r; // @[DCache.scala 117:19]
  wire [28:0] tlb_io_ptw_pmp_0_addr; // @[DCache.scala 117:19]
  wire [30:0] tlb_io_ptw_pmp_0_mask; // @[DCache.scala 117:19]
  wire  tlb_io_ptw_pmp_1_cfg_l; // @[DCache.scala 117:19]
  wire [1:0] tlb_io_ptw_pmp_1_cfg_a; // @[DCache.scala 117:19]
  wire  tlb_io_ptw_pmp_1_cfg_x; // @[DCache.scala 117:19]
  wire  tlb_io_ptw_pmp_1_cfg_w; // @[DCache.scala 117:19]
  wire  tlb_io_ptw_pmp_1_cfg_r; // @[DCache.scala 117:19]
  wire [28:0] tlb_io_ptw_pmp_1_addr; // @[DCache.scala 117:19]
  wire [30:0] tlb_io_ptw_pmp_1_mask; // @[DCache.scala 117:19]
  wire  tlb_io_ptw_pmp_2_cfg_l; // @[DCache.scala 117:19]
  wire [1:0] tlb_io_ptw_pmp_2_cfg_a; // @[DCache.scala 117:19]
  wire  tlb_io_ptw_pmp_2_cfg_x; // @[DCache.scala 117:19]
  wire  tlb_io_ptw_pmp_2_cfg_w; // @[DCache.scala 117:19]
  wire  tlb_io_ptw_pmp_2_cfg_r; // @[DCache.scala 117:19]
  wire [28:0] tlb_io_ptw_pmp_2_addr; // @[DCache.scala 117:19]
  wire [30:0] tlb_io_ptw_pmp_2_mask; // @[DCache.scala 117:19]
  wire  tlb_io_ptw_pmp_3_cfg_l; // @[DCache.scala 117:19]
  wire [1:0] tlb_io_ptw_pmp_3_cfg_a; // @[DCache.scala 117:19]
  wire  tlb_io_ptw_pmp_3_cfg_x; // @[DCache.scala 117:19]
  wire  tlb_io_ptw_pmp_3_cfg_w; // @[DCache.scala 117:19]
  wire  tlb_io_ptw_pmp_3_cfg_r; // @[DCache.scala 117:19]
  wire [28:0] tlb_io_ptw_pmp_3_addr; // @[DCache.scala 117:19]
  wire [30:0] tlb_io_ptw_pmp_3_mask; // @[DCache.scala 117:19]
  wire  tlb_io_ptw_pmp_4_cfg_l; // @[DCache.scala 117:19]
  wire [1:0] tlb_io_ptw_pmp_4_cfg_a; // @[DCache.scala 117:19]
  wire  tlb_io_ptw_pmp_4_cfg_x; // @[DCache.scala 117:19]
  wire  tlb_io_ptw_pmp_4_cfg_w; // @[DCache.scala 117:19]
  wire  tlb_io_ptw_pmp_4_cfg_r; // @[DCache.scala 117:19]
  wire [28:0] tlb_io_ptw_pmp_4_addr; // @[DCache.scala 117:19]
  wire [30:0] tlb_io_ptw_pmp_4_mask; // @[DCache.scala 117:19]
  wire  tlb_io_ptw_pmp_5_cfg_l; // @[DCache.scala 117:19]
  wire [1:0] tlb_io_ptw_pmp_5_cfg_a; // @[DCache.scala 117:19]
  wire  tlb_io_ptw_pmp_5_cfg_x; // @[DCache.scala 117:19]
  wire  tlb_io_ptw_pmp_5_cfg_w; // @[DCache.scala 117:19]
  wire  tlb_io_ptw_pmp_5_cfg_r; // @[DCache.scala 117:19]
  wire [28:0] tlb_io_ptw_pmp_5_addr; // @[DCache.scala 117:19]
  wire [30:0] tlb_io_ptw_pmp_5_mask; // @[DCache.scala 117:19]
  wire  tlb_io_ptw_pmp_6_cfg_l; // @[DCache.scala 117:19]
  wire [1:0] tlb_io_ptw_pmp_6_cfg_a; // @[DCache.scala 117:19]
  wire  tlb_io_ptw_pmp_6_cfg_x; // @[DCache.scala 117:19]
  wire  tlb_io_ptw_pmp_6_cfg_w; // @[DCache.scala 117:19]
  wire  tlb_io_ptw_pmp_6_cfg_r; // @[DCache.scala 117:19]
  wire [28:0] tlb_io_ptw_pmp_6_addr; // @[DCache.scala 117:19]
  wire [30:0] tlb_io_ptw_pmp_6_mask; // @[DCache.scala 117:19]
  wire  tlb_io_ptw_pmp_7_cfg_l; // @[DCache.scala 117:19]
  wire [1:0] tlb_io_ptw_pmp_7_cfg_a; // @[DCache.scala 117:19]
  wire  tlb_io_ptw_pmp_7_cfg_x; // @[DCache.scala 117:19]
  wire  tlb_io_ptw_pmp_7_cfg_w; // @[DCache.scala 117:19]
  wire  tlb_io_ptw_pmp_7_cfg_r; // @[DCache.scala 117:19]
  wire [28:0] tlb_io_ptw_pmp_7_addr; // @[DCache.scala 117:19]
  wire [30:0] tlb_io_ptw_pmp_7_mask; // @[DCache.scala 117:19]
  wire  pma_checker_io_req_valid; // @[DCache.scala 118:27]
  wire [31:0] pma_checker_io_req_bits_vaddr; // @[DCache.scala 118:27]
  wire [1:0] pma_checker_io_req_bits_size; // @[DCache.scala 118:27]
  wire [4:0] pma_checker_io_req_bits_cmd; // @[DCache.scala 118:27]
  wire [1:0] pma_checker_io_req_bits_prv; // @[DCache.scala 118:27]
  wire [30:0] pma_checker_io_resp_paddr; // @[DCache.scala 118:27]
  wire  pma_checker_io_resp_pf_ld; // @[DCache.scala 118:27]
  wire  pma_checker_io_resp_pf_st; // @[DCache.scala 118:27]
  wire  pma_checker_io_resp_ae_ld; // @[DCache.scala 118:27]
  wire  pma_checker_io_resp_ae_st; // @[DCache.scala 118:27]
  wire  pma_checker_io_resp_ma_ld; // @[DCache.scala 118:27]
  wire  pma_checker_io_resp_ma_st; // @[DCache.scala 118:27]
  wire  pma_checker_io_resp_cacheable; // @[DCache.scala 118:27]
  wire  pma_checker_io_ptw_status_debug; // @[DCache.scala 118:27]
  wire  pma_checker_io_ptw_pmp_0_cfg_l; // @[DCache.scala 118:27]
  wire [1:0] pma_checker_io_ptw_pmp_0_cfg_a; // @[DCache.scala 118:27]
  wire  pma_checker_io_ptw_pmp_0_cfg_x; // @[DCache.scala 118:27]
  wire  pma_checker_io_ptw_pmp_0_cfg_w; // @[DCache.scala 118:27]
  wire  pma_checker_io_ptw_pmp_0_cfg_r; // @[DCache.scala 118:27]
  wire [28:0] pma_checker_io_ptw_pmp_0_addr; // @[DCache.scala 118:27]
  wire [30:0] pma_checker_io_ptw_pmp_0_mask; // @[DCache.scala 118:27]
  wire  pma_checker_io_ptw_pmp_1_cfg_l; // @[DCache.scala 118:27]
  wire [1:0] pma_checker_io_ptw_pmp_1_cfg_a; // @[DCache.scala 118:27]
  wire  pma_checker_io_ptw_pmp_1_cfg_x; // @[DCache.scala 118:27]
  wire  pma_checker_io_ptw_pmp_1_cfg_w; // @[DCache.scala 118:27]
  wire  pma_checker_io_ptw_pmp_1_cfg_r; // @[DCache.scala 118:27]
  wire [28:0] pma_checker_io_ptw_pmp_1_addr; // @[DCache.scala 118:27]
  wire [30:0] pma_checker_io_ptw_pmp_1_mask; // @[DCache.scala 118:27]
  wire  pma_checker_io_ptw_pmp_2_cfg_l; // @[DCache.scala 118:27]
  wire [1:0] pma_checker_io_ptw_pmp_2_cfg_a; // @[DCache.scala 118:27]
  wire  pma_checker_io_ptw_pmp_2_cfg_x; // @[DCache.scala 118:27]
  wire  pma_checker_io_ptw_pmp_2_cfg_w; // @[DCache.scala 118:27]
  wire  pma_checker_io_ptw_pmp_2_cfg_r; // @[DCache.scala 118:27]
  wire [28:0] pma_checker_io_ptw_pmp_2_addr; // @[DCache.scala 118:27]
  wire [30:0] pma_checker_io_ptw_pmp_2_mask; // @[DCache.scala 118:27]
  wire  pma_checker_io_ptw_pmp_3_cfg_l; // @[DCache.scala 118:27]
  wire [1:0] pma_checker_io_ptw_pmp_3_cfg_a; // @[DCache.scala 118:27]
  wire  pma_checker_io_ptw_pmp_3_cfg_x; // @[DCache.scala 118:27]
  wire  pma_checker_io_ptw_pmp_3_cfg_w; // @[DCache.scala 118:27]
  wire  pma_checker_io_ptw_pmp_3_cfg_r; // @[DCache.scala 118:27]
  wire [28:0] pma_checker_io_ptw_pmp_3_addr; // @[DCache.scala 118:27]
  wire [30:0] pma_checker_io_ptw_pmp_3_mask; // @[DCache.scala 118:27]
  wire  pma_checker_io_ptw_pmp_4_cfg_l; // @[DCache.scala 118:27]
  wire [1:0] pma_checker_io_ptw_pmp_4_cfg_a; // @[DCache.scala 118:27]
  wire  pma_checker_io_ptw_pmp_4_cfg_x; // @[DCache.scala 118:27]
  wire  pma_checker_io_ptw_pmp_4_cfg_w; // @[DCache.scala 118:27]
  wire  pma_checker_io_ptw_pmp_4_cfg_r; // @[DCache.scala 118:27]
  wire [28:0] pma_checker_io_ptw_pmp_4_addr; // @[DCache.scala 118:27]
  wire [30:0] pma_checker_io_ptw_pmp_4_mask; // @[DCache.scala 118:27]
  wire  pma_checker_io_ptw_pmp_5_cfg_l; // @[DCache.scala 118:27]
  wire [1:0] pma_checker_io_ptw_pmp_5_cfg_a; // @[DCache.scala 118:27]
  wire  pma_checker_io_ptw_pmp_5_cfg_x; // @[DCache.scala 118:27]
  wire  pma_checker_io_ptw_pmp_5_cfg_w; // @[DCache.scala 118:27]
  wire  pma_checker_io_ptw_pmp_5_cfg_r; // @[DCache.scala 118:27]
  wire [28:0] pma_checker_io_ptw_pmp_5_addr; // @[DCache.scala 118:27]
  wire [30:0] pma_checker_io_ptw_pmp_5_mask; // @[DCache.scala 118:27]
  wire  pma_checker_io_ptw_pmp_6_cfg_l; // @[DCache.scala 118:27]
  wire [1:0] pma_checker_io_ptw_pmp_6_cfg_a; // @[DCache.scala 118:27]
  wire  pma_checker_io_ptw_pmp_6_cfg_x; // @[DCache.scala 118:27]
  wire  pma_checker_io_ptw_pmp_6_cfg_w; // @[DCache.scala 118:27]
  wire  pma_checker_io_ptw_pmp_6_cfg_r; // @[DCache.scala 118:27]
  wire [28:0] pma_checker_io_ptw_pmp_6_addr; // @[DCache.scala 118:27]
  wire [30:0] pma_checker_io_ptw_pmp_6_mask; // @[DCache.scala 118:27]
  wire  pma_checker_io_ptw_pmp_7_cfg_l; // @[DCache.scala 118:27]
  wire [1:0] pma_checker_io_ptw_pmp_7_cfg_a; // @[DCache.scala 118:27]
  wire  pma_checker_io_ptw_pmp_7_cfg_x; // @[DCache.scala 118:27]
  wire  pma_checker_io_ptw_pmp_7_cfg_w; // @[DCache.scala 118:27]
  wire  pma_checker_io_ptw_pmp_7_cfg_r; // @[DCache.scala 118:27]
  wire [28:0] pma_checker_io_ptw_pmp_7_addr; // @[DCache.scala 118:27]
  wire [30:0] pma_checker_io_ptw_pmp_7_mask; // @[DCache.scala 118:27]
  wire  lfsr_prng_clock; // @[PRNG.scala 91:22]
  wire  lfsr_prng_reset; // @[PRNG.scala 91:22]
  wire  lfsr_prng_io_increment; // @[PRNG.scala 91:22]
  wire  lfsr_prng_io_out_0; // @[PRNG.scala 91:22]
  wire  lfsr_prng_io_out_1; // @[PRNG.scala 91:22]
  wire  lfsr_prng_io_out_2; // @[PRNG.scala 91:22]
  wire  lfsr_prng_io_out_3; // @[PRNG.scala 91:22]
  wire  lfsr_prng_io_out_4; // @[PRNG.scala 91:22]
  wire  lfsr_prng_io_out_5; // @[PRNG.scala 91:22]
  wire  lfsr_prng_io_out_6; // @[PRNG.scala 91:22]
  wire  lfsr_prng_io_out_7; // @[PRNG.scala 91:22]
  wire  lfsr_prng_io_out_8; // @[PRNG.scala 91:22]
  wire  lfsr_prng_io_out_9; // @[PRNG.scala 91:22]
  wire  lfsr_prng_io_out_10; // @[PRNG.scala 91:22]
  wire  lfsr_prng_io_out_11; // @[PRNG.scala 91:22]
  wire  lfsr_prng_io_out_12; // @[PRNG.scala 91:22]
  wire  lfsr_prng_io_out_13; // @[PRNG.scala 91:22]
  wire  lfsr_prng_io_out_14; // @[PRNG.scala 91:22]
  wire  lfsr_prng_io_out_15; // @[PRNG.scala 91:22]
  wire  metaArb_io_in_0_valid; // @[DCache.scala 122:23]
  wire [31:0] metaArb_io_in_0_bits_addr; // @[DCache.scala 122:23]
  wire [5:0] metaArb_io_in_0_bits_idx; // @[DCache.scala 122:23]
  wire  metaArb_io_in_2_valid; // @[DCache.scala 122:23]
  wire [31:0] metaArb_io_in_2_bits_addr; // @[DCache.scala 122:23]
  wire [5:0] metaArb_io_in_2_bits_idx; // @[DCache.scala 122:23]
  wire [1:0] metaArb_io_in_2_bits_way_en; // @[DCache.scala 122:23]
  wire [20:0] metaArb_io_in_2_bits_data; // @[DCache.scala 122:23]
  wire  metaArb_io_in_3_valid; // @[DCache.scala 122:23]
  wire [31:0] metaArb_io_in_3_bits_addr; // @[DCache.scala 122:23]
  wire [5:0] metaArb_io_in_3_bits_idx; // @[DCache.scala 122:23]
  wire [1:0] metaArb_io_in_3_bits_way_en; // @[DCache.scala 122:23]
  wire [20:0] metaArb_io_in_3_bits_data; // @[DCache.scala 122:23]
  wire  metaArb_io_in_4_ready; // @[DCache.scala 122:23]
  wire  metaArb_io_in_4_valid; // @[DCache.scala 122:23]
  wire [31:0] metaArb_io_in_4_bits_addr; // @[DCache.scala 122:23]
  wire [5:0] metaArb_io_in_4_bits_idx; // @[DCache.scala 122:23]
  wire [1:0] metaArb_io_in_4_bits_way_en; // @[DCache.scala 122:23]
  wire [20:0] metaArb_io_in_4_bits_data; // @[DCache.scala 122:23]
  wire  metaArb_io_in_5_ready; // @[DCache.scala 122:23]
  wire  metaArb_io_in_5_valid; // @[DCache.scala 122:23]
  wire [31:0] metaArb_io_in_5_bits_addr; // @[DCache.scala 122:23]
  wire [5:0] metaArb_io_in_5_bits_idx; // @[DCache.scala 122:23]
  wire  metaArb_io_in_6_ready; // @[DCache.scala 122:23]
  wire  metaArb_io_in_6_valid; // @[DCache.scala 122:23]
  wire [31:0] metaArb_io_in_6_bits_addr; // @[DCache.scala 122:23]
  wire [5:0] metaArb_io_in_6_bits_idx; // @[DCache.scala 122:23]
  wire [1:0] metaArb_io_in_6_bits_way_en; // @[DCache.scala 122:23]
  wire [20:0] metaArb_io_in_6_bits_data; // @[DCache.scala 122:23]
  wire  metaArb_io_in_7_ready; // @[DCache.scala 122:23]
  wire  metaArb_io_in_7_valid; // @[DCache.scala 122:23]
  wire [31:0] metaArb_io_in_7_bits_addr; // @[DCache.scala 122:23]
  wire [5:0] metaArb_io_in_7_bits_idx; // @[DCache.scala 122:23]
  wire [1:0] metaArb_io_in_7_bits_way_en; // @[DCache.scala 122:23]
  wire [20:0] metaArb_io_in_7_bits_data; // @[DCache.scala 122:23]
  wire  metaArb_io_out_valid; // @[DCache.scala 122:23]
  wire  metaArb_io_out_bits_write; // @[DCache.scala 122:23]
  wire [31:0] metaArb_io_out_bits_addr; // @[DCache.scala 122:23]
  wire [5:0] metaArb_io_out_bits_idx; // @[DCache.scala 122:23]
  wire [1:0] metaArb_io_out_bits_way_en; // @[DCache.scala 122:23]
  wire [20:0] metaArb_io_out_bits_data; // @[DCache.scala 122:23]
  wire [5:0] tag_array_RW0_addr; // @[DescribedSRAM.scala 19:26]
  wire  tag_array_RW0_en; // @[DescribedSRAM.scala 19:26]
  wire  tag_array_RW0_clk; // @[DescribedSRAM.scala 19:26]
  wire  tag_array_RW0_wmode; // @[DescribedSRAM.scala 19:26]
  wire [20:0] tag_array_RW0_wdata_0; // @[DescribedSRAM.scala 19:26]
  wire [20:0] tag_array_RW0_wdata_1; // @[DescribedSRAM.scala 19:26]
  wire [20:0] tag_array_RW0_rdata_0; // @[DescribedSRAM.scala 19:26]
  wire [20:0] tag_array_RW0_rdata_1; // @[DescribedSRAM.scala 19:26]
  wire  tag_array_RW0_wmask_0; // @[DescribedSRAM.scala 19:26]
  wire  tag_array_RW0_wmask_1; // @[DescribedSRAM.scala 19:26]
  wire  data_clock; // @[DCache.scala 132:20]
  wire  data_io_req_valid; // @[DCache.scala 132:20]
  wire [11:0] data_io_req_bits_addr; // @[DCache.scala 132:20]
  wire  data_io_req_bits_write; // @[DCache.scala 132:20]
  wire [31:0] data_io_req_bits_wdata; // @[DCache.scala 132:20]
  wire [3:0] data_io_req_bits_eccMask; // @[DCache.scala 132:20]
  wire [1:0] data_io_req_bits_way_en; // @[DCache.scala 132:20]
  wire [31:0] data_io_resp_0; // @[DCache.scala 132:20]
  wire [31:0] data_io_resp_1; // @[DCache.scala 132:20]
  wire  dataArb_io_in_0_valid; // @[DCache.scala 133:23]
  wire [11:0] dataArb_io_in_0_bits_addr; // @[DCache.scala 133:23]
  wire  dataArb_io_in_0_bits_write; // @[DCache.scala 133:23]
  wire [31:0] dataArb_io_in_0_bits_wdata; // @[DCache.scala 133:23]
  wire [3:0] dataArb_io_in_0_bits_eccMask; // @[DCache.scala 133:23]
  wire [1:0] dataArb_io_in_0_bits_way_en; // @[DCache.scala 133:23]
  wire  dataArb_io_in_1_ready; // @[DCache.scala 133:23]
  wire  dataArb_io_in_1_valid; // @[DCache.scala 133:23]
  wire [11:0] dataArb_io_in_1_bits_addr; // @[DCache.scala 133:23]
  wire  dataArb_io_in_1_bits_write; // @[DCache.scala 133:23]
  wire [31:0] dataArb_io_in_1_bits_wdata; // @[DCache.scala 133:23]
  wire [1:0] dataArb_io_in_1_bits_way_en; // @[DCache.scala 133:23]
  wire  dataArb_io_in_2_ready; // @[DCache.scala 133:23]
  wire  dataArb_io_in_2_valid; // @[DCache.scala 133:23]
  wire [11:0] dataArb_io_in_2_bits_addr; // @[DCache.scala 133:23]
  wire [31:0] dataArb_io_in_2_bits_wdata; // @[DCache.scala 133:23]
  wire  dataArb_io_in_3_ready; // @[DCache.scala 133:23]
  wire  dataArb_io_in_3_valid; // @[DCache.scala 133:23]
  wire [11:0] dataArb_io_in_3_bits_addr; // @[DCache.scala 133:23]
  wire [31:0] dataArb_io_in_3_bits_wdata; // @[DCache.scala 133:23]
  wire  dataArb_io_in_3_bits_wordMask; // @[DCache.scala 133:23]
  wire  dataArb_io_out_valid; // @[DCache.scala 133:23]
  wire [11:0] dataArb_io_out_bits_addr; // @[DCache.scala 133:23]
  wire  dataArb_io_out_bits_write; // @[DCache.scala 133:23]
  wire [31:0] dataArb_io_out_bits_wdata; // @[DCache.scala 133:23]
  wire [3:0] dataArb_io_out_bits_eccMask; // @[DCache.scala 133:23]
  wire [1:0] dataArb_io_out_bits_way_en; // @[DCache.scala 133:23]
  wire [3:0] amoalu_io_mask; // @[DCache.scala 956:26]
  wire [4:0] amoalu_io_cmd; // @[DCache.scala 956:26]
  wire [31:0] amoalu_io_lhs; // @[DCache.scala 956:26]
  wire [31:0] amoalu_io_rhs; // @[DCache.scala 956:26]
  wire [31:0] amoalu_io_out; // @[DCache.scala 956:26]
  wire [7:0] lfsr_lo = {lfsr_prng_io_out_7,lfsr_prng_io_out_6,lfsr_prng_io_out_5,lfsr_prng_io_out_4,lfsr_prng_io_out_3,
    lfsr_prng_io_out_2,lfsr_prng_io_out_1,lfsr_prng_io_out_0}; // @[PRNG.scala 95:17]
  wire [15:0] lfsr = {lfsr_prng_io_out_15,lfsr_prng_io_out_14,lfsr_prng_io_out_13,lfsr_prng_io_out_12,
    lfsr_prng_io_out_11,lfsr_prng_io_out_10,lfsr_prng_io_out_9,lfsr_prng_io_out_8,lfsr_lo}; // @[PRNG.scala 95:17]
  wire  s1_valid_x12 = io_cpu_req_ready & io_cpu_req_valid; // @[Decoupled.scala 50:35]
  reg  s1_valid; // @[DCache.scala 162:21]
  reg [2:0] blockProbeAfterGrantCount; // @[DCache.scala 643:38]
  wire  _block_probe_for_core_progress_T = blockProbeAfterGrantCount > 3'h0; // @[DCache.scala 741:65]
  reg [6:0] lrscCount; // @[DCache.scala 447:22]
  wire  lrscValid = lrscCount > 7'h3; // @[DCache.scala 448:29]
  wire  block_probe_for_core_progress = blockProbeAfterGrantCount > 3'h0 | lrscValid; // @[DCache.scala 741:69]
  reg  s1_probe; // @[DCache.scala 163:21]
  reg  s2_probe; // @[DCache.scala 308:21]
  reg [3:0] release_state; // @[DCache.scala 208:26]
  wire  releaseInFlight = s1_probe | s2_probe | release_state != 4'h0; // @[DCache.scala 309:46]
  reg  release_ack_wait; // @[DCache.scala 206:29]
  reg [30:0] release_ack_addr; // @[DCache.scala 207:29]
  wire [30:0] _block_probe_for_pending_release_ack_T = auto_out_b_bits_address ^ release_ack_addr; // @[DCache.scala 742:88]
  wire  block_probe_for_pending_release_ack = release_ack_wait & _block_probe_for_pending_release_ack_T[21:6] == 16'h0; // @[DCache.scala 742:62]
  reg  grantInProgress; // @[DCache.scala 642:28]
  wire  block_probe_for_ordering = releaseInFlight | block_probe_for_pending_release_ack | grantInProgress; // @[DCache.scala 743:89]
  reg  s2_valid; // @[DCache.scala 306:21]
  wire  tl_out__b_ready = metaArb_io_in_6_ready & ~(block_probe_for_core_progress | block_probe_for_ordering | s1_valid
     | s2_valid); // @[DCache.scala 745:44]
  wire  s1_probe_x16 = tl_out__b_ready & auto_out_b_valid; // @[Decoupled.scala 50:35]
  reg [1:0] probe_bits_param; // @[Reg.scala 16:16]
  reg [3:0] probe_bits_size; // @[Reg.scala 16:16]
  reg  probe_bits_source; // @[Reg.scala 16:16]
  reg [30:0] probe_bits_address; // @[Reg.scala 16:16]
  wire  s1_valid_masked = s1_valid & ~io_cpu_s1_kill; // @[DCache.scala 166:34]
  reg [1:0] s2_probe_state_state; // @[Reg.scala 16:16]
  wire [3:0] _T_118 = {probe_bits_param,s2_probe_state_state}; // @[Cat.scala 31:58]
  wire  _T_175 = 4'h3 == _T_118; // @[Misc.scala 55:20]
  wire  _T_171 = 4'h2 == _T_118; // @[Misc.scala 55:20]
  wire  _T_167 = 4'h1 == _T_118; // @[Misc.scala 55:20]
  wire  _T_163 = 4'h0 == _T_118; // @[Misc.scala 55:20]
  wire  _T_159 = 4'h7 == _T_118; // @[Misc.scala 55:20]
  wire  _T_155 = 4'h6 == _T_118; // @[Misc.scala 55:20]
  wire  _T_151 = 4'h5 == _T_118; // @[Misc.scala 55:20]
  wire  _T_147 = 4'h4 == _T_118; // @[Misc.scala 55:20]
  wire  _T_143 = 4'hb == _T_118; // @[Misc.scala 55:20]
  wire  _T_139 = 4'ha == _T_118; // @[Misc.scala 55:20]
  wire  _T_135 = 4'h9 == _T_118; // @[Misc.scala 55:20]
  wire  _T_131 = 4'h8 == _T_118; // @[Misc.scala 55:20]
  wire  _T_148 = _T_147 ? 1'h0 : _T_143; // @[Misc.scala 37:9]
  wire  _T_152 = _T_151 ? 1'h0 : _T_148; // @[Misc.scala 37:9]
  wire  _T_156 = _T_155 ? 1'h0 : _T_152; // @[Misc.scala 37:9]
  wire  _T_164 = _T_163 ? 1'h0 : _T_159 | _T_156; // @[Misc.scala 37:9]
  wire  _T_168 = _T_167 ? 1'h0 : _T_164; // @[Misc.scala 37:9]
  wire  _T_172 = _T_171 ? 1'h0 : _T_168; // @[Misc.scala 37:9]
  wire  s2_prb_ack_data = _T_175 | _T_172; // @[Misc.scala 37:9]
  wire  _T_304 = s2_probe_state_state > 2'h0; // @[Metadata.scala 49:45]
  reg [9:0] counter_1; // @[Edges.scala 228:27]
  wire  _T_309 = release_state == 4'h1; // @[package.scala 15:47]
  wire  _T_310 = release_state == 4'h6; // @[package.scala 15:47]
  wire  _T_311 = release_state == 4'h9; // @[package.scala 15:47]
  wire  _T_313 = _T_309 | _T_310 | _T_311; // @[package.scala 72:59]
  wire [2:0] _GEN_332 = _T_311 ? 3'h6 : 3'h7; // @[DCache.scala 839:52 840:23 845:23]
  wire  _T_308 = release_state == 4'h2; // @[DCache.scala 834:25]
  wire [2:0] _GEN_324 = release_state == 4'h2 ? 3'h5 : 3'h4; // @[DCache.scala 834:48 835:21]
  wire [2:0] tl_out__c_bits_opcode = _T_313 ? _GEN_332 : _GEN_324; // @[DCache.scala 838:102]
  wire  beats1_opdata_1 = tl_out__c_bits_opcode[0]; // @[Edges.scala 101:36]
  wire [3:0] tl_out__c_bits_size = _T_313 ? 4'h6 : probe_bits_size; // @[DCache.scala 838:102]
  wire [26:0] _beats1_decode_T_5 = 27'hfff << tl_out__c_bits_size; // @[package.scala 234:77]
  wire [11:0] _beats1_decode_T_7 = ~_beats1_decode_T_5[11:0]; // @[package.scala 234:46]
  wire [9:0] beats1_decode_1 = _beats1_decode_T_7[11:2]; // @[Edges.scala 219:59]
  wire [9:0] beats1_1 = beats1_opdata_1 ? beats1_decode_1 : 10'h0; // @[Edges.scala 220:14]
  wire  c_last = counter_1 == 10'h1 | beats1_1 == 10'h0; // @[Edges.scala 231:37]
  reg  s2_release_data_valid; // @[DCache.scala 777:34]
  wire  c_first = counter_1 == 10'h0; // @[Edges.scala 230:25]
  wire  _GEN_273 = s2_prb_ack_data ? s2_release_data_valid & ~(c_first & release_ack_wait) : 1'h1; // @[DCache.scala 785:18 803:36]
  wire  _GEN_294 = s2_probe ? _GEN_273 : s2_release_data_valid & ~(c_first & release_ack_wait); // @[DCache.scala 785:18 799:21]
  wire  _GEN_311 = release_state == 4'h5 | _GEN_294; // @[DCache.scala 825:47 826:22]
  wire  tl_out__c_valid = release_state == 4'h3 | _GEN_311; // @[DCache.scala 829:48 830:22]
  wire  _T_298 = auto_out_c_ready & tl_out__c_valid; // @[Decoupled.scala 50:35]
  wire  releaseDone = c_last & _T_298; // @[Edges.scala 232:22]
  wire  _GEN_271 = _T_304 | ~releaseDone; // @[DCache.scala 805:45 811:19]
  wire  probeNack = s2_prb_ack_data | _GEN_271; // @[DCache.scala 803:36]
  reg [4:0] s1_req_cmd; // @[Reg.scala 16:16]
  wire  _s1_read_T = s1_req_cmd == 5'h0; // @[package.scala 15:47]
  wire  _s1_read_T_1 = s1_req_cmd == 5'h10; // @[package.scala 15:47]
  wire  _s1_read_T_2 = s1_req_cmd == 5'h6; // @[package.scala 15:47]
  wire  _s1_read_T_3 = s1_req_cmd == 5'h7; // @[package.scala 15:47]
  wire  _s1_read_T_6 = _s1_read_T | _s1_read_T_1 | _s1_read_T_2 | _s1_read_T_3; // @[package.scala 72:59]
  wire  _s1_read_T_7 = s1_req_cmd == 5'h4; // @[package.scala 15:47]
  wire  _s1_read_T_8 = s1_req_cmd == 5'h9; // @[package.scala 15:47]
  wire  _s1_read_T_9 = s1_req_cmd == 5'ha; // @[package.scala 15:47]
  wire  _s1_read_T_10 = s1_req_cmd == 5'hb; // @[package.scala 15:47]
  wire  _s1_read_T_13 = _s1_read_T_7 | _s1_read_T_8 | _s1_read_T_9 | _s1_read_T_10; // @[package.scala 72:59]
  wire  _s1_read_T_14 = s1_req_cmd == 5'h8; // @[package.scala 15:47]
  wire  _s1_read_T_15 = s1_req_cmd == 5'hc; // @[package.scala 15:47]
  wire  _s1_read_T_16 = s1_req_cmd == 5'hd; // @[package.scala 15:47]
  wire  _s1_read_T_17 = s1_req_cmd == 5'he; // @[package.scala 15:47]
  wire  _s1_read_T_18 = s1_req_cmd == 5'hf; // @[package.scala 15:47]
  wire  _s1_read_T_22 = _s1_read_T_14 | _s1_read_T_15 | _s1_read_T_16 | _s1_read_T_17 | _s1_read_T_18; // @[package.scala 72:59]
  wire  _s1_read_T_23 = _s1_read_T_13 | _s1_read_T_22; // @[Consts.scala 82:44]
  wire  s1_read = _s1_read_T_6 | _s1_read_T_23; // @[Consts.scala 84:68]
  reg [4:0] s2_req_cmd; // @[DCache.scala 314:19]
  wire  _s2_write_T_1 = s2_req_cmd == 5'h11; // @[Consts.scala 85:49]
  wire  _s2_write_T_3 = s2_req_cmd == 5'h7; // @[Consts.scala 85:66]
  wire  _s2_write_T_5 = s2_req_cmd == 5'h4; // @[package.scala 15:47]
  wire  _s2_write_T_6 = s2_req_cmd == 5'h9; // @[package.scala 15:47]
  wire  _s2_write_T_7 = s2_req_cmd == 5'ha; // @[package.scala 15:47]
  wire  _s2_write_T_8 = s2_req_cmd == 5'hb; // @[package.scala 15:47]
  wire  _s2_write_T_11 = _s2_write_T_5 | _s2_write_T_6 | _s2_write_T_7 | _s2_write_T_8; // @[package.scala 72:59]
  wire  _s2_write_T_12 = s2_req_cmd == 5'h8; // @[package.scala 15:47]
  wire  _s2_write_T_13 = s2_req_cmd == 5'hc; // @[package.scala 15:47]
  wire  _s2_write_T_14 = s2_req_cmd == 5'hd; // @[package.scala 15:47]
  wire  _s2_write_T_15 = s2_req_cmd == 5'he; // @[package.scala 15:47]
  wire  _s2_write_T_16 = s2_req_cmd == 5'hf; // @[package.scala 15:47]
  wire  _s2_write_T_20 = _s2_write_T_12 | _s2_write_T_13 | _s2_write_T_14 | _s2_write_T_15 | _s2_write_T_16; // @[package.scala 72:59]
  wire  _s2_write_T_21 = _s2_write_T_11 | _s2_write_T_20; // @[Consts.scala 82:44]
  wire  s2_write = s2_req_cmd == 5'h1 | s2_req_cmd == 5'h11 | s2_req_cmd == 5'h7 | _s2_write_T_21; // @[Consts.scala 85:76]
  reg  pstore1_held; // @[DCache.scala 479:29]
  wire  pstore1_valid_likely = s2_valid & s2_write | pstore1_held; // @[DCache.scala 480:51]
  reg [31:0] pstore1_addr; // @[Reg.scala 16:16]
  reg [31:0] s1_req_addr; // @[Reg.scala 16:16]
  wire [31:0] s1_vaddr = {s1_req_addr[31:12],s1_req_addr[11:0]}; // @[Cat.scala 31:58]
  wire  _s1_write_T_1 = s1_req_cmd == 5'h11; // @[Consts.scala 85:49]
  wire  s1_write = s1_req_cmd == 5'h1 | s1_req_cmd == 5'h11 | _s1_read_T_3 | _s1_read_T_23; // @[Consts.scala 85:76]
  reg [3:0] pstore1_mask; // @[Reg.scala 16:16]
  wire  _s1_hazard_T_10 = |pstore1_mask[3]; // @[DCache.scala 1155:66]
  wire  _s1_hazard_T_9 = |pstore1_mask[2]; // @[DCache.scala 1155:66]
  wire  _s1_hazard_T_8 = |pstore1_mask[1]; // @[DCache.scala 1155:66]
  wire  _s1_hazard_T_7 = |pstore1_mask[0]; // @[DCache.scala 1155:66]
  wire [3:0] _s1_hazard_T_11 = {_s1_hazard_T_10,_s1_hazard_T_9,_s1_hazard_T_8,_s1_hazard_T_7}; // @[Cat.scala 31:58]
  wire [3:0] _s1_hazard_T_16 = {_s1_hazard_T_11[3],_s1_hazard_T_11[2],_s1_hazard_T_11[1],_s1_hazard_T_11[0]}; // @[Cat.scala 31:58]
  reg [1:0] s1_req_size; // @[Reg.scala 16:16]
  wire  s1_mask_xwr_upper = s1_req_addr[0] | s1_req_size >= 2'h1; // @[AMOALU.scala 17:46]
  wire  s1_mask_xwr_lower = s1_req_addr[0] ? 1'h0 : 1'h1; // @[AMOALU.scala 18:22]
  wire [1:0] _s1_mask_xwr_T = {s1_mask_xwr_upper,s1_mask_xwr_lower}; // @[Cat.scala 31:58]
  wire [1:0] _s1_mask_xwr_upper_T_5 = s1_req_addr[1] ? _s1_mask_xwr_T : 2'h0; // @[AMOALU.scala 17:22]
  wire [1:0] _s1_mask_xwr_upper_T_7 = s1_req_size >= 2'h2 ? 2'h3 : 2'h0; // @[AMOALU.scala 17:51]
  wire [1:0] s1_mask_xwr_upper_1 = _s1_mask_xwr_upper_T_5 | _s1_mask_xwr_upper_T_7; // @[AMOALU.scala 17:46]
  wire [1:0] s1_mask_xwr_lower_1 = s1_req_addr[1] ? 2'h0 : _s1_mask_xwr_T; // @[AMOALU.scala 18:22]
  wire [3:0] s1_mask_xwr = {s1_mask_xwr_upper_1,s1_mask_xwr_lower_1}; // @[Cat.scala 31:58]
  wire  _s1_hazard_T_24 = |s1_mask_xwr[3]; // @[DCache.scala 1155:66]
  wire  _s1_hazard_T_23 = |s1_mask_xwr[2]; // @[DCache.scala 1155:66]
  wire  _s1_hazard_T_22 = |s1_mask_xwr[1]; // @[DCache.scala 1155:66]
  wire  _s1_hazard_T_21 = |s1_mask_xwr[0]; // @[DCache.scala 1155:66]
  wire [3:0] _s1_hazard_T_25 = {_s1_hazard_T_24,_s1_hazard_T_23,_s1_hazard_T_22,_s1_hazard_T_21}; // @[Cat.scala 31:58]
  wire [3:0] _s1_hazard_T_30 = {_s1_hazard_T_25[3],_s1_hazard_T_25[2],_s1_hazard_T_25[1],_s1_hazard_T_25[0]}; // @[Cat.scala 31:58]
  wire [3:0] _s1_hazard_T_31 = _s1_hazard_T_16 & _s1_hazard_T_30; // @[DCache.scala 537:38]
  wire [3:0] _s1_hazard_T_33 = pstore1_mask & s1_mask_xwr; // @[DCache.scala 537:77]
  wire  _s1_hazard_T_35 = s1_write ? |_s1_hazard_T_31 : |_s1_hazard_T_33; // @[DCache.scala 537:8]
  wire  _s1_hazard_T_36 = pstore1_addr[11:2] == s1_vaddr[11:2] & _s1_hazard_T_35; // @[DCache.scala 536:65]
  reg  pstore2_valid; // @[DCache.scala 476:30]
  reg [31:0] pstore2_addr; // @[Reg.scala 16:16]
  reg [3:0] mask; // @[DCache.scala 506:19]
  wire  _s1_hazard_T_48 = |mask[3]; // @[DCache.scala 1155:66]
  wire  _s1_hazard_T_47 = |mask[2]; // @[DCache.scala 1155:66]
  wire  _s1_hazard_T_46 = |mask[1]; // @[DCache.scala 1155:66]
  wire  _s1_hazard_T_45 = |mask[0]; // @[DCache.scala 1155:66]
  wire [3:0] _s1_hazard_T_49 = {_s1_hazard_T_48,_s1_hazard_T_47,_s1_hazard_T_46,_s1_hazard_T_45}; // @[Cat.scala 31:58]
  wire [3:0] _s1_hazard_T_54 = {_s1_hazard_T_49[3],_s1_hazard_T_49[2],_s1_hazard_T_49[1],_s1_hazard_T_49[0]}; // @[Cat.scala 31:58]
  wire [3:0] _s1_hazard_T_69 = _s1_hazard_T_54 & _s1_hazard_T_30; // @[DCache.scala 537:38]
  wire [3:0] _s1_hazard_T_71 = mask & s1_mask_xwr; // @[DCache.scala 537:77]
  wire  _s1_hazard_T_73 = s1_write ? |_s1_hazard_T_69 : |_s1_hazard_T_71; // @[DCache.scala 537:8]
  wire  _s1_hazard_T_74 = pstore2_addr[11:2] == s1_vaddr[11:2] & _s1_hazard_T_73; // @[DCache.scala 536:65]
  wire  _s1_hazard_T_75 = pstore2_valid & _s1_hazard_T_74; // @[DCache.scala 540:21]
  wire  s1_hazard = pstore1_valid_likely & _s1_hazard_T_36 | _s1_hazard_T_75; // @[DCache.scala 539:69]
  wire  s1_raw_hazard = s1_read & s1_hazard; // @[DCache.scala 541:31]
  wire [7:0] _s2_valid_no_xcpt_T = {io_cpu_s2_xcpt_ma_ld,io_cpu_s2_xcpt_ma_st,io_cpu_s2_xcpt_pf_ld,io_cpu_s2_xcpt_pf_st,
    io_cpu_s2_xcpt_gf_ld,io_cpu_s2_xcpt_gf_st,io_cpu_s2_xcpt_ae_ld,io_cpu_s2_xcpt_ae_st}; // @[DCache.scala 307:54]
  wire  s2_valid_no_xcpt = s2_valid & ~(|_s2_valid_no_xcpt_T); // @[DCache.scala 307:35]
  reg  s2_not_nacked_in_s1; // @[DCache.scala 310:36]
  wire  s2_valid_masked = s2_valid_no_xcpt & s2_not_nacked_in_s1; // @[DCache.scala 312:42]
  wire  _c_cat_T_48 = s2_req_cmd == 5'h6; // @[Consts.scala 86:71]
  wire  _c_cat_T_49 = s2_write | s2_req_cmd == 5'h3 | s2_req_cmd == 5'h6; // @[Consts.scala 86:64]
  reg [1:0] s2_hit_state_state; // @[Reg.scala 16:16]
  wire [3:0] _T_55 = {s2_write,_c_cat_T_49,s2_hit_state_state}; // @[Cat.scala 31:58]
  wire  _T_113 = 4'h3 == _T_55; // @[Misc.scala 48:20]
  wire  _T_110 = 4'h2 == _T_55; // @[Misc.scala 48:20]
  wire  _T_107 = 4'h1 == _T_55; // @[Misc.scala 48:20]
  wire  _T_104 = 4'h7 == _T_55; // @[Misc.scala 48:20]
  wire  _T_101 = 4'h6 == _T_55; // @[Misc.scala 48:20]
  wire  _T_98 = 4'hf == _T_55; // @[Misc.scala 48:20]
  wire  _T_95 = 4'he == _T_55; // @[Misc.scala 48:20]
  wire  _T_92 = 4'h0 == _T_55; // @[Misc.scala 48:20]
  wire  _T_89 = 4'h5 == _T_55; // @[Misc.scala 48:20]
  wire  _T_86 = 4'h4 == _T_55; // @[Misc.scala 48:20]
  wire  _T_83 = 4'hd == _T_55; // @[Misc.scala 48:20]
  wire  _T_80 = 4'hc == _T_55; // @[Misc.scala 48:20]
  wire  s2_hit = _T_113 | (_T_110 | (_T_107 | (_T_104 | (_T_101 | (_T_98 | _T_95))))); // @[Misc.scala 34:9]
  wire  s2_valid_hit_maybe_flush_pre_data_ecc_and_waw = s2_valid_masked & s2_hit; // @[DCache.scala 372:89]
  wire  _s2_read_T = s2_req_cmd == 5'h0; // @[package.scala 15:47]
  wire  _s2_read_T_1 = s2_req_cmd == 5'h10; // @[package.scala 15:47]
  wire  _s2_read_T_6 = _s2_read_T | _s2_read_T_1 | _c_cat_T_48 | _s2_write_T_3; // @[package.scala 72:59]
  wire  s2_read = _s2_read_T_6 | _s2_write_T_21; // @[Consts.scala 84:68]
  wire  s2_readwrite = s2_read | s2_write; // @[DCache.scala 329:30]
  wire  s2_valid_hit_pre_data_ecc_and_waw = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw & s2_readwrite; // @[DCache.scala 393:89]
  wire [1:0] _T_82 = _T_80 ? 2'h1 : 2'h0; // @[Misc.scala 34:36]
  wire [1:0] _T_85 = _T_83 ? 2'h2 : _T_82; // @[Misc.scala 34:36]
  wire [1:0] _T_88 = _T_86 ? 2'h1 : _T_85; // @[Misc.scala 34:36]
  wire [1:0] _T_91 = _T_89 ? 2'h2 : _T_88; // @[Misc.scala 34:36]
  wire [1:0] _T_94 = _T_92 ? 2'h0 : _T_91; // @[Misc.scala 34:36]
  wire [1:0] _T_97 = _T_95 ? 2'h3 : _T_94; // @[Misc.scala 34:36]
  wire [1:0] _T_100 = _T_98 ? 2'h3 : _T_97; // @[Misc.scala 34:36]
  wire [1:0] _T_103 = _T_101 ? 2'h2 : _T_100; // @[Misc.scala 34:36]
  wire [1:0] _T_106 = _T_104 ? 2'h3 : _T_103; // @[Misc.scala 34:36]
  wire [1:0] _T_109 = _T_107 ? 2'h1 : _T_106; // @[Misc.scala 34:36]
  wire [1:0] _T_112 = _T_110 ? 2'h2 : _T_109; // @[Misc.scala 34:36]
  wire [1:0] s2_grow_param = _T_113 ? 2'h3 : _T_112; // @[Misc.scala 34:36]
  wire  _s2_update_meta_T = s2_hit_state_state == s2_grow_param; // @[Metadata.scala 45:46]
  wire  s2_update_meta = ~_s2_update_meta_T; // @[Metadata.scala 46:40]
  wire  _T_243 = io_cpu_s2_nack | s2_valid_hit_pre_data_ecc_and_waw & s2_update_meta; // @[DCache.scala 421:24]
  wire  s1_readwrite = s1_read | s1_write; // @[DCache.scala 192:30]
  wire  s1_flush_line = s1_req_cmd == 5'h5 & s1_req_size[0]; // @[DCache.scala 194:50]
  wire  s1_cmd_uses_tlb = s1_readwrite | s1_flush_line | s1_req_cmd == 5'h17; // @[DCache.scala 250:55]
  wire  _GEN_147 = s1_valid & s1_raw_hazard | _T_243; // @[DCache.scala 546:{36,46}]
  wire  _GEN_292 = probeNack | _GEN_147; // @[DCache.scala 814:{24,34}]
  wire  s1_nack = s2_probe ? _GEN_292 : _GEN_147; // @[DCache.scala 799:21]
  wire  _s1_valid_not_nacked_T = ~s1_nack; // @[DCache.scala 167:41]
  wire  s1_valid_not_nacked = s1_valid & ~s1_nack; // @[DCache.scala 167:38]
  wire  s0_clk_en = metaArb_io_out_valid & ~metaArb_io_out_bits_write; // @[DCache.scala 170:40]
  wire [31:0] s0_req_addr = {metaArb_io_out_bits_addr[31:6],io_cpu_req_bits_addr[5:0]}; // @[Cat.scala 31:58]
  wire  s0_req_phys = ~metaArb_io_in_7_ready; // @[DCache.scala 175:9]
  reg [5:0] s1_req_tag; // @[Reg.scala 16:16]
  reg  s1_req_signed; // @[Reg.scala 16:16]
  reg [1:0] s1_req_dprv; // @[Reg.scala 16:16]
  reg [31:0] s1_tlb_req_vaddr; // @[Reg.scala 16:16]
  reg [1:0] s1_tlb_req_size; // @[Reg.scala 16:16]
  reg [4:0] s1_tlb_req_cmd; // @[Reg.scala 16:16]
  reg [1:0] s1_tlb_req_prv; // @[Reg.scala 16:16]
  wire  s1_sfence = s1_req_cmd == 5'h14 | s1_req_cmd == 5'h15 | s1_req_cmd == 5'h16; // @[DCache.scala 193:71]
  reg  s1_flush_valid; // @[DCache.scala 195:27]
  reg  cached_grant_wait; // @[DCache.scala 203:30]
  reg  resetting; // @[DCache.scala 204:26]
  reg [6:0] flushCounter; // @[DCache.scala 205:25]
  reg [1:0] refill_way; // @[DCache.scala 209:23]
  wire  inWriteback = _T_309 | _T_308; // @[package.scala 72:59]
  wire  _io_cpu_req_ready_T = release_state == 4'h0; // @[DCache.scala 213:38]
  wire  _io_cpu_req_ready_T_1 = ~cached_grant_wait; // @[DCache.scala 213:54]
  reg  uncachedInFlight_0; // @[DCache.scala 216:33]
  reg [31:0] uncachedReqs_0_addr; // @[DCache.scala 217:25]
  reg [5:0] uncachedReqs_0_tag; // @[DCache.scala 217:25]
  reg [1:0] uncachedReqs_0_size; // @[DCache.scala 217:25]
  reg  uncachedReqs_0_signed; // @[DCache.scala 217:25]
  wire  _s0_read_T = io_cpu_req_bits_cmd == 5'h0; // @[package.scala 15:47]
  wire  _s0_read_T_1 = io_cpu_req_bits_cmd == 5'h10; // @[package.scala 15:47]
  wire  _s0_read_T_2 = io_cpu_req_bits_cmd == 5'h6; // @[package.scala 15:47]
  wire  _s0_read_T_3 = io_cpu_req_bits_cmd == 5'h7; // @[package.scala 15:47]
  wire  _s0_read_T_6 = _s0_read_T | _s0_read_T_1 | _s0_read_T_2 | _s0_read_T_3; // @[package.scala 72:59]
  wire  _s0_read_T_7 = io_cpu_req_bits_cmd == 5'h4; // @[package.scala 15:47]
  wire  _s0_read_T_8 = io_cpu_req_bits_cmd == 5'h9; // @[package.scala 15:47]
  wire  _s0_read_T_9 = io_cpu_req_bits_cmd == 5'ha; // @[package.scala 15:47]
  wire  _s0_read_T_10 = io_cpu_req_bits_cmd == 5'hb; // @[package.scala 15:47]
  wire  _s0_read_T_13 = _s0_read_T_7 | _s0_read_T_8 | _s0_read_T_9 | _s0_read_T_10; // @[package.scala 72:59]
  wire  _s0_read_T_14 = io_cpu_req_bits_cmd == 5'h8; // @[package.scala 15:47]
  wire  _s0_read_T_15 = io_cpu_req_bits_cmd == 5'hc; // @[package.scala 15:47]
  wire  _s0_read_T_16 = io_cpu_req_bits_cmd == 5'hd; // @[package.scala 15:47]
  wire  _s0_read_T_17 = io_cpu_req_bits_cmd == 5'he; // @[package.scala 15:47]
  wire  _s0_read_T_18 = io_cpu_req_bits_cmd == 5'hf; // @[package.scala 15:47]
  wire  _s0_read_T_22 = _s0_read_T_14 | _s0_read_T_15 | _s0_read_T_16 | _s0_read_T_17 | _s0_read_T_18; // @[package.scala 72:59]
  wire  _s0_read_T_23 = _s0_read_T_13 | _s0_read_T_22; // @[Consts.scala 82:44]
  wire  s0_read = _s0_read_T_6 | _s0_read_T_23; // @[Consts.scala 84:68]
  wire  _dataArb_io_in_3_valid_res_T = io_cpu_req_bits_cmd == 5'h1; // @[package.scala 15:47]
  wire  _dataArb_io_in_3_valid_res_T_1 = io_cpu_req_bits_cmd == 5'h3; // @[package.scala 15:47]
  wire  _dataArb_io_in_3_valid_res_T_2 = _dataArb_io_in_3_valid_res_T | _dataArb_io_in_3_valid_res_T_1; // @[package.scala 72:59]
  wire  res = ~_dataArb_io_in_3_valid_res_T_2; // @[DCache.scala 1159:15]
  wire  _dataArb_io_in_3_valid_T_26 = io_cpu_req_bits_cmd == 5'h11; // @[Consts.scala 85:49]
  wire  _dataArb_io_in_3_valid_T_47 = _dataArb_io_in_3_valid_res_T | io_cpu_req_bits_cmd == 5'h11 | _s0_read_T_3 |
    _s0_read_T_23; // @[Consts.scala 85:76]
  wire  _dataArb_io_in_3_valid_T_51 = _dataArb_io_in_3_valid_T_47 & _dataArb_io_in_3_valid_T_26; // @[DCache.scala 1165:23]
  wire  _dataArb_io_in_3_valid_T_52 = s0_read | _dataArb_io_in_3_valid_T_51; // @[DCache.scala 1164:21]
  wire  _dataArb_io_in_3_valid_T_56 = ~reset; // @[DCache.scala 1160:11]
  wire  _dataArb_io_in_3_valid_T_58 = io_cpu_req_valid & res; // @[DCache.scala 222:46]
  wire [31:0] _dataArb_io_in_3_bits_addr_T_2 = {io_cpu_req_bits_addr[31:12],io_cpu_req_bits_addr[11:0]}; // @[Cat.scala 31:58]
  wire  _GEN_33 = ~dataArb_io_in_3_ready & s0_read ? 1'h0 : release_state == 4'h0 & ~cached_grant_wait &
    _s1_valid_not_nacked_T; // @[DCache.scala 213:20 238:{45,64}]
  wire  _s1_did_read_T_54 = dataArb_io_in_3_ready & (io_cpu_req_valid & _dataArb_io_in_3_valid_T_52); // @[DCache.scala 239:54]
  reg  s1_did_read; // @[Reg.scala 16:16]
  reg  s1_read_mask; // @[Reg.scala 16:16]
  wire  _GEN_36 = s0_req_phys ? 1'h0 : _GEN_33; // @[DCache.scala 247:{34,53}]
  wire [30:0] s1_paddr = {tlb_io_resp_paddr[30:12],s1_req_addr[11:0]}; // @[Cat.scala 31:58]
  wire  _T_19 = metaArb_io_out_valid & metaArb_io_out_bits_write; // @[DCache.scala 285:27]
  wire [5:0] _GEN_44 = metaArb_io_out_bits_idx; // @[DCache.scala 285:50]
  wire [20:0] _WIRE_2 = tag_array_RW0_rdata_0;
  wire [18:0] s1_meta_uncorrected_0_tag = _WIRE_2[18:0]; // @[DCache.scala 290:80]
  wire [1:0] s1_meta_uncorrected_0_coh_state = _WIRE_2[20:19]; // @[DCache.scala 290:80]
  wire [20:0] _WIRE_3 = tag_array_RW0_rdata_1;
  wire [18:0] s1_meta_uncorrected_1_tag = _WIRE_3[18:0]; // @[DCache.scala 290:80]
  wire [1:0] s1_meta_uncorrected_1_coh_state = _WIRE_3[20:19]; // @[DCache.scala 290:80]
  wire [18:0] s1_tag = s1_paddr[30:12]; // @[DCache.scala 291:29]
  wire  _T_28 = s1_meta_uncorrected_0_coh_state > 2'h0; // @[Metadata.scala 49:45]
  wire  _T_29 = s1_meta_uncorrected_0_tag == s1_tag; // @[DCache.scala 292:83]
  wire  _T_30 = _T_28 & s1_meta_uncorrected_0_tag == s1_tag; // @[DCache.scala 292:74]
  wire  _T_31 = s1_meta_uncorrected_1_coh_state > 2'h0; // @[Metadata.scala 49:45]
  wire  _T_32 = s1_meta_uncorrected_1_tag == s1_tag; // @[DCache.scala 292:83]
  wire  _T_33 = _T_31 & s1_meta_uncorrected_1_tag == s1_tag; // @[DCache.scala 292:74]
  wire [1:0] s1_meta_hit_way = {_T_33,_T_30}; // @[Cat.scala 31:58]
  wire  _T_35 = ~s1_flush_valid; // @[DCache.scala 294:62]
  wire [1:0] _T_37 = _T_29 & ~s1_flush_valid ? s1_meta_uncorrected_0_coh_state : 2'h0; // @[DCache.scala 294:41]
  wire [1:0] _T_41 = _T_32 & ~s1_flush_valid ? s1_meta_uncorrected_1_coh_state : 2'h0; // @[DCache.scala 294:41]
  wire [1:0] s1_meta_hit_state_state = _T_37 | _T_41; // @[DCache.scala 295:19]
  wire  s2_hit_valid = s2_hit_state_state > 2'h0; // @[Metadata.scala 49:45]
  reg [1:0] s2_hit_way; // @[Reg.scala 16:16]
  reg  s2_victim_way_r; // @[Reg.scala 16:16]
  wire [1:0] s2_victim_way = 2'h1 << s2_victim_way_r; // @[OneHot.scala 57:35]
  wire [1:0] s2_victim_or_hit_way = s2_hit_valid ? s2_hit_way : s2_victim_way; // @[DCache.scala 407:33]
  reg [1:0] s2_probe_way; // @[Reg.scala 16:16]
  wire [1:0] releaseWay = _T_313 ? s2_victim_or_hit_way : s2_probe_way; // @[DCache.scala 838:102 788:14 852:18]
  wire [1:0] s1_data_way_x42 = inWriteback ? releaseWay : s1_meta_hit_way; // @[DCache.scala 298:61]
  wire [15:0] tl_d_data_encoded_lo = {auto_out_d_bits_data[15:8],auto_out_d_bits_data[7:0]}; // @[Cat.scala 31:58]
  wire [15:0] tl_d_data_encoded_hi = {auto_out_d_bits_data[31:24],auto_out_d_bits_data[23:16]}; // @[Cat.scala 31:58]
  wire [31:0] _tl_d_data_encoded_T_4 = {auto_out_d_bits_data[31:24],auto_out_d_bits_data[23:16],auto_out_d_bits_data[15:
    8],auto_out_d_bits_data[7:0]}; // @[Cat.scala 31:58]
  wire [3:0] _T_47 = ~io_cpu_s1_data_mask; // @[DCache.scala 304:71]
  wire [3:0] _T_48 = s1_mask_xwr | _T_47; // @[DCache.scala 304:69]
  wire  s2_valid_x44 = s1_valid_masked & ~s1_sfence; // @[DCache.scala 306:43]
  reg [31:0] s2_req_addr; // @[DCache.scala 314:19]
  reg [5:0] s2_req_tag; // @[DCache.scala 314:19]
  reg [1:0] s2_req_size; // @[DCache.scala 314:19]
  reg  s2_req_signed; // @[DCache.scala 314:19]
  reg [1:0] s2_req_dprv; // @[DCache.scala 314:19]
  wire  _s2_cmd_flush_all_T = s2_req_cmd == 5'h5; // @[DCache.scala 315:37]
  wire  s2_cmd_flush_line = _s2_cmd_flush_all_T & s2_req_size[0]; // @[DCache.scala 316:54]
  reg  s2_tlb_xcpt_pf_ld; // @[DCache.scala 317:24]
  reg  s2_tlb_xcpt_pf_st; // @[DCache.scala 317:24]
  reg  s2_tlb_xcpt_ae_ld; // @[DCache.scala 317:24]
  reg  s2_tlb_xcpt_ae_st; // @[DCache.scala 317:24]
  reg  s2_tlb_xcpt_ma_ld; // @[DCache.scala 317:24]
  reg  s2_tlb_xcpt_ma_st; // @[DCache.scala 317:24]
  reg  s2_pma_cacheable; // @[DCache.scala 318:19]
  reg [31:0] s2_uncached_resp_addr; // @[DCache.scala 319:34]
  wire  _T_54 = s1_valid_not_nacked | s1_flush_valid; // @[DCache.scala 320:29]
  wire [31:0] _GEN_55 = s1_valid_not_nacked | s1_flush_valid ? {{1'd0}, s1_paddr} : s2_req_addr; // @[DCache.scala 320:48 322:17 314:19]
  wire [5:0] _GEN_56 = s1_valid_not_nacked | s1_flush_valid ? s1_req_tag : s2_req_tag; // @[DCache.scala 320:48 321:12 314:19]
  wire [4:0] _GEN_57 = s1_valid_not_nacked | s1_flush_valid ? s1_req_cmd : s2_req_cmd; // @[DCache.scala 320:48 321:12 314:19]
  wire [1:0] _GEN_58 = s1_valid_not_nacked | s1_flush_valid ? s1_req_size : s2_req_size; // @[DCache.scala 320:48 321:12 314:19]
  wire  _GEN_59 = s1_valid_not_nacked | s1_flush_valid ? s1_req_signed : s2_req_signed; // @[DCache.scala 320:48 321:12 314:19]
  reg [31:0] s2_vaddr_r; // @[Reg.scala 16:16]
  wire [31:0] s2_vaddr = {s2_vaddr_r[31:12],s2_req_addr[11:0]}; // @[Cat.scala 31:58]
  reg  s2_flush_valid_pre_tag_ecc; // @[DCache.scala 330:43]
  wire  s1_meta_clk_en = _T_54 | s1_probe; // @[DCache.scala 332:62]
  reg [20:0] s2_meta_corrected_r; // @[Reg.scala 16:16]
  wire [18:0] s2_meta_corrected_0_tag = s2_meta_corrected_r[18:0]; // @[DCache.scala 336:99]
  wire [1:0] s2_meta_corrected_0_coh_state = s2_meta_corrected_r[20:19]; // @[DCache.scala 336:99]
  reg [20:0] s2_meta_corrected_r_1; // @[Reg.scala 16:16]
  wire [18:0] s2_meta_corrected_1_tag = s2_meta_corrected_r_1[18:0]; // @[DCache.scala 336:99]
  wire [1:0] s2_meta_corrected_1_coh_state = s2_meta_corrected_r_1[20:19]; // @[DCache.scala 336:99]
  wire  en = s1_valid | inWriteback | io_cpu_replay_next; // @[DCache.scala 341:38]
  wire  word_en = inWriteback | s1_did_read & s1_read_mask; // @[DCache.scala 342:22]
  wire [31:0] s1_all_data_ways_0 = data_io_resp_0; // @[DCache.scala 300:{29,29}]
  wire [31:0] s1_all_data_ways_1 = data_io_resp_1; // @[DCache.scala 300:{29,29}]
  wire  s1_word_en = ~io_cpu_replay_next ? word_en : 1'h1; // @[DCache.scala 352:27]
  wire  grantIsUncachedData = auto_out_d_bits_opcode == 3'h1; // @[package.scala 15:47]
  reg  blockUncachedGrant; // @[DCache.scala 725:33]
  wire  grantIsRefill = auto_out_d_bits_opcode == 3'h5; // @[DCache.scala 641:29]
  wire  _T_292 = ~dataArb_io_in_1_ready; // @[DCache.scala 697:26]
  wire  _grantIsCached_T = auto_out_d_bits_opcode == 3'h4; // @[package.scala 15:47]
  wire  grantIsCached = _grantIsCached_T | grantIsRefill; // @[package.scala 72:59]
  reg [9:0] counter; // @[Edges.scala 228:27]
  wire  d_first = counter == 10'h0; // @[Edges.scala 230:25]
  wire  canAcceptCachedGrant = ~_T_313; // @[DCache.scala 645:30]
  wire  _bundleOut_0_d_ready_T_3 = grantIsCached ? (~d_first | auto_out_e_ready) & canAcceptCachedGrant : 1'h1; // @[DCache.scala 646:24]
  wire  _GEN_242 = grantIsRefill & ~dataArb_io_in_1_ready ? 1'h0 : _bundleOut_0_d_ready_T_3; // @[DCache.scala 646:18 697:51 699:20]
  wire  tl_out__d_ready = grantIsUncachedData & (blockUncachedGrant | s1_valid) ? 1'h0 : _GEN_242; // @[DCache.scala 727:68 728:22]
  wire  _T_272 = tl_out__d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
  wire  _T_268 = auto_out_d_bits_opcode == 3'h0; // @[package.scala 15:47]
  wire  _T_269 = auto_out_d_bits_opcode == 3'h2; // @[package.scala 15:47]
  wire  grantIsUncached = grantIsUncachedData | _T_268 | _T_269; // @[package.scala 72:59]
  wire [2:0] _GEN_198 = grantIsUncachedData ? 3'h4 : {{1'd0}, s1_data_way_x42}; // @[DCache.scala 666:34 669:25]
  wire [2:0] _GEN_207 = grantIsUncached ? _GEN_198 : {{1'd0}, s1_data_way_x42}; // @[DCache.scala 659:35]
  wire [2:0] _GEN_220 = grantIsCached ? {{1'd0}, s1_data_way_x42} : _GEN_207; // @[DCache.scala 650:26]
  wire [2:0] s1_data_way = _T_272 ? _GEN_220 : {{1'd0}, s1_data_way_x42}; // @[DCache.scala 649:26]
  wire [2:0] _s2_data_T_1 = s1_word_en ? s1_data_way : 3'h0; // @[DCache.scala 354:28]
  wire [31:0] _s2_data_T_5 = _s2_data_T_1[0] ? s1_all_data_ways_0 : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _s2_data_T_6 = _s2_data_T_1[1] ? s1_all_data_ways_1 : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _s2_data_T_7 = _s2_data_T_1[2] ? _tl_d_data_encoded_T_4 : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _s2_data_T_8 = _s2_data_T_5 | _s2_data_T_6; // @[Mux.scala 27:73]
  wire [31:0] _s2_data_T_9 = _s2_data_T_8 | _s2_data_T_7; // @[Mux.scala 27:73]
  reg [31:0] s2_data; // @[Reg.scala 16:16]
  wire [15:0] s2_data_corrected_lo = {s2_data[15:8],s2_data[7:0]}; // @[Cat.scala 31:58]
  wire [15:0] s2_data_corrected_hi = {s2_data[31:24],s2_data[23:16]}; // @[Cat.scala 31:58]
  wire [31:0] s2_data_corrected = {s2_data[31:24],s2_data[23:16],s2_data[15:8],s2_data[7:0]}; // @[Cat.scala 31:58]
  wire  s2_valid_flush_line = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw & s2_cmd_flush_line; // @[DCache.scala 394:75]
  wire  s2_valid_miss = s2_valid_masked & s2_readwrite & ~s2_hit; // @[DCache.scala 398:73]
  wire  s2_uncached = ~s2_pma_cacheable; // @[DCache.scala 399:21]
  wire  _s2_valid_cached_miss_T = ~s2_uncached; // @[DCache.scala 400:47]
  wire  _s2_valid_cached_miss_T_2 = |uncachedInFlight_0; // @[DCache.scala 400:88]
  wire  s2_valid_cached_miss = s2_valid_miss & ~s2_uncached & ~(|uncachedInFlight_0); // @[DCache.scala 400:60]
  wire  s2_want_victimize = s2_valid_cached_miss | s2_valid_flush_line | s2_flush_valid_pre_tag_ecc; // @[DCache.scala 402:125]
  wire  _s2_cannot_victimize_T = ~s2_flush_valid_pre_tag_ecc; // @[DCache.scala 403:29]
  wire  s2_valid_uncached_pending = s2_valid_miss & s2_uncached & ~(&uncachedInFlight_0); // @[DCache.scala 405:64]
  wire  s1_victim_way = lfsr[0]; // @[package.scala 154:13]
  wire [18:0] _s2_victim_tag_T_4 = s2_victim_way[0] ? s2_meta_corrected_0_tag : 19'h0; // @[Mux.scala 27:73]
  wire [18:0] _s2_victim_tag_T_5 = s2_victim_way[1] ? s2_meta_corrected_1_tag : 19'h0; // @[Mux.scala 27:73]
  wire [18:0] _s2_victim_tag_T_6 = _s2_victim_tag_T_4 | _s2_victim_tag_T_5; // @[Mux.scala 27:73]
  wire [1:0] _s2_victim_tag_T_7 = s2_victim_way[0] ? s2_meta_corrected_0_coh_state : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _s2_victim_tag_T_8 = s2_victim_way[1] ? s2_meta_corrected_1_coh_state : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _s2_victim_tag_T_9 = _s2_victim_tag_T_7 | _s2_victim_tag_T_8; // @[Mux.scala 27:73]
  wire [18:0] s2_victim_tag = s2_valid_flush_line ? s2_req_addr[30:12] : _s2_victim_tag_T_6; // @[DCache.scala 408:26]
  wire [1:0] s2_victim_state_state = s2_hit_valid ? s2_hit_state_state : _s2_victim_tag_T_9; // @[DCache.scala 409:28]
  wire [2:0] _T_133 = _T_131 ? 3'h5 : 3'h0; // @[Misc.scala 37:36]
  wire [2:0] _T_137 = _T_135 ? 3'h2 : _T_133; // @[Misc.scala 37:36]
  wire [2:0] _T_141 = _T_139 ? 3'h1 : _T_137; // @[Misc.scala 37:36]
  wire [2:0] _T_145 = _T_143 ? 3'h1 : _T_141; // @[Misc.scala 37:36]
  wire [2:0] _T_149 = _T_147 ? 3'h5 : _T_145; // @[Misc.scala 37:36]
  wire [2:0] _T_153 = _T_151 ? 3'h4 : _T_149; // @[Misc.scala 37:36]
  wire [1:0] _T_154 = _T_151 ? 2'h1 : 2'h0; // @[Misc.scala 37:63]
  wire [2:0] _T_157 = _T_155 ? 3'h0 : _T_153; // @[Misc.scala 37:36]
  wire [1:0] _T_158 = _T_155 ? 2'h1 : _T_154; // @[Misc.scala 37:63]
  wire [2:0] _T_161 = _T_159 ? 3'h0 : _T_157; // @[Misc.scala 37:36]
  wire [1:0] _T_162 = _T_159 ? 2'h1 : _T_158; // @[Misc.scala 37:63]
  wire [2:0] _T_165 = _T_163 ? 3'h5 : _T_161; // @[Misc.scala 37:36]
  wire [1:0] _T_166 = _T_163 ? 2'h0 : _T_162; // @[Misc.scala 37:63]
  wire [2:0] _T_169 = _T_167 ? 3'h4 : _T_165; // @[Misc.scala 37:36]
  wire [1:0] _T_170 = _T_167 ? 2'h1 : _T_166; // @[Misc.scala 37:63]
  wire [2:0] _T_173 = _T_171 ? 3'h3 : _T_169; // @[Misc.scala 37:36]
  wire [1:0] _T_174 = _T_171 ? 2'h2 : _T_170; // @[Misc.scala 37:63]
  wire [2:0] s2_report_param = _T_175 ? 3'h3 : _T_173; // @[Misc.scala 37:36]
  wire [1:0] probeNewCoh_state = _T_175 ? 2'h2 : _T_174; // @[Misc.scala 37:63]
  wire [3:0] _T_183 = {2'h2,s2_victim_state_state}; // @[Cat.scala 31:58]
  wire  _T_196 = 4'h8 == _T_183; // @[Misc.scala 55:20]
  wire [2:0] _T_198 = _T_196 ? 3'h5 : 3'h0; // @[Misc.scala 37:36]
  wire  _T_200 = 4'h9 == _T_183; // @[Misc.scala 55:20]
  wire [2:0] _T_202 = _T_200 ? 3'h2 : _T_198; // @[Misc.scala 37:36]
  wire  _T_204 = 4'ha == _T_183; // @[Misc.scala 55:20]
  wire [2:0] _T_206 = _T_204 ? 3'h1 : _T_202; // @[Misc.scala 37:36]
  wire  _T_208 = 4'hb == _T_183; // @[Misc.scala 55:20]
  wire [2:0] _T_210 = _T_208 ? 3'h1 : _T_206; // @[Misc.scala 37:36]
  wire  _T_212 = 4'h4 == _T_183; // @[Misc.scala 55:20]
  wire  _T_213 = _T_212 ? 1'h0 : _T_208; // @[Misc.scala 37:9]
  wire [2:0] _T_214 = _T_212 ? 3'h5 : _T_210; // @[Misc.scala 37:36]
  wire  _T_216 = 4'h5 == _T_183; // @[Misc.scala 55:20]
  wire  _T_217 = _T_216 ? 1'h0 : _T_213; // @[Misc.scala 37:9]
  wire [2:0] _T_218 = _T_216 ? 3'h4 : _T_214; // @[Misc.scala 37:36]
  wire [1:0] _T_219 = _T_216 ? 2'h1 : 2'h0; // @[Misc.scala 37:63]
  wire  _T_220 = 4'h6 == _T_183; // @[Misc.scala 55:20]
  wire  _T_221 = _T_220 ? 1'h0 : _T_217; // @[Misc.scala 37:9]
  wire [2:0] _T_222 = _T_220 ? 3'h0 : _T_218; // @[Misc.scala 37:36]
  wire [1:0] _T_223 = _T_220 ? 2'h1 : _T_219; // @[Misc.scala 37:63]
  wire  _T_224 = 4'h7 == _T_183; // @[Misc.scala 55:20]
  wire [2:0] _T_226 = _T_224 ? 3'h0 : _T_222; // @[Misc.scala 37:36]
  wire [1:0] _T_227 = _T_224 ? 2'h1 : _T_223; // @[Misc.scala 37:63]
  wire  _T_228 = 4'h0 == _T_183; // @[Misc.scala 55:20]
  wire  _T_229 = _T_228 ? 1'h0 : _T_224 | _T_221; // @[Misc.scala 37:9]
  wire [2:0] _T_230 = _T_228 ? 3'h5 : _T_226; // @[Misc.scala 37:36]
  wire [1:0] _T_231 = _T_228 ? 2'h0 : _T_227; // @[Misc.scala 37:63]
  wire  _T_232 = 4'h1 == _T_183; // @[Misc.scala 55:20]
  wire  _T_233 = _T_232 ? 1'h0 : _T_229; // @[Misc.scala 37:9]
  wire [2:0] _T_234 = _T_232 ? 3'h4 : _T_230; // @[Misc.scala 37:36]
  wire [1:0] _T_235 = _T_232 ? 2'h1 : _T_231; // @[Misc.scala 37:63]
  wire  _T_236 = 4'h2 == _T_183; // @[Misc.scala 55:20]
  wire  _T_237 = _T_236 ? 1'h0 : _T_233; // @[Misc.scala 37:9]
  wire [2:0] _T_238 = _T_236 ? 3'h3 : _T_234; // @[Misc.scala 37:36]
  wire [1:0] _T_239 = _T_236 ? 2'h2 : _T_235; // @[Misc.scala 37:63]
  wire  _T_240 = 4'h3 == _T_183; // @[Misc.scala 55:20]
  wire  s2_victim_dirty = _T_240 | _T_237; // @[Misc.scala 37:9]
  wire [2:0] s2_shrink_param = _T_240 ? 3'h3 : _T_238; // @[Misc.scala 37:36]
  wire [1:0] voluntaryNewCoh_state = _T_240 ? 2'h2 : _T_239; // @[Misc.scala 37:63]
  wire  s2_dont_nack_uncached = s2_valid_uncached_pending & auto_out_a_ready; // @[DCache.scala 415:57]
  wire  _s2_dont_nack_misc_T_10 = s2_req_cmd == 5'h17; // @[DCache.scala 419:17]
  wire  s2_dont_nack_misc = s2_valid_masked & _s2_dont_nack_misc_T_10; // @[DCache.scala 416:61]
  wire  _io_cpu_s2_nack_T_4 = ~s2_valid_hit_pre_data_ecc_and_waw; // @[DCache.scala 420:89]
  wire [18:0] metaArb_io_in_2_bits_data_meta_tag = s2_req_addr[30:12]; // @[HellaCache.scala 293:20 294:14]
  wire  _lrscBackingOff_T = lrscCount > 7'h0; // @[DCache.scala 449:34]
  wire  lrscBackingOff = lrscCount > 7'h0 & ~lrscValid; // @[DCache.scala 449:38]
  reg [25:0] lrscAddr; // @[DCache.scala 450:21]
  wire  lrscAddrMatch = lrscAddr == s2_req_addr[31:6]; // @[DCache.scala 451:32]
  wire  s2_sc_fail = _s2_write_T_3 & ~(lrscValid & lrscAddrMatch); // @[DCache.scala 452:26]
  wire [6:0] _lrscCount_T = s2_hit ? 7'h4f : 7'h0; // @[DCache.scala 454:21]
  wire [6:0] _GEN_129 = s2_valid_hit_pre_data_ecc_and_waw & _c_cat_T_48 & _io_cpu_req_ready_T_1 | s2_valid_cached_miss
     ? _lrscCount_T : lrscCount; // @[DCache.scala 453:99 454:15 447:22]
  wire [6:0] _lrscCount_T_2 = lrscCount - 7'h1; // @[DCache.scala 457:49]
  wire  _pstore1_cmd_T = s1_valid_not_nacked & s1_write; // @[DCache.scala 467:63]
  reg [4:0] pstore1_cmd; // @[Reg.scala 16:16]
  reg [31:0] pstore1_data; // @[Reg.scala 16:16]
  reg [1:0] pstore1_way; // @[Reg.scala 16:16]
  wire  _pstore1_rmw_T_51 = s1_write & _s1_write_T_1; // @[DCache.scala 1165:23]
  wire  _pstore1_rmw_T_52 = s1_read | _pstore1_rmw_T_51; // @[DCache.scala 1164:21]
  reg  pstore1_rmw_r; // @[Reg.scala 16:16]
  wire  _pstore1_merge_T = s2_valid_hit_pre_data_ecc_and_waw & s2_write; // @[DCache.scala 465:46]
  wire  _pstore1_merge_T_2 = s2_valid_hit_pre_data_ecc_and_waw & s2_write & ~s2_sc_fail; // @[DCache.scala 465:58]
  wire  pstore_drain_opportunistic = ~_dataArb_io_in_3_valid_T_58; // @[DCache.scala 477:36]
  reg  pstore_drain_on_miss_REG; // @[DCache.scala 478:56]
  wire  pstore_drain_on_miss = releaseInFlight | pstore_drain_on_miss_REG; // @[DCache.scala 478:46]
  wire  pstore1_valid = _pstore1_merge_T_2 | pstore1_held; // @[DCache.scala 482:38]
  wire  pstore_drain_structural = pstore1_valid_likely & pstore2_valid & (s1_valid & s1_write | pstore1_rmw_r); // @[DCache.scala 484:71]
  wire  _T_255 = _pstore1_merge_T | pstore1_held; // @[DCache.scala 481:96]
  wire  _pstore_drain_T_10 = (_T_255 & ~pstore1_rmw_r | pstore2_valid) & (pstore_drain_opportunistic |
    pstore_drain_on_miss); // @[DCache.scala 493:76]
  wire  pstore_drain = pstore_drain_structural | _pstore_drain_T_10; // @[DCache.scala 492:48]
  wire  _pstore1_held_T_9 = ~pstore_drain; // @[DCache.scala 496:91]
  wire  advance_pstore1 = pstore1_valid & pstore2_valid == pstore_drain; // @[DCache.scala 497:61]
  reg [1:0] pstore2_way; // @[Reg.scala 16:16]
  wire [31:0] pstore1_storegen_data = amoalu_io_out;
  reg [7:0] pstore2_storegen_data_r; // @[Reg.scala 16:16]
  reg [7:0] pstore2_storegen_data_r_1; // @[Reg.scala 16:16]
  reg [7:0] pstore2_storegen_data_r_2; // @[Reg.scala 16:16]
  reg [7:0] pstore2_storegen_data_r_3; // @[Reg.scala 16:16]
  wire [31:0] pstore2_storegen_data = {pstore2_storegen_data_r_3,pstore2_storegen_data_r_2,pstore2_storegen_data_r_1,
    pstore2_storegen_data_r}; // @[Cat.scala 31:58]
  wire [3:0] _pstore2_storegen_mask_mask_T = ~pstore1_mask; // @[DCache.scala 509:37]
  wire [3:0] _pstore2_storegen_mask_mask_T_2 = ~_pstore2_storegen_mask_mask_T; // @[DCache.scala 509:15]
  wire [31:0] _dataArb_io_in_0_bits_addr_T = pstore2_valid ? pstore2_addr : pstore1_addr; // @[DCache.scala 524:36]
  wire [31:0] _dataArb_io_in_0_bits_wdata_T = pstore2_valid ? pstore2_storegen_data : pstore1_data; // @[DCache.scala 526:63]
  wire [15:0] dataArb_io_in_0_bits_wdata_lo = {_dataArb_io_in_0_bits_wdata_T[15:8],_dataArb_io_in_0_bits_wdata_T[7:0]}; // @[Cat.scala 31:58]
  wire [15:0] dataArb_io_in_0_bits_wdata_hi = {_dataArb_io_in_0_bits_wdata_T[31:24],_dataArb_io_in_0_bits_wdata_T[23:16]
    }; // @[Cat.scala 31:58]
  wire [3:0] _dataArb_io_in_0_bits_eccMask_T = pstore2_valid ? mask : pstore1_mask; // @[DCache.scala 532:47]
  wire  _dataArb_io_in_0_bits_eccMask_T_5 = |_dataArb_io_in_0_bits_eccMask_T[0]; // @[DCache.scala 1155:66]
  wire  _dataArb_io_in_0_bits_eccMask_T_6 = |_dataArb_io_in_0_bits_eccMask_T[1]; // @[DCache.scala 1155:66]
  wire  _dataArb_io_in_0_bits_eccMask_T_7 = |_dataArb_io_in_0_bits_eccMask_T[2]; // @[DCache.scala 1155:66]
  wire  _dataArb_io_in_0_bits_eccMask_T_8 = |_dataArb_io_in_0_bits_eccMask_T[3]; // @[DCache.scala 1155:66]
  wire [1:0] dataArb_io_in_0_bits_eccMask_lo = {_dataArb_io_in_0_bits_eccMask_T_6,_dataArb_io_in_0_bits_eccMask_T_5}; // @[Cat.scala 31:58]
  wire [1:0] dataArb_io_in_0_bits_eccMask_hi = {_dataArb_io_in_0_bits_eccMask_T_8,_dataArb_io_in_0_bits_eccMask_T_7}; // @[Cat.scala 31:58]
  wire  _a_source_T = ~uncachedInFlight_0; // @[DCache.scala 552:34]
  wire [1:0] _a_source_T_1 = {_a_source_T, 1'h0}; // @[DCache.scala 552:59]
  wire  a_source = _a_source_T_1[0] ? 1'h0 : 1'h1; // @[Mux.scala 47:70]
  wire [31:0] acquire_address = {s2_req_addr[31:6], 6'h0}; // @[DCache.scala 553:49]
  wire [18:0] a_mask = {{15'd0}, pstore1_mask}; // @[DCache.scala 557:29]
  wire [1:0] _get_a_mask_sizeOH_T_1 = 2'h1 << s2_req_size[0]; // @[OneHot.scala 64:12]
  wire [1:0] get_a_mask_sizeOH = _get_a_mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _get_a_mask_T = s2_req_size >= 2'h2; // @[Misc.scala 205:21]
  wire  get_a_mask_size = get_a_mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  get_a_mask_bit = s2_req_addr[1]; // @[Misc.scala 209:26]
  wire  get_a_mask_nbit = ~get_a_mask_bit; // @[Misc.scala 210:20]
  wire  get_a_mask_acc = _get_a_mask_T | get_a_mask_size & get_a_mask_nbit; // @[Misc.scala 214:29]
  wire  get_a_mask_acc_1 = _get_a_mask_T | get_a_mask_size & get_a_mask_bit; // @[Misc.scala 214:29]
  wire  get_a_mask_size_1 = get_a_mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  get_a_mask_bit_1 = s2_req_addr[0]; // @[Misc.scala 209:26]
  wire  get_a_mask_nbit_1 = ~get_a_mask_bit_1; // @[Misc.scala 210:20]
  wire  get_a_mask_eq_2 = get_a_mask_nbit & get_a_mask_nbit_1; // @[Misc.scala 213:27]
  wire  get_a_mask_acc_2 = get_a_mask_acc | get_a_mask_size_1 & get_a_mask_eq_2; // @[Misc.scala 214:29]
  wire  get_a_mask_eq_3 = get_a_mask_nbit & get_a_mask_bit_1; // @[Misc.scala 213:27]
  wire  get_a_mask_acc_3 = get_a_mask_acc | get_a_mask_size_1 & get_a_mask_eq_3; // @[Misc.scala 214:29]
  wire  get_a_mask_eq_4 = get_a_mask_bit & get_a_mask_nbit_1; // @[Misc.scala 213:27]
  wire  get_a_mask_acc_4 = get_a_mask_acc_1 | get_a_mask_size_1 & get_a_mask_eq_4; // @[Misc.scala 214:29]
  wire  get_a_mask_eq_5 = get_a_mask_bit & get_a_mask_bit_1; // @[Misc.scala 213:27]
  wire  get_a_mask_acc_5 = get_a_mask_acc_1 | get_a_mask_size_1 & get_a_mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] get_mask = {get_a_mask_acc_5,get_a_mask_acc_4,get_a_mask_acc_3,get_a_mask_acc_2}; // @[Cat.scala 31:58]
  wire [2:0] _atomics_T_1_opcode = 5'h4 == s2_req_cmd ? 3'h3 : 3'h0; // @[Mux.scala 81:58]
  wire [3:0] atomics_a_size = {{2'd0}, s2_req_size}; // @[Edges.scala 513:17 516:15]
  wire [3:0] _atomics_T_1_size = 5'h4 == s2_req_cmd ? atomics_a_size : 4'h0; // @[Mux.scala 81:58]
  wire [30:0] atomics_a_address = s2_req_addr[30:0]; // @[Edges.scala 513:17 518:15]
  wire [30:0] _atomics_T_1_address = 5'h4 == s2_req_cmd ? atomics_a_address : 31'h0; // @[Mux.scala 81:58]
  wire [3:0] _atomics_T_1_mask = 5'h4 == s2_req_cmd ? get_mask : 4'h0; // @[Mux.scala 81:58]
  wire [31:0] _atomics_T_1_data = 5'h4 == s2_req_cmd ? pstore1_data : 32'h0; // @[Mux.scala 81:58]
  wire [2:0] _atomics_T_3_opcode = 5'h9 == s2_req_cmd ? 3'h3 : _atomics_T_1_opcode; // @[Mux.scala 81:58]
  wire [2:0] _atomics_T_3_param = 5'h9 == s2_req_cmd ? 3'h0 : _atomics_T_1_opcode; // @[Mux.scala 81:58]
  wire [3:0] _atomics_T_3_size = 5'h9 == s2_req_cmd ? atomics_a_size : _atomics_T_1_size; // @[Mux.scala 81:58]
  wire  _atomics_T_3_source = 5'h9 == s2_req_cmd ? a_source : 5'h4 == s2_req_cmd & a_source; // @[Mux.scala 81:58]
  wire [30:0] _atomics_T_3_address = 5'h9 == s2_req_cmd ? atomics_a_address : _atomics_T_1_address; // @[Mux.scala 81:58]
  wire [3:0] _atomics_T_3_mask = 5'h9 == s2_req_cmd ? get_mask : _atomics_T_1_mask; // @[Mux.scala 81:58]
  wire [31:0] _atomics_T_3_data = 5'h9 == s2_req_cmd ? pstore1_data : _atomics_T_1_data; // @[Mux.scala 81:58]
  wire [2:0] _atomics_T_5_opcode = 5'ha == s2_req_cmd ? 3'h3 : _atomics_T_3_opcode; // @[Mux.scala 81:58]
  wire [2:0] _atomics_T_5_param = 5'ha == s2_req_cmd ? 3'h1 : _atomics_T_3_param; // @[Mux.scala 81:58]
  wire [3:0] _atomics_T_5_size = 5'ha == s2_req_cmd ? atomics_a_size : _atomics_T_3_size; // @[Mux.scala 81:58]
  wire  _atomics_T_5_source = 5'ha == s2_req_cmd ? a_source : _atomics_T_3_source; // @[Mux.scala 81:58]
  wire [30:0] _atomics_T_5_address = 5'ha == s2_req_cmd ? atomics_a_address : _atomics_T_3_address; // @[Mux.scala 81:58]
  wire [3:0] _atomics_T_5_mask = 5'ha == s2_req_cmd ? get_mask : _atomics_T_3_mask; // @[Mux.scala 81:58]
  wire [31:0] _atomics_T_5_data = 5'ha == s2_req_cmd ? pstore1_data : _atomics_T_3_data; // @[Mux.scala 81:58]
  wire [2:0] _atomics_T_7_opcode = 5'hb == s2_req_cmd ? 3'h3 : _atomics_T_5_opcode; // @[Mux.scala 81:58]
  wire [2:0] _atomics_T_7_param = 5'hb == s2_req_cmd ? 3'h2 : _atomics_T_5_param; // @[Mux.scala 81:58]
  wire [3:0] _atomics_T_7_size = 5'hb == s2_req_cmd ? atomics_a_size : _atomics_T_5_size; // @[Mux.scala 81:58]
  wire  _atomics_T_7_source = 5'hb == s2_req_cmd ? a_source : _atomics_T_5_source; // @[Mux.scala 81:58]
  wire [30:0] _atomics_T_7_address = 5'hb == s2_req_cmd ? atomics_a_address : _atomics_T_5_address; // @[Mux.scala 81:58]
  wire [3:0] _atomics_T_7_mask = 5'hb == s2_req_cmd ? get_mask : _atomics_T_5_mask; // @[Mux.scala 81:58]
  wire [31:0] _atomics_T_7_data = 5'hb == s2_req_cmd ? pstore1_data : _atomics_T_5_data; // @[Mux.scala 81:58]
  wire [2:0] _atomics_T_9_opcode = 5'h8 == s2_req_cmd ? 3'h2 : _atomics_T_7_opcode; // @[Mux.scala 81:58]
  wire [2:0] _atomics_T_9_param = 5'h8 == s2_req_cmd ? 3'h4 : _atomics_T_7_param; // @[Mux.scala 81:58]
  wire [3:0] _atomics_T_9_size = 5'h8 == s2_req_cmd ? atomics_a_size : _atomics_T_7_size; // @[Mux.scala 81:58]
  wire  _atomics_T_9_source = 5'h8 == s2_req_cmd ? a_source : _atomics_T_7_source; // @[Mux.scala 81:58]
  wire [30:0] _atomics_T_9_address = 5'h8 == s2_req_cmd ? atomics_a_address : _atomics_T_7_address; // @[Mux.scala 81:58]
  wire [3:0] _atomics_T_9_mask = 5'h8 == s2_req_cmd ? get_mask : _atomics_T_7_mask; // @[Mux.scala 81:58]
  wire [31:0] _atomics_T_9_data = 5'h8 == s2_req_cmd ? pstore1_data : _atomics_T_7_data; // @[Mux.scala 81:58]
  wire [2:0] _atomics_T_11_opcode = 5'hc == s2_req_cmd ? 3'h2 : _atomics_T_9_opcode; // @[Mux.scala 81:58]
  wire [2:0] _atomics_T_11_param = 5'hc == s2_req_cmd ? 3'h0 : _atomics_T_9_param; // @[Mux.scala 81:58]
  wire [3:0] _atomics_T_11_size = 5'hc == s2_req_cmd ? atomics_a_size : _atomics_T_9_size; // @[Mux.scala 81:58]
  wire  _atomics_T_11_source = 5'hc == s2_req_cmd ? a_source : _atomics_T_9_source; // @[Mux.scala 81:58]
  wire [30:0] _atomics_T_11_address = 5'hc == s2_req_cmd ? atomics_a_address : _atomics_T_9_address; // @[Mux.scala 81:58]
  wire [3:0] _atomics_T_11_mask = 5'hc == s2_req_cmd ? get_mask : _atomics_T_9_mask; // @[Mux.scala 81:58]
  wire [31:0] _atomics_T_11_data = 5'hc == s2_req_cmd ? pstore1_data : _atomics_T_9_data; // @[Mux.scala 81:58]
  wire [2:0] _atomics_T_13_opcode = 5'hd == s2_req_cmd ? 3'h2 : _atomics_T_11_opcode; // @[Mux.scala 81:58]
  wire [2:0] _atomics_T_13_param = 5'hd == s2_req_cmd ? 3'h1 : _atomics_T_11_param; // @[Mux.scala 81:58]
  wire [3:0] _atomics_T_13_size = 5'hd == s2_req_cmd ? atomics_a_size : _atomics_T_11_size; // @[Mux.scala 81:58]
  wire  _atomics_T_13_source = 5'hd == s2_req_cmd ? a_source : _atomics_T_11_source; // @[Mux.scala 81:58]
  wire [30:0] _atomics_T_13_address = 5'hd == s2_req_cmd ? atomics_a_address : _atomics_T_11_address; // @[Mux.scala 81:58]
  wire [3:0] _atomics_T_13_mask = 5'hd == s2_req_cmd ? get_mask : _atomics_T_11_mask; // @[Mux.scala 81:58]
  wire [31:0] _atomics_T_13_data = 5'hd == s2_req_cmd ? pstore1_data : _atomics_T_11_data; // @[Mux.scala 81:58]
  wire [2:0] _atomics_T_15_opcode = 5'he == s2_req_cmd ? 3'h2 : _atomics_T_13_opcode; // @[Mux.scala 81:58]
  wire [2:0] _atomics_T_15_param = 5'he == s2_req_cmd ? 3'h2 : _atomics_T_13_param; // @[Mux.scala 81:58]
  wire [3:0] _atomics_T_15_size = 5'he == s2_req_cmd ? atomics_a_size : _atomics_T_13_size; // @[Mux.scala 81:58]
  wire  _atomics_T_15_source = 5'he == s2_req_cmd ? a_source : _atomics_T_13_source; // @[Mux.scala 81:58]
  wire [30:0] _atomics_T_15_address = 5'he == s2_req_cmd ? atomics_a_address : _atomics_T_13_address; // @[Mux.scala 81:58]
  wire [3:0] _atomics_T_15_mask = 5'he == s2_req_cmd ? get_mask : _atomics_T_13_mask; // @[Mux.scala 81:58]
  wire [31:0] _atomics_T_15_data = 5'he == s2_req_cmd ? pstore1_data : _atomics_T_13_data; // @[Mux.scala 81:58]
  wire [2:0] atomics_opcode = 5'hf == s2_req_cmd ? 3'h2 : _atomics_T_15_opcode; // @[Mux.scala 81:58]
  wire [2:0] atomics_param = 5'hf == s2_req_cmd ? 3'h3 : _atomics_T_15_param; // @[Mux.scala 81:58]
  wire [3:0] atomics_size = 5'hf == s2_req_cmd ? atomics_a_size : _atomics_T_15_size; // @[Mux.scala 81:58]
  wire  atomics_source = 5'hf == s2_req_cmd ? a_source : _atomics_T_15_source; // @[Mux.scala 81:58]
  wire [30:0] atomics_address = 5'hf == s2_req_cmd ? atomics_a_address : _atomics_T_15_address; // @[Mux.scala 81:58]
  wire [3:0] atomics_mask = 5'hf == s2_req_cmd ? get_mask : _atomics_T_15_mask; // @[Mux.scala 81:58]
  wire [31:0] atomics_data = 5'hf == s2_req_cmd ? pstore1_data : _atomics_T_15_data; // @[Mux.scala 81:58]
  wire [31:0] _GEN_366 = {{1'd0}, release_ack_addr}; // @[DCache.scala 581:43]
  wire [31:0] _tl_out_a_valid_T_1 = s2_req_addr ^ _GEN_366; // @[DCache.scala 581:43]
  wire  _tl_out_a_valid_T_5 = ~(release_ack_wait & _tl_out_a_valid_T_1[21:6] == 16'h0); // @[DCache.scala 581:8]
  wire  _tl_out_a_valid_T_6 = s2_valid_cached_miss & _tl_out_a_valid_T_5; // @[DCache.scala 580:29]
  wire  _tl_out_a_valid_T_7 = ~release_ack_wait; // @[DCache.scala 582:45]
  wire  _tl_out_a_valid_T_10 = ~s2_victim_dirty; // @[DCache.scala 582:89]
  wire  _tl_out_a_valid_T_12 = _tl_out_a_valid_T_6 & _tl_out_a_valid_T_10; // @[DCache.scala 581:125]
  wire  tl_out_a_valid = s2_valid_uncached_pending | _tl_out_a_valid_T_12; // @[DCache.scala 579:32]
  wire [2:0] _tl_out_a_bits_T_6_opcode = ~s2_read ? 3'h0 : atomics_opcode; // @[DCache.scala 586:8]
  wire [2:0] _tl_out_a_bits_T_6_param = ~s2_read ? 3'h0 : atomics_param; // @[DCache.scala 586:8]
  wire [3:0] _tl_out_a_bits_T_6_size = ~s2_read ? atomics_a_size : atomics_size; // @[DCache.scala 586:8]
  wire  _tl_out_a_bits_T_6_source = ~s2_read ? a_source : atomics_source; // @[DCache.scala 586:8]
  wire [30:0] _tl_out_a_bits_T_6_address = ~s2_read ? atomics_a_address : atomics_address; // @[DCache.scala 586:8]
  wire [3:0] _tl_out_a_bits_T_6_mask = ~s2_read ? get_mask : atomics_mask; // @[DCache.scala 586:8]
  wire [31:0] _tl_out_a_bits_T_6_data = ~s2_read ? pstore1_data : atomics_data; // @[DCache.scala 586:8]
  wire [2:0] _tl_out_a_bits_T_7_opcode = _s2_write_T_1 ? 3'h1 : _tl_out_a_bits_T_6_opcode; // @[DCache.scala 585:8]
  wire [2:0] _tl_out_a_bits_T_7_param = _s2_write_T_1 ? 3'h0 : _tl_out_a_bits_T_6_param; // @[DCache.scala 585:8]
  wire [3:0] _tl_out_a_bits_T_7_size = _s2_write_T_1 ? atomics_a_size : _tl_out_a_bits_T_6_size; // @[DCache.scala 585:8]
  wire  _tl_out_a_bits_T_7_source = _s2_write_T_1 ? a_source : _tl_out_a_bits_T_6_source; // @[DCache.scala 585:8]
  wire [30:0] _tl_out_a_bits_T_7_address = _s2_write_T_1 ? atomics_a_address : _tl_out_a_bits_T_6_address; // @[DCache.scala 585:8]
  wire [3:0] putpartial_mask = a_mask[3:0]; // @[Edges.scala 483:17 489:15]
  wire [3:0] _tl_out_a_bits_T_7_mask = _s2_write_T_1 ? putpartial_mask : _tl_out_a_bits_T_6_mask; // @[DCache.scala 585:8]
  wire [31:0] _tl_out_a_bits_T_7_data = _s2_write_T_1 ? pstore1_data : _tl_out_a_bits_T_6_data; // @[DCache.scala 585:8]
  wire [2:0] _tl_out_a_bits_T_8_opcode = ~s2_write ? 3'h4 : _tl_out_a_bits_T_7_opcode; // @[DCache.scala 584:8]
  wire [2:0] _tl_out_a_bits_T_8_param = ~s2_write ? 3'h0 : _tl_out_a_bits_T_7_param; // @[DCache.scala 584:8]
  wire [3:0] _tl_out_a_bits_T_8_size = ~s2_write ? atomics_a_size : _tl_out_a_bits_T_7_size; // @[DCache.scala 584:8]
  wire  _tl_out_a_bits_T_8_source = ~s2_write ? a_source : _tl_out_a_bits_T_7_source; // @[DCache.scala 584:8]
  wire [30:0] _tl_out_a_bits_T_8_address = ~s2_write ? atomics_a_address : _tl_out_a_bits_T_7_address; // @[DCache.scala 584:8]
  wire [3:0] _tl_out_a_bits_T_8_mask = ~s2_write ? get_mask : _tl_out_a_bits_T_7_mask; // @[DCache.scala 584:8]
  wire [31:0] _tl_out_a_bits_T_8_data = ~s2_write ? 32'h0 : _tl_out_a_bits_T_7_data; // @[DCache.scala 584:8]
  wire [2:0] tl_out_a_bits_a_param = {{1'd0}, s2_grow_param}; // @[Edges.scala 345:17 347:15]
  wire [30:0] tl_out_a_bits_a_address = acquire_address[30:0]; // @[Edges.scala 345:17 350:15]
  wire [1:0] _a_sel_T = 2'h1 << a_source; // @[OneHot.scala 64:12]
  wire  a_sel = _a_sel_T[1]; // @[DCache.scala 605:66]
  wire  _T_264 = auto_out_a_ready & tl_out_a_valid; // @[Decoupled.scala 50:35]
  wire  _GEN_148 = a_sel | uncachedInFlight_0; // @[DCache.scala 609:18 610:13 216:33]
  wire  _GEN_161 = s2_uncached ? _GEN_148 : uncachedInFlight_0; // @[DCache.scala 607:24 216:33]
  wire  _GEN_174 = s2_uncached ? cached_grant_wait : 1'h1; // @[DCache.scala 607:24 203:30 616:25]
  wire  _GEN_176 = _T_264 ? _GEN_161 : uncachedInFlight_0; // @[DCache.scala 606:26 216:33]
  wire  _GEN_189 = _T_264 ? _GEN_174 : cached_grant_wait; // @[DCache.scala 606:26 203:30]
  wire [26:0] _beats1_decode_T_1 = 27'hfff << auto_out_d_bits_size; // @[package.scala 234:77]
  wire [11:0] _beats1_decode_T_3 = ~_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
  wire [9:0] beats1_decode = _beats1_decode_T_3[11:2]; // @[Edges.scala 219:59]
  wire  beats1_opdata = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire [9:0] beats1 = beats1_opdata ? beats1_decode : 10'h0; // @[Edges.scala 220:14]
  wire [9:0] counter1 = counter - 10'h1; // @[Edges.scala 229:28]
  wire  d_last = counter == 10'h1 | beats1 == 10'h0; // @[Edges.scala 231:37]
  wire  d_done = d_last & _T_272; // @[Edges.scala 232:22]
  wire [9:0] _count_T = ~counter1; // @[Edges.scala 233:27]
  wire [9:0] count = beats1 & _count_T; // @[Edges.scala 233:25]
  wire [11:0] d_address_inc = {count, 2'h0}; // @[Edges.scala 268:29]
  wire  _tl_d_data_encoded_T_8 = ~grantIsUncached; // @[DCache.scala 638:129]
  wire  grantIsVoluntary = auto_out_d_bits_opcode == 3'h6; // @[DCache.scala 640:32]
  wire [2:0] _blockProbeAfterGrantCount_T_1 = blockProbeAfterGrantCount - 3'h1; // @[DCache.scala 644:97]
  wire [2:0] _GEN_192 = _block_probe_for_core_progress_T ? _blockProbeAfterGrantCount_T_1 : blockProbeAfterGrantCount; // @[DCache.scala 643:38 644:{40,68}]
  wire [1:0] _uncachedRespIdxOH_T = 2'h1 << auto_out_d_bits_source; // @[OneHot.scala 64:12]
  wire  uncachedRespIdxOH = _uncachedRespIdxOH_T[1]; // @[DCache.scala 647:90]
  wire  _T_277 = uncachedRespIdxOH & d_last; // @[DCache.scala 661:17]
  wire  _GEN_197 = uncachedRespIdxOH & d_last ? 1'h0 : _GEN_176; // @[DCache.scala 661:28 663:13]
  wire [30:0] dontCareBits = {s1_paddr[30:2], 2'h0}; // @[DCache.scala 676:55]
  wire [30:0] _GEN_367 = {{29'd0}, uncachedReqs_0_addr[1:0]}; // @[DCache.scala 677:26]
  wire [30:0] _s2_req_addr_T_1 = dontCareBits | _GEN_367; // @[DCache.scala 677:26]
  wire  _GEN_205 = grantIsVoluntary ? 1'h0 : release_ack_wait; // @[DCache.scala 682:36 684:24 206:29]
  wire  _GEN_214 = grantIsUncached ? release_ack_wait : _GEN_205; // @[DCache.scala 206:29 659:35]
  wire  _GEN_218 = grantIsCached & d_last; // @[DCache.scala 650:26 Replacement.scala 38:11]
  wire  _GEN_227 = grantIsCached ? release_ack_wait : _GEN_214; // @[DCache.scala 650:26 206:29]
  wire  _GEN_240 = _T_272 ? _GEN_227 : release_ack_wait; // @[DCache.scala 649:26 206:29]
  wire  tl_out__e_valid = grantIsRefill & ~dataArb_io_in_1_ready ? 1'h0 : auto_out_d_valid & d_first & grantIsCached &
    canAcceptCachedGrant; // @[DCache.scala 689:18 697:51 698:20]
  wire  _T_284 = auto_out_e_ready & tl_out__e_valid; // @[Decoupled.scala 50:35]
  wire [31:0] _dataArb_io_in_1_bits_addr_T_1 = {s2_vaddr[31:6], 6'h0}; // @[DCache.scala 703:57]
  wire [31:0] _GEN_368 = {{20'd0}, d_address_inc}; // @[DCache.scala 703:67]
  wire [31:0] _dataArb_io_in_1_bits_addr_T_2 = _dataArb_io_in_1_bits_addr_T_1 | _GEN_368; // @[DCache.scala 703:67]
  wire [3:0] _metaArb_io_in_3_bits_data_T_1 = {s2_write,_c_cat_T_49,auto_out_d_bits_param}; // @[Cat.scala 31:58]
  wire [1:0] _metaArb_io_in_3_bits_data_T_11 = 4'h1 == _metaArb_io_in_3_bits_data_T_1 ? 2'h1 : 2'h0; // @[Mux.scala 81:58]
  wire [1:0] _metaArb_io_in_3_bits_data_T_13 = 4'h0 == _metaArb_io_in_3_bits_data_T_1 ? 2'h2 :
    _metaArb_io_in_3_bits_data_T_11; // @[Mux.scala 81:58]
  wire [1:0] _metaArb_io_in_3_bits_data_T_15 = 4'h4 == _metaArb_io_in_3_bits_data_T_1 ? 2'h2 :
    _metaArb_io_in_3_bits_data_T_13; // @[Mux.scala 81:58]
  wire [1:0] metaArb_io_in_3_bits_data_meta_state = 4'hc == _metaArb_io_in_3_bits_data_T_1 ? 2'h3 :
    _metaArb_io_in_3_bits_data_T_15; // @[Mux.scala 81:58]
  wire  _GEN_243 = auto_out_d_valid ? 1'h0 : _GEN_36; // @[DCache.scala 730:29 731:26]
  wire  _GEN_244 = auto_out_d_valid | auto_out_d_valid & grantIsRefill & canAcceptCachedGrant; // @[DCache.scala 696:26 730:29 732:32]
  wire  _GEN_245 = auto_out_d_valid ? 1'h0 : 1'h1; // @[DCache.scala 730:29 702:33 733:37]
  wire [31:0] _metaArb_io_in_6_bits_addr_T_1 = {io_cpu_req_bits_addr[31],auto_out_b_bits_address}; // @[Cat.scala 31:58]
  wire [9:0] counter1_1 = counter_1 - 10'h1; // @[Edges.scala 229:28]
  wire [9:0] _count_T_1 = ~counter1_1; // @[Edges.scala 233:27]
  wire [9:0] c_count = beats1_1 & _count_T_1; // @[Edges.scala 233:25]
  reg  s1_release_data_valid; // @[DCache.scala 776:34]
  wire  releaseRejected = s2_release_data_valid & ~_T_298; // @[DCache.scala 778:44]
  wire [10:0] _releaseDataBeat_T = {1'h0,c_count}; // @[Cat.scala 31:58]
  wire [1:0] _releaseDataBeat_T_1 = {1'h0,s2_release_data_valid}; // @[Cat.scala 31:58]
  wire [1:0] _GEN_369 = {{1'd0}, s1_release_data_valid}; // @[DCache.scala 779:101]
  wire [1:0] _releaseDataBeat_T_3 = _GEN_369 + _releaseDataBeat_T_1; // @[DCache.scala 779:101]
  wire [1:0] _releaseDataBeat_T_4 = releaseRejected ? 2'h0 : _releaseDataBeat_T_3; // @[DCache.scala 779:52]
  wire [10:0] _GEN_370 = {{9'd0}, _releaseDataBeat_T_4}; // @[DCache.scala 779:47]
  wire [10:0] releaseDataBeat = _releaseDataBeat_T + _GEN_370; // @[DCache.scala 779:47]
  wire  discard_line = s2_valid_flush_line & s2_req_size[1]; // @[DCache.scala 793:46]
  wire [3:0] _release_state_T_13 = s2_victim_dirty & ~discard_line ? 4'h1 : 4'h6; // @[DCache.scala 794:27]
  wire [24:0] _probe_bits_T_2 = {s2_victim_tag,s2_req_addr[11:6]}; // @[Cat.scala 31:58]
  wire [30:0] res_2_address = {_probe_bits_T_2, 6'h0}; // @[DCache.scala 797:96]
  wire [3:0] _GEN_253 = s2_want_victimize ? _release_state_T_13 : release_state; // @[DCache.scala 791:25 794:21 208:26]
  wire [3:0] _release_state_T_14 = releaseDone ? 4'h7 : 4'h3; // @[DCache.scala 808:29]
  wire [3:0] _release_state_T_15 = releaseDone ? 4'h0 : 4'h5; // @[DCache.scala 812:29]
  wire [2:0] _GEN_264 = _T_304 ? s2_report_param : 3'h5; // @[DCache.scala 786:17 805:45 807:23]
  wire [3:0] _GEN_270 = _T_304 ? _release_state_T_14 : _release_state_T_15; // @[DCache.scala 805:45 808:23 812:23]
  wire [3:0] _GEN_272 = s2_prb_ack_data ? 4'h2 : _GEN_270; // @[DCache.scala 803:36 804:23]
  wire [2:0] _GEN_275 = s2_prb_ack_data ? 3'h5 : _GEN_264; // @[DCache.scala 786:17 803:36]
  wire [3:0] _GEN_293 = s2_probe ? _GEN_272 : _GEN_253; // @[DCache.scala 799:21]
  wire [2:0] _GEN_296 = s2_probe ? _GEN_275 : 3'h5; // @[DCache.scala 786:17 799:21]
  wire [31:0] _metaArb_io_in_6_bits_addr_T_3 = {io_cpu_req_bits_addr[31],probe_bits_address}; // @[Cat.scala 31:58]
  wire [3:0] _GEN_303 = metaArb_io_in_6_ready ? 4'h0 : _GEN_293; // @[DCache.scala 820:37 821:23]
  wire  _GEN_304 = metaArb_io_in_6_ready | s1_probe_x16; // @[DCache.scala 820:37 822:18 163:21]
  wire [3:0] _GEN_308 = release_state == 4'h4 ? _GEN_303 : _GEN_293; // @[DCache.scala 816:44]
  wire [3:0] _GEN_310 = releaseDone ? 4'h0 : _GEN_308; // @[DCache.scala 827:{26,42}]
  wire [3:0] _GEN_312 = release_state == 4'h5 ? _GEN_310 : _GEN_308; // @[DCache.scala 825:47]
  wire [3:0] _GEN_313 = releaseDone ? 4'h7 : _GEN_312; // @[DCache.scala 832:{26,42}]
  wire [2:0] _GEN_316 = release_state == 4'h3 ? s2_report_param : _GEN_296; // @[DCache.scala 829:48 831:21]
  wire [3:0] _GEN_322 = release_state == 4'h3 ? _GEN_313 : _GEN_312; // @[DCache.scala 829:48]
  wire [3:0] _GEN_323 = releaseDone ? 4'h7 : _GEN_322; // @[DCache.scala 836:{26,42}]
  wire [2:0] _GEN_325 = release_state == 4'h2 ? s2_report_param : _GEN_316; // @[DCache.scala 834:48 835:21]
  wire [3:0] _GEN_331 = release_state == 4'h2 ? _GEN_323 : _GEN_322; // @[DCache.scala 834:48]
  wire  _GEN_340 = _T_298 & c_first | _GEN_240; // @[DCache.scala 854:41 855:26]
  wire [1:0] newCoh_state = _T_313 ? voluntaryNewCoh_state : probeNewCoh_state; // @[DCache.scala 838:102 851:14]
  wire [11:0] _dataArb_io_in_2_bits_addr_T_1 = {probe_bits_address[11:6], 6'h0}; // @[DCache.scala 878:55]
  wire [5:0] _dataArb_io_in_2_bits_addr_T_3 = {releaseDataBeat[3:0], 2'h0}; // @[DCache.scala 878:117]
  wire [11:0] _GEN_373 = {{6'd0}, _dataArb_io_in_2_bits_addr_T_3}; // @[DCache.scala 878:72]
  wire  _metaArb_io_in_4_valid_T_1 = release_state == 4'h7; // @[package.scala 15:47]
  wire [18:0] metaArb_io_in_4_bits_data_meta_tag = probe_bits_address[30:12]; // @[DCache.scala 888:78]
  wire  _T_317 = metaArb_io_in_4_ready & metaArb_io_in_4_valid; // @[Decoupled.scala 50:35]
  reg  io_cpu_s2_xcpt_REG; // @[DCache.scala 907:32]
  reg  doUncachedResp; // @[DCache.scala 922:27]
  wire [15:0] io_cpu_resp_bits_data_shifted = get_a_mask_bit ? s2_data_corrected[31:16] : s2_data_corrected[15:0]; // @[AMOALU.scala 39:24]
  wire  _io_cpu_resp_bits_data_T_3 = s2_req_signed & io_cpu_resp_bits_data_shifted[15]; // @[AMOALU.scala 42:76]
  wire [15:0] _io_cpu_resp_bits_data_T_5 = _io_cpu_resp_bits_data_T_3 ? 16'hffff : 16'h0; // @[Bitwise.scala 74:12]
  wire [15:0] _io_cpu_resp_bits_data_T_7 = s2_req_size == 2'h1 ? _io_cpu_resp_bits_data_T_5 : s2_data_corrected[31:16]; // @[AMOALU.scala 42:20]
  wire [31:0] _io_cpu_resp_bits_data_T_8 = {_io_cpu_resp_bits_data_T_7,io_cpu_resp_bits_data_shifted}; // @[Cat.scala 31:58]
  wire [7:0] io_cpu_resp_bits_data_shifted_1 = get_a_mask_bit_1 ? _io_cpu_resp_bits_data_T_8[15:8] :
    _io_cpu_resp_bits_data_T_8[7:0]; // @[AMOALU.scala 39:24]
  wire [7:0] io_cpu_resp_bits_data_zeroed_1 = _s2_write_T_3 ? 8'h0 : io_cpu_resp_bits_data_shifted_1; // @[AMOALU.scala 41:23]
  wire  _io_cpu_resp_bits_data_T_12 = s2_req_signed & io_cpu_resp_bits_data_zeroed_1[7]; // @[AMOALU.scala 42:76]
  wire [23:0] _io_cpu_resp_bits_data_T_14 = _io_cpu_resp_bits_data_T_12 ? 24'hffffff : 24'h0; // @[Bitwise.scala 74:12]
  wire [23:0] _io_cpu_resp_bits_data_T_16 = s2_req_size == 2'h0 | _s2_write_T_3 ? _io_cpu_resp_bits_data_T_14 :
    _io_cpu_resp_bits_data_T_8[31:8]; // @[AMOALU.scala 42:20]
  wire [31:0] _io_cpu_resp_bits_data_T_17 = {_io_cpu_resp_bits_data_T_16,io_cpu_resp_bits_data_zeroed_1}; // @[Cat.scala 31:58]
  wire [31:0] _GEN_374 = {{31'd0}, s2_sc_fail}; // @[DCache.scala 948:41]
  reg  REG; // @[DCache.scala 982:18]
  wire  _GEN_358 = REG | resetting; // @[DCache.scala 204:26 982:{27,39}]
  wire [7:0] flushCounterNext = flushCounter + 7'h1; // @[DCache.scala 983:39]
  wire  flushDone = flushCounterNext[7:6] == 2'h2; // @[DCache.scala 984:57]
  wire  _s1_flush_valid_T = metaArb_io_in_5_ready & metaArb_io_in_5_valid; // @[Decoupled.scala 50:35]
  wire [11:0] _metaArb_io_in_5_bits_addr_T_1 = {metaArb_io_in_5_bits_idx, 6'h0}; // @[DCache.scala 992:98]
  wire [7:0] _GEN_360 = resetting ? flushCounterNext : {{1'd0}, flushCounter}; // @[DCache.scala 1025:20 1026:18 205:25]
  reg [9:0] io_cpu_perf_release_counter; // @[Edges.scala 228:27]
  wire [9:0] io_cpu_perf_release_counter1 = io_cpu_perf_release_counter - 10'h1; // @[Edges.scala 229:28]
  wire  io_cpu_perf_release_first = io_cpu_perf_release_counter == 10'h0; // @[Edges.scala 230:25]
  wire  io_cpu_perf_release_last = io_cpu_perf_release_counter == 10'h1 | beats1_1 == 10'h0; // @[Edges.scala 231:37]
  wire  _T_333 = ~grantIsCached; // @[DCache.scala 1107:35]
  wire  _GEN_387 = _T_272 & _T_333; // @[DCache.scala 662:17]
  TLB tlb ( // @[DCache.scala 117:19]
    .io_req_valid(tlb_io_req_valid),
    .io_req_bits_vaddr(tlb_io_req_bits_vaddr),
    .io_req_bits_size(tlb_io_req_bits_size),
    .io_req_bits_cmd(tlb_io_req_bits_cmd),
    .io_req_bits_prv(tlb_io_req_bits_prv),
    .io_resp_paddr(tlb_io_resp_paddr),
    .io_resp_pf_ld(tlb_io_resp_pf_ld),
    .io_resp_pf_st(tlb_io_resp_pf_st),
    .io_resp_ae_ld(tlb_io_resp_ae_ld),
    .io_resp_ae_st(tlb_io_resp_ae_st),
    .io_resp_ma_ld(tlb_io_resp_ma_ld),
    .io_resp_ma_st(tlb_io_resp_ma_st),
    .io_resp_cacheable(tlb_io_resp_cacheable),
    .io_ptw_status_debug(tlb_io_ptw_status_debug),
    .io_ptw_pmp_0_cfg_l(tlb_io_ptw_pmp_0_cfg_l),
    .io_ptw_pmp_0_cfg_a(tlb_io_ptw_pmp_0_cfg_a),
    .io_ptw_pmp_0_cfg_x(tlb_io_ptw_pmp_0_cfg_x),
    .io_ptw_pmp_0_cfg_w(tlb_io_ptw_pmp_0_cfg_w),
    .io_ptw_pmp_0_cfg_r(tlb_io_ptw_pmp_0_cfg_r),
    .io_ptw_pmp_0_addr(tlb_io_ptw_pmp_0_addr),
    .io_ptw_pmp_0_mask(tlb_io_ptw_pmp_0_mask),
    .io_ptw_pmp_1_cfg_l(tlb_io_ptw_pmp_1_cfg_l),
    .io_ptw_pmp_1_cfg_a(tlb_io_ptw_pmp_1_cfg_a),
    .io_ptw_pmp_1_cfg_x(tlb_io_ptw_pmp_1_cfg_x),
    .io_ptw_pmp_1_cfg_w(tlb_io_ptw_pmp_1_cfg_w),
    .io_ptw_pmp_1_cfg_r(tlb_io_ptw_pmp_1_cfg_r),
    .io_ptw_pmp_1_addr(tlb_io_ptw_pmp_1_addr),
    .io_ptw_pmp_1_mask(tlb_io_ptw_pmp_1_mask),
    .io_ptw_pmp_2_cfg_l(tlb_io_ptw_pmp_2_cfg_l),
    .io_ptw_pmp_2_cfg_a(tlb_io_ptw_pmp_2_cfg_a),
    .io_ptw_pmp_2_cfg_x(tlb_io_ptw_pmp_2_cfg_x),
    .io_ptw_pmp_2_cfg_w(tlb_io_ptw_pmp_2_cfg_w),
    .io_ptw_pmp_2_cfg_r(tlb_io_ptw_pmp_2_cfg_r),
    .io_ptw_pmp_2_addr(tlb_io_ptw_pmp_2_addr),
    .io_ptw_pmp_2_mask(tlb_io_ptw_pmp_2_mask),
    .io_ptw_pmp_3_cfg_l(tlb_io_ptw_pmp_3_cfg_l),
    .io_ptw_pmp_3_cfg_a(tlb_io_ptw_pmp_3_cfg_a),
    .io_ptw_pmp_3_cfg_x(tlb_io_ptw_pmp_3_cfg_x),
    .io_ptw_pmp_3_cfg_w(tlb_io_ptw_pmp_3_cfg_w),
    .io_ptw_pmp_3_cfg_r(tlb_io_ptw_pmp_3_cfg_r),
    .io_ptw_pmp_3_addr(tlb_io_ptw_pmp_3_addr),
    .io_ptw_pmp_3_mask(tlb_io_ptw_pmp_3_mask),
    .io_ptw_pmp_4_cfg_l(tlb_io_ptw_pmp_4_cfg_l),
    .io_ptw_pmp_4_cfg_a(tlb_io_ptw_pmp_4_cfg_a),
    .io_ptw_pmp_4_cfg_x(tlb_io_ptw_pmp_4_cfg_x),
    .io_ptw_pmp_4_cfg_w(tlb_io_ptw_pmp_4_cfg_w),
    .io_ptw_pmp_4_cfg_r(tlb_io_ptw_pmp_4_cfg_r),
    .io_ptw_pmp_4_addr(tlb_io_ptw_pmp_4_addr),
    .io_ptw_pmp_4_mask(tlb_io_ptw_pmp_4_mask),
    .io_ptw_pmp_5_cfg_l(tlb_io_ptw_pmp_5_cfg_l),
    .io_ptw_pmp_5_cfg_a(tlb_io_ptw_pmp_5_cfg_a),
    .io_ptw_pmp_5_cfg_x(tlb_io_ptw_pmp_5_cfg_x),
    .io_ptw_pmp_5_cfg_w(tlb_io_ptw_pmp_5_cfg_w),
    .io_ptw_pmp_5_cfg_r(tlb_io_ptw_pmp_5_cfg_r),
    .io_ptw_pmp_5_addr(tlb_io_ptw_pmp_5_addr),
    .io_ptw_pmp_5_mask(tlb_io_ptw_pmp_5_mask),
    .io_ptw_pmp_6_cfg_l(tlb_io_ptw_pmp_6_cfg_l),
    .io_ptw_pmp_6_cfg_a(tlb_io_ptw_pmp_6_cfg_a),
    .io_ptw_pmp_6_cfg_x(tlb_io_ptw_pmp_6_cfg_x),
    .io_ptw_pmp_6_cfg_w(tlb_io_ptw_pmp_6_cfg_w),
    .io_ptw_pmp_6_cfg_r(tlb_io_ptw_pmp_6_cfg_r),
    .io_ptw_pmp_6_addr(tlb_io_ptw_pmp_6_addr),
    .io_ptw_pmp_6_mask(tlb_io_ptw_pmp_6_mask),
    .io_ptw_pmp_7_cfg_l(tlb_io_ptw_pmp_7_cfg_l),
    .io_ptw_pmp_7_cfg_a(tlb_io_ptw_pmp_7_cfg_a),
    .io_ptw_pmp_7_cfg_x(tlb_io_ptw_pmp_7_cfg_x),
    .io_ptw_pmp_7_cfg_w(tlb_io_ptw_pmp_7_cfg_w),
    .io_ptw_pmp_7_cfg_r(tlb_io_ptw_pmp_7_cfg_r),
    .io_ptw_pmp_7_addr(tlb_io_ptw_pmp_7_addr),
    .io_ptw_pmp_7_mask(tlb_io_ptw_pmp_7_mask)
  );
  TLB pma_checker ( // @[DCache.scala 118:27]
    .io_req_valid(pma_checker_io_req_valid),
    .io_req_bits_vaddr(pma_checker_io_req_bits_vaddr),
    .io_req_bits_size(pma_checker_io_req_bits_size),
    .io_req_bits_cmd(pma_checker_io_req_bits_cmd),
    .io_req_bits_prv(pma_checker_io_req_bits_prv),
    .io_resp_paddr(pma_checker_io_resp_paddr),
    .io_resp_pf_ld(pma_checker_io_resp_pf_ld),
    .io_resp_pf_st(pma_checker_io_resp_pf_st),
    .io_resp_ae_ld(pma_checker_io_resp_ae_ld),
    .io_resp_ae_st(pma_checker_io_resp_ae_st),
    .io_resp_ma_ld(pma_checker_io_resp_ma_ld),
    .io_resp_ma_st(pma_checker_io_resp_ma_st),
    .io_resp_cacheable(pma_checker_io_resp_cacheable),
    .io_ptw_status_debug(pma_checker_io_ptw_status_debug),
    .io_ptw_pmp_0_cfg_l(pma_checker_io_ptw_pmp_0_cfg_l),
    .io_ptw_pmp_0_cfg_a(pma_checker_io_ptw_pmp_0_cfg_a),
    .io_ptw_pmp_0_cfg_x(pma_checker_io_ptw_pmp_0_cfg_x),
    .io_ptw_pmp_0_cfg_w(pma_checker_io_ptw_pmp_0_cfg_w),
    .io_ptw_pmp_0_cfg_r(pma_checker_io_ptw_pmp_0_cfg_r),
    .io_ptw_pmp_0_addr(pma_checker_io_ptw_pmp_0_addr),
    .io_ptw_pmp_0_mask(pma_checker_io_ptw_pmp_0_mask),
    .io_ptw_pmp_1_cfg_l(pma_checker_io_ptw_pmp_1_cfg_l),
    .io_ptw_pmp_1_cfg_a(pma_checker_io_ptw_pmp_1_cfg_a),
    .io_ptw_pmp_1_cfg_x(pma_checker_io_ptw_pmp_1_cfg_x),
    .io_ptw_pmp_1_cfg_w(pma_checker_io_ptw_pmp_1_cfg_w),
    .io_ptw_pmp_1_cfg_r(pma_checker_io_ptw_pmp_1_cfg_r),
    .io_ptw_pmp_1_addr(pma_checker_io_ptw_pmp_1_addr),
    .io_ptw_pmp_1_mask(pma_checker_io_ptw_pmp_1_mask),
    .io_ptw_pmp_2_cfg_l(pma_checker_io_ptw_pmp_2_cfg_l),
    .io_ptw_pmp_2_cfg_a(pma_checker_io_ptw_pmp_2_cfg_a),
    .io_ptw_pmp_2_cfg_x(pma_checker_io_ptw_pmp_2_cfg_x),
    .io_ptw_pmp_2_cfg_w(pma_checker_io_ptw_pmp_2_cfg_w),
    .io_ptw_pmp_2_cfg_r(pma_checker_io_ptw_pmp_2_cfg_r),
    .io_ptw_pmp_2_addr(pma_checker_io_ptw_pmp_2_addr),
    .io_ptw_pmp_2_mask(pma_checker_io_ptw_pmp_2_mask),
    .io_ptw_pmp_3_cfg_l(pma_checker_io_ptw_pmp_3_cfg_l),
    .io_ptw_pmp_3_cfg_a(pma_checker_io_ptw_pmp_3_cfg_a),
    .io_ptw_pmp_3_cfg_x(pma_checker_io_ptw_pmp_3_cfg_x),
    .io_ptw_pmp_3_cfg_w(pma_checker_io_ptw_pmp_3_cfg_w),
    .io_ptw_pmp_3_cfg_r(pma_checker_io_ptw_pmp_3_cfg_r),
    .io_ptw_pmp_3_addr(pma_checker_io_ptw_pmp_3_addr),
    .io_ptw_pmp_3_mask(pma_checker_io_ptw_pmp_3_mask),
    .io_ptw_pmp_4_cfg_l(pma_checker_io_ptw_pmp_4_cfg_l),
    .io_ptw_pmp_4_cfg_a(pma_checker_io_ptw_pmp_4_cfg_a),
    .io_ptw_pmp_4_cfg_x(pma_checker_io_ptw_pmp_4_cfg_x),
    .io_ptw_pmp_4_cfg_w(pma_checker_io_ptw_pmp_4_cfg_w),
    .io_ptw_pmp_4_cfg_r(pma_checker_io_ptw_pmp_4_cfg_r),
    .io_ptw_pmp_4_addr(pma_checker_io_ptw_pmp_4_addr),
    .io_ptw_pmp_4_mask(pma_checker_io_ptw_pmp_4_mask),
    .io_ptw_pmp_5_cfg_l(pma_checker_io_ptw_pmp_5_cfg_l),
    .io_ptw_pmp_5_cfg_a(pma_checker_io_ptw_pmp_5_cfg_a),
    .io_ptw_pmp_5_cfg_x(pma_checker_io_ptw_pmp_5_cfg_x),
    .io_ptw_pmp_5_cfg_w(pma_checker_io_ptw_pmp_5_cfg_w),
    .io_ptw_pmp_5_cfg_r(pma_checker_io_ptw_pmp_5_cfg_r),
    .io_ptw_pmp_5_addr(pma_checker_io_ptw_pmp_5_addr),
    .io_ptw_pmp_5_mask(pma_checker_io_ptw_pmp_5_mask),
    .io_ptw_pmp_6_cfg_l(pma_checker_io_ptw_pmp_6_cfg_l),
    .io_ptw_pmp_6_cfg_a(pma_checker_io_ptw_pmp_6_cfg_a),
    .io_ptw_pmp_6_cfg_x(pma_checker_io_ptw_pmp_6_cfg_x),
    .io_ptw_pmp_6_cfg_w(pma_checker_io_ptw_pmp_6_cfg_w),
    .io_ptw_pmp_6_cfg_r(pma_checker_io_ptw_pmp_6_cfg_r),
    .io_ptw_pmp_6_addr(pma_checker_io_ptw_pmp_6_addr),
    .io_ptw_pmp_6_mask(pma_checker_io_ptw_pmp_6_mask),
    .io_ptw_pmp_7_cfg_l(pma_checker_io_ptw_pmp_7_cfg_l),
    .io_ptw_pmp_7_cfg_a(pma_checker_io_ptw_pmp_7_cfg_a),
    .io_ptw_pmp_7_cfg_x(pma_checker_io_ptw_pmp_7_cfg_x),
    .io_ptw_pmp_7_cfg_w(pma_checker_io_ptw_pmp_7_cfg_w),
    .io_ptw_pmp_7_cfg_r(pma_checker_io_ptw_pmp_7_cfg_r),
    .io_ptw_pmp_7_addr(pma_checker_io_ptw_pmp_7_addr),
    .io_ptw_pmp_7_mask(pma_checker_io_ptw_pmp_7_mask)
  );
  MaxPeriodFibonacciLFSR lfsr_prng ( // @[PRNG.scala 91:22]
    .clock(lfsr_prng_clock),
    .reset(lfsr_prng_reset),
    .io_increment(lfsr_prng_io_increment),
    .io_out_0(lfsr_prng_io_out_0),
    .io_out_1(lfsr_prng_io_out_1),
    .io_out_2(lfsr_prng_io_out_2),
    .io_out_3(lfsr_prng_io_out_3),
    .io_out_4(lfsr_prng_io_out_4),
    .io_out_5(lfsr_prng_io_out_5),
    .io_out_6(lfsr_prng_io_out_6),
    .io_out_7(lfsr_prng_io_out_7),
    .io_out_8(lfsr_prng_io_out_8),
    .io_out_9(lfsr_prng_io_out_9),
    .io_out_10(lfsr_prng_io_out_10),
    .io_out_11(lfsr_prng_io_out_11),
    .io_out_12(lfsr_prng_io_out_12),
    .io_out_13(lfsr_prng_io_out_13),
    .io_out_14(lfsr_prng_io_out_14),
    .io_out_15(lfsr_prng_io_out_15)
  );
  DCacheModuleImpl_Anon_1 metaArb ( // @[DCache.scala 122:23]
    .io_in_0_valid(metaArb_io_in_0_valid),
    .io_in_0_bits_addr(metaArb_io_in_0_bits_addr),
    .io_in_0_bits_idx(metaArb_io_in_0_bits_idx),
    .io_in_2_valid(metaArb_io_in_2_valid),
    .io_in_2_bits_addr(metaArb_io_in_2_bits_addr),
    .io_in_2_bits_idx(metaArb_io_in_2_bits_idx),
    .io_in_2_bits_way_en(metaArb_io_in_2_bits_way_en),
    .io_in_2_bits_data(metaArb_io_in_2_bits_data),
    .io_in_3_valid(metaArb_io_in_3_valid),
    .io_in_3_bits_addr(metaArb_io_in_3_bits_addr),
    .io_in_3_bits_idx(metaArb_io_in_3_bits_idx),
    .io_in_3_bits_way_en(metaArb_io_in_3_bits_way_en),
    .io_in_3_bits_data(metaArb_io_in_3_bits_data),
    .io_in_4_ready(metaArb_io_in_4_ready),
    .io_in_4_valid(metaArb_io_in_4_valid),
    .io_in_4_bits_addr(metaArb_io_in_4_bits_addr),
    .io_in_4_bits_idx(metaArb_io_in_4_bits_idx),
    .io_in_4_bits_way_en(metaArb_io_in_4_bits_way_en),
    .io_in_4_bits_data(metaArb_io_in_4_bits_data),
    .io_in_5_ready(metaArb_io_in_5_ready),
    .io_in_5_valid(metaArb_io_in_5_valid),
    .io_in_5_bits_addr(metaArb_io_in_5_bits_addr),
    .io_in_5_bits_idx(metaArb_io_in_5_bits_idx),
    .io_in_6_ready(metaArb_io_in_6_ready),
    .io_in_6_valid(metaArb_io_in_6_valid),
    .io_in_6_bits_addr(metaArb_io_in_6_bits_addr),
    .io_in_6_bits_idx(metaArb_io_in_6_bits_idx),
    .io_in_6_bits_way_en(metaArb_io_in_6_bits_way_en),
    .io_in_6_bits_data(metaArb_io_in_6_bits_data),
    .io_in_7_ready(metaArb_io_in_7_ready),
    .io_in_7_valid(metaArb_io_in_7_valid),
    .io_in_7_bits_addr(metaArb_io_in_7_bits_addr),
    .io_in_7_bits_idx(metaArb_io_in_7_bits_idx),
    .io_in_7_bits_way_en(metaArb_io_in_7_bits_way_en),
    .io_in_7_bits_data(metaArb_io_in_7_bits_data),
    .io_out_valid(metaArb_io_out_valid),
    .io_out_bits_write(metaArb_io_out_bits_write),
    .io_out_bits_addr(metaArb_io_out_bits_addr),
    .io_out_bits_idx(metaArb_io_out_bits_idx),
    .io_out_bits_way_en(metaArb_io_out_bits_way_en),
    .io_out_bits_data(metaArb_io_out_bits_data)
  );
  tag_array tag_array ( // @[DescribedSRAM.scala 19:26]
    .RW0_addr(tag_array_RW0_addr),
    .RW0_en(tag_array_RW0_en),
    .RW0_clk(tag_array_RW0_clk),
    .RW0_wmode(tag_array_RW0_wmode),
    .RW0_wdata_0(tag_array_RW0_wdata_0),
    .RW0_wdata_1(tag_array_RW0_wdata_1),
    .RW0_rdata_0(tag_array_RW0_rdata_0),
    .RW0_rdata_1(tag_array_RW0_rdata_1),
    .RW0_wmask_0(tag_array_RW0_wmask_0),
    .RW0_wmask_1(tag_array_RW0_wmask_1)
  );
  DCacheDataArray data ( // @[DCache.scala 132:20]
    .clock(data_clock),
    .io_req_valid(data_io_req_valid),
    .io_req_bits_addr(data_io_req_bits_addr),
    .io_req_bits_write(data_io_req_bits_write),
    .io_req_bits_wdata(data_io_req_bits_wdata),
    .io_req_bits_eccMask(data_io_req_bits_eccMask),
    .io_req_bits_way_en(data_io_req_bits_way_en),
    .io_resp_0(data_io_resp_0),
    .io_resp_1(data_io_resp_1)
  );
  DCacheModuleImpl_Anon_2 dataArb ( // @[DCache.scala 133:23]
    .io_in_0_valid(dataArb_io_in_0_valid),
    .io_in_0_bits_addr(dataArb_io_in_0_bits_addr),
    .io_in_0_bits_write(dataArb_io_in_0_bits_write),
    .io_in_0_bits_wdata(dataArb_io_in_0_bits_wdata),
    .io_in_0_bits_eccMask(dataArb_io_in_0_bits_eccMask),
    .io_in_0_bits_way_en(dataArb_io_in_0_bits_way_en),
    .io_in_1_ready(dataArb_io_in_1_ready),
    .io_in_1_valid(dataArb_io_in_1_valid),
    .io_in_1_bits_addr(dataArb_io_in_1_bits_addr),
    .io_in_1_bits_write(dataArb_io_in_1_bits_write),
    .io_in_1_bits_wdata(dataArb_io_in_1_bits_wdata),
    .io_in_1_bits_way_en(dataArb_io_in_1_bits_way_en),
    .io_in_2_ready(dataArb_io_in_2_ready),
    .io_in_2_valid(dataArb_io_in_2_valid),
    .io_in_2_bits_addr(dataArb_io_in_2_bits_addr),
    .io_in_2_bits_wdata(dataArb_io_in_2_bits_wdata),
    .io_in_3_ready(dataArb_io_in_3_ready),
    .io_in_3_valid(dataArb_io_in_3_valid),
    .io_in_3_bits_addr(dataArb_io_in_3_bits_addr),
    .io_in_3_bits_wdata(dataArb_io_in_3_bits_wdata),
    .io_in_3_bits_wordMask(dataArb_io_in_3_bits_wordMask),
    .io_out_valid(dataArb_io_out_valid),
    .io_out_bits_addr(dataArb_io_out_bits_addr),
    .io_out_bits_write(dataArb_io_out_bits_write),
    .io_out_bits_wdata(dataArb_io_out_bits_wdata),
    .io_out_bits_eccMask(dataArb_io_out_bits_eccMask),
    .io_out_bits_way_en(dataArb_io_out_bits_way_en)
  );
  AMOALU amoalu ( // @[DCache.scala 956:26]
    .io_mask(amoalu_io_mask),
    .io_cmd(amoalu_io_cmd),
    .io_lhs(amoalu_io_lhs),
    .io_rhs(amoalu_io_rhs),
    .io_out(amoalu_io_out)
  );
  assign auto_out_a_valid = s2_valid_uncached_pending | _tl_out_a_valid_T_12; // @[DCache.scala 579:32]
  assign auto_out_a_bits_opcode = _s2_valid_cached_miss_T ? 3'h6 : _tl_out_a_bits_T_8_opcode; // @[DCache.scala 583:23]
  assign auto_out_a_bits_param = _s2_valid_cached_miss_T ? tl_out_a_bits_a_param : _tl_out_a_bits_T_8_param; // @[DCache.scala 583:23]
  assign auto_out_a_bits_size = _s2_valid_cached_miss_T ? 4'h6 : _tl_out_a_bits_T_8_size; // @[DCache.scala 583:23]
  assign auto_out_a_bits_source = _s2_valid_cached_miss_T ? 1'h0 : _tl_out_a_bits_T_8_source; // @[DCache.scala 583:23]
  assign auto_out_a_bits_address = _s2_valid_cached_miss_T ? tl_out_a_bits_a_address : _tl_out_a_bits_T_8_address; // @[DCache.scala 583:23]
  assign auto_out_a_bits_mask = _s2_valid_cached_miss_T ? 4'hf : _tl_out_a_bits_T_8_mask; // @[DCache.scala 583:23]
  assign auto_out_a_bits_data = _s2_valid_cached_miss_T ? 32'h0 : _tl_out_a_bits_T_8_data; // @[DCache.scala 583:23]
  assign auto_out_b_ready = metaArb_io_in_6_ready & ~(block_probe_for_core_progress | block_probe_for_ordering |
    s1_valid | s2_valid); // @[DCache.scala 745:44]
  assign auto_out_c_valid = release_state == 4'h3 | _GEN_311; // @[DCache.scala 829:48 830:22]
  assign auto_out_c_bits_opcode = _T_313 ? _GEN_332 : _GEN_324; // @[DCache.scala 838:102]
  assign auto_out_c_bits_param = _T_313 ? s2_shrink_param : _GEN_325; // @[DCache.scala 838:102]
  assign auto_out_c_bits_size = _T_313 ? 4'h6 : probe_bits_size; // @[DCache.scala 838:102]
  assign auto_out_c_bits_source = probe_bits_source; // @[Nodes.scala 1207:84 DCache.scala 859:26]
  assign auto_out_c_bits_address = probe_bits_address; // @[Nodes.scala 1207:84 DCache.scala 860:27]
  assign auto_out_c_bits_data = {s2_data_corrected_hi,s2_data_corrected_lo}; // @[Cat.scala 31:58]
  assign auto_out_d_ready = grantIsUncachedData & (blockUncachedGrant | s1_valid) ? 1'h0 : _GEN_242; // @[DCache.scala 727:68 728:22]
  assign auto_out_e_valid = grantIsRefill & ~dataArb_io_in_1_ready ? 1'h0 : auto_out_d_valid & d_first & grantIsCached
     & canAcceptCachedGrant; // @[DCache.scala 689:18 697:51 698:20]
  assign auto_out_e_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign io_cpu_req_ready = grantIsUncachedData & (blockUncachedGrant | s1_valid) ? _GEN_243 : _GEN_36; // @[DCache.scala 727:68]
  assign io_cpu_s2_nack = s2_valid_no_xcpt & ~s2_dont_nack_uncached & ~s2_dont_nack_misc & ~
    s2_valid_hit_pre_data_ecc_and_waw; // @[DCache.scala 420:86]
  assign io_cpu_resp_valid = s2_valid_hit_pre_data_ecc_and_waw | doUncachedResp; // @[DCache.scala 923:51]
  assign io_cpu_resp_bits_addr = doUncachedResp ? s2_uncached_resp_addr : s2_req_addr; // @[DCache.scala 892:20 925:25 928:27]
  assign io_cpu_resp_bits_tag = s2_req_tag; // @[DCache.scala 892:20]
  assign io_cpu_resp_bits_cmd = s2_req_cmd; // @[DCache.scala 892:20]
  assign io_cpu_resp_bits_size = s2_req_size; // @[DCache.scala 892:20]
  assign io_cpu_resp_bits_signed = s2_req_signed; // @[DCache.scala 892:20]
  assign io_cpu_resp_bits_dprv = s2_req_dprv; // @[DCache.scala 892:20]
  assign io_cpu_resp_bits_dv = 1'h0; // @[DCache.scala 892:20]
  assign io_cpu_resp_bits_data = _io_cpu_resp_bits_data_T_17 | _GEN_374; // @[DCache.scala 948:41]
  assign io_cpu_resp_bits_mask = 4'h0; // @[DCache.scala 892:20]
  assign io_cpu_resp_bits_replay = doUncachedResp; // @[DCache.scala 925:25 894:27 927:29]
  assign io_cpu_resp_bits_has_data = _s2_read_T_6 | _s2_write_T_21; // @[Consts.scala 84:68]
  assign io_cpu_resp_bits_data_word_bypass = {s2_data_corrected_hi,s2_data_corrected_lo}; // @[Cat.scala 31:58]
  assign io_cpu_resp_bits_data_raw = {s2_data_corrected_hi,s2_data_corrected_lo}; // @[Cat.scala 31:58]
  assign io_cpu_resp_bits_store_data = pstore1_data; // @[DCache.scala 951:31]
  assign io_cpu_replay_next = _T_272 & grantIsUncachedData; // @[DCache.scala 924:41]
  assign io_cpu_s2_xcpt_ma_ld = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ma_ld; // @[DCache.scala 907:24]
  assign io_cpu_s2_xcpt_ma_st = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ma_st; // @[DCache.scala 907:24]
  assign io_cpu_s2_xcpt_pf_ld = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_pf_ld; // @[DCache.scala 907:24]
  assign io_cpu_s2_xcpt_pf_st = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_pf_st; // @[DCache.scala 907:24]
  assign io_cpu_s2_xcpt_gf_ld = 1'h0; // @[DCache.scala 907:24]
  assign io_cpu_s2_xcpt_gf_st = 1'h0; // @[DCache.scala 907:24]
  assign io_cpu_s2_xcpt_ae_ld = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ae_ld; // @[DCache.scala 907:24]
  assign io_cpu_s2_xcpt_ae_st = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ae_st; // @[DCache.scala 907:24]
  assign io_cpu_ordered = ~(s1_valid | s2_valid | cached_grant_wait | _s2_valid_cached_miss_T_2); // @[DCache.scala 904:21]
  assign io_cpu_perf_release = io_cpu_perf_release_last & _T_298; // @[Edges.scala 232:22]
  assign io_cpu_perf_grant = auto_out_d_valid & d_last; // @[DCache.scala 1052:39]
  assign tlb_io_req_valid = s1_valid_masked & s1_cmd_uses_tlb; // @[DCache.scala 253:71]
  assign tlb_io_req_bits_vaddr = s1_tlb_req_vaddr; // @[DCache.scala 254:19]
  assign tlb_io_req_bits_size = s1_tlb_req_size; // @[DCache.scala 254:19]
  assign tlb_io_req_bits_cmd = s1_tlb_req_cmd; // @[DCache.scala 254:19]
  assign tlb_io_req_bits_prv = s1_tlb_req_prv; // @[DCache.scala 254:19]
  assign tlb_io_ptw_status_debug = io_ptw_status_debug; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_0_cfg_l = io_ptw_pmp_0_cfg_l; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_0_cfg_a = io_ptw_pmp_0_cfg_a; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_0_cfg_x = io_ptw_pmp_0_cfg_x; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_0_cfg_w = io_ptw_pmp_0_cfg_w; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_0_cfg_r = io_ptw_pmp_0_cfg_r; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_0_addr = io_ptw_pmp_0_addr; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_0_mask = io_ptw_pmp_0_mask; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_1_cfg_l = io_ptw_pmp_1_cfg_l; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_1_cfg_a = io_ptw_pmp_1_cfg_a; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_1_cfg_x = io_ptw_pmp_1_cfg_x; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_1_cfg_w = io_ptw_pmp_1_cfg_w; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_1_cfg_r = io_ptw_pmp_1_cfg_r; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_1_addr = io_ptw_pmp_1_addr; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_1_mask = io_ptw_pmp_1_mask; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_2_cfg_l = io_ptw_pmp_2_cfg_l; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_2_cfg_a = io_ptw_pmp_2_cfg_a; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_2_cfg_x = io_ptw_pmp_2_cfg_x; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_2_cfg_w = io_ptw_pmp_2_cfg_w; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_2_cfg_r = io_ptw_pmp_2_cfg_r; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_2_addr = io_ptw_pmp_2_addr; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_2_mask = io_ptw_pmp_2_mask; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_3_cfg_l = io_ptw_pmp_3_cfg_l; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_3_cfg_a = io_ptw_pmp_3_cfg_a; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_3_cfg_x = io_ptw_pmp_3_cfg_x; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_3_cfg_w = io_ptw_pmp_3_cfg_w; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_3_cfg_r = io_ptw_pmp_3_cfg_r; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_3_addr = io_ptw_pmp_3_addr; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_3_mask = io_ptw_pmp_3_mask; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_4_cfg_l = io_ptw_pmp_4_cfg_l; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_4_cfg_a = io_ptw_pmp_4_cfg_a; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_4_cfg_x = io_ptw_pmp_4_cfg_x; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_4_cfg_w = io_ptw_pmp_4_cfg_w; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_4_cfg_r = io_ptw_pmp_4_cfg_r; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_4_addr = io_ptw_pmp_4_addr; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_4_mask = io_ptw_pmp_4_mask; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_5_cfg_l = io_ptw_pmp_5_cfg_l; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_5_cfg_a = io_ptw_pmp_5_cfg_a; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_5_cfg_x = io_ptw_pmp_5_cfg_x; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_5_cfg_w = io_ptw_pmp_5_cfg_w; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_5_cfg_r = io_ptw_pmp_5_cfg_r; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_5_addr = io_ptw_pmp_5_addr; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_5_mask = io_ptw_pmp_5_mask; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_6_cfg_l = io_ptw_pmp_6_cfg_l; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_6_cfg_a = io_ptw_pmp_6_cfg_a; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_6_cfg_x = io_ptw_pmp_6_cfg_x; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_6_cfg_w = io_ptw_pmp_6_cfg_w; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_6_cfg_r = io_ptw_pmp_6_cfg_r; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_6_addr = io_ptw_pmp_6_addr; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_6_mask = io_ptw_pmp_6_mask; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_7_cfg_l = io_ptw_pmp_7_cfg_l; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_7_cfg_a = io_ptw_pmp_7_cfg_a; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_7_cfg_x = io_ptw_pmp_7_cfg_x; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_7_cfg_w = io_ptw_pmp_7_cfg_w; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_7_cfg_r = io_ptw_pmp_7_cfg_r; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_7_addr = io_ptw_pmp_7_addr; // @[DCache.scala 251:10]
  assign tlb_io_ptw_pmp_7_mask = io_ptw_pmp_7_mask; // @[DCache.scala 251:10]
  assign pma_checker_io_req_valid = 1'h0;
  assign pma_checker_io_req_bits_vaddr = 32'h0;
  assign pma_checker_io_req_bits_size = s1_req_size; // @[DCache.scala 271:27]
  assign pma_checker_io_req_bits_cmd = s1_req_cmd; // @[DCache.scala 271:27]
  assign pma_checker_io_req_bits_prv = 2'h0;
  assign pma_checker_io_ptw_status_debug = 1'h0;
  assign pma_checker_io_ptw_pmp_0_cfg_l = 1'h0;
  assign pma_checker_io_ptw_pmp_0_cfg_a = 2'h0;
  assign pma_checker_io_ptw_pmp_0_cfg_x = 1'h0;
  assign pma_checker_io_ptw_pmp_0_cfg_w = 1'h0;
  assign pma_checker_io_ptw_pmp_0_cfg_r = 1'h0;
  assign pma_checker_io_ptw_pmp_0_addr = 29'h0;
  assign pma_checker_io_ptw_pmp_0_mask = 31'h0;
  assign pma_checker_io_ptw_pmp_1_cfg_l = 1'h0;
  assign pma_checker_io_ptw_pmp_1_cfg_a = 2'h0;
  assign pma_checker_io_ptw_pmp_1_cfg_x = 1'h0;
  assign pma_checker_io_ptw_pmp_1_cfg_w = 1'h0;
  assign pma_checker_io_ptw_pmp_1_cfg_r = 1'h0;
  assign pma_checker_io_ptw_pmp_1_addr = 29'h0;
  assign pma_checker_io_ptw_pmp_1_mask = 31'h0;
  assign pma_checker_io_ptw_pmp_2_cfg_l = 1'h0;
  assign pma_checker_io_ptw_pmp_2_cfg_a = 2'h0;
  assign pma_checker_io_ptw_pmp_2_cfg_x = 1'h0;
  assign pma_checker_io_ptw_pmp_2_cfg_w = 1'h0;
  assign pma_checker_io_ptw_pmp_2_cfg_r = 1'h0;
  assign pma_checker_io_ptw_pmp_2_addr = 29'h0;
  assign pma_checker_io_ptw_pmp_2_mask = 31'h0;
  assign pma_checker_io_ptw_pmp_3_cfg_l = 1'h0;
  assign pma_checker_io_ptw_pmp_3_cfg_a = 2'h0;
  assign pma_checker_io_ptw_pmp_3_cfg_x = 1'h0;
  assign pma_checker_io_ptw_pmp_3_cfg_w = 1'h0;
  assign pma_checker_io_ptw_pmp_3_cfg_r = 1'h0;
  assign pma_checker_io_ptw_pmp_3_addr = 29'h0;
  assign pma_checker_io_ptw_pmp_3_mask = 31'h0;
  assign pma_checker_io_ptw_pmp_4_cfg_l = 1'h0;
  assign pma_checker_io_ptw_pmp_4_cfg_a = 2'h0;
  assign pma_checker_io_ptw_pmp_4_cfg_x = 1'h0;
  assign pma_checker_io_ptw_pmp_4_cfg_w = 1'h0;
  assign pma_checker_io_ptw_pmp_4_cfg_r = 1'h0;
  assign pma_checker_io_ptw_pmp_4_addr = 29'h0;
  assign pma_checker_io_ptw_pmp_4_mask = 31'h0;
  assign pma_checker_io_ptw_pmp_5_cfg_l = 1'h0;
  assign pma_checker_io_ptw_pmp_5_cfg_a = 2'h0;
  assign pma_checker_io_ptw_pmp_5_cfg_x = 1'h0;
  assign pma_checker_io_ptw_pmp_5_cfg_w = 1'h0;
  assign pma_checker_io_ptw_pmp_5_cfg_r = 1'h0;
  assign pma_checker_io_ptw_pmp_5_addr = 29'h0;
  assign pma_checker_io_ptw_pmp_5_mask = 31'h0;
  assign pma_checker_io_ptw_pmp_6_cfg_l = 1'h0;
  assign pma_checker_io_ptw_pmp_6_cfg_a = 2'h0;
  assign pma_checker_io_ptw_pmp_6_cfg_x = 1'h0;
  assign pma_checker_io_ptw_pmp_6_cfg_w = 1'h0;
  assign pma_checker_io_ptw_pmp_6_cfg_r = 1'h0;
  assign pma_checker_io_ptw_pmp_6_addr = 29'h0;
  assign pma_checker_io_ptw_pmp_6_mask = 31'h0;
  assign pma_checker_io_ptw_pmp_7_cfg_l = 1'h0;
  assign pma_checker_io_ptw_pmp_7_cfg_a = 2'h0;
  assign pma_checker_io_ptw_pmp_7_cfg_x = 1'h0;
  assign pma_checker_io_ptw_pmp_7_cfg_w = 1'h0;
  assign pma_checker_io_ptw_pmp_7_cfg_r = 1'h0;
  assign pma_checker_io_ptw_pmp_7_addr = 29'h0;
  assign pma_checker_io_ptw_pmp_7_mask = 31'h0;
  assign lfsr_prng_clock = clock;
  assign lfsr_prng_reset = reset;
  assign lfsr_prng_io_increment = _T_272 & _GEN_218; // @[DCache.scala 649:26 Replacement.scala 38:11]
  assign metaArb_io_in_0_valid = resetting; // @[DCache.scala 1020:26]
  assign metaArb_io_in_0_bits_addr = metaArb_io_in_5_bits_addr; // @[DCache.scala 1021:25]
  assign metaArb_io_in_0_bits_idx = metaArb_io_in_5_bits_idx; // @[DCache.scala 1021:25]
  assign metaArb_io_in_2_valid = s2_valid_hit_pre_data_ecc_and_waw & s2_update_meta; // @[DCache.scala 437:63]
  assign metaArb_io_in_2_bits_addr = {io_cpu_req_bits_addr[31:12],s2_vaddr[11:0]}; // @[Cat.scala 31:58]
  assign metaArb_io_in_2_bits_idx = s2_vaddr[11:6]; // @[DCache.scala 440:40]
  assign metaArb_io_in_2_bits_way_en = s2_hit_valid ? s2_hit_way : s2_victim_way; // @[DCache.scala 407:33]
  assign metaArb_io_in_2_bits_data = {s2_grow_param,metaArb_io_in_2_bits_data_meta_tag}; // @[DCache.scala 442:97]
  assign metaArb_io_in_3_valid = grantIsCached & d_done & ~auto_out_d_bits_denied; // @[DCache.scala 716:53]
  assign metaArb_io_in_3_bits_addr = {io_cpu_req_bits_addr[31:12],s2_vaddr[11:0]}; // @[Cat.scala 31:58]
  assign metaArb_io_in_3_bits_idx = s2_vaddr[11:6]; // @[DCache.scala 719:40]
  assign metaArb_io_in_3_bits_way_en = refill_way; // @[DCache.scala 718:32]
  assign metaArb_io_in_3_bits_data = {metaArb_io_in_3_bits_data_meta_state,metaArb_io_in_2_bits_data_meta_tag}; // @[DCache.scala 721:134]
  assign metaArb_io_in_4_valid = _T_310 | _metaArb_io_in_4_valid_T_1; // @[package.scala 72:59]
  assign metaArb_io_in_4_bits_addr = {io_cpu_req_bits_addr[31:12],probe_bits_address[11:0]}; // @[Cat.scala 31:58]
  assign metaArb_io_in_4_bits_idx = probe_bits_address[11:6]; // @[DCache.scala 1174:47]
  assign metaArb_io_in_4_bits_way_en = _T_313 ? s2_victim_or_hit_way : s2_probe_way; // @[DCache.scala 838:102 788:14 852:18]
  assign metaArb_io_in_4_bits_data = {newCoh_state,metaArb_io_in_4_bits_data_meta_tag}; // @[DCache.scala 888:97]
  assign metaArb_io_in_5_valid = 1'h0; // @[DCache.scala 989:38]
  assign metaArb_io_in_5_bits_addr = {io_cpu_req_bits_addr[31:12],_metaArb_io_in_5_bits_addr_T_1}; // @[Cat.scala 31:58]
  assign metaArb_io_in_5_bits_idx = flushCounter[5:0]; // @[DCache.scala 991:44]
  assign metaArb_io_in_6_valid = release_state == 4'h4 | auto_out_b_valid & (~block_probe_for_core_progress |
    lrscBackingOff); // @[DCache.scala 744:26 816:44 817:30]
  assign metaArb_io_in_6_bits_addr = release_state == 4'h4 ? _metaArb_io_in_6_bits_addr_T_3 :
    _metaArb_io_in_6_bits_addr_T_1; // @[DCache.scala 748:30 816:44 819:34]
  assign metaArb_io_in_6_bits_idx = release_state == 4'h4 ? probe_bits_address[11:6] : auto_out_b_bits_address[11:6]; // @[DCache.scala 747:29 816:44 818:33]
  assign metaArb_io_in_6_bits_way_en = metaArb_io_in_4_bits_way_en; // @[DCache.scala 749:32]
  assign metaArb_io_in_6_bits_data = metaArb_io_in_4_bits_data; // @[DCache.scala 750:30]
  assign metaArb_io_in_7_valid = io_cpu_req_valid; // @[DCache.scala 241:26]
  assign metaArb_io_in_7_bits_addr = io_cpu_req_bits_addr; // @[DCache.scala 244:30]
  assign metaArb_io_in_7_bits_idx = dataArb_io_in_3_bits_addr[11:6]; // @[DCache.scala 243:58]
  assign metaArb_io_in_7_bits_way_en = metaArb_io_in_4_bits_way_en; // @[DCache.scala 245:32]
  assign metaArb_io_in_7_bits_data = metaArb_io_in_4_bits_data; // @[DCache.scala 246:30]
  assign tag_array_RW0_clk = clock; // @[DCache.scala 285:50]
  assign tag_array_RW0_wdata_0 = metaArb_io_out_bits_data; // @[compatibility.scala 134:{12,12}]
  assign tag_array_RW0_wdata_1 = metaArb_io_out_bits_data; // @[compatibility.scala 134:{12,12}]
  assign tag_array_RW0_wmask_0 = metaArb_io_out_bits_way_en[0]; // @[DCache.scala 286:74]
  assign tag_array_RW0_wmask_1 = metaArb_io_out_bits_way_en[1]; // @[DCache.scala 286:74]
  assign data_clock = clock;
  assign data_io_req_valid = dataArb_io_out_valid; // @[DCache.scala 135:15]
  assign data_io_req_bits_addr = dataArb_io_out_bits_addr; // @[DCache.scala 135:15]
  assign data_io_req_bits_write = dataArb_io_out_bits_write; // @[DCache.scala 135:15]
  assign data_io_req_bits_wdata = dataArb_io_out_bits_wdata; // @[DCache.scala 135:15]
  assign data_io_req_bits_eccMask = dataArb_io_out_bits_eccMask; // @[DCache.scala 135:15]
  assign data_io_req_bits_way_en = dataArb_io_out_bits_way_en; // @[DCache.scala 135:15]
  assign dataArb_io_in_0_valid = pstore_drain_structural | _pstore_drain_T_10; // @[DCache.scala 492:48]
  assign dataArb_io_in_0_bits_addr = _dataArb_io_in_0_bits_addr_T[11:0]; // @[DCache.scala 524:30]
  assign dataArb_io_in_0_bits_write = pstore_drain_structural | _pstore_drain_T_10; // @[DCache.scala 492:48]
  assign dataArb_io_in_0_bits_wdata = {dataArb_io_in_0_bits_wdata_hi,dataArb_io_in_0_bits_wdata_lo}; // @[Cat.scala 31:58]
  assign dataArb_io_in_0_bits_eccMask = {dataArb_io_in_0_bits_eccMask_hi,dataArb_io_in_0_bits_eccMask_lo}; // @[Cat.scala 31:58]
  assign dataArb_io_in_0_bits_way_en = pstore2_valid ? pstore2_way : pstore1_way; // @[DCache.scala 525:38]
  assign dataArb_io_in_1_valid = grantIsUncachedData & (blockUncachedGrant | s1_valid) ? _GEN_244 : auto_out_d_valid &
    grantIsRefill & canAcceptCachedGrant; // @[DCache.scala 696:26 727:68]
  assign dataArb_io_in_1_bits_addr = _dataArb_io_in_1_bits_addr_T_2[11:0]; // @[DCache.scala 703:32]
  assign dataArb_io_in_1_bits_write = grantIsUncachedData & (blockUncachedGrant | s1_valid) ? _GEN_245 : 1'h1; // @[DCache.scala 702:33 727:68]
  assign dataArb_io_in_1_bits_wdata = {tl_d_data_encoded_hi,tl_d_data_encoded_lo}; // @[Cat.scala 31:58]
  assign dataArb_io_in_1_bits_way_en = refill_way; // @[DCache.scala 704:34]
  assign dataArb_io_in_2_valid = inWriteback & releaseDataBeat < 11'h10; // @[DCache.scala 875:41]
  assign dataArb_io_in_2_bits_addr = _dataArb_io_in_2_bits_addr_T_1 | _GEN_373; // @[DCache.scala 878:72]
  assign dataArb_io_in_2_bits_wdata = dataArb_io_in_1_bits_wdata; // @[DCache.scala 876:25]
  assign dataArb_io_in_3_valid = io_cpu_req_valid & res; // @[DCache.scala 222:46]
  assign dataArb_io_in_3_bits_addr = _dataArb_io_in_3_bits_addr_T_2[11:0]; // @[DCache.scala 225:30]
  assign dataArb_io_in_3_bits_wdata = dataArb_io_in_1_bits_wdata; // @[DCache.scala 223:25]
  assign dataArb_io_in_3_bits_wordMask = 1'h1; // @[DCache.scala 226:34]
  assign amoalu_io_mask = pstore1_mask; // @[DCache.scala 957:38]
  assign amoalu_io_cmd = pstore1_cmd; // @[DCache.scala 958:21]
  assign amoalu_io_lhs = {s2_data_corrected_hi,s2_data_corrected_lo}; // @[Cat.scala 31:58]
  assign amoalu_io_rhs = pstore1_data; // @[DCache.scala 960:37]
  assign tag_array_RW0_en = s0_clk_en | _T_19;
  assign tag_array_RW0_wmode = metaArb_io_out_bits_write;
  assign tag_array_RW0_addr = _T_19 ? _GEN_44 : _GEN_44;
  always @(posedge clock) begin
    if (reset) begin // @[DCache.scala 162:21]
      s1_valid <= 1'h0; // @[DCache.scala 162:21]
    end else begin
      s1_valid <= s1_valid_x12; // @[DCache.scala 162:21]
    end
    if (reset) begin // @[DCache.scala 643:38]
      blockProbeAfterGrantCount <= 3'h0; // @[DCache.scala 643:38]
    end else if (_T_272) begin // @[DCache.scala 649:26]
      if (grantIsCached) begin // @[DCache.scala 650:26]
        if (d_last) begin // @[DCache.scala 653:20]
          blockProbeAfterGrantCount <= 3'h7; // @[DCache.scala 656:35]
        end else begin
          blockProbeAfterGrantCount <= _GEN_192;
        end
      end else begin
        blockProbeAfterGrantCount <= _GEN_192;
      end
    end else begin
      blockProbeAfterGrantCount <= _GEN_192;
    end
    if (reset) begin // @[DCache.scala 447:22]
      lrscCount <= 7'h0; // @[DCache.scala 447:22]
    end else if (s1_probe) begin // @[DCache.scala 459:19]
      lrscCount <= 7'h0; // @[DCache.scala 459:31]
    end else if (s2_valid_masked & lrscValid) begin // @[DCache.scala 458:43]
      lrscCount <= 7'h3; // @[DCache.scala 458:55]
    end else if (_lrscBackingOff_T) begin // @[DCache.scala 457:24]
      lrscCount <= _lrscCount_T_2; // @[DCache.scala 457:36]
    end else begin
      lrscCount <= _GEN_129;
    end
    if (reset) begin // @[DCache.scala 163:21]
      s1_probe <= 1'h0; // @[DCache.scala 163:21]
    end else if (release_state == 4'h4) begin // @[DCache.scala 816:44]
      s1_probe <= _GEN_304;
    end else begin
      s1_probe <= s1_probe_x16; // @[DCache.scala 163:21]
    end
    if (reset) begin // @[DCache.scala 308:21]
      s2_probe <= 1'h0; // @[DCache.scala 308:21]
    end else begin
      s2_probe <= s1_probe; // @[DCache.scala 308:21]
    end
    if (reset) begin // @[DCache.scala 208:26]
      release_state <= 4'h0; // @[DCache.scala 208:26]
    end else if (_T_317) begin // @[DCache.scala 889:34]
      release_state <= 4'h0; // @[DCache.scala 889:50]
    end else if (_T_313) begin // @[DCache.scala 838:102]
      if (releaseDone) begin // @[DCache.scala 853:26]
        release_state <= 4'h6; // @[DCache.scala 853:42]
      end else begin
        release_state <= _GEN_331;
      end
    end else begin
      release_state <= _GEN_331;
    end
    if (reset) begin // @[DCache.scala 206:29]
      release_ack_wait <= 1'h0; // @[DCache.scala 206:29]
    end else if (_T_313) begin // @[DCache.scala 838:102]
      release_ack_wait <= _GEN_340;
    end else if (_T_272) begin // @[DCache.scala 649:26]
      if (!(grantIsCached)) begin // @[DCache.scala 650:26]
        release_ack_wait <= _GEN_214;
      end
    end
    if (_T_313) begin // @[DCache.scala 838:102]
      if (_T_298 & c_first) begin // @[DCache.scala 854:41]
        release_ack_addr <= probe_bits_address; // @[DCache.scala 856:26]
      end
    end
    if (reset) begin // @[DCache.scala 642:28]
      grantInProgress <= 1'h0; // @[DCache.scala 642:28]
    end else if (_T_272) begin // @[DCache.scala 649:26]
      if (grantIsCached) begin // @[DCache.scala 650:26]
        if (d_last) begin // @[DCache.scala 653:20]
          grantInProgress <= 1'h0; // @[DCache.scala 655:25]
        end else begin
          grantInProgress <= 1'h1; // @[DCache.scala 651:23]
        end
      end
    end
    if (reset) begin // @[DCache.scala 306:21]
      s2_valid <= 1'h0; // @[DCache.scala 306:21]
    end else begin
      s2_valid <= s2_valid_x44; // @[DCache.scala 306:21]
    end
    if (s2_want_victimize) begin // @[DCache.scala 791:25]
      probe_bits_param <= 2'h0; // @[DCache.scala 797:18]
    end else if (s1_probe_x16) begin // @[Reg.scala 17:18]
      probe_bits_param <= auto_out_b_bits_param; // @[Reg.scala 17:22]
    end
    if (s2_want_victimize) begin // @[DCache.scala 791:25]
      probe_bits_size <= 4'h0; // @[DCache.scala 797:18]
    end else if (s1_probe_x16) begin // @[Reg.scala 17:18]
      probe_bits_size <= auto_out_b_bits_size; // @[Reg.scala 17:22]
    end
    if (s2_want_victimize) begin // @[DCache.scala 791:25]
      probe_bits_source <= 1'h0; // @[DCache.scala 797:18]
    end else if (s1_probe_x16) begin // @[Reg.scala 17:18]
      probe_bits_source <= auto_out_b_bits_source; // @[Reg.scala 17:22]
    end
    if (s2_want_victimize) begin // @[DCache.scala 791:25]
      probe_bits_address <= res_2_address; // @[DCache.scala 797:18]
    end else if (s1_probe_x16) begin // @[Reg.scala 17:18]
      probe_bits_address <= auto_out_b_bits_address; // @[Reg.scala 17:22]
    end
    if (s1_probe) begin // @[Reg.scala 17:18]
      s2_probe_state_state <= s1_meta_hit_state_state; // @[Reg.scala 17:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      counter_1 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_T_298) begin // @[Edges.scala 234:17]
      if (c_first) begin // @[Edges.scala 235:21]
        if (beats1_opdata_1) begin // @[Edges.scala 220:14]
          counter_1 <= beats1_decode_1;
        end else begin
          counter_1 <= 10'h0;
        end
      end else begin
        counter_1 <= counter1_1;
      end
    end
    s2_release_data_valid <= s1_release_data_valid & ~releaseRejected; // @[DCache.scala 777:64]
    if (s0_clk_en) begin // @[Reg.scala 17:18]
      s1_req_cmd <= io_cpu_req_bits_cmd; // @[Reg.scala 17:22]
    end
    if (_T_272) begin // @[DCache.scala 649:26]
      if (grantIsCached) begin // @[DCache.scala 650:26]
        s2_req_cmd <= _GEN_57;
      end else if (grantIsUncached) begin // @[DCache.scala 659:35]
        if (grantIsUncachedData) begin // @[DCache.scala 666:34]
          s2_req_cmd <= 5'h0; // @[DCache.scala 670:22]
        end else begin
          s2_req_cmd <= _GEN_57;
        end
      end else begin
        s2_req_cmd <= _GEN_57;
      end
    end else begin
      s2_req_cmd <= _GEN_57;
    end
    if (reset) begin // @[DCache.scala 479:29]
      pstore1_held <= 1'h0; // @[DCache.scala 479:29]
    end else begin
      pstore1_held <= pstore1_valid & pstore2_valid & ~pstore_drain; // @[DCache.scala 496:16]
    end
    if (_pstore1_cmd_T) begin // @[Reg.scala 17:18]
      pstore1_addr <= s1_vaddr; // @[Reg.scala 17:22]
    end
    if (s0_clk_en) begin // @[Reg.scala 17:18]
      s1_req_addr <= s0_req_addr; // @[Reg.scala 17:22]
    end
    if (_pstore1_cmd_T) begin // @[Reg.scala 17:18]
      if (_s1_write_T_1) begin // @[DCache.scala 302:20]
        pstore1_mask <= io_cpu_s1_data_mask;
      end else begin
        pstore1_mask <= s1_mask_xwr;
      end
    end
    if (s0_clk_en) begin // @[Reg.scala 17:18]
      s1_req_size <= io_cpu_req_bits_size; // @[Reg.scala 17:22]
    end
    if (reset) begin // @[DCache.scala 476:30]
      pstore2_valid <= 1'h0; // @[DCache.scala 476:30]
    end else begin
      pstore2_valid <= pstore2_valid & _pstore1_held_T_9 | advance_pstore1; // @[DCache.scala 498:17]
    end
    if (advance_pstore1) begin // @[Reg.scala 17:18]
      pstore2_addr <= pstore1_addr; // @[Reg.scala 17:22]
    end
    if (advance_pstore1) begin // @[DCache.scala 507:45]
      mask <= _pstore2_storegen_mask_mask_T_2; // @[DCache.scala 509:12]
    end
    s2_not_nacked_in_s1 <= ~s1_nack; // @[DCache.scala 310:37]
    if (_T_54) begin // @[Reg.scala 17:18]
      s2_hit_state_state <= s1_meta_hit_state_state; // @[Reg.scala 17:22]
    end
    if (s0_clk_en) begin // @[Reg.scala 17:18]
      s1_req_tag <= io_cpu_req_bits_tag; // @[Reg.scala 17:22]
    end
    if (s0_clk_en) begin // @[Reg.scala 17:18]
      s1_req_signed <= io_cpu_req_bits_signed; // @[Reg.scala 17:22]
    end
    if (s0_clk_en) begin // @[Reg.scala 17:18]
      s1_req_dprv <= io_cpu_req_bits_dprv; // @[Reg.scala 17:22]
    end
    if (s0_clk_en) begin // @[Reg.scala 17:18]
      s1_tlb_req_vaddr <= s0_req_addr; // @[Reg.scala 17:22]
    end
    if (s0_clk_en) begin // @[Reg.scala 17:18]
      s1_tlb_req_size <= io_cpu_req_bits_size; // @[Reg.scala 17:22]
    end
    if (s0_clk_en) begin // @[Reg.scala 17:18]
      s1_tlb_req_cmd <= io_cpu_req_bits_cmd; // @[Reg.scala 17:22]
    end
    if (s0_clk_en) begin // @[Reg.scala 17:18]
      s1_tlb_req_prv <= io_cpu_req_bits_dprv; // @[Reg.scala 17:22]
    end
    s1_flush_valid <= _s1_flush_valid_T & _T_35 & _s2_cannot_victimize_T & _io_cpu_req_ready_T & _tl_out_a_valid_T_7; // @[DCache.scala 988:124]
    if (reset) begin // @[DCache.scala 203:30]
      cached_grant_wait <= 1'h0; // @[DCache.scala 203:30]
    end else if (_T_272) begin // @[DCache.scala 649:26]
      if (grantIsCached) begin // @[DCache.scala 650:26]
        if (d_last) begin // @[DCache.scala 653:20]
          cached_grant_wait <= 1'h0; // @[DCache.scala 654:27]
        end else begin
          cached_grant_wait <= _GEN_189;
        end
      end else begin
        cached_grant_wait <= _GEN_189;
      end
    end else begin
      cached_grant_wait <= _GEN_189;
    end
    if (reset) begin // @[DCache.scala 204:26]
      resetting <= 1'h0; // @[DCache.scala 204:26]
    end else if (resetting) begin // @[DCache.scala 1025:20]
      if (flushDone) begin // @[DCache.scala 1027:22]
        resetting <= 1'h0; // @[DCache.scala 1028:17]
      end else begin
        resetting <= _GEN_358;
      end
    end else begin
      resetting <= _GEN_358;
    end
    if (reset) begin // @[DCache.scala 205:25]
      flushCounter <= 7'h40; // @[DCache.scala 205:25]
    end else begin
      flushCounter <= _GEN_360[6:0];
    end
    if (_T_264) begin // @[DCache.scala 606:26]
      if (!(s2_uncached)) begin // @[DCache.scala 607:24]
        if (s2_hit_valid) begin // @[DCache.scala 407:33]
          refill_way <= s2_hit_way;
        end else begin
          refill_way <= s2_victim_way;
        end
      end
    end
    if (reset) begin // @[DCache.scala 216:33]
      uncachedInFlight_0 <= 1'h0; // @[DCache.scala 216:33]
    end else if (_T_272) begin // @[DCache.scala 649:26]
      if (grantIsCached) begin // @[DCache.scala 650:26]
        uncachedInFlight_0 <= _GEN_176;
      end else if (grantIsUncached) begin // @[DCache.scala 659:35]
        uncachedInFlight_0 <= _GEN_197;
      end else begin
        uncachedInFlight_0 <= _GEN_176;
      end
    end else begin
      uncachedInFlight_0 <= _GEN_176;
    end
    if (_T_264) begin // @[DCache.scala 606:26]
      if (s2_uncached) begin // @[DCache.scala 607:24]
        if (a_sel) begin // @[DCache.scala 609:18]
          uncachedReqs_0_addr <= s2_req_addr; // @[DCache.scala 611:13]
        end
      end
    end
    if (_T_264) begin // @[DCache.scala 606:26]
      if (s2_uncached) begin // @[DCache.scala 607:24]
        if (a_sel) begin // @[DCache.scala 609:18]
          uncachedReqs_0_tag <= s2_req_tag; // @[DCache.scala 611:13]
        end
      end
    end
    if (_T_264) begin // @[DCache.scala 606:26]
      if (s2_uncached) begin // @[DCache.scala 607:24]
        if (a_sel) begin // @[DCache.scala 609:18]
          uncachedReqs_0_size <= s2_req_size; // @[DCache.scala 611:13]
        end
      end
    end
    if (_T_264) begin // @[DCache.scala 606:26]
      if (s2_uncached) begin // @[DCache.scala 607:24]
        if (a_sel) begin // @[DCache.scala 609:18]
          uncachedReqs_0_signed <= s2_req_signed; // @[DCache.scala 611:13]
        end
      end
    end
    if (s0_clk_en) begin // @[Reg.scala 17:18]
      s1_did_read <= _s1_did_read_T_54; // @[Reg.scala 17:22]
    end
    if (s0_clk_en) begin // @[Reg.scala 17:18]
      s1_read_mask <= dataArb_io_in_3_bits_wordMask; // @[Reg.scala 17:22]
    end
    if (s1_valid_not_nacked) begin // @[Reg.scala 17:18]
      s2_hit_way <= s1_meta_hit_way; // @[Reg.scala 17:22]
    end
    if (_T_54) begin // @[Reg.scala 17:18]
      s2_victim_way_r <= s1_victim_way; // @[Reg.scala 17:22]
    end
    if (s1_probe) begin // @[Reg.scala 17:18]
      s2_probe_way <= s1_meta_hit_way; // @[Reg.scala 17:22]
    end
    if (_T_272) begin // @[DCache.scala 649:26]
      if (grantIsCached) begin // @[DCache.scala 650:26]
        s2_req_addr <= _GEN_55;
      end else if (grantIsUncached) begin // @[DCache.scala 659:35]
        if (grantIsUncachedData) begin // @[DCache.scala 666:34]
          s2_req_addr <= {{1'd0}, _s2_req_addr_T_1}; // @[DCache.scala 674:23]
        end else begin
          s2_req_addr <= _GEN_55;
        end
      end else begin
        s2_req_addr <= _GEN_55;
      end
    end else begin
      s2_req_addr <= _GEN_55;
    end
    if (_T_272) begin // @[DCache.scala 649:26]
      if (grantIsCached) begin // @[DCache.scala 650:26]
        s2_req_tag <= _GEN_56;
      end else if (grantIsUncached) begin // @[DCache.scala 659:35]
        if (grantIsUncachedData) begin // @[DCache.scala 666:34]
          s2_req_tag <= uncachedReqs_0_tag; // @[DCache.scala 673:22]
        end else begin
          s2_req_tag <= _GEN_56;
        end
      end else begin
        s2_req_tag <= _GEN_56;
      end
    end else begin
      s2_req_tag <= _GEN_56;
    end
    if (_T_272) begin // @[DCache.scala 649:26]
      if (grantIsCached) begin // @[DCache.scala 650:26]
        s2_req_size <= _GEN_58;
      end else if (grantIsUncached) begin // @[DCache.scala 659:35]
        if (grantIsUncachedData) begin // @[DCache.scala 666:34]
          s2_req_size <= uncachedReqs_0_size; // @[DCache.scala 671:23]
        end else begin
          s2_req_size <= _GEN_58;
        end
      end else begin
        s2_req_size <= _GEN_58;
      end
    end else begin
      s2_req_size <= _GEN_58;
    end
    if (_T_272) begin // @[DCache.scala 649:26]
      if (grantIsCached) begin // @[DCache.scala 650:26]
        s2_req_signed <= _GEN_59;
      end else if (grantIsUncached) begin // @[DCache.scala 659:35]
        if (grantIsUncachedData) begin // @[DCache.scala 666:34]
          s2_req_signed <= uncachedReqs_0_signed; // @[DCache.scala 672:25]
        end else begin
          s2_req_signed <= _GEN_59;
        end
      end else begin
        s2_req_signed <= _GEN_59;
      end
    end else begin
      s2_req_signed <= _GEN_59;
    end
    if (s1_valid_not_nacked | s1_flush_valid) begin // @[DCache.scala 320:48]
      s2_req_dprv <= s1_req_dprv; // @[DCache.scala 321:12]
    end
    if (s1_valid_not_nacked | s1_flush_valid) begin // @[DCache.scala 320:48]
      s2_tlb_xcpt_pf_ld <= tlb_io_resp_pf_ld; // @[DCache.scala 323:17]
    end
    if (s1_valid_not_nacked | s1_flush_valid) begin // @[DCache.scala 320:48]
      s2_tlb_xcpt_pf_st <= tlb_io_resp_pf_st; // @[DCache.scala 323:17]
    end
    if (s1_valid_not_nacked | s1_flush_valid) begin // @[DCache.scala 320:48]
      s2_tlb_xcpt_ae_ld <= tlb_io_resp_ae_ld; // @[DCache.scala 323:17]
    end
    if (s1_valid_not_nacked | s1_flush_valid) begin // @[DCache.scala 320:48]
      s2_tlb_xcpt_ae_st <= tlb_io_resp_ae_st; // @[DCache.scala 323:17]
    end
    if (s1_valid_not_nacked | s1_flush_valid) begin // @[DCache.scala 320:48]
      s2_tlb_xcpt_ma_ld <= tlb_io_resp_ma_ld; // @[DCache.scala 323:17]
    end
    if (s1_valid_not_nacked | s1_flush_valid) begin // @[DCache.scala 320:48]
      s2_tlb_xcpt_ma_st <= tlb_io_resp_ma_st; // @[DCache.scala 323:17]
    end
    if (s1_valid_not_nacked | s1_flush_valid) begin // @[DCache.scala 320:48]
      s2_pma_cacheable <= tlb_io_resp_cacheable; // @[DCache.scala 324:12]
    end
    if (_T_272) begin // @[DCache.scala 649:26]
      if (!(grantIsCached)) begin // @[DCache.scala 650:26]
        if (grantIsUncached) begin // @[DCache.scala 659:35]
          if (grantIsUncachedData) begin // @[DCache.scala 666:34]
            s2_uncached_resp_addr <= uncachedReqs_0_addr; // @[DCache.scala 679:33]
          end
        end
      end
    end
    if (_T_54) begin // @[Reg.scala 17:18]
      s2_vaddr_r <= s1_vaddr; // @[Reg.scala 17:22]
    end
    s2_flush_valid_pre_tag_ecc <= s1_flush_valid; // @[DCache.scala 330:43]
    if (s1_meta_clk_en) begin // @[Reg.scala 17:18]
      s2_meta_corrected_r <= tag_array_RW0_rdata_0; // @[Reg.scala 17:22]
    end
    if (s1_meta_clk_en) begin // @[Reg.scala 17:18]
      s2_meta_corrected_r_1 <= tag_array_RW0_rdata_1; // @[Reg.scala 17:22]
    end
    if (grantIsUncachedData & (blockUncachedGrant | s1_valid)) begin // @[DCache.scala 727:68]
      if (auto_out_d_valid) begin // @[DCache.scala 730:29]
        blockUncachedGrant <= _T_292; // @[DCache.scala 734:28]
      end else begin
        blockUncachedGrant <= dataArb_io_out_valid; // @[DCache.scala 726:24]
      end
    end else begin
      blockUncachedGrant <= dataArb_io_out_valid; // @[DCache.scala 726:24]
    end
    if (reset) begin // @[Edges.scala 228:27]
      counter <= 10'h0; // @[Edges.scala 228:27]
    end else if (_T_272) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (beats1_opdata) begin // @[Edges.scala 220:14]
          counter <= beats1_decode;
        end else begin
          counter <= 10'h0;
        end
      end else begin
        counter <= counter1;
      end
    end
    if (en) begin // @[Reg.scala 17:18]
      s2_data <= _s2_data_T_9; // @[Reg.scala 17:22]
    end
    if (s2_valid_hit_pre_data_ecc_and_waw & _c_cat_T_48 & _io_cpu_req_ready_T_1 | s2_valid_cached_miss) begin // @[DCache.scala 453:99]
      lrscAddr <= s2_req_addr[31:6]; // @[DCache.scala 455:14]
    end
    if (_pstore1_cmd_T) begin // @[Reg.scala 17:18]
      pstore1_cmd <= s1_req_cmd; // @[Reg.scala 17:22]
    end
    if (_pstore1_cmd_T) begin // @[Reg.scala 17:18]
      pstore1_data <= io_cpu_s1_data_data; // @[Reg.scala 17:22]
    end
    if (_pstore1_cmd_T) begin // @[Reg.scala 17:18]
      pstore1_way <= s1_meta_hit_way; // @[Reg.scala 17:22]
    end
    if (_pstore1_cmd_T) begin // @[Reg.scala 17:18]
      pstore1_rmw_r <= _pstore1_rmw_T_52; // @[Reg.scala 17:22]
    end
    pstore_drain_on_miss_REG <= io_cpu_s2_nack; // @[DCache.scala 478:56]
    if (advance_pstore1) begin // @[Reg.scala 17:18]
      pstore2_way <= pstore1_way; // @[Reg.scala 17:22]
    end
    if (advance_pstore1) begin // @[Reg.scala 17:18]
      pstore2_storegen_data_r <= pstore1_storegen_data[7:0]; // @[Reg.scala 17:22]
    end
    if (advance_pstore1) begin // @[Reg.scala 17:18]
      pstore2_storegen_data_r_1 <= pstore1_storegen_data[15:8]; // @[Reg.scala 17:22]
    end
    if (advance_pstore1) begin // @[Reg.scala 17:18]
      pstore2_storegen_data_r_2 <= pstore1_storegen_data[23:16]; // @[Reg.scala 17:22]
    end
    if (advance_pstore1) begin // @[Reg.scala 17:18]
      pstore2_storegen_data_r_3 <= pstore1_storegen_data[31:24]; // @[Reg.scala 17:22]
    end
    s1_release_data_valid <= dataArb_io_in_2_ready & dataArb_io_in_2_valid; // @[Decoupled.scala 50:35]
    io_cpu_s2_xcpt_REG <= tlb_io_req_valid & _s1_valid_not_nacked_T; // @[DCache.scala 906:65]
    doUncachedResp <= io_cpu_replay_next; // @[DCache.scala 922:27]
    REG <= reset; // @[compatibility.scala 290:56]
    if (reset) begin // @[Edges.scala 228:27]
      io_cpu_perf_release_counter <= 10'h0; // @[Edges.scala 228:27]
    end else if (_T_298) begin // @[Edges.scala 234:17]
      if (io_cpu_perf_release_first) begin // @[Edges.scala 235:21]
        if (beats1_opdata_1) begin // @[Edges.scala 220:14]
          io_cpu_perf_release_counter <= beats1_decode_1;
        end else begin
          io_cpu_perf_release_counter <= 10'h0;
        end
      end else begin
        io_cpu_perf_release_counter <= io_cpu_perf_release_counter1;
      end
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~_dataArb_io_in_3_valid_T_52 | res) & ~reset) begin
          $fatal; // @[DCache.scala 1160:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~_dataArb_io_in_3_valid_T_52 | res)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at DCache.scala:1160 assert(!needsRead(req) || res)\n"); // @[DCache.scala 1160:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(s1_valid_masked & _s1_write_T_1) | &_T_48) & _dataArb_io_in_3_valid_T_56) begin
          $fatal; // @[DCache.scala 304:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_dataArb_io_in_3_valid_T_56 & ~(~(s1_valid_masked & _s1_write_T_1) | &_T_48)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at DCache.scala:304 assert(!(s1_valid_masked && s1_req.cmd === M_PWR) || (s1_mask_xwr | ~io.cpu.s1_data.mask).andR)\n"
            ); // @[DCache.scala 304:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~_dataArb_io_in_3_valid_T_52 | res) & ~reset) begin
          $fatal; // @[DCache.scala 1160:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~_dataArb_io_in_3_valid_T_52 | res)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at DCache.scala:1160 assert(!needsRead(req) || res)\n"); // @[DCache.scala 1160:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(pstore1_rmw_r | _T_255 == pstore1_valid) & _dataArb_io_in_3_valid_T_56) begin
          $fatal; // @[DCache.scala 485:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_dataArb_io_in_3_valid_T_56 & ~(pstore1_rmw_r | _T_255 == pstore1_valid)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at DCache.scala:485 assert(pstore1_rmw || pstore1_valid_not_rmw(io.cpu.s2_kill) === pstore1_valid)\n"
            ); // @[DCache.scala 485:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_io_cpu_req_ready_T_1 & (_T_272 & grantIsCached & _dataArb_io_in_3_valid_T_56)) begin
          $fatal; // @[DCache.scala 652:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_272 & grantIsCached & _dataArb_io_in_3_valid_T_56 & _io_cpu_req_ready_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: A GrantData was unexpected by the dcache.\n    at DCache.scala:652 assert(cached_grant_wait, \"A GrantData was unexpected by the dcache.\")\n"
            ); // @[DCache.scala 652:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_a_source_T & (_T_272 & _T_333 & grantIsUncached & _T_277 & _dataArb_io_in_3_valid_T_56)) begin
          $fatal; // @[DCache.scala 662:17]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_272 & _T_333 & grantIsUncached & _T_277 & _dataArb_io_in_3_valid_T_56 & _a_source_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: An AccessAck was unexpected by the dcache.\n    at DCache.scala:662 assert(f, \"An AccessAck was unexpected by the dcache.\") // TODO must handle Ack coming back on same cycle!\n"
            ); // @[DCache.scala 662:17]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_tl_out_a_valid_T_7 & (_GEN_387 & _tl_d_data_encoded_T_8 & grantIsVoluntary & _dataArb_io_in_3_valid_T_56)
          ) begin
          $fatal; // @[DCache.scala 683:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_387 & _tl_d_data_encoded_T_8 & grantIsVoluntary & _dataArb_io_in_3_valid_T_56 & _tl_out_a_valid_T_7
          ) begin
          $fwrite(32'h80000002,
            "Assertion failed: A ReleaseAck was unexpected by the dcache.\n    at DCache.scala:683 assert(release_ack_wait, \"A ReleaseAck was unexpected by the dcache.\") // TODO should handle Ack coming back on same cycle!\n"
            ); // @[DCache.scala 683:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_284 == (_T_272 & d_first & grantIsCached)) & _dataArb_io_in_3_valid_T_56) begin
          $fatal; // @[DCache.scala 691:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_dataArb_io_in_3_valid_T_56 & ~(_T_284 == (_T_272 & d_first & grantIsCached))) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at DCache.scala:691 assert(tl_out.e.fire() === (tl_out.d.fire() && d_first && grantIsCached))\n"
            ); // @[DCache.scala 691:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(s2_valid_flush_line | s2_flush_valid_pre_tag_ecc | io_cpu_s2_nack) & (s2_want_victimize &
          _dataArb_io_in_3_valid_T_56)) begin
          $fatal; // @[DCache.scala 792:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (s2_want_victimize & _dataArb_io_in_3_valid_T_56 & ~(s2_valid_flush_line | s2_flush_valid_pre_tag_ecc |
          io_cpu_s2_nack)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at DCache.scala:792 assert(s2_valid_flush_line || s2_flush_valid || io.cpu.s2_nack)\n"
            ); // @[DCache.scala 792:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_io_cpu_s2_nack_T_4 & (doUncachedResp & _dataArb_io_in_3_valid_T_56)) begin
          $fatal; // @[DCache.scala 926:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (doUncachedResp & _dataArb_io_in_3_valid_T_56 & ~_io_cpu_s2_nack_T_4) begin
          $fwrite(32'h80000002,"Assertion failed\n    at DCache.scala:926 assert(!s2_valid_hit)\n"); // @[DCache.scala 926:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  s1_valid = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  blockProbeAfterGrantCount = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  lrscCount = _RAND_2[6:0];
  _RAND_3 = {1{`RANDOM}};
  s1_probe = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  s2_probe = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  release_state = _RAND_5[3:0];
  _RAND_6 = {1{`RANDOM}};
  release_ack_wait = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  release_ack_addr = _RAND_7[30:0];
  _RAND_8 = {1{`RANDOM}};
  grantInProgress = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  s2_valid = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  probe_bits_param = _RAND_10[1:0];
  _RAND_11 = {1{`RANDOM}};
  probe_bits_size = _RAND_11[3:0];
  _RAND_12 = {1{`RANDOM}};
  probe_bits_source = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  probe_bits_address = _RAND_13[30:0];
  _RAND_14 = {1{`RANDOM}};
  s2_probe_state_state = _RAND_14[1:0];
  _RAND_15 = {1{`RANDOM}};
  counter_1 = _RAND_15[9:0];
  _RAND_16 = {1{`RANDOM}};
  s2_release_data_valid = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  s1_req_cmd = _RAND_17[4:0];
  _RAND_18 = {1{`RANDOM}};
  s2_req_cmd = _RAND_18[4:0];
  _RAND_19 = {1{`RANDOM}};
  pstore1_held = _RAND_19[0:0];
  _RAND_20 = {1{`RANDOM}};
  pstore1_addr = _RAND_20[31:0];
  _RAND_21 = {1{`RANDOM}};
  s1_req_addr = _RAND_21[31:0];
  _RAND_22 = {1{`RANDOM}};
  pstore1_mask = _RAND_22[3:0];
  _RAND_23 = {1{`RANDOM}};
  s1_req_size = _RAND_23[1:0];
  _RAND_24 = {1{`RANDOM}};
  pstore2_valid = _RAND_24[0:0];
  _RAND_25 = {1{`RANDOM}};
  pstore2_addr = _RAND_25[31:0];
  _RAND_26 = {1{`RANDOM}};
  mask = _RAND_26[3:0];
  _RAND_27 = {1{`RANDOM}};
  s2_not_nacked_in_s1 = _RAND_27[0:0];
  _RAND_28 = {1{`RANDOM}};
  s2_hit_state_state = _RAND_28[1:0];
  _RAND_29 = {1{`RANDOM}};
  s1_req_tag = _RAND_29[5:0];
  _RAND_30 = {1{`RANDOM}};
  s1_req_signed = _RAND_30[0:0];
  _RAND_31 = {1{`RANDOM}};
  s1_req_dprv = _RAND_31[1:0];
  _RAND_32 = {1{`RANDOM}};
  s1_tlb_req_vaddr = _RAND_32[31:0];
  _RAND_33 = {1{`RANDOM}};
  s1_tlb_req_size = _RAND_33[1:0];
  _RAND_34 = {1{`RANDOM}};
  s1_tlb_req_cmd = _RAND_34[4:0];
  _RAND_35 = {1{`RANDOM}};
  s1_tlb_req_prv = _RAND_35[1:0];
  _RAND_36 = {1{`RANDOM}};
  s1_flush_valid = _RAND_36[0:0];
  _RAND_37 = {1{`RANDOM}};
  cached_grant_wait = _RAND_37[0:0];
  _RAND_38 = {1{`RANDOM}};
  resetting = _RAND_38[0:0];
  _RAND_39 = {1{`RANDOM}};
  flushCounter = _RAND_39[6:0];
  _RAND_40 = {1{`RANDOM}};
  refill_way = _RAND_40[1:0];
  _RAND_41 = {1{`RANDOM}};
  uncachedInFlight_0 = _RAND_41[0:0];
  _RAND_42 = {1{`RANDOM}};
  uncachedReqs_0_addr = _RAND_42[31:0];
  _RAND_43 = {1{`RANDOM}};
  uncachedReqs_0_tag = _RAND_43[5:0];
  _RAND_44 = {1{`RANDOM}};
  uncachedReqs_0_size = _RAND_44[1:0];
  _RAND_45 = {1{`RANDOM}};
  uncachedReqs_0_signed = _RAND_45[0:0];
  _RAND_46 = {1{`RANDOM}};
  s1_did_read = _RAND_46[0:0];
  _RAND_47 = {1{`RANDOM}};
  s1_read_mask = _RAND_47[0:0];
  _RAND_48 = {1{`RANDOM}};
  s2_hit_way = _RAND_48[1:0];
  _RAND_49 = {1{`RANDOM}};
  s2_victim_way_r = _RAND_49[0:0];
  _RAND_50 = {1{`RANDOM}};
  s2_probe_way = _RAND_50[1:0];
  _RAND_51 = {1{`RANDOM}};
  s2_req_addr = _RAND_51[31:0];
  _RAND_52 = {1{`RANDOM}};
  s2_req_tag = _RAND_52[5:0];
  _RAND_53 = {1{`RANDOM}};
  s2_req_size = _RAND_53[1:0];
  _RAND_54 = {1{`RANDOM}};
  s2_req_signed = _RAND_54[0:0];
  _RAND_55 = {1{`RANDOM}};
  s2_req_dprv = _RAND_55[1:0];
  _RAND_56 = {1{`RANDOM}};
  s2_tlb_xcpt_pf_ld = _RAND_56[0:0];
  _RAND_57 = {1{`RANDOM}};
  s2_tlb_xcpt_pf_st = _RAND_57[0:0];
  _RAND_58 = {1{`RANDOM}};
  s2_tlb_xcpt_ae_ld = _RAND_58[0:0];
  _RAND_59 = {1{`RANDOM}};
  s2_tlb_xcpt_ae_st = _RAND_59[0:0];
  _RAND_60 = {1{`RANDOM}};
  s2_tlb_xcpt_ma_ld = _RAND_60[0:0];
  _RAND_61 = {1{`RANDOM}};
  s2_tlb_xcpt_ma_st = _RAND_61[0:0];
  _RAND_62 = {1{`RANDOM}};
  s2_pma_cacheable = _RAND_62[0:0];
  _RAND_63 = {1{`RANDOM}};
  s2_uncached_resp_addr = _RAND_63[31:0];
  _RAND_64 = {1{`RANDOM}};
  s2_vaddr_r = _RAND_64[31:0];
  _RAND_65 = {1{`RANDOM}};
  s2_flush_valid_pre_tag_ecc = _RAND_65[0:0];
  _RAND_66 = {1{`RANDOM}};
  s2_meta_corrected_r = _RAND_66[20:0];
  _RAND_67 = {1{`RANDOM}};
  s2_meta_corrected_r_1 = _RAND_67[20:0];
  _RAND_68 = {1{`RANDOM}};
  blockUncachedGrant = _RAND_68[0:0];
  _RAND_69 = {1{`RANDOM}};
  counter = _RAND_69[9:0];
  _RAND_70 = {1{`RANDOM}};
  s2_data = _RAND_70[31:0];
  _RAND_71 = {1{`RANDOM}};
  lrscAddr = _RAND_71[25:0];
  _RAND_72 = {1{`RANDOM}};
  pstore1_cmd = _RAND_72[4:0];
  _RAND_73 = {1{`RANDOM}};
  pstore1_data = _RAND_73[31:0];
  _RAND_74 = {1{`RANDOM}};
  pstore1_way = _RAND_74[1:0];
  _RAND_75 = {1{`RANDOM}};
  pstore1_rmw_r = _RAND_75[0:0];
  _RAND_76 = {1{`RANDOM}};
  pstore_drain_on_miss_REG = _RAND_76[0:0];
  _RAND_77 = {1{`RANDOM}};
  pstore2_way = _RAND_77[1:0];
  _RAND_78 = {1{`RANDOM}};
  pstore2_storegen_data_r = _RAND_78[7:0];
  _RAND_79 = {1{`RANDOM}};
  pstore2_storegen_data_r_1 = _RAND_79[7:0];
  _RAND_80 = {1{`RANDOM}};
  pstore2_storegen_data_r_2 = _RAND_80[7:0];
  _RAND_81 = {1{`RANDOM}};
  pstore2_storegen_data_r_3 = _RAND_81[7:0];
  _RAND_82 = {1{`RANDOM}};
  s1_release_data_valid = _RAND_82[0:0];
  _RAND_83 = {1{`RANDOM}};
  io_cpu_s2_xcpt_REG = _RAND_83[0:0];
  _RAND_84 = {1{`RANDOM}};
  doUncachedResp = _RAND_84[0:0];
  _RAND_85 = {1{`RANDOM}};
  REG = _RAND_85[0:0];
  _RAND_86 = {1{`RANDOM}};
  io_cpu_perf_release_counter = _RAND_86[9:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ICache(
  input         clock,
  input         reset,
  output        auto_slave_in_a_ready,
  input         auto_slave_in_a_valid,
  input  [2:0]  auto_slave_in_a_bits_opcode,
  input  [1:0]  auto_slave_in_a_bits_size,
  input  [7:0]  auto_slave_in_a_bits_source,
  input  [27:0] auto_slave_in_a_bits_address,
  input  [3:0]  auto_slave_in_a_bits_mask,
  input  [31:0] auto_slave_in_a_bits_data,
  input         auto_slave_in_d_ready,
  output        auto_slave_in_d_valid,
  output [2:0]  auto_slave_in_d_bits_opcode,
  output [1:0]  auto_slave_in_d_bits_size,
  output [7:0]  auto_slave_in_d_bits_source,
  output [31:0] auto_slave_in_d_bits_data,
  input         auto_master_out_a_ready,
  output        auto_master_out_a_valid,
  output [30:0] auto_master_out_a_bits_address,
  output        auto_master_out_d_ready,
  input         auto_master_out_d_valid,
  input  [2:0]  auto_master_out_d_bits_opcode,
  input  [3:0]  auto_master_out_d_bits_size,
  input  [31:0] auto_master_out_d_bits_data,
  input         auto_master_out_d_bits_corrupt,
  output        io_req_ready,
  input         io_req_valid,
  input  [31:0] io_req_bits_addr,
  input  [30:0] io_s1_paddr,
  input  [31:0] io_s2_vaddr,
  input         io_s1_kill,
  input         io_s2_kill,
  output        io_resp_valid,
  output [31:0] io_resp_bits_data,
  output        io_resp_bits_ae,
  input         io_invalidate
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [255:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
`endif // RANDOMIZE_REG_INIT
  wire  repl_way_v0_prng_clock; // @[PRNG.scala 91:22]
  wire  repl_way_v0_prng_reset; // @[PRNG.scala 91:22]
  wire  repl_way_v0_prng_io_increment; // @[PRNG.scala 91:22]
  wire  repl_way_v0_prng_io_out_0; // @[PRNG.scala 91:22]
  wire  repl_way_v0_prng_io_out_1; // @[PRNG.scala 91:22]
  wire  repl_way_v0_prng_io_out_2; // @[PRNG.scala 91:22]
  wire  repl_way_v0_prng_io_out_3; // @[PRNG.scala 91:22]
  wire  repl_way_v0_prng_io_out_4; // @[PRNG.scala 91:22]
  wire  repl_way_v0_prng_io_out_5; // @[PRNG.scala 91:22]
  wire  repl_way_v0_prng_io_out_6; // @[PRNG.scala 91:22]
  wire  repl_way_v0_prng_io_out_7; // @[PRNG.scala 91:22]
  wire  repl_way_v0_prng_io_out_8; // @[PRNG.scala 91:22]
  wire  repl_way_v0_prng_io_out_9; // @[PRNG.scala 91:22]
  wire  repl_way_v0_prng_io_out_10; // @[PRNG.scala 91:22]
  wire  repl_way_v0_prng_io_out_11; // @[PRNG.scala 91:22]
  wire  repl_way_v0_prng_io_out_12; // @[PRNG.scala 91:22]
  wire  repl_way_v0_prng_io_out_13; // @[PRNG.scala 91:22]
  wire  repl_way_v0_prng_io_out_14; // @[PRNG.scala 91:22]
  wire  repl_way_v0_prng_io_out_15; // @[PRNG.scala 91:22]
  wire [6:0] tag_array_RW0_addr; // @[DescribedSRAM.scala 19:26]
  wire  tag_array_RW0_en; // @[DescribedSRAM.scala 19:26]
  wire  tag_array_RW0_clk; // @[DescribedSRAM.scala 19:26]
  wire  tag_array_RW0_wmode; // @[DescribedSRAM.scala 19:26]
  wire [18:0] tag_array_RW0_wdata_0; // @[DescribedSRAM.scala 19:26]
  wire [18:0] tag_array_RW0_wdata_1; // @[DescribedSRAM.scala 19:26]
  wire [18:0] tag_array_RW0_rdata_0; // @[DescribedSRAM.scala 19:26]
  wire [18:0] tag_array_RW0_rdata_1; // @[DescribedSRAM.scala 19:26]
  wire  tag_array_RW0_wmask_0; // @[DescribedSRAM.scala 19:26]
  wire  tag_array_RW0_wmask_1; // @[DescribedSRAM.scala 19:26]
  wire [10:0] data_arrays_0_RW0_addr; // @[DescribedSRAM.scala 19:26]
  wire  data_arrays_0_RW0_en; // @[DescribedSRAM.scala 19:26]
  wire  data_arrays_0_RW0_clk; // @[DescribedSRAM.scala 19:26]
  wire  data_arrays_0_RW0_wmode; // @[DescribedSRAM.scala 19:26]
  wire [31:0] data_arrays_0_RW0_wdata_0; // @[DescribedSRAM.scala 19:26]
  wire [31:0] data_arrays_0_RW0_wdata_1; // @[DescribedSRAM.scala 19:26]
  wire [31:0] data_arrays_0_RW0_rdata_0; // @[DescribedSRAM.scala 19:26]
  wire [31:0] data_arrays_0_RW0_rdata_1; // @[DescribedSRAM.scala 19:26]
  wire  data_arrays_0_RW0_wmask_0; // @[DescribedSRAM.scala 19:26]
  wire  data_arrays_0_RW0_wmask_1; // @[DescribedSRAM.scala 19:26]
  reg  scratchpadOn; // @[ICache.scala 149:29]
  reg [6:0] scratchpadMax; // @[ICache.scala 150:42]
  reg  s1_slaveValid; // @[ICache.scala 161:30]
  reg  s2_slaveValid; // @[ICache.scala 162:30]
  reg  s3_slaveValid; // @[ICache.scala 163:30]
  reg  respValid; // @[ICache.scala 350:32]
  wire  tl_in_a_ready = ~(auto_master_out_d_valid | s1_slaveValid | s2_slaveValid | s3_slaveValid | respValid); // @[ICache.scala 351:23]
  wire  s0_slaveValid = tl_in_a_ready & auto_slave_in_a_valid; // @[Decoupled.scala 50:35]
  wire  s0_valid = io_req_ready & io_req_valid; // @[Decoupled.scala 50:35]
  reg  s1_valid; // @[ICache.scala 168:21]
  reg [255:0] vb_array; // @[ICache.scala 230:21]
  wire [6:0] s1_idx = io_s1_paddr[12:6]; // @[ICache.scala 485:21]
  wire [7:0] _s1_vb_T = {1'h0,s1_idx}; // @[Cat.scala 31:58]
  wire [255:0] _s1_vb_T_1 = vb_array >> _s1_vb_T; // @[ICache.scala 258:25]
  wire  s1_vb = _s1_vb_T_1[0] & ~s1_slaveValid; // @[ICache.scala 258:48]
  wire [17:0] tag = tag_array_RW0_rdata_0[17:0]; // @[package.scala 154:13]
  wire [17:0] s1_tag = io_s1_paddr[30:13]; // @[ICache.scala 253:30]
  wire  tagMatch = s1_vb & tag == s1_tag; // @[ICache.scala 261:26]
  reg [13:0] s1s3_slaveAddr; // @[ICache.scala 248:27]
  wire [7:0] _GEN_77 = {{1'd0}, scratchpadMax}; // @[ICache.scala 151:77]
  wire  _scratchpadHit_T_3 = scratchpadOn & s1s3_slaveAddr[13:6] <= _GEN_77; // @[ICache.scala 151:69]
  wire  _scratchpadHit_T_6 = _scratchpadHit_T_3 & ~s1s3_slaveAddr[13]; // @[ICache.scala 256:58]
  wire  _scratchpadHit_T_11 = io_s1_paddr >= 31'h8000000 & io_s1_paddr < 31'h8004000; // @[ICache.scala 155:83]
  wire  _scratchpadHit_T_14 = scratchpadOn & io_s1_paddr[13:6] <= _GEN_77; // @[ICache.scala 151:69]
  wire  _scratchpadHit_T_15 = _scratchpadHit_T_11 & _scratchpadHit_T_14; // @[ICache.scala 156:66]
  wire  _scratchpadHit_T_18 = _scratchpadHit_T_15 & ~io_s1_paddr[13]; // @[ICache.scala 257:39]
  wire  scratchpadHit = s1_slaveValid ? _scratchpadHit_T_6 : _scratchpadHit_T_18; // @[ICache.scala 255:10]
  wire  s1_tag_hit_0 = tagMatch | scratchpadHit; // @[ICache.scala 264:31]
  wire [7:0] _s1_vb_T_4 = {1'h1,s1_idx}; // @[Cat.scala 31:58]
  wire [255:0] _s1_vb_T_5 = vb_array >> _s1_vb_T_4; // @[ICache.scala 258:25]
  wire  s1_vb_1 = _s1_vb_T_5[0] & ~s1_slaveValid; // @[ICache.scala 258:48]
  wire [17:0] tag_1 = tag_array_RW0_rdata_1[17:0]; // @[package.scala 154:13]
  wire  tagMatch_1 = s1_vb_1 & tag_1 == s1_tag; // @[ICache.scala 261:26]
  wire  s1_hit = s1_tag_hit_0 | tagMatch_1 | (s1_slaveValid | _scratchpadHit_T_11); // @[ICache.scala 171:40]
  reg  s2_valid; // @[ICache.scala 173:25]
  reg  s2_hit; // @[ICache.scala 174:23]
  reg  invalidated; // @[ICache.scala 176:24]
  reg  refill_valid; // @[ICache.scala 177:29]
  wire  s2_miss = s2_valid & ~s2_hit & ~io_s2_kill; // @[ICache.scala 181:37]
  reg  s2_request_refill_REG; // @[ICache.scala 183:45]
  wire  s2_request_refill = s2_miss & s2_request_refill_REG; // @[ICache.scala 183:35]
  wire  refill_fire = auto_master_out_a_ready & s2_request_refill; // @[Decoupled.scala 50:35]
  wire  s1_can_request_refill = ~(s2_miss | refill_valid); // @[ICache.scala 182:31]
  wire  _refill_paddr_T = s1_valid & s1_can_request_refill; // @[ICache.scala 184:54]
  reg [30:0] refill_paddr; // @[Reg.scala 16:16]
  wire [17:0] refill_tag = refill_paddr[30:13]; // @[ICache.scala 186:33]
  wire [6:0] refill_idx = refill_paddr[12:6]; // @[ICache.scala 485:21]
  wire  tl_out_d_ready = ~s3_slaveValid; // @[ICache.scala 195:21]
  wire  _refill_one_beat_T = tl_out_d_ready & auto_master_out_d_valid; // @[Decoupled.scala 50:35]
  wire  refill_one_beat_opdata = auto_master_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  refill_one_beat = _refill_one_beat_T & refill_one_beat_opdata; // @[ICache.scala 188:41]
  wire [26:0] _beats1_decode_T_1 = 27'hfff << auto_master_out_d_bits_size; // @[package.scala 234:77]
  wire [11:0] _beats1_decode_T_3 = ~_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
  wire [9:0] beats1_decode = _beats1_decode_T_3[11:2]; // @[Edges.scala 219:59]
  wire [9:0] beats1 = refill_one_beat_opdata ? beats1_decode : 10'h0; // @[Edges.scala 220:14]
  reg [9:0] counter; // @[Edges.scala 228:27]
  wire [9:0] counter1 = counter - 10'h1; // @[Edges.scala 229:28]
  wire  first = counter == 10'h0; // @[Edges.scala 230:25]
  wire  last = counter == 10'h1 | beats1 == 10'h0; // @[Edges.scala 231:37]
  wire  d_done = last & _refill_one_beat_T; // @[Edges.scala 232:22]
  wire [9:0] _count_T = ~counter1; // @[Edges.scala 233:27]
  wire [9:0] refill_cnt = beats1 & _count_T; // @[Edges.scala 233:25]
  wire  refill_done = refill_one_beat & d_done; // @[ICache.scala 194:37]
  wire [7:0] repl_way_v0_lo = {repl_way_v0_prng_io_out_7,repl_way_v0_prng_io_out_6,repl_way_v0_prng_io_out_5,
    repl_way_v0_prng_io_out_4,repl_way_v0_prng_io_out_3,repl_way_v0_prng_io_out_2,repl_way_v0_prng_io_out_1,
    repl_way_v0_prng_io_out_0}; // @[PRNG.scala 95:17]
  wire [15:0] _repl_way_v0_T = {repl_way_v0_prng_io_out_15,repl_way_v0_prng_io_out_14,repl_way_v0_prng_io_out_13,
    repl_way_v0_prng_io_out_12,repl_way_v0_prng_io_out_11,repl_way_v0_prng_io_out_10,repl_way_v0_prng_io_out_9,
    repl_way_v0_prng_io_out_8,repl_way_v0_lo}; // @[PRNG.scala 95:17]
  wire  repl_way_v0 = _repl_way_v0_T[0]; // @[ICache.scala 200:35]
  wire [7:0] _repl_way_T_1 = {repl_way_v0,refill_idx}; // @[Cat.scala 31:58]
  wire  _repl_way_T_3 = scratchpadOn & _repl_way_T_1 <= _GEN_77; // @[ICache.scala 151:69]
  wire  repl_way = repl_way_v0 | _repl_way_T_3; // @[ICache.scala 204:13]
  wire [7:0] _repl_way_T_5 = {repl_way,refill_idx}; // @[Cat.scala 31:58]
  wire  _repl_way_T_7 = scratchpadOn & _repl_way_T_5 <= _GEN_77; // @[ICache.scala 151:69]
  wire  _repl_way_T_10 = ~reset; // @[ICache.scala 206:11]
  wire  _tag_rdata_T_2 = ~refill_done & s0_valid; // @[ICache.scala 217:83]
  reg  accruedRefillError; // @[ICache.scala 218:31]
  wire  refillError = auto_master_out_d_bits_corrupt | refill_cnt > 10'h0 & accruedRefillError; // @[ICache.scala 219:43]
  wire [30:0] _io_errors_bus_bits_T_1 = {refill_paddr[30:6], 6'h0}; // @[ICache.scala 228:57]
  wire  _vb_array_T_1 = ~invalidated; // @[ICache.scala 234:75]
  wire [255:0] _vb_array_T_3 = 256'h1 << _repl_way_T_5; // @[ICache.scala 234:32]
  wire [255:0] _vb_array_T_4 = vb_array | _vb_array_T_3; // @[ICache.scala 234:32]
  wire [255:0] _vb_array_T_5 = ~vb_array; // @[ICache.scala 234:32]
  wire [255:0] _vb_array_T_6 = _vb_array_T_5 | _vb_array_T_3; // @[ICache.scala 234:32]
  wire [255:0] _vb_array_T_7 = ~_vb_array_T_6; // @[ICache.scala 234:32]
  wire  opdata = ~auto_slave_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  wire  _T_23 = scratchpadOn & auto_slave_in_a_bits_address[13:6] <= _GEN_77; // @[ICache.scala 151:69]
  wire  _GEN_58 = ~_T_23 | io_invalidate; // @[ICache.scala 360:65 362:26]
  wire  _GEN_60 = opdata ? _GEN_58 : io_invalidate; // @[ICache.scala 358:41]
  wire  invalidate = s0_slaveValid ? _GEN_60 : io_invalidate; // @[ICache.scala 354:30]
  wire  _GEN_22 = invalidate | invalidated; // @[ICache.scala 237:21 239:17 176:24]
  reg [31:0] s1s3_slaveData; // @[ICache.scala 249:27]
  wire  tl_error = tag_array_RW0_rdata_0[18]; // @[package.scala 154:13]
  wire  s1_tl_error_0 = tagMatch & tl_error; // @[ICache.scala 263:32]
  wire  tl_error_1 = tag_array_RW0_rdata_1[18]; // @[package.scala 154:13]
  wire  s1_tl_error_1 = tagMatch_1 & tl_error_1; // @[ICache.scala 263:32]
  wire  _T_3 = s1_valid | s1_slaveValid; // @[ICache.scala 266:21]
  wire [1:0] _T_9 = s1_tag_hit_0 + tagMatch_1; // @[Bitwise.scala 48:55]
  wire  s0_ren = s0_valid | s0_slaveValid; // @[ICache.scala 283:52]
  wire  wen = refill_one_beat & _vb_array_T_1 | s3_slaveValid; // @[ICache.scala 284:49]
  wire [10:0] _mem_idx_T = {refill_idx, 4'h0}; // @[ICache.scala 285:52]
  wire [10:0] _GEN_84 = {{1'd0}, refill_cnt}; // @[ICache.scala 285:79]
  wire [10:0] _mem_idx_T_1 = _mem_idx_T | _GEN_84; // @[ICache.scala 285:79]
  wire [10:0] _mem_idx_T_5 = s0_slaveValid ? auto_slave_in_a_bits_address[12:2] : io_req_bits_addr[12:2]; // @[ICache.scala 287:22]
  wire [10:0] _mem_idx_T_6 = s3_slaveValid ? s1s3_slaveAddr[12:2] : _mem_idx_T_5; // @[ICache.scala 286:22]
  wire  way = s3_slaveValid ? s1s3_slaveAddr[13] : repl_way; // @[ICache.scala 291:20]
  wire  _dout_T_1 = ~wen & s0_ren; // @[ICache.scala 294:46]
  wire [31:0] s1_dout_0 = data_arrays_0_RW0_rdata_0; // @[ICache.scala 295:71 296:15]
  wire [31:0] s1_dout_1 = data_arrays_0_RW0_rdata_1; // @[ICache.scala 295:71 296:15]
  reg [2:0] s1_a_opcode; // @[Reg.scala 16:16]
  wire  s1s2_full_word_write_opdata = ~s1_a_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] s1_a_mask; // @[Reg.scala 16:16]
  wire  s1s2_full_word_write = s1s2_full_word_write_opdata & &s1_a_mask; // @[ICache.scala 353:59]
  wire  s1_dont_read = s1_slaveValid & s1s2_full_word_write; // @[ICache.scala 302:36]
  reg  s2_tag_hit_0; // @[Reg.scala 16:16]
  reg  s2_tag_hit_1; // @[Reg.scala 16:16]
  reg [31:0] s2_dout_0; // @[Reg.scala 16:16]
  reg [31:0] s2_dout_1; // @[Reg.scala 16:16]
  wire [31:0] _s2_way_mux_T = s2_tag_hit_0 ? s2_dout_0 : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _s2_way_mux_T_1 = s2_tag_hit_1 ? s2_dout_1 : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] s2_way_mux = _s2_way_mux_T | _s2_way_mux_T_1; // @[Mux.scala 27:73]
  wire [1:0] _s2_tl_error_T = {s1_tl_error_1,s1_tl_error_0}; // @[ICache.scala 312:43]
  wire  _s2_tl_error_T_1 = |_s2_tl_error_T; // @[ICache.scala 312:50]
  reg  s2_tl_error; // @[Reg.scala 16:16]
  reg [1:0] s1_a_size; // @[Reg.scala 16:16]
  reg [7:0] s1_a_source; // @[Reg.scala 16:16]
  wire  enable = auto_slave_in_a_bits_address[13] < 1'h1; // @[ICache.scala 158:43]
  wire [7:0] _GEN_57 = ~_T_23 ? auto_slave_in_a_bits_address[13:6] : {{1'd0}, scratchpadMax}; // @[ICache.scala 360:65 361:33 150:42]
  wire [7:0] _GEN_59 = opdata ? _GEN_57 : {{1'd0}, scratchpadMax}; // @[ICache.scala 358:41 150:42]
  wire [27:0] _GEN_62 = s0_slaveValid ? auto_slave_in_a_bits_address : {{14'd0}, s1s3_slaveAddr}; // @[ICache.scala 354:30 356:26 248:27]
  wire [7:0] _GEN_64 = s0_slaveValid ? _GEN_59 : {{1'd0}, scratchpadMax}; // @[ICache.scala 354:30 150:42]
  reg [31:0] REG; // @[ICache.scala 379:44]
  reg [31:0] REG_1; // @[ICache.scala 379:36]
  wire  _s1s3_slaveData_T_2 = ~(s1s2_full_word_write_opdata & s1_a_mask[0]); // @[ICache.scala 395:32]
  wire [31:0] _s1s3_slaveData_T_3 = _s1s3_slaveData_T_2 ? s2_way_mux : s1s3_slaveData; // @[ICache.scala 396:62]
  wire  _s1s3_slaveData_T_7 = ~(s1s2_full_word_write_opdata & s1_a_mask[1]); // @[ICache.scala 395:32]
  wire [31:0] _s1s3_slaveData_T_8 = _s1s3_slaveData_T_7 ? s2_way_mux : s1s3_slaveData; // @[ICache.scala 396:62]
  wire  _s1s3_slaveData_T_12 = ~(s1s2_full_word_write_opdata & s1_a_mask[2]); // @[ICache.scala 395:32]
  wire [31:0] _s1s3_slaveData_T_13 = _s1s3_slaveData_T_12 ? s2_way_mux : s1s3_slaveData; // @[ICache.scala 396:62]
  wire  _s1s3_slaveData_T_17 = ~(s1s2_full_word_write_opdata & s1_a_mask[3]); // @[ICache.scala 395:32]
  wire [31:0] _s1s3_slaveData_T_18 = _s1s3_slaveData_T_17 ? s2_way_mux : s1s3_slaveData; // @[ICache.scala 396:62]
  wire [31:0] _s1s3_slaveData_T_20 = {_s1s3_slaveData_T_18[31:24],_s1s3_slaveData_T_13[23:16],_s1s3_slaveData_T_8[15:8],
    _s1s3_slaveData_T_3[7:0]}; // @[Cat.scala 31:58]
  wire  _T_55 = _io_errors_bus_bits_T_1 >= 31'h8000000 & _io_errors_bus_bits_T_1 < 31'h8004000; // @[ICache.scala 155:83]
  wire  _GEN_75 = refill_fire | refill_valid; // @[ICache.scala 476:22 177:29 476:37]
  MaxPeriodFibonacciLFSR repl_way_v0_prng ( // @[PRNG.scala 91:22]
    .clock(repl_way_v0_prng_clock),
    .reset(repl_way_v0_prng_reset),
    .io_increment(repl_way_v0_prng_io_increment),
    .io_out_0(repl_way_v0_prng_io_out_0),
    .io_out_1(repl_way_v0_prng_io_out_1),
    .io_out_2(repl_way_v0_prng_io_out_2),
    .io_out_3(repl_way_v0_prng_io_out_3),
    .io_out_4(repl_way_v0_prng_io_out_4),
    .io_out_5(repl_way_v0_prng_io_out_5),
    .io_out_6(repl_way_v0_prng_io_out_6),
    .io_out_7(repl_way_v0_prng_io_out_7),
    .io_out_8(repl_way_v0_prng_io_out_8),
    .io_out_9(repl_way_v0_prng_io_out_9),
    .io_out_10(repl_way_v0_prng_io_out_10),
    .io_out_11(repl_way_v0_prng_io_out_11),
    .io_out_12(repl_way_v0_prng_io_out_12),
    .io_out_13(repl_way_v0_prng_io_out_13),
    .io_out_14(repl_way_v0_prng_io_out_14),
    .io_out_15(repl_way_v0_prng_io_out_15)
  );
  tag_array_0 tag_array ( // @[DescribedSRAM.scala 19:26]
    .RW0_addr(tag_array_RW0_addr),
    .RW0_en(tag_array_RW0_en),
    .RW0_clk(tag_array_RW0_clk),
    .RW0_wmode(tag_array_RW0_wmode),
    .RW0_wdata_0(tag_array_RW0_wdata_0),
    .RW0_wdata_1(tag_array_RW0_wdata_1),
    .RW0_rdata_0(tag_array_RW0_rdata_0),
    .RW0_rdata_1(tag_array_RW0_rdata_1),
    .RW0_wmask_0(tag_array_RW0_wmask_0),
    .RW0_wmask_1(tag_array_RW0_wmask_1)
  );
  data_arrays_0_0 data_arrays_0 ( // @[DescribedSRAM.scala 19:26]
    .RW0_addr(data_arrays_0_RW0_addr),
    .RW0_en(data_arrays_0_RW0_en),
    .RW0_clk(data_arrays_0_RW0_clk),
    .RW0_wmode(data_arrays_0_RW0_wmode),
    .RW0_wdata_0(data_arrays_0_RW0_wdata_0),
    .RW0_wdata_1(data_arrays_0_RW0_wdata_1),
    .RW0_rdata_0(data_arrays_0_RW0_rdata_0),
    .RW0_rdata_1(data_arrays_0_RW0_rdata_1),
    .RW0_wmask_0(data_arrays_0_RW0_wmask_0),
    .RW0_wmask_1(data_arrays_0_RW0_wmask_1)
  );
  assign auto_slave_in_a_ready = ~(auto_master_out_d_valid | s1_slaveValid | s2_slaveValid | s3_slaveValid | respValid); // @[ICache.scala 351:23]
  assign auto_slave_in_d_valid = respValid; // @[Nodes.scala 1210:84 ICache.scala 399:20]
  assign auto_slave_in_d_bits_opcode = s1s2_full_word_write_opdata ? 3'h0 : 3'h1; // @[ICache.scala 400:25]
  assign auto_slave_in_d_bits_size = s1_a_size; // @[ICache.scala 400:25]
  assign auto_slave_in_d_bits_source = s1_a_source; // @[ICache.scala 400:25]
  assign auto_slave_in_d_bits_data = s1s3_slaveData; // @[Nodes.scala 1210:84 ICache.scala 403:24]
  assign auto_master_out_a_valid = s2_miss & s2_request_refill_REG; // @[ICache.scala 183:35]
  assign auto_master_out_a_bits_address = {refill_paddr[30:6], 6'h0}; // @[ICache.scala 420:64]
  assign auto_master_out_d_ready = ~s3_slaveValid; // @[ICache.scala 195:21]
  assign io_req_ready = ~(refill_one_beat | s0_slaveValid | s3_slaveValid); // @[ICache.scala 190:19]
  assign io_resp_valid = s2_valid & s2_hit; // @[ICache.scala 338:33]
  assign io_resp_bits_data = _s2_way_mux_T | _s2_way_mux_T_1; // @[Mux.scala 27:73]
  assign io_resp_bits_ae = s2_tl_error; // @[ICache.scala 336:23]
  assign repl_way_v0_prng_clock = clock;
  assign repl_way_v0_prng_reset = reset;
  assign repl_way_v0_prng_io_increment = auto_master_out_a_ready & s2_request_refill; // @[Decoupled.scala 50:35]
  assign tag_array_RW0_clk = clock; // @[ICache.scala 220:22]
  assign tag_array_RW0_wdata_0 = {refillError,refill_tag}; // @[Cat.scala 31:58]
  assign tag_array_RW0_wdata_1 = {refillError,refill_tag}; // @[Cat.scala 31:58]
  assign tag_array_RW0_wmask_0 = ~repl_way; // @[ICache.scala 223:88]
  assign tag_array_RW0_wmask_1 = repl_way_v0 | _repl_way_T_3; // @[ICache.scala 204:13]
  assign data_arrays_0_RW0_clk = clock; // @[ICache.scala 289:16]
  assign data_arrays_0_RW0_wdata_0 = s3_slaveValid ? s1s3_slaveData : auto_master_out_d_bits_data; // @[ICache.scala 290:21]
  assign data_arrays_0_RW0_wdata_1 = s3_slaveValid ? s1s3_slaveData : auto_master_out_d_bits_data; // @[ICache.scala 290:21]
  assign data_arrays_0_RW0_wmask_0 = ~way; // @[ICache.scala 292:93]
  assign data_arrays_0_RW0_wmask_1 = s3_slaveValid ? s1s3_slaveAddr[13] : repl_way; // @[ICache.scala 291:20]
  assign tag_array_RW0_en = _tag_rdata_T_2 | refill_done;
  assign tag_array_RW0_wmode = refill_one_beat & d_done; // @[ICache.scala 194:37]
  assign tag_array_RW0_addr = refill_done ? refill_idx : io_req_bits_addr[12:6];
  assign data_arrays_0_RW0_en = _dout_T_1 | wen;
  assign data_arrays_0_RW0_wmode = refill_one_beat & _vb_array_T_1 | s3_slaveValid; // @[ICache.scala 284:49]
  assign data_arrays_0_RW0_addr = refill_one_beat ? _mem_idx_T_1 : _mem_idx_T_6; // @[ICache.scala 285:22]
  always @(posedge clock) begin
    if (reset) begin // @[ICache.scala 149:29]
      scratchpadOn <= 1'h0; // @[ICache.scala 149:29]
    end else if (s0_slaveValid) begin // @[ICache.scala 354:30]
      if (opdata) begin // @[ICache.scala 358:41]
        scratchpadOn <= enable; // @[ICache.scala 364:26]
      end
    end
    scratchpadMax <= _GEN_64[6:0];
    if (reset) begin // @[ICache.scala 161:30]
      s1_slaveValid <= 1'h0; // @[ICache.scala 161:30]
    end else begin
      s1_slaveValid <= s0_slaveValid; // @[ICache.scala 161:30]
    end
    if (reset) begin // @[ICache.scala 162:30]
      s2_slaveValid <= 1'h0; // @[ICache.scala 162:30]
    end else begin
      s2_slaveValid <= s1_slaveValid; // @[ICache.scala 162:30]
    end
    s3_slaveValid <= s2_slaveValid & s1s2_full_word_write_opdata; // @[ICache.scala 393:30]
    if (reset) begin // @[ICache.scala 350:32]
      respValid <= 1'h0; // @[ICache.scala 350:32]
    end else begin
      respValid <= s2_slaveValid | respValid & ~auto_slave_in_d_ready; // @[ICache.scala 391:19]
    end
    if (reset) begin // @[ICache.scala 168:21]
      s1_valid <= 1'h0; // @[ICache.scala 168:21]
    end else begin
      s1_valid <= s0_valid; // @[ICache.scala 191:12]
    end
    if (reset) begin // @[ICache.scala 230:21]
      vb_array <= 256'h0; // @[ICache.scala 230:21]
    end else if (invalidate) begin // @[ICache.scala 237:21]
      vb_array <= 256'h0; // @[ICache.scala 238:14]
    end else if (refill_one_beat) begin // @[ICache.scala 231:26]
      if (refill_done & ~invalidated) begin // @[ICache.scala 234:32]
        vb_array <= _vb_array_T_4;
      end else begin
        vb_array <= _vb_array_T_7;
      end
    end
    s1s3_slaveAddr <= _GEN_62[13:0];
    if (reset) begin // @[ICache.scala 173:25]
      s2_valid <= 1'h0; // @[ICache.scala 173:25]
    end else begin
      s2_valid <= s1_valid & ~io_s1_kill; // @[ICache.scala 173:25]
    end
    s2_hit <= s1_hit; // @[ICache.scala 174:23]
    if (~refill_valid) begin // @[ICache.scala 475:24]
      invalidated <= 1'h0; // @[ICache.scala 475:38]
    end else begin
      invalidated <= _GEN_22;
    end
    if (reset) begin // @[ICache.scala 177:29]
      refill_valid <= 1'h0; // @[ICache.scala 177:29]
    end else if (refill_done) begin // @[ICache.scala 477:22]
      refill_valid <= 1'h0; // @[ICache.scala 477:37]
    end else begin
      refill_valid <= _GEN_75;
    end
    s2_request_refill_REG <= ~(s2_miss | refill_valid); // @[ICache.scala 182:31]
    if (_refill_paddr_T) begin // @[Reg.scala 17:18]
      refill_paddr <= io_s1_paddr; // @[Reg.scala 17:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      counter <= 10'h0; // @[Edges.scala 228:27]
    end else if (_refill_one_beat_T) begin // @[Edges.scala 234:17]
      if (first) begin // @[Edges.scala 235:21]
        if (refill_one_beat_opdata) begin // @[Edges.scala 220:14]
          counter <= beats1_decode;
        end else begin
          counter <= 10'h0;
        end
      end else begin
        counter <= counter1;
      end
    end
    if (refill_one_beat) begin // @[ICache.scala 231:26]
      accruedRefillError <= refillError; // @[ICache.scala 232:24]
    end
    if (s2_slaveValid) begin // @[ICache.scala 393:30]
      s1s3_slaveData <= _s1s3_slaveData_T_20; // @[ICache.scala 396:26]
    end else if (s0_slaveValid) begin // @[ICache.scala 354:30]
      s1s3_slaveData <= auto_slave_in_a_bits_data; // @[ICache.scala 357:26]
    end
    if (s0_slaveValid) begin // @[Reg.scala 17:18]
      s1_a_opcode <= auto_slave_in_a_bits_opcode; // @[Reg.scala 17:22]
    end
    if (s0_slaveValid) begin // @[Reg.scala 17:18]
      s1_a_mask <= auto_slave_in_a_bits_mask; // @[Reg.scala 17:22]
    end
    if (_T_3) begin // @[Reg.scala 17:18]
      if (s1_dont_read) begin // @[ICache.scala 305:33]
        s2_tag_hit_0 <= 1'h0;
      end else begin
        s2_tag_hit_0 <= s1_tag_hit_0;
      end
    end
    if (_T_3) begin // @[Reg.scala 17:18]
      if (s1_dont_read) begin // @[ICache.scala 305:33]
        s2_tag_hit_1 <= 1'h0;
      end else begin
        s2_tag_hit_1 <= tagMatch_1;
      end
    end
    if (_T_3) begin // @[Reg.scala 17:18]
      s2_dout_0 <= s1_dout_0; // @[Reg.scala 17:22]
    end
    if (_T_3) begin // @[Reg.scala 17:18]
      s2_dout_1 <= s1_dout_1; // @[Reg.scala 17:22]
    end
    if (_T_3) begin // @[Reg.scala 17:18]
      s2_tl_error <= _s2_tl_error_T_1; // @[Reg.scala 17:22]
    end
    if (s0_slaveValid) begin // @[Reg.scala 17:18]
      s1_a_size <= auto_slave_in_a_bits_size; // @[Reg.scala 17:22]
    end
    if (s0_slaveValid) begin // @[Reg.scala 17:18]
      s1_a_source <= auto_slave_in_a_bits_source; // @[Reg.scala 17:22]
    end
    REG <= io_req_bits_addr; // @[ICache.scala 379:44]
    REG_1 <= REG; // @[ICache.scala 379:36]
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~_repl_way_T_7) & ~reset) begin
          $fatal; // @[ICache.scala 206:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~_repl_way_T_7)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at ICache.scala:206 assert(!lineInScratchpad(Cat(v, refill_idx)))\n"); // @[ICache.scala 206:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(s1_valid | s1_slaveValid) | _T_9 <= 2'h1) & _repl_way_T_10) begin
          $fatal; // @[ICache.scala 266:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_repl_way_T_10 & ~(~(s1_valid | s1_slaveValid) | _T_9 <= 2'h1)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at ICache.scala:266 assert(!(s1_valid || s1_slaveValid) || PopCount(s1_tag_hit zip s1_tag_disparity map { case (h, d) => h && !d }) <= 1)\n"
            ); // @[ICache.scala 266:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~s2_valid | REG_1 == io_s2_vaddr) & _repl_way_T_10) begin
          $fatal; // @[ICache.scala 379:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_repl_way_T_10 & ~(~s2_valid | REG_1 == io_s2_vaddr)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at ICache.scala:379 assert(!s2_valid || RegNext(RegNext(s0_vaddr)) === io.s2_vaddr)\n"
            ); // @[ICache.scala 379:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(s2_request_refill & _T_55)) & _repl_way_T_10) begin
          $fatal; // @[ICache.scala 473:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_repl_way_T_10 & ~(~(s2_request_refill & _T_55))) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at ICache.scala:473 assert(!(tl_out.a.valid && addrMaybeInScratchpad(tl_out.a.bits.address)))\n"
            ); // @[ICache.scala 473:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  scratchpadOn = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  scratchpadMax = _RAND_1[6:0];
  _RAND_2 = {1{`RANDOM}};
  s1_slaveValid = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  s2_slaveValid = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  s3_slaveValid = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  respValid = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  s1_valid = _RAND_6[0:0];
  _RAND_7 = {8{`RANDOM}};
  vb_array = _RAND_7[255:0];
  _RAND_8 = {1{`RANDOM}};
  s1s3_slaveAddr = _RAND_8[13:0];
  _RAND_9 = {1{`RANDOM}};
  s2_valid = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  s2_hit = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  invalidated = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  refill_valid = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  s2_request_refill_REG = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  refill_paddr = _RAND_14[30:0];
  _RAND_15 = {1{`RANDOM}};
  counter = _RAND_15[9:0];
  _RAND_16 = {1{`RANDOM}};
  accruedRefillError = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  s1s3_slaveData = _RAND_17[31:0];
  _RAND_18 = {1{`RANDOM}};
  s1_a_opcode = _RAND_18[2:0];
  _RAND_19 = {1{`RANDOM}};
  s1_a_mask = _RAND_19[3:0];
  _RAND_20 = {1{`RANDOM}};
  s2_tag_hit_0 = _RAND_20[0:0];
  _RAND_21 = {1{`RANDOM}};
  s2_tag_hit_1 = _RAND_21[0:0];
  _RAND_22 = {1{`RANDOM}};
  s2_dout_0 = _RAND_22[31:0];
  _RAND_23 = {1{`RANDOM}};
  s2_dout_1 = _RAND_23[31:0];
  _RAND_24 = {1{`RANDOM}};
  s2_tl_error = _RAND_24[0:0];
  _RAND_25 = {1{`RANDOM}};
  s1_a_size = _RAND_25[1:0];
  _RAND_26 = {1{`RANDOM}};
  s1_a_source = _RAND_26[7:0];
  _RAND_27 = {1{`RANDOM}};
  REG = _RAND_27[31:0];
  _RAND_28 = {1{`RANDOM}};
  REG_1 = _RAND_28[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ShiftQueue(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input         io_enq_bits_btb_taken,
  input         io_enq_bits_btb_bridx,
  input  [4:0]  io_enq_bits_btb_entry,
  input  [7:0]  io_enq_bits_btb_bht_history,
  input  [31:0] io_enq_bits_pc,
  input  [31:0] io_enq_bits_data,
  input  [1:0]  io_enq_bits_mask,
  input         io_enq_bits_xcpt_ae_inst,
  input         io_enq_bits_replay,
  input         io_deq_ready,
  output        io_deq_valid,
  output        io_deq_bits_btb_taken,
  output        io_deq_bits_btb_bridx,
  output [4:0]  io_deq_bits_btb_entry,
  output [7:0]  io_deq_bits_btb_bht_history,
  output [31:0] io_deq_bits_pc,
  output [31:0] io_deq_bits_data,
  output        io_deq_bits_xcpt_ae_inst,
  output        io_deq_bits_replay,
  output [4:0]  io_mask
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [31:0] _RAND_33;
  reg [31:0] _RAND_34;
  reg [31:0] _RAND_35;
  reg [31:0] _RAND_36;
  reg [31:0] _RAND_37;
  reg [31:0] _RAND_38;
  reg [31:0] _RAND_39;
  reg [31:0] _RAND_40;
  reg [31:0] _RAND_41;
  reg [31:0] _RAND_42;
  reg [31:0] _RAND_43;
  reg [31:0] _RAND_44;
`endif // RANDOMIZE_REG_INIT
  reg  valid_0; // @[ShiftQueue.scala 21:30]
  reg  valid_1; // @[ShiftQueue.scala 21:30]
  reg  valid_2; // @[ShiftQueue.scala 21:30]
  reg  valid_3; // @[ShiftQueue.scala 21:30]
  reg  valid_4; // @[ShiftQueue.scala 21:30]
  reg  elts_0_btb_taken; // @[ShiftQueue.scala 22:25]
  reg  elts_0_btb_bridx; // @[ShiftQueue.scala 22:25]
  reg [4:0] elts_0_btb_entry; // @[ShiftQueue.scala 22:25]
  reg [7:0] elts_0_btb_bht_history; // @[ShiftQueue.scala 22:25]
  reg [31:0] elts_0_pc; // @[ShiftQueue.scala 22:25]
  reg [31:0] elts_0_data; // @[ShiftQueue.scala 22:25]
  reg  elts_0_xcpt_ae_inst; // @[ShiftQueue.scala 22:25]
  reg  elts_0_replay; // @[ShiftQueue.scala 22:25]
  reg  elts_1_btb_taken; // @[ShiftQueue.scala 22:25]
  reg  elts_1_btb_bridx; // @[ShiftQueue.scala 22:25]
  reg [4:0] elts_1_btb_entry; // @[ShiftQueue.scala 22:25]
  reg [7:0] elts_1_btb_bht_history; // @[ShiftQueue.scala 22:25]
  reg [31:0] elts_1_pc; // @[ShiftQueue.scala 22:25]
  reg [31:0] elts_1_data; // @[ShiftQueue.scala 22:25]
  reg  elts_1_xcpt_ae_inst; // @[ShiftQueue.scala 22:25]
  reg  elts_1_replay; // @[ShiftQueue.scala 22:25]
  reg  elts_2_btb_taken; // @[ShiftQueue.scala 22:25]
  reg  elts_2_btb_bridx; // @[ShiftQueue.scala 22:25]
  reg [4:0] elts_2_btb_entry; // @[ShiftQueue.scala 22:25]
  reg [7:0] elts_2_btb_bht_history; // @[ShiftQueue.scala 22:25]
  reg [31:0] elts_2_pc; // @[ShiftQueue.scala 22:25]
  reg [31:0] elts_2_data; // @[ShiftQueue.scala 22:25]
  reg  elts_2_xcpt_ae_inst; // @[ShiftQueue.scala 22:25]
  reg  elts_2_replay; // @[ShiftQueue.scala 22:25]
  reg  elts_3_btb_taken; // @[ShiftQueue.scala 22:25]
  reg  elts_3_btb_bridx; // @[ShiftQueue.scala 22:25]
  reg [4:0] elts_3_btb_entry; // @[ShiftQueue.scala 22:25]
  reg [7:0] elts_3_btb_bht_history; // @[ShiftQueue.scala 22:25]
  reg [31:0] elts_3_pc; // @[ShiftQueue.scala 22:25]
  reg [31:0] elts_3_data; // @[ShiftQueue.scala 22:25]
  reg  elts_3_xcpt_ae_inst; // @[ShiftQueue.scala 22:25]
  reg  elts_3_replay; // @[ShiftQueue.scala 22:25]
  reg  elts_4_btb_taken; // @[ShiftQueue.scala 22:25]
  reg  elts_4_btb_bridx; // @[ShiftQueue.scala 22:25]
  reg [4:0] elts_4_btb_entry; // @[ShiftQueue.scala 22:25]
  reg [7:0] elts_4_btb_bht_history; // @[ShiftQueue.scala 22:25]
  reg [31:0] elts_4_pc; // @[ShiftQueue.scala 22:25]
  reg [31:0] elts_4_data; // @[ShiftQueue.scala 22:25]
  reg  elts_4_xcpt_ae_inst; // @[ShiftQueue.scala 22:25]
  reg  elts_4_replay; // @[ShiftQueue.scala 22:25]
  wire  _wen_T = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
  wire  _wen_T_2 = _wen_T & valid_0; // @[ShiftQueue.scala 30:45]
  wire  _wen_T_3 = valid_1 | _wen_T & valid_0; // @[ShiftQueue.scala 30:28]
  wire  _wen_T_6 = ~valid_0; // @[ShiftQueue.scala 31:48]
  wire  _wen_T_7 = _wen_T & ~valid_0; // @[ShiftQueue.scala 31:45]
  wire  wen = io_deq_ready ? _wen_T_3 : _wen_T_7; // @[ShiftQueue.scala 29:10]
  wire  _valid_0_T_6 = _wen_T | valid_0; // @[ShiftQueue.scala 37:45]
  wire  _wen_T_10 = _wen_T & valid_1; // @[ShiftQueue.scala 30:45]
  wire  _wen_T_11 = valid_2 | _wen_T & valid_1; // @[ShiftQueue.scala 30:28]
  wire  _wen_T_15 = _wen_T_2 & ~valid_1; // @[ShiftQueue.scala 31:45]
  wire  wen_1 = io_deq_ready ? _wen_T_11 : _wen_T_15; // @[ShiftQueue.scala 29:10]
  wire  _valid_1_T_6 = _wen_T_2 | valid_1; // @[ShiftQueue.scala 37:45]
  wire  _wen_T_18 = _wen_T & valid_2; // @[ShiftQueue.scala 30:45]
  wire  _wen_T_19 = valid_3 | _wen_T & valid_2; // @[ShiftQueue.scala 30:28]
  wire  _wen_T_23 = _wen_T_10 & ~valid_2; // @[ShiftQueue.scala 31:45]
  wire  wen_2 = io_deq_ready ? _wen_T_19 : _wen_T_23; // @[ShiftQueue.scala 29:10]
  wire  _valid_2_T_6 = _wen_T_10 | valid_2; // @[ShiftQueue.scala 37:45]
  wire  _wen_T_26 = _wen_T & valid_3; // @[ShiftQueue.scala 30:45]
  wire  _wen_T_27 = valid_4 | _wen_T & valid_3; // @[ShiftQueue.scala 30:28]
  wire  _wen_T_31 = _wen_T_18 & ~valid_3; // @[ShiftQueue.scala 31:45]
  wire  wen_3 = io_deq_ready ? _wen_T_27 : _wen_T_31; // @[ShiftQueue.scala 29:10]
  wire  _valid_3_T_6 = _wen_T_18 | valid_3; // @[ShiftQueue.scala 37:45]
  wire  _wen_T_34 = _wen_T & valid_4; // @[ShiftQueue.scala 30:45]
  wire  _wen_T_39 = _wen_T_26 & ~valid_4; // @[ShiftQueue.scala 31:45]
  wire  wen_4 = io_deq_ready ? _wen_T_34 : _wen_T_39; // @[ShiftQueue.scala 29:10]
  wire  _valid_4_T_6 = _wen_T_26 | valid_4; // @[ShiftQueue.scala 37:45]
  wire [1:0] io_mask_lo = {valid_1,valid_0}; // @[ShiftQueue.scala 53:20]
  wire [2:0] io_mask_hi = {valid_4,valid_3,valid_2}; // @[ShiftQueue.scala 53:20]
  assign io_enq_ready = ~valid_4; // @[ShiftQueue.scala 40:19]
  assign io_deq_valid = io_enq_valid | valid_0; // @[ShiftQueue.scala 41:16 45:{25,40}]
  assign io_deq_bits_btb_taken = _wen_T_6 ? io_enq_bits_btb_taken : elts_0_btb_taken; // @[ShiftQueue.scala 42:15 46:{22,36}]
  assign io_deq_bits_btb_bridx = _wen_T_6 ? io_enq_bits_btb_bridx : elts_0_btb_bridx; // @[ShiftQueue.scala 42:15 46:{22,36}]
  assign io_deq_bits_btb_entry = _wen_T_6 ? io_enq_bits_btb_entry : elts_0_btb_entry; // @[ShiftQueue.scala 42:15 46:{22,36}]
  assign io_deq_bits_btb_bht_history = _wen_T_6 ? io_enq_bits_btb_bht_history : elts_0_btb_bht_history; // @[ShiftQueue.scala 42:15 46:{22,36}]
  assign io_deq_bits_pc = _wen_T_6 ? io_enq_bits_pc : elts_0_pc; // @[ShiftQueue.scala 42:15 46:{22,36}]
  assign io_deq_bits_data = _wen_T_6 ? io_enq_bits_data : elts_0_data; // @[ShiftQueue.scala 42:15 46:{22,36}]
  assign io_deq_bits_xcpt_ae_inst = _wen_T_6 ? io_enq_bits_xcpt_ae_inst : elts_0_xcpt_ae_inst; // @[ShiftQueue.scala 42:15 46:{22,36}]
  assign io_deq_bits_replay = _wen_T_6 ? io_enq_bits_replay : elts_0_replay; // @[ShiftQueue.scala 42:15 46:{22,36}]
  assign io_mask = {io_mask_hi,io_mask_lo}; // @[ShiftQueue.scala 53:20]
  always @(posedge clock) begin
    if (reset) begin // @[ShiftQueue.scala 21:30]
      valid_0 <= 1'h0; // @[ShiftQueue.scala 21:30]
    end else if (io_deq_ready) begin // @[ShiftQueue.scala 35:10]
      valid_0 <= _wen_T_3;
    end else begin
      valid_0 <= _valid_0_T_6;
    end
    if (reset) begin // @[ShiftQueue.scala 21:30]
      valid_1 <= 1'h0; // @[ShiftQueue.scala 21:30]
    end else if (io_deq_ready) begin // @[ShiftQueue.scala 35:10]
      valid_1 <= _wen_T_11;
    end else begin
      valid_1 <= _valid_1_T_6;
    end
    if (reset) begin // @[ShiftQueue.scala 21:30]
      valid_2 <= 1'h0; // @[ShiftQueue.scala 21:30]
    end else if (io_deq_ready) begin // @[ShiftQueue.scala 35:10]
      valid_2 <= _wen_T_19;
    end else begin
      valid_2 <= _valid_2_T_6;
    end
    if (reset) begin // @[ShiftQueue.scala 21:30]
      valid_3 <= 1'h0; // @[ShiftQueue.scala 21:30]
    end else if (io_deq_ready) begin // @[ShiftQueue.scala 35:10]
      valid_3 <= _wen_T_27;
    end else begin
      valid_3 <= _valid_3_T_6;
    end
    if (reset) begin // @[ShiftQueue.scala 21:30]
      valid_4 <= 1'h0; // @[ShiftQueue.scala 21:30]
    end else if (io_deq_ready) begin // @[ShiftQueue.scala 35:10]
      valid_4 <= _wen_T_34;
    end else begin
      valid_4 <= _valid_4_T_6;
    end
    if (wen) begin // @[ShiftQueue.scala 32:16]
      if (valid_1) begin // @[ShiftQueue.scala 27:57]
        elts_0_btb_taken <= elts_1_btb_taken;
      end else begin
        elts_0_btb_taken <= io_enq_bits_btb_taken;
      end
    end
    if (wen) begin // @[ShiftQueue.scala 32:16]
      if (valid_1) begin // @[ShiftQueue.scala 27:57]
        elts_0_btb_bridx <= elts_1_btb_bridx;
      end else begin
        elts_0_btb_bridx <= io_enq_bits_btb_bridx;
      end
    end
    if (wen) begin // @[ShiftQueue.scala 32:16]
      if (valid_1) begin // @[ShiftQueue.scala 27:57]
        elts_0_btb_entry <= elts_1_btb_entry;
      end else begin
        elts_0_btb_entry <= io_enq_bits_btb_entry;
      end
    end
    if (wen) begin // @[ShiftQueue.scala 32:16]
      if (valid_1) begin // @[ShiftQueue.scala 27:57]
        elts_0_btb_bht_history <= elts_1_btb_bht_history;
      end else begin
        elts_0_btb_bht_history <= io_enq_bits_btb_bht_history;
      end
    end
    if (wen) begin // @[ShiftQueue.scala 32:16]
      if (valid_1) begin // @[ShiftQueue.scala 27:57]
        elts_0_pc <= elts_1_pc;
      end else begin
        elts_0_pc <= io_enq_bits_pc;
      end
    end
    if (wen) begin // @[ShiftQueue.scala 32:16]
      if (valid_1) begin // @[ShiftQueue.scala 27:57]
        elts_0_data <= elts_1_data;
      end else begin
        elts_0_data <= io_enq_bits_data;
      end
    end
    if (wen) begin // @[ShiftQueue.scala 32:16]
      if (valid_1) begin // @[ShiftQueue.scala 27:57]
        elts_0_xcpt_ae_inst <= elts_1_xcpt_ae_inst;
      end else begin
        elts_0_xcpt_ae_inst <= io_enq_bits_xcpt_ae_inst;
      end
    end
    if (wen) begin // @[ShiftQueue.scala 32:16]
      if (valid_1) begin // @[ShiftQueue.scala 27:57]
        elts_0_replay <= elts_1_replay;
      end else begin
        elts_0_replay <= io_enq_bits_replay;
      end
    end
    if (wen_1) begin // @[ShiftQueue.scala 32:16]
      if (valid_2) begin // @[ShiftQueue.scala 27:57]
        elts_1_btb_taken <= elts_2_btb_taken;
      end else begin
        elts_1_btb_taken <= io_enq_bits_btb_taken;
      end
    end
    if (wen_1) begin // @[ShiftQueue.scala 32:16]
      if (valid_2) begin // @[ShiftQueue.scala 27:57]
        elts_1_btb_bridx <= elts_2_btb_bridx;
      end else begin
        elts_1_btb_bridx <= io_enq_bits_btb_bridx;
      end
    end
    if (wen_1) begin // @[ShiftQueue.scala 32:16]
      if (valid_2) begin // @[ShiftQueue.scala 27:57]
        elts_1_btb_entry <= elts_2_btb_entry;
      end else begin
        elts_1_btb_entry <= io_enq_bits_btb_entry;
      end
    end
    if (wen_1) begin // @[ShiftQueue.scala 32:16]
      if (valid_2) begin // @[ShiftQueue.scala 27:57]
        elts_1_btb_bht_history <= elts_2_btb_bht_history;
      end else begin
        elts_1_btb_bht_history <= io_enq_bits_btb_bht_history;
      end
    end
    if (wen_1) begin // @[ShiftQueue.scala 32:16]
      if (valid_2) begin // @[ShiftQueue.scala 27:57]
        elts_1_pc <= elts_2_pc;
      end else begin
        elts_1_pc <= io_enq_bits_pc;
      end
    end
    if (wen_1) begin // @[ShiftQueue.scala 32:16]
      if (valid_2) begin // @[ShiftQueue.scala 27:57]
        elts_1_data <= elts_2_data;
      end else begin
        elts_1_data <= io_enq_bits_data;
      end
    end
    if (wen_1) begin // @[ShiftQueue.scala 32:16]
      if (valid_2) begin // @[ShiftQueue.scala 27:57]
        elts_1_xcpt_ae_inst <= elts_2_xcpt_ae_inst;
      end else begin
        elts_1_xcpt_ae_inst <= io_enq_bits_xcpt_ae_inst;
      end
    end
    if (wen_1) begin // @[ShiftQueue.scala 32:16]
      if (valid_2) begin // @[ShiftQueue.scala 27:57]
        elts_1_replay <= elts_2_replay;
      end else begin
        elts_1_replay <= io_enq_bits_replay;
      end
    end
    if (wen_2) begin // @[ShiftQueue.scala 32:16]
      if (valid_3) begin // @[ShiftQueue.scala 27:57]
        elts_2_btb_taken <= elts_3_btb_taken;
      end else begin
        elts_2_btb_taken <= io_enq_bits_btb_taken;
      end
    end
    if (wen_2) begin // @[ShiftQueue.scala 32:16]
      if (valid_3) begin // @[ShiftQueue.scala 27:57]
        elts_2_btb_bridx <= elts_3_btb_bridx;
      end else begin
        elts_2_btb_bridx <= io_enq_bits_btb_bridx;
      end
    end
    if (wen_2) begin // @[ShiftQueue.scala 32:16]
      if (valid_3) begin // @[ShiftQueue.scala 27:57]
        elts_2_btb_entry <= elts_3_btb_entry;
      end else begin
        elts_2_btb_entry <= io_enq_bits_btb_entry;
      end
    end
    if (wen_2) begin // @[ShiftQueue.scala 32:16]
      if (valid_3) begin // @[ShiftQueue.scala 27:57]
        elts_2_btb_bht_history <= elts_3_btb_bht_history;
      end else begin
        elts_2_btb_bht_history <= io_enq_bits_btb_bht_history;
      end
    end
    if (wen_2) begin // @[ShiftQueue.scala 32:16]
      if (valid_3) begin // @[ShiftQueue.scala 27:57]
        elts_2_pc <= elts_3_pc;
      end else begin
        elts_2_pc <= io_enq_bits_pc;
      end
    end
    if (wen_2) begin // @[ShiftQueue.scala 32:16]
      if (valid_3) begin // @[ShiftQueue.scala 27:57]
        elts_2_data <= elts_3_data;
      end else begin
        elts_2_data <= io_enq_bits_data;
      end
    end
    if (wen_2) begin // @[ShiftQueue.scala 32:16]
      if (valid_3) begin // @[ShiftQueue.scala 27:57]
        elts_2_xcpt_ae_inst <= elts_3_xcpt_ae_inst;
      end else begin
        elts_2_xcpt_ae_inst <= io_enq_bits_xcpt_ae_inst;
      end
    end
    if (wen_2) begin // @[ShiftQueue.scala 32:16]
      if (valid_3) begin // @[ShiftQueue.scala 27:57]
        elts_2_replay <= elts_3_replay;
      end else begin
        elts_2_replay <= io_enq_bits_replay;
      end
    end
    if (wen_3) begin // @[ShiftQueue.scala 32:16]
      if (valid_4) begin // @[ShiftQueue.scala 27:57]
        elts_3_btb_taken <= elts_4_btb_taken;
      end else begin
        elts_3_btb_taken <= io_enq_bits_btb_taken;
      end
    end
    if (wen_3) begin // @[ShiftQueue.scala 32:16]
      if (valid_4) begin // @[ShiftQueue.scala 27:57]
        elts_3_btb_bridx <= elts_4_btb_bridx;
      end else begin
        elts_3_btb_bridx <= io_enq_bits_btb_bridx;
      end
    end
    if (wen_3) begin // @[ShiftQueue.scala 32:16]
      if (valid_4) begin // @[ShiftQueue.scala 27:57]
        elts_3_btb_entry <= elts_4_btb_entry;
      end else begin
        elts_3_btb_entry <= io_enq_bits_btb_entry;
      end
    end
    if (wen_3) begin // @[ShiftQueue.scala 32:16]
      if (valid_4) begin // @[ShiftQueue.scala 27:57]
        elts_3_btb_bht_history <= elts_4_btb_bht_history;
      end else begin
        elts_3_btb_bht_history <= io_enq_bits_btb_bht_history;
      end
    end
    if (wen_3) begin // @[ShiftQueue.scala 32:16]
      if (valid_4) begin // @[ShiftQueue.scala 27:57]
        elts_3_pc <= elts_4_pc;
      end else begin
        elts_3_pc <= io_enq_bits_pc;
      end
    end
    if (wen_3) begin // @[ShiftQueue.scala 32:16]
      if (valid_4) begin // @[ShiftQueue.scala 27:57]
        elts_3_data <= elts_4_data;
      end else begin
        elts_3_data <= io_enq_bits_data;
      end
    end
    if (wen_3) begin // @[ShiftQueue.scala 32:16]
      if (valid_4) begin // @[ShiftQueue.scala 27:57]
        elts_3_xcpt_ae_inst <= elts_4_xcpt_ae_inst;
      end else begin
        elts_3_xcpt_ae_inst <= io_enq_bits_xcpt_ae_inst;
      end
    end
    if (wen_3) begin // @[ShiftQueue.scala 32:16]
      if (valid_4) begin // @[ShiftQueue.scala 27:57]
        elts_3_replay <= elts_4_replay;
      end else begin
        elts_3_replay <= io_enq_bits_replay;
      end
    end
    if (wen_4) begin // @[ShiftQueue.scala 32:16]
      elts_4_btb_taken <= io_enq_bits_btb_taken; // @[ShiftQueue.scala 32:26]
    end
    if (wen_4) begin // @[ShiftQueue.scala 32:16]
      elts_4_btb_bridx <= io_enq_bits_btb_bridx; // @[ShiftQueue.scala 32:26]
    end
    if (wen_4) begin // @[ShiftQueue.scala 32:16]
      elts_4_btb_entry <= io_enq_bits_btb_entry; // @[ShiftQueue.scala 32:26]
    end
    if (wen_4) begin // @[ShiftQueue.scala 32:16]
      elts_4_btb_bht_history <= io_enq_bits_btb_bht_history; // @[ShiftQueue.scala 32:26]
    end
    if (wen_4) begin // @[ShiftQueue.scala 32:16]
      elts_4_pc <= io_enq_bits_pc; // @[ShiftQueue.scala 32:26]
    end
    if (wen_4) begin // @[ShiftQueue.scala 32:16]
      elts_4_data <= io_enq_bits_data; // @[ShiftQueue.scala 32:26]
    end
    if (wen_4) begin // @[ShiftQueue.scala 32:16]
      elts_4_xcpt_ae_inst <= io_enq_bits_xcpt_ae_inst; // @[ShiftQueue.scala 32:26]
    end
    if (wen_4) begin // @[ShiftQueue.scala 32:16]
      elts_4_replay <= io_enq_bits_replay; // @[ShiftQueue.scala 32:26]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  valid_0 = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  valid_1 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  valid_2 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  valid_3 = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  valid_4 = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  elts_0_btb_taken = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  elts_0_btb_bridx = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  elts_0_btb_entry = _RAND_7[4:0];
  _RAND_8 = {1{`RANDOM}};
  elts_0_btb_bht_history = _RAND_8[7:0];
  _RAND_9 = {1{`RANDOM}};
  elts_0_pc = _RAND_9[31:0];
  _RAND_10 = {1{`RANDOM}};
  elts_0_data = _RAND_10[31:0];
  _RAND_11 = {1{`RANDOM}};
  elts_0_xcpt_ae_inst = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  elts_0_replay = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  elts_1_btb_taken = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  elts_1_btb_bridx = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  elts_1_btb_entry = _RAND_15[4:0];
  _RAND_16 = {1{`RANDOM}};
  elts_1_btb_bht_history = _RAND_16[7:0];
  _RAND_17 = {1{`RANDOM}};
  elts_1_pc = _RAND_17[31:0];
  _RAND_18 = {1{`RANDOM}};
  elts_1_data = _RAND_18[31:0];
  _RAND_19 = {1{`RANDOM}};
  elts_1_xcpt_ae_inst = _RAND_19[0:0];
  _RAND_20 = {1{`RANDOM}};
  elts_1_replay = _RAND_20[0:0];
  _RAND_21 = {1{`RANDOM}};
  elts_2_btb_taken = _RAND_21[0:0];
  _RAND_22 = {1{`RANDOM}};
  elts_2_btb_bridx = _RAND_22[0:0];
  _RAND_23 = {1{`RANDOM}};
  elts_2_btb_entry = _RAND_23[4:0];
  _RAND_24 = {1{`RANDOM}};
  elts_2_btb_bht_history = _RAND_24[7:0];
  _RAND_25 = {1{`RANDOM}};
  elts_2_pc = _RAND_25[31:0];
  _RAND_26 = {1{`RANDOM}};
  elts_2_data = _RAND_26[31:0];
  _RAND_27 = {1{`RANDOM}};
  elts_2_xcpt_ae_inst = _RAND_27[0:0];
  _RAND_28 = {1{`RANDOM}};
  elts_2_replay = _RAND_28[0:0];
  _RAND_29 = {1{`RANDOM}};
  elts_3_btb_taken = _RAND_29[0:0];
  _RAND_30 = {1{`RANDOM}};
  elts_3_btb_bridx = _RAND_30[0:0];
  _RAND_31 = {1{`RANDOM}};
  elts_3_btb_entry = _RAND_31[4:0];
  _RAND_32 = {1{`RANDOM}};
  elts_3_btb_bht_history = _RAND_32[7:0];
  _RAND_33 = {1{`RANDOM}};
  elts_3_pc = _RAND_33[31:0];
  _RAND_34 = {1{`RANDOM}};
  elts_3_data = _RAND_34[31:0];
  _RAND_35 = {1{`RANDOM}};
  elts_3_xcpt_ae_inst = _RAND_35[0:0];
  _RAND_36 = {1{`RANDOM}};
  elts_3_replay = _RAND_36[0:0];
  _RAND_37 = {1{`RANDOM}};
  elts_4_btb_taken = _RAND_37[0:0];
  _RAND_38 = {1{`RANDOM}};
  elts_4_btb_bridx = _RAND_38[0:0];
  _RAND_39 = {1{`RANDOM}};
  elts_4_btb_entry = _RAND_39[4:0];
  _RAND_40 = {1{`RANDOM}};
  elts_4_btb_bht_history = _RAND_40[7:0];
  _RAND_41 = {1{`RANDOM}};
  elts_4_pc = _RAND_41[31:0];
  _RAND_42 = {1{`RANDOM}};
  elts_4_data = _RAND_42[31:0];
  _RAND_43 = {1{`RANDOM}};
  elts_4_xcpt_ae_inst = _RAND_43[0:0];
  _RAND_44 = {1{`RANDOM}};
  elts_4_replay = _RAND_44[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLB_1(
  input  [31:0] io_req_bits_vaddr,
  input  [1:0]  io_req_bits_prv,
  output [30:0] io_resp_paddr,
  output        io_resp_ae_inst,
  output        io_resp_cacheable,
  input         io_ptw_status_debug,
  input         io_ptw_pmp_0_cfg_l,
  input  [1:0]  io_ptw_pmp_0_cfg_a,
  input         io_ptw_pmp_0_cfg_x,
  input         io_ptw_pmp_0_cfg_w,
  input         io_ptw_pmp_0_cfg_r,
  input  [28:0] io_ptw_pmp_0_addr,
  input  [30:0] io_ptw_pmp_0_mask,
  input         io_ptw_pmp_1_cfg_l,
  input  [1:0]  io_ptw_pmp_1_cfg_a,
  input         io_ptw_pmp_1_cfg_x,
  input         io_ptw_pmp_1_cfg_w,
  input         io_ptw_pmp_1_cfg_r,
  input  [28:0] io_ptw_pmp_1_addr,
  input  [30:0] io_ptw_pmp_1_mask,
  input         io_ptw_pmp_2_cfg_l,
  input  [1:0]  io_ptw_pmp_2_cfg_a,
  input         io_ptw_pmp_2_cfg_x,
  input         io_ptw_pmp_2_cfg_w,
  input         io_ptw_pmp_2_cfg_r,
  input  [28:0] io_ptw_pmp_2_addr,
  input  [30:0] io_ptw_pmp_2_mask,
  input         io_ptw_pmp_3_cfg_l,
  input  [1:0]  io_ptw_pmp_3_cfg_a,
  input         io_ptw_pmp_3_cfg_x,
  input         io_ptw_pmp_3_cfg_w,
  input         io_ptw_pmp_3_cfg_r,
  input  [28:0] io_ptw_pmp_3_addr,
  input  [30:0] io_ptw_pmp_3_mask,
  input         io_ptw_pmp_4_cfg_l,
  input  [1:0]  io_ptw_pmp_4_cfg_a,
  input         io_ptw_pmp_4_cfg_x,
  input         io_ptw_pmp_4_cfg_w,
  input         io_ptw_pmp_4_cfg_r,
  input  [28:0] io_ptw_pmp_4_addr,
  input  [30:0] io_ptw_pmp_4_mask,
  input         io_ptw_pmp_5_cfg_l,
  input  [1:0]  io_ptw_pmp_5_cfg_a,
  input         io_ptw_pmp_5_cfg_x,
  input         io_ptw_pmp_5_cfg_w,
  input         io_ptw_pmp_5_cfg_r,
  input  [28:0] io_ptw_pmp_5_addr,
  input  [30:0] io_ptw_pmp_5_mask,
  input         io_ptw_pmp_6_cfg_l,
  input  [1:0]  io_ptw_pmp_6_cfg_a,
  input         io_ptw_pmp_6_cfg_x,
  input         io_ptw_pmp_6_cfg_w,
  input         io_ptw_pmp_6_cfg_r,
  input  [28:0] io_ptw_pmp_6_addr,
  input  [30:0] io_ptw_pmp_6_mask,
  input         io_ptw_pmp_7_cfg_l,
  input  [1:0]  io_ptw_pmp_7_cfg_a,
  input         io_ptw_pmp_7_cfg_x,
  input         io_ptw_pmp_7_cfg_w,
  input         io_ptw_pmp_7_cfg_r,
  input  [28:0] io_ptw_pmp_7_addr,
  input  [30:0] io_ptw_pmp_7_mask
);
  wire [1:0] pmp_io_prv; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_0_cfg_l; // @[TLB.scala 233:19]
  wire [1:0] pmp_io_pmp_0_cfg_a; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_0_cfg_x; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_0_cfg_w; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_0_cfg_r; // @[TLB.scala 233:19]
  wire [28:0] pmp_io_pmp_0_addr; // @[TLB.scala 233:19]
  wire [30:0] pmp_io_pmp_0_mask; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_1_cfg_l; // @[TLB.scala 233:19]
  wire [1:0] pmp_io_pmp_1_cfg_a; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_1_cfg_x; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_1_cfg_w; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_1_cfg_r; // @[TLB.scala 233:19]
  wire [28:0] pmp_io_pmp_1_addr; // @[TLB.scala 233:19]
  wire [30:0] pmp_io_pmp_1_mask; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_2_cfg_l; // @[TLB.scala 233:19]
  wire [1:0] pmp_io_pmp_2_cfg_a; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_2_cfg_x; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_2_cfg_w; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_2_cfg_r; // @[TLB.scala 233:19]
  wire [28:0] pmp_io_pmp_2_addr; // @[TLB.scala 233:19]
  wire [30:0] pmp_io_pmp_2_mask; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_3_cfg_l; // @[TLB.scala 233:19]
  wire [1:0] pmp_io_pmp_3_cfg_a; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_3_cfg_x; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_3_cfg_w; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_3_cfg_r; // @[TLB.scala 233:19]
  wire [28:0] pmp_io_pmp_3_addr; // @[TLB.scala 233:19]
  wire [30:0] pmp_io_pmp_3_mask; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_4_cfg_l; // @[TLB.scala 233:19]
  wire [1:0] pmp_io_pmp_4_cfg_a; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_4_cfg_x; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_4_cfg_w; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_4_cfg_r; // @[TLB.scala 233:19]
  wire [28:0] pmp_io_pmp_4_addr; // @[TLB.scala 233:19]
  wire [30:0] pmp_io_pmp_4_mask; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_5_cfg_l; // @[TLB.scala 233:19]
  wire [1:0] pmp_io_pmp_5_cfg_a; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_5_cfg_x; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_5_cfg_w; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_5_cfg_r; // @[TLB.scala 233:19]
  wire [28:0] pmp_io_pmp_5_addr; // @[TLB.scala 233:19]
  wire [30:0] pmp_io_pmp_5_mask; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_6_cfg_l; // @[TLB.scala 233:19]
  wire [1:0] pmp_io_pmp_6_cfg_a; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_6_cfg_x; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_6_cfg_w; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_6_cfg_r; // @[TLB.scala 233:19]
  wire [28:0] pmp_io_pmp_6_addr; // @[TLB.scala 233:19]
  wire [30:0] pmp_io_pmp_6_mask; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_7_cfg_l; // @[TLB.scala 233:19]
  wire [1:0] pmp_io_pmp_7_cfg_a; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_7_cfg_x; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_7_cfg_w; // @[TLB.scala 233:19]
  wire  pmp_io_pmp_7_cfg_r; // @[TLB.scala 233:19]
  wire [28:0] pmp_io_pmp_7_addr; // @[TLB.scala 233:19]
  wire [30:0] pmp_io_pmp_7_mask; // @[TLB.scala 233:19]
  wire [30:0] pmp_io_addr; // @[TLB.scala 233:19]
  wire  pmp_io_r; // @[TLB.scala 233:19]
  wire  pmp_io_w; // @[TLB.scala 233:19]
  wire  pmp_io_x; // @[TLB.scala 233:19]
  wire [19:0] vpn = io_req_bits_vaddr[31:12]; // @[TLB.scala 187:30]
  wire [19:0] mpu_ppn = io_req_bits_vaddr[31:12]; // @[TLB.scala 230:144]
  wire [31:0] mpu_physaddr = {mpu_ppn,io_req_bits_vaddr[11:0]}; // @[Cat.scala 31:58]
  wire [2:0] mpu_priv = {io_ptw_status_debug,io_req_bits_prv}; // @[Cat.scala 31:58]
  wire [31:0] _legal_address_T = mpu_physaddr ^ 32'h3000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_1 = {1'b0,$signed(_legal_address_T)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_3 = $signed(_legal_address_T_1) & -33'sh1000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_4 = $signed(_legal_address_T_3) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_5 = mpu_physaddr ^ 32'h10013000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_6 = {1'b0,$signed(_legal_address_T_5)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_8 = $signed(_legal_address_T_6) & -33'sh1000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_9 = $signed(_legal_address_T_8) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_10 = mpu_physaddr ^ 32'h10023000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_11 = {1'b0,$signed(_legal_address_T_10)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_13 = $signed(_legal_address_T_11) & -33'sh1000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_14 = $signed(_legal_address_T_13) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_15 = mpu_physaddr ^ 32'h10033000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_16 = {1'b0,$signed(_legal_address_T_15)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_18 = $signed(_legal_address_T_16) & -33'sh1000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_19 = $signed(_legal_address_T_18) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_20 = mpu_physaddr ^ 32'h10043000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_21 = {1'b0,$signed(_legal_address_T_20)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_23 = $signed(_legal_address_T_21) & -33'sh1000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_24 = $signed(_legal_address_T_23) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_25 = mpu_physaddr ^ 32'h10053000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_26 = {1'b0,$signed(_legal_address_T_25)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_28 = $signed(_legal_address_T_26) & -33'sh1000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_29 = $signed(_legal_address_T_28) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_30 = mpu_physaddr ^ 32'h10014000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_31 = {1'b0,$signed(_legal_address_T_30)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_33 = $signed(_legal_address_T_31) & -33'sh1000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_34 = $signed(_legal_address_T_33) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_35 = mpu_physaddr ^ 32'h20000000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_36 = {1'b0,$signed(_legal_address_T_35)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_38 = $signed(_legal_address_T_36) & -33'sh20000000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_39 = $signed(_legal_address_T_38) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_40 = mpu_physaddr ^ 32'h10034000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_41 = {1'b0,$signed(_legal_address_T_40)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_43 = $signed(_legal_address_T_41) & -33'sh1000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_44 = $signed(_legal_address_T_43) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_45 = mpu_physaddr ^ 32'h10024000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_46 = {1'b0,$signed(_legal_address_T_45)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_48 = $signed(_legal_address_T_46) & -33'sh1000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_49 = $signed(_legal_address_T_48) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_50 = mpu_physaddr ^ 32'h10012000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_51 = {1'b0,$signed(_legal_address_T_50)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_53 = $signed(_legal_address_T_51) & -33'sh1000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_54 = $signed(_legal_address_T_53) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_55 = mpu_physaddr ^ 32'h10015000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_56 = {1'b0,$signed(_legal_address_T_55)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_58 = $signed(_legal_address_T_56) & -33'sh1000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_59 = $signed(_legal_address_T_58) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_60 = mpu_physaddr ^ 32'h10025000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_61 = {1'b0,$signed(_legal_address_T_60)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_63 = $signed(_legal_address_T_61) & -33'sh1000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_64 = $signed(_legal_address_T_63) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_65 = mpu_physaddr ^ 32'h10035000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_66 = {1'b0,$signed(_legal_address_T_65)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_68 = $signed(_legal_address_T_66) & -33'sh1000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_69 = $signed(_legal_address_T_68) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_70 = mpu_physaddr ^ 32'h10016000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_71 = {1'b0,$signed(_legal_address_T_70)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_73 = $signed(_legal_address_T_71) & -33'sh1000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_74 = $signed(_legal_address_T_73) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_75 = mpu_physaddr ^ 32'h10026000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_76 = {1'b0,$signed(_legal_address_T_75)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_78 = $signed(_legal_address_T_76) & -33'sh1000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_79 = $signed(_legal_address_T_78) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_80 = mpu_physaddr ^ 32'hc000000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_81 = {1'b0,$signed(_legal_address_T_80)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_83 = $signed(_legal_address_T_81) & -33'sh4000000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_84 = $signed(_legal_address_T_83) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_85 = mpu_physaddr ^ 32'h2000000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_86 = {1'b0,$signed(_legal_address_T_85)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_88 = $signed(_legal_address_T_86) & -33'sh10000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_89 = $signed(_legal_address_T_88) == 33'sh0; // @[Parameters.scala 137:67]
  wire [32:0] _legal_address_T_91 = {1'b0,$signed(mpu_physaddr)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_93 = $signed(_legal_address_T_91) & -33'sh1000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_94 = $signed(_legal_address_T_93) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_95 = mpu_physaddr ^ 32'h8000000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_96 = {1'b0,$signed(_legal_address_T_95)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_98 = $signed(_legal_address_T_96) & -33'sh4000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_99 = $signed(_legal_address_T_98) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_100 = mpu_physaddr ^ 32'h10000000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_101 = {1'b0,$signed(_legal_address_T_100)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_103 = $signed(_legal_address_T_101) & -33'sh1000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_104 = $signed(_legal_address_T_103) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_105 = mpu_physaddr ^ 32'h10000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_106 = {1'b0,$signed(_legal_address_T_105)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_108 = $signed(_legal_address_T_106) & -33'sh10000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_109 = $signed(_legal_address_T_108) == 33'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _legal_address_T_110 = mpu_physaddr ^ 32'h40000000; // @[Parameters.scala 137:31]
  wire [32:0] _legal_address_T_111 = {1'b0,$signed(_legal_address_T_110)}; // @[Parameters.scala 137:49]
  wire [32:0] _legal_address_T_113 = $signed(_legal_address_T_111) & -33'sh20000000; // @[Parameters.scala 137:52]
  wire  _legal_address_T_114 = $signed(_legal_address_T_113) == 33'sh0; // @[Parameters.scala 137:67]
  wire  legal_address = _legal_address_T_4 | _legal_address_T_9 | _legal_address_T_14 | _legal_address_T_19 |
    _legal_address_T_24 | _legal_address_T_29 | _legal_address_T_34 | _legal_address_T_39 | _legal_address_T_44 |
    _legal_address_T_49 | _legal_address_T_54 | _legal_address_T_59 | _legal_address_T_64 | _legal_address_T_69 |
    _legal_address_T_74 | _legal_address_T_79 | _legal_address_T_84 | _legal_address_T_89 | _legal_address_T_94 |
    _legal_address_T_99 | _legal_address_T_104 | _legal_address_T_109 | _legal_address_T_114; // @[TLB.scala 238:67]
  wire [32:0] _cacheable_T_8 = $signed(_legal_address_T_111) & 33'sh40000000; // @[Parameters.scala 137:52]
  wire  _cacheable_T_9 = $signed(_cacheable_T_8) == 33'sh0; // @[Parameters.scala 137:67]
  wire  cacheable = legal_address & _cacheable_T_9; // @[TLB.scala 240:19]
  wire [32:0] _homogeneous_T_98 = $signed(_legal_address_T_36) & 33'sh60000000; // @[Parameters.scala 137:52]
  wire  _homogeneous_T_99 = $signed(_homogeneous_T_98) == 33'sh0; // @[Parameters.scala 137:67]
  wire [32:0] _homogeneous_T_116 = $signed(_legal_address_T_111) & 33'sh60000000; // @[Parameters.scala 137:52]
  wire  _homogeneous_T_117 = $signed(_homogeneous_T_116) == 33'sh0; // @[Parameters.scala 137:67]
  wire  deny_access_to_debug = mpu_priv <= 3'h3 & _legal_address_T_94; // @[TLB.scala 243:48]
  wire  _prot_r_T_6 = ~deny_access_to_debug; // @[TLB.scala 244:44]
  wire [32:0] _prot_x_T_3 = $signed(_legal_address_T_91) & 33'sh76040000; // @[Parameters.scala 137:52]
  wire  _prot_x_T_4 = $signed(_prot_x_T_3) == 33'sh0; // @[Parameters.scala 137:67]
  wire  _prot_x_T_16 = _prot_x_T_4 | _homogeneous_T_99 | _homogeneous_T_117; // @[Parameters.scala 615:89]
  wire  _prot_x_T_43 = legal_address & _prot_x_T_16; // @[TLB.scala 240:19]
  wire  prot_x = _prot_x_T_43 & _prot_r_T_6 & pmp_io_x; // @[TLB.scala 249:65]
  wire [18:0] ppn = vpn[18:0]; // @[TLB.scala 310:125]
  wire [1:0] _px_array_T_1 = prot_x ? 2'h3 : 2'h0; // @[Bitwise.scala 74:12]
  wire [6:0] px_array = {_px_array_T_1,5'h0}; // @[Cat.scala 31:58]
  wire [1:0] _c_array_T_1 = cacheable ? 2'h3 : 2'h0; // @[Bitwise.scala 74:12]
  wire [6:0] c_array = {_c_array_T_1,5'h0}; // @[Cat.scala 31:58]
  wire [6:0] _io_resp_ae_inst_T = ~px_array; // @[TLB.scala 427:23]
  wire [6:0] _io_resp_ae_inst_T_1 = _io_resp_ae_inst_T & 7'h40; // @[TLB.scala 427:33]
  wire [6:0] _io_resp_cacheable_T = c_array & 7'h40; // @[TLB.scala 431:33]
  PMPChecker pmp ( // @[TLB.scala 233:19]
    .io_prv(pmp_io_prv),
    .io_pmp_0_cfg_l(pmp_io_pmp_0_cfg_l),
    .io_pmp_0_cfg_a(pmp_io_pmp_0_cfg_a),
    .io_pmp_0_cfg_x(pmp_io_pmp_0_cfg_x),
    .io_pmp_0_cfg_w(pmp_io_pmp_0_cfg_w),
    .io_pmp_0_cfg_r(pmp_io_pmp_0_cfg_r),
    .io_pmp_0_addr(pmp_io_pmp_0_addr),
    .io_pmp_0_mask(pmp_io_pmp_0_mask),
    .io_pmp_1_cfg_l(pmp_io_pmp_1_cfg_l),
    .io_pmp_1_cfg_a(pmp_io_pmp_1_cfg_a),
    .io_pmp_1_cfg_x(pmp_io_pmp_1_cfg_x),
    .io_pmp_1_cfg_w(pmp_io_pmp_1_cfg_w),
    .io_pmp_1_cfg_r(pmp_io_pmp_1_cfg_r),
    .io_pmp_1_addr(pmp_io_pmp_1_addr),
    .io_pmp_1_mask(pmp_io_pmp_1_mask),
    .io_pmp_2_cfg_l(pmp_io_pmp_2_cfg_l),
    .io_pmp_2_cfg_a(pmp_io_pmp_2_cfg_a),
    .io_pmp_2_cfg_x(pmp_io_pmp_2_cfg_x),
    .io_pmp_2_cfg_w(pmp_io_pmp_2_cfg_w),
    .io_pmp_2_cfg_r(pmp_io_pmp_2_cfg_r),
    .io_pmp_2_addr(pmp_io_pmp_2_addr),
    .io_pmp_2_mask(pmp_io_pmp_2_mask),
    .io_pmp_3_cfg_l(pmp_io_pmp_3_cfg_l),
    .io_pmp_3_cfg_a(pmp_io_pmp_3_cfg_a),
    .io_pmp_3_cfg_x(pmp_io_pmp_3_cfg_x),
    .io_pmp_3_cfg_w(pmp_io_pmp_3_cfg_w),
    .io_pmp_3_cfg_r(pmp_io_pmp_3_cfg_r),
    .io_pmp_3_addr(pmp_io_pmp_3_addr),
    .io_pmp_3_mask(pmp_io_pmp_3_mask),
    .io_pmp_4_cfg_l(pmp_io_pmp_4_cfg_l),
    .io_pmp_4_cfg_a(pmp_io_pmp_4_cfg_a),
    .io_pmp_4_cfg_x(pmp_io_pmp_4_cfg_x),
    .io_pmp_4_cfg_w(pmp_io_pmp_4_cfg_w),
    .io_pmp_4_cfg_r(pmp_io_pmp_4_cfg_r),
    .io_pmp_4_addr(pmp_io_pmp_4_addr),
    .io_pmp_4_mask(pmp_io_pmp_4_mask),
    .io_pmp_5_cfg_l(pmp_io_pmp_5_cfg_l),
    .io_pmp_5_cfg_a(pmp_io_pmp_5_cfg_a),
    .io_pmp_5_cfg_x(pmp_io_pmp_5_cfg_x),
    .io_pmp_5_cfg_w(pmp_io_pmp_5_cfg_w),
    .io_pmp_5_cfg_r(pmp_io_pmp_5_cfg_r),
    .io_pmp_5_addr(pmp_io_pmp_5_addr),
    .io_pmp_5_mask(pmp_io_pmp_5_mask),
    .io_pmp_6_cfg_l(pmp_io_pmp_6_cfg_l),
    .io_pmp_6_cfg_a(pmp_io_pmp_6_cfg_a),
    .io_pmp_6_cfg_x(pmp_io_pmp_6_cfg_x),
    .io_pmp_6_cfg_w(pmp_io_pmp_6_cfg_w),
    .io_pmp_6_cfg_r(pmp_io_pmp_6_cfg_r),
    .io_pmp_6_addr(pmp_io_pmp_6_addr),
    .io_pmp_6_mask(pmp_io_pmp_6_mask),
    .io_pmp_7_cfg_l(pmp_io_pmp_7_cfg_l),
    .io_pmp_7_cfg_a(pmp_io_pmp_7_cfg_a),
    .io_pmp_7_cfg_x(pmp_io_pmp_7_cfg_x),
    .io_pmp_7_cfg_w(pmp_io_pmp_7_cfg_w),
    .io_pmp_7_cfg_r(pmp_io_pmp_7_cfg_r),
    .io_pmp_7_addr(pmp_io_pmp_7_addr),
    .io_pmp_7_mask(pmp_io_pmp_7_mask),
    .io_addr(pmp_io_addr),
    .io_r(pmp_io_r),
    .io_w(pmp_io_w),
    .io_x(pmp_io_x)
  );
  assign io_resp_paddr = {ppn,io_req_bits_vaddr[11:0]}; // @[Cat.scala 31:58]
  assign io_resp_ae_inst = |_io_resp_ae_inst_T_1; // @[TLB.scala 427:41]
  assign io_resp_cacheable = |_io_resp_cacheable_T; // @[TLB.scala 431:41]
  assign pmp_io_prv = mpu_priv[1:0]; // @[TLB.scala 237:14]
  assign pmp_io_pmp_0_cfg_l = io_ptw_pmp_0_cfg_l; // @[TLB.scala 236:14]
  assign pmp_io_pmp_0_cfg_a = io_ptw_pmp_0_cfg_a; // @[TLB.scala 236:14]
  assign pmp_io_pmp_0_cfg_x = io_ptw_pmp_0_cfg_x; // @[TLB.scala 236:14]
  assign pmp_io_pmp_0_cfg_w = io_ptw_pmp_0_cfg_w; // @[TLB.scala 236:14]
  assign pmp_io_pmp_0_cfg_r = io_ptw_pmp_0_cfg_r; // @[TLB.scala 236:14]
  assign pmp_io_pmp_0_addr = io_ptw_pmp_0_addr; // @[TLB.scala 236:14]
  assign pmp_io_pmp_0_mask = io_ptw_pmp_0_mask; // @[TLB.scala 236:14]
  assign pmp_io_pmp_1_cfg_l = io_ptw_pmp_1_cfg_l; // @[TLB.scala 236:14]
  assign pmp_io_pmp_1_cfg_a = io_ptw_pmp_1_cfg_a; // @[TLB.scala 236:14]
  assign pmp_io_pmp_1_cfg_x = io_ptw_pmp_1_cfg_x; // @[TLB.scala 236:14]
  assign pmp_io_pmp_1_cfg_w = io_ptw_pmp_1_cfg_w; // @[TLB.scala 236:14]
  assign pmp_io_pmp_1_cfg_r = io_ptw_pmp_1_cfg_r; // @[TLB.scala 236:14]
  assign pmp_io_pmp_1_addr = io_ptw_pmp_1_addr; // @[TLB.scala 236:14]
  assign pmp_io_pmp_1_mask = io_ptw_pmp_1_mask; // @[TLB.scala 236:14]
  assign pmp_io_pmp_2_cfg_l = io_ptw_pmp_2_cfg_l; // @[TLB.scala 236:14]
  assign pmp_io_pmp_2_cfg_a = io_ptw_pmp_2_cfg_a; // @[TLB.scala 236:14]
  assign pmp_io_pmp_2_cfg_x = io_ptw_pmp_2_cfg_x; // @[TLB.scala 236:14]
  assign pmp_io_pmp_2_cfg_w = io_ptw_pmp_2_cfg_w; // @[TLB.scala 236:14]
  assign pmp_io_pmp_2_cfg_r = io_ptw_pmp_2_cfg_r; // @[TLB.scala 236:14]
  assign pmp_io_pmp_2_addr = io_ptw_pmp_2_addr; // @[TLB.scala 236:14]
  assign pmp_io_pmp_2_mask = io_ptw_pmp_2_mask; // @[TLB.scala 236:14]
  assign pmp_io_pmp_3_cfg_l = io_ptw_pmp_3_cfg_l; // @[TLB.scala 236:14]
  assign pmp_io_pmp_3_cfg_a = io_ptw_pmp_3_cfg_a; // @[TLB.scala 236:14]
  assign pmp_io_pmp_3_cfg_x = io_ptw_pmp_3_cfg_x; // @[TLB.scala 236:14]
  assign pmp_io_pmp_3_cfg_w = io_ptw_pmp_3_cfg_w; // @[TLB.scala 236:14]
  assign pmp_io_pmp_3_cfg_r = io_ptw_pmp_3_cfg_r; // @[TLB.scala 236:14]
  assign pmp_io_pmp_3_addr = io_ptw_pmp_3_addr; // @[TLB.scala 236:14]
  assign pmp_io_pmp_3_mask = io_ptw_pmp_3_mask; // @[TLB.scala 236:14]
  assign pmp_io_pmp_4_cfg_l = io_ptw_pmp_4_cfg_l; // @[TLB.scala 236:14]
  assign pmp_io_pmp_4_cfg_a = io_ptw_pmp_4_cfg_a; // @[TLB.scala 236:14]
  assign pmp_io_pmp_4_cfg_x = io_ptw_pmp_4_cfg_x; // @[TLB.scala 236:14]
  assign pmp_io_pmp_4_cfg_w = io_ptw_pmp_4_cfg_w; // @[TLB.scala 236:14]
  assign pmp_io_pmp_4_cfg_r = io_ptw_pmp_4_cfg_r; // @[TLB.scala 236:14]
  assign pmp_io_pmp_4_addr = io_ptw_pmp_4_addr; // @[TLB.scala 236:14]
  assign pmp_io_pmp_4_mask = io_ptw_pmp_4_mask; // @[TLB.scala 236:14]
  assign pmp_io_pmp_5_cfg_l = io_ptw_pmp_5_cfg_l; // @[TLB.scala 236:14]
  assign pmp_io_pmp_5_cfg_a = io_ptw_pmp_5_cfg_a; // @[TLB.scala 236:14]
  assign pmp_io_pmp_5_cfg_x = io_ptw_pmp_5_cfg_x; // @[TLB.scala 236:14]
  assign pmp_io_pmp_5_cfg_w = io_ptw_pmp_5_cfg_w; // @[TLB.scala 236:14]
  assign pmp_io_pmp_5_cfg_r = io_ptw_pmp_5_cfg_r; // @[TLB.scala 236:14]
  assign pmp_io_pmp_5_addr = io_ptw_pmp_5_addr; // @[TLB.scala 236:14]
  assign pmp_io_pmp_5_mask = io_ptw_pmp_5_mask; // @[TLB.scala 236:14]
  assign pmp_io_pmp_6_cfg_l = io_ptw_pmp_6_cfg_l; // @[TLB.scala 236:14]
  assign pmp_io_pmp_6_cfg_a = io_ptw_pmp_6_cfg_a; // @[TLB.scala 236:14]
  assign pmp_io_pmp_6_cfg_x = io_ptw_pmp_6_cfg_x; // @[TLB.scala 236:14]
  assign pmp_io_pmp_6_cfg_w = io_ptw_pmp_6_cfg_w; // @[TLB.scala 236:14]
  assign pmp_io_pmp_6_cfg_r = io_ptw_pmp_6_cfg_r; // @[TLB.scala 236:14]
  assign pmp_io_pmp_6_addr = io_ptw_pmp_6_addr; // @[TLB.scala 236:14]
  assign pmp_io_pmp_6_mask = io_ptw_pmp_6_mask; // @[TLB.scala 236:14]
  assign pmp_io_pmp_7_cfg_l = io_ptw_pmp_7_cfg_l; // @[TLB.scala 236:14]
  assign pmp_io_pmp_7_cfg_a = io_ptw_pmp_7_cfg_a; // @[TLB.scala 236:14]
  assign pmp_io_pmp_7_cfg_x = io_ptw_pmp_7_cfg_x; // @[TLB.scala 236:14]
  assign pmp_io_pmp_7_cfg_w = io_ptw_pmp_7_cfg_w; // @[TLB.scala 236:14]
  assign pmp_io_pmp_7_cfg_r = io_ptw_pmp_7_cfg_r; // @[TLB.scala 236:14]
  assign pmp_io_pmp_7_addr = io_ptw_pmp_7_addr; // @[TLB.scala 236:14]
  assign pmp_io_pmp_7_mask = io_ptw_pmp_7_mask; // @[TLB.scala 236:14]
  assign pmp_io_addr = mpu_physaddr[30:0]; // @[TLB.scala 234:15]
endmodule
module BTB(
  input         clock,
  input         reset,
  input  [31:0] io_req_bits_addr,
  output        io_resp_valid,
  output        io_resp_bits_taken,
  output        io_resp_bits_bridx,
  output [31:0] io_resp_bits_target,
  output [4:0]  io_resp_bits_entry,
  output [7:0]  io_resp_bits_bht_history,
  output        io_resp_bits_bht_value,
  input         io_btb_update_valid,
  input  [4:0]  io_btb_update_bits_prediction_entry,
  input  [31:0] io_btb_update_bits_pc,
  input         io_btb_update_bits_isValid,
  input  [31:0] io_btb_update_bits_br_pc,
  input  [1:0]  io_btb_update_bits_cfiType,
  input         io_bht_update_valid,
  input  [7:0]  io_bht_update_bits_prediction_history,
  input  [31:0] io_bht_update_bits_pc,
  input         io_bht_update_bits_branch,
  input         io_bht_update_bits_taken,
  input         io_bht_update_bits_mispredict,
  input         io_bht_advance_valid,
  input         io_bht_advance_bits_bht_value,
  input         io_ras_update_valid,
  input  [1:0]  io_ras_update_bits_cfiType,
  input  [31:0] io_ras_update_bits_returnAddr,
  output        io_ras_head_valid,
  output [31:0] io_ras_head_bits,
  input         io_flush
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [31:0] _RAND_33;
  reg [31:0] _RAND_34;
  reg [31:0] _RAND_35;
  reg [31:0] _RAND_36;
  reg [31:0] _RAND_37;
  reg [31:0] _RAND_38;
  reg [31:0] _RAND_39;
  reg [31:0] _RAND_40;
  reg [31:0] _RAND_41;
  reg [31:0] _RAND_42;
  reg [31:0] _RAND_43;
  reg [31:0] _RAND_44;
  reg [31:0] _RAND_45;
  reg [31:0] _RAND_46;
  reg [31:0] _RAND_47;
  reg [31:0] _RAND_48;
  reg [31:0] _RAND_49;
  reg [31:0] _RAND_50;
  reg [31:0] _RAND_51;
  reg [31:0] _RAND_52;
  reg [31:0] _RAND_53;
  reg [31:0] _RAND_54;
  reg [31:0] _RAND_55;
  reg [31:0] _RAND_56;
  reg [31:0] _RAND_57;
  reg [31:0] _RAND_58;
  reg [31:0] _RAND_59;
  reg [31:0] _RAND_60;
  reg [31:0] _RAND_61;
  reg [31:0] _RAND_62;
  reg [31:0] _RAND_63;
  reg [31:0] _RAND_64;
  reg [31:0] _RAND_65;
  reg [31:0] _RAND_66;
  reg [31:0] _RAND_67;
  reg [31:0] _RAND_68;
  reg [31:0] _RAND_69;
  reg [31:0] _RAND_70;
  reg [31:0] _RAND_71;
  reg [31:0] _RAND_72;
  reg [31:0] _RAND_73;
  reg [31:0] _RAND_74;
  reg [31:0] _RAND_75;
  reg [31:0] _RAND_76;
  reg [31:0] _RAND_77;
  reg [31:0] _RAND_78;
  reg [31:0] _RAND_79;
  reg [31:0] _RAND_80;
  reg [31:0] _RAND_81;
  reg [31:0] _RAND_82;
  reg [31:0] _RAND_83;
  reg [31:0] _RAND_84;
  reg [31:0] _RAND_85;
  reg [31:0] _RAND_86;
  reg [31:0] _RAND_87;
  reg [31:0] _RAND_88;
  reg [31:0] _RAND_89;
  reg [31:0] _RAND_90;
  reg [31:0] _RAND_91;
  reg [31:0] _RAND_92;
  reg [31:0] _RAND_93;
  reg [31:0] _RAND_94;
  reg [31:0] _RAND_95;
  reg [31:0] _RAND_96;
  reg [31:0] _RAND_97;
  reg [31:0] _RAND_98;
  reg [31:0] _RAND_99;
  reg [31:0] _RAND_100;
  reg [31:0] _RAND_101;
  reg [31:0] _RAND_102;
  reg [31:0] _RAND_103;
  reg [31:0] _RAND_104;
  reg [31:0] _RAND_105;
  reg [31:0] _RAND_106;
  reg [31:0] _RAND_107;
  reg [31:0] _RAND_108;
  reg [31:0] _RAND_109;
  reg [31:0] _RAND_110;
  reg [31:0] _RAND_111;
  reg [31:0] _RAND_112;
  reg [31:0] _RAND_113;
  reg [31:0] _RAND_114;
  reg [31:0] _RAND_115;
  reg [31:0] _RAND_116;
  reg [31:0] _RAND_117;
  reg [31:0] _RAND_118;
  reg [31:0] _RAND_119;
  reg [31:0] _RAND_120;
  reg [31:0] _RAND_121;
  reg [31:0] _RAND_122;
  reg [31:0] _RAND_123;
  reg [31:0] _RAND_124;
  reg [31:0] _RAND_125;
  reg [31:0] _RAND_126;
  reg [31:0] _RAND_127;
  reg [31:0] _RAND_128;
  reg [31:0] _RAND_129;
  reg [31:0] _RAND_130;
  reg [31:0] _RAND_131;
  reg [31:0] _RAND_132;
  reg [31:0] _RAND_133;
  reg [31:0] _RAND_134;
  reg [31:0] _RAND_135;
  reg [31:0] _RAND_136;
  reg [31:0] _RAND_137;
  reg [31:0] _RAND_138;
  reg [31:0] _RAND_139;
  reg [31:0] _RAND_140;
  reg [31:0] _RAND_141;
  reg [31:0] _RAND_142;
  reg [31:0] _RAND_143;
  reg [31:0] _RAND_144;
  reg [31:0] _RAND_145;
  reg [31:0] _RAND_146;
  reg [31:0] _RAND_147;
  reg [31:0] _RAND_148;
  reg [31:0] _RAND_149;
  reg [31:0] _RAND_150;
  reg [31:0] _RAND_151;
  reg [31:0] _RAND_152;
  reg [31:0] _RAND_153;
  reg [31:0] _RAND_154;
  reg [31:0] _RAND_155;
  reg [31:0] _RAND_156;
  reg [31:0] _RAND_157;
  reg [31:0] _RAND_158;
  reg [31:0] _RAND_159;
  reg [31:0] _RAND_160;
  reg [31:0] _RAND_161;
  reg [31:0] _RAND_162;
  reg [31:0] _RAND_163;
  reg [31:0] _RAND_164;
  reg [31:0] _RAND_165;
  reg [31:0] _RAND_166;
  reg [31:0] _RAND_167;
  reg [31:0] _RAND_168;
  reg [31:0] _RAND_169;
  reg [31:0] _RAND_170;
  reg [31:0] _RAND_171;
  reg [31:0] _RAND_172;
  reg [31:0] _RAND_173;
  reg [31:0] _RAND_174;
  reg [31:0] _RAND_175;
  reg [31:0] _RAND_176;
  reg [31:0] _RAND_177;
  reg [31:0] _RAND_178;
  reg [31:0] _RAND_179;
  reg [31:0] _RAND_180;
  reg [31:0] _RAND_181;
  reg [31:0] _RAND_182;
  reg [31:0] _RAND_183;
  reg [31:0] _RAND_184;
  reg [31:0] _RAND_185;
  reg [31:0] _RAND_186;
  reg [31:0] _RAND_187;
  reg [31:0] _RAND_188;
  reg [31:0] _RAND_189;
  reg [31:0] _RAND_190;
  reg [31:0] _RAND_191;
  reg [31:0] _RAND_192;
  reg [31:0] _RAND_193;
  reg [31:0] _RAND_194;
  reg [31:0] _RAND_195;
  reg [31:0] _RAND_196;
  reg [31:0] _RAND_197;
`endif // RANDOMIZE_REG_INIT
  reg  table_ [0:511]; // @[BTB.scala 118:26]
  wire  table__res_res_value_MPORT_en; // @[BTB.scala 118:26]
  wire [8:0] table__res_res_value_MPORT_addr; // @[BTB.scala 118:26]
  wire  table__res_res_value_MPORT_data; // @[BTB.scala 118:26]
  wire  table__MPORT_data; // @[BTB.scala 118:26]
  wire [8:0] table__MPORT_addr; // @[BTB.scala 118:26]
  wire  table__MPORT_mask; // @[BTB.scala 118:26]
  wire  table__MPORT_en; // @[BTB.scala 118:26]
  reg [12:0] idxs_0; // @[BTB.scala 201:17]
  reg [12:0] idxs_1; // @[BTB.scala 201:17]
  reg [12:0] idxs_2; // @[BTB.scala 201:17]
  reg [12:0] idxs_3; // @[BTB.scala 201:17]
  reg [12:0] idxs_4; // @[BTB.scala 201:17]
  reg [12:0] idxs_5; // @[BTB.scala 201:17]
  reg [12:0] idxs_6; // @[BTB.scala 201:17]
  reg [12:0] idxs_7; // @[BTB.scala 201:17]
  reg [12:0] idxs_8; // @[BTB.scala 201:17]
  reg [12:0] idxs_9; // @[BTB.scala 201:17]
  reg [12:0] idxs_10; // @[BTB.scala 201:17]
  reg [12:0] idxs_11; // @[BTB.scala 201:17]
  reg [12:0] idxs_12; // @[BTB.scala 201:17]
  reg [12:0] idxs_13; // @[BTB.scala 201:17]
  reg [12:0] idxs_14; // @[BTB.scala 201:17]
  reg [12:0] idxs_15; // @[BTB.scala 201:17]
  reg [12:0] idxs_16; // @[BTB.scala 201:17]
  reg [12:0] idxs_17; // @[BTB.scala 201:17]
  reg [12:0] idxs_18; // @[BTB.scala 201:17]
  reg [12:0] idxs_19; // @[BTB.scala 201:17]
  reg [12:0] idxs_20; // @[BTB.scala 201:17]
  reg [12:0] idxs_21; // @[BTB.scala 201:17]
  reg [12:0] idxs_22; // @[BTB.scala 201:17]
  reg [12:0] idxs_23; // @[BTB.scala 201:17]
  reg [12:0] idxs_24; // @[BTB.scala 201:17]
  reg [12:0] idxs_25; // @[BTB.scala 201:17]
  reg [12:0] idxs_26; // @[BTB.scala 201:17]
  reg [12:0] idxs_27; // @[BTB.scala 201:17]
  reg [2:0] idxPages_0; // @[BTB.scala 202:21]
  reg [2:0] idxPages_1; // @[BTB.scala 202:21]
  reg [2:0] idxPages_2; // @[BTB.scala 202:21]
  reg [2:0] idxPages_3; // @[BTB.scala 202:21]
  reg [2:0] idxPages_4; // @[BTB.scala 202:21]
  reg [2:0] idxPages_5; // @[BTB.scala 202:21]
  reg [2:0] idxPages_6; // @[BTB.scala 202:21]
  reg [2:0] idxPages_7; // @[BTB.scala 202:21]
  reg [2:0] idxPages_8; // @[BTB.scala 202:21]
  reg [2:0] idxPages_9; // @[BTB.scala 202:21]
  reg [2:0] idxPages_10; // @[BTB.scala 202:21]
  reg [2:0] idxPages_11; // @[BTB.scala 202:21]
  reg [2:0] idxPages_12; // @[BTB.scala 202:21]
  reg [2:0] idxPages_13; // @[BTB.scala 202:21]
  reg [2:0] idxPages_14; // @[BTB.scala 202:21]
  reg [2:0] idxPages_15; // @[BTB.scala 202:21]
  reg [2:0] idxPages_16; // @[BTB.scala 202:21]
  reg [2:0] idxPages_17; // @[BTB.scala 202:21]
  reg [2:0] idxPages_18; // @[BTB.scala 202:21]
  reg [2:0] idxPages_19; // @[BTB.scala 202:21]
  reg [2:0] idxPages_20; // @[BTB.scala 202:21]
  reg [2:0] idxPages_21; // @[BTB.scala 202:21]
  reg [2:0] idxPages_22; // @[BTB.scala 202:21]
  reg [2:0] idxPages_23; // @[BTB.scala 202:21]
  reg [2:0] idxPages_24; // @[BTB.scala 202:21]
  reg [2:0] idxPages_25; // @[BTB.scala 202:21]
  reg [2:0] idxPages_26; // @[BTB.scala 202:21]
  reg [2:0] idxPages_27; // @[BTB.scala 202:21]
  reg [12:0] tgts_0; // @[BTB.scala 203:17]
  reg [12:0] tgts_1; // @[BTB.scala 203:17]
  reg [12:0] tgts_2; // @[BTB.scala 203:17]
  reg [12:0] tgts_3; // @[BTB.scala 203:17]
  reg [12:0] tgts_4; // @[BTB.scala 203:17]
  reg [12:0] tgts_5; // @[BTB.scala 203:17]
  reg [12:0] tgts_6; // @[BTB.scala 203:17]
  reg [12:0] tgts_7; // @[BTB.scala 203:17]
  reg [12:0] tgts_8; // @[BTB.scala 203:17]
  reg [12:0] tgts_9; // @[BTB.scala 203:17]
  reg [12:0] tgts_10; // @[BTB.scala 203:17]
  reg [12:0] tgts_11; // @[BTB.scala 203:17]
  reg [12:0] tgts_12; // @[BTB.scala 203:17]
  reg [12:0] tgts_13; // @[BTB.scala 203:17]
  reg [12:0] tgts_14; // @[BTB.scala 203:17]
  reg [12:0] tgts_15; // @[BTB.scala 203:17]
  reg [12:0] tgts_16; // @[BTB.scala 203:17]
  reg [12:0] tgts_17; // @[BTB.scala 203:17]
  reg [12:0] tgts_18; // @[BTB.scala 203:17]
  reg [12:0] tgts_19; // @[BTB.scala 203:17]
  reg [12:0] tgts_20; // @[BTB.scala 203:17]
  reg [12:0] tgts_21; // @[BTB.scala 203:17]
  reg [12:0] tgts_22; // @[BTB.scala 203:17]
  reg [12:0] tgts_23; // @[BTB.scala 203:17]
  reg [12:0] tgts_24; // @[BTB.scala 203:17]
  reg [12:0] tgts_25; // @[BTB.scala 203:17]
  reg [12:0] tgts_26; // @[BTB.scala 203:17]
  reg [12:0] tgts_27; // @[BTB.scala 203:17]
  reg [2:0] tgtPages_0; // @[BTB.scala 204:21]
  reg [2:0] tgtPages_1; // @[BTB.scala 204:21]
  reg [2:0] tgtPages_2; // @[BTB.scala 204:21]
  reg [2:0] tgtPages_3; // @[BTB.scala 204:21]
  reg [2:0] tgtPages_4; // @[BTB.scala 204:21]
  reg [2:0] tgtPages_5; // @[BTB.scala 204:21]
  reg [2:0] tgtPages_6; // @[BTB.scala 204:21]
  reg [2:0] tgtPages_7; // @[BTB.scala 204:21]
  reg [2:0] tgtPages_8; // @[BTB.scala 204:21]
  reg [2:0] tgtPages_9; // @[BTB.scala 204:21]
  reg [2:0] tgtPages_10; // @[BTB.scala 204:21]
  reg [2:0] tgtPages_11; // @[BTB.scala 204:21]
  reg [2:0] tgtPages_12; // @[BTB.scala 204:21]
  reg [2:0] tgtPages_13; // @[BTB.scala 204:21]
  reg [2:0] tgtPages_14; // @[BTB.scala 204:21]
  reg [2:0] tgtPages_15; // @[BTB.scala 204:21]
  reg [2:0] tgtPages_16; // @[BTB.scala 204:21]
  reg [2:0] tgtPages_17; // @[BTB.scala 204:21]
  reg [2:0] tgtPages_18; // @[BTB.scala 204:21]
  reg [2:0] tgtPages_19; // @[BTB.scala 204:21]
  reg [2:0] tgtPages_20; // @[BTB.scala 204:21]
  reg [2:0] tgtPages_21; // @[BTB.scala 204:21]
  reg [2:0] tgtPages_22; // @[BTB.scala 204:21]
  reg [2:0] tgtPages_23; // @[BTB.scala 204:21]
  reg [2:0] tgtPages_24; // @[BTB.scala 204:21]
  reg [2:0] tgtPages_25; // @[BTB.scala 204:21]
  reg [2:0] tgtPages_26; // @[BTB.scala 204:21]
  reg [2:0] tgtPages_27; // @[BTB.scala 204:21]
  reg [17:0] pages_0; // @[BTB.scala 205:18]
  reg [17:0] pages_1; // @[BTB.scala 205:18]
  reg [17:0] pages_2; // @[BTB.scala 205:18]
  reg [17:0] pages_3; // @[BTB.scala 205:18]
  reg [17:0] pages_4; // @[BTB.scala 205:18]
  reg [17:0] pages_5; // @[BTB.scala 205:18]
  reg [5:0] pageValid; // @[BTB.scala 206:22]
  wire [17:0] pagesMasked_0 = pageValid[0] ? pages_0 : 18'h0; // @[BTB.scala 207:75]
  wire [17:0] pagesMasked_1 = pageValid[1] ? pages_1 : 18'h0; // @[BTB.scala 207:75]
  wire [17:0] pagesMasked_2 = pageValid[2] ? pages_2 : 18'h0; // @[BTB.scala 207:75]
  wire [17:0] pagesMasked_3 = pageValid[3] ? pages_3 : 18'h0; // @[BTB.scala 207:75]
  wire [17:0] pagesMasked_4 = pageValid[4] ? pages_4 : 18'h0; // @[BTB.scala 207:75]
  wire [17:0] pagesMasked_5 = pageValid[5] ? pages_5 : 18'h0; // @[BTB.scala 207:75]
  reg [27:0] isValid; // @[BTB.scala 209:20]
  reg [1:0] cfiType_0; // @[BTB.scala 210:20]
  reg [1:0] cfiType_1; // @[BTB.scala 210:20]
  reg [1:0] cfiType_2; // @[BTB.scala 210:20]
  reg [1:0] cfiType_3; // @[BTB.scala 210:20]
  reg [1:0] cfiType_4; // @[BTB.scala 210:20]
  reg [1:0] cfiType_5; // @[BTB.scala 210:20]
  reg [1:0] cfiType_6; // @[BTB.scala 210:20]
  reg [1:0] cfiType_7; // @[BTB.scala 210:20]
  reg [1:0] cfiType_8; // @[BTB.scala 210:20]
  reg [1:0] cfiType_9; // @[BTB.scala 210:20]
  reg [1:0] cfiType_10; // @[BTB.scala 210:20]
  reg [1:0] cfiType_11; // @[BTB.scala 210:20]
  reg [1:0] cfiType_12; // @[BTB.scala 210:20]
  reg [1:0] cfiType_13; // @[BTB.scala 210:20]
  reg [1:0] cfiType_14; // @[BTB.scala 210:20]
  reg [1:0] cfiType_15; // @[BTB.scala 210:20]
  reg [1:0] cfiType_16; // @[BTB.scala 210:20]
  reg [1:0] cfiType_17; // @[BTB.scala 210:20]
  reg [1:0] cfiType_18; // @[BTB.scala 210:20]
  reg [1:0] cfiType_19; // @[BTB.scala 210:20]
  reg [1:0] cfiType_20; // @[BTB.scala 210:20]
  reg [1:0] cfiType_21; // @[BTB.scala 210:20]
  reg [1:0] cfiType_22; // @[BTB.scala 210:20]
  reg [1:0] cfiType_23; // @[BTB.scala 210:20]
  reg [1:0] cfiType_24; // @[BTB.scala 210:20]
  reg [1:0] cfiType_25; // @[BTB.scala 210:20]
  reg [1:0] cfiType_26; // @[BTB.scala 210:20]
  reg [1:0] cfiType_27; // @[BTB.scala 210:20]
  reg  brIdx_0; // @[BTB.scala 211:18]
  reg  brIdx_1; // @[BTB.scala 211:18]
  reg  brIdx_2; // @[BTB.scala 211:18]
  reg  brIdx_3; // @[BTB.scala 211:18]
  reg  brIdx_4; // @[BTB.scala 211:18]
  reg  brIdx_5; // @[BTB.scala 211:18]
  reg  brIdx_6; // @[BTB.scala 211:18]
  reg  brIdx_7; // @[BTB.scala 211:18]
  reg  brIdx_8; // @[BTB.scala 211:18]
  reg  brIdx_9; // @[BTB.scala 211:18]
  reg  brIdx_10; // @[BTB.scala 211:18]
  reg  brIdx_11; // @[BTB.scala 211:18]
  reg  brIdx_12; // @[BTB.scala 211:18]
  reg  brIdx_13; // @[BTB.scala 211:18]
  reg  brIdx_14; // @[BTB.scala 211:18]
  reg  brIdx_15; // @[BTB.scala 211:18]
  reg  brIdx_16; // @[BTB.scala 211:18]
  reg  brIdx_17; // @[BTB.scala 211:18]
  reg  brIdx_18; // @[BTB.scala 211:18]
  reg  brIdx_19; // @[BTB.scala 211:18]
  reg  brIdx_20; // @[BTB.scala 211:18]
  reg  brIdx_21; // @[BTB.scala 211:18]
  reg  brIdx_22; // @[BTB.scala 211:18]
  reg  brIdx_23; // @[BTB.scala 211:18]
  reg  brIdx_24; // @[BTB.scala 211:18]
  reg  brIdx_25; // @[BTB.scala 211:18]
  reg  brIdx_26; // @[BTB.scala 211:18]
  reg  brIdx_27; // @[BTB.scala 211:18]
  reg  r_btb_updatePipe_valid; // @[Valid.scala 127:22]
  reg [4:0] r_btb_updatePipe_bits_prediction_entry; // @[Reg.scala 16:16]
  reg [31:0] r_btb_updatePipe_bits_pc; // @[Reg.scala 16:16]
  reg  r_btb_updatePipe_bits_isValid; // @[Reg.scala 16:16]
  reg [31:0] r_btb_updatePipe_bits_br_pc; // @[Reg.scala 16:16]
  reg [1:0] r_btb_updatePipe_bits_cfiType; // @[Reg.scala 16:16]
  wire [17:0] pageHit_p = io_req_bits_addr[31:14]; // @[BTB.scala 213:39]
  wire  _pageHit_T = pages_0 == pageHit_p; // @[BTB.scala 216:29]
  wire  _pageHit_T_1 = pages_1 == pageHit_p; // @[BTB.scala 216:29]
  wire  _pageHit_T_2 = pages_2 == pageHit_p; // @[BTB.scala 216:29]
  wire  _pageHit_T_3 = pages_3 == pageHit_p; // @[BTB.scala 216:29]
  wire  _pageHit_T_4 = pages_4 == pageHit_p; // @[BTB.scala 216:29]
  wire  _pageHit_T_5 = pages_5 == pageHit_p; // @[BTB.scala 216:29]
  wire [5:0] _pageHit_T_6 = {_pageHit_T_5,_pageHit_T_4,_pageHit_T_3,_pageHit_T_2,_pageHit_T_1,_pageHit_T}; // @[Cat.scala 31:58]
  wire [5:0] pageHit = pageValid & _pageHit_T_6; // @[BTB.scala 216:15]
  wire [12:0] idxHit_idx = io_req_bits_addr[13:1]; // @[BTB.scala 219:19]
  wire  _idxHit_T = idxs_0 == idxHit_idx; // @[BTB.scala 220:16]
  wire  _idxHit_T_1 = idxs_1 == idxHit_idx; // @[BTB.scala 220:16]
  wire  _idxHit_T_2 = idxs_2 == idxHit_idx; // @[BTB.scala 220:16]
  wire  _idxHit_T_3 = idxs_3 == idxHit_idx; // @[BTB.scala 220:16]
  wire  _idxHit_T_4 = idxs_4 == idxHit_idx; // @[BTB.scala 220:16]
  wire  _idxHit_T_5 = idxs_5 == idxHit_idx; // @[BTB.scala 220:16]
  wire  _idxHit_T_6 = idxs_6 == idxHit_idx; // @[BTB.scala 220:16]
  wire  _idxHit_T_7 = idxs_7 == idxHit_idx; // @[BTB.scala 220:16]
  wire  _idxHit_T_8 = idxs_8 == idxHit_idx; // @[BTB.scala 220:16]
  wire  _idxHit_T_9 = idxs_9 == idxHit_idx; // @[BTB.scala 220:16]
  wire  _idxHit_T_10 = idxs_10 == idxHit_idx; // @[BTB.scala 220:16]
  wire  _idxHit_T_11 = idxs_11 == idxHit_idx; // @[BTB.scala 220:16]
  wire  _idxHit_T_12 = idxs_12 == idxHit_idx; // @[BTB.scala 220:16]
  wire  _idxHit_T_13 = idxs_13 == idxHit_idx; // @[BTB.scala 220:16]
  wire  _idxHit_T_14 = idxs_14 == idxHit_idx; // @[BTB.scala 220:16]
  wire  _idxHit_T_15 = idxs_15 == idxHit_idx; // @[BTB.scala 220:16]
  wire  _idxHit_T_16 = idxs_16 == idxHit_idx; // @[BTB.scala 220:16]
  wire  _idxHit_T_17 = idxs_17 == idxHit_idx; // @[BTB.scala 220:16]
  wire  _idxHit_T_18 = idxs_18 == idxHit_idx; // @[BTB.scala 220:16]
  wire  _idxHit_T_19 = idxs_19 == idxHit_idx; // @[BTB.scala 220:16]
  wire  _idxHit_T_20 = idxs_20 == idxHit_idx; // @[BTB.scala 220:16]
  wire  _idxHit_T_21 = idxs_21 == idxHit_idx; // @[BTB.scala 220:16]
  wire  _idxHit_T_22 = idxs_22 == idxHit_idx; // @[BTB.scala 220:16]
  wire  _idxHit_T_23 = idxs_23 == idxHit_idx; // @[BTB.scala 220:16]
  wire  _idxHit_T_24 = idxs_24 == idxHit_idx; // @[BTB.scala 220:16]
  wire  _idxHit_T_25 = idxs_25 == idxHit_idx; // @[BTB.scala 220:16]
  wire  _idxHit_T_26 = idxs_26 == idxHit_idx; // @[BTB.scala 220:16]
  wire  _idxHit_T_27 = idxs_27 == idxHit_idx; // @[BTB.scala 220:16]
  wire [6:0] idxHit_lo_lo = {_idxHit_T_6,_idxHit_T_5,_idxHit_T_4,_idxHit_T_3,_idxHit_T_2,_idxHit_T_1,_idxHit_T}; // @[Cat.scala 31:58]
  wire [13:0] idxHit_lo = {_idxHit_T_13,_idxHit_T_12,_idxHit_T_11,_idxHit_T_10,_idxHit_T_9,_idxHit_T_8,_idxHit_T_7,
    idxHit_lo_lo}; // @[Cat.scala 31:58]
  wire [6:0] idxHit_hi_lo = {_idxHit_T_20,_idxHit_T_19,_idxHit_T_18,_idxHit_T_17,_idxHit_T_16,_idxHit_T_15,_idxHit_T_14}
    ; // @[Cat.scala 31:58]
  wire [27:0] _idxHit_T_28 = {_idxHit_T_27,_idxHit_T_26,_idxHit_T_25,_idxHit_T_24,_idxHit_T_23,_idxHit_T_22,_idxHit_T_21
    ,idxHit_hi_lo,idxHit_lo}; // @[Cat.scala 31:58]
  wire [27:0] idxHit = _idxHit_T_28 & isValid; // @[BTB.scala 220:32]
  wire [17:0] updatePageHit_p = r_btb_updatePipe_bits_pc[31:14]; // @[BTB.scala 213:39]
  wire  _updatePageHit_T = pages_0 == updatePageHit_p; // @[BTB.scala 216:29]
  wire  _updatePageHit_T_1 = pages_1 == updatePageHit_p; // @[BTB.scala 216:29]
  wire  _updatePageHit_T_2 = pages_2 == updatePageHit_p; // @[BTB.scala 216:29]
  wire  _updatePageHit_T_3 = pages_3 == updatePageHit_p; // @[BTB.scala 216:29]
  wire  _updatePageHit_T_4 = pages_4 == updatePageHit_p; // @[BTB.scala 216:29]
  wire  _updatePageHit_T_5 = pages_5 == updatePageHit_p; // @[BTB.scala 216:29]
  wire [5:0] _updatePageHit_T_6 = {_updatePageHit_T_5,_updatePageHit_T_4,_updatePageHit_T_3,_updatePageHit_T_2,
    _updatePageHit_T_1,_updatePageHit_T}; // @[Cat.scala 31:58]
  wire [5:0] updatePageHit = pageValid & _updatePageHit_T_6; // @[BTB.scala 216:15]
  wire  updateHit = r_btb_updatePipe_bits_prediction_entry < 5'h1c; // @[BTB.scala 234:48]
  wire  useUpdatePageHit = |updatePageHit; // @[BTB.scala 236:40]
  wire  usePageHit = |pageHit; // @[BTB.scala 237:28]
  wire  doIdxPageRepl = ~useUpdatePageHit; // @[BTB.scala 238:23]
  reg [2:0] nextPageRepl; // @[BTB.scala 239:29]
  wire [5:0] _idxPageRepl_T_2 = {pageHit[4:0],pageHit[5]}; // @[Cat.scala 31:58]
  wire [7:0] _idxPageRepl_T_3 = 8'h1 << nextPageRepl; // @[OneHot.scala 57:35]
  wire [7:0] _idxPageRepl_T_4 = usePageHit ? 8'h0 : _idxPageRepl_T_3; // @[BTB.scala 240:70]
  wire [7:0] _GEN_430 = {{2'd0}, _idxPageRepl_T_2}; // @[BTB.scala 240:65]
  wire [7:0] idxPageRepl = _GEN_430 | _idxPageRepl_T_4; // @[BTB.scala 240:65]
  wire [7:0] idxPageUpdateOH = useUpdatePageHit ? {{2'd0}, updatePageHit} : idxPageRepl; // @[BTB.scala 241:28]
  wire [3:0] idxPageUpdate_hi = idxPageUpdateOH[7:4]; // @[OneHot.scala 30:18]
  wire [3:0] idxPageUpdate_lo = idxPageUpdateOH[3:0]; // @[OneHot.scala 31:18]
  wire  _idxPageUpdate_T = |idxPageUpdate_hi; // @[OneHot.scala 32:14]
  wire [3:0] _idxPageUpdate_T_1 = idxPageUpdate_hi | idxPageUpdate_lo; // @[OneHot.scala 32:28]
  wire [1:0] idxPageUpdate_hi_1 = _idxPageUpdate_T_1[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] idxPageUpdate_lo_1 = _idxPageUpdate_T_1[1:0]; // @[OneHot.scala 31:18]
  wire  _idxPageUpdate_T_2 = |idxPageUpdate_hi_1; // @[OneHot.scala 32:14]
  wire [1:0] _idxPageUpdate_T_3 = idxPageUpdate_hi_1 | idxPageUpdate_lo_1; // @[OneHot.scala 32:28]
  wire [2:0] idxPageUpdate = {_idxPageUpdate_T,_idxPageUpdate_T_2,_idxPageUpdate_T_3[1]}; // @[Cat.scala 31:58]
  wire [7:0] idxPageReplEn = doIdxPageRepl ? idxPageRepl : 8'h0; // @[BTB.scala 243:26]
  wire  samePage = updatePageHit_p == pageHit_p; // @[BTB.scala 245:45]
  wire  doTgtPageRepl = ~samePage & ~usePageHit; // @[BTB.scala 246:33]
  wire [5:0] _tgtPageRepl_T_2 = {idxPageUpdateOH[4:0],idxPageUpdateOH[5]}; // @[Cat.scala 31:58]
  wire [7:0] tgtPageRepl = samePage ? idxPageUpdateOH : {{2'd0}, _tgtPageRepl_T_2}; // @[BTB.scala 247:24]
  wire [7:0] _tgtPageUpdate_T = usePageHit ? 8'h0 : tgtPageRepl; // @[BTB.scala 248:45]
  wire [7:0] _GEN_431 = {{2'd0}, pageHit}; // @[BTB.scala 248:40]
  wire [7:0] _tgtPageUpdate_T_1 = _GEN_431 | _tgtPageUpdate_T; // @[BTB.scala 248:40]
  wire [3:0] tgtPageUpdate_hi = _tgtPageUpdate_T_1[7:4]; // @[OneHot.scala 30:18]
  wire [3:0] tgtPageUpdate_lo = _tgtPageUpdate_T_1[3:0]; // @[OneHot.scala 31:18]
  wire  _tgtPageUpdate_T_2 = |tgtPageUpdate_hi; // @[OneHot.scala 32:14]
  wire [3:0] _tgtPageUpdate_T_3 = tgtPageUpdate_hi | tgtPageUpdate_lo; // @[OneHot.scala 32:28]
  wire [1:0] tgtPageUpdate_hi_1 = _tgtPageUpdate_T_3[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] tgtPageUpdate_lo_1 = _tgtPageUpdate_T_3[1:0]; // @[OneHot.scala 31:18]
  wire  _tgtPageUpdate_T_4 = |tgtPageUpdate_hi_1; // @[OneHot.scala 32:14]
  wire [1:0] _tgtPageUpdate_T_5 = tgtPageUpdate_hi_1 | tgtPageUpdate_lo_1; // @[OneHot.scala 32:28]
  wire [2:0] tgtPageUpdate = {_tgtPageUpdate_T_2,_tgtPageUpdate_T_4,_tgtPageUpdate_T_5[1]}; // @[Cat.scala 31:58]
  wire [7:0] tgtPageReplEn = doTgtPageRepl ? tgtPageRepl : 8'h0; // @[BTB.scala 249:26]
  wire  both = doIdxPageRepl & doTgtPageRepl; // @[BTB.scala 252:30]
  wire [1:0] _next_T = both ? 2'h2 : 2'h1; // @[BTB.scala 253:40]
  wire [2:0] _GEN_432 = {{1'd0}, _next_T}; // @[BTB.scala 253:29]
  wire [2:0] next = nextPageRepl + _GEN_432; // @[BTB.scala 253:29]
  reg [26:0] state_reg; // @[Replacement.scala 168:70]
  wire  waddr_left_subtree_older = state_reg[26]; // @[Replacement.scala 243:38]
  wire [10:0] waddr_left_subtree_state = state_reg[25:15]; // @[package.scala 154:13]
  wire [14:0] waddr_right_subtree_state = state_reg[14:0]; // @[Replacement.scala 245:38]
  wire  waddr_left_subtree_older_1 = waddr_left_subtree_state[10]; // @[Replacement.scala 243:38]
  wire [2:0] waddr_left_subtree_state_1 = waddr_left_subtree_state[9:7]; // @[package.scala 154:13]
  wire [6:0] waddr_right_subtree_state_1 = waddr_left_subtree_state[6:0]; // @[Replacement.scala 245:38]
  wire  waddr_left_subtree_older_2 = waddr_left_subtree_state_1[2]; // @[Replacement.scala 243:38]
  wire  waddr_left_subtree_state_2 = waddr_left_subtree_state_1[1]; // @[package.scala 154:13]
  wire  waddr_right_subtree_state_2 = waddr_left_subtree_state_1[0]; // @[Replacement.scala 245:38]
  wire  _waddr_T_2 = waddr_left_subtree_older_2 ? waddr_left_subtree_state_2 : waddr_right_subtree_state_2; // @[Replacement.scala 250:16]
  wire [1:0] _waddr_T_3 = {waddr_left_subtree_older_2,_waddr_T_2}; // @[Cat.scala 31:58]
  wire  waddr_left_subtree_older_3 = waddr_right_subtree_state_1[6]; // @[Replacement.scala 243:38]
  wire [2:0] waddr_left_subtree_state_3 = waddr_right_subtree_state_1[5:3]; // @[package.scala 154:13]
  wire [2:0] waddr_right_subtree_state_3 = waddr_right_subtree_state_1[2:0]; // @[Replacement.scala 245:38]
  wire  waddr_left_subtree_older_4 = waddr_left_subtree_state_3[2]; // @[Replacement.scala 243:38]
  wire  waddr_left_subtree_state_4 = waddr_left_subtree_state_3[1]; // @[package.scala 154:13]
  wire  waddr_right_subtree_state_4 = waddr_left_subtree_state_3[0]; // @[Replacement.scala 245:38]
  wire  _waddr_T_6 = waddr_left_subtree_older_4 ? waddr_left_subtree_state_4 : waddr_right_subtree_state_4; // @[Replacement.scala 250:16]
  wire [1:0] _waddr_T_7 = {waddr_left_subtree_older_4,_waddr_T_6}; // @[Cat.scala 31:58]
  wire  waddr_left_subtree_older_5 = waddr_right_subtree_state_3[2]; // @[Replacement.scala 243:38]
  wire  waddr_left_subtree_state_5 = waddr_right_subtree_state_3[1]; // @[package.scala 154:13]
  wire  waddr_right_subtree_state_5 = waddr_right_subtree_state_3[0]; // @[Replacement.scala 245:38]
  wire  _waddr_T_10 = waddr_left_subtree_older_5 ? waddr_left_subtree_state_5 : waddr_right_subtree_state_5; // @[Replacement.scala 250:16]
  wire [1:0] _waddr_T_11 = {waddr_left_subtree_older_5,_waddr_T_10}; // @[Cat.scala 31:58]
  wire [1:0] _waddr_T_12 = waddr_left_subtree_older_3 ? _waddr_T_7 : _waddr_T_11; // @[Replacement.scala 250:16]
  wire [2:0] _waddr_T_13 = {waddr_left_subtree_older_3,_waddr_T_12}; // @[Cat.scala 31:58]
  wire [2:0] _waddr_T_14 = waddr_left_subtree_older_1 ? {{1'd0}, _waddr_T_3} : _waddr_T_13; // @[Replacement.scala 250:16]
  wire [3:0] _waddr_T_15 = {waddr_left_subtree_older_1,_waddr_T_14}; // @[Cat.scala 31:58]
  wire  waddr_left_subtree_older_6 = waddr_right_subtree_state[14]; // @[Replacement.scala 243:38]
  wire [6:0] waddr_left_subtree_state_6 = waddr_right_subtree_state[13:7]; // @[package.scala 154:13]
  wire [6:0] waddr_right_subtree_state_6 = waddr_right_subtree_state[6:0]; // @[Replacement.scala 245:38]
  wire  waddr_left_subtree_older_7 = waddr_left_subtree_state_6[6]; // @[Replacement.scala 243:38]
  wire [2:0] waddr_left_subtree_state_7 = waddr_left_subtree_state_6[5:3]; // @[package.scala 154:13]
  wire [2:0] waddr_right_subtree_state_7 = waddr_left_subtree_state_6[2:0]; // @[Replacement.scala 245:38]
  wire  waddr_left_subtree_older_8 = waddr_left_subtree_state_7[2]; // @[Replacement.scala 243:38]
  wire  waddr_left_subtree_state_8 = waddr_left_subtree_state_7[1]; // @[package.scala 154:13]
  wire  waddr_right_subtree_state_8 = waddr_left_subtree_state_7[0]; // @[Replacement.scala 245:38]
  wire  _waddr_T_18 = waddr_left_subtree_older_8 ? waddr_left_subtree_state_8 : waddr_right_subtree_state_8; // @[Replacement.scala 250:16]
  wire [1:0] _waddr_T_19 = {waddr_left_subtree_older_8,_waddr_T_18}; // @[Cat.scala 31:58]
  wire  waddr_left_subtree_older_9 = waddr_right_subtree_state_7[2]; // @[Replacement.scala 243:38]
  wire  waddr_left_subtree_state_9 = waddr_right_subtree_state_7[1]; // @[package.scala 154:13]
  wire  waddr_right_subtree_state_9 = waddr_right_subtree_state_7[0]; // @[Replacement.scala 245:38]
  wire  _waddr_T_22 = waddr_left_subtree_older_9 ? waddr_left_subtree_state_9 : waddr_right_subtree_state_9; // @[Replacement.scala 250:16]
  wire [1:0] _waddr_T_23 = {waddr_left_subtree_older_9,_waddr_T_22}; // @[Cat.scala 31:58]
  wire [1:0] _waddr_T_24 = waddr_left_subtree_older_7 ? _waddr_T_19 : _waddr_T_23; // @[Replacement.scala 250:16]
  wire [2:0] _waddr_T_25 = {waddr_left_subtree_older_7,_waddr_T_24}; // @[Cat.scala 31:58]
  wire  waddr_left_subtree_older_10 = waddr_right_subtree_state_6[6]; // @[Replacement.scala 243:38]
  wire [2:0] waddr_left_subtree_state_10 = waddr_right_subtree_state_6[5:3]; // @[package.scala 154:13]
  wire [2:0] waddr_right_subtree_state_10 = waddr_right_subtree_state_6[2:0]; // @[Replacement.scala 245:38]
  wire  waddr_left_subtree_older_11 = waddr_left_subtree_state_10[2]; // @[Replacement.scala 243:38]
  wire  waddr_left_subtree_state_11 = waddr_left_subtree_state_10[1]; // @[package.scala 154:13]
  wire  waddr_right_subtree_state_11 = waddr_left_subtree_state_10[0]; // @[Replacement.scala 245:38]
  wire  _waddr_T_28 = waddr_left_subtree_older_11 ? waddr_left_subtree_state_11 : waddr_right_subtree_state_11; // @[Replacement.scala 250:16]
  wire [1:0] _waddr_T_29 = {waddr_left_subtree_older_11,_waddr_T_28}; // @[Cat.scala 31:58]
  wire  waddr_left_subtree_older_12 = waddr_right_subtree_state_10[2]; // @[Replacement.scala 243:38]
  wire  waddr_left_subtree_state_12 = waddr_right_subtree_state_10[1]; // @[package.scala 154:13]
  wire  waddr_right_subtree_state_12 = waddr_right_subtree_state_10[0]; // @[Replacement.scala 245:38]
  wire  _waddr_T_32 = waddr_left_subtree_older_12 ? waddr_left_subtree_state_12 : waddr_right_subtree_state_12; // @[Replacement.scala 250:16]
  wire [1:0] _waddr_T_33 = {waddr_left_subtree_older_12,_waddr_T_32}; // @[Cat.scala 31:58]
  wire [1:0] _waddr_T_34 = waddr_left_subtree_older_10 ? _waddr_T_29 : _waddr_T_33; // @[Replacement.scala 250:16]
  wire [2:0] _waddr_T_35 = {waddr_left_subtree_older_10,_waddr_T_34}; // @[Cat.scala 31:58]
  wire [2:0] _waddr_T_36 = waddr_left_subtree_older_6 ? _waddr_T_25 : _waddr_T_35; // @[Replacement.scala 250:16]
  wire [3:0] _waddr_T_37 = {waddr_left_subtree_older_6,_waddr_T_36}; // @[Cat.scala 31:58]
  wire [3:0] _waddr_T_38 = waddr_left_subtree_older ? _waddr_T_15 : _waddr_T_37; // @[Replacement.scala 250:16]
  wire [4:0] _waddr_T_39 = {waddr_left_subtree_older,_waddr_T_38}; // @[Cat.scala 31:58]
  wire [4:0] waddr = updateHit ? r_btb_updatePipe_bits_prediction_entry : _waddr_T_39; // @[BTB.scala 258:18]
  reg  r_respPipe_valid; // @[Valid.scala 127:22]
  reg  r_respPipe_bits_taken; // @[Reg.scala 16:16]
  reg [4:0] r_respPipe_bits_entry; // @[Reg.scala 16:16]
  wire [4:0] state_reg_touch_way_sized = r_btb_updatePipe_valid ? waddr : r_respPipe_bits_entry; // @[BTB.scala 261:20]
  wire  state_reg_set_left_older = ~state_reg_touch_way_sized[4]; // @[Replacement.scala 196:33]
  wire  state_reg_set_left_older_1 = ~state_reg_touch_way_sized[3]; // @[Replacement.scala 196:33]
  wire  state_reg_set_left_older_2 = ~state_reg_touch_way_sized[1]; // @[Replacement.scala 196:33]
  wire  _state_reg_T_4 = ~state_reg_touch_way_sized[0]; // @[Replacement.scala 218:7]
  wire  _state_reg_T_5 = state_reg_set_left_older_2 ? waddr_left_subtree_state_2 : _state_reg_T_4; // @[Replacement.scala 203:16]
  wire  _state_reg_T_9 = state_reg_set_left_older_2 ? _state_reg_T_4 : waddr_right_subtree_state_2; // @[Replacement.scala 206:16]
  wire [2:0] _state_reg_T_10 = {state_reg_set_left_older_2,_state_reg_T_5,_state_reg_T_9}; // @[Cat.scala 31:58]
  wire [2:0] _state_reg_T_11 = state_reg_set_left_older_1 ? waddr_left_subtree_state_1 : _state_reg_T_10; // @[Replacement.scala 203:16]
  wire  state_reg_set_left_older_3 = ~state_reg_touch_way_sized[2]; // @[Replacement.scala 196:33]
  wire  state_reg_set_left_older_4 = ~state_reg_touch_way_sized[1]; // @[Replacement.scala 196:33]
  wire  _state_reg_T_16 = ~state_reg_touch_way_sized[0]; // @[Replacement.scala 218:7]
  wire  _state_reg_T_17 = state_reg_set_left_older_4 ? waddr_left_subtree_state_4 : _state_reg_T_16; // @[Replacement.scala 203:16]
  wire  _state_reg_T_21 = state_reg_set_left_older_4 ? _state_reg_T_16 : waddr_right_subtree_state_4; // @[Replacement.scala 206:16]
  wire [2:0] _state_reg_T_22 = {state_reg_set_left_older_4,_state_reg_T_17,_state_reg_T_21}; // @[Cat.scala 31:58]
  wire [2:0] _state_reg_T_23 = state_reg_set_left_older_3 ? waddr_left_subtree_state_3 : _state_reg_T_22; // @[Replacement.scala 203:16]
  wire  _state_reg_T_28 = state_reg_set_left_older_4 ? waddr_left_subtree_state_5 : _state_reg_T_16; // @[Replacement.scala 203:16]
  wire  _state_reg_T_32 = state_reg_set_left_older_4 ? _state_reg_T_16 : waddr_right_subtree_state_5; // @[Replacement.scala 206:16]
  wire [2:0] _state_reg_T_33 = {state_reg_set_left_older_4,_state_reg_T_28,_state_reg_T_32}; // @[Cat.scala 31:58]
  wire [2:0] _state_reg_T_34 = state_reg_set_left_older_3 ? _state_reg_T_33 : waddr_right_subtree_state_3; // @[Replacement.scala 206:16]
  wire [6:0] _state_reg_T_35 = {state_reg_set_left_older_3,_state_reg_T_23,_state_reg_T_34}; // @[Cat.scala 31:58]
  wire [6:0] _state_reg_T_36 = state_reg_set_left_older_1 ? _state_reg_T_35 : waddr_right_subtree_state_1; // @[Replacement.scala 206:16]
  wire [10:0] _state_reg_T_37 = {state_reg_set_left_older_1,_state_reg_T_11,_state_reg_T_36}; // @[Cat.scala 31:58]
  wire [10:0] _state_reg_T_38 = state_reg_set_left_older ? waddr_left_subtree_state : _state_reg_T_37; // @[Replacement.scala 203:16]
  wire  _state_reg_T_45 = state_reg_set_left_older_4 ? waddr_left_subtree_state_8 : _state_reg_T_16; // @[Replacement.scala 203:16]
  wire  _state_reg_T_49 = state_reg_set_left_older_4 ? _state_reg_T_16 : waddr_right_subtree_state_8; // @[Replacement.scala 206:16]
  wire [2:0] _state_reg_T_50 = {state_reg_set_left_older_4,_state_reg_T_45,_state_reg_T_49}; // @[Cat.scala 31:58]
  wire [2:0] _state_reg_T_51 = state_reg_set_left_older_3 ? waddr_left_subtree_state_7 : _state_reg_T_50; // @[Replacement.scala 203:16]
  wire  _state_reg_T_56 = state_reg_set_left_older_4 ? waddr_left_subtree_state_9 : _state_reg_T_16; // @[Replacement.scala 203:16]
  wire  _state_reg_T_60 = state_reg_set_left_older_4 ? _state_reg_T_16 : waddr_right_subtree_state_9; // @[Replacement.scala 206:16]
  wire [2:0] _state_reg_T_61 = {state_reg_set_left_older_4,_state_reg_T_56,_state_reg_T_60}; // @[Cat.scala 31:58]
  wire [2:0] _state_reg_T_62 = state_reg_set_left_older_3 ? _state_reg_T_61 : waddr_right_subtree_state_7; // @[Replacement.scala 206:16]
  wire [6:0] _state_reg_T_63 = {state_reg_set_left_older_3,_state_reg_T_51,_state_reg_T_62}; // @[Cat.scala 31:58]
  wire [6:0] _state_reg_T_64 = state_reg_set_left_older_1 ? waddr_left_subtree_state_6 : _state_reg_T_63; // @[Replacement.scala 203:16]
  wire  _state_reg_T_70 = state_reg_set_left_older_4 ? waddr_left_subtree_state_11 : _state_reg_T_16; // @[Replacement.scala 203:16]
  wire  _state_reg_T_74 = state_reg_set_left_older_4 ? _state_reg_T_16 : waddr_right_subtree_state_11; // @[Replacement.scala 206:16]
  wire [2:0] _state_reg_T_75 = {state_reg_set_left_older_4,_state_reg_T_70,_state_reg_T_74}; // @[Cat.scala 31:58]
  wire [2:0] _state_reg_T_76 = state_reg_set_left_older_3 ? waddr_left_subtree_state_10 : _state_reg_T_75; // @[Replacement.scala 203:16]
  wire  _state_reg_T_81 = state_reg_set_left_older_4 ? waddr_left_subtree_state_12 : _state_reg_T_16; // @[Replacement.scala 203:16]
  wire  _state_reg_T_85 = state_reg_set_left_older_4 ? _state_reg_T_16 : waddr_right_subtree_state_12; // @[Replacement.scala 206:16]
  wire [2:0] _state_reg_T_86 = {state_reg_set_left_older_4,_state_reg_T_81,_state_reg_T_85}; // @[Cat.scala 31:58]
  wire [2:0] _state_reg_T_87 = state_reg_set_left_older_3 ? _state_reg_T_86 : waddr_right_subtree_state_10; // @[Replacement.scala 206:16]
  wire [6:0] _state_reg_T_88 = {state_reg_set_left_older_3,_state_reg_T_76,_state_reg_T_87}; // @[Cat.scala 31:58]
  wire [6:0] _state_reg_T_89 = state_reg_set_left_older_1 ? _state_reg_T_88 : waddr_right_subtree_state_6; // @[Replacement.scala 206:16]
  wire [14:0] _state_reg_T_90 = {state_reg_set_left_older_1,_state_reg_T_64,_state_reg_T_89}; // @[Cat.scala 31:58]
  wire [14:0] _state_reg_T_91 = state_reg_set_left_older ? _state_reg_T_90 : waddr_right_subtree_state; // @[Replacement.scala 206:16]
  wire [26:0] _state_reg_T_92 = {state_reg_set_left_older,_state_reg_T_38,_state_reg_T_91}; // @[Cat.scala 31:58]
  wire [31:0] mask = 32'h1 << waddr; // @[OneHot.scala 57:35]
  wire [3:0] _idxPages_T = idxPageUpdate + 3'h1; // @[BTB.scala 268:38]
  wire [31:0] _GEN_433 = {{4'd0}, isValid}; // @[BTB.scala 271:55]
  wire [31:0] _isValid_T = _GEN_433 | mask; // @[BTB.scala 271:55]
  wire [31:0] _isValid_T_1 = ~mask; // @[BTB.scala 271:73]
  wire [31:0] _isValid_T_2 = _GEN_433 & _isValid_T_1; // @[BTB.scala 271:71]
  wire [31:0] _isValid_T_3 = r_btb_updatePipe_bits_isValid ? _isValid_T : _isValid_T_2; // @[BTB.scala 271:19]
  wire  idxWritesEven = ~idxPageUpdate[0]; // @[BTB.scala 276:25]
  wire [7:0] _T_5 = idxWritesEven ? idxPageReplEn : tgtPageReplEn; // @[BTB.scala 282:24]
  wire [7:0] _T_12 = idxWritesEven ? tgtPageReplEn : idxPageReplEn; // @[BTB.scala 284:24]
  wire [7:0] _GEN_435 = {{2'd0}, pageValid}; // @[BTB.scala 286:28]
  wire [7:0] _pageValid_T = _GEN_435 | tgtPageReplEn; // @[BTB.scala 286:28]
  wire [7:0] _pageValid_T_1 = _pageValid_T | idxPageReplEn; // @[BTB.scala 286:44]
  wire [31:0] _GEN_338 = r_btb_updatePipe_valid ? _isValid_T_3 : {{4'd0}, isValid}; // @[BTB.scala 264:29 271:13 209:20]
  wire [7:0] _GEN_373 = r_btb_updatePipe_valid ? _pageValid_T_1 : {{2'd0}, pageValid}; // @[BTB.scala 264:29 286:15 206:22]
  wire [6:0] _io_resp_valid_T = {pageHit, 1'h0}; // @[BTB.scala 289:29]
  wire [2:0] _io_resp_valid_T_29 = idxHit[0] ? idxPages_0 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_30 = idxHit[1] ? idxPages_1 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_31 = idxHit[2] ? idxPages_2 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_32 = idxHit[3] ? idxPages_3 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_33 = idxHit[4] ? idxPages_4 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_34 = idxHit[5] ? idxPages_5 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_35 = idxHit[6] ? idxPages_6 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_36 = idxHit[7] ? idxPages_7 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_37 = idxHit[8] ? idxPages_8 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_38 = idxHit[9] ? idxPages_9 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_39 = idxHit[10] ? idxPages_10 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_40 = idxHit[11] ? idxPages_11 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_41 = idxHit[12] ? idxPages_12 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_42 = idxHit[13] ? idxPages_13 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_43 = idxHit[14] ? idxPages_14 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_44 = idxHit[15] ? idxPages_15 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_45 = idxHit[16] ? idxPages_16 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_46 = idxHit[17] ? idxPages_17 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_47 = idxHit[18] ? idxPages_18 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_48 = idxHit[19] ? idxPages_19 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_49 = idxHit[20] ? idxPages_20 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_50 = idxHit[21] ? idxPages_21 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_51 = idxHit[22] ? idxPages_22 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_52 = idxHit[23] ? idxPages_23 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_53 = idxHit[24] ? idxPages_24 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_54 = idxHit[25] ? idxPages_25 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_55 = idxHit[26] ? idxPages_26 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_56 = idxHit[27] ? idxPages_27 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_57 = _io_resp_valid_T_29 | _io_resp_valid_T_30; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_58 = _io_resp_valid_T_57 | _io_resp_valid_T_31; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_59 = _io_resp_valid_T_58 | _io_resp_valid_T_32; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_60 = _io_resp_valid_T_59 | _io_resp_valid_T_33; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_61 = _io_resp_valid_T_60 | _io_resp_valid_T_34; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_62 = _io_resp_valid_T_61 | _io_resp_valid_T_35; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_63 = _io_resp_valid_T_62 | _io_resp_valid_T_36; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_64 = _io_resp_valid_T_63 | _io_resp_valid_T_37; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_65 = _io_resp_valid_T_64 | _io_resp_valid_T_38; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_66 = _io_resp_valid_T_65 | _io_resp_valid_T_39; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_67 = _io_resp_valid_T_66 | _io_resp_valid_T_40; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_68 = _io_resp_valid_T_67 | _io_resp_valid_T_41; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_69 = _io_resp_valid_T_68 | _io_resp_valid_T_42; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_70 = _io_resp_valid_T_69 | _io_resp_valid_T_43; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_71 = _io_resp_valid_T_70 | _io_resp_valid_T_44; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_72 = _io_resp_valid_T_71 | _io_resp_valid_T_45; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_73 = _io_resp_valid_T_72 | _io_resp_valid_T_46; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_74 = _io_resp_valid_T_73 | _io_resp_valid_T_47; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_75 = _io_resp_valid_T_74 | _io_resp_valid_T_48; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_76 = _io_resp_valid_T_75 | _io_resp_valid_T_49; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_77 = _io_resp_valid_T_76 | _io_resp_valid_T_50; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_78 = _io_resp_valid_T_77 | _io_resp_valid_T_51; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_79 = _io_resp_valid_T_78 | _io_resp_valid_T_52; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_80 = _io_resp_valid_T_79 | _io_resp_valid_T_53; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_81 = _io_resp_valid_T_80 | _io_resp_valid_T_54; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_82 = _io_resp_valid_T_81 | _io_resp_valid_T_55; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_valid_T_83 = _io_resp_valid_T_82 | _io_resp_valid_T_56; // @[Mux.scala 27:73]
  wire [6:0] _io_resp_valid_T_84 = _io_resp_valid_T >> _io_resp_valid_T_83; // @[BTB.scala 289:34]
  wire [2:0] _io_resp_bits_target_T_28 = idxHit[0] ? tgtPages_0 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_29 = idxHit[1] ? tgtPages_1 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_30 = idxHit[2] ? tgtPages_2 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_31 = idxHit[3] ? tgtPages_3 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_32 = idxHit[4] ? tgtPages_4 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_33 = idxHit[5] ? tgtPages_5 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_34 = idxHit[6] ? tgtPages_6 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_35 = idxHit[7] ? tgtPages_7 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_36 = idxHit[8] ? tgtPages_8 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_37 = idxHit[9] ? tgtPages_9 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_38 = idxHit[10] ? tgtPages_10 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_39 = idxHit[11] ? tgtPages_11 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_40 = idxHit[12] ? tgtPages_12 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_41 = idxHit[13] ? tgtPages_13 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_42 = idxHit[14] ? tgtPages_14 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_43 = idxHit[15] ? tgtPages_15 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_44 = idxHit[16] ? tgtPages_16 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_45 = idxHit[17] ? tgtPages_17 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_46 = idxHit[18] ? tgtPages_18 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_47 = idxHit[19] ? tgtPages_19 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_48 = idxHit[20] ? tgtPages_20 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_49 = idxHit[21] ? tgtPages_21 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_50 = idxHit[22] ? tgtPages_22 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_51 = idxHit[23] ? tgtPages_23 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_52 = idxHit[24] ? tgtPages_24 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_53 = idxHit[25] ? tgtPages_25 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_54 = idxHit[26] ? tgtPages_26 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_55 = idxHit[27] ? tgtPages_27 : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_56 = _io_resp_bits_target_T_28 | _io_resp_bits_target_T_29; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_57 = _io_resp_bits_target_T_56 | _io_resp_bits_target_T_30; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_58 = _io_resp_bits_target_T_57 | _io_resp_bits_target_T_31; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_59 = _io_resp_bits_target_T_58 | _io_resp_bits_target_T_32; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_60 = _io_resp_bits_target_T_59 | _io_resp_bits_target_T_33; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_61 = _io_resp_bits_target_T_60 | _io_resp_bits_target_T_34; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_62 = _io_resp_bits_target_T_61 | _io_resp_bits_target_T_35; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_63 = _io_resp_bits_target_T_62 | _io_resp_bits_target_T_36; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_64 = _io_resp_bits_target_T_63 | _io_resp_bits_target_T_37; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_65 = _io_resp_bits_target_T_64 | _io_resp_bits_target_T_38; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_66 = _io_resp_bits_target_T_65 | _io_resp_bits_target_T_39; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_67 = _io_resp_bits_target_T_66 | _io_resp_bits_target_T_40; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_68 = _io_resp_bits_target_T_67 | _io_resp_bits_target_T_41; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_69 = _io_resp_bits_target_T_68 | _io_resp_bits_target_T_42; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_70 = _io_resp_bits_target_T_69 | _io_resp_bits_target_T_43; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_71 = _io_resp_bits_target_T_70 | _io_resp_bits_target_T_44; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_72 = _io_resp_bits_target_T_71 | _io_resp_bits_target_T_45; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_73 = _io_resp_bits_target_T_72 | _io_resp_bits_target_T_46; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_74 = _io_resp_bits_target_T_73 | _io_resp_bits_target_T_47; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_75 = _io_resp_bits_target_T_74 | _io_resp_bits_target_T_48; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_76 = _io_resp_bits_target_T_75 | _io_resp_bits_target_T_49; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_77 = _io_resp_bits_target_T_76 | _io_resp_bits_target_T_50; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_78 = _io_resp_bits_target_T_77 | _io_resp_bits_target_T_51; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_79 = _io_resp_bits_target_T_78 | _io_resp_bits_target_T_52; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_80 = _io_resp_bits_target_T_79 | _io_resp_bits_target_T_53; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_81 = _io_resp_bits_target_T_80 | _io_resp_bits_target_T_54; // @[Mux.scala 27:73]
  wire [2:0] _io_resp_bits_target_T_82 = _io_resp_bits_target_T_81 | _io_resp_bits_target_T_55; // @[Mux.scala 27:73]
  wire [17:0] _io_resp_bits_target_T_84 = _io_resp_bits_target_T_82 == 3'h1 ? pagesMasked_1 : pagesMasked_0; // @[package.scala 32:76]
  wire [17:0] _io_resp_bits_target_T_86 = _io_resp_bits_target_T_82 == 3'h2 ? pagesMasked_2 : _io_resp_bits_target_T_84; // @[package.scala 32:76]
  wire [17:0] _io_resp_bits_target_T_88 = _io_resp_bits_target_T_82 == 3'h3 ? pagesMasked_3 : _io_resp_bits_target_T_86; // @[package.scala 32:76]
  wire [17:0] _io_resp_bits_target_T_90 = _io_resp_bits_target_T_82 == 3'h4 ? pagesMasked_4 : _io_resp_bits_target_T_88; // @[package.scala 32:76]
  wire [17:0] _io_resp_bits_target_T_92 = _io_resp_bits_target_T_82 == 3'h5 ? pagesMasked_5 : _io_resp_bits_target_T_90; // @[package.scala 32:76]
  wire [17:0] _io_resp_bits_target_T_94 = _io_resp_bits_target_T_82 == 3'h6 ? pagesMasked_4 : _io_resp_bits_target_T_92; // @[package.scala 32:76]
  wire [17:0] _io_resp_bits_target_T_96 = _io_resp_bits_target_T_82 == 3'h7 ? pagesMasked_5 : _io_resp_bits_target_T_94; // @[package.scala 32:76]
  wire [12:0] _io_resp_bits_target_T_125 = idxHit[0] ? tgts_0 : 13'h0; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_126 = idxHit[1] ? tgts_1 : 13'h0; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_127 = idxHit[2] ? tgts_2 : 13'h0; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_128 = idxHit[3] ? tgts_3 : 13'h0; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_129 = idxHit[4] ? tgts_4 : 13'h0; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_130 = idxHit[5] ? tgts_5 : 13'h0; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_131 = idxHit[6] ? tgts_6 : 13'h0; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_132 = idxHit[7] ? tgts_7 : 13'h0; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_133 = idxHit[8] ? tgts_8 : 13'h0; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_134 = idxHit[9] ? tgts_9 : 13'h0; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_135 = idxHit[10] ? tgts_10 : 13'h0; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_136 = idxHit[11] ? tgts_11 : 13'h0; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_137 = idxHit[12] ? tgts_12 : 13'h0; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_138 = idxHit[13] ? tgts_13 : 13'h0; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_139 = idxHit[14] ? tgts_14 : 13'h0; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_140 = idxHit[15] ? tgts_15 : 13'h0; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_141 = idxHit[16] ? tgts_16 : 13'h0; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_142 = idxHit[17] ? tgts_17 : 13'h0; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_143 = idxHit[18] ? tgts_18 : 13'h0; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_144 = idxHit[19] ? tgts_19 : 13'h0; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_145 = idxHit[20] ? tgts_20 : 13'h0; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_146 = idxHit[21] ? tgts_21 : 13'h0; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_147 = idxHit[22] ? tgts_22 : 13'h0; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_148 = idxHit[23] ? tgts_23 : 13'h0; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_149 = idxHit[24] ? tgts_24 : 13'h0; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_150 = idxHit[25] ? tgts_25 : 13'h0; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_151 = idxHit[26] ? tgts_26 : 13'h0; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_152 = idxHit[27] ? tgts_27 : 13'h0; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_153 = _io_resp_bits_target_T_125 | _io_resp_bits_target_T_126; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_154 = _io_resp_bits_target_T_153 | _io_resp_bits_target_T_127; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_155 = _io_resp_bits_target_T_154 | _io_resp_bits_target_T_128; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_156 = _io_resp_bits_target_T_155 | _io_resp_bits_target_T_129; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_157 = _io_resp_bits_target_T_156 | _io_resp_bits_target_T_130; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_158 = _io_resp_bits_target_T_157 | _io_resp_bits_target_T_131; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_159 = _io_resp_bits_target_T_158 | _io_resp_bits_target_T_132; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_160 = _io_resp_bits_target_T_159 | _io_resp_bits_target_T_133; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_161 = _io_resp_bits_target_T_160 | _io_resp_bits_target_T_134; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_162 = _io_resp_bits_target_T_161 | _io_resp_bits_target_T_135; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_163 = _io_resp_bits_target_T_162 | _io_resp_bits_target_T_136; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_164 = _io_resp_bits_target_T_163 | _io_resp_bits_target_T_137; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_165 = _io_resp_bits_target_T_164 | _io_resp_bits_target_T_138; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_166 = _io_resp_bits_target_T_165 | _io_resp_bits_target_T_139; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_167 = _io_resp_bits_target_T_166 | _io_resp_bits_target_T_140; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_168 = _io_resp_bits_target_T_167 | _io_resp_bits_target_T_141; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_169 = _io_resp_bits_target_T_168 | _io_resp_bits_target_T_142; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_170 = _io_resp_bits_target_T_169 | _io_resp_bits_target_T_143; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_171 = _io_resp_bits_target_T_170 | _io_resp_bits_target_T_144; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_172 = _io_resp_bits_target_T_171 | _io_resp_bits_target_T_145; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_173 = _io_resp_bits_target_T_172 | _io_resp_bits_target_T_146; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_174 = _io_resp_bits_target_T_173 | _io_resp_bits_target_T_147; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_175 = _io_resp_bits_target_T_174 | _io_resp_bits_target_T_148; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_176 = _io_resp_bits_target_T_175 | _io_resp_bits_target_T_149; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_177 = _io_resp_bits_target_T_176 | _io_resp_bits_target_T_150; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_178 = _io_resp_bits_target_T_177 | _io_resp_bits_target_T_151; // @[Mux.scala 27:73]
  wire [12:0] _io_resp_bits_target_T_179 = _io_resp_bits_target_T_178 | _io_resp_bits_target_T_152; // @[Mux.scala 27:73]
  wire [13:0] _io_resp_bits_target_T_180 = {_io_resp_bits_target_T_179, 1'h0}; // @[BTB.scala 291:88]
  wire [31:0] _io_resp_bits_target_T_181 = {_io_resp_bits_target_T_96,_io_resp_bits_target_T_180}; // @[Cat.scala 31:58]
  wire [11:0] io_resp_bits_entry_hi = idxHit[27:16]; // @[OneHot.scala 30:18]
  wire [15:0] io_resp_bits_entry_lo = idxHit[15:0]; // @[OneHot.scala 31:18]
  wire  _io_resp_bits_entry_T = |io_resp_bits_entry_hi; // @[OneHot.scala 32:14]
  wire [15:0] _GEN_436 = {{4'd0}, io_resp_bits_entry_hi}; // @[OneHot.scala 32:28]
  wire [15:0] _io_resp_bits_entry_T_1 = _GEN_436 | io_resp_bits_entry_lo; // @[OneHot.scala 32:28]
  wire [7:0] io_resp_bits_entry_hi_1 = _io_resp_bits_entry_T_1[15:8]; // @[OneHot.scala 30:18]
  wire [7:0] io_resp_bits_entry_lo_1 = _io_resp_bits_entry_T_1[7:0]; // @[OneHot.scala 31:18]
  wire  _io_resp_bits_entry_T_2 = |io_resp_bits_entry_hi_1; // @[OneHot.scala 32:14]
  wire [7:0] _io_resp_bits_entry_T_3 = io_resp_bits_entry_hi_1 | io_resp_bits_entry_lo_1; // @[OneHot.scala 32:28]
  wire [3:0] io_resp_bits_entry_hi_2 = _io_resp_bits_entry_T_3[7:4]; // @[OneHot.scala 30:18]
  wire [3:0] io_resp_bits_entry_lo_2 = _io_resp_bits_entry_T_3[3:0]; // @[OneHot.scala 31:18]
  wire  _io_resp_bits_entry_T_4 = |io_resp_bits_entry_hi_2; // @[OneHot.scala 32:14]
  wire [3:0] _io_resp_bits_entry_T_5 = io_resp_bits_entry_hi_2 | io_resp_bits_entry_lo_2; // @[OneHot.scala 32:28]
  wire [1:0] io_resp_bits_entry_hi_3 = _io_resp_bits_entry_T_5[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] io_resp_bits_entry_lo_3 = _io_resp_bits_entry_T_5[1:0]; // @[OneHot.scala 31:18]
  wire  _io_resp_bits_entry_T_6 = |io_resp_bits_entry_hi_3; // @[OneHot.scala 32:14]
  wire [1:0] _io_resp_bits_entry_T_7 = io_resp_bits_entry_hi_3 | io_resp_bits_entry_lo_3; // @[OneHot.scala 32:28]
  wire [3:0] _io_resp_bits_entry_T_11 = {_io_resp_bits_entry_T_2,_io_resp_bits_entry_T_4,_io_resp_bits_entry_T_6,
    _io_resp_bits_entry_T_7[1]}; // @[Cat.scala 31:58]
  wire  _io_resp_bits_bridx_T_43 = idxHit[15] & brIdx_15; // @[Mux.scala 27:73]
  wire  _io_resp_bits_bridx_T_70 = idxHit[0] & brIdx_0 | idxHit[1] & brIdx_1 | idxHit[2] & brIdx_2 | idxHit[3] & brIdx_3
     | idxHit[4] & brIdx_4 | idxHit[5] & brIdx_5 | idxHit[6] & brIdx_6 | idxHit[7] & brIdx_7 | idxHit[8] & brIdx_8 |
    idxHit[9] & brIdx_9 | idxHit[10] & brIdx_10 | idxHit[11] & brIdx_11 | idxHit[12] & brIdx_12 | idxHit[13] & brIdx_13
     | idxHit[14] & brIdx_14 | _io_resp_bits_bridx_T_43; // @[Mux.scala 27:73]
  wire  leftOne = idxHit[0]; // @[Misc.scala 180:37]
  wire  leftOne_1 = idxHit[1]; // @[Misc.scala 180:37]
  wire  rightOne = idxHit[2]; // @[Misc.scala 181:39]
  wire  rightOne_1 = leftOne_1 | rightOne; // @[Misc.scala 182:16]
  wire  rightTwo = leftOne_1 & rightOne; // @[Misc.scala 182:61]
  wire  leftOne_2 = leftOne | rightOne_1; // @[Misc.scala 182:16]
  wire  leftTwo = rightTwo | leftOne & rightOne_1; // @[Misc.scala 182:49]
  wire  leftOne_3 = idxHit[3]; // @[Misc.scala 180:37]
  wire  rightOne_2 = idxHit[4]; // @[Misc.scala 181:39]
  wire  leftOne_4 = leftOne_3 | rightOne_2; // @[Misc.scala 182:16]
  wire  leftTwo_1 = leftOne_3 & rightOne_2; // @[Misc.scala 182:61]
  wire  leftOne_5 = idxHit[5]; // @[Misc.scala 180:37]
  wire  rightOne_3 = idxHit[6]; // @[Misc.scala 181:39]
  wire  rightOne_4 = leftOne_5 | rightOne_3; // @[Misc.scala 182:16]
  wire  rightTwo_1 = leftOne_5 & rightOne_3; // @[Misc.scala 182:61]
  wire  rightOne_5 = leftOne_4 | rightOne_4; // @[Misc.scala 182:16]
  wire  rightTwo_2 = leftTwo_1 | rightTwo_1 | leftOne_4 & rightOne_4; // @[Misc.scala 182:49]
  wire  leftOne_6 = leftOne_2 | rightOne_5; // @[Misc.scala 182:16]
  wire  leftTwo_2 = leftTwo | rightTwo_2 | leftOne_2 & rightOne_5; // @[Misc.scala 182:49]
  wire  leftOne_7 = idxHit[7]; // @[Misc.scala 180:37]
  wire  leftOne_8 = idxHit[8]; // @[Misc.scala 180:37]
  wire  rightOne_6 = idxHit[9]; // @[Misc.scala 181:39]
  wire  rightOne_7 = leftOne_8 | rightOne_6; // @[Misc.scala 182:16]
  wire  rightTwo_3 = leftOne_8 & rightOne_6; // @[Misc.scala 182:61]
  wire  leftOne_9 = leftOne_7 | rightOne_7; // @[Misc.scala 182:16]
  wire  leftTwo_3 = rightTwo_3 | leftOne_7 & rightOne_7; // @[Misc.scala 182:49]
  wire  leftOne_10 = idxHit[10]; // @[Misc.scala 180:37]
  wire  rightOne_8 = idxHit[11]; // @[Misc.scala 181:39]
  wire  leftOne_11 = leftOne_10 | rightOne_8; // @[Misc.scala 182:16]
  wire  leftTwo_4 = leftOne_10 & rightOne_8; // @[Misc.scala 182:61]
  wire  leftOne_12 = idxHit[12]; // @[Misc.scala 180:37]
  wire  rightOne_9 = idxHit[13]; // @[Misc.scala 181:39]
  wire  rightOne_10 = leftOne_12 | rightOne_9; // @[Misc.scala 182:16]
  wire  rightTwo_4 = leftOne_12 & rightOne_9; // @[Misc.scala 182:61]
  wire  rightOne_11 = leftOne_11 | rightOne_10; // @[Misc.scala 182:16]
  wire  rightTwo_5 = leftTwo_4 | rightTwo_4 | leftOne_11 & rightOne_10; // @[Misc.scala 182:49]
  wire  rightOne_12 = leftOne_9 | rightOne_11; // @[Misc.scala 182:16]
  wire  rightTwo_6 = leftTwo_3 | rightTwo_5 | leftOne_9 & rightOne_11; // @[Misc.scala 182:49]
  wire  leftOne_13 = leftOne_6 | rightOne_12; // @[Misc.scala 182:16]
  wire  leftTwo_5 = leftTwo_2 | rightTwo_6 | leftOne_6 & rightOne_12; // @[Misc.scala 182:49]
  wire  leftOne_14 = idxHit[14]; // @[Misc.scala 180:37]
  wire  leftOne_15 = idxHit[15]; // @[Misc.scala 180:37]
  wire  rightOne_13 = idxHit[16]; // @[Misc.scala 181:39]
  wire  rightOne_14 = leftOne_15 | rightOne_13; // @[Misc.scala 182:16]
  wire  rightTwo_7 = leftOne_15 & rightOne_13; // @[Misc.scala 182:61]
  wire  leftOne_16 = leftOne_14 | rightOne_14; // @[Misc.scala 182:16]
  wire  leftTwo_6 = rightTwo_7 | leftOne_14 & rightOne_14; // @[Misc.scala 182:49]
  wire  leftOne_17 = idxHit[17]; // @[Misc.scala 180:37]
  wire  rightOne_15 = idxHit[18]; // @[Misc.scala 181:39]
  wire  leftOne_18 = leftOne_17 | rightOne_15; // @[Misc.scala 182:16]
  wire  leftTwo_7 = leftOne_17 & rightOne_15; // @[Misc.scala 182:61]
  wire  leftOne_19 = idxHit[19]; // @[Misc.scala 180:37]
  wire  rightOne_16 = idxHit[20]; // @[Misc.scala 181:39]
  wire  rightOne_17 = leftOne_19 | rightOne_16; // @[Misc.scala 182:16]
  wire  rightTwo_8 = leftOne_19 & rightOne_16; // @[Misc.scala 182:61]
  wire  rightOne_18 = leftOne_18 | rightOne_17; // @[Misc.scala 182:16]
  wire  rightTwo_9 = leftTwo_7 | rightTwo_8 | leftOne_18 & rightOne_17; // @[Misc.scala 182:49]
  wire  leftOne_20 = leftOne_16 | rightOne_18; // @[Misc.scala 182:16]
  wire  leftTwo_8 = leftTwo_6 | rightTwo_9 | leftOne_16 & rightOne_18; // @[Misc.scala 182:49]
  wire  leftOne_21 = idxHit[21]; // @[Misc.scala 180:37]
  wire  leftOne_22 = idxHit[22]; // @[Misc.scala 180:37]
  wire  rightOne_19 = idxHit[23]; // @[Misc.scala 181:39]
  wire  rightOne_20 = leftOne_22 | rightOne_19; // @[Misc.scala 182:16]
  wire  rightTwo_10 = leftOne_22 & rightOne_19; // @[Misc.scala 182:61]
  wire  leftOne_23 = leftOne_21 | rightOne_20; // @[Misc.scala 182:16]
  wire  leftTwo_9 = rightTwo_10 | leftOne_21 & rightOne_20; // @[Misc.scala 182:49]
  wire  leftOne_24 = idxHit[24]; // @[Misc.scala 180:37]
  wire  rightOne_21 = idxHit[25]; // @[Misc.scala 181:39]
  wire  leftOne_25 = leftOne_24 | rightOne_21; // @[Misc.scala 182:16]
  wire  leftTwo_10 = leftOne_24 & rightOne_21; // @[Misc.scala 182:61]
  wire  leftOne_26 = idxHit[26]; // @[Misc.scala 180:37]
  wire  rightOne_22 = idxHit[27]; // @[Misc.scala 181:39]
  wire  rightOne_23 = leftOne_26 | rightOne_22; // @[Misc.scala 182:16]
  wire  rightTwo_11 = leftOne_26 & rightOne_22; // @[Misc.scala 182:61]
  wire  rightOne_24 = leftOne_25 | rightOne_23; // @[Misc.scala 182:16]
  wire  rightTwo_12 = leftTwo_10 | rightTwo_11 | leftOne_25 & rightOne_23; // @[Misc.scala 182:49]
  wire  rightOne_25 = leftOne_23 | rightOne_24; // @[Misc.scala 182:16]
  wire  rightTwo_13 = leftTwo_9 | rightTwo_12 | leftOne_23 & rightOne_24; // @[Misc.scala 182:49]
  wire  rightOne_26 = leftOne_20 | rightOne_25; // @[Misc.scala 182:16]
  wire  rightTwo_14 = leftTwo_8 | rightTwo_13 | leftOne_20 & rightOne_25; // @[Misc.scala 182:49]
  wire  _T_128 = leftTwo_5 | rightTwo_14 | leftOne_13 & rightOne_26; // @[Misc.scala 182:49]
  wire [27:0] _isValid_T_4 = ~idxHit; // @[BTB.scala 299:26]
  wire [27:0] _isValid_T_5 = isValid & _isValid_T_4; // @[BTB.scala 299:24]
  wire [31:0] _GEN_374 = _T_128 ? {{4'd0}, _isValid_T_5} : _GEN_338; // @[BTB.scala 298:37 299:13]
  wire [31:0] _GEN_375 = io_flush ? 32'h0 : _GEN_374; // @[BTB.scala 301:19 302:13]
  reg [7:0] history; // @[BTB.scala 119:24]
  reg [9:0] reset_waddr; // @[BTB.scala 121:36]
  wire  resetting = ~reset_waddr[9]; // @[BTB.scala 122:27]
  wire [9:0] _reset_waddr_T_1 = reset_waddr + 10'h1; // @[BTB.scala 126:49]
  wire [29:0] waddr_hi = io_bht_update_bits_pc[31:2]; // @[BTB.scala 87:21]
  wire [8:0] _GEN_437 = {{7'd0}, waddr_hi[10:9]}; // @[BTB.scala 88:42]
  wire [8:0] _waddr_T_43 = waddr_hi[8:0] ^ _GEN_437; // @[BTB.scala 88:42]
  wire [15:0] _waddr_T_44 = 8'hdd * io_bht_update_bits_prediction_history; // @[BTB.scala 84:12]
  wire [8:0] _waddr_T_46 = {_waddr_T_44[7:5], 6'h0}; // @[BTB.scala 90:44]
  wire [8:0] _waddr_T_47 = _waddr_T_43 ^ _waddr_T_46; // @[BTB.scala 90:20]
  wire [9:0] _GEN_383 = ~resetting ? {{1'd0}, _waddr_T_47} : reset_waddr; // @[BTB.scala 100:23 101:13]
  wire [9:0] _GEN_388 = io_bht_update_bits_branch ? _GEN_383 : reset_waddr; // @[BTB.scala 313:40]
  wire [9:0] waddr_1 = io_bht_update_valid ? _GEN_388 : reset_waddr; // @[BTB.scala 312:32]
  wire  _GEN_387 = io_bht_update_bits_branch | resetting; // @[BTB.scala 313:40 99:9]
  wire  _GEN_384 = ~resetting & io_bht_update_bits_taken; // @[BTB.scala 100:23 102:13]
  wire  _GEN_389 = io_bht_update_bits_branch & _GEN_384; // @[BTB.scala 313:40]
  wire  _isBranch_T = cfiType_0 == 2'h0; // @[BTB.scala 307:44]
  wire  _isBranch_T_1 = cfiType_1 == 2'h0; // @[BTB.scala 307:44]
  wire  _isBranch_T_2 = cfiType_2 == 2'h0; // @[BTB.scala 307:44]
  wire  _isBranch_T_3 = cfiType_3 == 2'h0; // @[BTB.scala 307:44]
  wire  _isBranch_T_4 = cfiType_4 == 2'h0; // @[BTB.scala 307:44]
  wire  _isBranch_T_5 = cfiType_5 == 2'h0; // @[BTB.scala 307:44]
  wire  _isBranch_T_6 = cfiType_6 == 2'h0; // @[BTB.scala 307:44]
  wire  _isBranch_T_7 = cfiType_7 == 2'h0; // @[BTB.scala 307:44]
  wire  _isBranch_T_8 = cfiType_8 == 2'h0; // @[BTB.scala 307:44]
  wire  _isBranch_T_9 = cfiType_9 == 2'h0; // @[BTB.scala 307:44]
  wire  _isBranch_T_10 = cfiType_10 == 2'h0; // @[BTB.scala 307:44]
  wire  _isBranch_T_11 = cfiType_11 == 2'h0; // @[BTB.scala 307:44]
  wire  _isBranch_T_12 = cfiType_12 == 2'h0; // @[BTB.scala 307:44]
  wire  _isBranch_T_13 = cfiType_13 == 2'h0; // @[BTB.scala 307:44]
  wire  _isBranch_T_14 = cfiType_14 == 2'h0; // @[BTB.scala 307:44]
  wire  _isBranch_T_15 = cfiType_15 == 2'h0; // @[BTB.scala 307:44]
  wire  _isBranch_T_16 = cfiType_16 == 2'h0; // @[BTB.scala 307:44]
  wire  _isBranch_T_17 = cfiType_17 == 2'h0; // @[BTB.scala 307:44]
  wire  _isBranch_T_18 = cfiType_18 == 2'h0; // @[BTB.scala 307:44]
  wire  _isBranch_T_19 = cfiType_19 == 2'h0; // @[BTB.scala 307:44]
  wire  _isBranch_T_20 = cfiType_20 == 2'h0; // @[BTB.scala 307:44]
  wire  _isBranch_T_21 = cfiType_21 == 2'h0; // @[BTB.scala 307:44]
  wire  _isBranch_T_22 = cfiType_22 == 2'h0; // @[BTB.scala 307:44]
  wire  _isBranch_T_23 = cfiType_23 == 2'h0; // @[BTB.scala 307:44]
  wire  _isBranch_T_24 = cfiType_24 == 2'h0; // @[BTB.scala 307:44]
  wire  _isBranch_T_25 = cfiType_25 == 2'h0; // @[BTB.scala 307:44]
  wire  _isBranch_T_26 = cfiType_26 == 2'h0; // @[BTB.scala 307:44]
  wire  _isBranch_T_27 = cfiType_27 == 2'h0; // @[BTB.scala 307:44]
  wire [6:0] isBranch_lo_lo = {_isBranch_T_6,_isBranch_T_5,_isBranch_T_4,_isBranch_T_3,_isBranch_T_2,_isBranch_T_1,
    _isBranch_T}; // @[Cat.scala 31:58]
  wire [13:0] isBranch_lo = {_isBranch_T_13,_isBranch_T_12,_isBranch_T_11,_isBranch_T_10,_isBranch_T_9,_isBranch_T_8,
    _isBranch_T_7,isBranch_lo_lo}; // @[Cat.scala 31:58]
  wire [6:0] isBranch_hi_lo = {_isBranch_T_20,_isBranch_T_19,_isBranch_T_18,_isBranch_T_17,_isBranch_T_16,_isBranch_T_15
    ,_isBranch_T_14}; // @[Cat.scala 31:58]
  wire [27:0] _isBranch_T_28 = {_isBranch_T_27,_isBranch_T_26,_isBranch_T_25,_isBranch_T_24,_isBranch_T_23,
    _isBranch_T_22,_isBranch_T_21,isBranch_hi_lo,isBranch_lo}; // @[Cat.scala 31:58]
  wire [27:0] _isBranch_T_29 = idxHit & _isBranch_T_28; // @[BTB.scala 307:28]
  wire  isBranch = |_isBranch_T_29; // @[BTB.scala 307:72]
  wire [29:0] res_res_value_hi = io_req_bits_addr[31:2]; // @[BTB.scala 87:21]
  wire [8:0] _GEN_438 = {{7'd0}, res_res_value_hi[10:9]}; // @[BTB.scala 88:42]
  wire [8:0] _res_res_value_T_3 = res_res_value_hi[8:0] ^ _GEN_438; // @[BTB.scala 88:42]
  wire [15:0] _res_res_value_T_4 = 8'hdd * history; // @[BTB.scala 84:12]
  wire [8:0] _res_res_value_T_6 = {_res_res_value_T_4[7:5], 6'h0}; // @[BTB.scala 90:44]
  wire  res_value = resetting ? 1'h0 : table__res_res_value_MPORT_data; // @[BTB.scala 94:21]
  wire [7:0] _history_T_1 = {io_bht_advance_bits_bht_value,history[7:1]}; // @[Cat.scala 31:58]
  wire [7:0] _GEN_382 = io_bht_advance_valid ? _history_T_1 : history; // @[BTB.scala 115:13 119:24 309:33]
  wire [7:0] _history_T_3 = {io_bht_update_bits_taken,io_bht_update_bits_prediction_history[7:1]}; // @[Cat.scala 31:58]
  reg [2:0] count; // @[BTB.scala 58:30]
  reg [2:0] pos; // @[BTB.scala 59:28]
  reg [31:0] stack_0; // @[BTB.scala 60:26]
  reg [31:0] stack_1; // @[BTB.scala 60:26]
  reg [31:0] stack_2; // @[BTB.scala 60:26]
  reg [31:0] stack_3; // @[BTB.scala 60:26]
  reg [31:0] stack_4; // @[BTB.scala 60:26]
  reg [31:0] stack_5; // @[BTB.scala 60:26]
  wire  _doPeek_T = cfiType_0 == 2'h3; // @[BTB.scala 328:42]
  wire  _doPeek_T_1 = cfiType_1 == 2'h3; // @[BTB.scala 328:42]
  wire  _doPeek_T_2 = cfiType_2 == 2'h3; // @[BTB.scala 328:42]
  wire  _doPeek_T_3 = cfiType_3 == 2'h3; // @[BTB.scala 328:42]
  wire  _doPeek_T_4 = cfiType_4 == 2'h3; // @[BTB.scala 328:42]
  wire  _doPeek_T_5 = cfiType_5 == 2'h3; // @[BTB.scala 328:42]
  wire  _doPeek_T_6 = cfiType_6 == 2'h3; // @[BTB.scala 328:42]
  wire  _doPeek_T_7 = cfiType_7 == 2'h3; // @[BTB.scala 328:42]
  wire  _doPeek_T_8 = cfiType_8 == 2'h3; // @[BTB.scala 328:42]
  wire  _doPeek_T_9 = cfiType_9 == 2'h3; // @[BTB.scala 328:42]
  wire  _doPeek_T_10 = cfiType_10 == 2'h3; // @[BTB.scala 328:42]
  wire  _doPeek_T_11 = cfiType_11 == 2'h3; // @[BTB.scala 328:42]
  wire  _doPeek_T_12 = cfiType_12 == 2'h3; // @[BTB.scala 328:42]
  wire  _doPeek_T_13 = cfiType_13 == 2'h3; // @[BTB.scala 328:42]
  wire  _doPeek_T_14 = cfiType_14 == 2'h3; // @[BTB.scala 328:42]
  wire  _doPeek_T_15 = cfiType_15 == 2'h3; // @[BTB.scala 328:42]
  wire  _doPeek_T_16 = cfiType_16 == 2'h3; // @[BTB.scala 328:42]
  wire  _doPeek_T_17 = cfiType_17 == 2'h3; // @[BTB.scala 328:42]
  wire  _doPeek_T_18 = cfiType_18 == 2'h3; // @[BTB.scala 328:42]
  wire  _doPeek_T_19 = cfiType_19 == 2'h3; // @[BTB.scala 328:42]
  wire  _doPeek_T_20 = cfiType_20 == 2'h3; // @[BTB.scala 328:42]
  wire  _doPeek_T_21 = cfiType_21 == 2'h3; // @[BTB.scala 328:42]
  wire  _doPeek_T_22 = cfiType_22 == 2'h3; // @[BTB.scala 328:42]
  wire  _doPeek_T_23 = cfiType_23 == 2'h3; // @[BTB.scala 328:42]
  wire  _doPeek_T_24 = cfiType_24 == 2'h3; // @[BTB.scala 328:42]
  wire  _doPeek_T_25 = cfiType_25 == 2'h3; // @[BTB.scala 328:42]
  wire  _doPeek_T_26 = cfiType_26 == 2'h3; // @[BTB.scala 328:42]
  wire  _doPeek_T_27 = cfiType_27 == 2'h3; // @[BTB.scala 328:42]
  wire [6:0] doPeek_lo_lo = {_doPeek_T_6,_doPeek_T_5,_doPeek_T_4,_doPeek_T_3,_doPeek_T_2,_doPeek_T_1,_doPeek_T}; // @[Cat.scala 31:58]
  wire [13:0] doPeek_lo = {_doPeek_T_13,_doPeek_T_12,_doPeek_T_11,_doPeek_T_10,_doPeek_T_9,_doPeek_T_8,_doPeek_T_7,
    doPeek_lo_lo}; // @[Cat.scala 31:58]
  wire [6:0] doPeek_hi_lo = {_doPeek_T_20,_doPeek_T_19,_doPeek_T_18,_doPeek_T_17,_doPeek_T_16,_doPeek_T_15,_doPeek_T_14}
    ; // @[Cat.scala 31:58]
  wire [27:0] _doPeek_T_28 = {_doPeek_T_27,_doPeek_T_26,_doPeek_T_25,_doPeek_T_24,_doPeek_T_23,_doPeek_T_22,_doPeek_T_21
    ,doPeek_hi_lo,doPeek_lo}; // @[Cat.scala 31:58]
  wire [27:0] _doPeek_T_29 = idxHit & _doPeek_T_28; // @[BTB.scala 328:26]
  wire  doPeek = |_doPeek_T_29; // @[BTB.scala 328:67]
  wire  _io_ras_head_valid_T = count == 3'h0; // @[BTB.scala 56:29]
  wire  _io_ras_head_valid_T_1 = ~_io_ras_head_valid_T; // @[BTB.scala 329:26]
  wire [31:0] _GEN_397 = 3'h1 == pos ? stack_1 : stack_0; // @[BTB.scala 330:{22,22}]
  wire [31:0] _GEN_398 = 3'h2 == pos ? stack_2 : _GEN_397; // @[BTB.scala 330:{22,22}]
  wire [31:0] _GEN_399 = 3'h3 == pos ? stack_3 : _GEN_398; // @[BTB.scala 330:{22,22}]
  wire [31:0] _GEN_400 = 3'h4 == pos ? stack_4 : _GEN_399; // @[BTB.scala 330:{22,22}]
  wire [31:0] _GEN_401 = 3'h5 == pos ? stack_5 : _GEN_400; // @[BTB.scala 330:{22,22}]
  wire [2:0] _count_T_1 = count + 3'h1; // @[BTB.scala 45:42]
  wire [2:0] _nextPos_T_3 = pos + 3'h1; // @[BTB.scala 46:62]
  wire [2:0] nextPos = pos < 3'h5 ? _nextPos_T_3 : 3'h0; // @[BTB.scala 46:22]
  wire [2:0] _count_T_3 = count - 3'h1; // @[BTB.scala 52:20]
  wire [2:0] _pos_T_3 = pos - 3'h1; // @[BTB.scala 53:50]
  wire [2:0] _pos_T_4 = pos > 3'h0 ? _pos_T_3 : 3'h5; // @[BTB.scala 53:15]
  wire [2:0] _GEN_410 = _io_ras_head_valid_T_1 ? _count_T_3 : count; // @[BTB.scala 51:37 52:11 58:30]
  wire [2:0] _GEN_411 = _io_ras_head_valid_T_1 ? _pos_T_4 : pos; // @[BTB.scala 51:37 53:9 59:28]
  assign table__res_res_value_MPORT_en = 1'h1;
  assign table__res_res_value_MPORT_addr = _res_res_value_T_3 ^ _res_res_value_T_6;
  assign table__res_res_value_MPORT_data = table_[table__res_res_value_MPORT_addr]; // @[BTB.scala 118:26]
  assign table__MPORT_data = io_bht_update_valid & _GEN_389;
  assign table__MPORT_addr = waddr_1[8:0];
  assign table__MPORT_mask = 1'h1;
  assign table__MPORT_en = io_bht_update_valid ? _GEN_387 : resetting;
  assign io_resp_valid = _io_resp_valid_T_84[0]; // @[BTB.scala 289:34]
  assign io_resp_bits_taken = ~res_value & isBranch ? 1'h0 : 1'h1; // @[BTB.scala 290:22 322:{35,56}]
  assign io_resp_bits_bridx = _io_resp_bits_bridx_T_70 | idxHit[16] & brIdx_16 | idxHit[17] & brIdx_17 | idxHit[18] &
    brIdx_18 | idxHit[19] & brIdx_19 | idxHit[20] & brIdx_20 | idxHit[21] & brIdx_21 | idxHit[22] & brIdx_22 | idxHit[23
    ] & brIdx_23 | idxHit[24] & brIdx_24 | idxHit[25] & brIdx_25 | idxHit[26] & brIdx_26 | idxHit[27] & brIdx_27; // @[Mux.scala 27:73]
  assign io_resp_bits_target = _io_ras_head_valid_T_1 & doPeek ? _GEN_401 : _io_resp_bits_target_T_181; // @[BTB.scala 291:23 331:35 332:27]
  assign io_resp_bits_entry = {_io_resp_bits_entry_T,_io_resp_bits_entry_T_11}; // @[Cat.scala 31:58]
  assign io_resp_bits_bht_history = history; // @[BTB.scala 93:19 95:17]
  assign io_resp_bits_bht_value = resetting ? 1'h0 : table__res_res_value_MPORT_data; // @[BTB.scala 94:21]
  assign io_ras_head_valid = ~_io_ras_head_valid_T; // @[BTB.scala 329:26]
  assign io_ras_head_bits = 3'h5 == pos ? stack_5 : _GEN_400; // @[BTB.scala 330:{22,22}]
  always @(posedge clock) begin
    if (table__MPORT_en & table__MPORT_mask) begin
      table_[table__MPORT_addr] <= table__MPORT_data; // @[BTB.scala 118:26]
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h0 == waddr) begin // @[BTB.scala 266:17]
        idxs_0 <= r_btb_updatePipe_bits_pc[13:1]; // @[BTB.scala 266:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h1 == waddr) begin // @[BTB.scala 266:17]
        idxs_1 <= r_btb_updatePipe_bits_pc[13:1]; // @[BTB.scala 266:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h2 == waddr) begin // @[BTB.scala 266:17]
        idxs_2 <= r_btb_updatePipe_bits_pc[13:1]; // @[BTB.scala 266:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h3 == waddr) begin // @[BTB.scala 266:17]
        idxs_3 <= r_btb_updatePipe_bits_pc[13:1]; // @[BTB.scala 266:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h4 == waddr) begin // @[BTB.scala 266:17]
        idxs_4 <= r_btb_updatePipe_bits_pc[13:1]; // @[BTB.scala 266:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h5 == waddr) begin // @[BTB.scala 266:17]
        idxs_5 <= r_btb_updatePipe_bits_pc[13:1]; // @[BTB.scala 266:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h6 == waddr) begin // @[BTB.scala 266:17]
        idxs_6 <= r_btb_updatePipe_bits_pc[13:1]; // @[BTB.scala 266:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h7 == waddr) begin // @[BTB.scala 266:17]
        idxs_7 <= r_btb_updatePipe_bits_pc[13:1]; // @[BTB.scala 266:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h8 == waddr) begin // @[BTB.scala 266:17]
        idxs_8 <= r_btb_updatePipe_bits_pc[13:1]; // @[BTB.scala 266:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h9 == waddr) begin // @[BTB.scala 266:17]
        idxs_9 <= r_btb_updatePipe_bits_pc[13:1]; // @[BTB.scala 266:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'ha == waddr) begin // @[BTB.scala 266:17]
        idxs_10 <= r_btb_updatePipe_bits_pc[13:1]; // @[BTB.scala 266:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'hb == waddr) begin // @[BTB.scala 266:17]
        idxs_11 <= r_btb_updatePipe_bits_pc[13:1]; // @[BTB.scala 266:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'hc == waddr) begin // @[BTB.scala 266:17]
        idxs_12 <= r_btb_updatePipe_bits_pc[13:1]; // @[BTB.scala 266:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'hd == waddr) begin // @[BTB.scala 266:17]
        idxs_13 <= r_btb_updatePipe_bits_pc[13:1]; // @[BTB.scala 266:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'he == waddr) begin // @[BTB.scala 266:17]
        idxs_14 <= r_btb_updatePipe_bits_pc[13:1]; // @[BTB.scala 266:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'hf == waddr) begin // @[BTB.scala 266:17]
        idxs_15 <= r_btb_updatePipe_bits_pc[13:1]; // @[BTB.scala 266:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h10 == waddr) begin // @[BTB.scala 266:17]
        idxs_16 <= r_btb_updatePipe_bits_pc[13:1]; // @[BTB.scala 266:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h11 == waddr) begin // @[BTB.scala 266:17]
        idxs_17 <= r_btb_updatePipe_bits_pc[13:1]; // @[BTB.scala 266:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h12 == waddr) begin // @[BTB.scala 266:17]
        idxs_18 <= r_btb_updatePipe_bits_pc[13:1]; // @[BTB.scala 266:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h13 == waddr) begin // @[BTB.scala 266:17]
        idxs_19 <= r_btb_updatePipe_bits_pc[13:1]; // @[BTB.scala 266:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h14 == waddr) begin // @[BTB.scala 266:17]
        idxs_20 <= r_btb_updatePipe_bits_pc[13:1]; // @[BTB.scala 266:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h15 == waddr) begin // @[BTB.scala 266:17]
        idxs_21 <= r_btb_updatePipe_bits_pc[13:1]; // @[BTB.scala 266:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h16 == waddr) begin // @[BTB.scala 266:17]
        idxs_22 <= r_btb_updatePipe_bits_pc[13:1]; // @[BTB.scala 266:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h17 == waddr) begin // @[BTB.scala 266:17]
        idxs_23 <= r_btb_updatePipe_bits_pc[13:1]; // @[BTB.scala 266:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h18 == waddr) begin // @[BTB.scala 266:17]
        idxs_24 <= r_btb_updatePipe_bits_pc[13:1]; // @[BTB.scala 266:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h19 == waddr) begin // @[BTB.scala 266:17]
        idxs_25 <= r_btb_updatePipe_bits_pc[13:1]; // @[BTB.scala 266:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h1a == waddr) begin // @[BTB.scala 266:17]
        idxs_26 <= r_btb_updatePipe_bits_pc[13:1]; // @[BTB.scala 266:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h1b == waddr) begin // @[BTB.scala 266:17]
        idxs_27 <= r_btb_updatePipe_bits_pc[13:1]; // @[BTB.scala 266:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h0 == waddr) begin // @[BTB.scala 268:21]
        idxPages_0 <= _idxPages_T[2:0]; // @[BTB.scala 268:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h1 == waddr) begin // @[BTB.scala 268:21]
        idxPages_1 <= _idxPages_T[2:0]; // @[BTB.scala 268:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h2 == waddr) begin // @[BTB.scala 268:21]
        idxPages_2 <= _idxPages_T[2:0]; // @[BTB.scala 268:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h3 == waddr) begin // @[BTB.scala 268:21]
        idxPages_3 <= _idxPages_T[2:0]; // @[BTB.scala 268:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h4 == waddr) begin // @[BTB.scala 268:21]
        idxPages_4 <= _idxPages_T[2:0]; // @[BTB.scala 268:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h5 == waddr) begin // @[BTB.scala 268:21]
        idxPages_5 <= _idxPages_T[2:0]; // @[BTB.scala 268:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h6 == waddr) begin // @[BTB.scala 268:21]
        idxPages_6 <= _idxPages_T[2:0]; // @[BTB.scala 268:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h7 == waddr) begin // @[BTB.scala 268:21]
        idxPages_7 <= _idxPages_T[2:0]; // @[BTB.scala 268:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h8 == waddr) begin // @[BTB.scala 268:21]
        idxPages_8 <= _idxPages_T[2:0]; // @[BTB.scala 268:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h9 == waddr) begin // @[BTB.scala 268:21]
        idxPages_9 <= _idxPages_T[2:0]; // @[BTB.scala 268:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'ha == waddr) begin // @[BTB.scala 268:21]
        idxPages_10 <= _idxPages_T[2:0]; // @[BTB.scala 268:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'hb == waddr) begin // @[BTB.scala 268:21]
        idxPages_11 <= _idxPages_T[2:0]; // @[BTB.scala 268:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'hc == waddr) begin // @[BTB.scala 268:21]
        idxPages_12 <= _idxPages_T[2:0]; // @[BTB.scala 268:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'hd == waddr) begin // @[BTB.scala 268:21]
        idxPages_13 <= _idxPages_T[2:0]; // @[BTB.scala 268:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'he == waddr) begin // @[BTB.scala 268:21]
        idxPages_14 <= _idxPages_T[2:0]; // @[BTB.scala 268:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'hf == waddr) begin // @[BTB.scala 268:21]
        idxPages_15 <= _idxPages_T[2:0]; // @[BTB.scala 268:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h10 == waddr) begin // @[BTB.scala 268:21]
        idxPages_16 <= _idxPages_T[2:0]; // @[BTB.scala 268:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h11 == waddr) begin // @[BTB.scala 268:21]
        idxPages_17 <= _idxPages_T[2:0]; // @[BTB.scala 268:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h12 == waddr) begin // @[BTB.scala 268:21]
        idxPages_18 <= _idxPages_T[2:0]; // @[BTB.scala 268:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h13 == waddr) begin // @[BTB.scala 268:21]
        idxPages_19 <= _idxPages_T[2:0]; // @[BTB.scala 268:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h14 == waddr) begin // @[BTB.scala 268:21]
        idxPages_20 <= _idxPages_T[2:0]; // @[BTB.scala 268:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h15 == waddr) begin // @[BTB.scala 268:21]
        idxPages_21 <= _idxPages_T[2:0]; // @[BTB.scala 268:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h16 == waddr) begin // @[BTB.scala 268:21]
        idxPages_22 <= _idxPages_T[2:0]; // @[BTB.scala 268:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h17 == waddr) begin // @[BTB.scala 268:21]
        idxPages_23 <= _idxPages_T[2:0]; // @[BTB.scala 268:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h18 == waddr) begin // @[BTB.scala 268:21]
        idxPages_24 <= _idxPages_T[2:0]; // @[BTB.scala 268:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h19 == waddr) begin // @[BTB.scala 268:21]
        idxPages_25 <= _idxPages_T[2:0]; // @[BTB.scala 268:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h1a == waddr) begin // @[BTB.scala 268:21]
        idxPages_26 <= _idxPages_T[2:0]; // @[BTB.scala 268:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h1b == waddr) begin // @[BTB.scala 268:21]
        idxPages_27 <= _idxPages_T[2:0]; // @[BTB.scala 268:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h0 == waddr) begin // @[BTB.scala 267:17]
        tgts_0 <= idxHit_idx; // @[BTB.scala 267:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h1 == waddr) begin // @[BTB.scala 267:17]
        tgts_1 <= idxHit_idx; // @[BTB.scala 267:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h2 == waddr) begin // @[BTB.scala 267:17]
        tgts_2 <= idxHit_idx; // @[BTB.scala 267:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h3 == waddr) begin // @[BTB.scala 267:17]
        tgts_3 <= idxHit_idx; // @[BTB.scala 267:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h4 == waddr) begin // @[BTB.scala 267:17]
        tgts_4 <= idxHit_idx; // @[BTB.scala 267:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h5 == waddr) begin // @[BTB.scala 267:17]
        tgts_5 <= idxHit_idx; // @[BTB.scala 267:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h6 == waddr) begin // @[BTB.scala 267:17]
        tgts_6 <= idxHit_idx; // @[BTB.scala 267:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h7 == waddr) begin // @[BTB.scala 267:17]
        tgts_7 <= idxHit_idx; // @[BTB.scala 267:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h8 == waddr) begin // @[BTB.scala 267:17]
        tgts_8 <= idxHit_idx; // @[BTB.scala 267:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h9 == waddr) begin // @[BTB.scala 267:17]
        tgts_9 <= idxHit_idx; // @[BTB.scala 267:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'ha == waddr) begin // @[BTB.scala 267:17]
        tgts_10 <= idxHit_idx; // @[BTB.scala 267:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'hb == waddr) begin // @[BTB.scala 267:17]
        tgts_11 <= idxHit_idx; // @[BTB.scala 267:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'hc == waddr) begin // @[BTB.scala 267:17]
        tgts_12 <= idxHit_idx; // @[BTB.scala 267:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'hd == waddr) begin // @[BTB.scala 267:17]
        tgts_13 <= idxHit_idx; // @[BTB.scala 267:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'he == waddr) begin // @[BTB.scala 267:17]
        tgts_14 <= idxHit_idx; // @[BTB.scala 267:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'hf == waddr) begin // @[BTB.scala 267:17]
        tgts_15 <= idxHit_idx; // @[BTB.scala 267:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h10 == waddr) begin // @[BTB.scala 267:17]
        tgts_16 <= idxHit_idx; // @[BTB.scala 267:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h11 == waddr) begin // @[BTB.scala 267:17]
        tgts_17 <= idxHit_idx; // @[BTB.scala 267:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h12 == waddr) begin // @[BTB.scala 267:17]
        tgts_18 <= idxHit_idx; // @[BTB.scala 267:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h13 == waddr) begin // @[BTB.scala 267:17]
        tgts_19 <= idxHit_idx; // @[BTB.scala 267:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h14 == waddr) begin // @[BTB.scala 267:17]
        tgts_20 <= idxHit_idx; // @[BTB.scala 267:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h15 == waddr) begin // @[BTB.scala 267:17]
        tgts_21 <= idxHit_idx; // @[BTB.scala 267:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h16 == waddr) begin // @[BTB.scala 267:17]
        tgts_22 <= idxHit_idx; // @[BTB.scala 267:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h17 == waddr) begin // @[BTB.scala 267:17]
        tgts_23 <= idxHit_idx; // @[BTB.scala 267:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h18 == waddr) begin // @[BTB.scala 267:17]
        tgts_24 <= idxHit_idx; // @[BTB.scala 267:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h19 == waddr) begin // @[BTB.scala 267:17]
        tgts_25 <= idxHit_idx; // @[BTB.scala 267:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h1a == waddr) begin // @[BTB.scala 267:17]
        tgts_26 <= idxHit_idx; // @[BTB.scala 267:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h1b == waddr) begin // @[BTB.scala 267:17]
        tgts_27 <= idxHit_idx; // @[BTB.scala 267:17]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h0 == waddr) begin // @[BTB.scala 269:21]
        tgtPages_0 <= tgtPageUpdate; // @[BTB.scala 269:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h1 == waddr) begin // @[BTB.scala 269:21]
        tgtPages_1 <= tgtPageUpdate; // @[BTB.scala 269:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h2 == waddr) begin // @[BTB.scala 269:21]
        tgtPages_2 <= tgtPageUpdate; // @[BTB.scala 269:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h3 == waddr) begin // @[BTB.scala 269:21]
        tgtPages_3 <= tgtPageUpdate; // @[BTB.scala 269:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h4 == waddr) begin // @[BTB.scala 269:21]
        tgtPages_4 <= tgtPageUpdate; // @[BTB.scala 269:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h5 == waddr) begin // @[BTB.scala 269:21]
        tgtPages_5 <= tgtPageUpdate; // @[BTB.scala 269:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h6 == waddr) begin // @[BTB.scala 269:21]
        tgtPages_6 <= tgtPageUpdate; // @[BTB.scala 269:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h7 == waddr) begin // @[BTB.scala 269:21]
        tgtPages_7 <= tgtPageUpdate; // @[BTB.scala 269:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h8 == waddr) begin // @[BTB.scala 269:21]
        tgtPages_8 <= tgtPageUpdate; // @[BTB.scala 269:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h9 == waddr) begin // @[BTB.scala 269:21]
        tgtPages_9 <= tgtPageUpdate; // @[BTB.scala 269:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'ha == waddr) begin // @[BTB.scala 269:21]
        tgtPages_10 <= tgtPageUpdate; // @[BTB.scala 269:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'hb == waddr) begin // @[BTB.scala 269:21]
        tgtPages_11 <= tgtPageUpdate; // @[BTB.scala 269:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'hc == waddr) begin // @[BTB.scala 269:21]
        tgtPages_12 <= tgtPageUpdate; // @[BTB.scala 269:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'hd == waddr) begin // @[BTB.scala 269:21]
        tgtPages_13 <= tgtPageUpdate; // @[BTB.scala 269:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'he == waddr) begin // @[BTB.scala 269:21]
        tgtPages_14 <= tgtPageUpdate; // @[BTB.scala 269:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'hf == waddr) begin // @[BTB.scala 269:21]
        tgtPages_15 <= tgtPageUpdate; // @[BTB.scala 269:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h10 == waddr) begin // @[BTB.scala 269:21]
        tgtPages_16 <= tgtPageUpdate; // @[BTB.scala 269:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h11 == waddr) begin // @[BTB.scala 269:21]
        tgtPages_17 <= tgtPageUpdate; // @[BTB.scala 269:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h12 == waddr) begin // @[BTB.scala 269:21]
        tgtPages_18 <= tgtPageUpdate; // @[BTB.scala 269:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h13 == waddr) begin // @[BTB.scala 269:21]
        tgtPages_19 <= tgtPageUpdate; // @[BTB.scala 269:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h14 == waddr) begin // @[BTB.scala 269:21]
        tgtPages_20 <= tgtPageUpdate; // @[BTB.scala 269:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h15 == waddr) begin // @[BTB.scala 269:21]
        tgtPages_21 <= tgtPageUpdate; // @[BTB.scala 269:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h16 == waddr) begin // @[BTB.scala 269:21]
        tgtPages_22 <= tgtPageUpdate; // @[BTB.scala 269:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h17 == waddr) begin // @[BTB.scala 269:21]
        tgtPages_23 <= tgtPageUpdate; // @[BTB.scala 269:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h18 == waddr) begin // @[BTB.scala 269:21]
        tgtPages_24 <= tgtPageUpdate; // @[BTB.scala 269:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h19 == waddr) begin // @[BTB.scala 269:21]
        tgtPages_25 <= tgtPageUpdate; // @[BTB.scala 269:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h1a == waddr) begin // @[BTB.scala 269:21]
        tgtPages_26 <= tgtPageUpdate; // @[BTB.scala 269:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h1b == waddr) begin // @[BTB.scala 269:21]
        tgtPages_27 <= tgtPageUpdate; // @[BTB.scala 269:21]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (_T_5[0]) begin // @[BTB.scala 280:22]
        if (idxWritesEven) begin // @[BTB.scala 283:10]
          pages_0 <= updatePageHit_p;
        end else begin
          pages_0 <= pageHit_p;
        end
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (_T_12[1]) begin // @[BTB.scala 280:22]
        if (idxWritesEven) begin // @[BTB.scala 285:10]
          pages_1 <= pageHit_p;
        end else begin
          pages_1 <= updatePageHit_p;
        end
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (_T_5[2]) begin // @[BTB.scala 280:22]
        if (idxWritesEven) begin // @[BTB.scala 283:10]
          pages_2 <= updatePageHit_p;
        end else begin
          pages_2 <= pageHit_p;
        end
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (_T_12[3]) begin // @[BTB.scala 280:22]
        if (idxWritesEven) begin // @[BTB.scala 285:10]
          pages_3 <= pageHit_p;
        end else begin
          pages_3 <= updatePageHit_p;
        end
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (_T_5[4]) begin // @[BTB.scala 280:22]
        if (idxWritesEven) begin // @[BTB.scala 283:10]
          pages_4 <= updatePageHit_p;
        end else begin
          pages_4 <= pageHit_p;
        end
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (_T_12[5]) begin // @[BTB.scala 280:22]
        if (idxWritesEven) begin // @[BTB.scala 285:10]
          pages_5 <= pageHit_p;
        end else begin
          pages_5 <= updatePageHit_p;
        end
      end
    end
    if (reset) begin // @[BTB.scala 206:22]
      pageValid <= 6'h0; // @[BTB.scala 206:22]
    end else begin
      pageValid <= _GEN_373[5:0];
    end
    if (reset) begin // @[BTB.scala 209:20]
      isValid <= 28'h0; // @[BTB.scala 209:20]
    end else begin
      isValid <= _GEN_375[27:0];
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h0 == waddr) begin // @[BTB.scala 270:20]
        cfiType_0 <= r_btb_updatePipe_bits_cfiType; // @[BTB.scala 270:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h1 == waddr) begin // @[BTB.scala 270:20]
        cfiType_1 <= r_btb_updatePipe_bits_cfiType; // @[BTB.scala 270:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h2 == waddr) begin // @[BTB.scala 270:20]
        cfiType_2 <= r_btb_updatePipe_bits_cfiType; // @[BTB.scala 270:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h3 == waddr) begin // @[BTB.scala 270:20]
        cfiType_3 <= r_btb_updatePipe_bits_cfiType; // @[BTB.scala 270:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h4 == waddr) begin // @[BTB.scala 270:20]
        cfiType_4 <= r_btb_updatePipe_bits_cfiType; // @[BTB.scala 270:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h5 == waddr) begin // @[BTB.scala 270:20]
        cfiType_5 <= r_btb_updatePipe_bits_cfiType; // @[BTB.scala 270:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h6 == waddr) begin // @[BTB.scala 270:20]
        cfiType_6 <= r_btb_updatePipe_bits_cfiType; // @[BTB.scala 270:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h7 == waddr) begin // @[BTB.scala 270:20]
        cfiType_7 <= r_btb_updatePipe_bits_cfiType; // @[BTB.scala 270:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h8 == waddr) begin // @[BTB.scala 270:20]
        cfiType_8 <= r_btb_updatePipe_bits_cfiType; // @[BTB.scala 270:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h9 == waddr) begin // @[BTB.scala 270:20]
        cfiType_9 <= r_btb_updatePipe_bits_cfiType; // @[BTB.scala 270:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'ha == waddr) begin // @[BTB.scala 270:20]
        cfiType_10 <= r_btb_updatePipe_bits_cfiType; // @[BTB.scala 270:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'hb == waddr) begin // @[BTB.scala 270:20]
        cfiType_11 <= r_btb_updatePipe_bits_cfiType; // @[BTB.scala 270:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'hc == waddr) begin // @[BTB.scala 270:20]
        cfiType_12 <= r_btb_updatePipe_bits_cfiType; // @[BTB.scala 270:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'hd == waddr) begin // @[BTB.scala 270:20]
        cfiType_13 <= r_btb_updatePipe_bits_cfiType; // @[BTB.scala 270:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'he == waddr) begin // @[BTB.scala 270:20]
        cfiType_14 <= r_btb_updatePipe_bits_cfiType; // @[BTB.scala 270:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'hf == waddr) begin // @[BTB.scala 270:20]
        cfiType_15 <= r_btb_updatePipe_bits_cfiType; // @[BTB.scala 270:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h10 == waddr) begin // @[BTB.scala 270:20]
        cfiType_16 <= r_btb_updatePipe_bits_cfiType; // @[BTB.scala 270:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h11 == waddr) begin // @[BTB.scala 270:20]
        cfiType_17 <= r_btb_updatePipe_bits_cfiType; // @[BTB.scala 270:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h12 == waddr) begin // @[BTB.scala 270:20]
        cfiType_18 <= r_btb_updatePipe_bits_cfiType; // @[BTB.scala 270:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h13 == waddr) begin // @[BTB.scala 270:20]
        cfiType_19 <= r_btb_updatePipe_bits_cfiType; // @[BTB.scala 270:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h14 == waddr) begin // @[BTB.scala 270:20]
        cfiType_20 <= r_btb_updatePipe_bits_cfiType; // @[BTB.scala 270:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h15 == waddr) begin // @[BTB.scala 270:20]
        cfiType_21 <= r_btb_updatePipe_bits_cfiType; // @[BTB.scala 270:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h16 == waddr) begin // @[BTB.scala 270:20]
        cfiType_22 <= r_btb_updatePipe_bits_cfiType; // @[BTB.scala 270:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h17 == waddr) begin // @[BTB.scala 270:20]
        cfiType_23 <= r_btb_updatePipe_bits_cfiType; // @[BTB.scala 270:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h18 == waddr) begin // @[BTB.scala 270:20]
        cfiType_24 <= r_btb_updatePipe_bits_cfiType; // @[BTB.scala 270:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h19 == waddr) begin // @[BTB.scala 270:20]
        cfiType_25 <= r_btb_updatePipe_bits_cfiType; // @[BTB.scala 270:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h1a == waddr) begin // @[BTB.scala 270:20]
        cfiType_26 <= r_btb_updatePipe_bits_cfiType; // @[BTB.scala 270:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h1b == waddr) begin // @[BTB.scala 270:20]
        cfiType_27 <= r_btb_updatePipe_bits_cfiType; // @[BTB.scala 270:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h0 == waddr) begin // @[BTB.scala 273:20]
        brIdx_0 <= r_btb_updatePipe_bits_br_pc[1]; // @[BTB.scala 273:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h1 == waddr) begin // @[BTB.scala 273:20]
        brIdx_1 <= r_btb_updatePipe_bits_br_pc[1]; // @[BTB.scala 273:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h2 == waddr) begin // @[BTB.scala 273:20]
        brIdx_2 <= r_btb_updatePipe_bits_br_pc[1]; // @[BTB.scala 273:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h3 == waddr) begin // @[BTB.scala 273:20]
        brIdx_3 <= r_btb_updatePipe_bits_br_pc[1]; // @[BTB.scala 273:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h4 == waddr) begin // @[BTB.scala 273:20]
        brIdx_4 <= r_btb_updatePipe_bits_br_pc[1]; // @[BTB.scala 273:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h5 == waddr) begin // @[BTB.scala 273:20]
        brIdx_5 <= r_btb_updatePipe_bits_br_pc[1]; // @[BTB.scala 273:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h6 == waddr) begin // @[BTB.scala 273:20]
        brIdx_6 <= r_btb_updatePipe_bits_br_pc[1]; // @[BTB.scala 273:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h7 == waddr) begin // @[BTB.scala 273:20]
        brIdx_7 <= r_btb_updatePipe_bits_br_pc[1]; // @[BTB.scala 273:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h8 == waddr) begin // @[BTB.scala 273:20]
        brIdx_8 <= r_btb_updatePipe_bits_br_pc[1]; // @[BTB.scala 273:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h9 == waddr) begin // @[BTB.scala 273:20]
        brIdx_9 <= r_btb_updatePipe_bits_br_pc[1]; // @[BTB.scala 273:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'ha == waddr) begin // @[BTB.scala 273:20]
        brIdx_10 <= r_btb_updatePipe_bits_br_pc[1]; // @[BTB.scala 273:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'hb == waddr) begin // @[BTB.scala 273:20]
        brIdx_11 <= r_btb_updatePipe_bits_br_pc[1]; // @[BTB.scala 273:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'hc == waddr) begin // @[BTB.scala 273:20]
        brIdx_12 <= r_btb_updatePipe_bits_br_pc[1]; // @[BTB.scala 273:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'hd == waddr) begin // @[BTB.scala 273:20]
        brIdx_13 <= r_btb_updatePipe_bits_br_pc[1]; // @[BTB.scala 273:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'he == waddr) begin // @[BTB.scala 273:20]
        brIdx_14 <= r_btb_updatePipe_bits_br_pc[1]; // @[BTB.scala 273:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'hf == waddr) begin // @[BTB.scala 273:20]
        brIdx_15 <= r_btb_updatePipe_bits_br_pc[1]; // @[BTB.scala 273:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h10 == waddr) begin // @[BTB.scala 273:20]
        brIdx_16 <= r_btb_updatePipe_bits_br_pc[1]; // @[BTB.scala 273:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h11 == waddr) begin // @[BTB.scala 273:20]
        brIdx_17 <= r_btb_updatePipe_bits_br_pc[1]; // @[BTB.scala 273:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h12 == waddr) begin // @[BTB.scala 273:20]
        brIdx_18 <= r_btb_updatePipe_bits_br_pc[1]; // @[BTB.scala 273:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h13 == waddr) begin // @[BTB.scala 273:20]
        brIdx_19 <= r_btb_updatePipe_bits_br_pc[1]; // @[BTB.scala 273:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h14 == waddr) begin // @[BTB.scala 273:20]
        brIdx_20 <= r_btb_updatePipe_bits_br_pc[1]; // @[BTB.scala 273:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h15 == waddr) begin // @[BTB.scala 273:20]
        brIdx_21 <= r_btb_updatePipe_bits_br_pc[1]; // @[BTB.scala 273:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h16 == waddr) begin // @[BTB.scala 273:20]
        brIdx_22 <= r_btb_updatePipe_bits_br_pc[1]; // @[BTB.scala 273:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h17 == waddr) begin // @[BTB.scala 273:20]
        brIdx_23 <= r_btb_updatePipe_bits_br_pc[1]; // @[BTB.scala 273:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h18 == waddr) begin // @[BTB.scala 273:20]
        brIdx_24 <= r_btb_updatePipe_bits_br_pc[1]; // @[BTB.scala 273:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h19 == waddr) begin // @[BTB.scala 273:20]
        brIdx_25 <= r_btb_updatePipe_bits_br_pc[1]; // @[BTB.scala 273:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h1a == waddr) begin // @[BTB.scala 273:20]
        brIdx_26 <= r_btb_updatePipe_bits_br_pc[1]; // @[BTB.scala 273:20]
      end
    end
    if (r_btb_updatePipe_valid) begin // @[BTB.scala 264:29]
      if (5'h1b == waddr) begin // @[BTB.scala 273:20]
        brIdx_27 <= r_btb_updatePipe_bits_br_pc[1]; // @[BTB.scala 273:20]
      end
    end
    if (reset) begin // @[Valid.scala 127:22]
      r_btb_updatePipe_valid <= 1'h0; // @[Valid.scala 127:22]
    end else begin
      r_btb_updatePipe_valid <= io_btb_update_valid; // @[Valid.scala 127:22]
    end
    if (io_btb_update_valid) begin // @[Reg.scala 17:18]
      r_btb_updatePipe_bits_prediction_entry <= io_btb_update_bits_prediction_entry; // @[Reg.scala 17:22]
    end
    if (io_btb_update_valid) begin // @[Reg.scala 17:18]
      r_btb_updatePipe_bits_pc <= io_btb_update_bits_pc; // @[Reg.scala 17:22]
    end
    if (io_btb_update_valid) begin // @[Reg.scala 17:18]
      r_btb_updatePipe_bits_isValid <= io_btb_update_bits_isValid; // @[Reg.scala 17:22]
    end
    if (io_btb_update_valid) begin // @[Reg.scala 17:18]
      r_btb_updatePipe_bits_br_pc <= io_btb_update_bits_br_pc; // @[Reg.scala 17:22]
    end
    if (io_btb_update_valid) begin // @[Reg.scala 17:18]
      r_btb_updatePipe_bits_cfiType <= io_btb_update_bits_cfiType; // @[Reg.scala 17:22]
    end
    if (reset) begin // @[BTB.scala 239:29]
      nextPageRepl <= 3'h0; // @[BTB.scala 239:29]
    end else if (r_btb_updatePipe_valid & (doIdxPageRepl | doTgtPageRepl)) begin // @[BTB.scala 251:65]
      if (next >= 3'h6) begin // @[BTB.scala 254:24]
        nextPageRepl <= {{2'd0}, next[0]};
      end else begin
        nextPageRepl <= next;
      end
    end
    if (reset) begin // @[Replacement.scala 168:70]
      state_reg <= 27'h0; // @[Replacement.scala 168:70]
    end else if (r_respPipe_valid & r_respPipe_bits_taken | r_btb_updatePipe_valid) begin // @[BTB.scala 260:66]
      state_reg <= _state_reg_T_92; // @[Replacement.scala 172:15]
    end
    if (reset) begin // @[Valid.scala 127:22]
      r_respPipe_valid <= 1'h0; // @[Valid.scala 127:22]
    end else begin
      r_respPipe_valid <= io_resp_valid; // @[Valid.scala 127:22]
    end
    if (io_resp_valid) begin // @[Reg.scala 17:18]
      r_respPipe_bits_taken <= io_resp_bits_taken; // @[Reg.scala 17:22]
    end
    if (io_resp_valid) begin // @[Reg.scala 17:18]
      r_respPipe_bits_entry <= io_resp_bits_entry; // @[Reg.scala 17:22]
    end
    if (reset) begin // @[BTB.scala 119:24]
      history <= 8'h0; // @[BTB.scala 119:24]
    end else if (io_bht_update_valid) begin // @[BTB.scala 312:32]
      if (io_bht_update_bits_branch) begin // @[BTB.scala 313:40]
        if (io_bht_update_bits_mispredict) begin // @[BTB.scala 315:46]
          history <= _history_T_3; // @[BTB.scala 112:13]
        end else begin
          history <= _GEN_382;
        end
      end else if (io_bht_update_bits_mispredict) begin // @[BTB.scala 318:50]
        history <= io_bht_update_bits_prediction_history; // @[BTB.scala 109:13]
      end else begin
        history <= _GEN_382;
      end
    end else begin
      history <= _GEN_382;
    end
    if (reset) begin // @[BTB.scala 121:36]
      reset_waddr <= 10'h0; // @[BTB.scala 121:36]
    end else if (resetting) begin // @[BTB.scala 126:20]
      reset_waddr <= _reset_waddr_T_1; // @[BTB.scala 126:34]
    end
    if (reset) begin // @[BTB.scala 58:30]
      count <= 3'h0; // @[BTB.scala 58:30]
    end else if (io_ras_update_valid) begin // @[BTB.scala 334:32]
      if (io_ras_update_bits_cfiType == 2'h2) begin // @[BTB.scala 335:58]
        if (count < 3'h6) begin // @[BTB.scala 45:25]
          count <= _count_T_1; // @[BTB.scala 45:33]
        end
      end else if (io_ras_update_bits_cfiType == 2'h3) begin // @[BTB.scala 337:63]
        count <= _GEN_410;
      end
    end
    if (reset) begin // @[BTB.scala 59:28]
      pos <= 3'h0; // @[BTB.scala 59:28]
    end else if (io_ras_update_valid) begin // @[BTB.scala 334:32]
      if (io_ras_update_bits_cfiType == 2'h2) begin // @[BTB.scala 335:58]
        if (pos < 3'h5) begin // @[BTB.scala 46:22]
          pos <= _nextPos_T_3;
        end else begin
          pos <= 3'h0;
        end
      end else if (io_ras_update_bits_cfiType == 2'h3) begin // @[BTB.scala 337:63]
        pos <= _GEN_411;
      end
    end
    if (io_ras_update_valid) begin // @[BTB.scala 334:32]
      if (io_ras_update_bits_cfiType == 2'h2) begin // @[BTB.scala 335:58]
        if (3'h0 == nextPos) begin // @[BTB.scala 47:20]
          stack_0 <= io_ras_update_bits_returnAddr; // @[BTB.scala 47:20]
        end
      end
    end
    if (io_ras_update_valid) begin // @[BTB.scala 334:32]
      if (io_ras_update_bits_cfiType == 2'h2) begin // @[BTB.scala 335:58]
        if (3'h1 == nextPos) begin // @[BTB.scala 47:20]
          stack_1 <= io_ras_update_bits_returnAddr; // @[BTB.scala 47:20]
        end
      end
    end
    if (io_ras_update_valid) begin // @[BTB.scala 334:32]
      if (io_ras_update_bits_cfiType == 2'h2) begin // @[BTB.scala 335:58]
        if (3'h2 == nextPos) begin // @[BTB.scala 47:20]
          stack_2 <= io_ras_update_bits_returnAddr; // @[BTB.scala 47:20]
        end
      end
    end
    if (io_ras_update_valid) begin // @[BTB.scala 334:32]
      if (io_ras_update_bits_cfiType == 2'h2) begin // @[BTB.scala 335:58]
        if (3'h3 == nextPos) begin // @[BTB.scala 47:20]
          stack_3 <= io_ras_update_bits_returnAddr; // @[BTB.scala 47:20]
        end
      end
    end
    if (io_ras_update_valid) begin // @[BTB.scala 334:32]
      if (io_ras_update_bits_cfiType == 2'h2) begin // @[BTB.scala 335:58]
        if (3'h4 == nextPos) begin // @[BTB.scala 47:20]
          stack_4 <= io_ras_update_bits_returnAddr; // @[BTB.scala 47:20]
        end
      end
    end
    if (io_ras_update_valid) begin // @[BTB.scala 334:32]
      if (io_ras_update_bits_cfiType == 2'h2) begin // @[BTB.scala 335:58]
        if (3'h5 == nextPos) begin // @[BTB.scala 47:20]
          stack_5 <= io_ras_update_bits_returnAddr; // @[BTB.scala 47:20]
        end
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 512; initvar = initvar+1)
    table_[initvar] = _RAND_0[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_1 = {1{`RANDOM}};
  idxs_0 = _RAND_1[12:0];
  _RAND_2 = {1{`RANDOM}};
  idxs_1 = _RAND_2[12:0];
  _RAND_3 = {1{`RANDOM}};
  idxs_2 = _RAND_3[12:0];
  _RAND_4 = {1{`RANDOM}};
  idxs_3 = _RAND_4[12:0];
  _RAND_5 = {1{`RANDOM}};
  idxs_4 = _RAND_5[12:0];
  _RAND_6 = {1{`RANDOM}};
  idxs_5 = _RAND_6[12:0];
  _RAND_7 = {1{`RANDOM}};
  idxs_6 = _RAND_7[12:0];
  _RAND_8 = {1{`RANDOM}};
  idxs_7 = _RAND_8[12:0];
  _RAND_9 = {1{`RANDOM}};
  idxs_8 = _RAND_9[12:0];
  _RAND_10 = {1{`RANDOM}};
  idxs_9 = _RAND_10[12:0];
  _RAND_11 = {1{`RANDOM}};
  idxs_10 = _RAND_11[12:0];
  _RAND_12 = {1{`RANDOM}};
  idxs_11 = _RAND_12[12:0];
  _RAND_13 = {1{`RANDOM}};
  idxs_12 = _RAND_13[12:0];
  _RAND_14 = {1{`RANDOM}};
  idxs_13 = _RAND_14[12:0];
  _RAND_15 = {1{`RANDOM}};
  idxs_14 = _RAND_15[12:0];
  _RAND_16 = {1{`RANDOM}};
  idxs_15 = _RAND_16[12:0];
  _RAND_17 = {1{`RANDOM}};
  idxs_16 = _RAND_17[12:0];
  _RAND_18 = {1{`RANDOM}};
  idxs_17 = _RAND_18[12:0];
  _RAND_19 = {1{`RANDOM}};
  idxs_18 = _RAND_19[12:0];
  _RAND_20 = {1{`RANDOM}};
  idxs_19 = _RAND_20[12:0];
  _RAND_21 = {1{`RANDOM}};
  idxs_20 = _RAND_21[12:0];
  _RAND_22 = {1{`RANDOM}};
  idxs_21 = _RAND_22[12:0];
  _RAND_23 = {1{`RANDOM}};
  idxs_22 = _RAND_23[12:0];
  _RAND_24 = {1{`RANDOM}};
  idxs_23 = _RAND_24[12:0];
  _RAND_25 = {1{`RANDOM}};
  idxs_24 = _RAND_25[12:0];
  _RAND_26 = {1{`RANDOM}};
  idxs_25 = _RAND_26[12:0];
  _RAND_27 = {1{`RANDOM}};
  idxs_26 = _RAND_27[12:0];
  _RAND_28 = {1{`RANDOM}};
  idxs_27 = _RAND_28[12:0];
  _RAND_29 = {1{`RANDOM}};
  idxPages_0 = _RAND_29[2:0];
  _RAND_30 = {1{`RANDOM}};
  idxPages_1 = _RAND_30[2:0];
  _RAND_31 = {1{`RANDOM}};
  idxPages_2 = _RAND_31[2:0];
  _RAND_32 = {1{`RANDOM}};
  idxPages_3 = _RAND_32[2:0];
  _RAND_33 = {1{`RANDOM}};
  idxPages_4 = _RAND_33[2:0];
  _RAND_34 = {1{`RANDOM}};
  idxPages_5 = _RAND_34[2:0];
  _RAND_35 = {1{`RANDOM}};
  idxPages_6 = _RAND_35[2:0];
  _RAND_36 = {1{`RANDOM}};
  idxPages_7 = _RAND_36[2:0];
  _RAND_37 = {1{`RANDOM}};
  idxPages_8 = _RAND_37[2:0];
  _RAND_38 = {1{`RANDOM}};
  idxPages_9 = _RAND_38[2:0];
  _RAND_39 = {1{`RANDOM}};
  idxPages_10 = _RAND_39[2:0];
  _RAND_40 = {1{`RANDOM}};
  idxPages_11 = _RAND_40[2:0];
  _RAND_41 = {1{`RANDOM}};
  idxPages_12 = _RAND_41[2:0];
  _RAND_42 = {1{`RANDOM}};
  idxPages_13 = _RAND_42[2:0];
  _RAND_43 = {1{`RANDOM}};
  idxPages_14 = _RAND_43[2:0];
  _RAND_44 = {1{`RANDOM}};
  idxPages_15 = _RAND_44[2:0];
  _RAND_45 = {1{`RANDOM}};
  idxPages_16 = _RAND_45[2:0];
  _RAND_46 = {1{`RANDOM}};
  idxPages_17 = _RAND_46[2:0];
  _RAND_47 = {1{`RANDOM}};
  idxPages_18 = _RAND_47[2:0];
  _RAND_48 = {1{`RANDOM}};
  idxPages_19 = _RAND_48[2:0];
  _RAND_49 = {1{`RANDOM}};
  idxPages_20 = _RAND_49[2:0];
  _RAND_50 = {1{`RANDOM}};
  idxPages_21 = _RAND_50[2:0];
  _RAND_51 = {1{`RANDOM}};
  idxPages_22 = _RAND_51[2:0];
  _RAND_52 = {1{`RANDOM}};
  idxPages_23 = _RAND_52[2:0];
  _RAND_53 = {1{`RANDOM}};
  idxPages_24 = _RAND_53[2:0];
  _RAND_54 = {1{`RANDOM}};
  idxPages_25 = _RAND_54[2:0];
  _RAND_55 = {1{`RANDOM}};
  idxPages_26 = _RAND_55[2:0];
  _RAND_56 = {1{`RANDOM}};
  idxPages_27 = _RAND_56[2:0];
  _RAND_57 = {1{`RANDOM}};
  tgts_0 = _RAND_57[12:0];
  _RAND_58 = {1{`RANDOM}};
  tgts_1 = _RAND_58[12:0];
  _RAND_59 = {1{`RANDOM}};
  tgts_2 = _RAND_59[12:0];
  _RAND_60 = {1{`RANDOM}};
  tgts_3 = _RAND_60[12:0];
  _RAND_61 = {1{`RANDOM}};
  tgts_4 = _RAND_61[12:0];
  _RAND_62 = {1{`RANDOM}};
  tgts_5 = _RAND_62[12:0];
  _RAND_63 = {1{`RANDOM}};
  tgts_6 = _RAND_63[12:0];
  _RAND_64 = {1{`RANDOM}};
  tgts_7 = _RAND_64[12:0];
  _RAND_65 = {1{`RANDOM}};
  tgts_8 = _RAND_65[12:0];
  _RAND_66 = {1{`RANDOM}};
  tgts_9 = _RAND_66[12:0];
  _RAND_67 = {1{`RANDOM}};
  tgts_10 = _RAND_67[12:0];
  _RAND_68 = {1{`RANDOM}};
  tgts_11 = _RAND_68[12:0];
  _RAND_69 = {1{`RANDOM}};
  tgts_12 = _RAND_69[12:0];
  _RAND_70 = {1{`RANDOM}};
  tgts_13 = _RAND_70[12:0];
  _RAND_71 = {1{`RANDOM}};
  tgts_14 = _RAND_71[12:0];
  _RAND_72 = {1{`RANDOM}};
  tgts_15 = _RAND_72[12:0];
  _RAND_73 = {1{`RANDOM}};
  tgts_16 = _RAND_73[12:0];
  _RAND_74 = {1{`RANDOM}};
  tgts_17 = _RAND_74[12:0];
  _RAND_75 = {1{`RANDOM}};
  tgts_18 = _RAND_75[12:0];
  _RAND_76 = {1{`RANDOM}};
  tgts_19 = _RAND_76[12:0];
  _RAND_77 = {1{`RANDOM}};
  tgts_20 = _RAND_77[12:0];
  _RAND_78 = {1{`RANDOM}};
  tgts_21 = _RAND_78[12:0];
  _RAND_79 = {1{`RANDOM}};
  tgts_22 = _RAND_79[12:0];
  _RAND_80 = {1{`RANDOM}};
  tgts_23 = _RAND_80[12:0];
  _RAND_81 = {1{`RANDOM}};
  tgts_24 = _RAND_81[12:0];
  _RAND_82 = {1{`RANDOM}};
  tgts_25 = _RAND_82[12:0];
  _RAND_83 = {1{`RANDOM}};
  tgts_26 = _RAND_83[12:0];
  _RAND_84 = {1{`RANDOM}};
  tgts_27 = _RAND_84[12:0];
  _RAND_85 = {1{`RANDOM}};
  tgtPages_0 = _RAND_85[2:0];
  _RAND_86 = {1{`RANDOM}};
  tgtPages_1 = _RAND_86[2:0];
  _RAND_87 = {1{`RANDOM}};
  tgtPages_2 = _RAND_87[2:0];
  _RAND_88 = {1{`RANDOM}};
  tgtPages_3 = _RAND_88[2:0];
  _RAND_89 = {1{`RANDOM}};
  tgtPages_4 = _RAND_89[2:0];
  _RAND_90 = {1{`RANDOM}};
  tgtPages_5 = _RAND_90[2:0];
  _RAND_91 = {1{`RANDOM}};
  tgtPages_6 = _RAND_91[2:0];
  _RAND_92 = {1{`RANDOM}};
  tgtPages_7 = _RAND_92[2:0];
  _RAND_93 = {1{`RANDOM}};
  tgtPages_8 = _RAND_93[2:0];
  _RAND_94 = {1{`RANDOM}};
  tgtPages_9 = _RAND_94[2:0];
  _RAND_95 = {1{`RANDOM}};
  tgtPages_10 = _RAND_95[2:0];
  _RAND_96 = {1{`RANDOM}};
  tgtPages_11 = _RAND_96[2:0];
  _RAND_97 = {1{`RANDOM}};
  tgtPages_12 = _RAND_97[2:0];
  _RAND_98 = {1{`RANDOM}};
  tgtPages_13 = _RAND_98[2:0];
  _RAND_99 = {1{`RANDOM}};
  tgtPages_14 = _RAND_99[2:0];
  _RAND_100 = {1{`RANDOM}};
  tgtPages_15 = _RAND_100[2:0];
  _RAND_101 = {1{`RANDOM}};
  tgtPages_16 = _RAND_101[2:0];
  _RAND_102 = {1{`RANDOM}};
  tgtPages_17 = _RAND_102[2:0];
  _RAND_103 = {1{`RANDOM}};
  tgtPages_18 = _RAND_103[2:0];
  _RAND_104 = {1{`RANDOM}};
  tgtPages_19 = _RAND_104[2:0];
  _RAND_105 = {1{`RANDOM}};
  tgtPages_20 = _RAND_105[2:0];
  _RAND_106 = {1{`RANDOM}};
  tgtPages_21 = _RAND_106[2:0];
  _RAND_107 = {1{`RANDOM}};
  tgtPages_22 = _RAND_107[2:0];
  _RAND_108 = {1{`RANDOM}};
  tgtPages_23 = _RAND_108[2:0];
  _RAND_109 = {1{`RANDOM}};
  tgtPages_24 = _RAND_109[2:0];
  _RAND_110 = {1{`RANDOM}};
  tgtPages_25 = _RAND_110[2:0];
  _RAND_111 = {1{`RANDOM}};
  tgtPages_26 = _RAND_111[2:0];
  _RAND_112 = {1{`RANDOM}};
  tgtPages_27 = _RAND_112[2:0];
  _RAND_113 = {1{`RANDOM}};
  pages_0 = _RAND_113[17:0];
  _RAND_114 = {1{`RANDOM}};
  pages_1 = _RAND_114[17:0];
  _RAND_115 = {1{`RANDOM}};
  pages_2 = _RAND_115[17:0];
  _RAND_116 = {1{`RANDOM}};
  pages_3 = _RAND_116[17:0];
  _RAND_117 = {1{`RANDOM}};
  pages_4 = _RAND_117[17:0];
  _RAND_118 = {1{`RANDOM}};
  pages_5 = _RAND_118[17:0];
  _RAND_119 = {1{`RANDOM}};
  pageValid = _RAND_119[5:0];
  _RAND_120 = {1{`RANDOM}};
  isValid = _RAND_120[27:0];
  _RAND_121 = {1{`RANDOM}};
  cfiType_0 = _RAND_121[1:0];
  _RAND_122 = {1{`RANDOM}};
  cfiType_1 = _RAND_122[1:0];
  _RAND_123 = {1{`RANDOM}};
  cfiType_2 = _RAND_123[1:0];
  _RAND_124 = {1{`RANDOM}};
  cfiType_3 = _RAND_124[1:0];
  _RAND_125 = {1{`RANDOM}};
  cfiType_4 = _RAND_125[1:0];
  _RAND_126 = {1{`RANDOM}};
  cfiType_5 = _RAND_126[1:0];
  _RAND_127 = {1{`RANDOM}};
  cfiType_6 = _RAND_127[1:0];
  _RAND_128 = {1{`RANDOM}};
  cfiType_7 = _RAND_128[1:0];
  _RAND_129 = {1{`RANDOM}};
  cfiType_8 = _RAND_129[1:0];
  _RAND_130 = {1{`RANDOM}};
  cfiType_9 = _RAND_130[1:0];
  _RAND_131 = {1{`RANDOM}};
  cfiType_10 = _RAND_131[1:0];
  _RAND_132 = {1{`RANDOM}};
  cfiType_11 = _RAND_132[1:0];
  _RAND_133 = {1{`RANDOM}};
  cfiType_12 = _RAND_133[1:0];
  _RAND_134 = {1{`RANDOM}};
  cfiType_13 = _RAND_134[1:0];
  _RAND_135 = {1{`RANDOM}};
  cfiType_14 = _RAND_135[1:0];
  _RAND_136 = {1{`RANDOM}};
  cfiType_15 = _RAND_136[1:0];
  _RAND_137 = {1{`RANDOM}};
  cfiType_16 = _RAND_137[1:0];
  _RAND_138 = {1{`RANDOM}};
  cfiType_17 = _RAND_138[1:0];
  _RAND_139 = {1{`RANDOM}};
  cfiType_18 = _RAND_139[1:0];
  _RAND_140 = {1{`RANDOM}};
  cfiType_19 = _RAND_140[1:0];
  _RAND_141 = {1{`RANDOM}};
  cfiType_20 = _RAND_141[1:0];
  _RAND_142 = {1{`RANDOM}};
  cfiType_21 = _RAND_142[1:0];
  _RAND_143 = {1{`RANDOM}};
  cfiType_22 = _RAND_143[1:0];
  _RAND_144 = {1{`RANDOM}};
  cfiType_23 = _RAND_144[1:0];
  _RAND_145 = {1{`RANDOM}};
  cfiType_24 = _RAND_145[1:0];
  _RAND_146 = {1{`RANDOM}};
  cfiType_25 = _RAND_146[1:0];
  _RAND_147 = {1{`RANDOM}};
  cfiType_26 = _RAND_147[1:0];
  _RAND_148 = {1{`RANDOM}};
  cfiType_27 = _RAND_148[1:0];
  _RAND_149 = {1{`RANDOM}};
  brIdx_0 = _RAND_149[0:0];
  _RAND_150 = {1{`RANDOM}};
  brIdx_1 = _RAND_150[0:0];
  _RAND_151 = {1{`RANDOM}};
  brIdx_2 = _RAND_151[0:0];
  _RAND_152 = {1{`RANDOM}};
  brIdx_3 = _RAND_152[0:0];
  _RAND_153 = {1{`RANDOM}};
  brIdx_4 = _RAND_153[0:0];
  _RAND_154 = {1{`RANDOM}};
  brIdx_5 = _RAND_154[0:0];
  _RAND_155 = {1{`RANDOM}};
  brIdx_6 = _RAND_155[0:0];
  _RAND_156 = {1{`RANDOM}};
  brIdx_7 = _RAND_156[0:0];
  _RAND_157 = {1{`RANDOM}};
  brIdx_8 = _RAND_157[0:0];
  _RAND_158 = {1{`RANDOM}};
  brIdx_9 = _RAND_158[0:0];
  _RAND_159 = {1{`RANDOM}};
  brIdx_10 = _RAND_159[0:0];
  _RAND_160 = {1{`RANDOM}};
  brIdx_11 = _RAND_160[0:0];
  _RAND_161 = {1{`RANDOM}};
  brIdx_12 = _RAND_161[0:0];
  _RAND_162 = {1{`RANDOM}};
  brIdx_13 = _RAND_162[0:0];
  _RAND_163 = {1{`RANDOM}};
  brIdx_14 = _RAND_163[0:0];
  _RAND_164 = {1{`RANDOM}};
  brIdx_15 = _RAND_164[0:0];
  _RAND_165 = {1{`RANDOM}};
  brIdx_16 = _RAND_165[0:0];
  _RAND_166 = {1{`RANDOM}};
  brIdx_17 = _RAND_166[0:0];
  _RAND_167 = {1{`RANDOM}};
  brIdx_18 = _RAND_167[0:0];
  _RAND_168 = {1{`RANDOM}};
  brIdx_19 = _RAND_168[0:0];
  _RAND_169 = {1{`RANDOM}};
  brIdx_20 = _RAND_169[0:0];
  _RAND_170 = {1{`RANDOM}};
  brIdx_21 = _RAND_170[0:0];
  _RAND_171 = {1{`RANDOM}};
  brIdx_22 = _RAND_171[0:0];
  _RAND_172 = {1{`RANDOM}};
  brIdx_23 = _RAND_172[0:0];
  _RAND_173 = {1{`RANDOM}};
  brIdx_24 = _RAND_173[0:0];
  _RAND_174 = {1{`RANDOM}};
  brIdx_25 = _RAND_174[0:0];
  _RAND_175 = {1{`RANDOM}};
  brIdx_26 = _RAND_175[0:0];
  _RAND_176 = {1{`RANDOM}};
  brIdx_27 = _RAND_176[0:0];
  _RAND_177 = {1{`RANDOM}};
  r_btb_updatePipe_valid = _RAND_177[0:0];
  _RAND_178 = {1{`RANDOM}};
  r_btb_updatePipe_bits_prediction_entry = _RAND_178[4:0];
  _RAND_179 = {1{`RANDOM}};
  r_btb_updatePipe_bits_pc = _RAND_179[31:0];
  _RAND_180 = {1{`RANDOM}};
  r_btb_updatePipe_bits_isValid = _RAND_180[0:0];
  _RAND_181 = {1{`RANDOM}};
  r_btb_updatePipe_bits_br_pc = _RAND_181[31:0];
  _RAND_182 = {1{`RANDOM}};
  r_btb_updatePipe_bits_cfiType = _RAND_182[1:0];
  _RAND_183 = {1{`RANDOM}};
  nextPageRepl = _RAND_183[2:0];
  _RAND_184 = {1{`RANDOM}};
  state_reg = _RAND_184[26:0];
  _RAND_185 = {1{`RANDOM}};
  r_respPipe_valid = _RAND_185[0:0];
  _RAND_186 = {1{`RANDOM}};
  r_respPipe_bits_taken = _RAND_186[0:0];
  _RAND_187 = {1{`RANDOM}};
  r_respPipe_bits_entry = _RAND_187[4:0];
  _RAND_188 = {1{`RANDOM}};
  history = _RAND_188[7:0];
  _RAND_189 = {1{`RANDOM}};
  reset_waddr = _RAND_189[9:0];
  _RAND_190 = {1{`RANDOM}};
  count = _RAND_190[2:0];
  _RAND_191 = {1{`RANDOM}};
  pos = _RAND_191[2:0];
  _RAND_192 = {1{`RANDOM}};
  stack_0 = _RAND_192[31:0];
  _RAND_193 = {1{`RANDOM}};
  stack_1 = _RAND_193[31:0];
  _RAND_194 = {1{`RANDOM}};
  stack_2 = _RAND_194[31:0];
  _RAND_195 = {1{`RANDOM}};
  stack_3 = _RAND_195[31:0];
  _RAND_196 = {1{`RANDOM}};
  stack_4 = _RAND_196[31:0];
  _RAND_197 = {1{`RANDOM}};
  stack_5 = _RAND_197[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Frontend(
  input         clock,
  input         reset,
  output        auto_icache_slave_in_a_ready,
  input         auto_icache_slave_in_a_valid,
  input  [2:0]  auto_icache_slave_in_a_bits_opcode,
  input  [1:0]  auto_icache_slave_in_a_bits_size,
  input  [7:0]  auto_icache_slave_in_a_bits_source,
  input  [27:0] auto_icache_slave_in_a_bits_address,
  input  [3:0]  auto_icache_slave_in_a_bits_mask,
  input  [31:0] auto_icache_slave_in_a_bits_data,
  input         auto_icache_slave_in_d_ready,
  output        auto_icache_slave_in_d_valid,
  output [2:0]  auto_icache_slave_in_d_bits_opcode,
  output [1:0]  auto_icache_slave_in_d_bits_size,
  output [7:0]  auto_icache_slave_in_d_bits_source,
  output [31:0] auto_icache_slave_in_d_bits_data,
  input         auto_icache_master_out_a_ready,
  output        auto_icache_master_out_a_valid,
  output [30:0] auto_icache_master_out_a_bits_address,
  output        auto_icache_master_out_d_ready,
  input         auto_icache_master_out_d_valid,
  input  [2:0]  auto_icache_master_out_d_bits_opcode,
  input  [3:0]  auto_icache_master_out_d_bits_size,
  input  [31:0] auto_icache_master_out_d_bits_data,
  input         auto_icache_master_out_d_bits_corrupt,
  input         io_cpu_might_request,
  input         io_cpu_req_valid,
  input  [31:0] io_cpu_req_bits_pc,
  input         io_cpu_req_bits_speculative,
  input         io_cpu_resp_ready,
  output        io_cpu_resp_valid,
  output        io_cpu_resp_bits_btb_taken,
  output        io_cpu_resp_bits_btb_bridx,
  output [4:0]  io_cpu_resp_bits_btb_entry,
  output [7:0]  io_cpu_resp_bits_btb_bht_history,
  output [31:0] io_cpu_resp_bits_pc,
  output [31:0] io_cpu_resp_bits_data,
  output        io_cpu_resp_bits_xcpt_ae_inst,
  output        io_cpu_resp_bits_replay,
  input         io_cpu_btb_update_valid,
  input  [4:0]  io_cpu_btb_update_bits_prediction_entry,
  input  [31:0] io_cpu_btb_update_bits_pc,
  input         io_cpu_btb_update_bits_isValid,
  input  [31:0] io_cpu_btb_update_bits_br_pc,
  input  [1:0]  io_cpu_btb_update_bits_cfiType,
  input         io_cpu_bht_update_valid,
  input  [7:0]  io_cpu_bht_update_bits_prediction_history,
  input  [31:0] io_cpu_bht_update_bits_pc,
  input         io_cpu_bht_update_bits_branch,
  input         io_cpu_bht_update_bits_taken,
  input         io_cpu_bht_update_bits_mispredict,
  input         io_cpu_flush_icache,
  output [31:0] io_cpu_npc,
  input         io_ptw_status_debug,
  input  [1:0]  io_ptw_status_prv,
  input         io_ptw_pmp_0_cfg_l,
  input  [1:0]  io_ptw_pmp_0_cfg_a,
  input         io_ptw_pmp_0_cfg_x,
  input         io_ptw_pmp_0_cfg_w,
  input         io_ptw_pmp_0_cfg_r,
  input  [28:0] io_ptw_pmp_0_addr,
  input  [30:0] io_ptw_pmp_0_mask,
  input         io_ptw_pmp_1_cfg_l,
  input  [1:0]  io_ptw_pmp_1_cfg_a,
  input         io_ptw_pmp_1_cfg_x,
  input         io_ptw_pmp_1_cfg_w,
  input         io_ptw_pmp_1_cfg_r,
  input  [28:0] io_ptw_pmp_1_addr,
  input  [30:0] io_ptw_pmp_1_mask,
  input         io_ptw_pmp_2_cfg_l,
  input  [1:0]  io_ptw_pmp_2_cfg_a,
  input         io_ptw_pmp_2_cfg_x,
  input         io_ptw_pmp_2_cfg_w,
  input         io_ptw_pmp_2_cfg_r,
  input  [28:0] io_ptw_pmp_2_addr,
  input  [30:0] io_ptw_pmp_2_mask,
  input         io_ptw_pmp_3_cfg_l,
  input  [1:0]  io_ptw_pmp_3_cfg_a,
  input         io_ptw_pmp_3_cfg_x,
  input         io_ptw_pmp_3_cfg_w,
  input         io_ptw_pmp_3_cfg_r,
  input  [28:0] io_ptw_pmp_3_addr,
  input  [30:0] io_ptw_pmp_3_mask,
  input         io_ptw_pmp_4_cfg_l,
  input  [1:0]  io_ptw_pmp_4_cfg_a,
  input         io_ptw_pmp_4_cfg_x,
  input         io_ptw_pmp_4_cfg_w,
  input         io_ptw_pmp_4_cfg_r,
  input  [28:0] io_ptw_pmp_4_addr,
  input  [30:0] io_ptw_pmp_4_mask,
  input         io_ptw_pmp_5_cfg_l,
  input  [1:0]  io_ptw_pmp_5_cfg_a,
  input         io_ptw_pmp_5_cfg_x,
  input         io_ptw_pmp_5_cfg_w,
  input         io_ptw_pmp_5_cfg_r,
  input  [28:0] io_ptw_pmp_5_addr,
  input  [30:0] io_ptw_pmp_5_mask,
  input         io_ptw_pmp_6_cfg_l,
  input  [1:0]  io_ptw_pmp_6_cfg_a,
  input         io_ptw_pmp_6_cfg_x,
  input         io_ptw_pmp_6_cfg_w,
  input         io_ptw_pmp_6_cfg_r,
  input  [28:0] io_ptw_pmp_6_addr,
  input  [30:0] io_ptw_pmp_6_mask,
  input         io_ptw_pmp_7_cfg_l,
  input  [1:0]  io_ptw_pmp_7_cfg_a,
  input         io_ptw_pmp_7_cfg_x,
  input         io_ptw_pmp_7_cfg_w,
  input         io_ptw_pmp_7_cfg_r,
  input  [28:0] io_ptw_pmp_7_addr,
  input  [30:0] io_ptw_pmp_7_mask,
  input  [31:0] io_ptw_customCSRs_csrs_0_value
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
`endif // RANDOMIZE_REG_INIT
  wire  icache_clock; // @[Frontend.scala 66:26]
  wire  icache_reset; // @[Frontend.scala 66:26]
  wire  icache_auto_slave_in_a_ready; // @[Frontend.scala 66:26]
  wire  icache_auto_slave_in_a_valid; // @[Frontend.scala 66:26]
  wire [2:0] icache_auto_slave_in_a_bits_opcode; // @[Frontend.scala 66:26]
  wire [1:0] icache_auto_slave_in_a_bits_size; // @[Frontend.scala 66:26]
  wire [7:0] icache_auto_slave_in_a_bits_source; // @[Frontend.scala 66:26]
  wire [27:0] icache_auto_slave_in_a_bits_address; // @[Frontend.scala 66:26]
  wire [3:0] icache_auto_slave_in_a_bits_mask; // @[Frontend.scala 66:26]
  wire [31:0] icache_auto_slave_in_a_bits_data; // @[Frontend.scala 66:26]
  wire  icache_auto_slave_in_d_ready; // @[Frontend.scala 66:26]
  wire  icache_auto_slave_in_d_valid; // @[Frontend.scala 66:26]
  wire [2:0] icache_auto_slave_in_d_bits_opcode; // @[Frontend.scala 66:26]
  wire [1:0] icache_auto_slave_in_d_bits_size; // @[Frontend.scala 66:26]
  wire [7:0] icache_auto_slave_in_d_bits_source; // @[Frontend.scala 66:26]
  wire [31:0] icache_auto_slave_in_d_bits_data; // @[Frontend.scala 66:26]
  wire  icache_auto_master_out_a_ready; // @[Frontend.scala 66:26]
  wire  icache_auto_master_out_a_valid; // @[Frontend.scala 66:26]
  wire [30:0] icache_auto_master_out_a_bits_address; // @[Frontend.scala 66:26]
  wire  icache_auto_master_out_d_ready; // @[Frontend.scala 66:26]
  wire  icache_auto_master_out_d_valid; // @[Frontend.scala 66:26]
  wire [2:0] icache_auto_master_out_d_bits_opcode; // @[Frontend.scala 66:26]
  wire [3:0] icache_auto_master_out_d_bits_size; // @[Frontend.scala 66:26]
  wire [31:0] icache_auto_master_out_d_bits_data; // @[Frontend.scala 66:26]
  wire  icache_auto_master_out_d_bits_corrupt; // @[Frontend.scala 66:26]
  wire  icache_io_req_ready; // @[Frontend.scala 66:26]
  wire  icache_io_req_valid; // @[Frontend.scala 66:26]
  wire [31:0] icache_io_req_bits_addr; // @[Frontend.scala 66:26]
  wire [30:0] icache_io_s1_paddr; // @[Frontend.scala 66:26]
  wire [31:0] icache_io_s2_vaddr; // @[Frontend.scala 66:26]
  wire  icache_io_s1_kill; // @[Frontend.scala 66:26]
  wire  icache_io_s2_kill; // @[Frontend.scala 66:26]
  wire  icache_io_resp_valid; // @[Frontend.scala 66:26]
  wire [31:0] icache_io_resp_bits_data; // @[Frontend.scala 66:26]
  wire  icache_io_resp_bits_ae; // @[Frontend.scala 66:26]
  wire  icache_io_invalidate; // @[Frontend.scala 66:26]
  wire  fq_clock; // @[Frontend.scala 88:57]
  wire  fq_reset; // @[Frontend.scala 88:57]
  wire  fq_io_enq_ready; // @[Frontend.scala 88:57]
  wire  fq_io_enq_valid; // @[Frontend.scala 88:57]
  wire  fq_io_enq_bits_btb_taken; // @[Frontend.scala 88:57]
  wire  fq_io_enq_bits_btb_bridx; // @[Frontend.scala 88:57]
  wire [4:0] fq_io_enq_bits_btb_entry; // @[Frontend.scala 88:57]
  wire [7:0] fq_io_enq_bits_btb_bht_history; // @[Frontend.scala 88:57]
  wire [31:0] fq_io_enq_bits_pc; // @[Frontend.scala 88:57]
  wire [31:0] fq_io_enq_bits_data; // @[Frontend.scala 88:57]
  wire [1:0] fq_io_enq_bits_mask; // @[Frontend.scala 88:57]
  wire  fq_io_enq_bits_xcpt_ae_inst; // @[Frontend.scala 88:57]
  wire  fq_io_enq_bits_replay; // @[Frontend.scala 88:57]
  wire  fq_io_deq_ready; // @[Frontend.scala 88:57]
  wire  fq_io_deq_valid; // @[Frontend.scala 88:57]
  wire  fq_io_deq_bits_btb_taken; // @[Frontend.scala 88:57]
  wire  fq_io_deq_bits_btb_bridx; // @[Frontend.scala 88:57]
  wire [4:0] fq_io_deq_bits_btb_entry; // @[Frontend.scala 88:57]
  wire [7:0] fq_io_deq_bits_btb_bht_history; // @[Frontend.scala 88:57]
  wire [31:0] fq_io_deq_bits_pc; // @[Frontend.scala 88:57]
  wire [31:0] fq_io_deq_bits_data; // @[Frontend.scala 88:57]
  wire  fq_io_deq_bits_xcpt_ae_inst; // @[Frontend.scala 88:57]
  wire  fq_io_deq_bits_replay; // @[Frontend.scala 88:57]
  wire [4:0] fq_io_mask; // @[Frontend.scala 88:57]
  wire [31:0] tlb_io_req_bits_vaddr; // @[Frontend.scala 102:19]
  wire [1:0] tlb_io_req_bits_prv; // @[Frontend.scala 102:19]
  wire [30:0] tlb_io_resp_paddr; // @[Frontend.scala 102:19]
  wire  tlb_io_resp_ae_inst; // @[Frontend.scala 102:19]
  wire  tlb_io_resp_cacheable; // @[Frontend.scala 102:19]
  wire  tlb_io_ptw_status_debug; // @[Frontend.scala 102:19]
  wire  tlb_io_ptw_pmp_0_cfg_l; // @[Frontend.scala 102:19]
  wire [1:0] tlb_io_ptw_pmp_0_cfg_a; // @[Frontend.scala 102:19]
  wire  tlb_io_ptw_pmp_0_cfg_x; // @[Frontend.scala 102:19]
  wire  tlb_io_ptw_pmp_0_cfg_w; // @[Frontend.scala 102:19]
  wire  tlb_io_ptw_pmp_0_cfg_r; // @[Frontend.scala 102:19]
  wire [28:0] tlb_io_ptw_pmp_0_addr; // @[Frontend.scala 102:19]
  wire [30:0] tlb_io_ptw_pmp_0_mask; // @[Frontend.scala 102:19]
  wire  tlb_io_ptw_pmp_1_cfg_l; // @[Frontend.scala 102:19]
  wire [1:0] tlb_io_ptw_pmp_1_cfg_a; // @[Frontend.scala 102:19]
  wire  tlb_io_ptw_pmp_1_cfg_x; // @[Frontend.scala 102:19]
  wire  tlb_io_ptw_pmp_1_cfg_w; // @[Frontend.scala 102:19]
  wire  tlb_io_ptw_pmp_1_cfg_r; // @[Frontend.scala 102:19]
  wire [28:0] tlb_io_ptw_pmp_1_addr; // @[Frontend.scala 102:19]
  wire [30:0] tlb_io_ptw_pmp_1_mask; // @[Frontend.scala 102:19]
  wire  tlb_io_ptw_pmp_2_cfg_l; // @[Frontend.scala 102:19]
  wire [1:0] tlb_io_ptw_pmp_2_cfg_a; // @[Frontend.scala 102:19]
  wire  tlb_io_ptw_pmp_2_cfg_x; // @[Frontend.scala 102:19]
  wire  tlb_io_ptw_pmp_2_cfg_w; // @[Frontend.scala 102:19]
  wire  tlb_io_ptw_pmp_2_cfg_r; // @[Frontend.scala 102:19]
  wire [28:0] tlb_io_ptw_pmp_2_addr; // @[Frontend.scala 102:19]
  wire [30:0] tlb_io_ptw_pmp_2_mask; // @[Frontend.scala 102:19]
  wire  tlb_io_ptw_pmp_3_cfg_l; // @[Frontend.scala 102:19]
  wire [1:0] tlb_io_ptw_pmp_3_cfg_a; // @[Frontend.scala 102:19]
  wire  tlb_io_ptw_pmp_3_cfg_x; // @[Frontend.scala 102:19]
  wire  tlb_io_ptw_pmp_3_cfg_w; // @[Frontend.scala 102:19]
  wire  tlb_io_ptw_pmp_3_cfg_r; // @[Frontend.scala 102:19]
  wire [28:0] tlb_io_ptw_pmp_3_addr; // @[Frontend.scala 102:19]
  wire [30:0] tlb_io_ptw_pmp_3_mask; // @[Frontend.scala 102:19]
  wire  tlb_io_ptw_pmp_4_cfg_l; // @[Frontend.scala 102:19]
  wire [1:0] tlb_io_ptw_pmp_4_cfg_a; // @[Frontend.scala 102:19]
  wire  tlb_io_ptw_pmp_4_cfg_x; // @[Frontend.scala 102:19]
  wire  tlb_io_ptw_pmp_4_cfg_w; // @[Frontend.scala 102:19]
  wire  tlb_io_ptw_pmp_4_cfg_r; // @[Frontend.scala 102:19]
  wire [28:0] tlb_io_ptw_pmp_4_addr; // @[Frontend.scala 102:19]
  wire [30:0] tlb_io_ptw_pmp_4_mask; // @[Frontend.scala 102:19]
  wire  tlb_io_ptw_pmp_5_cfg_l; // @[Frontend.scala 102:19]
  wire [1:0] tlb_io_ptw_pmp_5_cfg_a; // @[Frontend.scala 102:19]
  wire  tlb_io_ptw_pmp_5_cfg_x; // @[Frontend.scala 102:19]
  wire  tlb_io_ptw_pmp_5_cfg_w; // @[Frontend.scala 102:19]
  wire  tlb_io_ptw_pmp_5_cfg_r; // @[Frontend.scala 102:19]
  wire [28:0] tlb_io_ptw_pmp_5_addr; // @[Frontend.scala 102:19]
  wire [30:0] tlb_io_ptw_pmp_5_mask; // @[Frontend.scala 102:19]
  wire  tlb_io_ptw_pmp_6_cfg_l; // @[Frontend.scala 102:19]
  wire [1:0] tlb_io_ptw_pmp_6_cfg_a; // @[Frontend.scala 102:19]
  wire  tlb_io_ptw_pmp_6_cfg_x; // @[Frontend.scala 102:19]
  wire  tlb_io_ptw_pmp_6_cfg_w; // @[Frontend.scala 102:19]
  wire  tlb_io_ptw_pmp_6_cfg_r; // @[Frontend.scala 102:19]
  wire [28:0] tlb_io_ptw_pmp_6_addr; // @[Frontend.scala 102:19]
  wire [30:0] tlb_io_ptw_pmp_6_mask; // @[Frontend.scala 102:19]
  wire  tlb_io_ptw_pmp_7_cfg_l; // @[Frontend.scala 102:19]
  wire [1:0] tlb_io_ptw_pmp_7_cfg_a; // @[Frontend.scala 102:19]
  wire  tlb_io_ptw_pmp_7_cfg_x; // @[Frontend.scala 102:19]
  wire  tlb_io_ptw_pmp_7_cfg_w; // @[Frontend.scala 102:19]
  wire  tlb_io_ptw_pmp_7_cfg_r; // @[Frontend.scala 102:19]
  wire [28:0] tlb_io_ptw_pmp_7_addr; // @[Frontend.scala 102:19]
  wire [30:0] tlb_io_ptw_pmp_7_mask; // @[Frontend.scala 102:19]
  wire  btb_clock; // @[Frontend.scala 185:21]
  wire  btb_reset; // @[Frontend.scala 185:21]
  wire [31:0] btb_io_req_bits_addr; // @[Frontend.scala 185:21]
  wire  btb_io_resp_valid; // @[Frontend.scala 185:21]
  wire  btb_io_resp_bits_taken; // @[Frontend.scala 185:21]
  wire  btb_io_resp_bits_bridx; // @[Frontend.scala 185:21]
  wire [31:0] btb_io_resp_bits_target; // @[Frontend.scala 185:21]
  wire [4:0] btb_io_resp_bits_entry; // @[Frontend.scala 185:21]
  wire [7:0] btb_io_resp_bits_bht_history; // @[Frontend.scala 185:21]
  wire  btb_io_resp_bits_bht_value; // @[Frontend.scala 185:21]
  wire  btb_io_btb_update_valid; // @[Frontend.scala 185:21]
  wire [4:0] btb_io_btb_update_bits_prediction_entry; // @[Frontend.scala 185:21]
  wire [31:0] btb_io_btb_update_bits_pc; // @[Frontend.scala 185:21]
  wire  btb_io_btb_update_bits_isValid; // @[Frontend.scala 185:21]
  wire [31:0] btb_io_btb_update_bits_br_pc; // @[Frontend.scala 185:21]
  wire [1:0] btb_io_btb_update_bits_cfiType; // @[Frontend.scala 185:21]
  wire  btb_io_bht_update_valid; // @[Frontend.scala 185:21]
  wire [7:0] btb_io_bht_update_bits_prediction_history; // @[Frontend.scala 185:21]
  wire [31:0] btb_io_bht_update_bits_pc; // @[Frontend.scala 185:21]
  wire  btb_io_bht_update_bits_branch; // @[Frontend.scala 185:21]
  wire  btb_io_bht_update_bits_taken; // @[Frontend.scala 185:21]
  wire  btb_io_bht_update_bits_mispredict; // @[Frontend.scala 185:21]
  wire  btb_io_bht_advance_valid; // @[Frontend.scala 185:21]
  wire  btb_io_bht_advance_bits_bht_value; // @[Frontend.scala 185:21]
  wire  btb_io_ras_update_valid; // @[Frontend.scala 185:21]
  wire [1:0] btb_io_ras_update_bits_cfiType; // @[Frontend.scala 185:21]
  wire [31:0] btb_io_ras_update_bits_returnAddr; // @[Frontend.scala 185:21]
  wire  btb_io_ras_head_valid; // @[Frontend.scala 185:21]
  wire [31:0] btb_io_ras_head_bits; // @[Frontend.scala 185:21]
  wire  btb_io_flush; // @[Frontend.scala 185:21]
  wire  _T_9 = ~reset; // @[Frontend.scala 93:9]
  reg  s1_valid; // @[Frontend.scala 104:21]
  reg  s2_valid; // @[Frontend.scala 105:25]
  wire  _s0_fq_has_space_T_4 = ~s1_valid; // @[Frontend.scala 108:45]
  wire  _s0_fq_has_space_T_5 = ~s2_valid; // @[Frontend.scala 108:58]
  wire  _s0_fq_has_space_T_7 = ~fq_io_mask[3] & (~s1_valid | ~s2_valid); // @[Frontend.scala 108:41]
  wire  _s0_fq_has_space_T_8 = ~fq_io_mask[2] | _s0_fq_has_space_T_7; // @[Frontend.scala 107:40]
  wire  _s0_fq_has_space_T_14 = ~fq_io_mask[4] & (_s0_fq_has_space_T_4 & _s0_fq_has_space_T_5); // @[Frontend.scala 109:41]
  wire  s0_fq_has_space = _s0_fq_has_space_T_8 | _s0_fq_has_space_T_14; // @[Frontend.scala 108:70]
  wire  s0_valid = io_cpu_req_valid | s0_fq_has_space; // @[Frontend.scala 110:35]
  reg [31:0] s1_pc; // @[Frontend.scala 112:18]
  reg  s1_speculative; // @[Frontend.scala 113:27]
  reg [31:0] s2_pc; // @[Frontend.scala 114:22]
  reg  s2_btb_resp_valid; // @[Frontend.scala 115:44]
  reg  s2_btb_resp_bits_taken; // @[Frontend.scala 116:29]
  reg  s2_btb_resp_bits_bridx; // @[Frontend.scala 116:29]
  reg [4:0] s2_btb_resp_bits_entry; // @[Frontend.scala 116:29]
  reg [7:0] s2_btb_resp_bits_bht_history; // @[Frontend.scala 116:29]
  reg  s2_btb_resp_bits_bht_value; // @[Frontend.scala 116:29]
  wire  s2_btb_taken = s2_btb_resp_valid & s2_btb_resp_bits_taken; // @[Frontend.scala 117:40]
  reg  s2_tlb_resp_ae_inst; // @[Frontend.scala 118:24]
  reg  s2_tlb_resp_cacheable; // @[Frontend.scala 118:24]
  reg  s2_speculative; // @[Frontend.scala 120:27]
  reg  s2_partial_insn_valid; // @[Frontend.scala 121:38]
  reg [15:0] s2_partial_insn; // @[Frontend.scala 122:28]
  reg  wrong_path; // @[Frontend.scala 123:27]
  wire [31:0] _s1_base_pc_T = ~s1_pc; // @[Frontend.scala 125:22]
  wire [31:0] _s1_base_pc_T_1 = _s1_base_pc_T | 32'h3; // @[Frontend.scala 125:29]
  wire [31:0] s1_base_pc = ~_s1_base_pc_T_1; // @[Frontend.scala 125:20]
  wire [31:0] ntpc = s1_base_pc + 32'h4; // @[Frontend.scala 126:25]
  wire  _s2_replay_T = fq_io_enq_ready & fq_io_enq_valid; // @[Decoupled.scala 50:35]
  reg  s2_replay_REG; // @[Frontend.scala 131:58]
  wire  s2_replay = s2_valid & ~_s2_replay_T | s2_replay_REG; // @[Frontend.scala 131:48]
  wire  _taken_prevRVI_T_1 = s2_partial_insn[1:0] != 2'h3; // @[Frontend.scala 214:45]
  wire  taken_prevRVI = s2_partial_insn_valid & ~_taken_prevRVI_T_1; // @[Frontend.scala 215:31]
  wire [15:0] taken_bits = fq_io_enq_bits_data[15:0]; // @[Frontend.scala 217:37]
  wire [31:0] taken_rviBits = {taken_bits,s2_partial_insn}; // @[Cat.scala 31:58]
  wire  taken_rviJump = taken_rviBits[6:0] == 7'h6f; // @[Frontend.scala 221:34]
  wire  taken_rviJALR = taken_rviBits[6:0] == 7'h67; // @[Frontend.scala 222:34]
  wire  taken_rviBranch = taken_rviBits[6:0] == 7'h63; // @[Frontend.scala 220:36]
  wire  taken_valid = fq_io_enq_bits_mask[0] & ~taken_prevRVI; // @[Frontend.scala 216:44]
  wire [15:0] _taken_rvcJump_T = taken_bits & 16'he003; // @[Frontend.scala 227:26]
  wire  taken_rvcJAL = 16'h2001 == _taken_rvcJump_T; // @[Frontend.scala 226:45]
  wire  taken_rvcJump = 16'ha001 == _taken_rvcJump_T | taken_rvcJAL; // @[Frontend.scala 227:47]
  wire [15:0] _taken_rvcJALR_T = taken_bits & 16'hf003; // @[Frontend.scala 231:26]
  wire  _taken_rvcJALR_T_3 = taken_bits[6:2] == 5'h0; // @[Frontend.scala 231:62]
  wire  taken_rvcJALR = 16'h9002 == _taken_rvcJALR_T & taken_bits[6:2] == 5'h0; // @[Frontend.scala 231:49]
  wire  taken_rvcJR = 16'h8002 == _taken_rvcJALR_T & _taken_rvcJALR_T_3; // @[Frontend.scala 229:46]
  wire  taken_rvcBranch = 16'hc001 == _taken_rvcJump_T | 16'he001 == _taken_rvcJump_T; // @[Frontend.scala 225:52]
  wire  _taken_taken_T_8 = taken_valid & (taken_rvcJump | taken_rvcJALR | taken_rvcJR | taken_rvcBranch &
    s2_btb_resp_bits_bht_value); // @[Frontend.scala 237:15]
  wire  taken_taken = taken_prevRVI & (taken_rviJump | taken_rviJALR | taken_rviBranch & s2_btb_resp_bits_bht_value) |
    _taken_taken_T_8; // @[Frontend.scala 236:71]
  wire  taken_idx = ~taken_taken; // @[Frontend.scala 251:13]
  wire  _taken_T_36 = ~s2_btb_taken; // @[Frontend.scala 260:15]
  wire  _taken_prevRVI_T_4 = taken_bits[1:0] != 2'h3; // @[Frontend.scala 214:45]
  wire  _taken_prevRVI_T_5 = ~_taken_prevRVI_T_4; // @[Frontend.scala 215:34]
  wire  taken_prevRVI_1 = taken_valid & ~_taken_prevRVI_T_4; // @[Frontend.scala 215:31]
  wire [15:0] taken_bits_1 = fq_io_enq_bits_data[31:16]; // @[Frontend.scala 217:37]
  wire [31:0] taken_rviBits_1 = {taken_bits_1,taken_bits}; // @[Cat.scala 31:58]
  wire  taken_rviJALR_1 = taken_rviBits_1[6:0] == 7'h67; // @[Frontend.scala 222:34]
  wire [4:0] _taken_rviReturn_T_10 = taken_rviBits_1[19:15] & 5'h1b; // @[Frontend.scala 223:66]
  wire  taken_rviReturn_1 = taken_rviJALR_1 & ~taken_rviBits_1[7] & 5'h1 == _taken_rviReturn_T_10; // @[Frontend.scala 223:46]
  wire  taken_valid_1 = fq_io_enq_bits_mask[1] & ~taken_prevRVI_1; // @[Frontend.scala 216:44]
  wire [15:0] _taken_rvcJR_T_4 = taken_bits_1 & 16'hf003; // @[Frontend.scala 229:24]
  wire  _taken_rvcJR_T_7 = taken_bits_1[6:2] == 5'h0; // @[Frontend.scala 229:59]
  wire  taken_rvcJR_1 = 16'h8002 == _taken_rvcJR_T_4 & taken_bits_1[6:2] == 5'h0; // @[Frontend.scala 229:46]
  wire [4:0] _taken_rvcReturn_T_4 = taken_bits_1[11:7] & 5'h1b; // @[Frontend.scala 230:49]
  wire  taken_rvcReturn_1 = taken_rvcJR_1 & 5'h1 == _taken_rvcReturn_T_4; // @[Frontend.scala 230:29]
  wire  taken_predictReturn_1 = btb_io_ras_head_valid & (taken_prevRVI_1 & taken_rviReturn_1 | taken_valid_1 &
    taken_rvcReturn_1); // @[Frontend.scala 238:49]
  wire [4:0] _taken_rviReturn_T_4 = taken_rviBits[19:15] & 5'h1b; // @[Frontend.scala 223:66]
  wire  taken_rviReturn = taken_rviJALR & ~taken_rviBits[7] & 5'h1 == _taken_rviReturn_T_4; // @[Frontend.scala 223:46]
  wire [4:0] _taken_rvcReturn_T_1 = taken_bits[11:7] & 5'h1b; // @[Frontend.scala 230:49]
  wire  taken_rvcReturn = taken_rvcJR & 5'h1 == _taken_rvcReturn_T_1; // @[Frontend.scala 230:29]
  wire  taken_predictReturn = btb_io_ras_head_valid & (taken_prevRVI & taken_rviReturn | taken_valid & taken_rvcReturn); // @[Frontend.scala 238:49]
  wire  _taken_T_16 = s2_valid & taken_predictReturn; // @[Frontend.scala 264:26]
  wire  _GEN_54 = ~s2_btb_taken & _taken_T_16; // @[Frontend.scala 260:30]
  wire  _GEN_87 = s2_valid & taken_predictReturn_1 | _GEN_54; // @[Frontend.scala 264:44 265:20]
  wire  _GEN_90 = ~s2_btb_taken ? _GEN_87 : ~s2_btb_taken & _taken_T_16; // @[Frontend.scala 260:30]
  wire  useRAS = taken_idx ? _GEN_90 : _GEN_54; // @[Frontend.scala 251:25]
  wire  taken_rviBranch_1 = taken_rviBits_1[6:0] == 7'h63; // @[Frontend.scala 220:36]
  wire [15:0] _taken_rvcBranch_T_4 = taken_bits_1 & 16'he003; // @[Frontend.scala 225:28]
  wire  taken_rvcBranch_1 = 16'hc001 == _taken_rvcBranch_T_4 | 16'he001 == _taken_rvcBranch_T_4; // @[Frontend.scala 225:52]
  wire  _taken_predictBranch_T_5 = taken_prevRVI_1 & taken_rviBranch_1 | taken_valid_1 & taken_rvcBranch_1; // @[Frontend.scala 240:66]
  wire  taken_predictBranch_1 = s2_btb_resp_bits_bht_value & (taken_prevRVI_1 & taken_rviBranch_1 | taken_valid_1 &
    taken_rvcBranch_1); // @[Frontend.scala 240:41]
  wire  taken_rviJump_1 = taken_rviBits_1[6:0] == 7'h6f; // @[Frontend.scala 221:34]
  wire  taken_rvcJAL_1 = 16'h2001 == _taken_rvcBranch_T_4; // @[Frontend.scala 226:45]
  wire  taken_rvcJump_1 = 16'ha001 == _taken_rvcBranch_T_4 | taken_rvcJAL_1; // @[Frontend.scala 227:47]
  wire  taken_predictJump_1 = taken_prevRVI_1 & taken_rviJump_1 | taken_valid_1 & taken_rvcJump_1; // @[Frontend.scala 239:44]
  wire [31:0] _s2_base_pc_T = ~s2_pc; // @[Frontend.scala 207:24]
  wire [31:0] _s2_base_pc_T_1 = _s2_base_pc_T | 32'h3; // @[Frontend.scala 207:31]
  wire [31:0] s2_base_pc = ~_s2_base_pc_T_1; // @[Frontend.scala 207:22]
  wire [31:0] taken_pc_1 = s2_base_pc | 32'h2; // @[Frontend.scala 268:33]
  wire [31:0] _taken_npc_T_6 = taken_pc_1 - 32'h2; // @[Frontend.scala 271:36]
  wire [31:0] _taken_npc_T_8 = taken_prevRVI_1 ? _taken_npc_T_6 : taken_pc_1; // @[Frontend.scala 271:57]
  wire  taken_rviImm_sign_2 = taken_rviBits_1[31]; // @[RocketCore.scala 1083:53]
  wire  taken_rviImm_hi_hi_hi_2 = taken_rviBits_1[31]; // @[Cat.scala 31:58]
  wire [10:0] taken_rviImm_hi_hi_lo_2 = {11{taken_rviImm_sign_2}}; // @[Cat.scala 31:58]
  wire [7:0] taken_rviImm_hi_lo_hi_2 = taken_rviBits_1[19:12]; // @[Cat.scala 31:58]
  wire  taken_rviImm_hi_lo_lo_2 = taken_rviBits_1[20]; // @[Cat.scala 31:58]
  wire [5:0] taken_rviImm_b10_5_2 = taken_rviBits_1[30:25]; // @[RocketCore.scala 1089:66]
  wire [3:0] taken_rviImm_b4_1_2 = taken_rviBits_1[24:21]; // @[RocketCore.scala 1092:52]
  wire [31:0] _taken_rviImm_T_7 = {taken_rviImm_hi_hi_hi_2,taken_rviImm_hi_hi_lo_2,taken_rviImm_hi_lo_hi_2,
    taken_rviImm_hi_lo_lo_2,taken_rviImm_b10_5_2,taken_rviImm_b4_1_2,1'h0}; // @[RocketCore.scala 1097:53]
  wire [7:0] taken_rviImm_hi_lo_hi_3 = {8{taken_rviImm_sign_2}}; // @[Cat.scala 31:58]
  wire  taken_rviImm_hi_lo_lo_3 = taken_rviBits_1[7]; // @[Cat.scala 31:58]
  wire [31:0] _taken_rviImm_T_9 = {taken_rviImm_hi_hi_hi_2,taken_rviImm_hi_hi_lo_2,taken_rviImm_hi_lo_hi_3,
    taken_rviImm_hi_lo_lo_3,taken_rviImm_b10_5_2,taken_rviBits_1[11:8],1'h0}; // @[RocketCore.scala 1097:53]
  wire [31:0] taken_rviImm_1 = taken_rviBits_1[3] ? $signed(_taken_rviImm_T_7) : $signed(_taken_rviImm_T_9); // @[Frontend.scala 233:23]
  wire [4:0] _taken_rvcImm_T_25 = taken_bits_1[12] ? 5'h1f : 5'h0; // @[Bitwise.scala 74:12]
  wire [12:0] _taken_rvcImm_T_31 = {_taken_rvcImm_T_25,taken_bits_1[6:5],taken_bits_1[2],taken_bits_1[11:10],
    taken_bits_1[4:3],1'h0}; // @[Frontend.scala 228:66]
  wire [9:0] _taken_rvcImm_T_34 = taken_bits_1[12] ? 10'h3ff : 10'h0; // @[Bitwise.scala 74:12]
  wire [20:0] _taken_rvcImm_T_43 = {_taken_rvcImm_T_34,taken_bits_1[8],taken_bits_1[10:9],taken_bits_1[6],taken_bits_1[7
    ],taken_bits_1[2],taken_bits_1[11],taken_bits_1[5:3],1'h0}; // @[Frontend.scala 228:106]
  wire [20:0] taken_rvcImm_1 = taken_bits_1[14] ? $signed({{8{_taken_rvcImm_T_31[12]}},_taken_rvcImm_T_31}) : $signed(
    _taken_rvcImm_T_43); // @[Frontend.scala 228:23]
  wire [31:0] _taken_npc_T_9 = taken_prevRVI_1 ? $signed(taken_rviImm_1) : $signed({{11{taken_rvcImm_1[20]}},
    taken_rvcImm_1}); // @[Frontend.scala 271:69]
  wire [31:0] _taken_predicted_npc_T_1 = $signed(_taken_npc_T_8) + $signed(_taken_npc_T_9); // @[Frontend.scala 272:34]
  wire  _taken_predictBranch_T_2 = taken_prevRVI & taken_rviBranch | taken_valid & taken_rvcBranch; // @[Frontend.scala 240:66]
  wire  taken_predictBranch = s2_btb_resp_bits_bht_value & (taken_prevRVI & taken_rviBranch | taken_valid &
    taken_rvcBranch); // @[Frontend.scala 240:41]
  wire  taken_predictJump = taken_prevRVI & taken_rviJump | taken_valid & taken_rvcJump; // @[Frontend.scala 239:44]
  wire [31:0] _taken_npc_T = ~_s2_base_pc_T_1; // @[Frontend.scala 270:32]
  wire  taken_rviImm_sign = taken_rviBits[31]; // @[RocketCore.scala 1083:53]
  wire  taken_rviImm_hi_hi_hi = taken_rviBits[31]; // @[Cat.scala 31:58]
  wire [10:0] taken_rviImm_hi_hi_lo = {11{taken_rviImm_sign}}; // @[Cat.scala 31:58]
  wire [7:0] taken_rviImm_hi_lo_hi = taken_rviBits[19:12]; // @[Cat.scala 31:58]
  wire  taken_rviImm_hi_lo_lo = taken_rviBits[20]; // @[Cat.scala 31:58]
  wire [5:0] taken_rviImm_b10_5 = taken_rviBits[30:25]; // @[RocketCore.scala 1089:66]
  wire [3:0] taken_rviImm_b4_1 = taken_rviBits[24:21]; // @[RocketCore.scala 1092:52]
  wire [31:0] _taken_rviImm_T_2 = {taken_rviImm_hi_hi_hi,taken_rviImm_hi_hi_lo,taken_rviImm_hi_lo_hi,
    taken_rviImm_hi_lo_lo,taken_rviImm_b10_5,taken_rviImm_b4_1,1'h0}; // @[RocketCore.scala 1097:53]
  wire [7:0] taken_rviImm_hi_lo_hi_1 = {8{taken_rviImm_sign}}; // @[Cat.scala 31:58]
  wire  taken_rviImm_hi_lo_lo_1 = taken_rviBits[7]; // @[Cat.scala 31:58]
  wire [31:0] _taken_rviImm_T_4 = {taken_rviImm_hi_hi_hi,taken_rviImm_hi_hi_lo,taken_rviImm_hi_lo_hi_1,
    taken_rviImm_hi_lo_lo_1,taken_rviImm_b10_5,taken_rviBits[11:8],1'h0}; // @[RocketCore.scala 1097:53]
  wire [31:0] taken_rviImm = taken_rviBits[3] ? $signed(_taken_rviImm_T_2) : $signed(_taken_rviImm_T_4); // @[Frontend.scala 233:23]
  wire [32:0] _taken_npc_T_1 = $signed(taken_rviImm) - 32'sh2; // @[Frontend.scala 270:61]
  wire [4:0] _taken_rvcImm_T_3 = taken_bits[12] ? 5'h1f : 5'h0; // @[Bitwise.scala 74:12]
  wire [12:0] _taken_rvcImm_T_9 = {_taken_rvcImm_T_3,taken_bits[6:5],taken_bits[2],taken_bits[11:10],taken_bits[4:3],1'h0
    }; // @[Frontend.scala 228:66]
  wire [9:0] _taken_rvcImm_T_12 = taken_bits[12] ? 10'h3ff : 10'h0; // @[Bitwise.scala 74:12]
  wire [20:0] _taken_rvcImm_T_21 = {_taken_rvcImm_T_12,taken_bits[8],taken_bits[10:9],taken_bits[6],taken_bits[7],
    taken_bits[2],taken_bits[11],taken_bits[5:3],1'h0}; // @[Frontend.scala 228:106]
  wire [20:0] taken_rvcImm = taken_bits[14] ? $signed({{8{_taken_rvcImm_T_9[12]}},_taken_rvcImm_T_9}) : $signed(
    _taken_rvcImm_T_21); // @[Frontend.scala 228:23]
  wire [32:0] _taken_npc_T_2 = taken_prevRVI ? $signed(_taken_npc_T_1) : $signed({{12{taken_rvcImm[20]}},taken_rvcImm}); // @[Frontend.scala 270:44]
  wire [32:0] _GEN_140 = {{1{_taken_npc_T[31]}},_taken_npc_T}; // @[Frontend.scala 270:39]
  wire [32:0] _taken_predicted_npc_T = $signed(_GEN_140) + $signed(_taken_npc_T_2); // @[Frontend.scala 272:34]
  wire  predicted_taken = btb_io_resp_valid & btb_io_resp_bits_taken; // @[Frontend.scala 198:29]
  wire [31:0] _GEN_37 = predicted_taken ? btb_io_resp_bits_target : ntpc; // @[Frontend.scala 198:56 199:21]
  wire [32:0] _GEN_52 = s2_valid & (taken_predictBranch | taken_predictJump) ? _taken_predicted_npc_T : {{1'd0}, _GEN_37
    }; // @[Frontend.scala 267:61 272:27]
  wire [32:0] _GEN_55 = ~s2_btb_taken ? _GEN_52 : {{1'd0}, _GEN_37}; // @[Frontend.scala 260:30]
  wire [32:0] _GEN_88 = s2_valid & (taken_predictBranch_1 | taken_predictJump_1) ? {{1'd0}, _taken_predicted_npc_T_1} :
    _GEN_55; // @[Frontend.scala 267:61 272:27]
  wire [32:0] _GEN_91 = ~s2_btb_taken ? _GEN_88 : _GEN_55; // @[Frontend.scala 260:30]
  wire [32:0] _GEN_108 = taken_idx ? _GEN_91 : _GEN_55; // @[Frontend.scala 251:25]
  wire [32:0] predicted_npc = useRAS ? {{1'd0}, btb_io_ras_head_bits} : _GEN_108; // @[Frontend.scala 311:19 312:21]
  wire [32:0] npc = s2_replay ? {{1'd0}, s2_pc} : predicted_npc; // @[Frontend.scala 132:16]
  wire  s0_speculative = s1_speculative | s2_valid & ~s2_speculative | predicted_taken; // @[Frontend.scala 138:72]
  wire  _T_11 = ~s2_replay; // @[Frontend.scala 144:9]
  wire  taken_rvcJALR_1 = 16'h9002 == _taken_rvcJR_T_4 & _taken_rvcJR_T_7; // @[Frontend.scala 231:49]
  wire  _taken_taken_T_17 = taken_valid_1 & (taken_rvcJump_1 | taken_rvcJALR_1 | taken_rvcJR_1 | taken_rvcBranch_1 &
    s2_btb_resp_bits_bht_value); // @[Frontend.scala 237:15]
  wire  taken_taken_1 = taken_prevRVI_1 & (taken_rviJump_1 | taken_rviJALR_1 | taken_rviBranch_1 &
    s2_btb_resp_bits_bht_value) | _taken_taken_T_17; // @[Frontend.scala 236:71]
  wire  taken = taken_taken | taken_taken_1; // @[Frontend.scala 292:19]
  wire  _GEN_125 = _s2_replay_T | io_cpu_req_valid; // @[Frontend.scala 322:{33,47}]
  wire  _GEN_129 = taken ? _GEN_125 : io_cpu_req_valid; // @[Frontend.scala 318:20]
  wire  s2_redirect = _taken_T_36 ? _GEN_129 : io_cpu_req_valid; // @[Frontend.scala 317:26]
  wire  _GEN_0 = ~s2_replay & ~s2_redirect; // @[Frontend.scala 143:12 144:21 145:14]
  wire  s2_can_speculatively_refill = s2_tlb_resp_cacheable & ~io_ptw_customCSRs_csrs_0_value[3]; // @[Frontend.scala 167:59]
  reg  fq_io_enq_valid_REG; // @[Frontend.scala 171:29]
  wire [32:0] _io_cpu_npc_T = io_cpu_req_valid ? {{1'd0}, io_cpu_req_bits_pc} : npc; // @[Frontend.scala 173:28]
  wire [32:0] _io_cpu_npc_T_1 = ~_io_cpu_npc_T; // @[Frontend.scala 362:29]
  wire [32:0] _io_cpu_npc_T_2 = _io_cpu_npc_T_1 | 33'h1; // @[Frontend.scala 362:33]
  wire [32:0] _io_cpu_npc_T_3 = ~_io_cpu_npc_T_2; // @[Frontend.scala 362:27]
  wire [2:0] _fq_io_enq_bits_mask_T_1 = 3'h3 << s2_pc[1]; // @[Frontend.scala 176:52]
  wire  fetch_bubble_likely = ~fq_io_mask[1]; // @[Frontend.scala 299:33]
  wire  _btb_io_btb_update_valid_T_2 = _s2_replay_T & ~wrong_path; // @[Frontend.scala 300:51]
  wire  _taken_T_27 = ~s2_btb_resp_valid & (taken_predictBranch & s2_btb_resp_bits_bht_value | taken_predictJump |
    taken_predictReturn); // @[Frontend.scala 279:34]
  wire  _GEN_101 = ~s2_btb_resp_valid & (taken_predictBranch_1 & s2_btb_resp_bits_bht_value | taken_predictJump_1 |
    taken_predictReturn_1) | ~s2_btb_resp_valid & (taken_predictBranch & s2_btb_resp_bits_bht_value | taken_predictJump
     | taken_predictReturn); // @[Frontend.scala 279:125 280:21]
  wire  updateBTB = taken_idx ? _GEN_101 : _taken_T_27; // @[Frontend.scala 251:25]
  wire [1:0] _btb_io_btb_update_bits_br_pc_T = {taken_idx, 1'h0}; // @[Frontend.scala 304:63]
  wire [31:0] _GEN_141 = {{30'd0}, _btb_io_btb_update_bits_br_pc_T}; // @[Frontend.scala 304:50]
  wire [31:0] _btb_io_btb_update_bits_br_pc_T_1 = s2_base_pc | _GEN_141; // @[Frontend.scala 304:50]
  wire [1:0] after_idx = taken_idx ? 2'h2 : 2'h1; // @[Frontend.scala 251:25 253:19]
  wire [2:0] _btb_io_ras_update_bits_returnAddr_T = {after_idx, 1'h0}; // @[Frontend.scala 308:66]
  wire [31:0] _GEN_142 = {{29'd0}, _btb_io_ras_update_bits_returnAddr_T}; // @[Frontend.scala 308:53]
  wire  taken_rviCall = (taken_rviJALR | taken_rviJump) & taken_rviBits[7]; // @[Frontend.scala 224:42]
  wire  taken_rvcCall = taken_rvcJAL | taken_rvcJALR; // @[Frontend.scala 232:28]
  wire  _GEN_48 = s2_valid & s2_btb_resp_valid & ~s2_btb_resp_bits_bridx & taken_valid & _taken_prevRVI_T_5 |
    icache_io_s2_kill & ~icache_io_resp_valid & ~s2_tlb_resp_ae_inst; // @[Frontend.scala 177:25 242:95 246:31]
  wire  _GEN_49 = s2_valid & s2_btb_resp_valid & ~s2_btb_resp_bits_bridx & taken_valid & _taken_prevRVI_T_5 | wrong_path
    ; // @[Frontend.scala 242:95 247:20 123:27]
  wire  _taken_btb_io_ras_update_bits_cfiType_T = taken_prevRVI ? taken_rviReturn : taken_rvcReturn; // @[Frontend.scala 255:50]
  wire  _taken_btb_io_ras_update_bits_cfiType_T_1 = taken_prevRVI ? taken_rviCall : taken_rvcCall; // @[Frontend.scala 256:50]
  wire  _taken_btb_io_ras_update_bits_cfiType_T_2 = taken_prevRVI ? taken_rviBranch : taken_rvcBranch; // @[Frontend.scala 257:50]
  wire  _taken_btb_io_ras_update_bits_cfiType_T_5 = _taken_btb_io_ras_update_bits_cfiType_T_2 ? 1'h0 : 1'h1; // @[Frontend.scala 257:46]
  wire [1:0] _taken_btb_io_ras_update_bits_cfiType_T_6 = _taken_btb_io_ras_update_bits_cfiType_T_1 ? 2'h2 : {{1'd0},
    _taken_btb_io_ras_update_bits_cfiType_T_5}; // @[Frontend.scala 256:46]
  wire [1:0] _taken_btb_io_ras_update_bits_cfiType_T_7 = _taken_btb_io_ras_update_bits_cfiType_T ? 2'h3 :
    _taken_btb_io_ras_update_bits_cfiType_T_6; // @[Frontend.scala 255:46]
  wire  _GEN_50 = _s2_replay_T & taken_taken & ~taken_predictBranch & ~taken_predictJump & ~taken_predictReturn |
    _GEN_49; // @[Frontend.scala 261:96 262:24]
  wire  _GEN_53 = ~s2_btb_taken ? _GEN_50 : _GEN_49; // @[Frontend.scala 260:30]
  wire  _GEN_56 = _taken_predictBranch_T_2 & _btb_io_btb_update_valid_T_2; // @[Frontend.scala 192:30 275:59 276:36]
  wire  taken_rvc_1 = taken_bits_1[1:0] != 2'h3; // @[Frontend.scala 214:45]
  wire  taken_rviCall_1 = (taken_rviJALR_1 | taken_rviJump_1) & taken_rviBits_1[7]; // @[Frontend.scala 224:42]
  wire  taken_rvcCall_1 = taken_rvcJAL_1 | taken_rvcJALR_1; // @[Frontend.scala 232:28]
  wire  _taken_T_33 = ~taken_rvc_1; // @[Frontend.scala 242:89]
  wire  _GEN_85 = s2_valid & s2_btb_resp_valid & s2_btb_resp_bits_bridx & taken_valid_1 & ~taken_rvc_1 | _GEN_53; // @[Frontend.scala 242:95 247:20]
  wire  _taken_btb_io_ras_update_bits_cfiType_T_8 = taken_prevRVI_1 ? taken_rviReturn_1 : taken_rvcReturn_1; // @[Frontend.scala 255:50]
  wire  _taken_btb_io_ras_update_bits_cfiType_T_9 = taken_prevRVI_1 ? taken_rviCall_1 : taken_rvcCall_1; // @[Frontend.scala 256:50]
  wire  _taken_btb_io_ras_update_bits_cfiType_T_10 = taken_prevRVI_1 ? taken_rviBranch_1 : taken_rvcBranch_1; // @[Frontend.scala 257:50]
  wire  _taken_btb_io_ras_update_bits_cfiType_T_13 = _taken_btb_io_ras_update_bits_cfiType_T_10 ? 1'h0 : 1'h1; // @[Frontend.scala 257:46]
  wire [1:0] _taken_btb_io_ras_update_bits_cfiType_T_14 = _taken_btb_io_ras_update_bits_cfiType_T_9 ? 2'h2 : {{1'd0},
    _taken_btb_io_ras_update_bits_cfiType_T_13}; // @[Frontend.scala 256:46]
  wire [1:0] _taken_btb_io_ras_update_bits_cfiType_T_15 = _taken_btb_io_ras_update_bits_cfiType_T_8 ? 2'h3 :
    _taken_btb_io_ras_update_bits_cfiType_T_14; // @[Frontend.scala 255:46]
  wire  _GEN_86 = _s2_replay_T & taken_taken_1 & ~taken_predictBranch_1 & ~taken_predictJump_1 & ~taken_predictReturn_1
     | _GEN_85; // @[Frontend.scala 261:96 262:24]
  wire  _GEN_92 = _taken_predictBranch_T_5 ? _btb_io_btb_update_valid_T_2 : _GEN_56; // @[Frontend.scala 275:59 276:36]
  wire  _taken_T_61 = taken_valid_1 & taken_idx & _taken_T_33; // @[Frontend.scala 287:37]
  wire [15:0] _taken_s2_partial_insn_T = taken_bits_1 | 16'h3; // @[Frontend.scala 289:37]
  wire  _GEN_126 = taken ? taken_idx : s2_btb_resp_bits_bridx; // @[Frontend.scala 318:20 178:22 319:34]
  wire  _GEN_127 = taken | s2_btb_taken; // @[Frontend.scala 318:20 179:28 320:34]
  wire [4:0] _GEN_128 = taken ? 5'h1c : s2_btb_resp_bits_entry; // @[Frontend.scala 318:20 178:22 321:34]
  ICache icache ( // @[Frontend.scala 66:26]
    .clock(icache_clock),
    .reset(icache_reset),
    .auto_slave_in_a_ready(icache_auto_slave_in_a_ready),
    .auto_slave_in_a_valid(icache_auto_slave_in_a_valid),
    .auto_slave_in_a_bits_opcode(icache_auto_slave_in_a_bits_opcode),
    .auto_slave_in_a_bits_size(icache_auto_slave_in_a_bits_size),
    .auto_slave_in_a_bits_source(icache_auto_slave_in_a_bits_source),
    .auto_slave_in_a_bits_address(icache_auto_slave_in_a_bits_address),
    .auto_slave_in_a_bits_mask(icache_auto_slave_in_a_bits_mask),
    .auto_slave_in_a_bits_data(icache_auto_slave_in_a_bits_data),
    .auto_slave_in_d_ready(icache_auto_slave_in_d_ready),
    .auto_slave_in_d_valid(icache_auto_slave_in_d_valid),
    .auto_slave_in_d_bits_opcode(icache_auto_slave_in_d_bits_opcode),
    .auto_slave_in_d_bits_size(icache_auto_slave_in_d_bits_size),
    .auto_slave_in_d_bits_source(icache_auto_slave_in_d_bits_source),
    .auto_slave_in_d_bits_data(icache_auto_slave_in_d_bits_data),
    .auto_master_out_a_ready(icache_auto_master_out_a_ready),
    .auto_master_out_a_valid(icache_auto_master_out_a_valid),
    .auto_master_out_a_bits_address(icache_auto_master_out_a_bits_address),
    .auto_master_out_d_ready(icache_auto_master_out_d_ready),
    .auto_master_out_d_valid(icache_auto_master_out_d_valid),
    .auto_master_out_d_bits_opcode(icache_auto_master_out_d_bits_opcode),
    .auto_master_out_d_bits_size(icache_auto_master_out_d_bits_size),
    .auto_master_out_d_bits_data(icache_auto_master_out_d_bits_data),
    .auto_master_out_d_bits_corrupt(icache_auto_master_out_d_bits_corrupt),
    .io_req_ready(icache_io_req_ready),
    .io_req_valid(icache_io_req_valid),
    .io_req_bits_addr(icache_io_req_bits_addr),
    .io_s1_paddr(icache_io_s1_paddr),
    .io_s2_vaddr(icache_io_s2_vaddr),
    .io_s1_kill(icache_io_s1_kill),
    .io_s2_kill(icache_io_s2_kill),
    .io_resp_valid(icache_io_resp_valid),
    .io_resp_bits_data(icache_io_resp_bits_data),
    .io_resp_bits_ae(icache_io_resp_bits_ae),
    .io_invalidate(icache_io_invalidate)
  );
  ShiftQueue fq ( // @[Frontend.scala 88:57]
    .clock(fq_clock),
    .reset(fq_reset),
    .io_enq_ready(fq_io_enq_ready),
    .io_enq_valid(fq_io_enq_valid),
    .io_enq_bits_btb_taken(fq_io_enq_bits_btb_taken),
    .io_enq_bits_btb_bridx(fq_io_enq_bits_btb_bridx),
    .io_enq_bits_btb_entry(fq_io_enq_bits_btb_entry),
    .io_enq_bits_btb_bht_history(fq_io_enq_bits_btb_bht_history),
    .io_enq_bits_pc(fq_io_enq_bits_pc),
    .io_enq_bits_data(fq_io_enq_bits_data),
    .io_enq_bits_mask(fq_io_enq_bits_mask),
    .io_enq_bits_xcpt_ae_inst(fq_io_enq_bits_xcpt_ae_inst),
    .io_enq_bits_replay(fq_io_enq_bits_replay),
    .io_deq_ready(fq_io_deq_ready),
    .io_deq_valid(fq_io_deq_valid),
    .io_deq_bits_btb_taken(fq_io_deq_bits_btb_taken),
    .io_deq_bits_btb_bridx(fq_io_deq_bits_btb_bridx),
    .io_deq_bits_btb_entry(fq_io_deq_bits_btb_entry),
    .io_deq_bits_btb_bht_history(fq_io_deq_bits_btb_bht_history),
    .io_deq_bits_pc(fq_io_deq_bits_pc),
    .io_deq_bits_data(fq_io_deq_bits_data),
    .io_deq_bits_xcpt_ae_inst(fq_io_deq_bits_xcpt_ae_inst),
    .io_deq_bits_replay(fq_io_deq_bits_replay),
    .io_mask(fq_io_mask)
  );
  TLB_1 tlb ( // @[Frontend.scala 102:19]
    .io_req_bits_vaddr(tlb_io_req_bits_vaddr),
    .io_req_bits_prv(tlb_io_req_bits_prv),
    .io_resp_paddr(tlb_io_resp_paddr),
    .io_resp_ae_inst(tlb_io_resp_ae_inst),
    .io_resp_cacheable(tlb_io_resp_cacheable),
    .io_ptw_status_debug(tlb_io_ptw_status_debug),
    .io_ptw_pmp_0_cfg_l(tlb_io_ptw_pmp_0_cfg_l),
    .io_ptw_pmp_0_cfg_a(tlb_io_ptw_pmp_0_cfg_a),
    .io_ptw_pmp_0_cfg_x(tlb_io_ptw_pmp_0_cfg_x),
    .io_ptw_pmp_0_cfg_w(tlb_io_ptw_pmp_0_cfg_w),
    .io_ptw_pmp_0_cfg_r(tlb_io_ptw_pmp_0_cfg_r),
    .io_ptw_pmp_0_addr(tlb_io_ptw_pmp_0_addr),
    .io_ptw_pmp_0_mask(tlb_io_ptw_pmp_0_mask),
    .io_ptw_pmp_1_cfg_l(tlb_io_ptw_pmp_1_cfg_l),
    .io_ptw_pmp_1_cfg_a(tlb_io_ptw_pmp_1_cfg_a),
    .io_ptw_pmp_1_cfg_x(tlb_io_ptw_pmp_1_cfg_x),
    .io_ptw_pmp_1_cfg_w(tlb_io_ptw_pmp_1_cfg_w),
    .io_ptw_pmp_1_cfg_r(tlb_io_ptw_pmp_1_cfg_r),
    .io_ptw_pmp_1_addr(tlb_io_ptw_pmp_1_addr),
    .io_ptw_pmp_1_mask(tlb_io_ptw_pmp_1_mask),
    .io_ptw_pmp_2_cfg_l(tlb_io_ptw_pmp_2_cfg_l),
    .io_ptw_pmp_2_cfg_a(tlb_io_ptw_pmp_2_cfg_a),
    .io_ptw_pmp_2_cfg_x(tlb_io_ptw_pmp_2_cfg_x),
    .io_ptw_pmp_2_cfg_w(tlb_io_ptw_pmp_2_cfg_w),
    .io_ptw_pmp_2_cfg_r(tlb_io_ptw_pmp_2_cfg_r),
    .io_ptw_pmp_2_addr(tlb_io_ptw_pmp_2_addr),
    .io_ptw_pmp_2_mask(tlb_io_ptw_pmp_2_mask),
    .io_ptw_pmp_3_cfg_l(tlb_io_ptw_pmp_3_cfg_l),
    .io_ptw_pmp_3_cfg_a(tlb_io_ptw_pmp_3_cfg_a),
    .io_ptw_pmp_3_cfg_x(tlb_io_ptw_pmp_3_cfg_x),
    .io_ptw_pmp_3_cfg_w(tlb_io_ptw_pmp_3_cfg_w),
    .io_ptw_pmp_3_cfg_r(tlb_io_ptw_pmp_3_cfg_r),
    .io_ptw_pmp_3_addr(tlb_io_ptw_pmp_3_addr),
    .io_ptw_pmp_3_mask(tlb_io_ptw_pmp_3_mask),
    .io_ptw_pmp_4_cfg_l(tlb_io_ptw_pmp_4_cfg_l),
    .io_ptw_pmp_4_cfg_a(tlb_io_ptw_pmp_4_cfg_a),
    .io_ptw_pmp_4_cfg_x(tlb_io_ptw_pmp_4_cfg_x),
    .io_ptw_pmp_4_cfg_w(tlb_io_ptw_pmp_4_cfg_w),
    .io_ptw_pmp_4_cfg_r(tlb_io_ptw_pmp_4_cfg_r),
    .io_ptw_pmp_4_addr(tlb_io_ptw_pmp_4_addr),
    .io_ptw_pmp_4_mask(tlb_io_ptw_pmp_4_mask),
    .io_ptw_pmp_5_cfg_l(tlb_io_ptw_pmp_5_cfg_l),
    .io_ptw_pmp_5_cfg_a(tlb_io_ptw_pmp_5_cfg_a),
    .io_ptw_pmp_5_cfg_x(tlb_io_ptw_pmp_5_cfg_x),
    .io_ptw_pmp_5_cfg_w(tlb_io_ptw_pmp_5_cfg_w),
    .io_ptw_pmp_5_cfg_r(tlb_io_ptw_pmp_5_cfg_r),
    .io_ptw_pmp_5_addr(tlb_io_ptw_pmp_5_addr),
    .io_ptw_pmp_5_mask(tlb_io_ptw_pmp_5_mask),
    .io_ptw_pmp_6_cfg_l(tlb_io_ptw_pmp_6_cfg_l),
    .io_ptw_pmp_6_cfg_a(tlb_io_ptw_pmp_6_cfg_a),
    .io_ptw_pmp_6_cfg_x(tlb_io_ptw_pmp_6_cfg_x),
    .io_ptw_pmp_6_cfg_w(tlb_io_ptw_pmp_6_cfg_w),
    .io_ptw_pmp_6_cfg_r(tlb_io_ptw_pmp_6_cfg_r),
    .io_ptw_pmp_6_addr(tlb_io_ptw_pmp_6_addr),
    .io_ptw_pmp_6_mask(tlb_io_ptw_pmp_6_mask),
    .io_ptw_pmp_7_cfg_l(tlb_io_ptw_pmp_7_cfg_l),
    .io_ptw_pmp_7_cfg_a(tlb_io_ptw_pmp_7_cfg_a),
    .io_ptw_pmp_7_cfg_x(tlb_io_ptw_pmp_7_cfg_x),
    .io_ptw_pmp_7_cfg_w(tlb_io_ptw_pmp_7_cfg_w),
    .io_ptw_pmp_7_cfg_r(tlb_io_ptw_pmp_7_cfg_r),
    .io_ptw_pmp_7_addr(tlb_io_ptw_pmp_7_addr),
    .io_ptw_pmp_7_mask(tlb_io_ptw_pmp_7_mask)
  );
  BTB btb ( // @[Frontend.scala 185:21]
    .clock(btb_clock),
    .reset(btb_reset),
    .io_req_bits_addr(btb_io_req_bits_addr),
    .io_resp_valid(btb_io_resp_valid),
    .io_resp_bits_taken(btb_io_resp_bits_taken),
    .io_resp_bits_bridx(btb_io_resp_bits_bridx),
    .io_resp_bits_target(btb_io_resp_bits_target),
    .io_resp_bits_entry(btb_io_resp_bits_entry),
    .io_resp_bits_bht_history(btb_io_resp_bits_bht_history),
    .io_resp_bits_bht_value(btb_io_resp_bits_bht_value),
    .io_btb_update_valid(btb_io_btb_update_valid),
    .io_btb_update_bits_prediction_entry(btb_io_btb_update_bits_prediction_entry),
    .io_btb_update_bits_pc(btb_io_btb_update_bits_pc),
    .io_btb_update_bits_isValid(btb_io_btb_update_bits_isValid),
    .io_btb_update_bits_br_pc(btb_io_btb_update_bits_br_pc),
    .io_btb_update_bits_cfiType(btb_io_btb_update_bits_cfiType),
    .io_bht_update_valid(btb_io_bht_update_valid),
    .io_bht_update_bits_prediction_history(btb_io_bht_update_bits_prediction_history),
    .io_bht_update_bits_pc(btb_io_bht_update_bits_pc),
    .io_bht_update_bits_branch(btb_io_bht_update_bits_branch),
    .io_bht_update_bits_taken(btb_io_bht_update_bits_taken),
    .io_bht_update_bits_mispredict(btb_io_bht_update_bits_mispredict),
    .io_bht_advance_valid(btb_io_bht_advance_valid),
    .io_bht_advance_bits_bht_value(btb_io_bht_advance_bits_bht_value),
    .io_ras_update_valid(btb_io_ras_update_valid),
    .io_ras_update_bits_cfiType(btb_io_ras_update_bits_cfiType),
    .io_ras_update_bits_returnAddr(btb_io_ras_update_bits_returnAddr),
    .io_ras_head_valid(btb_io_ras_head_valid),
    .io_ras_head_bits(btb_io_ras_head_bits),
    .io_flush(btb_io_flush)
  );
  assign auto_icache_slave_in_a_ready = icache_auto_slave_in_a_ready; // @[LazyModule.scala 309:16]
  assign auto_icache_slave_in_d_valid = icache_auto_slave_in_d_valid; // @[LazyModule.scala 309:16]
  assign auto_icache_slave_in_d_bits_opcode = icache_auto_slave_in_d_bits_opcode; // @[LazyModule.scala 309:16]
  assign auto_icache_slave_in_d_bits_size = icache_auto_slave_in_d_bits_size; // @[LazyModule.scala 309:16]
  assign auto_icache_slave_in_d_bits_source = icache_auto_slave_in_d_bits_source; // @[LazyModule.scala 309:16]
  assign auto_icache_slave_in_d_bits_data = icache_auto_slave_in_d_bits_data; // @[LazyModule.scala 309:16]
  assign auto_icache_master_out_a_valid = icache_auto_master_out_a_valid; // @[LazyModule.scala 311:12]
  assign auto_icache_master_out_a_bits_address = icache_auto_master_out_a_bits_address; // @[LazyModule.scala 311:12]
  assign auto_icache_master_out_d_ready = icache_auto_master_out_d_ready; // @[LazyModule.scala 311:12]
  assign io_cpu_resp_valid = fq_io_deq_valid; // @[Frontend.scala 331:15]
  assign io_cpu_resp_bits_btb_taken = fq_io_deq_bits_btb_taken; // @[Frontend.scala 331:15]
  assign io_cpu_resp_bits_btb_bridx = fq_io_deq_bits_btb_bridx; // @[Frontend.scala 331:15]
  assign io_cpu_resp_bits_btb_entry = fq_io_deq_bits_btb_entry; // @[Frontend.scala 331:15]
  assign io_cpu_resp_bits_btb_bht_history = fq_io_deq_bits_btb_bht_history; // @[Frontend.scala 331:15]
  assign io_cpu_resp_bits_pc = fq_io_deq_bits_pc; // @[Frontend.scala 331:15]
  assign io_cpu_resp_bits_data = fq_io_deq_bits_data; // @[Frontend.scala 331:15]
  assign io_cpu_resp_bits_xcpt_ae_inst = fq_io_deq_bits_xcpt_ae_inst; // @[Frontend.scala 331:15]
  assign io_cpu_resp_bits_replay = fq_io_deq_bits_replay; // @[Frontend.scala 331:15]
  assign io_cpu_npc = _io_cpu_npc_T_3[31:0]; // @[Frontend.scala 173:14]
  assign icache_clock = clock; // @[Frontend.scala 98:16]
  assign icache_reset = reset;
  assign icache_auto_slave_in_a_valid = auto_icache_slave_in_a_valid; // @[LazyModule.scala 309:16]
  assign icache_auto_slave_in_a_bits_opcode = auto_icache_slave_in_a_bits_opcode; // @[LazyModule.scala 309:16]
  assign icache_auto_slave_in_a_bits_size = auto_icache_slave_in_a_bits_size; // @[LazyModule.scala 309:16]
  assign icache_auto_slave_in_a_bits_source = auto_icache_slave_in_a_bits_source; // @[LazyModule.scala 309:16]
  assign icache_auto_slave_in_a_bits_address = auto_icache_slave_in_a_bits_address; // @[LazyModule.scala 309:16]
  assign icache_auto_slave_in_a_bits_mask = auto_icache_slave_in_a_bits_mask; // @[LazyModule.scala 309:16]
  assign icache_auto_slave_in_a_bits_data = auto_icache_slave_in_a_bits_data; // @[LazyModule.scala 309:16]
  assign icache_auto_slave_in_d_ready = auto_icache_slave_in_d_ready; // @[LazyModule.scala 309:16]
  assign icache_auto_master_out_a_ready = auto_icache_master_out_a_ready; // @[LazyModule.scala 311:12]
  assign icache_auto_master_out_d_valid = auto_icache_master_out_d_valid; // @[LazyModule.scala 311:12]
  assign icache_auto_master_out_d_bits_opcode = auto_icache_master_out_d_bits_opcode; // @[LazyModule.scala 311:12]
  assign icache_auto_master_out_d_bits_size = auto_icache_master_out_d_bits_size; // @[LazyModule.scala 311:12]
  assign icache_auto_master_out_d_bits_data = auto_icache_master_out_d_bits_data; // @[LazyModule.scala 311:12]
  assign icache_auto_master_out_d_bits_corrupt = auto_icache_master_out_d_bits_corrupt; // @[LazyModule.scala 311:12]
  assign icache_io_req_valid = io_cpu_req_valid | s0_fq_has_space; // @[Frontend.scala 110:35]
  assign icache_io_req_bits_addr = io_cpu_npc; // @[Frontend.scala 162:27]
  assign icache_io_s1_paddr = tlb_io_resp_paddr; // @[Frontend.scala 164:22]
  assign icache_io_s2_vaddr = s2_pc; // @[Frontend.scala 165:22]
  assign icache_io_s1_kill = s2_redirect | s2_replay; // @[Frontend.scala 166:56]
  assign icache_io_s2_kill = s2_speculative & ~s2_can_speculatively_refill | s2_tlb_resp_ae_inst; // @[Frontend.scala 168:71]
  assign icache_io_invalidate = io_cpu_flush_icache; // @[Frontend.scala 163:24]
  assign fq_clock = clock;
  assign fq_reset = reset | io_cpu_req_valid; // @[Frontend.scala 88:28]
  assign fq_io_enq_valid = fq_io_enq_valid_REG & s2_valid & (icache_io_resp_valid | icache_io_s2_kill); // @[Frontend.scala 171:52]
  assign fq_io_enq_bits_btb_taken = _taken_T_36 ? _GEN_127 : s2_btb_taken; // @[Frontend.scala 317:26 179:28]
  assign fq_io_enq_bits_btb_bridx = _taken_T_36 ? _GEN_126 : s2_btb_resp_bits_bridx; // @[Frontend.scala 178:22 317:26]
  assign fq_io_enq_bits_btb_entry = _taken_T_36 ? _GEN_128 : s2_btb_resp_bits_entry; // @[Frontend.scala 178:22 317:26]
  assign fq_io_enq_bits_btb_bht_history = s2_btb_resp_bits_bht_history; // @[Frontend.scala 178:22]
  assign fq_io_enq_bits_pc = s2_pc; // @[Frontend.scala 172:21]
  assign fq_io_enq_bits_data = icache_io_resp_bits_data; // @[Frontend.scala 175:23]
  assign fq_io_enq_bits_mask = _fq_io_enq_bits_mask_T_1[1:0]; // @[Frontend.scala 176:23]
  assign fq_io_enq_bits_xcpt_ae_inst = icache_io_resp_valid & icache_io_resp_bits_ae | s2_tlb_resp_ae_inst; // @[Frontend.scala 180:23 182:{57,87}]
  assign fq_io_enq_bits_replay = s2_valid & s2_btb_resp_valid & s2_btb_resp_bits_bridx & taken_valid_1 & ~taken_rvc_1 |
    _GEN_48; // @[Frontend.scala 242:95 246:31]
  assign fq_io_deq_ready = io_cpu_resp_ready; // @[Frontend.scala 331:15]
  assign tlb_io_req_bits_vaddr = s1_pc; // @[Frontend.scala 153:25]
  assign tlb_io_req_bits_prv = io_ptw_status_prv; // @[Frontend.scala 156:23]
  assign tlb_io_ptw_status_debug = io_ptw_status_debug; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_0_cfg_l = io_ptw_pmp_0_cfg_l; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_0_cfg_a = io_ptw_pmp_0_cfg_a; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_0_cfg_x = io_ptw_pmp_0_cfg_x; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_0_cfg_w = io_ptw_pmp_0_cfg_w; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_0_cfg_r = io_ptw_pmp_0_cfg_r; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_0_addr = io_ptw_pmp_0_addr; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_0_mask = io_ptw_pmp_0_mask; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_1_cfg_l = io_ptw_pmp_1_cfg_l; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_1_cfg_a = io_ptw_pmp_1_cfg_a; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_1_cfg_x = io_ptw_pmp_1_cfg_x; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_1_cfg_w = io_ptw_pmp_1_cfg_w; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_1_cfg_r = io_ptw_pmp_1_cfg_r; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_1_addr = io_ptw_pmp_1_addr; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_1_mask = io_ptw_pmp_1_mask; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_2_cfg_l = io_ptw_pmp_2_cfg_l; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_2_cfg_a = io_ptw_pmp_2_cfg_a; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_2_cfg_x = io_ptw_pmp_2_cfg_x; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_2_cfg_w = io_ptw_pmp_2_cfg_w; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_2_cfg_r = io_ptw_pmp_2_cfg_r; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_2_addr = io_ptw_pmp_2_addr; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_2_mask = io_ptw_pmp_2_mask; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_3_cfg_l = io_ptw_pmp_3_cfg_l; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_3_cfg_a = io_ptw_pmp_3_cfg_a; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_3_cfg_x = io_ptw_pmp_3_cfg_x; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_3_cfg_w = io_ptw_pmp_3_cfg_w; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_3_cfg_r = io_ptw_pmp_3_cfg_r; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_3_addr = io_ptw_pmp_3_addr; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_3_mask = io_ptw_pmp_3_mask; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_4_cfg_l = io_ptw_pmp_4_cfg_l; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_4_cfg_a = io_ptw_pmp_4_cfg_a; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_4_cfg_x = io_ptw_pmp_4_cfg_x; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_4_cfg_w = io_ptw_pmp_4_cfg_w; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_4_cfg_r = io_ptw_pmp_4_cfg_r; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_4_addr = io_ptw_pmp_4_addr; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_4_mask = io_ptw_pmp_4_mask; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_5_cfg_l = io_ptw_pmp_5_cfg_l; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_5_cfg_a = io_ptw_pmp_5_cfg_a; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_5_cfg_x = io_ptw_pmp_5_cfg_x; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_5_cfg_w = io_ptw_pmp_5_cfg_w; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_5_cfg_r = io_ptw_pmp_5_cfg_r; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_5_addr = io_ptw_pmp_5_addr; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_5_mask = io_ptw_pmp_5_mask; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_6_cfg_l = io_ptw_pmp_6_cfg_l; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_6_cfg_a = io_ptw_pmp_6_cfg_a; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_6_cfg_x = io_ptw_pmp_6_cfg_x; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_6_cfg_w = io_ptw_pmp_6_cfg_w; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_6_cfg_r = io_ptw_pmp_6_cfg_r; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_6_addr = io_ptw_pmp_6_addr; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_6_mask = io_ptw_pmp_6_mask; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_7_cfg_l = io_ptw_pmp_7_cfg_l; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_7_cfg_a = io_ptw_pmp_7_cfg_a; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_7_cfg_x = io_ptw_pmp_7_cfg_x; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_7_cfg_w = io_ptw_pmp_7_cfg_w; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_7_cfg_r = io_ptw_pmp_7_cfg_r; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_7_addr = io_ptw_pmp_7_addr; // @[Frontend.scala 151:10]
  assign tlb_io_ptw_pmp_7_mask = io_ptw_pmp_7_mask; // @[Frontend.scala 151:10]
  assign btb_clock = clock;
  assign btb_reset = reset;
  assign btb_io_req_bits_addr = s1_pc; // @[Frontend.scala 188:26]
  assign btb_io_btb_update_valid = ~io_cpu_btb_update_valid ? _s2_replay_T & ~wrong_path & fetch_bubble_likely &
    updateBTB : io_cpu_btb_update_valid; // @[Frontend.scala 189:23 298:37 300:31]
  assign btb_io_btb_update_bits_prediction_entry = ~io_cpu_btb_update_valid ? 5'h1c :
    io_cpu_btb_update_bits_prediction_entry; // @[Frontend.scala 189:23 298:37 301:47]
  assign btb_io_btb_update_bits_pc = ~io_cpu_btb_update_valid ? s2_base_pc : io_cpu_btb_update_bits_pc; // @[Frontend.scala 189:23 298:37 305:33]
  assign btb_io_btb_update_bits_isValid = ~io_cpu_btb_update_valid | io_cpu_btb_update_bits_isValid; // @[Frontend.scala 189:23 298:37 302:38]
  assign btb_io_btb_update_bits_br_pc = ~io_cpu_btb_update_valid ? _btb_io_btb_update_bits_br_pc_T_1 :
    io_cpu_btb_update_bits_br_pc; // @[Frontend.scala 189:23 298:37 304:36]
  assign btb_io_btb_update_bits_cfiType = ~io_cpu_btb_update_valid ? btb_io_ras_update_bits_cfiType :
    io_cpu_btb_update_bits_cfiType; // @[Frontend.scala 189:23 298:37 303:38]
  assign btb_io_bht_update_valid = io_cpu_bht_update_valid; // @[Frontend.scala 190:23 205:{24,50}]
  assign btb_io_bht_update_bits_prediction_history = io_cpu_bht_update_bits_prediction_history; // @[Frontend.scala 190:23]
  assign btb_io_bht_update_bits_pc = io_cpu_bht_update_bits_pc; // @[Frontend.scala 190:23]
  assign btb_io_bht_update_bits_branch = io_cpu_bht_update_bits_branch; // @[Frontend.scala 190:23]
  assign btb_io_bht_update_bits_taken = io_cpu_bht_update_bits_taken; // @[Frontend.scala 190:23]
  assign btb_io_bht_update_bits_mispredict = io_cpu_bht_update_bits_mispredict; // @[Frontend.scala 190:23]
  assign btb_io_bht_advance_valid = taken_idx ? _GEN_92 : _GEN_56; // @[Frontend.scala 251:25]
  assign btb_io_bht_advance_bits_bht_value = s2_btb_resp_bits_bht_value; // @[Frontend.scala 251:25]
  assign btb_io_ras_update_valid = taken_idx ? _btb_io_btb_update_valid_T_2 & (taken_prevRVI_1 & (taken_rviCall_1 |
    taken_rviReturn_1) | taken_valid_1 & (taken_rvcCall_1 | taken_rvcReturn_1)) : _btb_io_btb_update_valid_T_2 & (
    taken_prevRVI & (taken_rviCall | taken_rviReturn) | taken_valid & (taken_rvcCall | taken_rvcReturn)); // @[Frontend.scala 251:25 254:33]
  assign btb_io_ras_update_bits_cfiType = taken_idx ? _taken_btb_io_ras_update_bits_cfiType_T_15 :
    _taken_btb_io_ras_update_bits_cfiType_T_7; // @[Frontend.scala 251:25 255:40]
  assign btb_io_ras_update_bits_returnAddr = s2_base_pc + _GEN_142; // @[Frontend.scala 308:53]
  assign btb_io_flush = s2_valid & s2_btb_resp_valid & s2_btb_resp_bits_bridx & taken_valid_1 & ~taken_rvc_1 | s2_valid
     & s2_btb_resp_valid & ~s2_btb_resp_bits_bridx & taken_valid & _taken_prevRVI_T_5; // @[Frontend.scala 242:95 245:22]
  always @(posedge clock) begin
    s1_valid <= io_cpu_req_valid | s0_fq_has_space; // @[Frontend.scala 110:35]
    if (reset) begin // @[Frontend.scala 105:25]
      s2_valid <= 1'h0; // @[Frontend.scala 105:25]
    end else begin
      s2_valid <= _GEN_0;
    end
    s1_pc <= io_cpu_npc; // @[Frontend.scala 134:9]
    if (io_cpu_req_valid) begin // @[Frontend.scala 140:24]
      s1_speculative <= io_cpu_req_bits_speculative;
    end else if (s2_replay) begin // @[Frontend.scala 140:75]
      s1_speculative <= s2_speculative;
    end else begin
      s1_speculative <= s0_speculative;
    end
    if (reset) begin // @[Frontend.scala 114:22]
      s2_pc <= 32'h10040; // @[Frontend.scala 114:22]
    end else if (~s2_replay) begin // @[Frontend.scala 144:21]
      s2_pc <= s1_pc; // @[Frontend.scala 146:11]
    end
    if (_T_11) begin // @[Frontend.scala 193:23]
      s2_btb_resp_valid <= btb_io_resp_valid; // @[Frontend.scala 195:25]
    end
    if (_T_11) begin // @[Frontend.scala 193:23]
      s2_btb_resp_bits_taken <= btb_io_resp_bits_taken; // @[Frontend.scala 196:24]
    end
    if (_T_11) begin // @[Frontend.scala 193:23]
      s2_btb_resp_bits_bridx <= btb_io_resp_bits_bridx; // @[Frontend.scala 196:24]
    end
    if (_T_11) begin // @[Frontend.scala 193:23]
      s2_btb_resp_bits_entry <= btb_io_resp_bits_entry; // @[Frontend.scala 196:24]
    end
    if (_T_11) begin // @[Frontend.scala 193:23]
      s2_btb_resp_bits_bht_history <= btb_io_resp_bits_bht_history; // @[Frontend.scala 196:24]
    end
    if (_T_11) begin // @[Frontend.scala 193:23]
      s2_btb_resp_bits_bht_value <= btb_io_resp_bits_bht_value; // @[Frontend.scala 196:24]
    end
    if (~s2_replay) begin // @[Frontend.scala 144:21]
      s2_tlb_resp_ae_inst <= tlb_io_resp_ae_inst; // @[Frontend.scala 148:17]
    end
    if (~s2_replay) begin // @[Frontend.scala 144:21]
      s2_tlb_resp_cacheable <= tlb_io_resp_cacheable; // @[Frontend.scala 148:17]
    end
    if (reset) begin // @[Frontend.scala 120:27]
      s2_speculative <= 1'h0; // @[Frontend.scala 120:27]
    end else if (~s2_replay) begin // @[Frontend.scala 144:21]
      s2_speculative <= s1_speculative; // @[Frontend.scala 147:20]
    end
    if (reset) begin // @[Frontend.scala 121:38]
      s2_partial_insn_valid <= 1'h0; // @[Frontend.scala 121:38]
    end else if (s2_redirect) begin // @[Frontend.scala 327:24]
      s2_partial_insn_valid <= 1'h0; // @[Frontend.scala 327:48]
    end else if (_s2_replay_T & (s2_btb_taken | taken)) begin // @[Frontend.scala 314:56]
      s2_partial_insn_valid <= 1'h0; // @[Frontend.scala 315:29]
    end else if (_s2_replay_T) begin // @[Frontend.scala 285:33]
      s2_partial_insn_valid <= _taken_T_61;
    end
    if (_s2_replay_T) begin // @[Frontend.scala 285:33]
      if (taken_valid_1 & taken_idx & _taken_T_33) begin // @[Frontend.scala 287:46]
        s2_partial_insn <= _taken_s2_partial_insn_T; // @[Frontend.scala 289:29]
      end
    end
    if (reset) begin // @[Frontend.scala 123:27]
      wrong_path <= 1'h0; // @[Frontend.scala 123:27]
    end else if (io_cpu_req_valid) begin // @[Frontend.scala 328:29]
      wrong_path <= 1'h0; // @[Frontend.scala 328:42]
    end else if (taken_idx) begin // @[Frontend.scala 251:25]
      if (~s2_btb_taken) begin // @[Frontend.scala 260:30]
        wrong_path <= _GEN_86;
      end else begin
        wrong_path <= _GEN_85;
      end
    end else begin
      wrong_path <= _GEN_85;
    end
    s2_replay_REG <= reset | s2_replay & ~s0_valid; // @[Frontend.scala 131:{58,58,58}]
    fq_io_enq_valid_REG <= s1_valid; // @[Frontend.scala 171:29]
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_cpu_req_valid | io_cpu_flush_icache | io_cpu_bht_update_valid | io_cpu_btb_update_valid) |
          io_cpu_might_request) & ~reset) begin
          $fatal; // @[Frontend.scala 93:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~(io_cpu_req_valid | io_cpu_flush_icache | io_cpu_bht_update_valid | io_cpu_btb_update_valid) |
          io_cpu_might_request)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Frontend.scala:93 assert(!(io.cpu.req.valid || io.cpu.sfence.valid || io.cpu.flush_icache || io.cpu.bht_update.valid || io.cpu.btb_update.valid) || io.cpu.might_request)\n"
            ); // @[Frontend.scala 93:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(s2_speculative & io_ptw_customCSRs_csrs_0_value[3] & ~icache_io_s2_kill)) & _T_9) begin
          $fatal; // @[Frontend.scala 181:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_9 & ~(~(s2_speculative & io_ptw_customCSRs_csrs_0_value[3] & ~icache_io_s2_kill))) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Frontend.scala:181 assert(!(s2_speculative && io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableSpeculativeICacheRefill && !icache.io.s2_kill))\n"
            ); // @[Frontend.scala 181:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~s2_partial_insn_valid | fq_io_enq_bits_mask[0]) & _T_9) begin
          $fatal; // @[Frontend.scala 326:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_9 & ~(~s2_partial_insn_valid | fq_io_enq_bits_mask[0])) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Frontend.scala:326 assert(!s2_partial_insn_valid || fq.io.enq.bits.mask(0))\n"); // @[Frontend.scala 326:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  s1_valid = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  s2_valid = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  s1_pc = _RAND_2[31:0];
  _RAND_3 = {1{`RANDOM}};
  s1_speculative = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  s2_pc = _RAND_4[31:0];
  _RAND_5 = {1{`RANDOM}};
  s2_btb_resp_valid = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  s2_btb_resp_bits_taken = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  s2_btb_resp_bits_bridx = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  s2_btb_resp_bits_entry = _RAND_8[4:0];
  _RAND_9 = {1{`RANDOM}};
  s2_btb_resp_bits_bht_history = _RAND_9[7:0];
  _RAND_10 = {1{`RANDOM}};
  s2_btb_resp_bits_bht_value = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  s2_tlb_resp_ae_inst = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  s2_tlb_resp_cacheable = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  s2_speculative = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  s2_partial_insn_valid = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  s2_partial_insn = _RAND_15[15:0];
  _RAND_16 = {1{`RANDOM}};
  wrong_path = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  s2_replay_REG = _RAND_17[0:0];
  _RAND_18 = {1{`RANDOM}};
  fq_io_enq_valid_REG = _RAND_18[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLFragmenter_21(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [27:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output [31:0] auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [1:0]  auto_out_a_bits_size,
  output [7:0]  auto_out_a_bits_source,
  output [27:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_size,
  input  [7:0]  auto_out_d_bits_source,
  input  [31:0] auto_out_d_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
  wire  repeater_clock; // @[Fragmenter.scala 262:30]
  wire  repeater_reset; // @[Fragmenter.scala 262:30]
  wire  repeater_io_repeat; // @[Fragmenter.scala 262:30]
  wire  repeater_io_full; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_enq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_enq_bits_source; // @[Fragmenter.scala 262:30]
  wire [27:0] repeater_io_enq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_enq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_ready; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_valid; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_opcode; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_param; // @[Fragmenter.scala 262:30]
  wire [2:0] repeater_io_deq_bits_size; // @[Fragmenter.scala 262:30]
  wire [1:0] repeater_io_deq_bits_source; // @[Fragmenter.scala 262:30]
  wire [27:0] repeater_io_deq_bits_address; // @[Fragmenter.scala 262:30]
  wire [3:0] repeater_io_deq_bits_mask; // @[Fragmenter.scala 262:30]
  wire  repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 262:30]
  reg [3:0] acknum; // @[Fragmenter.scala 189:29]
  reg [2:0] dOrig; // @[Fragmenter.scala 190:24]
  reg  dToggle; // @[Fragmenter.scala 191:30]
  wire [3:0] dFragnum = auto_out_d_bits_source[3:0]; // @[Fragmenter.scala 192:41]
  wire  dFirst = acknum == 4'h0; // @[Fragmenter.scala 193:29]
  wire  dLast = dFragnum == 4'h0; // @[Fragmenter.scala 194:30]
  wire [3:0] _dsizeOH_T = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 64:12]
  wire [2:0] dsizeOH = _dsizeOH_T[2:0]; // @[OneHot.scala 64:27]
  wire [4:0] _dsizeOH1_T_1 = 5'h3 << auto_out_d_bits_size; // @[package.scala 234:77]
  wire [1:0] dsizeOH1 = ~_dsizeOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  dHasData = auto_out_d_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  _T_5 = ~reset; // @[Fragmenter.scala 202:16]
  wire  ack_decrement = dHasData | dsizeOH[2]; // @[Fragmenter.scala 204:32]
  wire [5:0] _dFirst_size_T = {dFragnum, 2'h0}; // @[Fragmenter.scala 206:47]
  wire [5:0] _GEN_7 = {{4'd0}, dsizeOH1}; // @[Fragmenter.scala 206:69]
  wire [5:0] _dFirst_size_T_1 = _dFirst_size_T | _GEN_7; // @[Fragmenter.scala 206:69]
  wire [6:0] _dFirst_size_T_2 = {_dFirst_size_T_1, 1'h0}; // @[package.scala 232:35]
  wire [6:0] _dFirst_size_T_3 = _dFirst_size_T_2 | 7'h1; // @[package.scala 232:40]
  wire [6:0] _dFirst_size_T_4 = {1'h0,_dFirst_size_T_1}; // @[Cat.scala 31:58]
  wire [6:0] _dFirst_size_T_5 = ~_dFirst_size_T_4; // @[package.scala 232:53]
  wire [6:0] _dFirst_size_T_6 = _dFirst_size_T_3 & _dFirst_size_T_5; // @[package.scala 232:51]
  wire [2:0] dFirst_size_hi = _dFirst_size_T_6[6:4]; // @[OneHot.scala 30:18]
  wire [3:0] dFirst_size_lo = _dFirst_size_T_6[3:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_7 = |dFirst_size_hi; // @[OneHot.scala 32:14]
  wire [3:0] _GEN_8 = {{1'd0}, dFirst_size_hi}; // @[OneHot.scala 32:28]
  wire [3:0] _dFirst_size_T_8 = _GEN_8 | dFirst_size_lo; // @[OneHot.scala 32:28]
  wire [1:0] dFirst_size_hi_1 = _dFirst_size_T_8[3:2]; // @[OneHot.scala 30:18]
  wire [1:0] dFirst_size_lo_1 = _dFirst_size_T_8[1:0]; // @[OneHot.scala 31:18]
  wire  _dFirst_size_T_9 = |dFirst_size_hi_1; // @[OneHot.scala 32:14]
  wire [1:0] _dFirst_size_T_10 = dFirst_size_hi_1 | dFirst_size_lo_1; // @[OneHot.scala 32:28]
  wire [2:0] dFirst_size = {_dFirst_size_T_7,_dFirst_size_T_9,_dFirst_size_T_10[1]}; // @[Cat.scala 31:58]
  wire  doEarlyAck = auto_out_d_bits_source[5]; // @[Fragmenter.scala 219:54]
  wire  _drop_T_1 = doEarlyAck ? dFirst : dLast; // @[Fragmenter.scala 222:37]
  wire  drop = ~dHasData & ~_drop_T_1; // @[Fragmenter.scala 222:30]
  wire  bundleOut_0_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  wire  _T_7 = bundleOut_0_d_ready & auto_out_d_valid; // @[Decoupled.scala 50:35]
  wire [3:0] _GEN_9 = {{3'd0}, ack_decrement}; // @[Fragmenter.scala 209:55]
  wire [3:0] _acknum_T_1 = acknum - _GEN_9; // @[Fragmenter.scala 209:55]
  wire [2:0] aFrag = repeater_io_deq_bits_size > 3'h2 ? 3'h2 : repeater_io_deq_bits_size; // @[Fragmenter.scala 285:24]
  wire [12:0] _aOrigOH1_T_1 = 13'h3f << repeater_io_deq_bits_size; // @[package.scala 234:77]
  wire [5:0] aOrigOH1 = ~_aOrigOH1_T_1[5:0]; // @[package.scala 234:46]
  wire [8:0] _aFragOH1_T_1 = 9'h3 << aFrag; // @[package.scala 234:77]
  wire [1:0] aFragOH1 = ~_aFragOH1_T_1[1:0]; // @[package.scala 234:46]
  wire  aHasData = ~repeater_io_deq_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [3:0] gennum; // @[Fragmenter.scala 291:29]
  wire  aFirst = gennum == 4'h0; // @[Fragmenter.scala 292:29]
  wire [3:0] _old_gennum1_T_2 = gennum - 4'h1; // @[Fragmenter.scala 293:79]
  wire [3:0] old_gennum1 = aFirst ? aOrigOH1[5:2] : _old_gennum1_T_2; // @[Fragmenter.scala 293:30]
  wire [3:0] _new_gennum_T = ~old_gennum1; // @[Fragmenter.scala 294:28]
  wire [3:0] new_gennum = ~_new_gennum_T; // @[Fragmenter.scala 294:26]
  reg  aToggle_r; // @[Reg.scala 16:16]
  wire  _GEN_5 = aFirst ? dToggle : aToggle_r; // @[Reg.scala 16:16 17:{18,22}]
  wire  aToggle = ~_GEN_5; // @[Fragmenter.scala 297:23]
  wire  aFull = repeater_io_deq_bits_opcode == 3'h0; // @[Fragmenter.scala 298:78]
  wire  bundleOut_0_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  wire  _T_8 = auto_out_a_ready & bundleOut_0_a_valid; // @[Decoupled.scala 50:35]
  wire  _repeater_io_repeat_T = ~aHasData; // @[Fragmenter.scala 302:31]
  wire [5:0] _bundleOut_0_a_bits_address_T = {old_gennum1, 2'h0}; // @[Fragmenter.scala 304:65]
  wire [5:0] _bundleOut_0_a_bits_address_T_1 = ~aOrigOH1; // @[Fragmenter.scala 304:90]
  wire [5:0] _bundleOut_0_a_bits_address_T_2 = _bundleOut_0_a_bits_address_T | _bundleOut_0_a_bits_address_T_1; // @[Fragmenter.scala 304:88]
  wire [5:0] _GEN_10 = {{4'd0}, aFragOH1}; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_3 = _bundleOut_0_a_bits_address_T_2 | _GEN_10; // @[Fragmenter.scala 304:100]
  wire [5:0] _bundleOut_0_a_bits_address_T_4 = _bundleOut_0_a_bits_address_T_3 | 6'h3; // @[Fragmenter.scala 304:111]
  wire [5:0] _bundleOut_0_a_bits_address_T_5 = ~_bundleOut_0_a_bits_address_T_4; // @[Fragmenter.scala 304:51]
  wire [27:0] _GEN_11 = {{22'd0}, _bundleOut_0_a_bits_address_T_5}; // @[Fragmenter.scala 304:49]
  wire [4:0] bundleOut_0_a_bits_source_lo = {aToggle,new_gennum}; // @[Cat.scala 31:58]
  wire [2:0] bundleOut_0_a_bits_source_hi = {repeater_io_deq_bits_source,aFull}; // @[Cat.scala 31:58]
  wire  _T_9 = ~repeater_io_full; // @[Fragmenter.scala 309:17]
  Repeater_16 repeater ( // @[Fragmenter.scala 262:30]
    .clock(repeater_clock),
    .reset(repeater_reset),
    .io_repeat(repeater_io_repeat),
    .io_full(repeater_io_full),
    .io_enq_ready(repeater_io_enq_ready),
    .io_enq_valid(repeater_io_enq_valid),
    .io_enq_bits_opcode(repeater_io_enq_bits_opcode),
    .io_enq_bits_param(repeater_io_enq_bits_param),
    .io_enq_bits_size(repeater_io_enq_bits_size),
    .io_enq_bits_source(repeater_io_enq_bits_source),
    .io_enq_bits_address(repeater_io_enq_bits_address),
    .io_enq_bits_mask(repeater_io_enq_bits_mask),
    .io_enq_bits_corrupt(repeater_io_enq_bits_corrupt),
    .io_deq_ready(repeater_io_deq_ready),
    .io_deq_valid(repeater_io_deq_valid),
    .io_deq_bits_opcode(repeater_io_deq_bits_opcode),
    .io_deq_bits_param(repeater_io_deq_bits_param),
    .io_deq_bits_size(repeater_io_deq_bits_size),
    .io_deq_bits_source(repeater_io_deq_bits_source),
    .io_deq_bits_address(repeater_io_deq_bits_address),
    .io_deq_bits_mask(repeater_io_deq_bits_mask),
    .io_deq_bits_corrupt(repeater_io_deq_bits_corrupt)
  );
  assign auto_in_a_ready = repeater_io_enq_ready; // @[Nodes.scala 1210:84 Fragmenter.scala 263:25]
  assign auto_in_d_valid = auto_out_d_valid & ~drop; // @[Fragmenter.scala 224:36]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = dFirst ? dFirst_size : dOrig; // @[Fragmenter.scala 227:32]
  assign auto_in_d_bits_source = auto_out_d_bits_source[7:6]; // @[Fragmenter.scala 226:47]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = repeater_io_deq_valid; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_opcode = repeater_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Fragmenter.scala 303:15]
  assign auto_out_a_bits_size = aFrag[1:0]; // @[Nodes.scala 1207:84 Fragmenter.scala 306:25]
  assign auto_out_a_bits_source = {bundleOut_0_a_bits_source_hi,bundleOut_0_a_bits_source_lo}; // @[Cat.scala 31:58]
  assign auto_out_a_bits_address = repeater_io_deq_bits_address | _GEN_11; // @[Fragmenter.scala 304:49]
  assign auto_out_a_bits_mask = repeater_io_full ? 4'hf : auto_in_a_bits_mask; // @[Fragmenter.scala 313:31]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_d_ready = auto_in_d_ready | drop; // @[Fragmenter.scala 223:35]
  assign repeater_clock = clock;
  assign repeater_reset = reset;
  assign repeater_io_repeat = ~aHasData & new_gennum != 4'h0; // @[Fragmenter.scala 302:41]
  assign repeater_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign repeater_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  always @(posedge clock) begin
    if (reset) begin // @[Fragmenter.scala 189:29]
      acknum <= 4'h0; // @[Fragmenter.scala 189:29]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 209:24]
        acknum <= dFragnum;
      end else begin
        acknum <= _acknum_T_1;
      end
    end
    if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dOrig <= dFirst_size; // @[Fragmenter.scala 211:19]
      end
    end
    if (reset) begin // @[Fragmenter.scala 191:30]
      dToggle <= 1'h0; // @[Fragmenter.scala 191:30]
    end else if (_T_7) begin // @[Fragmenter.scala 208:29]
      if (dFirst) begin // @[Fragmenter.scala 210:25]
        dToggle <= auto_out_d_bits_source[4]; // @[Fragmenter.scala 212:21]
      end
    end
    if (reset) begin // @[Fragmenter.scala 291:29]
      gennum <= 4'h0; // @[Fragmenter.scala 291:29]
    end else if (_T_8) begin // @[Fragmenter.scala 300:29]
      gennum <= new_gennum; // @[Fragmenter.scala 300:38]
    end
    if (aFirst) begin // @[Reg.scala 17:18]
      aToggle_r <= dToggle; // @[Reg.scala 17:22]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~repeater_io_full | _repeater_io_repeat_T) & _T_5) begin
          $fatal; // @[Fragmenter.scala 309:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(~repeater_io_full | _repeater_io_repeat_T)) begin
          $fwrite(32'h80000002,"Assertion failed\n    at Fragmenter.scala:309 assert (!repeater.io.full || !aHasData)\n"
            ); // @[Fragmenter.scala 309:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_9 | repeater_io_deq_bits_mask == 4'hf) & _T_5) begin
          $fatal; // @[Fragmenter.scala 312:16]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_5 & ~(_T_9 | repeater_io_deq_bits_mask == 4'hf)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Fragmenter.scala:312 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"
            ); // @[Fragmenter.scala 312:16]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  acknum = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  dOrig = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  dToggle = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  gennum = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  aToggle_r = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module HellaCacheArbiter(
  output        io_requestor_0_req_ready,
  input         io_requestor_0_req_valid,
  input  [31:0] io_requestor_0_req_bits_addr,
  input  [5:0]  io_requestor_0_req_bits_tag,
  input  [4:0]  io_requestor_0_req_bits_cmd,
  input  [1:0]  io_requestor_0_req_bits_size,
  input         io_requestor_0_req_bits_signed,
  input  [1:0]  io_requestor_0_req_bits_dprv,
  input         io_requestor_0_s1_kill,
  input  [31:0] io_requestor_0_s1_data_data,
  output        io_requestor_0_s2_nack,
  output        io_requestor_0_resp_valid,
  output [5:0]  io_requestor_0_resp_bits_tag,
  output [31:0] io_requestor_0_resp_bits_data,
  output        io_requestor_0_resp_bits_replay,
  output        io_requestor_0_resp_bits_has_data,
  output [31:0] io_requestor_0_resp_bits_data_word_bypass,
  output        io_requestor_0_replay_next,
  output        io_requestor_0_s2_xcpt_ma_ld,
  output        io_requestor_0_s2_xcpt_ma_st,
  output        io_requestor_0_s2_xcpt_pf_ld,
  output        io_requestor_0_s2_xcpt_pf_st,
  output        io_requestor_0_s2_xcpt_ae_ld,
  output        io_requestor_0_s2_xcpt_ae_st,
  output        io_requestor_0_ordered,
  output        io_requestor_0_perf_release,
  output        io_requestor_0_perf_grant,
  input         io_mem_req_ready,
  output        io_mem_req_valid,
  output [31:0] io_mem_req_bits_addr,
  output [5:0]  io_mem_req_bits_tag,
  output [4:0]  io_mem_req_bits_cmd,
  output [1:0]  io_mem_req_bits_size,
  output        io_mem_req_bits_signed,
  output [1:0]  io_mem_req_bits_dprv,
  output        io_mem_s1_kill,
  output [31:0] io_mem_s1_data_data,
  input         io_mem_s2_nack,
  input         io_mem_resp_valid,
  input  [5:0]  io_mem_resp_bits_tag,
  input  [31:0] io_mem_resp_bits_data,
  input         io_mem_resp_bits_replay,
  input         io_mem_resp_bits_has_data,
  input  [31:0] io_mem_resp_bits_data_word_bypass,
  input         io_mem_replay_next,
  input         io_mem_s2_xcpt_ma_ld,
  input         io_mem_s2_xcpt_ma_st,
  input         io_mem_s2_xcpt_pf_ld,
  input         io_mem_s2_xcpt_pf_st,
  input         io_mem_s2_xcpt_ae_ld,
  input         io_mem_s2_xcpt_ae_st,
  input         io_mem_ordered,
  input         io_mem_perf_release,
  input         io_mem_perf_grant
);
  assign io_requestor_0_req_ready = io_mem_req_ready; // @[HellaCacheArbiter.scala 17:12]
  assign io_requestor_0_s2_nack = io_mem_s2_nack; // @[HellaCacheArbiter.scala 17:12]
  assign io_requestor_0_resp_valid = io_mem_resp_valid; // @[HellaCacheArbiter.scala 17:12]
  assign io_requestor_0_resp_bits_tag = io_mem_resp_bits_tag; // @[HellaCacheArbiter.scala 17:12]
  assign io_requestor_0_resp_bits_data = io_mem_resp_bits_data; // @[HellaCacheArbiter.scala 17:12]
  assign io_requestor_0_resp_bits_replay = io_mem_resp_bits_replay; // @[HellaCacheArbiter.scala 17:12]
  assign io_requestor_0_resp_bits_has_data = io_mem_resp_bits_has_data; // @[HellaCacheArbiter.scala 17:12]
  assign io_requestor_0_resp_bits_data_word_bypass = io_mem_resp_bits_data_word_bypass; // @[HellaCacheArbiter.scala 17:12]
  assign io_requestor_0_replay_next = io_mem_replay_next; // @[HellaCacheArbiter.scala 17:12]
  assign io_requestor_0_s2_xcpt_ma_ld = io_mem_s2_xcpt_ma_ld; // @[HellaCacheArbiter.scala 17:12]
  assign io_requestor_0_s2_xcpt_ma_st = io_mem_s2_xcpt_ma_st; // @[HellaCacheArbiter.scala 17:12]
  assign io_requestor_0_s2_xcpt_pf_ld = io_mem_s2_xcpt_pf_ld; // @[HellaCacheArbiter.scala 17:12]
  assign io_requestor_0_s2_xcpt_pf_st = io_mem_s2_xcpt_pf_st; // @[HellaCacheArbiter.scala 17:12]
  assign io_requestor_0_s2_xcpt_ae_ld = io_mem_s2_xcpt_ae_ld; // @[HellaCacheArbiter.scala 17:12]
  assign io_requestor_0_s2_xcpt_ae_st = io_mem_s2_xcpt_ae_st; // @[HellaCacheArbiter.scala 17:12]
  assign io_requestor_0_ordered = io_mem_ordered; // @[HellaCacheArbiter.scala 17:12]
  assign io_requestor_0_perf_release = io_mem_perf_release; // @[HellaCacheArbiter.scala 17:12]
  assign io_requestor_0_perf_grant = io_mem_perf_grant; // @[HellaCacheArbiter.scala 17:12]
  assign io_mem_req_valid = io_requestor_0_req_valid; // @[HellaCacheArbiter.scala 17:12]
  assign io_mem_req_bits_addr = io_requestor_0_req_bits_addr; // @[HellaCacheArbiter.scala 17:12]
  assign io_mem_req_bits_tag = io_requestor_0_req_bits_tag; // @[HellaCacheArbiter.scala 17:12]
  assign io_mem_req_bits_cmd = io_requestor_0_req_bits_cmd; // @[HellaCacheArbiter.scala 17:12]
  assign io_mem_req_bits_size = io_requestor_0_req_bits_size; // @[HellaCacheArbiter.scala 17:12]
  assign io_mem_req_bits_signed = io_requestor_0_req_bits_signed; // @[HellaCacheArbiter.scala 17:12]
  assign io_mem_req_bits_dprv = io_requestor_0_req_bits_dprv; // @[HellaCacheArbiter.scala 17:12]
  assign io_mem_s1_kill = io_requestor_0_s1_kill; // @[HellaCacheArbiter.scala 17:12]
  assign io_mem_s1_data_data = io_requestor_0_s1_data_data; // @[HellaCacheArbiter.scala 17:12]
endmodule
module PTW(
  input         clock,
  input         reset,
  output        io_requestor_0_status_debug,
  output        io_requestor_0_pmp_0_cfg_l,
  output [1:0]  io_requestor_0_pmp_0_cfg_a,
  output        io_requestor_0_pmp_0_cfg_x,
  output        io_requestor_0_pmp_0_cfg_w,
  output        io_requestor_0_pmp_0_cfg_r,
  output [28:0] io_requestor_0_pmp_0_addr,
  output [30:0] io_requestor_0_pmp_0_mask,
  output        io_requestor_0_pmp_1_cfg_l,
  output [1:0]  io_requestor_0_pmp_1_cfg_a,
  output        io_requestor_0_pmp_1_cfg_x,
  output        io_requestor_0_pmp_1_cfg_w,
  output        io_requestor_0_pmp_1_cfg_r,
  output [28:0] io_requestor_0_pmp_1_addr,
  output [30:0] io_requestor_0_pmp_1_mask,
  output        io_requestor_0_pmp_2_cfg_l,
  output [1:0]  io_requestor_0_pmp_2_cfg_a,
  output        io_requestor_0_pmp_2_cfg_x,
  output        io_requestor_0_pmp_2_cfg_w,
  output        io_requestor_0_pmp_2_cfg_r,
  output [28:0] io_requestor_0_pmp_2_addr,
  output [30:0] io_requestor_0_pmp_2_mask,
  output        io_requestor_0_pmp_3_cfg_l,
  output [1:0]  io_requestor_0_pmp_3_cfg_a,
  output        io_requestor_0_pmp_3_cfg_x,
  output        io_requestor_0_pmp_3_cfg_w,
  output        io_requestor_0_pmp_3_cfg_r,
  output [28:0] io_requestor_0_pmp_3_addr,
  output [30:0] io_requestor_0_pmp_3_mask,
  output        io_requestor_0_pmp_4_cfg_l,
  output [1:0]  io_requestor_0_pmp_4_cfg_a,
  output        io_requestor_0_pmp_4_cfg_x,
  output        io_requestor_0_pmp_4_cfg_w,
  output        io_requestor_0_pmp_4_cfg_r,
  output [28:0] io_requestor_0_pmp_4_addr,
  output [30:0] io_requestor_0_pmp_4_mask,
  output        io_requestor_0_pmp_5_cfg_l,
  output [1:0]  io_requestor_0_pmp_5_cfg_a,
  output        io_requestor_0_pmp_5_cfg_x,
  output        io_requestor_0_pmp_5_cfg_w,
  output        io_requestor_0_pmp_5_cfg_r,
  output [28:0] io_requestor_0_pmp_5_addr,
  output [30:0] io_requestor_0_pmp_5_mask,
  output        io_requestor_0_pmp_6_cfg_l,
  output [1:0]  io_requestor_0_pmp_6_cfg_a,
  output        io_requestor_0_pmp_6_cfg_x,
  output        io_requestor_0_pmp_6_cfg_w,
  output        io_requestor_0_pmp_6_cfg_r,
  output [28:0] io_requestor_0_pmp_6_addr,
  output [30:0] io_requestor_0_pmp_6_mask,
  output        io_requestor_0_pmp_7_cfg_l,
  output [1:0]  io_requestor_0_pmp_7_cfg_a,
  output        io_requestor_0_pmp_7_cfg_x,
  output        io_requestor_0_pmp_7_cfg_w,
  output        io_requestor_0_pmp_7_cfg_r,
  output [28:0] io_requestor_0_pmp_7_addr,
  output [30:0] io_requestor_0_pmp_7_mask,
  output        io_requestor_1_status_debug,
  output [1:0]  io_requestor_1_status_prv,
  output        io_requestor_1_pmp_0_cfg_l,
  output [1:0]  io_requestor_1_pmp_0_cfg_a,
  output        io_requestor_1_pmp_0_cfg_x,
  output        io_requestor_1_pmp_0_cfg_w,
  output        io_requestor_1_pmp_0_cfg_r,
  output [28:0] io_requestor_1_pmp_0_addr,
  output [30:0] io_requestor_1_pmp_0_mask,
  output        io_requestor_1_pmp_1_cfg_l,
  output [1:0]  io_requestor_1_pmp_1_cfg_a,
  output        io_requestor_1_pmp_1_cfg_x,
  output        io_requestor_1_pmp_1_cfg_w,
  output        io_requestor_1_pmp_1_cfg_r,
  output [28:0] io_requestor_1_pmp_1_addr,
  output [30:0] io_requestor_1_pmp_1_mask,
  output        io_requestor_1_pmp_2_cfg_l,
  output [1:0]  io_requestor_1_pmp_2_cfg_a,
  output        io_requestor_1_pmp_2_cfg_x,
  output        io_requestor_1_pmp_2_cfg_w,
  output        io_requestor_1_pmp_2_cfg_r,
  output [28:0] io_requestor_1_pmp_2_addr,
  output [30:0] io_requestor_1_pmp_2_mask,
  output        io_requestor_1_pmp_3_cfg_l,
  output [1:0]  io_requestor_1_pmp_3_cfg_a,
  output        io_requestor_1_pmp_3_cfg_x,
  output        io_requestor_1_pmp_3_cfg_w,
  output        io_requestor_1_pmp_3_cfg_r,
  output [28:0] io_requestor_1_pmp_3_addr,
  output [30:0] io_requestor_1_pmp_3_mask,
  output        io_requestor_1_pmp_4_cfg_l,
  output [1:0]  io_requestor_1_pmp_4_cfg_a,
  output        io_requestor_1_pmp_4_cfg_x,
  output        io_requestor_1_pmp_4_cfg_w,
  output        io_requestor_1_pmp_4_cfg_r,
  output [28:0] io_requestor_1_pmp_4_addr,
  output [30:0] io_requestor_1_pmp_4_mask,
  output        io_requestor_1_pmp_5_cfg_l,
  output [1:0]  io_requestor_1_pmp_5_cfg_a,
  output        io_requestor_1_pmp_5_cfg_x,
  output        io_requestor_1_pmp_5_cfg_w,
  output        io_requestor_1_pmp_5_cfg_r,
  output [28:0] io_requestor_1_pmp_5_addr,
  output [30:0] io_requestor_1_pmp_5_mask,
  output        io_requestor_1_pmp_6_cfg_l,
  output [1:0]  io_requestor_1_pmp_6_cfg_a,
  output        io_requestor_1_pmp_6_cfg_x,
  output        io_requestor_1_pmp_6_cfg_w,
  output        io_requestor_1_pmp_6_cfg_r,
  output [28:0] io_requestor_1_pmp_6_addr,
  output [30:0] io_requestor_1_pmp_6_mask,
  output        io_requestor_1_pmp_7_cfg_l,
  output [1:0]  io_requestor_1_pmp_7_cfg_a,
  output        io_requestor_1_pmp_7_cfg_x,
  output        io_requestor_1_pmp_7_cfg_w,
  output        io_requestor_1_pmp_7_cfg_r,
  output [28:0] io_requestor_1_pmp_7_addr,
  output [30:0] io_requestor_1_pmp_7_mask,
  output [31:0] io_requestor_1_customCSRs_csrs_0_value,
  input         io_dpath_status_debug,
  input  [1:0]  io_dpath_status_prv,
  input         io_dpath_pmp_0_cfg_l,
  input  [1:0]  io_dpath_pmp_0_cfg_a,
  input         io_dpath_pmp_0_cfg_x,
  input         io_dpath_pmp_0_cfg_w,
  input         io_dpath_pmp_0_cfg_r,
  input  [28:0] io_dpath_pmp_0_addr,
  input  [30:0] io_dpath_pmp_0_mask,
  input         io_dpath_pmp_1_cfg_l,
  input  [1:0]  io_dpath_pmp_1_cfg_a,
  input         io_dpath_pmp_1_cfg_x,
  input         io_dpath_pmp_1_cfg_w,
  input         io_dpath_pmp_1_cfg_r,
  input  [28:0] io_dpath_pmp_1_addr,
  input  [30:0] io_dpath_pmp_1_mask,
  input         io_dpath_pmp_2_cfg_l,
  input  [1:0]  io_dpath_pmp_2_cfg_a,
  input         io_dpath_pmp_2_cfg_x,
  input         io_dpath_pmp_2_cfg_w,
  input         io_dpath_pmp_2_cfg_r,
  input  [28:0] io_dpath_pmp_2_addr,
  input  [30:0] io_dpath_pmp_2_mask,
  input         io_dpath_pmp_3_cfg_l,
  input  [1:0]  io_dpath_pmp_3_cfg_a,
  input         io_dpath_pmp_3_cfg_x,
  input         io_dpath_pmp_3_cfg_w,
  input         io_dpath_pmp_3_cfg_r,
  input  [28:0] io_dpath_pmp_3_addr,
  input  [30:0] io_dpath_pmp_3_mask,
  input         io_dpath_pmp_4_cfg_l,
  input  [1:0]  io_dpath_pmp_4_cfg_a,
  input         io_dpath_pmp_4_cfg_x,
  input         io_dpath_pmp_4_cfg_w,
  input         io_dpath_pmp_4_cfg_r,
  input  [28:0] io_dpath_pmp_4_addr,
  input  [30:0] io_dpath_pmp_4_mask,
  input         io_dpath_pmp_5_cfg_l,
  input  [1:0]  io_dpath_pmp_5_cfg_a,
  input         io_dpath_pmp_5_cfg_x,
  input         io_dpath_pmp_5_cfg_w,
  input         io_dpath_pmp_5_cfg_r,
  input  [28:0] io_dpath_pmp_5_addr,
  input  [30:0] io_dpath_pmp_5_mask,
  input         io_dpath_pmp_6_cfg_l,
  input  [1:0]  io_dpath_pmp_6_cfg_a,
  input         io_dpath_pmp_6_cfg_x,
  input         io_dpath_pmp_6_cfg_w,
  input         io_dpath_pmp_6_cfg_r,
  input  [28:0] io_dpath_pmp_6_addr,
  input  [30:0] io_dpath_pmp_6_mask,
  input         io_dpath_pmp_7_cfg_l,
  input  [1:0]  io_dpath_pmp_7_cfg_a,
  input         io_dpath_pmp_7_cfg_x,
  input         io_dpath_pmp_7_cfg_w,
  input         io_dpath_pmp_7_cfg_r,
  input  [28:0] io_dpath_pmp_7_addr,
  input  [30:0] io_dpath_pmp_7_mask,
  output        io_dpath_perf_l2hit,
  output        io_dpath_perf_pte_miss,
  output        io_dpath_perf_pte_hit,
  input  [31:0] io_dpath_customCSRs_csrs_0_value
);
  assign io_requestor_0_status_debug = io_dpath_status_debug; // @[PTW.scala 402:28]
  assign io_requestor_0_pmp_0_cfg_l = io_dpath_pmp_0_cfg_l; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_0_cfg_a = io_dpath_pmp_0_cfg_a; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_0_cfg_x = io_dpath_pmp_0_cfg_x; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_0_cfg_w = io_dpath_pmp_0_cfg_w; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_0_cfg_r = io_dpath_pmp_0_cfg_r; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_0_addr = io_dpath_pmp_0_addr; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_0_mask = io_dpath_pmp_0_mask; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_1_cfg_l = io_dpath_pmp_1_cfg_l; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_1_cfg_a = io_dpath_pmp_1_cfg_a; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_1_cfg_x = io_dpath_pmp_1_cfg_x; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_1_cfg_w = io_dpath_pmp_1_cfg_w; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_1_cfg_r = io_dpath_pmp_1_cfg_r; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_1_addr = io_dpath_pmp_1_addr; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_1_mask = io_dpath_pmp_1_mask; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_2_cfg_l = io_dpath_pmp_2_cfg_l; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_2_cfg_a = io_dpath_pmp_2_cfg_a; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_2_cfg_x = io_dpath_pmp_2_cfg_x; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_2_cfg_w = io_dpath_pmp_2_cfg_w; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_2_cfg_r = io_dpath_pmp_2_cfg_r; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_2_addr = io_dpath_pmp_2_addr; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_2_mask = io_dpath_pmp_2_mask; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_3_cfg_l = io_dpath_pmp_3_cfg_l; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_3_cfg_a = io_dpath_pmp_3_cfg_a; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_3_cfg_x = io_dpath_pmp_3_cfg_x; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_3_cfg_w = io_dpath_pmp_3_cfg_w; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_3_cfg_r = io_dpath_pmp_3_cfg_r; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_3_addr = io_dpath_pmp_3_addr; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_3_mask = io_dpath_pmp_3_mask; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_4_cfg_l = io_dpath_pmp_4_cfg_l; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_4_cfg_a = io_dpath_pmp_4_cfg_a; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_4_cfg_x = io_dpath_pmp_4_cfg_x; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_4_cfg_w = io_dpath_pmp_4_cfg_w; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_4_cfg_r = io_dpath_pmp_4_cfg_r; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_4_addr = io_dpath_pmp_4_addr; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_4_mask = io_dpath_pmp_4_mask; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_5_cfg_l = io_dpath_pmp_5_cfg_l; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_5_cfg_a = io_dpath_pmp_5_cfg_a; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_5_cfg_x = io_dpath_pmp_5_cfg_x; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_5_cfg_w = io_dpath_pmp_5_cfg_w; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_5_cfg_r = io_dpath_pmp_5_cfg_r; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_5_addr = io_dpath_pmp_5_addr; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_5_mask = io_dpath_pmp_5_mask; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_6_cfg_l = io_dpath_pmp_6_cfg_l; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_6_cfg_a = io_dpath_pmp_6_cfg_a; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_6_cfg_x = io_dpath_pmp_6_cfg_x; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_6_cfg_w = io_dpath_pmp_6_cfg_w; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_6_cfg_r = io_dpath_pmp_6_cfg_r; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_6_addr = io_dpath_pmp_6_addr; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_6_mask = io_dpath_pmp_6_mask; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_7_cfg_l = io_dpath_pmp_7_cfg_l; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_7_cfg_a = io_dpath_pmp_7_cfg_a; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_7_cfg_x = io_dpath_pmp_7_cfg_x; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_7_cfg_w = io_dpath_pmp_7_cfg_w; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_7_cfg_r = io_dpath_pmp_7_cfg_r; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_7_addr = io_dpath_pmp_7_addr; // @[PTW.scala 405:25]
  assign io_requestor_0_pmp_7_mask = io_dpath_pmp_7_mask; // @[PTW.scala 405:25]
  assign io_requestor_1_status_debug = io_dpath_status_debug; // @[PTW.scala 402:28]
  assign io_requestor_1_status_prv = io_dpath_status_prv; // @[PTW.scala 402:28]
  assign io_requestor_1_pmp_0_cfg_l = io_dpath_pmp_0_cfg_l; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_0_cfg_a = io_dpath_pmp_0_cfg_a; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_0_cfg_x = io_dpath_pmp_0_cfg_x; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_0_cfg_w = io_dpath_pmp_0_cfg_w; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_0_cfg_r = io_dpath_pmp_0_cfg_r; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_0_addr = io_dpath_pmp_0_addr; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_0_mask = io_dpath_pmp_0_mask; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_1_cfg_l = io_dpath_pmp_1_cfg_l; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_1_cfg_a = io_dpath_pmp_1_cfg_a; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_1_cfg_x = io_dpath_pmp_1_cfg_x; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_1_cfg_w = io_dpath_pmp_1_cfg_w; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_1_cfg_r = io_dpath_pmp_1_cfg_r; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_1_addr = io_dpath_pmp_1_addr; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_1_mask = io_dpath_pmp_1_mask; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_2_cfg_l = io_dpath_pmp_2_cfg_l; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_2_cfg_a = io_dpath_pmp_2_cfg_a; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_2_cfg_x = io_dpath_pmp_2_cfg_x; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_2_cfg_w = io_dpath_pmp_2_cfg_w; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_2_cfg_r = io_dpath_pmp_2_cfg_r; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_2_addr = io_dpath_pmp_2_addr; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_2_mask = io_dpath_pmp_2_mask; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_3_cfg_l = io_dpath_pmp_3_cfg_l; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_3_cfg_a = io_dpath_pmp_3_cfg_a; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_3_cfg_x = io_dpath_pmp_3_cfg_x; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_3_cfg_w = io_dpath_pmp_3_cfg_w; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_3_cfg_r = io_dpath_pmp_3_cfg_r; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_3_addr = io_dpath_pmp_3_addr; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_3_mask = io_dpath_pmp_3_mask; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_4_cfg_l = io_dpath_pmp_4_cfg_l; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_4_cfg_a = io_dpath_pmp_4_cfg_a; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_4_cfg_x = io_dpath_pmp_4_cfg_x; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_4_cfg_w = io_dpath_pmp_4_cfg_w; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_4_cfg_r = io_dpath_pmp_4_cfg_r; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_4_addr = io_dpath_pmp_4_addr; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_4_mask = io_dpath_pmp_4_mask; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_5_cfg_l = io_dpath_pmp_5_cfg_l; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_5_cfg_a = io_dpath_pmp_5_cfg_a; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_5_cfg_x = io_dpath_pmp_5_cfg_x; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_5_cfg_w = io_dpath_pmp_5_cfg_w; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_5_cfg_r = io_dpath_pmp_5_cfg_r; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_5_addr = io_dpath_pmp_5_addr; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_5_mask = io_dpath_pmp_5_mask; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_6_cfg_l = io_dpath_pmp_6_cfg_l; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_6_cfg_a = io_dpath_pmp_6_cfg_a; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_6_cfg_x = io_dpath_pmp_6_cfg_x; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_6_cfg_w = io_dpath_pmp_6_cfg_w; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_6_cfg_r = io_dpath_pmp_6_cfg_r; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_6_addr = io_dpath_pmp_6_addr; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_6_mask = io_dpath_pmp_6_mask; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_7_cfg_l = io_dpath_pmp_7_cfg_l; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_7_cfg_a = io_dpath_pmp_7_cfg_a; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_7_cfg_x = io_dpath_pmp_7_cfg_x; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_7_cfg_w = io_dpath_pmp_7_cfg_w; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_7_cfg_r = io_dpath_pmp_7_cfg_r; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_7_addr = io_dpath_pmp_7_addr; // @[PTW.scala 405:25]
  assign io_requestor_1_pmp_7_mask = io_dpath_pmp_7_mask; // @[PTW.scala 405:25]
  assign io_requestor_1_customCSRs_csrs_0_value = io_dpath_customCSRs_csrs_0_value; // @[PTW.scala 401:32]
  assign io_dpath_perf_l2hit = 1'h0; // @[PTW.scala 264:23]
  assign io_dpath_perf_pte_miss = 1'h0; // @[PTW.scala 413:18 256:26]
  assign io_dpath_perf_pte_hit = 1'h0; // @[PTW.scala 257:57]
  always @(posedge clock) begin
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(io_dpath_perf_l2hit & (io_dpath_perf_pte_miss | io_dpath_perf_pte_hit))) & ~reset) begin
          $fatal; // @[PTW.scala 258:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~(io_dpath_perf_l2hit & (io_dpath_perf_pte_miss | io_dpath_perf_pte_hit)))) begin
          $fwrite(32'h80000002,
            "Assertion failed: PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event\n    at PTW.scala:258 assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss || io.dpath.perf.pte_hit)),\n"
            ); // @[PTW.scala 258:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
endmodule
module RVCExpander(
  input  [31:0] io_in,
  output [31:0] io_out_bits,
  output [4:0]  io_out_rd,
  output [4:0]  io_out_rs1,
  output [4:0]  io_out_rs2,
  output        io_rvc
);
  wire [6:0] io_out_s_opc = |io_in[12:5] ? 7'h13 : 7'h1f; // @[RVC.scala 53:20]
  wire [4:0] _io_out_s_T_6 = {2'h1,io_in[4:2]}; // @[Cat.scala 31:58]
  wire [29:0] _io_out_s_T_7 = {io_in[10:7],io_in[12:11],io_in[5],io_in[6],2'h0,5'h2,3'h0,2'h1,io_in[4:2],io_out_s_opc}; // @[Cat.scala 31:58]
  wire [7:0] _io_out_s_T_15 = {io_in[6:5],io_in[12:10],3'h0}; // @[Cat.scala 31:58]
  wire [4:0] _io_out_s_T_17 = {2'h1,io_in[9:7]}; // @[Cat.scala 31:58]
  wire [27:0] _io_out_s_T_20 = {io_in[6:5],io_in[12:10],3'h0,2'h1,io_in[9:7],3'h3,2'h1,io_in[4:2],7'h7}; // @[Cat.scala 31:58]
  wire [6:0] _io_out_s_T_31 = {io_in[5],io_in[12:10],io_in[6],2'h0}; // @[Cat.scala 31:58]
  wire [26:0] _io_out_s_T_36 = {io_in[5],io_in[12:10],io_in[6],2'h0,2'h1,io_in[9:7],3'h2,2'h1,io_in[4:2],7'h3}; // @[Cat.scala 31:58]
  wire [26:0] _io_out_s_T_52 = {io_in[5],io_in[12:10],io_in[6],2'h0,2'h1,io_in[9:7],3'h2,2'h1,io_in[4:2],7'h7}; // @[Cat.scala 31:58]
  wire [26:0] _io_out_s_T_74 = {_io_out_s_T_31[6:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h2,_io_out_s_T_31[4:0],7'h3f}; // @[Cat.scala 31:58]
  wire [27:0] _io_out_s_T_94 = {_io_out_s_T_15[7:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h3,_io_out_s_T_15[4:0],7'h27}; // @[Cat.scala 31:58]
  wire [26:0] _io_out_s_T_116 = {_io_out_s_T_31[6:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h2,_io_out_s_T_31[4:0],7'h23}; // @[Cat.scala 31:58]
  wire [26:0] _io_out_s_T_138 = {_io_out_s_T_31[6:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h2,_io_out_s_T_31[4:0],7'h27}; // @[Cat.scala 31:58]
  wire [6:0] _io_out_s_T_148 = io_in[12] ? 7'h7f : 7'h0; // @[Bitwise.scala 74:12]
  wire [11:0] _io_out_s_T_150 = {_io_out_s_T_148,io_in[6:2]}; // @[Cat.scala 31:58]
  wire [31:0] io_out_s_8_bits = {_io_out_s_T_148,io_in[6:2],io_in[11:7],3'h0,io_in[11:7],7'h13}; // @[Cat.scala 31:58]
  wire [9:0] _io_out_s_T_161 = io_in[12] ? 10'h3ff : 10'h0; // @[Bitwise.scala 74:12]
  wire [20:0] _io_out_s_T_169 = {_io_out_s_T_161,io_in[8],io_in[10:9],io_in[6],io_in[7],io_in[2],io_in[11],io_in[5:3],1'h0
    }; // @[Cat.scala 31:58]
  wire [31:0] io_out_s_9_bits = {_io_out_s_T_169[20],_io_out_s_T_169[10:1],_io_out_s_T_169[11],_io_out_s_T_169[19:12],5'h1
    ,7'h6f}; // @[Cat.scala 31:58]
  wire [31:0] io_out_s_10_bits = {_io_out_s_T_148,io_in[6:2],5'h0,3'h0,io_in[11:7],7'h13}; // @[Cat.scala 31:58]
  wire  _io_out_s_opc_T_7 = |_io_out_s_T_150; // @[RVC.scala 90:29]
  wire [6:0] io_out_s_opc_1 = |_io_out_s_T_150 ? 7'h37 : 7'h3f; // @[RVC.scala 90:20]
  wire [14:0] _io_out_s_me_T_2 = io_in[12] ? 15'h7fff : 15'h0; // @[Bitwise.scala 74:12]
  wire [31:0] _io_out_s_me_T_4 = {_io_out_s_me_T_2,io_in[6:2],12'h0}; // @[Cat.scala 31:58]
  wire [31:0] io_out_s_me_bits = {_io_out_s_me_T_4[31:12],io_in[11:7],io_out_s_opc_1}; // @[Cat.scala 31:58]
  wire [6:0] io_out_s_opc_2 = _io_out_s_opc_T_7 ? 7'h13 : 7'h1f; // @[RVC.scala 86:20]
  wire [2:0] _io_out_s_T_230 = io_in[12] ? 3'h7 : 3'h0; // @[Bitwise.scala 74:12]
  wire [31:0] io_out_s_res_bits = {_io_out_s_T_230,io_in[4:3],io_in[5],io_in[2],io_in[6],4'h0,io_in[11:7],3'h0,io_in[11:
    7],io_out_s_opc_2}; // @[Cat.scala 31:58]
  wire [31:0] io_out_s_11_bits = io_in[11:7] == 5'h0 | io_in[11:7] == 5'h2 ? io_out_s_res_bits : io_out_s_me_bits; // @[RVC.scala 92:10]
  wire [4:0] io_out_s_11_rd = io_in[11:7] == 5'h0 | io_in[11:7] == 5'h2 ? io_in[11:7] : io_in[11:7]; // @[RVC.scala 92:10]
  wire [4:0] io_out_s_11_rs2 = io_in[11:7] == 5'h0 | io_in[11:7] == 5'h2 ? _io_out_s_T_6 : _io_out_s_T_6; // @[RVC.scala 92:10]
  wire [25:0] _io_out_s_T_251 = {io_in[12],io_in[6:2],2'h1,io_in[9:7],3'h5,2'h1,io_in[9:7],7'h13}; // @[Cat.scala 31:58]
  wire [30:0] _GEN_0 = {{5'd0}, _io_out_s_T_251}; // @[RVC.scala 99:23]
  wire [30:0] _io_out_s_T_260 = _GEN_0 | 31'h40000000; // @[RVC.scala 99:23]
  wire [31:0] _io_out_s_T_270 = {_io_out_s_T_148,io_in[6:2],2'h1,io_in[9:7],3'h7,2'h1,io_in[9:7],7'h13}; // @[Cat.scala 31:58]
  wire [2:0] _io_out_s_funct_T_2 = {io_in[12],io_in[6:5]}; // @[Cat.scala 31:58]
  wire [2:0] _io_out_s_funct_T_4 = _io_out_s_funct_T_2 == 3'h1 ? 3'h4 : 3'h0; // @[package.scala 32:76]
  wire [2:0] _io_out_s_funct_T_6 = _io_out_s_funct_T_2 == 3'h2 ? 3'h6 : _io_out_s_funct_T_4; // @[package.scala 32:76]
  wire [2:0] _io_out_s_funct_T_8 = _io_out_s_funct_T_2 == 3'h3 ? 3'h7 : _io_out_s_funct_T_6; // @[package.scala 32:76]
  wire [2:0] _io_out_s_funct_T_10 = _io_out_s_funct_T_2 == 3'h4 ? 3'h0 : _io_out_s_funct_T_8; // @[package.scala 32:76]
  wire [2:0] _io_out_s_funct_T_12 = _io_out_s_funct_T_2 == 3'h5 ? 3'h0 : _io_out_s_funct_T_10; // @[package.scala 32:76]
  wire [2:0] _io_out_s_funct_T_14 = _io_out_s_funct_T_2 == 3'h6 ? 3'h2 : _io_out_s_funct_T_12; // @[package.scala 32:76]
  wire [2:0] io_out_s_funct = _io_out_s_funct_T_2 == 3'h7 ? 3'h3 : _io_out_s_funct_T_14; // @[package.scala 32:76]
  wire [30:0] io_out_s_sub = io_in[6:5] == 2'h0 ? 31'h40000000 : 31'h0; // @[RVC.scala 103:22]
  wire [6:0] io_out_s_opc_3 = io_in[12] ? 7'h3b : 7'h33; // @[RVC.scala 104:22]
  wire [24:0] _io_out_s_T_277 = {2'h1,io_in[4:2],2'h1,io_in[9:7],io_out_s_funct,2'h1,io_in[9:7],io_out_s_opc_3}; // @[Cat.scala 31:58]
  wire [30:0] _GEN_1 = {{6'd0}, _io_out_s_T_277}; // @[RVC.scala 105:43]
  wire [30:0] _io_out_s_T_278 = _GEN_1 | io_out_s_sub; // @[RVC.scala 105:43]
  wire [30:0] _io_out_s_T_281 = io_in[11:10] == 2'h1 ? _io_out_s_T_260 : {{5'd0}, _io_out_s_T_251}; // @[package.scala 32:76]
  wire [31:0] _io_out_s_T_283 = io_in[11:10] == 2'h2 ? _io_out_s_T_270 : {{1'd0}, _io_out_s_T_281}; // @[package.scala 32:76]
  wire [31:0] io_out_s_12_bits = io_in[11:10] == 2'h3 ? {{1'd0}, _io_out_s_T_278} : _io_out_s_T_283; // @[package.scala 32:76]
  wire [31:0] io_out_s_13_bits = {_io_out_s_T_169[20],_io_out_s_T_169[10:1],_io_out_s_T_169[11],_io_out_s_T_169[19:12],5'h0
    ,7'h6f}; // @[Cat.scala 31:58]
  wire [4:0] _io_out_s_T_349 = io_in[12] ? 5'h1f : 5'h0; // @[Bitwise.scala 74:12]
  wire [12:0] _io_out_s_T_354 = {_io_out_s_T_349,io_in[6:5],io_in[2],io_in[11:10],io_in[4:3],1'h0}; // @[Cat.scala 31:58]
  wire [31:0] io_out_s_14_bits = {_io_out_s_T_354[12],_io_out_s_T_354[10:5],5'h0,2'h1,io_in[9:7],3'h0,_io_out_s_T_354[4:
    1],_io_out_s_T_354[11],7'h63}; // @[Cat.scala 31:58]
  wire [31:0] io_out_s_15_bits = {_io_out_s_T_354[12],_io_out_s_T_354[10:5],5'h0,2'h1,io_in[9:7],3'h1,_io_out_s_T_354[4:
    1],_io_out_s_T_354[11],7'h63}; // @[Cat.scala 31:58]
  wire  _io_out_s_load_opc_T_1 = |io_in[11:7]; // @[RVC.scala 113:27]
  wire [6:0] io_out_s_load_opc = |io_in[11:7] ? 7'h3 : 7'h1f; // @[RVC.scala 113:23]
  wire [25:0] _io_out_s_T_438 = {io_in[12],io_in[6:2],io_in[11:7],3'h1,io_in[11:7],7'h13}; // @[Cat.scala 31:58]
  wire [28:0] _io_out_s_T_448 = {io_in[4:2],io_in[12],io_in[6:5],3'h0,5'h2,3'h3,io_in[11:7],7'h7}; // @[Cat.scala 31:58]
  wire [27:0] _io_out_s_T_457 = {io_in[3:2],io_in[12],io_in[6:4],2'h0,5'h2,3'h2,io_in[11:7],io_out_s_load_opc}; // @[Cat.scala 31:58]
  wire [27:0] _io_out_s_T_466 = {io_in[3:2],io_in[12],io_in[6:4],2'h0,5'h2,3'h2,io_in[11:7],7'h7}; // @[Cat.scala 31:58]
  wire [24:0] _io_out_s_mv_T_2 = {io_in[6:2],5'h0,3'h0,io_in[11:7],7'h33}; // @[Cat.scala 31:58]
  wire [24:0] _io_out_s_add_T_3 = {io_in[6:2],io_in[11:7],3'h0,io_in[11:7],7'h33}; // @[Cat.scala 31:58]
  wire [24:0] io_out_s_jr = {io_in[6:2],io_in[11:7],3'h0,12'h67}; // @[Cat.scala 31:58]
  wire [24:0] io_out_s_reserved = {io_out_s_jr[24:7],7'h1f}; // @[Cat.scala 31:58]
  wire [24:0] _io_out_s_jr_reserved_T_2 = _io_out_s_load_opc_T_1 ? io_out_s_jr : io_out_s_reserved; // @[RVC.scala 134:33]
  wire  _io_out_s_jr_mv_T_1 = |io_in[6:2]; // @[RVC.scala 135:27]
  wire [31:0] io_out_s_mv_bits = {{7'd0}, _io_out_s_mv_T_2}; // @[RVC.scala 21:19 22:14]
  wire [31:0] io_out_s_jr_reserved_bits = {{7'd0}, _io_out_s_jr_reserved_T_2}; // @[RVC.scala 21:19 22:14]
  wire [31:0] io_out_s_jr_mv_bits = |io_in[6:2] ? io_out_s_mv_bits : io_out_s_jr_reserved_bits; // @[RVC.scala 135:22]
  wire [4:0] io_out_s_jr_mv_rd = |io_in[6:2] ? io_in[11:7] : 5'h0; // @[RVC.scala 135:22]
  wire [4:0] io_out_s_jr_mv_rs1 = |io_in[6:2] ? 5'h0 : io_in[11:7]; // @[RVC.scala 135:22]
  wire [4:0] io_out_s_jr_mv_rs2 = |io_in[6:2] ? io_in[6:2] : io_in[6:2]; // @[RVC.scala 135:22]
  wire [24:0] io_out_s_jalr = {io_in[6:2],io_in[11:7],3'h0,12'he7}; // @[Cat.scala 31:58]
  wire [24:0] _io_out_s_ebreak_T_1 = {io_out_s_jr[24:7],7'h73}; // @[Cat.scala 31:58]
  wire [24:0] io_out_s_ebreak = _io_out_s_ebreak_T_1 | 25'h100000; // @[RVC.scala 137:46]
  wire [24:0] _io_out_s_jalr_ebreak_T_2 = _io_out_s_load_opc_T_1 ? io_out_s_jalr : io_out_s_ebreak; // @[RVC.scala 138:33]
  wire [31:0] io_out_s_add_bits = {{7'd0}, _io_out_s_add_T_3}; // @[RVC.scala 21:19 22:14]
  wire [31:0] io_out_s_jalr_ebreak_bits = {{7'd0}, _io_out_s_jalr_ebreak_T_2}; // @[RVC.scala 21:19 22:14]
  wire [31:0] io_out_s_jalr_add_bits = _io_out_s_jr_mv_T_1 ? io_out_s_add_bits : io_out_s_jalr_ebreak_bits; // @[RVC.scala 139:25]
  wire [4:0] io_out_s_jalr_add_rd = _io_out_s_jr_mv_T_1 ? io_in[11:7] : 5'h1; // @[RVC.scala 139:25]
  wire [4:0] io_out_s_jalr_add_rs1 = _io_out_s_jr_mv_T_1 ? io_in[11:7] : io_in[11:7]; // @[RVC.scala 139:25]
  wire [31:0] io_out_s_20_bits = io_in[12] ? io_out_s_jalr_add_bits : io_out_s_jr_mv_bits; // @[RVC.scala 140:10]
  wire [4:0] io_out_s_20_rd = io_in[12] ? io_out_s_jalr_add_rd : io_out_s_jr_mv_rd; // @[RVC.scala 140:10]
  wire [4:0] io_out_s_20_rs1 = io_in[12] ? io_out_s_jalr_add_rs1 : io_out_s_jr_mv_rs1; // @[RVC.scala 140:10]
  wire [4:0] io_out_s_20_rs2 = io_in[12] ? io_out_s_jr_mv_rs2 : io_out_s_jr_mv_rs2; // @[RVC.scala 140:10]
  wire [8:0] _io_out_s_T_473 = {io_in[9:7],io_in[12:10],3'h0}; // @[Cat.scala 31:58]
  wire [28:0] _io_out_s_T_480 = {_io_out_s_T_473[8:5],io_in[6:2],5'h2,3'h3,_io_out_s_T_473[4:0],7'h27}; // @[Cat.scala 31:58]
  wire [7:0] _io_out_s_T_486 = {io_in[8:7],io_in[12:9],2'h0}; // @[Cat.scala 31:58]
  wire [27:0] _io_out_s_T_493 = {_io_out_s_T_486[7:5],io_in[6:2],5'h2,3'h2,_io_out_s_T_486[4:0],7'h23}; // @[Cat.scala 31:58]
  wire [27:0] _io_out_s_T_506 = {_io_out_s_T_486[7:5],io_in[6:2],5'h2,3'h2,_io_out_s_T_486[4:0],7'h27}; // @[Cat.scala 31:58]
  wire [4:0] io_out_s_24_rs1 = io_in[19:15]; // @[RVC.scala 20:57]
  wire [4:0] io_out_s_24_rs2 = io_in[24:20]; // @[RVC.scala 20:79]
  wire [4:0] _io_out_T_2 = {io_in[1:0],io_in[15:13]}; // @[Cat.scala 31:58]
  wire [31:0] io_out_s_1_bits = {{4'd0}, _io_out_s_T_20}; // @[RVC.scala 21:19 22:14]
  wire [31:0] io_out_s_0_bits = {{2'd0}, _io_out_s_T_7}; // @[RVC.scala 21:19 22:14]
  wire [31:0] _io_out_T_4_bits = _io_out_T_2 == 5'h1 ? io_out_s_1_bits : io_out_s_0_bits; // @[package.scala 32:76]
  wire [4:0] _io_out_T_4_rd = _io_out_T_2 == 5'h1 ? _io_out_s_T_6 : _io_out_s_T_6; // @[package.scala 32:76]
  wire [4:0] _io_out_T_4_rs1 = _io_out_T_2 == 5'h1 ? _io_out_s_T_17 : 5'h2; // @[package.scala 32:76]
  wire [31:0] io_out_s_2_bits = {{5'd0}, _io_out_s_T_36}; // @[RVC.scala 21:19 22:14]
  wire [31:0] _io_out_T_6_bits = _io_out_T_2 == 5'h2 ? io_out_s_2_bits : _io_out_T_4_bits; // @[package.scala 32:76]
  wire [4:0] _io_out_T_6_rd = _io_out_T_2 == 5'h2 ? _io_out_s_T_6 : _io_out_T_4_rd; // @[package.scala 32:76]
  wire [4:0] _io_out_T_6_rs1 = _io_out_T_2 == 5'h2 ? _io_out_s_T_17 : _io_out_T_4_rs1; // @[package.scala 32:76]
  wire [31:0] io_out_s_3_bits = {{5'd0}, _io_out_s_T_52}; // @[RVC.scala 21:19 22:14]
  wire [31:0] _io_out_T_8_bits = _io_out_T_2 == 5'h3 ? io_out_s_3_bits : _io_out_T_6_bits; // @[package.scala 32:76]
  wire [4:0] _io_out_T_8_rd = _io_out_T_2 == 5'h3 ? _io_out_s_T_6 : _io_out_T_6_rd; // @[package.scala 32:76]
  wire [4:0] _io_out_T_8_rs1 = _io_out_T_2 == 5'h3 ? _io_out_s_T_17 : _io_out_T_6_rs1; // @[package.scala 32:76]
  wire [31:0] io_out_s_4_bits = {{5'd0}, _io_out_s_T_74}; // @[RVC.scala 21:19 22:14]
  wire [31:0] _io_out_T_10_bits = _io_out_T_2 == 5'h4 ? io_out_s_4_bits : _io_out_T_8_bits; // @[package.scala 32:76]
  wire [4:0] _io_out_T_10_rd = _io_out_T_2 == 5'h4 ? _io_out_s_T_6 : _io_out_T_8_rd; // @[package.scala 32:76]
  wire [4:0] _io_out_T_10_rs1 = _io_out_T_2 == 5'h4 ? _io_out_s_T_17 : _io_out_T_8_rs1; // @[package.scala 32:76]
  wire [31:0] io_out_s_5_bits = {{4'd0}, _io_out_s_T_94}; // @[RVC.scala 21:19 22:14]
  wire [31:0] _io_out_T_12_bits = _io_out_T_2 == 5'h5 ? io_out_s_5_bits : _io_out_T_10_bits; // @[package.scala 32:76]
  wire [4:0] _io_out_T_12_rd = _io_out_T_2 == 5'h5 ? _io_out_s_T_6 : _io_out_T_10_rd; // @[package.scala 32:76]
  wire [4:0] _io_out_T_12_rs1 = _io_out_T_2 == 5'h5 ? _io_out_s_T_17 : _io_out_T_10_rs1; // @[package.scala 32:76]
  wire [31:0] io_out_s_6_bits = {{5'd0}, _io_out_s_T_116}; // @[RVC.scala 21:19 22:14]
  wire [31:0] _io_out_T_14_bits = _io_out_T_2 == 5'h6 ? io_out_s_6_bits : _io_out_T_12_bits; // @[package.scala 32:76]
  wire [4:0] _io_out_T_14_rd = _io_out_T_2 == 5'h6 ? _io_out_s_T_6 : _io_out_T_12_rd; // @[package.scala 32:76]
  wire [4:0] _io_out_T_14_rs1 = _io_out_T_2 == 5'h6 ? _io_out_s_T_17 : _io_out_T_12_rs1; // @[package.scala 32:76]
  wire [31:0] io_out_s_7_bits = {{5'd0}, _io_out_s_T_138}; // @[RVC.scala 21:19 22:14]
  wire [31:0] _io_out_T_16_bits = _io_out_T_2 == 5'h7 ? io_out_s_7_bits : _io_out_T_14_bits; // @[package.scala 32:76]
  wire [4:0] _io_out_T_16_rd = _io_out_T_2 == 5'h7 ? _io_out_s_T_6 : _io_out_T_14_rd; // @[package.scala 32:76]
  wire [4:0] _io_out_T_16_rs1 = _io_out_T_2 == 5'h7 ? _io_out_s_T_17 : _io_out_T_14_rs1; // @[package.scala 32:76]
  wire [31:0] _io_out_T_18_bits = _io_out_T_2 == 5'h8 ? io_out_s_8_bits : _io_out_T_16_bits; // @[package.scala 32:76]
  wire [4:0] _io_out_T_18_rd = _io_out_T_2 == 5'h8 ? io_in[11:7] : _io_out_T_16_rd; // @[package.scala 32:76]
  wire [4:0] _io_out_T_18_rs1 = _io_out_T_2 == 5'h8 ? io_in[11:7] : _io_out_T_16_rs1; // @[package.scala 32:76]
  wire [4:0] _io_out_T_18_rs2 = _io_out_T_2 == 5'h8 ? _io_out_s_T_6 : _io_out_T_16_rd; // @[package.scala 32:76]
  wire [31:0] _io_out_T_20_bits = _io_out_T_2 == 5'h9 ? io_out_s_9_bits : _io_out_T_18_bits; // @[package.scala 32:76]
  wire [4:0] _io_out_T_20_rd = _io_out_T_2 == 5'h9 ? 5'h1 : _io_out_T_18_rd; // @[package.scala 32:76]
  wire [4:0] _io_out_T_20_rs1 = _io_out_T_2 == 5'h9 ? io_in[11:7] : _io_out_T_18_rs1; // @[package.scala 32:76]
  wire [4:0] _io_out_T_20_rs2 = _io_out_T_2 == 5'h9 ? _io_out_s_T_6 : _io_out_T_18_rs2; // @[package.scala 32:76]
  wire [31:0] _io_out_T_22_bits = _io_out_T_2 == 5'ha ? io_out_s_10_bits : _io_out_T_20_bits; // @[package.scala 32:76]
  wire [4:0] _io_out_T_22_rd = _io_out_T_2 == 5'ha ? io_in[11:7] : _io_out_T_20_rd; // @[package.scala 32:76]
  wire [4:0] _io_out_T_22_rs1 = _io_out_T_2 == 5'ha ? 5'h0 : _io_out_T_20_rs1; // @[package.scala 32:76]
  wire [4:0] _io_out_T_22_rs2 = _io_out_T_2 == 5'ha ? _io_out_s_T_6 : _io_out_T_20_rs2; // @[package.scala 32:76]
  wire [31:0] _io_out_T_24_bits = _io_out_T_2 == 5'hb ? io_out_s_11_bits : _io_out_T_22_bits; // @[package.scala 32:76]
  wire [4:0] _io_out_T_24_rd = _io_out_T_2 == 5'hb ? io_out_s_11_rd : _io_out_T_22_rd; // @[package.scala 32:76]
  wire [4:0] _io_out_T_24_rs1 = _io_out_T_2 == 5'hb ? io_out_s_11_rd : _io_out_T_22_rs1; // @[package.scala 32:76]
  wire [4:0] _io_out_T_24_rs2 = _io_out_T_2 == 5'hb ? io_out_s_11_rs2 : _io_out_T_22_rs2; // @[package.scala 32:76]
  wire [31:0] _io_out_T_26_bits = _io_out_T_2 == 5'hc ? io_out_s_12_bits : _io_out_T_24_bits; // @[package.scala 32:76]
  wire [4:0] _io_out_T_26_rd = _io_out_T_2 == 5'hc ? _io_out_s_T_17 : _io_out_T_24_rd; // @[package.scala 32:76]
  wire [4:0] _io_out_T_26_rs1 = _io_out_T_2 == 5'hc ? _io_out_s_T_17 : _io_out_T_24_rs1; // @[package.scala 32:76]
  wire [4:0] _io_out_T_26_rs2 = _io_out_T_2 == 5'hc ? _io_out_s_T_6 : _io_out_T_24_rs2; // @[package.scala 32:76]
  wire [31:0] _io_out_T_28_bits = _io_out_T_2 == 5'hd ? io_out_s_13_bits : _io_out_T_26_bits; // @[package.scala 32:76]
  wire [4:0] _io_out_T_28_rd = _io_out_T_2 == 5'hd ? 5'h0 : _io_out_T_26_rd; // @[package.scala 32:76]
  wire [4:0] _io_out_T_28_rs1 = _io_out_T_2 == 5'hd ? _io_out_s_T_17 : _io_out_T_26_rs1; // @[package.scala 32:76]
  wire [4:0] _io_out_T_28_rs2 = _io_out_T_2 == 5'hd ? _io_out_s_T_6 : _io_out_T_26_rs2; // @[package.scala 32:76]
  wire [31:0] _io_out_T_30_bits = _io_out_T_2 == 5'he ? io_out_s_14_bits : _io_out_T_28_bits; // @[package.scala 32:76]
  wire [4:0] _io_out_T_30_rd = _io_out_T_2 == 5'he ? _io_out_s_T_17 : _io_out_T_28_rd; // @[package.scala 32:76]
  wire [4:0] _io_out_T_30_rs1 = _io_out_T_2 == 5'he ? _io_out_s_T_17 : _io_out_T_28_rs1; // @[package.scala 32:76]
  wire [4:0] _io_out_T_30_rs2 = _io_out_T_2 == 5'he ? 5'h0 : _io_out_T_28_rs2; // @[package.scala 32:76]
  wire [31:0] _io_out_T_32_bits = _io_out_T_2 == 5'hf ? io_out_s_15_bits : _io_out_T_30_bits; // @[package.scala 32:76]
  wire [4:0] _io_out_T_32_rd = _io_out_T_2 == 5'hf ? 5'h0 : _io_out_T_30_rd; // @[package.scala 32:76]
  wire [4:0] _io_out_T_32_rs1 = _io_out_T_2 == 5'hf ? _io_out_s_T_17 : _io_out_T_30_rs1; // @[package.scala 32:76]
  wire [4:0] _io_out_T_32_rs2 = _io_out_T_2 == 5'hf ? 5'h0 : _io_out_T_30_rs2; // @[package.scala 32:76]
  wire [31:0] io_out_s_16_bits = {{6'd0}, _io_out_s_T_438}; // @[RVC.scala 21:19 22:14]
  wire [31:0] _io_out_T_34_bits = _io_out_T_2 == 5'h10 ? io_out_s_16_bits : _io_out_T_32_bits; // @[package.scala 32:76]
  wire [4:0] _io_out_T_34_rd = _io_out_T_2 == 5'h10 ? io_in[11:7] : _io_out_T_32_rd; // @[package.scala 32:76]
  wire [4:0] _io_out_T_34_rs1 = _io_out_T_2 == 5'h10 ? io_in[11:7] : _io_out_T_32_rs1; // @[package.scala 32:76]
  wire [4:0] _io_out_T_34_rs2 = _io_out_T_2 == 5'h10 ? io_in[6:2] : _io_out_T_32_rs2; // @[package.scala 32:76]
  wire [31:0] io_out_s_17_bits = {{3'd0}, _io_out_s_T_448}; // @[RVC.scala 21:19 22:14]
  wire [31:0] _io_out_T_36_bits = _io_out_T_2 == 5'h11 ? io_out_s_17_bits : _io_out_T_34_bits; // @[package.scala 32:76]
  wire [4:0] _io_out_T_36_rd = _io_out_T_2 == 5'h11 ? io_in[11:7] : _io_out_T_34_rd; // @[package.scala 32:76]
  wire [4:0] _io_out_T_36_rs1 = _io_out_T_2 == 5'h11 ? 5'h2 : _io_out_T_34_rs1; // @[package.scala 32:76]
  wire [4:0] _io_out_T_36_rs2 = _io_out_T_2 == 5'h11 ? io_in[6:2] : _io_out_T_34_rs2; // @[package.scala 32:76]
  wire [31:0] io_out_s_18_bits = {{4'd0}, _io_out_s_T_457}; // @[RVC.scala 21:19 22:14]
  wire [31:0] _io_out_T_38_bits = _io_out_T_2 == 5'h12 ? io_out_s_18_bits : _io_out_T_36_bits; // @[package.scala 32:76]
  wire [4:0] _io_out_T_38_rd = _io_out_T_2 == 5'h12 ? io_in[11:7] : _io_out_T_36_rd; // @[package.scala 32:76]
  wire [4:0] _io_out_T_38_rs1 = _io_out_T_2 == 5'h12 ? 5'h2 : _io_out_T_36_rs1; // @[package.scala 32:76]
  wire [4:0] _io_out_T_38_rs2 = _io_out_T_2 == 5'h12 ? io_in[6:2] : _io_out_T_36_rs2; // @[package.scala 32:76]
  wire [31:0] io_out_s_19_bits = {{4'd0}, _io_out_s_T_466}; // @[RVC.scala 21:19 22:14]
  wire [31:0] _io_out_T_40_bits = _io_out_T_2 == 5'h13 ? io_out_s_19_bits : _io_out_T_38_bits; // @[package.scala 32:76]
  wire [4:0] _io_out_T_40_rd = _io_out_T_2 == 5'h13 ? io_in[11:7] : _io_out_T_38_rd; // @[package.scala 32:76]
  wire [4:0] _io_out_T_40_rs1 = _io_out_T_2 == 5'h13 ? 5'h2 : _io_out_T_38_rs1; // @[package.scala 32:76]
  wire [4:0] _io_out_T_40_rs2 = _io_out_T_2 == 5'h13 ? io_in[6:2] : _io_out_T_38_rs2; // @[package.scala 32:76]
  wire [31:0] _io_out_T_42_bits = _io_out_T_2 == 5'h14 ? io_out_s_20_bits : _io_out_T_40_bits; // @[package.scala 32:76]
  wire [4:0] _io_out_T_42_rd = _io_out_T_2 == 5'h14 ? io_out_s_20_rd : _io_out_T_40_rd; // @[package.scala 32:76]
  wire [4:0] _io_out_T_42_rs1 = _io_out_T_2 == 5'h14 ? io_out_s_20_rs1 : _io_out_T_40_rs1; // @[package.scala 32:76]
  wire [4:0] _io_out_T_42_rs2 = _io_out_T_2 == 5'h14 ? io_out_s_20_rs2 : _io_out_T_40_rs2; // @[package.scala 32:76]
  wire [31:0] io_out_s_21_bits = {{3'd0}, _io_out_s_T_480}; // @[RVC.scala 21:19 22:14]
  wire [31:0] _io_out_T_44_bits = _io_out_T_2 == 5'h15 ? io_out_s_21_bits : _io_out_T_42_bits; // @[package.scala 32:76]
  wire [4:0] _io_out_T_44_rd = _io_out_T_2 == 5'h15 ? io_in[11:7] : _io_out_T_42_rd; // @[package.scala 32:76]
  wire [4:0] _io_out_T_44_rs1 = _io_out_T_2 == 5'h15 ? 5'h2 : _io_out_T_42_rs1; // @[package.scala 32:76]
  wire [4:0] _io_out_T_44_rs2 = _io_out_T_2 == 5'h15 ? io_in[6:2] : _io_out_T_42_rs2; // @[package.scala 32:76]
  wire [31:0] io_out_s_22_bits = {{4'd0}, _io_out_s_T_493}; // @[RVC.scala 21:19 22:14]
  wire [31:0] _io_out_T_46_bits = _io_out_T_2 == 5'h16 ? io_out_s_22_bits : _io_out_T_44_bits; // @[package.scala 32:76]
  wire [4:0] _io_out_T_46_rd = _io_out_T_2 == 5'h16 ? io_in[11:7] : _io_out_T_44_rd; // @[package.scala 32:76]
  wire [4:0] _io_out_T_46_rs1 = _io_out_T_2 == 5'h16 ? 5'h2 : _io_out_T_44_rs1; // @[package.scala 32:76]
  wire [4:0] _io_out_T_46_rs2 = _io_out_T_2 == 5'h16 ? io_in[6:2] : _io_out_T_44_rs2; // @[package.scala 32:76]
  wire [31:0] io_out_s_23_bits = {{4'd0}, _io_out_s_T_506}; // @[RVC.scala 21:19 22:14]
  wire [31:0] _io_out_T_48_bits = _io_out_T_2 == 5'h17 ? io_out_s_23_bits : _io_out_T_46_bits; // @[package.scala 32:76]
  wire [4:0] _io_out_T_48_rd = _io_out_T_2 == 5'h17 ? io_in[11:7] : _io_out_T_46_rd; // @[package.scala 32:76]
  wire [4:0] _io_out_T_48_rs1 = _io_out_T_2 == 5'h17 ? 5'h2 : _io_out_T_46_rs1; // @[package.scala 32:76]
  wire [4:0] _io_out_T_48_rs2 = _io_out_T_2 == 5'h17 ? io_in[6:2] : _io_out_T_46_rs2; // @[package.scala 32:76]
  wire [31:0] _io_out_T_50_bits = _io_out_T_2 == 5'h18 ? io_in : _io_out_T_48_bits; // @[package.scala 32:76]
  wire [4:0] _io_out_T_50_rd = _io_out_T_2 == 5'h18 ? io_in[11:7] : _io_out_T_48_rd; // @[package.scala 32:76]
  wire [4:0] _io_out_T_50_rs1 = _io_out_T_2 == 5'h18 ? io_out_s_24_rs1 : _io_out_T_48_rs1; // @[package.scala 32:76]
  wire [4:0] _io_out_T_50_rs2 = _io_out_T_2 == 5'h18 ? io_out_s_24_rs2 : _io_out_T_48_rs2; // @[package.scala 32:76]
  wire [31:0] _io_out_T_52_bits = _io_out_T_2 == 5'h19 ? io_in : _io_out_T_50_bits; // @[package.scala 32:76]
  wire [4:0] _io_out_T_52_rd = _io_out_T_2 == 5'h19 ? io_in[11:7] : _io_out_T_50_rd; // @[package.scala 32:76]
  wire [4:0] _io_out_T_52_rs1 = _io_out_T_2 == 5'h19 ? io_out_s_24_rs1 : _io_out_T_50_rs1; // @[package.scala 32:76]
  wire [4:0] _io_out_T_52_rs2 = _io_out_T_2 == 5'h19 ? io_out_s_24_rs2 : _io_out_T_50_rs2; // @[package.scala 32:76]
  wire [31:0] _io_out_T_54_bits = _io_out_T_2 == 5'h1a ? io_in : _io_out_T_52_bits; // @[package.scala 32:76]
  wire [4:0] _io_out_T_54_rd = _io_out_T_2 == 5'h1a ? io_in[11:7] : _io_out_T_52_rd; // @[package.scala 32:76]
  wire [4:0] _io_out_T_54_rs1 = _io_out_T_2 == 5'h1a ? io_out_s_24_rs1 : _io_out_T_52_rs1; // @[package.scala 32:76]
  wire [4:0] _io_out_T_54_rs2 = _io_out_T_2 == 5'h1a ? io_out_s_24_rs2 : _io_out_T_52_rs2; // @[package.scala 32:76]
  wire [31:0] _io_out_T_56_bits = _io_out_T_2 == 5'h1b ? io_in : _io_out_T_54_bits; // @[package.scala 32:76]
  wire [4:0] _io_out_T_56_rd = _io_out_T_2 == 5'h1b ? io_in[11:7] : _io_out_T_54_rd; // @[package.scala 32:76]
  wire [4:0] _io_out_T_56_rs1 = _io_out_T_2 == 5'h1b ? io_out_s_24_rs1 : _io_out_T_54_rs1; // @[package.scala 32:76]
  wire [4:0] _io_out_T_56_rs2 = _io_out_T_2 == 5'h1b ? io_out_s_24_rs2 : _io_out_T_54_rs2; // @[package.scala 32:76]
  wire [31:0] _io_out_T_58_bits = _io_out_T_2 == 5'h1c ? io_in : _io_out_T_56_bits; // @[package.scala 32:76]
  wire [4:0] _io_out_T_58_rd = _io_out_T_2 == 5'h1c ? io_in[11:7] : _io_out_T_56_rd; // @[package.scala 32:76]
  wire [4:0] _io_out_T_58_rs1 = _io_out_T_2 == 5'h1c ? io_out_s_24_rs1 : _io_out_T_56_rs1; // @[package.scala 32:76]
  wire [4:0] _io_out_T_58_rs2 = _io_out_T_2 == 5'h1c ? io_out_s_24_rs2 : _io_out_T_56_rs2; // @[package.scala 32:76]
  wire [31:0] _io_out_T_60_bits = _io_out_T_2 == 5'h1d ? io_in : _io_out_T_58_bits; // @[package.scala 32:76]
  wire [4:0] _io_out_T_60_rd = _io_out_T_2 == 5'h1d ? io_in[11:7] : _io_out_T_58_rd; // @[package.scala 32:76]
  wire [4:0] _io_out_T_60_rs1 = _io_out_T_2 == 5'h1d ? io_out_s_24_rs1 : _io_out_T_58_rs1; // @[package.scala 32:76]
  wire [4:0] _io_out_T_60_rs2 = _io_out_T_2 == 5'h1d ? io_out_s_24_rs2 : _io_out_T_58_rs2; // @[package.scala 32:76]
  wire [31:0] _io_out_T_62_bits = _io_out_T_2 == 5'h1e ? io_in : _io_out_T_60_bits; // @[package.scala 32:76]
  wire [4:0] _io_out_T_62_rd = _io_out_T_2 == 5'h1e ? io_in[11:7] : _io_out_T_60_rd; // @[package.scala 32:76]
  wire [4:0] _io_out_T_62_rs1 = _io_out_T_2 == 5'h1e ? io_out_s_24_rs1 : _io_out_T_60_rs1; // @[package.scala 32:76]
  wire [4:0] _io_out_T_62_rs2 = _io_out_T_2 == 5'h1e ? io_out_s_24_rs2 : _io_out_T_60_rs2; // @[package.scala 32:76]
  assign io_out_bits = _io_out_T_2 == 5'h1f ? io_in : _io_out_T_62_bits; // @[package.scala 32:76]
  assign io_out_rd = _io_out_T_2 == 5'h1f ? io_in[11:7] : _io_out_T_62_rd; // @[package.scala 32:76]
  assign io_out_rs1 = _io_out_T_2 == 5'h1f ? io_out_s_24_rs1 : _io_out_T_62_rs1; // @[package.scala 32:76]
  assign io_out_rs2 = _io_out_T_2 == 5'h1f ? io_out_s_24_rs2 : _io_out_T_62_rs2; // @[package.scala 32:76]
  assign io_rvc = io_in[1:0] != 2'h3; // @[RVC.scala 163:26]
endmodule
module IBuf(
  input         clock,
  input         reset,
  output        io_imem_ready,
  input         io_imem_valid,
  input         io_imem_bits_btb_taken,
  input         io_imem_bits_btb_bridx,
  input  [4:0]  io_imem_bits_btb_entry,
  input  [7:0]  io_imem_bits_btb_bht_history,
  input  [31:0] io_imem_bits_pc,
  input  [31:0] io_imem_bits_data,
  input         io_imem_bits_xcpt_ae_inst,
  input         io_imem_bits_replay,
  input         io_kill,
  output [31:0] io_pc,
  output [4:0]  io_btb_resp_entry,
  output [7:0]  io_btb_resp_bht_history,
  input         io_inst_0_ready,
  output        io_inst_0_valid,
  output        io_inst_0_bits_xcpt0_ae_inst,
  output        io_inst_0_bits_xcpt1_pf_inst,
  output        io_inst_0_bits_xcpt1_gf_inst,
  output        io_inst_0_bits_xcpt1_ae_inst,
  output        io_inst_0_bits_replay,
  output        io_inst_0_bits_rvc,
  output [31:0] io_inst_0_bits_inst_bits,
  output [4:0]  io_inst_0_bits_inst_rd,
  output [4:0]  io_inst_0_bits_inst_rs1,
  output [4:0]  io_inst_0_bits_inst_rs2,
  output [31:0] io_inst_0_bits_raw
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] exp_io_in; // @[IBuf.scala 86:21]
  wire [31:0] exp_io_out_bits; // @[IBuf.scala 86:21]
  wire [4:0] exp_io_out_rd; // @[IBuf.scala 86:21]
  wire [4:0] exp_io_out_rs1; // @[IBuf.scala 86:21]
  wire [4:0] exp_io_out_rs2; // @[IBuf.scala 86:21]
  wire  exp_io_rvc; // @[IBuf.scala 86:21]
  reg  nBufValid; // @[IBuf.scala 34:47]
  reg [31:0] buf__pc; // @[IBuf.scala 35:16]
  reg [31:0] buf__data; // @[IBuf.scala 35:16]
  reg  buf__xcpt_ae_inst; // @[IBuf.scala 35:16]
  reg  buf__replay; // @[IBuf.scala 35:16]
  reg [4:0] ibufBTBResp_entry; // @[IBuf.scala 36:24]
  reg [7:0] ibufBTBResp_bht_history; // @[IBuf.scala 36:24]
  wire  pcWordBits = io_imem_bits_pc[1]; // @[package.scala 154:13]
  wire [1:0] _nIC_T = io_imem_bits_btb_bridx + 1'h1; // @[IBuf.scala 41:64]
  wire [1:0] _nIC_T_1 = io_imem_bits_btb_taken ? _nIC_T : 2'h2; // @[IBuf.scala 41:16]
  wire [1:0] _GEN_58 = {{1'd0}, pcWordBits}; // @[IBuf.scala 41:88]
  wire [1:0] nIC = _nIC_T_1 - _GEN_58; // @[IBuf.scala 41:88]
  wire [1:0] _nValid_T = io_imem_valid ? nIC : 2'h0; // @[IBuf.scala 43:19]
  wire [1:0] _GEN_59 = {{1'd0}, nBufValid}; // @[IBuf.scala 43:49]
  wire [1:0] nValid = _nValid_T + _GEN_59; // @[IBuf.scala 43:49]
  wire [3:0] _valid_T = 4'h1 << nValid; // @[OneHot.scala 57:35]
  wire [3:0] _valid_T_2 = _valid_T - 4'h1; // @[IBuf.scala 74:33]
  wire [1:0] valid = _valid_T_2[1:0]; // @[IBuf.scala 74:37]
  wire [1:0] _full_insn_T_2 = {{1'd0}, valid[1]}; // @[IBuf.scala 93:42]
  wire [1:0] _bufMask_T = 2'h1 << nBufValid; // @[OneHot.scala 57:35]
  wire [1:0] bufMask = _bufMask_T - 2'h1; // @[IBuf.scala 75:37]
  wire [1:0] buf_replay = buf__replay ? bufMask : 2'h0; // @[IBuf.scala 77:23]
  wire  full_insn = exp_io_rvc | _full_insn_T_2[0] | buf_replay[0]; // @[IBuf.scala 93:48]
  wire [1:0] _nReady_T_4 = exp_io_rvc ? 2'h1 : 2'h2; // @[IBuf.scala 102:71]
  wire [1:0] nReady = full_insn ? _nReady_T_4 : 2'h0; // @[IBuf.scala 102:{56,65}]
  wire [1:0] nICReady = nReady - _GEN_59; // @[IBuf.scala 42:25]
  wire  _io_imem_ready_T = nReady >= _GEN_59; // @[IBuf.scala 44:47]
  wire [1:0] _io_imem_ready_T_4 = nIC - nICReady; // @[IBuf.scala 44:92]
  wire  _io_imem_ready_T_5 = 2'h1 >= _io_imem_ready_T_4; // @[IBuf.scala 44:85]
  wire  _nBufValid_T_2 = _io_imem_ready_T | ~nBufValid; // @[package.scala 209:38]
  wire [1:0] _nBufValid_T_4 = _GEN_59 - nReady; // @[IBuf.scala 48:65]
  wire [1:0] _nBufValid_T_5 = _nBufValid_T_2 ? 2'h0 : _nBufValid_T_4; // @[IBuf.scala 48:23]
  wire [1:0] shamt = _GEN_58 + nICReady; // @[IBuf.scala 55:32]
  wire [63:0] buf_data_data = {io_imem_bits_data[31:16],io_imem_bits_data[31:16],io_imem_bits_data}; // @[Cat.scala 31:58]
  wire [5:0] _buf_data_T = {shamt, 4'h0}; // @[IBuf.scala 128:19]
  wire [63:0] _buf_data_T_1 = buf_data_data >> _buf_data_T; // @[IBuf.scala 128:10]
  wire [31:0] _buf_pc_T_1 = io_imem_bits_pc & 32'hfffffffc; // @[IBuf.scala 59:35]
  wire [2:0] _buf_pc_T_2 = {nICReady, 1'h0}; // @[IBuf.scala 59:80]
  wire [31:0] _GEN_67 = {{29'd0}, _buf_pc_T_2}; // @[IBuf.scala 59:68]
  wire [31:0] _buf_pc_T_4 = io_imem_bits_pc + _GEN_67; // @[IBuf.scala 59:68]
  wire [31:0] _buf_pc_T_5 = _buf_pc_T_4 & 32'h3; // @[IBuf.scala 59:109]
  wire [31:0] _buf_pc_T_6 = _buf_pc_T_1 | _buf_pc_T_5; // @[IBuf.scala 59:49]
  wire [1:0] _GEN_0 = io_imem_valid & _io_imem_ready_T & nICReady < nIC & _io_imem_ready_T_5 ? _io_imem_ready_T_4 :
    _nBufValid_T_5; // @[IBuf.scala 48:17 54:92 56:19]
  wire [1:0] _GEN_24 = io_inst_0_ready ? _GEN_0 : {{1'd0}, nBufValid}; // @[IBuf.scala 47:29 34:47]
  wire [1:0] _GEN_48 = io_kill ? 2'h0 : _GEN_24; // @[IBuf.scala 63:20 64:17]
  wire [1:0] _icShiftAmt_T_1 = 2'h2 + _GEN_59; // @[IBuf.scala 68:32]
  wire [1:0] icShiftAmt = _icShiftAmt_T_1 - _GEN_58; // @[IBuf.scala 68:44]
  wire [63:0] _icData_T_2 = {io_imem_bits_data,io_imem_bits_data[15:0],io_imem_bits_data[15:0]}; // @[Cat.scala 31:58]
  wire [127:0] icData_data = {_icData_T_2[63:48],_icData_T_2[63:48],_icData_T_2[63:48],_icData_T_2[63:48],
    io_imem_bits_data,io_imem_bits_data[15:0],io_imem_bits_data[15:0]}; // @[Cat.scala 31:58]
  wire [5:0] _icData_T_3 = {icShiftAmt, 4'h0}; // @[IBuf.scala 121:19]
  wire [190:0] _GEN_1 = {{63'd0}, icData_data}; // @[IBuf.scala 121:10]
  wire [190:0] _icData_T_4 = _GEN_1 << _icData_T_3; // @[IBuf.scala 121:10]
  wire [31:0] icData = _icData_T_4[95:64]; // @[package.scala 154:13]
  wire [4:0] _icMask_T_1 = {nBufValid, 4'h0}; // @[IBuf.scala 71:65]
  wire [62:0] _icMask_T_2 = 63'hffffffff << _icMask_T_1; // @[IBuf.scala 71:51]
  wire [31:0] icMask = _icMask_T_2[31:0]; // @[IBuf.scala 71:92]
  wire [31:0] _inst_T = icData & icMask; // @[IBuf.scala 72:21]
  wire [31:0] _inst_T_1 = ~icMask; // @[IBuf.scala 72:43]
  wire [31:0] _inst_T_2 = buf__data & _inst_T_1; // @[IBuf.scala 72:41]
  wire  xcpt_1_ae_inst = bufMask[1] ? buf__xcpt_ae_inst : io_imem_bits_xcpt_ae_inst; // @[IBuf.scala 76:53]
  wire [1:0] _ic_replay_T = ~bufMask; // @[IBuf.scala 78:65]
  wire [1:0] _ic_replay_T_1 = valid & _ic_replay_T; // @[IBuf.scala 78:63]
  wire [1:0] _ic_replay_T_2 = io_imem_bits_replay ? _ic_replay_T_1 : 2'h0; // @[IBuf.scala 78:35]
  wire [1:0] ic_replay = buf_replay | _ic_replay_T_2; // @[IBuf.scala 78:30]
  wire [1:0] _replay_T_5 = {{1'd0}, ic_replay[1]}; // @[IBuf.scala 92:61]
  wire [2:0] _io_inst_0_bits_xcpt1_T_4 = {2'h0,xcpt_1_ae_inst}; // @[IBuf.scala 96:63]
  wire [2:0] _io_inst_0_bits_xcpt1_T_5 = exp_io_rvc ? 3'h0 : _io_inst_0_bits_xcpt1_T_4; // @[IBuf.scala 96:35]
  wire [1:0] _T_21 = {{1'd0}, bufMask[1]}; // @[IBuf.scala 100:50]
  RVCExpander exp ( // @[IBuf.scala 86:21]
    .io_in(exp_io_in),
    .io_out_bits(exp_io_out_bits),
    .io_out_rd(exp_io_out_rd),
    .io_out_rs1(exp_io_out_rs1),
    .io_out_rs2(exp_io_out_rs2),
    .io_rvc(exp_io_rvc)
  );
  assign io_imem_ready = io_inst_0_ready & nReady >= _GEN_59 & (nICReady >= nIC | 2'h1 >= _io_imem_ready_T_4); // @[IBuf.scala 44:60]
  assign io_pc = nBufValid > 1'h0 ? buf__pc : io_imem_bits_pc; // @[IBuf.scala 82:15]
  assign io_btb_resp_entry = bufMask[0] & exp_io_rvc | _T_21[0] ? ibufBTBResp_entry : io_imem_bits_btb_entry; // @[IBuf.scala 100:{57,71} 81:15]
  assign io_btb_resp_bht_history = bufMask[0] & exp_io_rvc | _T_21[0] ? ibufBTBResp_bht_history :
    io_imem_bits_btb_bht_history; // @[IBuf.scala 100:{57,71} 81:15]
  assign io_inst_0_valid = valid[0] & full_insn; // @[IBuf.scala 94:36]
  assign io_inst_0_bits_xcpt0_ae_inst = bufMask[0] ? buf__xcpt_ae_inst : io_imem_bits_xcpt_ae_inst; // @[IBuf.scala 76:53]
  assign io_inst_0_bits_xcpt1_pf_inst = _io_inst_0_bits_xcpt1_T_5[2]; // @[IBuf.scala 96:79]
  assign io_inst_0_bits_xcpt1_gf_inst = _io_inst_0_bits_xcpt1_T_5[1]; // @[IBuf.scala 96:79]
  assign io_inst_0_bits_xcpt1_ae_inst = _io_inst_0_bits_xcpt1_T_5[0]; // @[IBuf.scala 96:79]
  assign io_inst_0_bits_replay = ic_replay[0] | ~exp_io_rvc & _replay_T_5[0]; // @[IBuf.scala 92:33]
  assign io_inst_0_bits_rvc = exp_io_rvc; // @[IBuf.scala 98:27]
  assign io_inst_0_bits_inst_bits = exp_io_out_bits; // @[IBuf.scala 88:26]
  assign io_inst_0_bits_inst_rd = exp_io_out_rd; // @[IBuf.scala 88:26]
  assign io_inst_0_bits_inst_rs1 = exp_io_out_rs1; // @[IBuf.scala 88:26]
  assign io_inst_0_bits_inst_rs2 = exp_io_out_rs2; // @[IBuf.scala 88:26]
  assign io_inst_0_bits_raw = _inst_T | _inst_T_2; // @[IBuf.scala 72:30]
  assign exp_io_in = _inst_T | _inst_T_2; // @[IBuf.scala 72:30]
  always @(posedge clock) begin
    if (reset) begin // @[IBuf.scala 34:47]
      nBufValid <= 1'h0; // @[IBuf.scala 34:47]
    end else begin
      nBufValid <= _GEN_48[0];
    end
    if (io_inst_0_ready) begin // @[IBuf.scala 47:29]
      if (io_imem_valid & _io_imem_ready_T & nICReady < nIC & _io_imem_ready_T_5) begin // @[IBuf.scala 54:92]
        buf__pc <= _buf_pc_T_6; // @[IBuf.scala 59:16]
      end
    end
    if (io_inst_0_ready) begin // @[IBuf.scala 47:29]
      if (io_imem_valid & _io_imem_ready_T & nICReady < nIC & _io_imem_ready_T_5) begin // @[IBuf.scala 54:92]
        buf__data <= {{16'd0}, _buf_data_T_1[15:0]}; // @[IBuf.scala 58:18]
      end
    end
    if (io_inst_0_ready) begin // @[IBuf.scala 47:29]
      if (io_imem_valid & _io_imem_ready_T & nICReady < nIC & _io_imem_ready_T_5) begin // @[IBuf.scala 54:92]
        buf__xcpt_ae_inst <= io_imem_bits_xcpt_ae_inst; // @[IBuf.scala 57:13]
      end
    end
    if (io_inst_0_ready) begin // @[IBuf.scala 47:29]
      if (io_imem_valid & _io_imem_ready_T & nICReady < nIC & _io_imem_ready_T_5) begin // @[IBuf.scala 54:92]
        buf__replay <= io_imem_bits_replay; // @[IBuf.scala 57:13]
      end
    end
    if (io_inst_0_ready) begin // @[IBuf.scala 47:29]
      if (io_imem_valid & _io_imem_ready_T & nICReady < nIC & _io_imem_ready_T_5) begin // @[IBuf.scala 54:92]
        ibufBTBResp_entry <= io_imem_bits_btb_entry; // @[IBuf.scala 60:21]
      end
    end
    if (io_inst_0_ready) begin // @[IBuf.scala 47:29]
      if (io_imem_valid & _io_imem_ready_T & nICReady < nIC & _io_imem_ready_T_5) begin // @[IBuf.scala 54:92]
        ibufBTBResp_bht_history <= io_imem_bits_btb_bht_history; // @[IBuf.scala 60:21]
      end
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~io_imem_valid | ~io_imem_bits_btb_taken | io_imem_bits_btb_bridx >= pcWordBits) & ~reset) begin
          $fatal; // @[IBuf.scala 79:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~io_imem_valid | ~io_imem_bits_btb_taken | io_imem_bits_btb_bridx >= pcWordBits)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at IBuf.scala:79 assert(!io.imem.valid || !io.imem.bits.btb.taken || io.imem.bits.btb.bridx >= pcWordBits)\n"
            ); // @[IBuf.scala 79:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  nBufValid = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  buf__pc = _RAND_1[31:0];
  _RAND_2 = {1{`RANDOM}};
  buf__data = _RAND_2[31:0];
  _RAND_3 = {1{`RANDOM}};
  buf__xcpt_ae_inst = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  buf__replay = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  ibufBTBResp_entry = _RAND_5[4:0];
  _RAND_6 = {1{`RANDOM}};
  ibufBTBResp_bht_history = _RAND_6[7:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module CSRFile(
  input         clock,
  input         reset,
  input         io_ungated_clock,
  input         io_interrupts_debug,
  input         io_interrupts_mtip,
  input         io_interrupts_msip,
  input         io_interrupts_meip,
  input         io_interrupts_seip,
  input         io_hartid,
  input  [11:0] io_rw_addr,
  input  [2:0]  io_rw_cmd,
  output [31:0] io_rw_rdata,
  input  [31:0] io_rw_wdata,
  input  [31:0] io_decode_0_inst,
  output        io_decode_0_fp_illegal,
  output        io_decode_0_fp_csr,
  output        io_decode_0_read_illegal,
  output        io_decode_0_write_illegal,
  output        io_decode_0_write_flush,
  output        io_decode_0_system_illegal,
  output        io_csr_stall,
  output        io_eret,
  output        io_singleStep,
  output        io_status_debug,
  output        io_status_cease,
  output        io_status_wfi,
  output [31:0] io_status_isa,
  output [1:0]  io_status_dprv,
  output        io_status_dv,
  output [1:0]  io_status_prv,
  output        io_status_v,
  output        io_status_sd,
  output [22:0] io_status_zero2,
  output        io_status_mpv,
  output        io_status_gva,
  output        io_status_mbe,
  output        io_status_sbe,
  output [1:0]  io_status_sxl,
  output [1:0]  io_status_uxl,
  output        io_status_sd_rv32,
  output [7:0]  io_status_zero1,
  output        io_status_tsr,
  output        io_status_tw,
  output        io_status_tvm,
  output        io_status_mxr,
  output        io_status_sum,
  output        io_status_mprv,
  output [1:0]  io_status_xs,
  output [1:0]  io_status_fs,
  output [1:0]  io_status_mpp,
  output [1:0]  io_status_vs,
  output        io_status_spp,
  output        io_status_mpie,
  output        io_status_ube,
  output        io_status_spie,
  output        io_status_upie,
  output        io_status_mie,
  output        io_status_hie,
  output        io_status_sie,
  output        io_status_uie,
  output [31:0] io_evec,
  input         io_exception,
  input         io_retire,
  input  [31:0] io_cause,
  input  [31:0] io_pc,
  input  [31:0] io_tval,
  input         io_gva,
  output [31:0] io_time,
  output        io_interrupt,
  output [31:0] io_interrupt_cause,
  output        io_bp_0_control_action,
  output        io_bp_0_control_chain,
  output [1:0]  io_bp_0_control_tmatch,
  output        io_bp_0_control_m,
  output        io_bp_0_control_s,
  output        io_bp_0_control_u,
  output        io_bp_0_control_x,
  output        io_bp_0_control_w,
  output        io_bp_0_control_r,
  output [31:0] io_bp_0_address,
  output        io_bp_1_control_action,
  output [1:0]  io_bp_1_control_tmatch,
  output        io_bp_1_control_m,
  output        io_bp_1_control_s,
  output        io_bp_1_control_u,
  output        io_bp_1_control_x,
  output        io_bp_1_control_w,
  output        io_bp_1_control_r,
  output [31:0] io_bp_1_address,
  output        io_pmp_0_cfg_l,
  output [1:0]  io_pmp_0_cfg_a,
  output        io_pmp_0_cfg_x,
  output        io_pmp_0_cfg_w,
  output        io_pmp_0_cfg_r,
  output [28:0] io_pmp_0_addr,
  output [30:0] io_pmp_0_mask,
  output        io_pmp_1_cfg_l,
  output [1:0]  io_pmp_1_cfg_a,
  output        io_pmp_1_cfg_x,
  output        io_pmp_1_cfg_w,
  output        io_pmp_1_cfg_r,
  output [28:0] io_pmp_1_addr,
  output [30:0] io_pmp_1_mask,
  output        io_pmp_2_cfg_l,
  output [1:0]  io_pmp_2_cfg_a,
  output        io_pmp_2_cfg_x,
  output        io_pmp_2_cfg_w,
  output        io_pmp_2_cfg_r,
  output [28:0] io_pmp_2_addr,
  output [30:0] io_pmp_2_mask,
  output        io_pmp_3_cfg_l,
  output [1:0]  io_pmp_3_cfg_a,
  output        io_pmp_3_cfg_x,
  output        io_pmp_3_cfg_w,
  output        io_pmp_3_cfg_r,
  output [28:0] io_pmp_3_addr,
  output [30:0] io_pmp_3_mask,
  output        io_pmp_4_cfg_l,
  output [1:0]  io_pmp_4_cfg_a,
  output        io_pmp_4_cfg_x,
  output        io_pmp_4_cfg_w,
  output        io_pmp_4_cfg_r,
  output [28:0] io_pmp_4_addr,
  output [30:0] io_pmp_4_mask,
  output        io_pmp_5_cfg_l,
  output [1:0]  io_pmp_5_cfg_a,
  output        io_pmp_5_cfg_x,
  output        io_pmp_5_cfg_w,
  output        io_pmp_5_cfg_r,
  output [28:0] io_pmp_5_addr,
  output [30:0] io_pmp_5_mask,
  output        io_pmp_6_cfg_l,
  output [1:0]  io_pmp_6_cfg_a,
  output        io_pmp_6_cfg_x,
  output        io_pmp_6_cfg_w,
  output        io_pmp_6_cfg_r,
  output [28:0] io_pmp_6_addr,
  output [30:0] io_pmp_6_mask,
  output        io_pmp_7_cfg_l,
  output [1:0]  io_pmp_7_cfg_a,
  output        io_pmp_7_cfg_x,
  output        io_pmp_7_cfg_w,
  output        io_pmp_7_cfg_r,
  output [28:0] io_pmp_7_addr,
  output [30:0] io_pmp_7_mask,
  output        io_inhibit_cycle,
  input  [31:0] io_inst_0,
  output        io_trace_0_valid,
  output [31:0] io_trace_0_iaddr,
  output [31:0] io_trace_0_insn,
  output        io_trace_0_exception,
  output [31:0] io_customCSRs_0_value
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [31:0] _RAND_33;
  reg [31:0] _RAND_34;
  reg [31:0] _RAND_35;
  reg [31:0] _RAND_36;
  reg [31:0] _RAND_37;
  reg [31:0] _RAND_38;
  reg [31:0] _RAND_39;
  reg [31:0] _RAND_40;
  reg [31:0] _RAND_41;
  reg [31:0] _RAND_42;
  reg [31:0] _RAND_43;
  reg [31:0] _RAND_44;
  reg [31:0] _RAND_45;
  reg [31:0] _RAND_46;
  reg [31:0] _RAND_47;
  reg [31:0] _RAND_48;
  reg [31:0] _RAND_49;
  reg [31:0] _RAND_50;
  reg [31:0] _RAND_51;
  reg [31:0] _RAND_52;
  reg [31:0] _RAND_53;
  reg [31:0] _RAND_54;
  reg [31:0] _RAND_55;
  reg [31:0] _RAND_56;
  reg [31:0] _RAND_57;
  reg [31:0] _RAND_58;
  reg [31:0] _RAND_59;
  reg [31:0] _RAND_60;
  reg [31:0] _RAND_61;
  reg [31:0] _RAND_62;
  reg [31:0] _RAND_63;
  reg [31:0] _RAND_64;
  reg [31:0] _RAND_65;
  reg [31:0] _RAND_66;
  reg [31:0] _RAND_67;
  reg [31:0] _RAND_68;
  reg [31:0] _RAND_69;
  reg [31:0] _RAND_70;
  reg [31:0] _RAND_71;
  reg [31:0] _RAND_72;
  reg [31:0] _RAND_73;
  reg [31:0] _RAND_74;
  reg [31:0] _RAND_75;
  reg [31:0] _RAND_76;
  reg [31:0] _RAND_77;
  reg [31:0] _RAND_78;
  reg [31:0] _RAND_79;
  reg [31:0] _RAND_80;
  reg [31:0] _RAND_81;
  reg [31:0] _RAND_82;
  reg [31:0] _RAND_83;
  reg [31:0] _RAND_84;
  reg [31:0] _RAND_85;
  reg [31:0] _RAND_86;
  reg [31:0] _RAND_87;
  reg [31:0] _RAND_88;
  reg [31:0] _RAND_89;
  reg [31:0] _RAND_90;
  reg [31:0] _RAND_91;
  reg [31:0] _RAND_92;
  reg [31:0] _RAND_93;
  reg [31:0] _RAND_94;
  reg [31:0] _RAND_95;
  reg [31:0] _RAND_96;
  reg [31:0] _RAND_97;
  reg [31:0] _RAND_98;
  reg [31:0] _RAND_99;
  reg [31:0] _RAND_100;
  reg [31:0] _RAND_101;
  reg [31:0] _RAND_102;
  reg [31:0] _RAND_103;
  reg [31:0] _RAND_104;
  reg [31:0] _RAND_105;
  reg [31:0] _RAND_106;
  reg [31:0] _RAND_107;
  reg [31:0] _RAND_108;
  reg [31:0] _RAND_109;
  reg [31:0] _RAND_110;
  reg [31:0] _RAND_111;
  reg [31:0] _RAND_112;
  reg [63:0] _RAND_113;
  reg [31:0] _RAND_114;
  reg [63:0] _RAND_115;
  reg [31:0] _RAND_116;
  reg [31:0] _RAND_117;
  reg [31:0] _RAND_118;
`endif // RANDOMIZE_REG_INIT
  reg [1:0] reg_mstatus_prv; // @[CSR.scala 369:24]
  reg  reg_mstatus_gva; // @[CSR.scala 369:24]
  reg  reg_mstatus_tsr; // @[CSR.scala 369:24]
  reg  reg_mstatus_tw; // @[CSR.scala 369:24]
  reg  reg_mstatus_mprv; // @[CSR.scala 369:24]
  reg [1:0] reg_mstatus_fs; // @[CSR.scala 369:24]
  reg [1:0] reg_mstatus_mpp; // @[CSR.scala 369:24]
  reg  reg_mstatus_spp; // @[CSR.scala 369:24]
  reg  reg_mstatus_mpie; // @[CSR.scala 369:24]
  reg  reg_mstatus_spie; // @[CSR.scala 369:24]
  reg  reg_mstatus_mie; // @[CSR.scala 369:24]
  reg  reg_mstatus_sie; // @[CSR.scala 369:24]
  wire  system_insn = io_rw_cmd == 3'h4; // @[CSR.scala 813:31]
  wire [31:0] _T_327 = {io_rw_addr, 20'h0}; // @[CSR.scala 829:28]
  wire [31:0] _T_334 = _T_327 & 32'h10400000; // @[Decode.scala 14:65]
  wire  _T_335 = _T_334 == 32'h10000000; // @[Decode.scala 14:121]
  wire  insn_ret = system_insn & _T_335; // @[CSR.scala 829:95]
  reg [1:0] reg_dcsr_prv; // @[CSR.scala 377:21]
  wire [1:0] _GEN_236 = io_rw_addr[10] & io_rw_addr[7] ? reg_dcsr_prv : reg_mstatus_mpp; // @[CSR.scala 1064:70 1065:15]
  wire [1:0] ret_prv = ~io_rw_addr[9] ? {{1'd0}, reg_mstatus_spp} : _GEN_236; // @[CSR.scala 1047:52]
  wire [31:0] _T_328 = _T_327 & 32'h10100000; // @[Decode.scala 14:65]
  wire  _T_329 = _T_328 == 32'h0; // @[Decode.scala 14:121]
  wire  insn_call = system_insn & _T_329; // @[CSR.scala 829:95]
  wire  _T_332 = _T_328 == 32'h100000; // @[Decode.scala 14:121]
  wire  insn_break = system_insn & _T_332; // @[CSR.scala 829:95]
  wire  _exception_T = insn_call | insn_break; // @[CSR.scala 953:29]
  wire  exception = insn_call | insn_break | io_exception; // @[CSR.scala 953:43]
  reg  reg_singleStepped; // @[CSR.scala 453:30]
  wire [3:0] _GEN_34 = {{2'd0}, reg_mstatus_prv}; // @[CSR.scala 893:38]
  wire [3:0] _cause_T_4 = 4'h8 + _GEN_34; // @[CSR.scala 893:38]
  wire [31:0] _cause_T_5 = insn_break ? 32'h3 : io_cause; // @[CSR.scala 894:14]
  wire [31:0] cause = insn_call ? {{28'd0}, _cause_T_4} : _cause_T_5; // @[CSR.scala 893:8]
  wire [7:0] cause_lsbs = cause[7:0]; // @[CSR.scala 895:25]
  wire  _causeIsDebugInt_T_1 = cause_lsbs == 8'he; // @[CSR.scala 896:53]
  wire  causeIsDebugInt = cause[31] & cause_lsbs == 8'he; // @[CSR.scala 896:39]
  wire  _causeIsDebugTrigger_T_1 = ~cause[31]; // @[CSR.scala 897:29]
  wire  causeIsDebugTrigger = ~cause[31] & _causeIsDebugInt_T_1; // @[CSR.scala 897:44]
  reg  reg_dcsr_ebreakm; // @[CSR.scala 377:21]
  reg  reg_dcsr_ebreaks; // @[CSR.scala 377:21]
  reg  reg_dcsr_ebreaku; // @[CSR.scala 377:21]
  wire [3:0] _causeIsDebugBreak_T_3 = {reg_dcsr_ebreakm,1'h0,reg_dcsr_ebreaks,reg_dcsr_ebreaku}; // @[Cat.scala 31:58]
  wire [3:0] _causeIsDebugBreak_T_4 = _causeIsDebugBreak_T_3 >> reg_mstatus_prv; // @[CSR.scala 898:134]
  wire  causeIsDebugBreak = _causeIsDebugTrigger_T_1 & insn_break & _causeIsDebugBreak_T_4[0]; // @[CSR.scala 898:56]
  reg  reg_debug; // @[CSR.scala 449:22]
  wire  trapToDebug = reg_singleStepped | causeIsDebugInt | causeIsDebugTrigger | causeIsDebugBreak | reg_debug; // @[CSR.scala 899:123]
  wire  _T_401 = ~reg_debug; // @[CSR.scala 969:13]
  wire [1:0] _GEN_56 = ~reg_debug ? 2'h3 : reg_mstatus_prv; // @[CSR.scala 969:25 976:17]
  wire  _delegate_T = reg_mstatus_prv <= 2'h1; // @[CSR.scala 903:59]
  reg [31:0] reg_mideleg; // @[CSR.scala 464:18]
  wire [31:0] read_mideleg = reg_mideleg & 32'h222; // @[CSR.scala 465:36]
  wire [31:0] _delegate_T_3 = read_mideleg >> cause_lsbs; // @[CSR.scala 903:102]
  reg [31:0] reg_medeleg; // @[CSR.scala 468:18]
  wire [31:0] read_medeleg = reg_medeleg & 32'hf0b55d; // @[CSR.scala 469:36]
  wire [31:0] _delegate_T_5 = read_medeleg >> cause_lsbs; // @[CSR.scala 903:128]
  wire  _delegate_T_7 = cause[31] ? _delegate_T_3[0] : _delegate_T_5[0]; // @[CSR.scala 903:74]
  wire  delegate = reg_mstatus_prv <= 2'h1 & _delegate_T_7; // @[CSR.scala 903:68]
  wire [1:0] _GEN_75 = delegate ? 2'h1 : 2'h3; // @[CSR.scala 1009:15 1021:15 997:35]
  wire [1:0] _GEN_150 = trapToDebug ? _GEN_56 : _GEN_75; // @[CSR.scala 968:24]
  wire [1:0] _GEN_187 = exception ? _GEN_150 : reg_mstatus_prv; // @[CSR.scala 967:20]
  wire [1:0] new_prv = insn_ret ? ret_prv : _GEN_187; // @[CSR.scala 1045:19 1084:13]
  reg [2:0] reg_dcsr_cause; // @[CSR.scala 377:21]
  reg  reg_dcsr_step; // @[CSR.scala 377:21]
  reg [31:0] reg_dpc; // @[CSR.scala 450:20]
  reg [31:0] reg_dscratch; // @[CSR.scala 451:25]
  reg  reg_tselect; // @[CSR.scala 458:24]
  reg  reg_bp_0_control_dmode; // @[CSR.scala 459:19]
  reg  reg_bp_0_control_action; // @[CSR.scala 459:19]
  reg  reg_bp_0_control_chain; // @[CSR.scala 459:19]
  reg [1:0] reg_bp_0_control_tmatch; // @[CSR.scala 459:19]
  reg  reg_bp_0_control_m; // @[CSR.scala 459:19]
  reg  reg_bp_0_control_s; // @[CSR.scala 459:19]
  reg  reg_bp_0_control_u; // @[CSR.scala 459:19]
  reg  reg_bp_0_control_x; // @[CSR.scala 459:19]
  reg  reg_bp_0_control_w; // @[CSR.scala 459:19]
  reg  reg_bp_0_control_r; // @[CSR.scala 459:19]
  reg [31:0] reg_bp_0_address; // @[CSR.scala 459:19]
  reg  reg_bp_1_control_dmode; // @[CSR.scala 459:19]
  reg  reg_bp_1_control_action; // @[CSR.scala 459:19]
  reg [1:0] reg_bp_1_control_tmatch; // @[CSR.scala 459:19]
  reg  reg_bp_1_control_m; // @[CSR.scala 459:19]
  reg  reg_bp_1_control_s; // @[CSR.scala 459:19]
  reg  reg_bp_1_control_u; // @[CSR.scala 459:19]
  reg  reg_bp_1_control_x; // @[CSR.scala 459:19]
  reg  reg_bp_1_control_w; // @[CSR.scala 459:19]
  reg  reg_bp_1_control_r; // @[CSR.scala 459:19]
  reg [31:0] reg_bp_1_address; // @[CSR.scala 459:19]
  reg  reg_pmp_0_cfg_l; // @[CSR.scala 460:20]
  reg [1:0] reg_pmp_0_cfg_a; // @[CSR.scala 460:20]
  reg  reg_pmp_0_cfg_x; // @[CSR.scala 460:20]
  reg  reg_pmp_0_cfg_w; // @[CSR.scala 460:20]
  reg  reg_pmp_0_cfg_r; // @[CSR.scala 460:20]
  reg [28:0] reg_pmp_0_addr; // @[CSR.scala 460:20]
  reg  reg_pmp_1_cfg_l; // @[CSR.scala 460:20]
  reg [1:0] reg_pmp_1_cfg_a; // @[CSR.scala 460:20]
  reg  reg_pmp_1_cfg_x; // @[CSR.scala 460:20]
  reg  reg_pmp_1_cfg_w; // @[CSR.scala 460:20]
  reg  reg_pmp_1_cfg_r; // @[CSR.scala 460:20]
  reg [28:0] reg_pmp_1_addr; // @[CSR.scala 460:20]
  reg  reg_pmp_2_cfg_l; // @[CSR.scala 460:20]
  reg [1:0] reg_pmp_2_cfg_a; // @[CSR.scala 460:20]
  reg  reg_pmp_2_cfg_x; // @[CSR.scala 460:20]
  reg  reg_pmp_2_cfg_w; // @[CSR.scala 460:20]
  reg  reg_pmp_2_cfg_r; // @[CSR.scala 460:20]
  reg [28:0] reg_pmp_2_addr; // @[CSR.scala 460:20]
  reg  reg_pmp_3_cfg_l; // @[CSR.scala 460:20]
  reg [1:0] reg_pmp_3_cfg_a; // @[CSR.scala 460:20]
  reg  reg_pmp_3_cfg_x; // @[CSR.scala 460:20]
  reg  reg_pmp_3_cfg_w; // @[CSR.scala 460:20]
  reg  reg_pmp_3_cfg_r; // @[CSR.scala 460:20]
  reg [28:0] reg_pmp_3_addr; // @[CSR.scala 460:20]
  reg  reg_pmp_4_cfg_l; // @[CSR.scala 460:20]
  reg [1:0] reg_pmp_4_cfg_a; // @[CSR.scala 460:20]
  reg  reg_pmp_4_cfg_x; // @[CSR.scala 460:20]
  reg  reg_pmp_4_cfg_w; // @[CSR.scala 460:20]
  reg  reg_pmp_4_cfg_r; // @[CSR.scala 460:20]
  reg [28:0] reg_pmp_4_addr; // @[CSR.scala 460:20]
  reg  reg_pmp_5_cfg_l; // @[CSR.scala 460:20]
  reg [1:0] reg_pmp_5_cfg_a; // @[CSR.scala 460:20]
  reg  reg_pmp_5_cfg_x; // @[CSR.scala 460:20]
  reg  reg_pmp_5_cfg_w; // @[CSR.scala 460:20]
  reg  reg_pmp_5_cfg_r; // @[CSR.scala 460:20]
  reg [28:0] reg_pmp_5_addr; // @[CSR.scala 460:20]
  reg  reg_pmp_6_cfg_l; // @[CSR.scala 460:20]
  reg [1:0] reg_pmp_6_cfg_a; // @[CSR.scala 460:20]
  reg  reg_pmp_6_cfg_x; // @[CSR.scala 460:20]
  reg  reg_pmp_6_cfg_w; // @[CSR.scala 460:20]
  reg  reg_pmp_6_cfg_r; // @[CSR.scala 460:20]
  reg [28:0] reg_pmp_6_addr; // @[CSR.scala 460:20]
  reg  reg_pmp_7_cfg_l; // @[CSR.scala 460:20]
  reg [1:0] reg_pmp_7_cfg_a; // @[CSR.scala 460:20]
  reg  reg_pmp_7_cfg_x; // @[CSR.scala 460:20]
  reg  reg_pmp_7_cfg_w; // @[CSR.scala 460:20]
  reg  reg_pmp_7_cfg_r; // @[CSR.scala 460:20]
  reg [28:0] reg_pmp_7_addr; // @[CSR.scala 460:20]
  reg [31:0] reg_mie; // @[CSR.scala 462:20]
  reg  reg_mip_seip; // @[CSR.scala 471:20]
  reg  reg_mip_stip; // @[CSR.scala 471:20]
  reg  reg_mip_ssip; // @[CSR.scala 471:20]
  reg [31:0] reg_mepc; // @[CSR.scala 472:21]
  reg [31:0] reg_mcause; // @[CSR.scala 473:27]
  reg [31:0] reg_mtval; // @[CSR.scala 474:22]
  reg [31:0] reg_mscratch; // @[CSR.scala 476:25]
  reg [30:0] reg_mtvec; // @[CSR.scala 479:27]
  reg [31:0] reg_mcounteren; // @[CSR.scala 494:18]
  wire [31:0] read_mcounteren = reg_mcounteren & 32'h7; // @[CSR.scala 495:30]
  reg [31:0] reg_scounteren; // @[CSR.scala 498:18]
  wire [31:0] read_scounteren = reg_scounteren & 32'h7; // @[CSR.scala 499:36]
  wire [15:0] _read_hvip_T = {4'h0,2'h0,reg_mip_seip,1'h0,2'h0,reg_mip_stip,1'h0,2'h0,reg_mip_ssip,1'h0}; // @[CSR.scala 518:27]
  reg [31:0] reg_sepc; // @[CSR.scala 532:21]
  reg [31:0] reg_scause; // @[CSR.scala 533:23]
  reg [31:0] reg_stval; // @[CSR.scala 534:22]
  reg [31:0] reg_sscratch; // @[CSR.scala 535:25]
  reg [31:0] reg_stvec; // @[CSR.scala 536:22]
  reg  reg_wfi; // @[CSR.scala 538:50]
  reg [2:0] reg_mcountinhibit; // @[CSR.scala 547:34]
  wire  x79 = reg_mcountinhibit[2]; // @[CSR.scala 549:75]
  reg [5:0] small_; // @[Counters.scala 45:37]
  wire [5:0] _GEN_35 = {{5'd0}, io_retire}; // @[Counters.scala 46:33]
  wire [6:0] nextSmall = small_ + _GEN_35; // @[Counters.scala 46:33]
  wire  _T_14 = ~x79; // @[Counters.scala 47:9]
  wire [6:0] _GEN_0 = ~x79 ? nextSmall : {{1'd0}, small_}; // @[Counters.scala 47:{19,27} 45:37]
  reg [57:0] large_; // @[Counters.scala 50:27]
  wire [57:0] _large_r_T_1 = large_ + 58'h1; // @[Counters.scala 51:55]
  wire [57:0] _GEN_1 = nextSmall[6] & _T_14 ? _large_r_T_1 : large_; // @[Counters.scala 50:27 51:{46,50}]
  wire [63:0] value = {large_,small_}; // @[Cat.scala 31:58]
  wire  x86 = ~io_csr_stall; // @[CSR.scala 551:56]
  reg [5:0] small_1; // @[Counters.scala 45:37]
  wire [5:0] _GEN_40 = {{5'd0}, x86}; // @[Counters.scala 46:33]
  wire [6:0] nextSmall_1 = small_1 + _GEN_40; // @[Counters.scala 46:33]
  wire  _T_15 = ~reg_mcountinhibit[0]; // @[Counters.scala 47:9]
  wire [6:0] _GEN_2 = ~reg_mcountinhibit[0] ? nextSmall_1 : {{1'd0}, small_1}; // @[Counters.scala 47:{19,27} 45:37]
  reg [57:0] large_1; // @[Counters.scala 50:27]
  wire [57:0] _large_r_T_3 = large_1 + 58'h1; // @[Counters.scala 51:55]
  wire [57:0] _GEN_3 = nextSmall_1[6] & _T_15 ? _large_r_T_3 : large_1; // @[Counters.scala 50:27 51:{46,50}]
  wire [63:0] value_1 = {large_1,small_1}; // @[Cat.scala 31:58]
  wire  mip_seip = reg_mip_seip | io_interrupts_seip; // @[CSR.scala 563:57]
  wire [7:0] read_mip_lo = {io_interrupts_mtip,1'h0,reg_mip_stip,1'h0,io_interrupts_msip,1'h0,reg_mip_ssip,1'h0}; // @[CSR.scala 567:22]
  wire [15:0] _read_mip_T = {4'h0,io_interrupts_meip,1'h0,mip_seip,1'h0,read_mip_lo}; // @[CSR.scala 567:22]
  wire [15:0] read_mip = _read_mip_T & 16'haaa; // @[CSR.scala 567:29]
  wire [31:0] _GEN_41 = {{16'd0}, read_mip}; // @[CSR.scala 571:56]
  wire [31:0] pending_interrupts = _GEN_41 & reg_mie; // @[CSR.scala 571:56]
  wire [14:0] d_interrupts = {io_interrupts_debug, 14'h0}; // @[CSR.scala 572:42]
  wire [31:0] _m_interrupts_T_3 = ~pending_interrupts; // @[CSR.scala 577:83]
  wire [31:0] _m_interrupts_T_4 = _m_interrupts_T_3 | read_mideleg; // @[CSR.scala 577:103]
  wire [31:0] _m_interrupts_T_5 = ~_m_interrupts_T_4; // @[CSR.scala 577:81]
  wire [31:0] m_interrupts = _delegate_T | reg_mstatus_mie ? _m_interrupts_T_5 : 32'h0; // @[CSR.scala 577:25]
  wire [31:0] _s_interrupts_T_6 = pending_interrupts & read_mideleg; // @[CSR.scala 578:147]
  wire [31:0] s_interrupts = reg_mstatus_prv < 2'h1 | reg_mstatus_prv == 2'h1 & reg_mstatus_sie ? _s_interrupts_T_6 : 32'h0
    ; // @[CSR.scala 578:25]
  wire  _any_T_78 = d_interrupts[14] | d_interrupts[13] | d_interrupts[12] | d_interrupts[11] | d_interrupts[3] |
    d_interrupts[7] | d_interrupts[9] | d_interrupts[1] | d_interrupts[5] | d_interrupts[10] | d_interrupts[2] |
    d_interrupts[6] | d_interrupts[8] | d_interrupts[0] | d_interrupts[4] | m_interrupts[15]; // @[CSR.scala 1534:90]
  wire  _any_T_93 = _any_T_78 | m_interrupts[14] | m_interrupts[13] | m_interrupts[12] | m_interrupts[11] | m_interrupts
    [3] | m_interrupts[7] | m_interrupts[9] | m_interrupts[1] | m_interrupts[5] | m_interrupts[10] | m_interrupts[2] |
    m_interrupts[6] | m_interrupts[8] | m_interrupts[0] | m_interrupts[4]; // @[CSR.scala 1534:90]
  wire  _any_T_108 = _any_T_93 | s_interrupts[15] | s_interrupts[14] | s_interrupts[13] | s_interrupts[12] |
    s_interrupts[11] | s_interrupts[3] | s_interrupts[7] | s_interrupts[9] | s_interrupts[1] | s_interrupts[5] |
    s_interrupts[10] | s_interrupts[2] | s_interrupts[6] | s_interrupts[8] | s_interrupts[0]; // @[CSR.scala 1534:90]
  wire  anyInterrupt = _any_T_108 | s_interrupts[4]; // @[CSR.scala 1534:90]
  wire [3:0] _which_T_79 = s_interrupts[0] ? 4'h0 : 4'h4; // @[Mux.scala 47:70]
  wire [3:0] _which_T_80 = s_interrupts[8] ? 4'h8 : _which_T_79; // @[Mux.scala 47:70]
  wire [3:0] _which_T_81 = s_interrupts[6] ? 4'h6 : _which_T_80; // @[Mux.scala 47:70]
  wire [3:0] _which_T_82 = s_interrupts[2] ? 4'h2 : _which_T_81; // @[Mux.scala 47:70]
  wire [3:0] _which_T_83 = s_interrupts[10] ? 4'ha : _which_T_82; // @[Mux.scala 47:70]
  wire [3:0] _which_T_84 = s_interrupts[5] ? 4'h5 : _which_T_83; // @[Mux.scala 47:70]
  wire [3:0] _which_T_85 = s_interrupts[1] ? 4'h1 : _which_T_84; // @[Mux.scala 47:70]
  wire [3:0] _which_T_86 = s_interrupts[9] ? 4'h9 : _which_T_85; // @[Mux.scala 47:70]
  wire [3:0] _which_T_87 = s_interrupts[7] ? 4'h7 : _which_T_86; // @[Mux.scala 47:70]
  wire [3:0] _which_T_88 = s_interrupts[3] ? 4'h3 : _which_T_87; // @[Mux.scala 47:70]
  wire [3:0] _which_T_89 = s_interrupts[11] ? 4'hb : _which_T_88; // @[Mux.scala 47:70]
  wire [3:0] _which_T_90 = s_interrupts[12] ? 4'hc : _which_T_89; // @[Mux.scala 47:70]
  wire [3:0] _which_T_91 = s_interrupts[13] ? 4'hd : _which_T_90; // @[Mux.scala 47:70]
  wire [3:0] _which_T_92 = s_interrupts[14] ? 4'he : _which_T_91; // @[Mux.scala 47:70]
  wire [3:0] _which_T_93 = s_interrupts[15] ? 4'hf : _which_T_92; // @[Mux.scala 47:70]
  wire [3:0] _which_T_94 = m_interrupts[4] ? 4'h4 : _which_T_93; // @[Mux.scala 47:70]
  wire [3:0] _which_T_95 = m_interrupts[0] ? 4'h0 : _which_T_94; // @[Mux.scala 47:70]
  wire [3:0] _which_T_96 = m_interrupts[8] ? 4'h8 : _which_T_95; // @[Mux.scala 47:70]
  wire [3:0] _which_T_97 = m_interrupts[6] ? 4'h6 : _which_T_96; // @[Mux.scala 47:70]
  wire [3:0] _which_T_98 = m_interrupts[2] ? 4'h2 : _which_T_97; // @[Mux.scala 47:70]
  wire [3:0] _which_T_99 = m_interrupts[10] ? 4'ha : _which_T_98; // @[Mux.scala 47:70]
  wire [3:0] _which_T_100 = m_interrupts[5] ? 4'h5 : _which_T_99; // @[Mux.scala 47:70]
  wire [3:0] _which_T_101 = m_interrupts[1] ? 4'h1 : _which_T_100; // @[Mux.scala 47:70]
  wire [3:0] _which_T_102 = m_interrupts[9] ? 4'h9 : _which_T_101; // @[Mux.scala 47:70]
  wire [3:0] _which_T_103 = m_interrupts[7] ? 4'h7 : _which_T_102; // @[Mux.scala 47:70]
  wire [3:0] _which_T_104 = m_interrupts[3] ? 4'h3 : _which_T_103; // @[Mux.scala 47:70]
  wire [3:0] _which_T_105 = m_interrupts[11] ? 4'hb : _which_T_104; // @[Mux.scala 47:70]
  wire [3:0] _which_T_106 = m_interrupts[12] ? 4'hc : _which_T_105; // @[Mux.scala 47:70]
  wire [3:0] _which_T_107 = m_interrupts[13] ? 4'hd : _which_T_106; // @[Mux.scala 47:70]
  wire [3:0] _which_T_108 = m_interrupts[14] ? 4'he : _which_T_107; // @[Mux.scala 47:70]
  wire [3:0] _which_T_109 = m_interrupts[15] ? 4'hf : _which_T_108; // @[Mux.scala 47:70]
  wire [3:0] _which_T_111 = d_interrupts[4] ? 4'h4 : _which_T_109; // @[Mux.scala 47:70]
  wire [3:0] _which_T_112 = d_interrupts[0] ? 4'h0 : _which_T_111; // @[Mux.scala 47:70]
  wire [3:0] _which_T_113 = d_interrupts[8] ? 4'h8 : _which_T_112; // @[Mux.scala 47:70]
  wire [3:0] _which_T_114 = d_interrupts[6] ? 4'h6 : _which_T_113; // @[Mux.scala 47:70]
  wire [3:0] _which_T_115 = d_interrupts[2] ? 4'h2 : _which_T_114; // @[Mux.scala 47:70]
  wire [3:0] _which_T_116 = d_interrupts[10] ? 4'ha : _which_T_115; // @[Mux.scala 47:70]
  wire [3:0] _which_T_117 = d_interrupts[5] ? 4'h5 : _which_T_116; // @[Mux.scala 47:70]
  wire [3:0] _which_T_118 = d_interrupts[1] ? 4'h1 : _which_T_117; // @[Mux.scala 47:70]
  wire [3:0] _which_T_119 = d_interrupts[9] ? 4'h9 : _which_T_118; // @[Mux.scala 47:70]
  wire [3:0] _which_T_120 = d_interrupts[7] ? 4'h7 : _which_T_119; // @[Mux.scala 47:70]
  wire [3:0] _which_T_121 = d_interrupts[3] ? 4'h3 : _which_T_120; // @[Mux.scala 47:70]
  wire [3:0] _which_T_122 = d_interrupts[11] ? 4'hb : _which_T_121; // @[Mux.scala 47:70]
  wire [3:0] _which_T_123 = d_interrupts[12] ? 4'hc : _which_T_122; // @[Mux.scala 47:70]
  wire [3:0] _which_T_124 = d_interrupts[13] ? 4'hd : _which_T_123; // @[Mux.scala 47:70]
  wire [3:0] whichInterrupt = d_interrupts[14] ? 4'he : _which_T_124; // @[Mux.scala 47:70]
  wire [31:0] _GEN_639 = {{28'd0}, whichInterrupt}; // @[CSR.scala 582:67]
  wire  _io_interrupt_T = ~io_singleStep; // @[CSR.scala 583:36]
  wire [29:0] pmp_mask_base = {reg_pmp_0_addr,reg_pmp_0_cfg_a[0]}; // @[Cat.scala 31:58]
  wire [29:0] _pmp_mask_T_1 = pmp_mask_base + 30'h1; // @[PMP.scala 59:23]
  wire [29:0] _pmp_mask_T_2 = ~_pmp_mask_T_1; // @[PMP.scala 59:16]
  wire [29:0] _pmp_mask_T_3 = pmp_mask_base & _pmp_mask_T_2; // @[PMP.scala 59:14]
  wire [31:0] _pmp_mask_T_4 = {_pmp_mask_T_3,2'h3}; // @[Cat.scala 31:58]
  wire [29:0] pmp_mask_base_1 = {reg_pmp_1_addr,reg_pmp_1_cfg_a[0]}; // @[Cat.scala 31:58]
  wire [29:0] _pmp_mask_T_6 = pmp_mask_base_1 + 30'h1; // @[PMP.scala 59:23]
  wire [29:0] _pmp_mask_T_7 = ~_pmp_mask_T_6; // @[PMP.scala 59:16]
  wire [29:0] _pmp_mask_T_8 = pmp_mask_base_1 & _pmp_mask_T_7; // @[PMP.scala 59:14]
  wire [31:0] _pmp_mask_T_9 = {_pmp_mask_T_8,2'h3}; // @[Cat.scala 31:58]
  wire [29:0] pmp_mask_base_2 = {reg_pmp_2_addr,reg_pmp_2_cfg_a[0]}; // @[Cat.scala 31:58]
  wire [29:0] _pmp_mask_T_11 = pmp_mask_base_2 + 30'h1; // @[PMP.scala 59:23]
  wire [29:0] _pmp_mask_T_12 = ~_pmp_mask_T_11; // @[PMP.scala 59:16]
  wire [29:0] _pmp_mask_T_13 = pmp_mask_base_2 & _pmp_mask_T_12; // @[PMP.scala 59:14]
  wire [31:0] _pmp_mask_T_14 = {_pmp_mask_T_13,2'h3}; // @[Cat.scala 31:58]
  wire [29:0] pmp_mask_base_3 = {reg_pmp_3_addr,reg_pmp_3_cfg_a[0]}; // @[Cat.scala 31:58]
  wire [29:0] _pmp_mask_T_16 = pmp_mask_base_3 + 30'h1; // @[PMP.scala 59:23]
  wire [29:0] _pmp_mask_T_17 = ~_pmp_mask_T_16; // @[PMP.scala 59:16]
  wire [29:0] _pmp_mask_T_18 = pmp_mask_base_3 & _pmp_mask_T_17; // @[PMP.scala 59:14]
  wire [31:0] _pmp_mask_T_19 = {_pmp_mask_T_18,2'h3}; // @[Cat.scala 31:58]
  wire [29:0] pmp_mask_base_4 = {reg_pmp_4_addr,reg_pmp_4_cfg_a[0]}; // @[Cat.scala 31:58]
  wire [29:0] _pmp_mask_T_21 = pmp_mask_base_4 + 30'h1; // @[PMP.scala 59:23]
  wire [29:0] _pmp_mask_T_22 = ~_pmp_mask_T_21; // @[PMP.scala 59:16]
  wire [29:0] _pmp_mask_T_23 = pmp_mask_base_4 & _pmp_mask_T_22; // @[PMP.scala 59:14]
  wire [31:0] _pmp_mask_T_24 = {_pmp_mask_T_23,2'h3}; // @[Cat.scala 31:58]
  wire [29:0] pmp_mask_base_5 = {reg_pmp_5_addr,reg_pmp_5_cfg_a[0]}; // @[Cat.scala 31:58]
  wire [29:0] _pmp_mask_T_26 = pmp_mask_base_5 + 30'h1; // @[PMP.scala 59:23]
  wire [29:0] _pmp_mask_T_27 = ~_pmp_mask_T_26; // @[PMP.scala 59:16]
  wire [29:0] _pmp_mask_T_28 = pmp_mask_base_5 & _pmp_mask_T_27; // @[PMP.scala 59:14]
  wire [31:0] _pmp_mask_T_29 = {_pmp_mask_T_28,2'h3}; // @[Cat.scala 31:58]
  wire [29:0] pmp_mask_base_6 = {reg_pmp_6_addr,reg_pmp_6_cfg_a[0]}; // @[Cat.scala 31:58]
  wire [29:0] _pmp_mask_T_31 = pmp_mask_base_6 + 30'h1; // @[PMP.scala 59:23]
  wire [29:0] _pmp_mask_T_32 = ~_pmp_mask_T_31; // @[PMP.scala 59:16]
  wire [29:0] _pmp_mask_T_33 = pmp_mask_base_6 & _pmp_mask_T_32; // @[PMP.scala 59:14]
  wire [31:0] _pmp_mask_T_34 = {_pmp_mask_T_33,2'h3}; // @[Cat.scala 31:58]
  wire [29:0] pmp_mask_base_7 = {reg_pmp_7_addr,reg_pmp_7_cfg_a[0]}; // @[Cat.scala 31:58]
  wire [29:0] _pmp_mask_T_36 = pmp_mask_base_7 + 30'h1; // @[PMP.scala 59:23]
  wire [29:0] _pmp_mask_T_37 = ~_pmp_mask_T_36; // @[PMP.scala 59:16]
  wire [29:0] _pmp_mask_T_38 = pmp_mask_base_7 & _pmp_mask_T_37; // @[PMP.scala 59:14]
  wire [31:0] _pmp_mask_T_39 = {_pmp_mask_T_38,2'h3}; // @[Cat.scala 31:58]
  reg [31:0] reg_misa; // @[CSR.scala 605:21]
  wire [8:0] read_mstatus_lo_lo = {io_status_spp,io_status_mpie,io_status_ube,io_status_spie,io_status_upie,
    io_status_mie,io_status_hie,io_status_sie,io_status_uie}; // @[CSR.scala 606:38]
  wire [21:0] read_mstatus_lo = {io_status_tw,io_status_tvm,io_status_mxr,io_status_sum,io_status_mprv,io_status_xs,
    io_status_fs,io_status_mpp,io_status_vs,read_mstatus_lo_lo}; // @[CSR.scala 606:38]
  wire [64:0] read_mstatus_hi_hi = {io_status_debug,io_status_cease,io_status_wfi,io_status_isa,io_status_dprv,
    io_status_dv,io_status_prv,io_status_v,io_status_sd,io_status_zero2}; // @[CSR.scala 606:38]
  wire [82:0] read_mstatus_hi = {read_mstatus_hi_hi,io_status_mpv,io_status_gva,io_status_mbe,io_status_sbe,
    io_status_sxl,io_status_uxl,io_status_sd_rv32,io_status_zero1,io_status_tsr}; // @[CSR.scala 606:38]
  wire [104:0] _read_mstatus_T = {read_mstatus_hi,read_mstatus_lo}; // @[CSR.scala 606:38]
  wire [31:0] read_mstatus = _read_mstatus_T[31:0]; // @[CSR.scala 606:40]
  wire [6:0] _read_mtvec_T_1 = reg_mtvec[0] ? 7'h7e : 7'h2; // @[CSR.scala 1563:39]
  wire [30:0] _read_mtvec_T_3 = {{24'd0}, _read_mtvec_T_1}; // @[package.scala 165:41]
  wire [30:0] _read_mtvec_T_4 = ~_read_mtvec_T_3; // @[package.scala 165:37]
  wire [30:0] _read_mtvec_T_5 = reg_mtvec & _read_mtvec_T_4; // @[package.scala 165:35]
  wire [31:0] read_mtvec = {1'h0,_read_mtvec_T_5}; // @[Cat.scala 31:58]
  wire [6:0] _read_stvec_T_1 = reg_stvec[0] ? 7'h7e : 7'h2; // @[CSR.scala 1563:39]
  wire [31:0] _read_stvec_T_3 = {{25'd0}, _read_stvec_T_1}; // @[package.scala 165:41]
  wire [31:0] _read_stvec_T_4 = ~_read_stvec_T_3; // @[package.scala 165:37]
  wire [31:0] read_stvec = reg_stvec & _read_stvec_T_4; // @[package.scala 165:35]
  wire  _GEN_5 = reg_tselect ? reg_bp_1_control_x : reg_bp_0_control_x; // @[CSR.scala 612:{48,48}]
  wire  _GEN_7 = reg_tselect ? reg_bp_1_control_w : reg_bp_0_control_w; // @[CSR.scala 612:{48,48}]
  wire  _GEN_9 = reg_tselect ? reg_bp_1_control_r : reg_bp_0_control_r; // @[CSR.scala 612:{48,48}]
  wire  _GEN_11 = reg_tselect ? reg_bp_1_control_s : reg_bp_0_control_s; // @[CSR.scala 612:{48,48}]
  wire  _GEN_13 = reg_tselect ? reg_bp_1_control_u : reg_bp_0_control_u; // @[CSR.scala 612:{48,48}]
  wire  _GEN_15 = reg_tselect ? reg_bp_1_control_m : reg_bp_0_control_m; // @[CSR.scala 612:{48,48}]
  wire [6:0] lo_4 = {_GEN_15,1'h0,_GEN_11,_GEN_13,_GEN_5,_GEN_7,_GEN_9}; // @[CSR.scala 612:48]
  wire [1:0] _GEN_21 = reg_tselect ? reg_bp_1_control_tmatch : reg_bp_0_control_tmatch; // @[CSR.scala 612:{48,48}]
  wire  _GEN_23 = reg_tselect ? reg_bp_1_control_action : reg_bp_0_control_action; // @[CSR.scala 612:{48,48}]
  wire  _GEN_25 = reg_tselect ? 1'h0 : reg_bp_0_control_chain; // @[CSR.scala 612:{48,48}]
  wire  _GEN_33 = reg_tselect ? reg_bp_1_control_dmode : reg_bp_0_control_dmode; // @[CSR.scala 612:{48,48}]
  wire [31:0] _T_16 = {4'h2,_GEN_33,14'h400,_GEN_23,_GEN_25,2'h0,_GEN_21,lo_4}; // @[CSR.scala 612:48]
  wire [31:0] _T_18 = ~reg_mepc; // @[CSR.scala 1562:28]
  wire [1:0] _T_20 = reg_misa[2] ? 2'h1 : 2'h3; // @[CSR.scala 1562:36]
  wire [31:0] _GEN_640 = {{30'd0}, _T_20}; // @[CSR.scala 1562:31]
  wire [31:0] _T_21 = _T_18 | _GEN_640; // @[CSR.scala 1562:31]
  wire [31:0] _T_22 = ~_T_21; // @[CSR.scala 1562:26]
  wire [10:0] lo_6 = {2'h0,reg_dcsr_cause,1'h0,2'h0,reg_dcsr_step,reg_dcsr_prv}; // @[CSR.scala 627:27]
  wire [31:0] _T_23 = {4'h4,12'h0,reg_dcsr_ebreakm,1'h0,reg_dcsr_ebreaks,reg_dcsr_ebreaku,1'h0,lo_6}; // @[CSR.scala 627:27]
  wire [31:0] _T_24 = ~reg_dpc; // @[CSR.scala 1562:28]
  wire [31:0] _T_27 = _T_24 | _GEN_640; // @[CSR.scala 1562:31]
  wire [31:0] _T_28 = ~_T_27; // @[CSR.scala 1562:26]
  wire [31:0] sie_mask = read_mideleg & 32'hefff; // @[CSR.scala 703:18]
  wire [31:0] read_sie = reg_mie & sie_mask; // @[CSR.scala 706:28]
  wire [31:0] read_sip = _GEN_41 & sie_mask; // @[CSR.scala 707:29]
  wire [8:0] lo_lo_6 = {io_status_spp,1'h0,1'h0,io_status_spie,1'h0,2'h0,io_status_sie,1'h0}; // @[CSR.scala 721:57]
  wire [21:0] lo_7 = {2'h0,io_status_mxr,io_status_sum,1'h0,io_status_xs,io_status_fs,2'h0,io_status_vs,lo_lo_6}; // @[CSR.scala 721:57]
  wire [104:0] _T_91 = {37'h0,4'h0,io_status_sd,23'h0,6'h0,io_status_uxl,io_status_sd_rv32,9'h0,lo_7}; // @[CSR.scala 721:57]
  wire [31:0] _T_94 = ~reg_sepc; // @[CSR.scala 1562:28]
  wire [31:0] _T_97 = _T_94 | _GEN_640; // @[CSR.scala 1562:31]
  wire [31:0] _T_98 = ~_T_97; // @[CSR.scala 1562:26]
  wire [7:0] _T_99 = {reg_pmp_0_cfg_l,2'h0,reg_pmp_0_cfg_a,reg_pmp_0_cfg_x,reg_pmp_0_cfg_w,reg_pmp_0_cfg_r}; // @[package.scala 36:38]
  wire [7:0] _T_101 = {reg_pmp_2_cfg_l,2'h0,reg_pmp_2_cfg_a,reg_pmp_2_cfg_x,reg_pmp_2_cfg_w,reg_pmp_2_cfg_r}; // @[package.scala 36:38]
  wire [15:0] lo_12 = {reg_pmp_1_cfg_l,2'h0,reg_pmp_1_cfg_a,reg_pmp_1_cfg_x,reg_pmp_1_cfg_w,reg_pmp_1_cfg_r,_T_99}; // @[Cat.scala 31:58]
  wire [31:0] _T_103 = {reg_pmp_3_cfg_l,2'h0,reg_pmp_3_cfg_a,reg_pmp_3_cfg_x,reg_pmp_3_cfg_w,reg_pmp_3_cfg_r,_T_101,
    lo_12}; // @[Cat.scala 31:58]
  wire [7:0] _T_104 = {reg_pmp_4_cfg_l,2'h0,reg_pmp_4_cfg_a,reg_pmp_4_cfg_x,reg_pmp_4_cfg_w,reg_pmp_4_cfg_r}; // @[package.scala 36:38]
  wire [7:0] _T_106 = {reg_pmp_6_cfg_l,2'h0,reg_pmp_6_cfg_a,reg_pmp_6_cfg_x,reg_pmp_6_cfg_w,reg_pmp_6_cfg_r}; // @[package.scala 36:38]
  wire [15:0] lo_17 = {reg_pmp_5_cfg_l,2'h0,reg_pmp_5_cfg_a,reg_pmp_5_cfg_x,reg_pmp_5_cfg_w,reg_pmp_5_cfg_r,_T_104}; // @[Cat.scala 31:58]
  wire [31:0] _T_108 = {reg_pmp_7_cfg_l,2'h0,reg_pmp_7_cfg_a,reg_pmp_7_cfg_x,reg_pmp_7_cfg_w,reg_pmp_7_cfg_r,_T_106,
    lo_17}; // @[Cat.scala 31:58]
  reg [31:0] reg_custom_0; // @[CSR.scala 750:43]
  wire [12:0] addr = {io_status_v,io_rw_addr}; // @[Cat.scala 31:58]
  wire [12:0] _decoded_T = addr & 13'hc13; // @[Decode.scala 14:65]
  wire  decoded_0 = _decoded_T == 13'h400; // @[Decode.scala 14:121]
  wire [12:0] _decoded_T_2 = addr & 13'hc53; // @[Decode.scala 14:65]
  wire  decoded_1 = _decoded_T_2 == 13'h401; // @[Decode.scala 14:121]
  wire  decoded_2 = _decoded_T == 13'h402; // @[Decode.scala 14:121]
  wire [12:0] _decoded_T_8 = addr & 13'h867; // @[Decode.scala 14:65]
  wire  decoded_4 = _decoded_T_8 == 13'h1; // @[Decode.scala 14:121]
  wire [12:0] _decoded_T_10 = addr & 13'ha67; // @[Decode.scala 14:65]
  wire  decoded_5 = _decoded_T_10 == 13'h200; // @[Decode.scala 14:121]
  wire [12:0] _decoded_T_12 = addr & 13'ha25; // @[Decode.scala 14:65]
  wire  decoded_6 = _decoded_T_12 == 13'h205; // @[Decode.scala 14:121]
  wire [12:0] _decoded_T_14 = addr & 13'h244; // @[Decode.scala 14:65]
  wire  decoded_7 = _decoded_T_14 == 13'h244; // @[Decode.scala 14:121]
  wire  decoded_8 = _decoded_T_10 == 13'h204; // @[Decode.scala 14:121]
  wire [12:0] _decoded_T_18 = addr & 13'h247; // @[Decode.scala 14:65]
  wire  decoded_9 = _decoded_T_18 == 13'h240; // @[Decode.scala 14:121]
  wire [12:0] _decoded_T_20 = addr & 13'h643; // @[Decode.scala 14:65]
  wire  decoded_10 = _decoded_T_20 == 13'h241; // @[Decode.scala 14:121]
  wire [12:0] _decoded_T_22 = addr & 13'h243; // @[Decode.scala 14:65]
  wire  decoded_11 = _decoded_T_22 == 13'h243; // @[Decode.scala 14:121]
  wire  decoded_12 = _decoded_T_22 == 13'h242; // @[Decode.scala 14:121]
  wire [12:0] _decoded_T_26 = addr & 13'h683; // @[Decode.scala 14:65]
  wire  decoded_13 = _decoded_T_26 == 13'h600; // @[Decode.scala 14:121]
  wire  decoded_14 = _decoded_T == 13'h410; // @[Decode.scala 14:121]
  wire [12:0] _decoded_T_30 = addr & 13'hc11; // @[Decode.scala 14:65]
  wire  decoded_15 = _decoded_T_30 == 13'h411; // @[Decode.scala 14:121]
  wire [12:0] _decoded_T_32 = addr & 13'hc12; // @[Decode.scala 14:65]
  wire  decoded_16 = _decoded_T_32 == 13'h412; // @[Decode.scala 14:121]
  wire [12:0] _decoded_T_34 = addr & 13'hbe; // @[Decode.scala 14:65]
  wire  decoded_17 = _decoded_T_34 == 13'h20; // @[Decode.scala 14:121]
  wire [12:0] _decoded_T_36 = addr & 13'hc9e; // @[Decode.scala 14:65]
  wire  decoded_18 = _decoded_T_36 == 13'h800; // @[Decode.scala 14:121]
  wire [12:0] _decoded_T_38 = addr & 13'hc9f; // @[Decode.scala 14:65]
  wire  decoded_19 = _decoded_T_38 == 13'h802; // @[Decode.scala 14:121]
  wire [12:0] _decoded_T_54 = addr & 13'h19f; // @[Decode.scala 14:65]
  wire [12:0] _decoded_T_58 = addr & 13'h29f; // @[Decode.scala 14:65]
  wire [12:0] _decoded_T_82 = addr & 13'h4bf; // @[Decode.scala 14:65]
  wire [12:0] _decoded_T_170 = addr & 13'h89f; // @[Decode.scala 14:65]
  wire [12:0] _decoded_T_330 = addr & 13'ha26; // @[Decode.scala 14:65]
  wire  decoded_165 = _decoded_T_330 == 13'h206; // @[Decode.scala 14:121]
  wire [12:0] _decoded_T_332 = addr & 13'h19e; // @[Decode.scala 14:65]
  wire  decoded_166 = _decoded_T_332 == 13'h0; // @[Decode.scala 14:121]
  wire  decoded_167 = _decoded_T_54 == 13'h2; // @[Decode.scala 14:121]
  wire  decoded_168 = _decoded_T_36 == 13'h880; // @[Decode.scala 14:121]
  wire  decoded_169 = _decoded_T_82 == 13'h82; // @[Decode.scala 14:121]
  wire  decoded_170 = _decoded_T_332 == 13'h80; // @[Decode.scala 14:121]
  wire  decoded_171 = _decoded_T_58 == 13'h82; // @[Decode.scala 14:121]
  wire [12:0] _decoded_T_344 = addr & 13'hac4; // @[Decode.scala 14:65]
  wire  decoded_172 = _decoded_T_344 == 13'h0; // @[Decode.scala 14:121]
  wire  decoded_173 = _decoded_T_14 == 13'h44; // @[Decode.scala 14:121]
  wire [12:0] _decoded_T_348 = addr & 13'ha47; // @[Decode.scala 14:65]
  wire  decoded_174 = _decoded_T_348 == 13'h4; // @[Decode.scala 14:121]
  wire  decoded_175 = _decoded_T_18 == 13'h40; // @[Decode.scala 14:121]
  wire [12:0] _decoded_T_352 = addr & 13'ha07; // @[Decode.scala 14:65]
  wire  decoded_176 = _decoded_T_352 == 13'h2; // @[Decode.scala 14:121]
  wire [12:0] _decoded_T_354 = addr & 13'ha03; // @[Decode.scala 14:65]
  wire  decoded_177 = _decoded_T_354 == 13'h3; // @[Decode.scala 14:121]
  wire  decoded_179 = _decoded_T_352 == 13'h1; // @[Decode.scala 14:121]
  wire [12:0] _decoded_T_360 = addr & 13'ha41; // @[Decode.scala 14:65]
  wire  decoded_180 = _decoded_T_360 == 13'h1; // @[Decode.scala 14:121]
  wire [12:0] _decoded_T_362 = addr & 13'ha42; // @[Decode.scala 14:65]
  wire  decoded_181 = _decoded_T_362 == 13'h2; // @[Decode.scala 14:121]
  wire [12:0] _decoded_T_364 = addr & 13'h863; // @[Decode.scala 14:65]
  wire  decoded_182 = _decoded_T_364 == 13'h3; // @[Decode.scala 14:121]
  wire  decoded_183 = _decoded_T_8 == 13'h2; // @[Decode.scala 14:121]
  wire [12:0] _decoded_T_368 = addr & 13'he93; // @[Decode.scala 14:65]
  wire  decoded_184 = _decoded_T_368 == 13'h280; // @[Decode.scala 14:121]
  wire [12:0] _decoded_T_370 = addr & 13'hc93; // @[Decode.scala 14:65]
  wire  decoded_185 = _decoded_T_370 == 13'h81; // @[Decode.scala 14:121]
  wire  decoded_188 = _decoded_T_38 == 13'h90; // @[Decode.scala 14:121]
  wire  decoded_189 = _decoded_T_38 == 13'h91; // @[Decode.scala 14:121]
  wire  decoded_190 = _decoded_T_38 == 13'h92; // @[Decode.scala 14:121]
  wire  decoded_191 = _decoded_T_170 == 13'h93; // @[Decode.scala 14:121]
  wire [12:0] _decoded_T_384 = addr & 13'h88f; // @[Decode.scala 14:65]
  wire  decoded_192 = _decoded_T_384 == 13'h84; // @[Decode.scala 14:121]
  wire  decoded_193 = _decoded_T_384 == 13'h85; // @[Decode.scala 14:121]
  wire  decoded_194 = _decoded_T_384 == 13'h86; // @[Decode.scala 14:121]
  wire  decoded_195 = _decoded_T_384 == 13'h87; // @[Decode.scala 14:121]
  wire [12:0] _decoded_T_408 = addr & 13'hc20; // @[Decode.scala 14:65]
  wire  decoded_204 = _decoded_T_408 == 13'h400; // @[Decode.scala 14:121]
  wire [12:0] _decoded_T_410 = addr & 13'h685; // @[Decode.scala 14:65]
  wire  decoded_205 = _decoded_T_410 == 13'h600; // @[Decode.scala 14:121]
  wire  decoded_207 = _decoded_T_26 == 13'h603; // @[Decode.scala 14:121]
  wire [31:0] _wdata_T_1 = io_rw_cmd[1] ? io_rw_rdata : 32'h0; // @[CSR.scala 1540:9]
  wire [31:0] _wdata_T_2 = _wdata_T_1 | io_rw_wdata; // @[CSR.scala 1540:34]
  wire [31:0] _wdata_T_5 = &io_rw_cmd[1:0] ? io_rw_wdata : 32'h0; // @[CSR.scala 1540:49]
  wire [31:0] _wdata_T_6 = ~_wdata_T_5; // @[CSR.scala 1540:45]
  wire [31:0] wdata = _wdata_T_2 & _wdata_T_6; // @[CSR.scala 1540:43]
  wire [31:0] _T_337 = _T_327 & 32'h20200000; // @[Decode.scala 14:65]
  wire  _T_338 = _T_337 == 32'h20000000; // @[Decode.scala 14:121]
  wire [31:0] _T_340 = _T_327 & 32'h30200000; // @[Decode.scala 14:65]
  wire  _T_341 = _T_340 == 32'h10000000; // @[Decode.scala 14:121]
  wire  insn_cease = system_insn & _T_338; // @[CSR.scala 829:95]
  wire  insn_wfi = system_insn & _T_341; // @[CSR.scala 829:95]
  wire [11:0] addr_1 = io_decode_0_inst[31:20]; // @[CSR.scala 832:27]
  wire [31:0] _T_358 = io_decode_0_inst & 32'h10400000; // @[Decode.scala 14:65]
  wire  is_ret = _T_358 == 32'h10000000; // @[Decode.scala 14:121]
  wire [31:0] _T_364 = io_decode_0_inst & 32'h30200000; // @[Decode.scala 14:65]
  wire  is_wfi = _T_364 == 32'h10000000; // @[Decode.scala 14:121]
  wire  _is_counter_T_2 = addr_1 >= 12'hc00 & addr_1 < 12'hc20; // @[package.scala 204:55]
  wire  _is_counter_T_5 = addr_1 >= 12'hc80 & addr_1 < 12'hca0; // @[package.scala 204:55]
  wire  is_counter = _is_counter_T_2 | _is_counter_T_5; // @[CSR.scala 839:75]
  wire  _allow_wfi_T = reg_mstatus_prv > 2'h1; // @[CSR.scala 841:63]
  wire  allow_wfi = reg_mstatus_prv > 2'h1 | ~reg_mstatus_tw; // @[CSR.scala 841:71]
  wire  _allow_hfence_vvma_T_1 = reg_mstatus_prv >= 2'h1; // @[CSR.scala 843:90]
  wire  allow_sret = _allow_wfi_T | ~reg_mstatus_tsr; // @[CSR.scala 845:72]
  wire [4:0] counter_addr = addr_1[4:0]; // @[CSR.scala 846:28]
  wire [31:0] _allow_counter_T_1 = read_mcounteren >> counter_addr; // @[CSR.scala 847:68]
  wire [31:0] _allow_counter_T_6 = read_scounteren >> counter_addr; // @[CSR.scala 848:71]
  wire  _allow_counter_T_8 = _allow_hfence_vvma_T_1 | _allow_counter_T_6[0]; // @[CSR.scala 848:53]
  wire  allow_counter = (_allow_wfi_T | _allow_counter_T_1[0]) & _allow_counter_T_8; // @[CSR.scala 847:84]
  wire  csr_addr_legal = reg_mstatus_prv >= addr_1[9:8]; // @[CSR.scala 854:42]
  wire  _csr_exists_T_15 = addr_1 == 12'h7b1; // @[CSR.scala 834:93]
  wire  _csr_exists_T_222 = addr_1 == 12'h7a0 | addr_1 == 12'h7a1 | addr_1 == 12'h7a2 | addr_1 == 12'h7a3 | addr_1 == 12'h301
     | addr_1 == 12'h300 | addr_1 == 12'h305 | addr_1 == 12'h344 | addr_1 == 12'h304 | addr_1 == 12'h340 | addr_1 == 12'h341
     | addr_1 == 12'h343 | addr_1 == 12'h342 | addr_1 == 12'hf14 | addr_1 == 12'h7b0 | _csr_exists_T_15; // @[CSR.scala 834:109]
  wire  _csr_exists_T_237 = _csr_exists_T_222 | addr_1 == 12'h7b2 | addr_1 == 12'h320 | addr_1 == 12'hb00 | addr_1 == 12'hb02
     | addr_1 == 12'h323 | addr_1 == 12'hb03 | addr_1 == 12'hc03 | addr_1 == 12'hb83 | addr_1 == 12'hc83 | addr_1 == 12'h324
     | addr_1 == 12'hb04 | addr_1 == 12'hc04 | addr_1 == 12'hb84 | addr_1 == 12'hc84 | addr_1 == 12'h325; // @[CSR.scala 834:109]
  wire  _csr_exists_T_252 = _csr_exists_T_237 | addr_1 == 12'hb05 | addr_1 == 12'hc05 | addr_1 == 12'hb85 | addr_1 == 12'hc85
     | addr_1 == 12'h326 | addr_1 == 12'hb06 | addr_1 == 12'hc06 | addr_1 == 12'hb86 | addr_1 == 12'hc86 | addr_1 == 12'h327
     | addr_1 == 12'hb07 | addr_1 == 12'hc07 | addr_1 == 12'hb87 | addr_1 == 12'hc87 | addr_1 == 12'h328; // @[CSR.scala 834:109]
  wire  _csr_exists_T_267 = _csr_exists_T_252 | addr_1 == 12'hb08 | addr_1 == 12'hc08 | addr_1 == 12'hb88 | addr_1 == 12'hc88
     | addr_1 == 12'h329 | addr_1 == 12'hb09 | addr_1 == 12'hc09 | addr_1 == 12'hb89 | addr_1 == 12'hc89 | addr_1 == 12'h32a
     | addr_1 == 12'hb0a | addr_1 == 12'hc0a | addr_1 == 12'hb8a | addr_1 == 12'hc8a | addr_1 == 12'h32b; // @[CSR.scala 834:109]
  wire  _csr_exists_T_282 = _csr_exists_T_267 | addr_1 == 12'hb0b | addr_1 == 12'hc0b | addr_1 == 12'hb8b | addr_1 == 12'hc8b
     | addr_1 == 12'h32c | addr_1 == 12'hb0c | addr_1 == 12'hc0c | addr_1 == 12'hb8c | addr_1 == 12'hc8c | addr_1 == 12'h32d
     | addr_1 == 12'hb0d | addr_1 == 12'hc0d | addr_1 == 12'hb8d | addr_1 == 12'hc8d | addr_1 == 12'h32e; // @[CSR.scala 834:109]
  wire  _csr_exists_T_297 = _csr_exists_T_282 | addr_1 == 12'hb0e | addr_1 == 12'hc0e | addr_1 == 12'hb8e | addr_1 == 12'hc8e
     | addr_1 == 12'h32f | addr_1 == 12'hb0f | addr_1 == 12'hc0f | addr_1 == 12'hb8f | addr_1 == 12'hc8f | addr_1 == 12'h330
     | addr_1 == 12'hb10 | addr_1 == 12'hc10 | addr_1 == 12'hb90 | addr_1 == 12'hc90 | addr_1 == 12'h331; // @[CSR.scala 834:109]
  wire  _csr_exists_T_312 = _csr_exists_T_297 | addr_1 == 12'hb11 | addr_1 == 12'hc11 | addr_1 == 12'hb91 | addr_1 == 12'hc91
     | addr_1 == 12'h332 | addr_1 == 12'hb12 | addr_1 == 12'hc12 | addr_1 == 12'hb92 | addr_1 == 12'hc92 | addr_1 == 12'h333
     | addr_1 == 12'hb13 | addr_1 == 12'hc13 | addr_1 == 12'hb93 | addr_1 == 12'hc93 | addr_1 == 12'h334; // @[CSR.scala 834:109]
  wire  _csr_exists_T_327 = _csr_exists_T_312 | addr_1 == 12'hb14 | addr_1 == 12'hc14 | addr_1 == 12'hb94 | addr_1 == 12'hc94
     | addr_1 == 12'h335 | addr_1 == 12'hb15 | addr_1 == 12'hc15 | addr_1 == 12'hb95 | addr_1 == 12'hc95 | addr_1 == 12'h336
     | addr_1 == 12'hb16 | addr_1 == 12'hc16 | addr_1 == 12'hb96 | addr_1 == 12'hc96 | addr_1 == 12'h337; // @[CSR.scala 834:109]
  wire  _csr_exists_T_342 = _csr_exists_T_327 | addr_1 == 12'hb17 | addr_1 == 12'hc17 | addr_1 == 12'hb97 | addr_1 == 12'hc97
     | addr_1 == 12'h338 | addr_1 == 12'hb18 | addr_1 == 12'hc18 | addr_1 == 12'hb98 | addr_1 == 12'hc98 | addr_1 == 12'h339
     | addr_1 == 12'hb19 | addr_1 == 12'hc19 | addr_1 == 12'hb99 | addr_1 == 12'hc99 | addr_1 == 12'h33a; // @[CSR.scala 834:109]
  wire  _csr_exists_T_357 = _csr_exists_T_342 | addr_1 == 12'hb1a | addr_1 == 12'hc1a | addr_1 == 12'hb9a | addr_1 == 12'hc9a
     | addr_1 == 12'h33b | addr_1 == 12'hb1b | addr_1 == 12'hc1b | addr_1 == 12'hb9b | addr_1 == 12'hc9b | addr_1 == 12'h33c
     | addr_1 == 12'hb1c | addr_1 == 12'hc1c | addr_1 == 12'hb9c | addr_1 == 12'hc9c | addr_1 == 12'h33d; // @[CSR.scala 834:109]
  wire  _csr_exists_T_372 = _csr_exists_T_357 | addr_1 == 12'hb1d | addr_1 == 12'hc1d | addr_1 == 12'hb9d | addr_1 == 12'hc9d
     | addr_1 == 12'h33e | addr_1 == 12'hb1e | addr_1 == 12'hc1e | addr_1 == 12'hb9e | addr_1 == 12'hc9e | addr_1 == 12'h33f
     | addr_1 == 12'hb1f | addr_1 == 12'hc1f | addr_1 == 12'hb9f | addr_1 == 12'hc9f | addr_1 == 12'h306; // @[CSR.scala 834:109]
  wire  _csr_exists_T_387 = _csr_exists_T_372 | addr_1 == 12'hc00 | addr_1 == 12'hc02 | addr_1 == 12'hb80 | addr_1 == 12'hb82
     | addr_1 == 12'hc80 | addr_1 == 12'hc82 | addr_1 == 12'h100 | addr_1 == 12'h144 | addr_1 == 12'h104 | addr_1 == 12'h140
     | addr_1 == 12'h142 | addr_1 == 12'h143 | addr_1 == 12'h180 | addr_1 == 12'h141 | addr_1 == 12'h105; // @[CSR.scala 834:109]
  wire  _csr_exists_T_402 = _csr_exists_T_387 | addr_1 == 12'h106 | addr_1 == 12'h303 | addr_1 == 12'h302 | addr_1 == 12'h3a0
     | addr_1 == 12'h3a1 | addr_1 == 12'h3a2 | addr_1 == 12'h3a3 | addr_1 == 12'h3b0 | addr_1 == 12'h3b1 | addr_1 == 12'h3b2
     | addr_1 == 12'h3b3 | addr_1 == 12'h3b4 | addr_1 == 12'h3b5 | addr_1 == 12'h3b6 | addr_1 == 12'h3b7; // @[CSR.scala 834:109]
  wire  csr_exists = _csr_exists_T_402 | addr_1 == 12'h3b8 | addr_1 == 12'h3b9 | addr_1 == 12'h3ba | addr_1 == 12'h3bb
     | addr_1 == 12'h3bc | addr_1 == 12'h3bd | addr_1 == 12'h3be | addr_1 == 12'h3bf | addr_1 == 12'h7c1 | addr_1 == 12'hf12
     | addr_1 == 12'hf11 | addr_1 == 12'hf13; // @[CSR.scala 834:109]
  wire  _io_decode_0_read_illegal_T = ~csr_addr_legal; // @[CSR.scala 857:28]
  wire  _io_decode_0_read_illegal_T_1 = ~csr_exists; // @[CSR.scala 858:7]
  wire  _io_decode_0_read_illegal_T_2 = ~csr_addr_legal | _io_decode_0_read_illegal_T_1; // @[CSR.scala 857:44]
  wire  _io_decode_0_read_illegal_T_10 = is_counter & ~allow_counter; // @[CSR.scala 860:18]
  wire  _io_decode_0_read_illegal_T_11 = _io_decode_0_read_illegal_T_2 | _io_decode_0_read_illegal_T_10; // @[CSR.scala 859:74]
  wire [11:0] _io_decode_0_read_illegal_T_12 = addr_1 & 12'hc10; // @[Decode.scala 14:65]
  wire  _io_decode_0_read_illegal_T_13 = _io_decode_0_read_illegal_T_12 == 12'h410; // @[Decode.scala 14:121]
  wire  _io_decode_0_read_illegal_T_17 = _io_decode_0_read_illegal_T_13 & _T_401; // @[CSR.scala 861:42]
  wire  _io_decode_0_read_illegal_T_18 = _io_decode_0_read_illegal_T_11 | _io_decode_0_read_illegal_T_17; // @[CSR.scala 860:36]
  wire  _io_decode_0_read_illegal_T_21 = io_decode_0_fp_csr & io_decode_0_fp_illegal; // @[CSR.scala 863:21]
  wire [11:0] io_decode_0_write_flush_addr_m = addr_1 | 12'h300; // @[CSR.scala 866:25]
  wire  _io_decode_0_system_illegal_T_4 = is_wfi & ~allow_wfi; // @[CSR.scala 870:14]
  wire  _io_decode_0_system_illegal_T_5 = _io_decode_0_read_illegal_T | _io_decode_0_system_illegal_T_4; // @[CSR.scala 869:58]
  wire  _io_decode_0_system_illegal_T_7 = is_ret & ~allow_sret; // @[CSR.scala 871:14]
  wire  _io_decode_0_system_illegal_T_8 = _io_decode_0_system_illegal_T_5 | _io_decode_0_system_illegal_T_7; // @[CSR.scala 870:28]
  wire  _io_decode_0_system_illegal_T_14 = is_ret & addr_1[10] & addr_1[7] & _T_401; // @[CSR.scala 872:37]
  wire [11:0] _debugTVec_T = insn_break ? 12'h800 : 12'h808; // @[CSR.scala 902:37]
  wire [11:0] debugTVec = reg_debug ? _debugTVec_T : 12'h800; // @[CSR.scala 902:22]
  wire [31:0] notDebugTVec_base = delegate ? read_stvec : read_mtvec; // @[CSR.scala 911:19]
  wire [6:0] notDebugTVec_interruptOffset = {cause[4:0], 2'h0}; // @[CSR.scala 912:59]
  wire [31:0] notDebugTVec_interruptVec = {notDebugTVec_base[31:7],notDebugTVec_interruptOffset}; // @[Cat.scala 31:58]
  wire  notDebugTVec_doVector = notDebugTVec_base[0] & cause[31] & cause_lsbs[7:5] == 3'h0; // @[CSR.scala 914:55]
  wire [31:0] _notDebugTVec_T_1 = {notDebugTVec_base[31:2], 2'h0}; // @[CSR.scala 915:56]
  wire [31:0] notDebugTVec = notDebugTVec_doVector ? notDebugTVec_interruptVec : _notDebugTVec_T_1; // @[CSR.scala 915:8]
  wire [31:0] tvec = trapToDebug ? {{20'd0}, debugTVec} : notDebugTVec; // @[CSR.scala 928:17]
  wire [1:0] _T_369 = insn_ret + insn_call; // @[Bitwise.scala 48:55]
  wire [1:0] _T_371 = insn_break + io_exception; // @[Bitwise.scala 48:55]
  wire [2:0] _T_373 = _T_369 + _T_371; // @[Bitwise.scala 48:55]
  wire  _T_377 = ~reset; // @[CSR.scala 954:9]
  wire  _GEN_46 = insn_wfi & _io_interrupt_T & _T_401 | reg_wfi; // @[CSR.scala 538:50 956:{51,61}]
  wire  _GEN_48 = io_retire | exception | reg_singleStepped; // @[CSR.scala 453:30 960:{36,56}]
  wire [31:0] _epc_T = ~io_pc; // @[CSR.scala 1561:28]
  wire [31:0] _epc_T_1 = _epc_T | 32'h1; // @[CSR.scala 1561:31]
  wire [31:0] epc = ~_epc_T_1; // @[CSR.scala 1561:26]
  wire [1:0] _reg_dcsr_cause_T = causeIsDebugTrigger ? 2'h2 : 2'h1; // @[CSR.scala 973:86]
  wire [1:0] _reg_dcsr_cause_T_1 = causeIsDebugInt ? 2'h3 : _reg_dcsr_cause_T; // @[CSR.scala 973:56]
  wire [2:0] _reg_dcsr_cause_T_2 = reg_singleStepped ? 3'h4 : {{1'd0}, _reg_dcsr_cause_T_1}; // @[CSR.scala 973:30]
  wire  _GEN_51 = ~reg_debug | reg_debug; // @[CSR.scala 969:25 971:19 449:22]
  wire [31:0] _GEN_52 = ~reg_debug ? epc : reg_dpc; // @[CSR.scala 969:25 972:17 450:20]
  wire [1:0] _GEN_54 = ~reg_debug ? reg_mstatus_prv : reg_dcsr_prv; // @[CSR.scala 377:21 969:25 974:22]
  wire [31:0] _GEN_68 = delegate ? epc : reg_sepc; // @[CSR.scala 1002:16 532:21 997:35]
  wire [31:0] _GEN_69 = delegate ? cause : reg_scause; // @[CSR.scala 1003:18 533:23 997:35]
  wire [31:0] _GEN_70 = delegate ? io_tval : reg_stval; // @[CSR.scala 1004:17 534:22 997:35]
  wire  _GEN_72 = delegate ? reg_mstatus_sie : reg_mstatus_spie; // @[CSR.scala 1006:24 369:24 997:35]
  wire [1:0] _GEN_73 = delegate ? reg_mstatus_prv : {{1'd0}, reg_mstatus_spp}; // @[CSR.scala 1007:23 369:24 997:35]
  wire  _GEN_74 = delegate ? 1'h0 : reg_mstatus_sie; // @[CSR.scala 1008:23 369:24 997:35]
  wire [31:0] _GEN_78 = delegate ? reg_mepc : epc; // @[CSR.scala 1014:16 472:21 997:35]
  wire [31:0] _GEN_79 = delegate ? reg_mcause : cause; // @[CSR.scala 1015:18 473:27 997:35]
  wire [31:0] _GEN_80 = delegate ? reg_mtval : io_tval; // @[CSR.scala 1016:17 474:22 997:35]
  wire  _GEN_82 = delegate ? reg_mstatus_mpie : reg_mstatus_mie; // @[CSR.scala 1018:24 369:24 997:35]
  wire [1:0] _GEN_83 = delegate ? reg_mstatus_mpp : reg_mstatus_prv; // @[CSR.scala 1019:23 369:24 997:35]
  wire  _GEN_84 = delegate & reg_mstatus_mie; // @[CSR.scala 1020:23 369:24 997:35]
  wire  _GEN_145 = trapToDebug ? _GEN_51 : reg_debug; // @[CSR.scala 449:22 968:24]
  wire [31:0] _GEN_146 = trapToDebug ? _GEN_52 : reg_dpc; // @[CSR.scala 450:20 968:24]
  wire [1:0] _GEN_148 = trapToDebug ? _GEN_54 : reg_dcsr_prv; // @[CSR.scala 377:21 968:24]
  wire [31:0] _GEN_165 = trapToDebug ? reg_sepc : _GEN_68; // @[CSR.scala 532:21 968:24]
  wire [31:0] _GEN_166 = trapToDebug ? reg_scause : _GEN_69; // @[CSR.scala 533:23 968:24]
  wire [31:0] _GEN_167 = trapToDebug ? reg_stval : _GEN_70; // @[CSR.scala 534:22 968:24]
  wire  _GEN_169 = trapToDebug ? reg_mstatus_spie : _GEN_72; // @[CSR.scala 369:24 968:24]
  wire [1:0] _GEN_170 = trapToDebug ? {{1'd0}, reg_mstatus_spp} : _GEN_73; // @[CSR.scala 369:24 968:24]
  wire  _GEN_171 = trapToDebug ? reg_mstatus_sie : _GEN_74; // @[CSR.scala 369:24 968:24]
  wire [31:0] _GEN_174 = trapToDebug ? reg_mepc : _GEN_78; // @[CSR.scala 472:21 968:24]
  wire [31:0] _GEN_175 = trapToDebug ? reg_mcause : _GEN_79; // @[CSR.scala 968:24 473:27]
  wire [31:0] _GEN_176 = trapToDebug ? reg_mtval : _GEN_80; // @[CSR.scala 474:22 968:24]
  wire  _GEN_178 = trapToDebug ? reg_mstatus_mpie : _GEN_82; // @[CSR.scala 369:24 968:24]
  wire [1:0] _GEN_179 = trapToDebug ? reg_mstatus_mpp : _GEN_83; // @[CSR.scala 369:24 968:24]
  wire  _GEN_180 = trapToDebug ? reg_mstatus_mie : _GEN_84; // @[CSR.scala 369:24 968:24]
  wire  _GEN_182 = exception ? _GEN_145 : reg_debug; // @[CSR.scala 967:20 449:22]
  wire [31:0] _GEN_183 = exception ? _GEN_146 : reg_dpc; // @[CSR.scala 450:20 967:20]
  wire [1:0] _GEN_185 = exception ? _GEN_148 : reg_dcsr_prv; // @[CSR.scala 967:20 377:21]
  wire [31:0] _GEN_202 = exception ? _GEN_165 : reg_sepc; // @[CSR.scala 967:20 532:21]
  wire [31:0] _GEN_203 = exception ? _GEN_166 : reg_scause; // @[CSR.scala 967:20 533:23]
  wire [31:0] _GEN_204 = exception ? _GEN_167 : reg_stval; // @[CSR.scala 967:20 534:22]
  wire  _GEN_206 = exception ? _GEN_169 : reg_mstatus_spie; // @[CSR.scala 967:20 369:24]
  wire [1:0] _GEN_207 = exception ? _GEN_170 : {{1'd0}, reg_mstatus_spp}; // @[CSR.scala 967:20 369:24]
  wire  _GEN_208 = exception ? _GEN_171 : reg_mstatus_sie; // @[CSR.scala 967:20 369:24]
  wire [31:0] _GEN_211 = exception ? _GEN_174 : reg_mepc; // @[CSR.scala 967:20 472:21]
  wire [31:0] _GEN_212 = exception ? _GEN_175 : reg_mcause; // @[CSR.scala 967:20 473:27]
  wire [31:0] _GEN_213 = exception ? _GEN_176 : reg_mtval; // @[CSR.scala 967:20 474:22]
  wire  _GEN_215 = exception ? _GEN_178 : reg_mstatus_mpie; // @[CSR.scala 967:20 369:24]
  wire [1:0] _GEN_216 = exception ? _GEN_179 : reg_mstatus_mpp; // @[CSR.scala 967:20 369:24]
  wire  _GEN_217 = exception ? _GEN_180 : reg_mstatus_mie; // @[CSR.scala 967:20 369:24]
  wire [31:0] _GEN_239 = io_rw_addr[10] & io_rw_addr[7] ? _T_28 : _T_22; // @[CSR.scala 1064:70 1068:15]
  wire  _GEN_241 = io_rw_addr[10] & io_rw_addr[7] ? _GEN_217 : reg_mstatus_mpie; // @[CSR.scala 1064:70]
  wire  _GEN_242 = io_rw_addr[10] & io_rw_addr[7] ? _GEN_215 : 1'h1; // @[CSR.scala 1064:70]
  wire [1:0] _GEN_243 = io_rw_addr[10] & io_rw_addr[7] ? _GEN_216 : 2'h0; // @[CSR.scala 1064:70]
  wire  _GEN_245 = ~io_rw_addr[9] ? reg_mstatus_spie : _GEN_208; // @[CSR.scala 1047:52]
  wire  _GEN_246 = ~io_rw_addr[9] | _GEN_206; // @[CSR.scala 1047:52]
  wire [1:0] _GEN_247 = ~io_rw_addr[9] ? 2'h0 : _GEN_207; // @[CSR.scala 1047:52]
  wire [31:0] _GEN_250 = ~io_rw_addr[9] ? _T_98 : _GEN_239; // @[CSR.scala 1047:52]
  wire  _GEN_257 = ~io_rw_addr[9] ? _GEN_217 : _GEN_241; // @[CSR.scala 1047:52]
  wire  _GEN_258 = ~io_rw_addr[9] ? _GEN_215 : _GEN_242; // @[CSR.scala 1047:52]
  wire [1:0] _GEN_259 = ~io_rw_addr[9] ? _GEN_216 : _GEN_243; // @[CSR.scala 1047:52]
  wire  _GEN_261 = ret_prv <= 2'h1 ? 1'h0 : reg_mstatus_mprv; // @[CSR.scala 1085:42 1086:24 369:24]
  wire  _GEN_262 = insn_ret ? _GEN_245 : _GEN_208; // @[CSR.scala 1045:19]
  wire  _GEN_263 = insn_ret ? _GEN_246 : _GEN_206; // @[CSR.scala 1045:19]
  wire [1:0] _GEN_264 = insn_ret ? _GEN_247 : _GEN_207; // @[CSR.scala 1045:19]
  wire  _GEN_273 = insn_ret ? _GEN_257 : _GEN_217; // @[CSR.scala 1045:19]
  wire  _GEN_274 = insn_ret ? _GEN_258 : _GEN_215; // @[CSR.scala 1045:19]
  wire [1:0] _GEN_275 = insn_ret ? _GEN_259 : _GEN_216; // @[CSR.scala 1045:19]
  wire  _GEN_278 = insn_ret ? _GEN_261 : reg_mstatus_mprv; // @[CSR.scala 1045:19 369:24]
  reg  io_status_cease_r; // @[Reg.scala 28:20]
  wire  _GEN_279 = insn_cease | io_status_cease_r; // @[Reg.scala 29:18 28:20 29:22]
  wire  _io_rw_rdata_T = decoded_0 & reg_tselect; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_1 = decoded_1 ? _T_16 : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _GEN_281 = reg_tselect ? reg_bp_1_address : reg_bp_0_address; // @[Mux.scala 27:{73,73}]
  wire [31:0] _io_rw_rdata_T_2 = decoded_2 ? _GEN_281 : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_4 = decoded_4 ? reg_misa : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_5 = decoded_5 ? read_mstatus : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_6 = decoded_6 ? read_mtvec : 32'h0; // @[Mux.scala 27:73]
  wire [15:0] _io_rw_rdata_T_7 = decoded_7 ? read_mip : 16'h0; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_8 = decoded_8 ? reg_mie : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_9 = decoded_9 ? reg_mscratch : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_10 = decoded_10 ? _T_22 : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_11 = decoded_11 ? reg_mtval : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_12 = decoded_12 ? reg_mcause : 32'h0; // @[Mux.scala 27:73]
  wire  _io_rw_rdata_T_13 = decoded_13 & io_hartid; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_14 = decoded_14 ? _T_23 : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_15 = decoded_15 ? _T_28 : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_16 = decoded_16 ? reg_dscratch : 32'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_rw_rdata_T_17 = decoded_17 ? reg_mcountinhibit : 3'h0; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_18 = decoded_18 ? value_1 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_19 = decoded_19 ? value : 64'h0; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_165 = decoded_165 ? read_mcounteren : 32'h0; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_166 = decoded_166 ? value_1 : 64'h0; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_167 = decoded_167 ? value : 64'h0; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_168 = decoded_168 ? value_1[63:32] : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_169 = decoded_169 ? value[63:32] : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_170 = decoded_170 ? value_1[63:32] : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_171 = decoded_171 ? value[63:32] : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_172 = decoded_172 ? _T_91[31:0] : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_173 = decoded_173 ? read_sip : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_174 = decoded_174 ? read_sie : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_175 = decoded_175 ? reg_sscratch : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_176 = decoded_176 ? reg_scause : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_177 = decoded_177 ? reg_stval : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_179 = decoded_179 ? _T_98 : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_180 = decoded_180 ? read_stvec : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_181 = decoded_181 ? read_scounteren : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_182 = decoded_182 ? read_mideleg : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_183 = decoded_183 ? read_medeleg : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_184 = decoded_184 ? _T_103 : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_185 = decoded_185 ? _T_108 : 32'h0; // @[Mux.scala 27:73]
  wire [28:0] _io_rw_rdata_T_188 = decoded_188 ? reg_pmp_0_addr : 29'h0; // @[Mux.scala 27:73]
  wire [28:0] _io_rw_rdata_T_189 = decoded_189 ? reg_pmp_1_addr : 29'h0; // @[Mux.scala 27:73]
  wire [28:0] _io_rw_rdata_T_190 = decoded_190 ? reg_pmp_2_addr : 29'h0; // @[Mux.scala 27:73]
  wire [28:0] _io_rw_rdata_T_191 = decoded_191 ? reg_pmp_3_addr : 29'h0; // @[Mux.scala 27:73]
  wire [28:0] _io_rw_rdata_T_192 = decoded_192 ? reg_pmp_4_addr : 29'h0; // @[Mux.scala 27:73]
  wire [28:0] _io_rw_rdata_T_193 = decoded_193 ? reg_pmp_5_addr : 29'h0; // @[Mux.scala 27:73]
  wire [28:0] _io_rw_rdata_T_194 = decoded_194 ? reg_pmp_6_addr : 29'h0; // @[Mux.scala 27:73]
  wire [28:0] _io_rw_rdata_T_195 = decoded_195 ? reg_pmp_7_addr : 29'h0; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_204 = decoded_204 ? reg_custom_0 : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_205 = decoded_205 ? 32'h1 : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_207 = decoded_207 ? 32'h20181004 : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _GEN_648 = {{31'd0}, _io_rw_rdata_T}; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_208 = _GEN_648 | _io_rw_rdata_T_1; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_209 = _io_rw_rdata_T_208 | _io_rw_rdata_T_2; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_211 = _io_rw_rdata_T_209 | _io_rw_rdata_T_4; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_212 = _io_rw_rdata_T_211 | _io_rw_rdata_T_5; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_213 = _io_rw_rdata_T_212 | _io_rw_rdata_T_6; // @[Mux.scala 27:73]
  wire [31:0] _GEN_649 = {{16'd0}, _io_rw_rdata_T_7}; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_214 = _io_rw_rdata_T_213 | _GEN_649; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_215 = _io_rw_rdata_T_214 | _io_rw_rdata_T_8; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_216 = _io_rw_rdata_T_215 | _io_rw_rdata_T_9; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_217 = _io_rw_rdata_T_216 | _io_rw_rdata_T_10; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_218 = _io_rw_rdata_T_217 | _io_rw_rdata_T_11; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_219 = _io_rw_rdata_T_218 | _io_rw_rdata_T_12; // @[Mux.scala 27:73]
  wire [31:0] _GEN_650 = {{31'd0}, _io_rw_rdata_T_13}; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_220 = _io_rw_rdata_T_219 | _GEN_650; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_221 = _io_rw_rdata_T_220 | _io_rw_rdata_T_14; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_222 = _io_rw_rdata_T_221 | _io_rw_rdata_T_15; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_223 = _io_rw_rdata_T_222 | _io_rw_rdata_T_16; // @[Mux.scala 27:73]
  wire [31:0] _GEN_651 = {{29'd0}, _io_rw_rdata_T_17}; // @[Mux.scala 27:73]
  wire [31:0] _io_rw_rdata_T_224 = _io_rw_rdata_T_223 | _GEN_651; // @[Mux.scala 27:73]
  wire [63:0] _GEN_652 = {{32'd0}, _io_rw_rdata_T_224}; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_225 = _GEN_652 | _io_rw_rdata_T_18; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_226 = _io_rw_rdata_T_225 | _io_rw_rdata_T_19; // @[Mux.scala 27:73]
  wire [63:0] _GEN_653 = {{32'd0}, _io_rw_rdata_T_165}; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_372 = _io_rw_rdata_T_226 | _GEN_653; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_373 = _io_rw_rdata_T_372 | _io_rw_rdata_T_166; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_374 = _io_rw_rdata_T_373 | _io_rw_rdata_T_167; // @[Mux.scala 27:73]
  wire [63:0] _GEN_654 = {{32'd0}, _io_rw_rdata_T_168}; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_375 = _io_rw_rdata_T_374 | _GEN_654; // @[Mux.scala 27:73]
  wire [63:0] _GEN_655 = {{32'd0}, _io_rw_rdata_T_169}; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_376 = _io_rw_rdata_T_375 | _GEN_655; // @[Mux.scala 27:73]
  wire [63:0] _GEN_656 = {{32'd0}, _io_rw_rdata_T_170}; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_377 = _io_rw_rdata_T_376 | _GEN_656; // @[Mux.scala 27:73]
  wire [63:0] _GEN_657 = {{32'd0}, _io_rw_rdata_T_171}; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_378 = _io_rw_rdata_T_377 | _GEN_657; // @[Mux.scala 27:73]
  wire [63:0] _GEN_658 = {{32'd0}, _io_rw_rdata_T_172}; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_379 = _io_rw_rdata_T_378 | _GEN_658; // @[Mux.scala 27:73]
  wire [63:0] _GEN_659 = {{32'd0}, _io_rw_rdata_T_173}; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_380 = _io_rw_rdata_T_379 | _GEN_659; // @[Mux.scala 27:73]
  wire [63:0] _GEN_660 = {{32'd0}, _io_rw_rdata_T_174}; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_381 = _io_rw_rdata_T_380 | _GEN_660; // @[Mux.scala 27:73]
  wire [63:0] _GEN_661 = {{32'd0}, _io_rw_rdata_T_175}; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_382 = _io_rw_rdata_T_381 | _GEN_661; // @[Mux.scala 27:73]
  wire [63:0] _GEN_662 = {{32'd0}, _io_rw_rdata_T_176}; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_383 = _io_rw_rdata_T_382 | _GEN_662; // @[Mux.scala 27:73]
  wire [63:0] _GEN_663 = {{32'd0}, _io_rw_rdata_T_177}; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_384 = _io_rw_rdata_T_383 | _GEN_663; // @[Mux.scala 27:73]
  wire [63:0] _GEN_664 = {{32'd0}, _io_rw_rdata_T_179}; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_386 = _io_rw_rdata_T_384 | _GEN_664; // @[Mux.scala 27:73]
  wire [63:0] _GEN_665 = {{32'd0}, _io_rw_rdata_T_180}; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_387 = _io_rw_rdata_T_386 | _GEN_665; // @[Mux.scala 27:73]
  wire [63:0] _GEN_666 = {{32'd0}, _io_rw_rdata_T_181}; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_388 = _io_rw_rdata_T_387 | _GEN_666; // @[Mux.scala 27:73]
  wire [63:0] _GEN_667 = {{32'd0}, _io_rw_rdata_T_182}; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_389 = _io_rw_rdata_T_388 | _GEN_667; // @[Mux.scala 27:73]
  wire [63:0] _GEN_668 = {{32'd0}, _io_rw_rdata_T_183}; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_390 = _io_rw_rdata_T_389 | _GEN_668; // @[Mux.scala 27:73]
  wire [63:0] _GEN_669 = {{32'd0}, _io_rw_rdata_T_184}; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_391 = _io_rw_rdata_T_390 | _GEN_669; // @[Mux.scala 27:73]
  wire [63:0] _GEN_670 = {{32'd0}, _io_rw_rdata_T_185}; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_392 = _io_rw_rdata_T_391 | _GEN_670; // @[Mux.scala 27:73]
  wire [63:0] _GEN_671 = {{35'd0}, _io_rw_rdata_T_188}; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_395 = _io_rw_rdata_T_392 | _GEN_671; // @[Mux.scala 27:73]
  wire [63:0] _GEN_672 = {{35'd0}, _io_rw_rdata_T_189}; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_396 = _io_rw_rdata_T_395 | _GEN_672; // @[Mux.scala 27:73]
  wire [63:0] _GEN_673 = {{35'd0}, _io_rw_rdata_T_190}; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_397 = _io_rw_rdata_T_396 | _GEN_673; // @[Mux.scala 27:73]
  wire [63:0] _GEN_674 = {{35'd0}, _io_rw_rdata_T_191}; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_398 = _io_rw_rdata_T_397 | _GEN_674; // @[Mux.scala 27:73]
  wire [63:0] _GEN_675 = {{35'd0}, _io_rw_rdata_T_192}; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_399 = _io_rw_rdata_T_398 | _GEN_675; // @[Mux.scala 27:73]
  wire [63:0] _GEN_676 = {{35'd0}, _io_rw_rdata_T_193}; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_400 = _io_rw_rdata_T_399 | _GEN_676; // @[Mux.scala 27:73]
  wire [63:0] _GEN_677 = {{35'd0}, _io_rw_rdata_T_194}; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_401 = _io_rw_rdata_T_400 | _GEN_677; // @[Mux.scala 27:73]
  wire [63:0] _GEN_678 = {{35'd0}, _io_rw_rdata_T_195}; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_402 = _io_rw_rdata_T_401 | _GEN_678; // @[Mux.scala 27:73]
  wire [63:0] _GEN_679 = {{32'd0}, _io_rw_rdata_T_204}; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_411 = _io_rw_rdata_T_402 | _GEN_679; // @[Mux.scala 27:73]
  wire [63:0] _GEN_680 = {{32'd0}, _io_rw_rdata_T_205}; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_412 = _io_rw_rdata_T_411 | _GEN_680; // @[Mux.scala 27:73]
  wire [63:0] _GEN_681 = {{32'd0}, _io_rw_rdata_T_207}; // @[Mux.scala 27:73]
  wire [63:0] _io_rw_rdata_T_414 = _io_rw_rdata_T_412 | _GEN_681; // @[Mux.scala 27:73]
  wire  _T_529 = io_rw_cmd == 3'h5; // @[package.scala 15:47]
  wire  _T_530 = io_rw_cmd == 3'h6; // @[package.scala 15:47]
  wire  _T_531 = io_rw_cmd == 3'h7; // @[package.scala 15:47]
  wire  csr_wen = _T_530 | _T_531 | _T_529; // @[package.scala 72:59]
  wire [104:0] _new_mstatus_WIRE = {{73'd0}, wdata};
  wire  new_mstatus_sie = _new_mstatus_WIRE[1]; // @[CSR.scala 1153:47]
  wire  new_mstatus_mie = _new_mstatus_WIRE[3]; // @[CSR.scala 1153:47]
  wire  new_mstatus_spie = _new_mstatus_WIRE[5]; // @[CSR.scala 1153:47]
  wire  new_mstatus_mpie = _new_mstatus_WIRE[7]; // @[CSR.scala 1153:47]
  wire  new_mstatus_spp = _new_mstatus_WIRE[8]; // @[CSR.scala 1153:47]
  wire [1:0] new_mstatus_mpp = _new_mstatus_WIRE[12:11]; // @[CSR.scala 1153:47]
  wire [1:0] new_mstatus_fs = _new_mstatus_WIRE[14:13]; // @[CSR.scala 1153:47]
  wire  new_mstatus_mprv = _new_mstatus_WIRE[17]; // @[CSR.scala 1153:47]
  wire  new_mstatus_tw = _new_mstatus_WIRE[21]; // @[CSR.scala 1153:47]
  wire  new_mstatus_tsr = _new_mstatus_WIRE[22]; // @[CSR.scala 1153:47]
  wire  _reg_mstatus_fs_T = |new_mstatus_fs; // @[CSR.scala 1565:73]
  wire [1:0] _reg_mstatus_fs_T_2 = _reg_mstatus_fs_T ? 2'h3 : 2'h0; // @[Bitwise.scala 74:12]
  wire [1:0] _GEN_288 = decoded_5 ? {{1'd0}, new_mstatus_spp} : _GEN_264; // @[CSR.scala 1152:39 1161:27]
  wire  f = wdata[5]; // @[CSR.scala 1183:20]
  wire [31:0] _reg_misa_T = ~wdata; // @[CSR.scala 1187:25]
  wire  _reg_misa_T_1 = ~f; // @[CSR.scala 1187:35]
  wire [3:0] _reg_misa_T_2 = {_reg_misa_T_1, 3'h0}; // @[CSR.scala 1187:38]
  wire [31:0] _GEN_682 = {{28'd0}, _reg_misa_T_2}; // @[CSR.scala 1187:32]
  wire [31:0] _reg_misa_T_3 = _reg_misa_T | _GEN_682; // @[CSR.scala 1187:32]
  wire [31:0] _reg_misa_T_4 = ~_reg_misa_T_3; // @[CSR.scala 1187:23]
  wire [31:0] _reg_misa_T_5 = _reg_misa_T_4 & 32'h1005; // @[CSR.scala 1187:55]
  wire [31:0] _reg_misa_T_7 = reg_misa & 32'hffffeffa; // @[CSR.scala 1187:73]
  wire [31:0] _reg_misa_T_8 = _reg_misa_T_5 | _reg_misa_T_7; // @[CSR.scala 1187:62]
  wire [15:0] _new_mip_T_2 = io_rw_cmd[1] ? _read_hvip_T : 16'h0; // @[CSR.scala 1540:9]
  wire [31:0] _GEN_683 = {{16'd0}, _new_mip_T_2}; // @[CSR.scala 1540:34]
  wire [31:0] _new_mip_T_3 = _GEN_683 | io_rw_wdata; // @[CSR.scala 1540:34]
  wire [31:0] _new_mip_T_8 = _new_mip_T_3 & _wdata_T_6; // @[CSR.scala 1540:43]
  wire  new_mip_ssip = _new_mip_T_8[1]; // @[CSR.scala 1195:88]
  wire  new_mip_stip = _new_mip_T_8[5]; // @[CSR.scala 1195:88]
  wire  new_mip_seip = _new_mip_T_8[9]; // @[CSR.scala 1195:88]
  wire [31:0] _reg_mie_T = wdata & 32'haaa; // @[CSR.scala 1205:59]
  wire [31:0] _reg_mepc_T_1 = _reg_misa_T | 32'h1; // @[CSR.scala 1561:31]
  wire [31:0] _reg_mepc_T_2 = ~_reg_mepc_T_1; // @[CSR.scala 1561:26]
  wire [31:0] _GEN_303 = decoded_6 ? wdata : {{1'd0}, reg_mtvec}; // @[CSR.scala 1209:{40,52} 479:27]
  wire [31:0] _reg_mcause_T = wdata & 32'h8000000f; // @[CSR.scala 1210:62]
  wire [31:0] _reg_mcountinhibit_T_1 = wdata & 32'hfffffffd; // @[CSR.scala 1230:76]
  wire [31:0] _GEN_306 = decoded_17 ? _reg_mcountinhibit_T_1 : {{29'd0}, reg_mcountinhibit}; // @[CSR.scala 1230:{47,67} 547:34]
  wire [63:0] _T_2681 = {value_1[63:32],wdata}; // @[Cat.scala 31:58]
  wire [63:0] _GEN_307 = decoded_18 ? _T_2681 : {{57'd0}, _GEN_2}; // @[CSR.scala 1555:31 Counters.scala 65:11]
  wire [63:0] _T_2684 = {wdata,value_1[31:0]}; // @[Cat.scala 31:58]
  wire [63:0] _GEN_309 = decoded_168 ? _T_2684 : _GEN_307; // @[CSR.scala 1556:31 Counters.scala 65:11]
  wire [63:0] _T_2686 = {value[63:32],wdata}; // @[Cat.scala 31:58]
  wire [63:0] _GEN_311 = decoded_19 ? _T_2686 : {{57'd0}, _GEN_0}; // @[CSR.scala 1555:31 Counters.scala 65:11]
  wire [63:0] _T_2689 = {wdata,value[31:0]}; // @[Cat.scala 31:58]
  wire [63:0] _GEN_313 = decoded_169 ? _T_2689 : _GEN_311; // @[CSR.scala 1556:31 Counters.scala 65:11]
  wire [1:0] new_dcsr_prv = wdata[1:0]; // @[CSR.scala 1246:43]
  wire  new_dcsr_ebreaku = wdata[12]; // @[CSR.scala 1246:43]
  wire  new_dcsr_ebreaks = wdata[13]; // @[CSR.scala 1246:43]
  wire  new_dcsr_ebreakm = wdata[15]; // @[CSR.scala 1246:43]
  wire [1:0] _GEN_324 = decoded_172 ? {{1'd0}, new_mstatus_spp} : _GEN_288; // @[CSR.scala 1261:41 1265:25]
  wire [31:0] _new_sip_T = ~read_mideleg; // @[CSR.scala 1274:54]
  wire [31:0] _new_sip_T_1 = _GEN_41 & _new_sip_T; // @[CSR.scala 1274:52]
  wire [31:0] _new_sip_T_2 = wdata & read_mideleg; // @[CSR.scala 1274:78]
  wire [31:0] _new_sip_T_3 = _new_sip_T_1 | _new_sip_T_2; // @[CSR.scala 1274:69]
  wire  new_sip_ssip = _new_sip_T_3[1]; // @[CSR.scala 1274:41]
  wire [31:0] _reg_mie_T_1 = ~sie_mask; // @[CSR.scala 1287:66]
  wire [31:0] _reg_mie_T_2 = reg_mie & _reg_mie_T_1; // @[CSR.scala 1287:64]
  wire [31:0] _reg_mie_T_3 = wdata & sie_mask; // @[CSR.scala 1287:86]
  wire [31:0] _reg_mie_T_4 = _reg_mie_T_2 | _reg_mie_T_3; // @[CSR.scala 1287:77]
  wire [31:0] _reg_scause_T = wdata & 32'h8000001f; // @[CSR.scala 1291:64]
  wire [31:0] _GEN_338 = decoded_0 ? wdata : {{31'd0}, reg_tselect}; // @[CSR.scala 1373:{41,55} 458:24]
  wire [6:0] newBPC_lo = {reg_bp_0_control_m,1'h0,reg_bp_0_control_s,reg_bp_0_control_u,reg_bp_0_control_x,
    reg_bp_0_control_w,reg_bp_0_control_r}; // @[CSR.scala 1395:67]
  wire [31:0] _newBPC_T = {4'h2,reg_bp_0_control_dmode,14'h400,reg_bp_0_control_action,reg_bp_0_control_chain,2'h0,
    reg_bp_0_control_tmatch,newBPC_lo}; // @[CSR.scala 1395:67]
  wire [31:0] _newBPC_T_2 = io_rw_cmd[1] ? _newBPC_T : 32'h0; // @[CSR.scala 1540:9]
  wire [31:0] _newBPC_T_3 = _newBPC_T_2 | io_rw_wdata; // @[CSR.scala 1540:34]
  wire [31:0] _newBPC_T_8 = _newBPC_T_3 & _wdata_T_6; // @[CSR.scala 1540:43]
  wire  newBPC_chain = _newBPC_T_8[11]; // @[CSR.scala 1395:96]
  wire  newBPC_action = _newBPC_T_8[12]; // @[CSR.scala 1395:96]
  wire  newBPC_dmode = _newBPC_T_8[27]; // @[CSR.scala 1395:96]
  wire  dMode = newBPC_dmode & reg_debug; // @[CSR.scala 1396:38]
  wire  _GEN_340 = dMode & newBPC_action; // @[CSR.scala 1398:{120,51,71}]
  wire  _reg_bp_0_control_chain_T_3 = ~reg_bp_1_control_dmode; // @[CSR.scala 1399:88]
  wire [6:0] newBPC_lo_1 = {reg_bp_1_control_m,1'h0,reg_bp_1_control_s,reg_bp_1_control_u,reg_bp_1_control_x,
    reg_bp_1_control_w,reg_bp_1_control_r}; // @[CSR.scala 1395:67]
  wire [31:0] _newBPC_T_24 = {4'h2,reg_bp_1_control_dmode,14'h400,reg_bp_1_control_action,1'h0,2'h0,
    reg_bp_1_control_tmatch,newBPC_lo_1}; // @[CSR.scala 1395:67]
  wire [31:0] _newBPC_T_26 = io_rw_cmd[1] ? _newBPC_T_24 : 32'h0; // @[CSR.scala 1540:9]
  wire [31:0] _newBPC_T_27 = _newBPC_T_26 | io_rw_wdata; // @[CSR.scala 1540:34]
  wire [31:0] _newBPC_T_32 = _newBPC_T_27 & _wdata_T_6; // @[CSR.scala 1540:43]
  wire  newBPC_1_action = _newBPC_T_32[12]; // @[CSR.scala 1395:96]
  wire  newBPC_1_dmode = _newBPC_T_32[27]; // @[CSR.scala 1395:96]
  wire  dMode_1 = newBPC_1_dmode & reg_debug & (reg_bp_0_control_dmode | ~reg_bp_0_control_chain); // @[CSR.scala 1396:51]
  wire  _GEN_373 = dMode_1 & newBPC_1_action; // @[CSR.scala 1398:{120,51,71}]
  wire  newCfg_r = wdata[0]; // @[CSR.scala 1409:46]
  wire  newCfg_w = wdata[1]; // @[CSR.scala 1409:46]
  wire  newCfg_x = wdata[2]; // @[CSR.scala 1409:46]
  wire [1:0] newCfg_a = wdata[4:3]; // @[CSR.scala 1409:46]
  wire  newCfg_l = wdata[7]; // @[CSR.scala 1409:46]
  wire  _T_2707 = ~reg_pmp_1_cfg_a[1] & reg_pmp_1_cfg_a[0]; // @[PMP.scala 48:20]
  wire  _T_2709 = reg_pmp_0_cfg_l | reg_pmp_1_cfg_l & _T_2707; // @[PMP.scala 50:44]
  wire [31:0] _GEN_411 = decoded_188 & ~_T_2709 ? wdata : {{3'd0}, reg_pmp_0_addr}; // @[CSR.scala 1417:71 1418:18 460:20]
  wire  newCfg_1_r = wdata[8]; // @[CSR.scala 1409:46]
  wire  newCfg_1_w = wdata[9]; // @[CSR.scala 1409:46]
  wire  newCfg_1_x = wdata[10]; // @[CSR.scala 1409:46]
  wire [1:0] newCfg_1_a = wdata[12:11]; // @[CSR.scala 1409:46]
  wire  newCfg_1_l = wdata[15]; // @[CSR.scala 1409:46]
  wire  _T_2717 = ~reg_pmp_2_cfg_a[1] & reg_pmp_2_cfg_a[0]; // @[PMP.scala 48:20]
  wire  _T_2719 = reg_pmp_1_cfg_l | reg_pmp_2_cfg_l & _T_2717; // @[PMP.scala 50:44]
  wire [31:0] _GEN_418 = decoded_189 & ~_T_2719 ? wdata : {{3'd0}, reg_pmp_1_addr}; // @[CSR.scala 1417:71 1418:18 460:20]
  wire  newCfg_2_r = wdata[16]; // @[CSR.scala 1409:46]
  wire  newCfg_2_w = wdata[17]; // @[CSR.scala 1409:46]
  wire  newCfg_2_x = wdata[18]; // @[CSR.scala 1409:46]
  wire [1:0] newCfg_2_a = wdata[20:19]; // @[CSR.scala 1409:46]
  wire  newCfg_2_l = wdata[23]; // @[CSR.scala 1409:46]
  wire  _T_2727 = ~reg_pmp_3_cfg_a[1] & reg_pmp_3_cfg_a[0]; // @[PMP.scala 48:20]
  wire  _T_2729 = reg_pmp_2_cfg_l | reg_pmp_3_cfg_l & _T_2727; // @[PMP.scala 50:44]
  wire [31:0] _GEN_425 = decoded_190 & ~_T_2729 ? wdata : {{3'd0}, reg_pmp_2_addr}; // @[CSR.scala 1417:71 1418:18 460:20]
  wire  newCfg_3_r = wdata[24]; // @[CSR.scala 1409:46]
  wire  newCfg_3_w = wdata[25]; // @[CSR.scala 1409:46]
  wire  newCfg_3_x = wdata[26]; // @[CSR.scala 1409:46]
  wire [1:0] newCfg_3_a = wdata[28:27]; // @[CSR.scala 1409:46]
  wire  newCfg_3_l = wdata[31]; // @[CSR.scala 1409:46]
  wire  _T_2737 = ~reg_pmp_4_cfg_a[1] & reg_pmp_4_cfg_a[0]; // @[PMP.scala 48:20]
  wire  _T_2739 = reg_pmp_3_cfg_l | reg_pmp_4_cfg_l & _T_2737; // @[PMP.scala 50:44]
  wire [31:0] _GEN_432 = decoded_191 & ~_T_2739 ? wdata : {{3'd0}, reg_pmp_3_addr}; // @[CSR.scala 1417:71 1418:18 460:20]
  wire  _T_2747 = ~reg_pmp_5_cfg_a[1] & reg_pmp_5_cfg_a[0]; // @[PMP.scala 48:20]
  wire  _T_2749 = reg_pmp_4_cfg_l | reg_pmp_5_cfg_l & _T_2747; // @[PMP.scala 50:44]
  wire [31:0] _GEN_439 = decoded_192 & ~_T_2749 ? wdata : {{3'd0}, reg_pmp_4_addr}; // @[CSR.scala 1417:71 1418:18 460:20]
  wire  _T_2757 = ~reg_pmp_6_cfg_a[1] & reg_pmp_6_cfg_a[0]; // @[PMP.scala 48:20]
  wire  _T_2759 = reg_pmp_5_cfg_l | reg_pmp_6_cfg_l & _T_2757; // @[PMP.scala 50:44]
  wire [31:0] _GEN_446 = decoded_193 & ~_T_2759 ? wdata : {{3'd0}, reg_pmp_5_addr}; // @[CSR.scala 1417:71 1418:18 460:20]
  wire  _T_2767 = ~reg_pmp_7_cfg_a[1] & reg_pmp_7_cfg_a[0]; // @[PMP.scala 48:20]
  wire  _T_2769 = reg_pmp_6_cfg_l | reg_pmp_7_cfg_l & _T_2767; // @[PMP.scala 50:44]
  wire [31:0] _GEN_453 = decoded_194 & ~_T_2769 ? wdata : {{3'd0}, reg_pmp_6_addr}; // @[CSR.scala 1417:71 1418:18 460:20]
  wire  _T_2779 = reg_pmp_7_cfg_l | reg_pmp_7_cfg_l & _T_2767; // @[PMP.scala 50:44]
  wire [31:0] _GEN_460 = decoded_195 & ~_T_2779 ? wdata : {{3'd0}, reg_pmp_7_addr}; // @[CSR.scala 1417:71 1418:18 460:20]
  wire [31:0] _reg_custom_0_T = wdata & 32'h208; // @[CSR.scala 1424:23]
  wire [31:0] _reg_custom_0_T_2 = reg_custom_0 & 32'hfffffdf7; // @[CSR.scala 1424:38]
  wire [31:0] _reg_custom_0_T_3 = _reg_custom_0_T | _reg_custom_0_T_2; // @[CSR.scala 1424:31]
  wire [1:0] _GEN_473 = csr_wen ? _GEN_324 : _GEN_264; // @[CSR.scala 1148:18]
  wire [31:0] _GEN_487 = csr_wen ? _GEN_303 : {{1'd0}, reg_mtvec}; // @[CSR.scala 1148:18 479:27]
  wire [31:0] _GEN_490 = csr_wen ? _GEN_306 : {{29'd0}, reg_mcountinhibit}; // @[CSR.scala 1148:18 547:34]
  wire [63:0] _GEN_491 = csr_wen ? _GEN_309 : {{57'd0}, _GEN_2}; // @[CSR.scala 1148:18]
  wire [63:0] _GEN_493 = csr_wen ? _GEN_313 : {{57'd0}, _GEN_0}; // @[CSR.scala 1148:18]
  wire [31:0] _GEN_511 = csr_wen ? _GEN_338 : {{31'd0}, reg_tselect}; // @[CSR.scala 1148:18 458:24]
  wire [31:0] _GEN_550 = csr_wen ? _GEN_411 : {{3'd0}, reg_pmp_0_addr}; // @[CSR.scala 1148:18 460:20]
  wire [31:0] _GEN_557 = csr_wen ? _GEN_418 : {{3'd0}, reg_pmp_1_addr}; // @[CSR.scala 1148:18 460:20]
  wire [31:0] _GEN_564 = csr_wen ? _GEN_425 : {{3'd0}, reg_pmp_2_addr}; // @[CSR.scala 1148:18 460:20]
  wire [31:0] _GEN_571 = csr_wen ? _GEN_432 : {{3'd0}, reg_pmp_3_addr}; // @[CSR.scala 1148:18 460:20]
  wire [31:0] _GEN_578 = csr_wen ? _GEN_439 : {{3'd0}, reg_pmp_4_addr}; // @[CSR.scala 1148:18 460:20]
  wire [31:0] _GEN_585 = csr_wen ? _GEN_446 : {{3'd0}, reg_pmp_5_addr}; // @[CSR.scala 1148:18 460:20]
  wire [31:0] _GEN_592 = csr_wen ? _GEN_453 : {{3'd0}, reg_pmp_6_addr}; // @[CSR.scala 1148:18 460:20]
  wire [31:0] _GEN_599 = csr_wen ? _GEN_460 : {{3'd0}, reg_pmp_7_addr}; // @[CSR.scala 1148:18 460:20]
  assign io_rw_rdata = _io_rw_rdata_T_414[31:0]; // @[CSR.scala 1101:15]
  assign io_decode_0_fp_illegal = io_status_fs == 2'h0 | ~reg_misa[5]; // @[CSR.scala 850:87]
  assign io_decode_0_fp_csr = 1'h0; // @[CSR.scala 852:19]
  assign io_decode_0_read_illegal = _io_decode_0_read_illegal_T_18 | _io_decode_0_read_illegal_T_21; // @[CSR.scala 862:68]
  assign io_decode_0_write_illegal = &addr_1[11:10]; // @[CSR.scala 864:41]
  assign io_decode_0_write_flush = ~(io_decode_0_write_flush_addr_m >= 12'h340 & io_decode_0_write_flush_addr_m <= 12'h343
    ); // @[CSR.scala 867:7]
  assign io_decode_0_system_illegal = _io_decode_0_system_illegal_T_8 | _io_decode_0_system_illegal_T_14; // @[CSR.scala 871:29]
  assign io_csr_stall = reg_wfi | io_status_cease; // @[CSR.scala 1091:27]
  assign io_eret = _exception_T | insn_ret; // @[CSR.scala 933:38]
  assign io_singleStep = reg_dcsr_step & _T_401; // @[CSR.scala 934:34]
  assign io_status_debug = reg_debug; // @[CSR.scala 937:19]
  assign io_status_cease = io_status_cease_r; // @[CSR.scala 1092:19]
  assign io_status_wfi = reg_wfi; // @[CSR.scala 1093:17]
  assign io_status_isa = reg_misa; // @[CSR.scala 938:17]
  assign io_status_dprv = reg_mstatus_mprv & _T_401 ? reg_mstatus_mpp : reg_mstatus_prv; // @[CSR.scala 941:24]
  assign io_status_dv = 1'h0; // @[CSR.scala 942:39]
  assign io_status_prv = reg_mstatus_prv; // @[CSR.scala 935:13]
  assign io_status_v = 1'h0; // @[CSR.scala 935:13]
  assign io_status_sd = &io_status_fs | &io_status_xs | &io_status_vs; // @[CSR.scala 936:58]
  assign io_status_zero2 = 23'h0; // @[CSR.scala 935:13]
  assign io_status_mpv = 1'h0; // @[CSR.scala 944:17]
  assign io_status_gva = reg_mstatus_gva; // @[CSR.scala 945:17]
  assign io_status_mbe = 1'h0; // @[CSR.scala 935:13]
  assign io_status_sbe = 1'h0; // @[CSR.scala 935:13]
  assign io_status_sxl = 2'h1; // @[CSR.scala 940:17]
  assign io_status_uxl = 2'h1; // @[CSR.scala 939:17]
  assign io_status_sd_rv32 = io_status_sd; // @[CSR.scala 943:35]
  assign io_status_zero1 = 8'h0; // @[CSR.scala 935:13]
  assign io_status_tsr = reg_mstatus_tsr; // @[CSR.scala 935:13]
  assign io_status_tw = reg_mstatus_tw; // @[CSR.scala 935:13]
  assign io_status_tvm = 1'h0; // @[CSR.scala 935:13]
  assign io_status_mxr = 1'h0; // @[CSR.scala 935:13]
  assign io_status_sum = 1'h0; // @[CSR.scala 935:13]
  assign io_status_mprv = reg_mstatus_mprv; // @[CSR.scala 935:13]
  assign io_status_xs = 2'h0; // @[CSR.scala 935:13]
  assign io_status_fs = reg_mstatus_fs; // @[CSR.scala 935:13]
  assign io_status_mpp = reg_mstatus_mpp; // @[CSR.scala 935:13]
  assign io_status_vs = 2'h0; // @[CSR.scala 935:13]
  assign io_status_spp = reg_mstatus_spp; // @[CSR.scala 935:13]
  assign io_status_mpie = reg_mstatus_mpie; // @[CSR.scala 935:13]
  assign io_status_ube = 1'h0; // @[CSR.scala 935:13]
  assign io_status_spie = reg_mstatus_spie; // @[CSR.scala 935:13]
  assign io_status_upie = 1'h0; // @[CSR.scala 935:13]
  assign io_status_mie = reg_mstatus_mie; // @[CSR.scala 935:13]
  assign io_status_hie = 1'h0; // @[CSR.scala 935:13]
  assign io_status_sie = reg_mstatus_sie; // @[CSR.scala 935:13]
  assign io_status_uie = 1'h0; // @[CSR.scala 935:13]
  assign io_evec = insn_ret ? _GEN_250 : tvec; // @[CSR.scala 1045:19 929:11]
  assign io_time = value_1[31:0]; // @[CSR.scala 1090:11]
  assign io_interrupt = (anyInterrupt & ~io_singleStep | reg_singleStepped) & ~(reg_debug | io_status_cease); // @[CSR.scala 583:73]
  assign io_interrupt_cause = 32'h80000000 + _GEN_639; // @[CSR.scala 582:67]
  assign io_bp_0_control_action = reg_bp_0_control_action; // @[CSR.scala 585:9]
  assign io_bp_0_control_chain = reg_bp_0_control_chain; // @[CSR.scala 585:9]
  assign io_bp_0_control_tmatch = reg_bp_0_control_tmatch; // @[CSR.scala 585:9]
  assign io_bp_0_control_m = reg_bp_0_control_m; // @[CSR.scala 585:9]
  assign io_bp_0_control_s = reg_bp_0_control_s; // @[CSR.scala 585:9]
  assign io_bp_0_control_u = reg_bp_0_control_u; // @[CSR.scala 585:9]
  assign io_bp_0_control_x = reg_bp_0_control_x; // @[CSR.scala 585:9]
  assign io_bp_0_control_w = reg_bp_0_control_w; // @[CSR.scala 585:9]
  assign io_bp_0_control_r = reg_bp_0_control_r; // @[CSR.scala 585:9]
  assign io_bp_0_address = reg_bp_0_address; // @[CSR.scala 585:9]
  assign io_bp_1_control_action = reg_bp_1_control_action; // @[CSR.scala 585:9]
  assign io_bp_1_control_tmatch = reg_bp_1_control_tmatch; // @[CSR.scala 585:9]
  assign io_bp_1_control_m = reg_bp_1_control_m; // @[CSR.scala 585:9]
  assign io_bp_1_control_s = reg_bp_1_control_s; // @[CSR.scala 585:9]
  assign io_bp_1_control_u = reg_bp_1_control_u; // @[CSR.scala 585:9]
  assign io_bp_1_control_x = reg_bp_1_control_x; // @[CSR.scala 585:9]
  assign io_bp_1_control_w = reg_bp_1_control_w; // @[CSR.scala 585:9]
  assign io_bp_1_control_r = reg_bp_1_control_r; // @[CSR.scala 585:9]
  assign io_bp_1_address = reg_bp_1_address; // @[CSR.scala 585:9]
  assign io_pmp_0_cfg_l = reg_pmp_0_cfg_l; // @[PMP.scala 25:19 26:13]
  assign io_pmp_0_cfg_a = reg_pmp_0_cfg_a; // @[PMP.scala 25:19 26:13]
  assign io_pmp_0_cfg_x = reg_pmp_0_cfg_x; // @[PMP.scala 25:19 26:13]
  assign io_pmp_0_cfg_w = reg_pmp_0_cfg_w; // @[PMP.scala 25:19 26:13]
  assign io_pmp_0_cfg_r = reg_pmp_0_cfg_r; // @[PMP.scala 25:19 26:13]
  assign io_pmp_0_addr = reg_pmp_0_addr; // @[PMP.scala 25:19 27:14]
  assign io_pmp_0_mask = _pmp_mask_T_4[30:0]; // @[PMP.scala 25:19 28:14]
  assign io_pmp_1_cfg_l = reg_pmp_1_cfg_l; // @[PMP.scala 25:19 26:13]
  assign io_pmp_1_cfg_a = reg_pmp_1_cfg_a; // @[PMP.scala 25:19 26:13]
  assign io_pmp_1_cfg_x = reg_pmp_1_cfg_x; // @[PMP.scala 25:19 26:13]
  assign io_pmp_1_cfg_w = reg_pmp_1_cfg_w; // @[PMP.scala 25:19 26:13]
  assign io_pmp_1_cfg_r = reg_pmp_1_cfg_r; // @[PMP.scala 25:19 26:13]
  assign io_pmp_1_addr = reg_pmp_1_addr; // @[PMP.scala 25:19 27:14]
  assign io_pmp_1_mask = _pmp_mask_T_9[30:0]; // @[PMP.scala 25:19 28:14]
  assign io_pmp_2_cfg_l = reg_pmp_2_cfg_l; // @[PMP.scala 25:19 26:13]
  assign io_pmp_2_cfg_a = reg_pmp_2_cfg_a; // @[PMP.scala 25:19 26:13]
  assign io_pmp_2_cfg_x = reg_pmp_2_cfg_x; // @[PMP.scala 25:19 26:13]
  assign io_pmp_2_cfg_w = reg_pmp_2_cfg_w; // @[PMP.scala 25:19 26:13]
  assign io_pmp_2_cfg_r = reg_pmp_2_cfg_r; // @[PMP.scala 25:19 26:13]
  assign io_pmp_2_addr = reg_pmp_2_addr; // @[PMP.scala 25:19 27:14]
  assign io_pmp_2_mask = _pmp_mask_T_14[30:0]; // @[PMP.scala 25:19 28:14]
  assign io_pmp_3_cfg_l = reg_pmp_3_cfg_l; // @[PMP.scala 25:19 26:13]
  assign io_pmp_3_cfg_a = reg_pmp_3_cfg_a; // @[PMP.scala 25:19 26:13]
  assign io_pmp_3_cfg_x = reg_pmp_3_cfg_x; // @[PMP.scala 25:19 26:13]
  assign io_pmp_3_cfg_w = reg_pmp_3_cfg_w; // @[PMP.scala 25:19 26:13]
  assign io_pmp_3_cfg_r = reg_pmp_3_cfg_r; // @[PMP.scala 25:19 26:13]
  assign io_pmp_3_addr = reg_pmp_3_addr; // @[PMP.scala 25:19 27:14]
  assign io_pmp_3_mask = _pmp_mask_T_19[30:0]; // @[PMP.scala 25:19 28:14]
  assign io_pmp_4_cfg_l = reg_pmp_4_cfg_l; // @[PMP.scala 25:19 26:13]
  assign io_pmp_4_cfg_a = reg_pmp_4_cfg_a; // @[PMP.scala 25:19 26:13]
  assign io_pmp_4_cfg_x = reg_pmp_4_cfg_x; // @[PMP.scala 25:19 26:13]
  assign io_pmp_4_cfg_w = reg_pmp_4_cfg_w; // @[PMP.scala 25:19 26:13]
  assign io_pmp_4_cfg_r = reg_pmp_4_cfg_r; // @[PMP.scala 25:19 26:13]
  assign io_pmp_4_addr = reg_pmp_4_addr; // @[PMP.scala 25:19 27:14]
  assign io_pmp_4_mask = _pmp_mask_T_24[30:0]; // @[PMP.scala 25:19 28:14]
  assign io_pmp_5_cfg_l = reg_pmp_5_cfg_l; // @[PMP.scala 25:19 26:13]
  assign io_pmp_5_cfg_a = reg_pmp_5_cfg_a; // @[PMP.scala 25:19 26:13]
  assign io_pmp_5_cfg_x = reg_pmp_5_cfg_x; // @[PMP.scala 25:19 26:13]
  assign io_pmp_5_cfg_w = reg_pmp_5_cfg_w; // @[PMP.scala 25:19 26:13]
  assign io_pmp_5_cfg_r = reg_pmp_5_cfg_r; // @[PMP.scala 25:19 26:13]
  assign io_pmp_5_addr = reg_pmp_5_addr; // @[PMP.scala 25:19 27:14]
  assign io_pmp_5_mask = _pmp_mask_T_29[30:0]; // @[PMP.scala 25:19 28:14]
  assign io_pmp_6_cfg_l = reg_pmp_6_cfg_l; // @[PMP.scala 25:19 26:13]
  assign io_pmp_6_cfg_a = reg_pmp_6_cfg_a; // @[PMP.scala 25:19 26:13]
  assign io_pmp_6_cfg_x = reg_pmp_6_cfg_x; // @[PMP.scala 25:19 26:13]
  assign io_pmp_6_cfg_w = reg_pmp_6_cfg_w; // @[PMP.scala 25:19 26:13]
  assign io_pmp_6_cfg_r = reg_pmp_6_cfg_r; // @[PMP.scala 25:19 26:13]
  assign io_pmp_6_addr = reg_pmp_6_addr; // @[PMP.scala 25:19 27:14]
  assign io_pmp_6_mask = _pmp_mask_T_34[30:0]; // @[PMP.scala 25:19 28:14]
  assign io_pmp_7_cfg_l = reg_pmp_7_cfg_l; // @[PMP.scala 25:19 26:13]
  assign io_pmp_7_cfg_a = reg_pmp_7_cfg_a; // @[PMP.scala 25:19 26:13]
  assign io_pmp_7_cfg_x = reg_pmp_7_cfg_x; // @[PMP.scala 25:19 26:13]
  assign io_pmp_7_cfg_w = reg_pmp_7_cfg_w; // @[PMP.scala 25:19 26:13]
  assign io_pmp_7_cfg_r = reg_pmp_7_cfg_r; // @[PMP.scala 25:19 26:13]
  assign io_pmp_7_addr = reg_pmp_7_addr; // @[PMP.scala 25:19 27:14]
  assign io_pmp_7_mask = _pmp_mask_T_39[30:0]; // @[PMP.scala 25:19 28:14]
  assign io_inhibit_cycle = reg_mcountinhibit[0]; // @[CSR.scala 548:40]
  assign io_trace_0_valid = io_retire > 1'h0 | io_trace_0_exception; // @[CSR.scala 1519:30]
  assign io_trace_0_iaddr = io_pc; // @[CSR.scala 1521:13]
  assign io_trace_0_insn = io_inst_0; // @[CSR.scala 1520:12]
  assign io_trace_0_exception = insn_call | insn_break | io_exception; // @[CSR.scala 953:43]
  assign io_customCSRs_0_value = reg_custom_0; // @[CSR.scala 1098:14]
  always @(posedge clock) begin
    if (reset) begin // @[CSR.scala 369:24]
      reg_mstatus_prv <= 2'h3; // @[CSR.scala 369:24]
    end else if (new_prv == 2'h2) begin // @[CSR.scala 1544:29]
      reg_mstatus_prv <= 2'h0;
    end else if (insn_ret) begin // @[CSR.scala 1045:19]
      if (~io_rw_addr[9]) begin // @[CSR.scala 1047:52]
        reg_mstatus_prv <= {{1'd0}, reg_mstatus_spp};
      end else begin
        reg_mstatus_prv <= _GEN_236;
      end
    end else if (exception) begin // @[CSR.scala 967:20]
      reg_mstatus_prv <= _GEN_150;
    end
    if (reset) begin // @[CSR.scala 369:24]
      reg_mstatus_gva <= 1'h0; // @[CSR.scala 369:24]
    end else if (exception) begin // @[CSR.scala 967:20]
      if (!(trapToDebug)) begin // @[CSR.scala 968:24]
        if (!(delegate)) begin // @[CSR.scala 997:35]
          reg_mstatus_gva <= io_gva; // @[CSR.scala 1013:23]
        end
      end
    end
    if (reset) begin // @[CSR.scala 369:24]
      reg_mstatus_tsr <= 1'h0; // @[CSR.scala 369:24]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_5) begin // @[CSR.scala 1152:39]
        reg_mstatus_tsr <= new_mstatus_tsr; // @[CSR.scala 1165:27]
      end
    end
    if (reset) begin // @[CSR.scala 369:24]
      reg_mstatus_tw <= 1'h0; // @[CSR.scala 369:24]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_5) begin // @[CSR.scala 1152:39]
        reg_mstatus_tw <= new_mstatus_tw; // @[CSR.scala 1164:26]
      end
    end
    if (reset) begin // @[CSR.scala 369:24]
      reg_mstatus_mprv <= 1'h0; // @[CSR.scala 369:24]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_5) begin // @[CSR.scala 1152:39]
        reg_mstatus_mprv <= new_mstatus_mprv; // @[CSR.scala 1158:26]
      end else begin
        reg_mstatus_mprv <= _GEN_278;
      end
    end else begin
      reg_mstatus_mprv <= _GEN_278;
    end
    if (reset) begin // @[CSR.scala 369:24]
      reg_mstatus_fs <= 2'h0; // @[CSR.scala 369:24]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_172) begin // @[CSR.scala 1261:41]
        reg_mstatus_fs <= _reg_mstatus_fs_T_2; // @[CSR.scala 1266:24]
      end else if (decoded_5) begin // @[CSR.scala 1152:39]
        reg_mstatus_fs <= _reg_mstatus_fs_T_2; // @[CSR.scala 1178:55]
      end
    end
    if (reset) begin // @[CSR.scala 369:24]
      reg_mstatus_mpp <= 2'h3; // @[CSR.scala 369:24]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_5) begin // @[CSR.scala 1152:39]
        if (new_mstatus_mpp == 2'h2) begin // @[CSR.scala 1544:29]
          reg_mstatus_mpp <= 2'h0;
        end else begin
          reg_mstatus_mpp <= new_mstatus_mpp;
        end
      end else begin
        reg_mstatus_mpp <= _GEN_275;
      end
    end else begin
      reg_mstatus_mpp <= _GEN_275;
    end
    if (reset) begin // @[CSR.scala 369:24]
      reg_mstatus_spp <= 1'h0; // @[CSR.scala 369:24]
    end else begin
      reg_mstatus_spp <= _GEN_473[0];
    end
    if (reset) begin // @[CSR.scala 369:24]
      reg_mstatus_mpie <= 1'h0; // @[CSR.scala 369:24]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_5) begin // @[CSR.scala 1152:39]
        reg_mstatus_mpie <= new_mstatus_mpie; // @[CSR.scala 1155:24]
      end else begin
        reg_mstatus_mpie <= _GEN_274;
      end
    end else begin
      reg_mstatus_mpie <= _GEN_274;
    end
    if (reset) begin // @[CSR.scala 369:24]
      reg_mstatus_spie <= 1'h0; // @[CSR.scala 369:24]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_172) begin // @[CSR.scala 1261:41]
        reg_mstatus_spie <= new_mstatus_spie; // @[CSR.scala 1264:26]
      end else if (decoded_5) begin // @[CSR.scala 1152:39]
        reg_mstatus_spie <= new_mstatus_spie; // @[CSR.scala 1162:28]
      end else begin
        reg_mstatus_spie <= _GEN_263;
      end
    end else begin
      reg_mstatus_spie <= _GEN_263;
    end
    if (reset) begin // @[CSR.scala 369:24]
      reg_mstatus_mie <= 1'h0; // @[CSR.scala 369:24]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_5) begin // @[CSR.scala 1152:39]
        reg_mstatus_mie <= new_mstatus_mie; // @[CSR.scala 1154:23]
      end else begin
        reg_mstatus_mie <= _GEN_273;
      end
    end else begin
      reg_mstatus_mie <= _GEN_273;
    end
    if (reset) begin // @[CSR.scala 369:24]
      reg_mstatus_sie <= 1'h0; // @[CSR.scala 369:24]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_172) begin // @[CSR.scala 1261:41]
        reg_mstatus_sie <= new_mstatus_sie; // @[CSR.scala 1263:25]
      end else if (decoded_5) begin // @[CSR.scala 1152:39]
        reg_mstatus_sie <= new_mstatus_sie; // @[CSR.scala 1163:27]
      end else begin
        reg_mstatus_sie <= _GEN_262;
      end
    end else begin
      reg_mstatus_sie <= _GEN_262;
    end
    if (reset) begin // @[CSR.scala 377:21]
      reg_dcsr_prv <= 2'h3; // @[CSR.scala 377:21]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_14) begin // @[CSR.scala 1245:38]
        if (new_dcsr_prv == 2'h2) begin // @[CSR.scala 1544:29]
          reg_dcsr_prv <= 2'h0;
        end else begin
          reg_dcsr_prv <= new_dcsr_prv;
        end
      end else begin
        reg_dcsr_prv <= _GEN_185;
      end
    end else begin
      reg_dcsr_prv <= _GEN_185;
    end
    if (_io_interrupt_T) begin // @[CSR.scala 961:25]
      reg_singleStepped <= 1'h0; // @[CSR.scala 961:45]
    end else begin
      reg_singleStepped <= _GEN_48;
    end
    if (reset) begin // @[CSR.scala 377:21]
      reg_dcsr_ebreakm <= 1'h0; // @[CSR.scala 377:21]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_14) begin // @[CSR.scala 1245:38]
        reg_dcsr_ebreakm <= new_dcsr_ebreakm; // @[CSR.scala 1248:26]
      end
    end
    if (reset) begin // @[CSR.scala 377:21]
      reg_dcsr_ebreaks <= 1'h0; // @[CSR.scala 377:21]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_14) begin // @[CSR.scala 1245:38]
        reg_dcsr_ebreaks <= new_dcsr_ebreaks; // @[CSR.scala 1249:47]
      end
    end
    if (reset) begin // @[CSR.scala 377:21]
      reg_dcsr_ebreaku <= 1'h0; // @[CSR.scala 377:21]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_14) begin // @[CSR.scala 1245:38]
        reg_dcsr_ebreaku <= new_dcsr_ebreaku; // @[CSR.scala 1250:41]
      end
    end
    if (reset) begin // @[CSR.scala 449:22]
      reg_debug <= 1'h0; // @[CSR.scala 449:22]
    end else if (insn_ret) begin // @[CSR.scala 1045:19]
      if (~io_rw_addr[9]) begin // @[CSR.scala 1047:52]
        reg_debug <= _GEN_182;
      end else if (io_rw_addr[10] & io_rw_addr[7]) begin // @[CSR.scala 1064:70]
        reg_debug <= 1'h0; // @[CSR.scala 1067:17]
      end else begin
        reg_debug <= _GEN_182;
      end
    end else begin
      reg_debug <= _GEN_182;
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_182) begin // @[CSR.scala 1293:42]
        reg_mideleg <= wdata; // @[CSR.scala 1293:56]
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_183) begin // @[CSR.scala 1294:42]
        reg_medeleg <= wdata; // @[CSR.scala 1294:56]
      end
    end
    if (reset) begin // @[CSR.scala 377:21]
      reg_dcsr_cause <= 3'h0; // @[CSR.scala 377:21]
    end else if (exception) begin // @[CSR.scala 967:20]
      if (trapToDebug) begin // @[CSR.scala 968:24]
        if (~reg_debug) begin // @[CSR.scala 969:25]
          reg_dcsr_cause <= _reg_dcsr_cause_T_2; // @[CSR.scala 973:24]
        end
      end
    end
    if (reset) begin // @[CSR.scala 377:21]
      reg_dcsr_step <= 1'h0; // @[CSR.scala 377:21]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_14) begin // @[CSR.scala 1245:38]
        reg_dcsr_step <= wdata[2]; // @[CSR.scala 1247:23]
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_15) begin // @[CSR.scala 1254:42]
        reg_dpc <= _reg_mepc_T_2; // @[CSR.scala 1254:52]
      end else begin
        reg_dpc <= _GEN_183;
      end
    end else begin
      reg_dpc <= _GEN_183;
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_16) begin // @[CSR.scala 1255:42]
        reg_dscratch <= wdata; // @[CSR.scala 1255:57]
      end
    end
    reg_tselect <= _GEN_511[0];
    if (reset) begin // @[CSR.scala 1497:18]
      reg_bp_0_control_dmode <= 1'h0; // @[CSR.scala 1499:17]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (~reg_tselect & (~reg_bp_0_control_dmode | reg_debug)) begin // @[CSR.scala 1376:70]
        if (decoded_1) begin // @[CSR.scala 1388:44]
          reg_bp_0_control_dmode <= dMode; // @[CSR.scala 1397:30]
        end
      end
    end
    if (reset) begin // @[CSR.scala 1497:18]
      reg_bp_0_control_action <= 1'h0; // @[CSR.scala 1498:18]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (~reg_tselect & (~reg_bp_0_control_dmode | reg_debug)) begin // @[CSR.scala 1376:70]
        if (decoded_1) begin // @[CSR.scala 1388:44]
          reg_bp_0_control_action <= _GEN_340;
        end
      end
    end
    if (reset) begin // @[CSR.scala 1497:18]
      reg_bp_0_control_chain <= 1'h0; // @[CSR.scala 1500:17]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (~reg_tselect & (~reg_bp_0_control_dmode | reg_debug)) begin // @[CSR.scala 1376:70]
        if (decoded_1) begin // @[CSR.scala 1388:44]
          reg_bp_0_control_chain <= newBPC_chain & (dMode | ~reg_bp_1_control_dmode); // @[CSR.scala 1399:30]
        end
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (~reg_tselect & (~reg_bp_0_control_dmode | reg_debug)) begin // @[CSR.scala 1376:70]
        if (decoded_1) begin // @[CSR.scala 1388:44]
          reg_bp_0_control_tmatch <= wdata[8:7]; // @[CSR.scala 1389:24]
        end
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (~reg_tselect & (~reg_bp_0_control_dmode | reg_debug)) begin // @[CSR.scala 1376:70]
        if (decoded_1) begin // @[CSR.scala 1388:44]
          reg_bp_0_control_m <= wdata[6]; // @[CSR.scala 1389:24]
        end
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (~reg_tselect & (~reg_bp_0_control_dmode | reg_debug)) begin // @[CSR.scala 1376:70]
        if (decoded_1) begin // @[CSR.scala 1388:44]
          reg_bp_0_control_s <= wdata[4]; // @[CSR.scala 1389:24]
        end
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (~reg_tselect & (~reg_bp_0_control_dmode | reg_debug)) begin // @[CSR.scala 1376:70]
        if (decoded_1) begin // @[CSR.scala 1388:44]
          reg_bp_0_control_u <= wdata[3]; // @[CSR.scala 1389:24]
        end
      end
    end
    if (reset) begin // @[CSR.scala 1497:18]
      reg_bp_0_control_x <= 1'h0; // @[CSR.scala 1503:13]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (~reg_tselect & (~reg_bp_0_control_dmode | reg_debug)) begin // @[CSR.scala 1376:70]
        if (decoded_1) begin // @[CSR.scala 1388:44]
          reg_bp_0_control_x <= wdata[2]; // @[CSR.scala 1389:24]
        end
      end
    end
    if (reset) begin // @[CSR.scala 1497:18]
      reg_bp_0_control_w <= 1'h0; // @[CSR.scala 1502:13]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (~reg_tselect & (~reg_bp_0_control_dmode | reg_debug)) begin // @[CSR.scala 1376:70]
        if (decoded_1) begin // @[CSR.scala 1388:44]
          reg_bp_0_control_w <= wdata[1]; // @[CSR.scala 1389:24]
        end
      end
    end
    if (reset) begin // @[CSR.scala 1497:18]
      reg_bp_0_control_r <= 1'h0; // @[CSR.scala 1501:13]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (~reg_tselect & (~reg_bp_0_control_dmode | reg_debug)) begin // @[CSR.scala 1376:70]
        if (decoded_1) begin // @[CSR.scala 1388:44]
          reg_bp_0_control_r <= wdata[0]; // @[CSR.scala 1389:24]
        end
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (~reg_tselect & (~reg_bp_0_control_dmode | reg_debug)) begin // @[CSR.scala 1376:70]
        if (decoded_2) begin // @[CSR.scala 1377:44]
          reg_bp_0_address <= wdata; // @[CSR.scala 1377:57]
        end
      end
    end
    if (reset) begin // @[CSR.scala 1497:18]
      reg_bp_1_control_dmode <= 1'h0; // @[CSR.scala 1499:17]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (reg_tselect & (_reg_bp_0_control_chain_T_3 | reg_debug)) begin // @[CSR.scala 1376:70]
        if (decoded_1) begin // @[CSR.scala 1388:44]
          reg_bp_1_control_dmode <= dMode_1; // @[CSR.scala 1397:30]
        end
      end
    end
    if (reset) begin // @[CSR.scala 1497:18]
      reg_bp_1_control_action <= 1'h0; // @[CSR.scala 1498:18]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (reg_tselect & (_reg_bp_0_control_chain_T_3 | reg_debug)) begin // @[CSR.scala 1376:70]
        if (decoded_1) begin // @[CSR.scala 1388:44]
          reg_bp_1_control_action <= _GEN_373;
        end
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (reg_tselect & (_reg_bp_0_control_chain_T_3 | reg_debug)) begin // @[CSR.scala 1376:70]
        if (decoded_1) begin // @[CSR.scala 1388:44]
          reg_bp_1_control_tmatch <= wdata[8:7]; // @[CSR.scala 1389:24]
        end
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (reg_tselect & (_reg_bp_0_control_chain_T_3 | reg_debug)) begin // @[CSR.scala 1376:70]
        if (decoded_1) begin // @[CSR.scala 1388:44]
          reg_bp_1_control_m <= wdata[6]; // @[CSR.scala 1389:24]
        end
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (reg_tselect & (_reg_bp_0_control_chain_T_3 | reg_debug)) begin // @[CSR.scala 1376:70]
        if (decoded_1) begin // @[CSR.scala 1388:44]
          reg_bp_1_control_s <= wdata[4]; // @[CSR.scala 1389:24]
        end
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (reg_tselect & (_reg_bp_0_control_chain_T_3 | reg_debug)) begin // @[CSR.scala 1376:70]
        if (decoded_1) begin // @[CSR.scala 1388:44]
          reg_bp_1_control_u <= wdata[3]; // @[CSR.scala 1389:24]
        end
      end
    end
    if (reset) begin // @[CSR.scala 1497:18]
      reg_bp_1_control_x <= 1'h0; // @[CSR.scala 1503:13]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (reg_tselect & (_reg_bp_0_control_chain_T_3 | reg_debug)) begin // @[CSR.scala 1376:70]
        if (decoded_1) begin // @[CSR.scala 1388:44]
          reg_bp_1_control_x <= wdata[2]; // @[CSR.scala 1389:24]
        end
      end
    end
    if (reset) begin // @[CSR.scala 1497:18]
      reg_bp_1_control_w <= 1'h0; // @[CSR.scala 1502:13]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (reg_tselect & (_reg_bp_0_control_chain_T_3 | reg_debug)) begin // @[CSR.scala 1376:70]
        if (decoded_1) begin // @[CSR.scala 1388:44]
          reg_bp_1_control_w <= wdata[1]; // @[CSR.scala 1389:24]
        end
      end
    end
    if (reset) begin // @[CSR.scala 1497:18]
      reg_bp_1_control_r <= 1'h0; // @[CSR.scala 1501:13]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (reg_tselect & (_reg_bp_0_control_chain_T_3 | reg_debug)) begin // @[CSR.scala 1376:70]
        if (decoded_1) begin // @[CSR.scala 1388:44]
          reg_bp_1_control_r <= wdata[0]; // @[CSR.scala 1389:24]
        end
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (reg_tselect & (_reg_bp_0_control_chain_T_3 | reg_debug)) begin // @[CSR.scala 1376:70]
        if (decoded_2) begin // @[CSR.scala 1377:44]
          reg_bp_1_address <= wdata; // @[CSR.scala 1377:57]
        end
      end
    end
    if (reset) begin // @[CSR.scala 1514:18]
      reg_pmp_0_cfg_l <= 1'h0; // @[PMP.scala 39:11]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_184 & ~reg_pmp_0_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_0_cfg_l <= newCfg_l; // @[CSR.scala 1410:17]
      end
    end
    if (reset) begin // @[CSR.scala 1514:18]
      reg_pmp_0_cfg_a <= 2'h0; // @[PMP.scala 38:11]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_184 & ~reg_pmp_0_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_0_cfg_a <= newCfg_a; // @[CSR.scala 1410:17]
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_184 & ~reg_pmp_0_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_0_cfg_x <= newCfg_x; // @[CSR.scala 1410:17]
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_184 & ~reg_pmp_0_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_0_cfg_w <= newCfg_w & newCfg_r; // @[CSR.scala 1412:19]
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_184 & ~reg_pmp_0_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_0_cfg_r <= newCfg_r; // @[CSR.scala 1410:17]
      end
    end
    reg_pmp_0_addr <= _GEN_550[28:0];
    if (reset) begin // @[CSR.scala 1514:18]
      reg_pmp_1_cfg_l <= 1'h0; // @[PMP.scala 39:11]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_184 & ~reg_pmp_1_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_1_cfg_l <= newCfg_1_l; // @[CSR.scala 1410:17]
      end
    end
    if (reset) begin // @[CSR.scala 1514:18]
      reg_pmp_1_cfg_a <= 2'h0; // @[PMP.scala 38:11]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_184 & ~reg_pmp_1_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_1_cfg_a <= newCfg_1_a; // @[CSR.scala 1410:17]
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_184 & ~reg_pmp_1_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_1_cfg_x <= newCfg_1_x; // @[CSR.scala 1410:17]
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_184 & ~reg_pmp_1_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_1_cfg_w <= newCfg_1_w & newCfg_1_r; // @[CSR.scala 1412:19]
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_184 & ~reg_pmp_1_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_1_cfg_r <= newCfg_1_r; // @[CSR.scala 1410:17]
      end
    end
    reg_pmp_1_addr <= _GEN_557[28:0];
    if (reset) begin // @[CSR.scala 1514:18]
      reg_pmp_2_cfg_l <= 1'h0; // @[PMP.scala 39:11]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_184 & ~reg_pmp_2_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_2_cfg_l <= newCfg_2_l; // @[CSR.scala 1410:17]
      end
    end
    if (reset) begin // @[CSR.scala 1514:18]
      reg_pmp_2_cfg_a <= 2'h0; // @[PMP.scala 38:11]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_184 & ~reg_pmp_2_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_2_cfg_a <= newCfg_2_a; // @[CSR.scala 1410:17]
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_184 & ~reg_pmp_2_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_2_cfg_x <= newCfg_2_x; // @[CSR.scala 1410:17]
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_184 & ~reg_pmp_2_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_2_cfg_w <= newCfg_2_w & newCfg_2_r; // @[CSR.scala 1412:19]
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_184 & ~reg_pmp_2_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_2_cfg_r <= newCfg_2_r; // @[CSR.scala 1410:17]
      end
    end
    reg_pmp_2_addr <= _GEN_564[28:0];
    if (reset) begin // @[CSR.scala 1514:18]
      reg_pmp_3_cfg_l <= 1'h0; // @[PMP.scala 39:11]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_184 & ~reg_pmp_3_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_3_cfg_l <= newCfg_3_l; // @[CSR.scala 1410:17]
      end
    end
    if (reset) begin // @[CSR.scala 1514:18]
      reg_pmp_3_cfg_a <= 2'h0; // @[PMP.scala 38:11]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_184 & ~reg_pmp_3_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_3_cfg_a <= newCfg_3_a; // @[CSR.scala 1410:17]
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_184 & ~reg_pmp_3_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_3_cfg_x <= newCfg_3_x; // @[CSR.scala 1410:17]
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_184 & ~reg_pmp_3_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_3_cfg_w <= newCfg_3_w & newCfg_3_r; // @[CSR.scala 1412:19]
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_184 & ~reg_pmp_3_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_3_cfg_r <= newCfg_3_r; // @[CSR.scala 1410:17]
      end
    end
    reg_pmp_3_addr <= _GEN_571[28:0];
    if (reset) begin // @[CSR.scala 1514:18]
      reg_pmp_4_cfg_l <= 1'h0; // @[PMP.scala 39:11]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_185 & ~reg_pmp_4_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_4_cfg_l <= newCfg_l; // @[CSR.scala 1410:17]
      end
    end
    if (reset) begin // @[CSR.scala 1514:18]
      reg_pmp_4_cfg_a <= 2'h0; // @[PMP.scala 38:11]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_185 & ~reg_pmp_4_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_4_cfg_a <= newCfg_a; // @[CSR.scala 1410:17]
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_185 & ~reg_pmp_4_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_4_cfg_x <= newCfg_x; // @[CSR.scala 1410:17]
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_185 & ~reg_pmp_4_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_4_cfg_w <= newCfg_w & newCfg_r; // @[CSR.scala 1412:19]
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_185 & ~reg_pmp_4_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_4_cfg_r <= newCfg_r; // @[CSR.scala 1410:17]
      end
    end
    reg_pmp_4_addr <= _GEN_578[28:0];
    if (reset) begin // @[CSR.scala 1514:18]
      reg_pmp_5_cfg_l <= 1'h0; // @[PMP.scala 39:11]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_185 & ~reg_pmp_5_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_5_cfg_l <= newCfg_1_l; // @[CSR.scala 1410:17]
      end
    end
    if (reset) begin // @[CSR.scala 1514:18]
      reg_pmp_5_cfg_a <= 2'h0; // @[PMP.scala 38:11]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_185 & ~reg_pmp_5_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_5_cfg_a <= newCfg_1_a; // @[CSR.scala 1410:17]
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_185 & ~reg_pmp_5_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_5_cfg_x <= newCfg_1_x; // @[CSR.scala 1410:17]
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_185 & ~reg_pmp_5_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_5_cfg_w <= newCfg_1_w & newCfg_1_r; // @[CSR.scala 1412:19]
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_185 & ~reg_pmp_5_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_5_cfg_r <= newCfg_1_r; // @[CSR.scala 1410:17]
      end
    end
    reg_pmp_5_addr <= _GEN_585[28:0];
    if (reset) begin // @[CSR.scala 1514:18]
      reg_pmp_6_cfg_l <= 1'h0; // @[PMP.scala 39:11]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_185 & ~reg_pmp_6_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_6_cfg_l <= newCfg_2_l; // @[CSR.scala 1410:17]
      end
    end
    if (reset) begin // @[CSR.scala 1514:18]
      reg_pmp_6_cfg_a <= 2'h0; // @[PMP.scala 38:11]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_185 & ~reg_pmp_6_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_6_cfg_a <= newCfg_2_a; // @[CSR.scala 1410:17]
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_185 & ~reg_pmp_6_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_6_cfg_x <= newCfg_2_x; // @[CSR.scala 1410:17]
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_185 & ~reg_pmp_6_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_6_cfg_w <= newCfg_2_w & newCfg_2_r; // @[CSR.scala 1412:19]
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_185 & ~reg_pmp_6_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_6_cfg_r <= newCfg_2_r; // @[CSR.scala 1410:17]
      end
    end
    reg_pmp_6_addr <= _GEN_592[28:0];
    if (reset) begin // @[CSR.scala 1514:18]
      reg_pmp_7_cfg_l <= 1'h0; // @[PMP.scala 39:11]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_185 & ~reg_pmp_7_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_7_cfg_l <= newCfg_3_l; // @[CSR.scala 1410:17]
      end
    end
    if (reset) begin // @[CSR.scala 1514:18]
      reg_pmp_7_cfg_a <= 2'h0; // @[PMP.scala 38:11]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_185 & ~reg_pmp_7_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_7_cfg_a <= newCfg_3_a; // @[CSR.scala 1410:17]
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_185 & ~reg_pmp_7_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_7_cfg_x <= newCfg_3_x; // @[CSR.scala 1410:17]
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_185 & ~reg_pmp_7_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_7_cfg_w <= newCfg_3_w & newCfg_3_r; // @[CSR.scala 1412:19]
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_185 & ~reg_pmp_7_cfg_l) begin // @[CSR.scala 1408:76]
        reg_pmp_7_cfg_r <= newCfg_3_r; // @[CSR.scala 1410:17]
      end
    end
    reg_pmp_7_addr <= _GEN_599[28:0];
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_174) begin // @[CSR.scala 1287:42]
        reg_mie <= _reg_mie_T_4; // @[CSR.scala 1287:52]
      end else if (decoded_8) begin // @[CSR.scala 1205:40]
        reg_mie <= _reg_mie_T; // @[CSR.scala 1205:50]
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_7) begin // @[CSR.scala 1190:35]
        reg_mip_seip <= new_mip_seip; // @[CSR.scala 1199:22]
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_7) begin // @[CSR.scala 1190:35]
        reg_mip_stip <= new_mip_stip; // @[CSR.scala 1198:22]
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_173) begin // @[CSR.scala 1273:37]
        reg_mip_ssip <= new_sip_ssip; // @[CSR.scala 1275:22]
      end else if (decoded_7) begin // @[CSR.scala 1190:35]
        reg_mip_ssip <= new_mip_ssip; // @[CSR.scala 1197:22]
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_10) begin // @[CSR.scala 1206:40]
        reg_mepc <= _reg_mepc_T_2; // @[CSR.scala 1206:51]
      end else begin
        reg_mepc <= _GEN_211;
      end
    end else begin
      reg_mepc <= _GEN_211;
    end
    if (reset) begin // @[CSR.scala 473:27]
      reg_mcause <= 32'h0; // @[CSR.scala 473:27]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_12) begin // @[CSR.scala 1210:40]
        reg_mcause <= _reg_mcause_T; // @[CSR.scala 1210:53]
      end else begin
        reg_mcause <= _GEN_212;
      end
    end else begin
      reg_mcause <= _GEN_212;
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_11) begin // @[CSR.scala 1211:40]
        reg_mtval <= wdata; // @[CSR.scala 1211:52]
      end else begin
        reg_mtval <= _GEN_213;
      end
    end else begin
      reg_mtval <= _GEN_213;
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_9) begin // @[CSR.scala 1207:40]
        reg_mscratch <= wdata; // @[CSR.scala 1207:55]
      end
    end
    if (reset) begin // @[CSR.scala 479:27]
      reg_mtvec <= 31'h0; // @[CSR.scala 479:27]
    end else begin
      reg_mtvec <= _GEN_487[30:0];
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_165) begin // @[CSR.scala 1370:44]
        reg_mcounteren <= wdata; // @[CSR.scala 1370:61]
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_181) begin // @[CSR.scala 1295:44]
        reg_scounteren <= wdata; // @[CSR.scala 1295:61]
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_179) begin // @[CSR.scala 1289:42]
        reg_sepc <= _reg_mepc_T_2; // @[CSR.scala 1289:53]
      end else begin
        reg_sepc <= _GEN_202;
      end
    end else begin
      reg_sepc <= _GEN_202;
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_176) begin // @[CSR.scala 1291:42]
        reg_scause <= _reg_scause_T; // @[CSR.scala 1291:55]
      end else begin
        reg_scause <= _GEN_203;
      end
    end else begin
      reg_scause <= _GEN_203;
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_177) begin // @[CSR.scala 1292:42]
        reg_stval <= wdata; // @[CSR.scala 1292:54]
      end else begin
        reg_stval <= _GEN_204;
      end
    end else begin
      reg_stval <= _GEN_204;
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_175) begin // @[CSR.scala 1288:42]
        reg_sscratch <= wdata; // @[CSR.scala 1288:57]
      end
    end
    if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_180) begin // @[CSR.scala 1290:42]
        reg_stvec <= wdata; // @[CSR.scala 1290:54]
      end
    end
    if (reset) begin // @[CSR.scala 547:34]
      reg_mcountinhibit <= 3'h0; // @[CSR.scala 547:34]
    end else begin
      reg_mcountinhibit <= _GEN_490[2:0];
    end
    if (reset) begin // @[Counters.scala 45:37]
      small_ <= 6'h0; // @[Counters.scala 45:37]
    end else begin
      small_ <= _GEN_493[5:0];
    end
    if (reset) begin // @[Counters.scala 50:27]
      large_ <= 58'h0; // @[Counters.scala 50:27]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_169) begin // @[CSR.scala 1556:31]
        large_ <= _T_2689[63:6]; // @[Counters.scala 66:23]
      end else if (decoded_19) begin // @[CSR.scala 1555:31]
        large_ <= _T_2686[63:6]; // @[Counters.scala 66:23]
      end else begin
        large_ <= _GEN_1;
      end
    end else begin
      large_ <= _GEN_1;
    end
    if (reset) begin // @[CSR.scala 605:21]
      reg_misa <= 32'h40941105; // @[CSR.scala 605:21]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_4) begin // @[CSR.scala 1181:36]
        if (~io_pc[1] | wdata[2]) begin // @[CSR.scala 1185:64]
          reg_misa <= _reg_misa_T_8; // @[CSR.scala 1187:20]
        end
      end
    end
    if (reset) begin // @[CSR.scala 750:43]
      reg_custom_0 <= 32'h208; // @[CSR.scala 750:43]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_204) begin // @[CSR.scala 1423:35]
        reg_custom_0 <= _reg_custom_0_T_3; // @[CSR.scala 1424:13]
      end
    end
    if (reset) begin // @[Reg.scala 28:20]
      io_status_cease_r <= 1'h0; // @[Reg.scala 28:20]
    end else begin
      io_status_cease_r <= _GEN_279;
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_373 <= 3'h1) & ~reset) begin
          $fatal; // @[CSR.scala 954:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(_T_373 <= 3'h1)) begin
          $fwrite(32'h80000002,
            "Assertion failed: these conditions must be mutually exclusive\n    at CSR.scala:954 assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1, \"these conditions must be mutually exclusive\")\n"
            ); // @[CSR.scala 954:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~reg_singleStepped | ~io_retire) & _T_377) begin
          $fatal; // @[CSR.scala 963:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_377 & ~(~reg_singleStepped | ~io_retire)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at CSR.scala:963 assert(!reg_singleStepped || io.retire === UInt(0))\n"); // @[CSR.scala 963:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge io_ungated_clock) begin
    if (reset) begin // @[CSR.scala 538:50]
      reg_wfi <= 1'h0; // @[CSR.scala 538:50]
    end else if (|pending_interrupts | io_interrupts_debug | exception) begin // @[CSR.scala 957:69]
      reg_wfi <= 1'h0; // @[CSR.scala 957:79]
    end else begin
      reg_wfi <= _GEN_46;
    end
    if (reset) begin // @[Counters.scala 45:37]
      small_1 <= 6'h0; // @[Counters.scala 45:37]
    end else begin
      small_1 <= _GEN_491[5:0];
    end
    if (reset) begin // @[Counters.scala 50:27]
      large_1 <= 58'h0; // @[Counters.scala 50:27]
    end else if (csr_wen) begin // @[CSR.scala 1148:18]
      if (decoded_168) begin // @[CSR.scala 1556:31]
        large_1 <= _T_2684[63:6]; // @[Counters.scala 66:23]
      end else if (decoded_18) begin // @[CSR.scala 1555:31]
        large_1 <= _T_2681[63:6]; // @[Counters.scala 66:23]
      end else begin
        large_1 <= _GEN_3;
      end
    end else begin
      large_1 <= _GEN_3;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  reg_mstatus_prv = _RAND_0[1:0];
  _RAND_1 = {1{`RANDOM}};
  reg_mstatus_gva = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  reg_mstatus_tsr = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  reg_mstatus_tw = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  reg_mstatus_mprv = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  reg_mstatus_fs = _RAND_5[1:0];
  _RAND_6 = {1{`RANDOM}};
  reg_mstatus_mpp = _RAND_6[1:0];
  _RAND_7 = {1{`RANDOM}};
  reg_mstatus_spp = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  reg_mstatus_mpie = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  reg_mstatus_spie = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  reg_mstatus_mie = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  reg_mstatus_sie = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  reg_dcsr_prv = _RAND_12[1:0];
  _RAND_13 = {1{`RANDOM}};
  reg_singleStepped = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  reg_dcsr_ebreakm = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  reg_dcsr_ebreaks = _RAND_15[0:0];
  _RAND_16 = {1{`RANDOM}};
  reg_dcsr_ebreaku = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  reg_debug = _RAND_17[0:0];
  _RAND_18 = {1{`RANDOM}};
  reg_mideleg = _RAND_18[31:0];
  _RAND_19 = {1{`RANDOM}};
  reg_medeleg = _RAND_19[31:0];
  _RAND_20 = {1{`RANDOM}};
  reg_dcsr_cause = _RAND_20[2:0];
  _RAND_21 = {1{`RANDOM}};
  reg_dcsr_step = _RAND_21[0:0];
  _RAND_22 = {1{`RANDOM}};
  reg_dpc = _RAND_22[31:0];
  _RAND_23 = {1{`RANDOM}};
  reg_dscratch = _RAND_23[31:0];
  _RAND_24 = {1{`RANDOM}};
  reg_tselect = _RAND_24[0:0];
  _RAND_25 = {1{`RANDOM}};
  reg_bp_0_control_dmode = _RAND_25[0:0];
  _RAND_26 = {1{`RANDOM}};
  reg_bp_0_control_action = _RAND_26[0:0];
  _RAND_27 = {1{`RANDOM}};
  reg_bp_0_control_chain = _RAND_27[0:0];
  _RAND_28 = {1{`RANDOM}};
  reg_bp_0_control_tmatch = _RAND_28[1:0];
  _RAND_29 = {1{`RANDOM}};
  reg_bp_0_control_m = _RAND_29[0:0];
  _RAND_30 = {1{`RANDOM}};
  reg_bp_0_control_s = _RAND_30[0:0];
  _RAND_31 = {1{`RANDOM}};
  reg_bp_0_control_u = _RAND_31[0:0];
  _RAND_32 = {1{`RANDOM}};
  reg_bp_0_control_x = _RAND_32[0:0];
  _RAND_33 = {1{`RANDOM}};
  reg_bp_0_control_w = _RAND_33[0:0];
  _RAND_34 = {1{`RANDOM}};
  reg_bp_0_control_r = _RAND_34[0:0];
  _RAND_35 = {1{`RANDOM}};
  reg_bp_0_address = _RAND_35[31:0];
  _RAND_36 = {1{`RANDOM}};
  reg_bp_1_control_dmode = _RAND_36[0:0];
  _RAND_37 = {1{`RANDOM}};
  reg_bp_1_control_action = _RAND_37[0:0];
  _RAND_38 = {1{`RANDOM}};
  reg_bp_1_control_tmatch = _RAND_38[1:0];
  _RAND_39 = {1{`RANDOM}};
  reg_bp_1_control_m = _RAND_39[0:0];
  _RAND_40 = {1{`RANDOM}};
  reg_bp_1_control_s = _RAND_40[0:0];
  _RAND_41 = {1{`RANDOM}};
  reg_bp_1_control_u = _RAND_41[0:0];
  _RAND_42 = {1{`RANDOM}};
  reg_bp_1_control_x = _RAND_42[0:0];
  _RAND_43 = {1{`RANDOM}};
  reg_bp_1_control_w = _RAND_43[0:0];
  _RAND_44 = {1{`RANDOM}};
  reg_bp_1_control_r = _RAND_44[0:0];
  _RAND_45 = {1{`RANDOM}};
  reg_bp_1_address = _RAND_45[31:0];
  _RAND_46 = {1{`RANDOM}};
  reg_pmp_0_cfg_l = _RAND_46[0:0];
  _RAND_47 = {1{`RANDOM}};
  reg_pmp_0_cfg_a = _RAND_47[1:0];
  _RAND_48 = {1{`RANDOM}};
  reg_pmp_0_cfg_x = _RAND_48[0:0];
  _RAND_49 = {1{`RANDOM}};
  reg_pmp_0_cfg_w = _RAND_49[0:0];
  _RAND_50 = {1{`RANDOM}};
  reg_pmp_0_cfg_r = _RAND_50[0:0];
  _RAND_51 = {1{`RANDOM}};
  reg_pmp_0_addr = _RAND_51[28:0];
  _RAND_52 = {1{`RANDOM}};
  reg_pmp_1_cfg_l = _RAND_52[0:0];
  _RAND_53 = {1{`RANDOM}};
  reg_pmp_1_cfg_a = _RAND_53[1:0];
  _RAND_54 = {1{`RANDOM}};
  reg_pmp_1_cfg_x = _RAND_54[0:0];
  _RAND_55 = {1{`RANDOM}};
  reg_pmp_1_cfg_w = _RAND_55[0:0];
  _RAND_56 = {1{`RANDOM}};
  reg_pmp_1_cfg_r = _RAND_56[0:0];
  _RAND_57 = {1{`RANDOM}};
  reg_pmp_1_addr = _RAND_57[28:0];
  _RAND_58 = {1{`RANDOM}};
  reg_pmp_2_cfg_l = _RAND_58[0:0];
  _RAND_59 = {1{`RANDOM}};
  reg_pmp_2_cfg_a = _RAND_59[1:0];
  _RAND_60 = {1{`RANDOM}};
  reg_pmp_2_cfg_x = _RAND_60[0:0];
  _RAND_61 = {1{`RANDOM}};
  reg_pmp_2_cfg_w = _RAND_61[0:0];
  _RAND_62 = {1{`RANDOM}};
  reg_pmp_2_cfg_r = _RAND_62[0:0];
  _RAND_63 = {1{`RANDOM}};
  reg_pmp_2_addr = _RAND_63[28:0];
  _RAND_64 = {1{`RANDOM}};
  reg_pmp_3_cfg_l = _RAND_64[0:0];
  _RAND_65 = {1{`RANDOM}};
  reg_pmp_3_cfg_a = _RAND_65[1:0];
  _RAND_66 = {1{`RANDOM}};
  reg_pmp_3_cfg_x = _RAND_66[0:0];
  _RAND_67 = {1{`RANDOM}};
  reg_pmp_3_cfg_w = _RAND_67[0:0];
  _RAND_68 = {1{`RANDOM}};
  reg_pmp_3_cfg_r = _RAND_68[0:0];
  _RAND_69 = {1{`RANDOM}};
  reg_pmp_3_addr = _RAND_69[28:0];
  _RAND_70 = {1{`RANDOM}};
  reg_pmp_4_cfg_l = _RAND_70[0:0];
  _RAND_71 = {1{`RANDOM}};
  reg_pmp_4_cfg_a = _RAND_71[1:0];
  _RAND_72 = {1{`RANDOM}};
  reg_pmp_4_cfg_x = _RAND_72[0:0];
  _RAND_73 = {1{`RANDOM}};
  reg_pmp_4_cfg_w = _RAND_73[0:0];
  _RAND_74 = {1{`RANDOM}};
  reg_pmp_4_cfg_r = _RAND_74[0:0];
  _RAND_75 = {1{`RANDOM}};
  reg_pmp_4_addr = _RAND_75[28:0];
  _RAND_76 = {1{`RANDOM}};
  reg_pmp_5_cfg_l = _RAND_76[0:0];
  _RAND_77 = {1{`RANDOM}};
  reg_pmp_5_cfg_a = _RAND_77[1:0];
  _RAND_78 = {1{`RANDOM}};
  reg_pmp_5_cfg_x = _RAND_78[0:0];
  _RAND_79 = {1{`RANDOM}};
  reg_pmp_5_cfg_w = _RAND_79[0:0];
  _RAND_80 = {1{`RANDOM}};
  reg_pmp_5_cfg_r = _RAND_80[0:0];
  _RAND_81 = {1{`RANDOM}};
  reg_pmp_5_addr = _RAND_81[28:0];
  _RAND_82 = {1{`RANDOM}};
  reg_pmp_6_cfg_l = _RAND_82[0:0];
  _RAND_83 = {1{`RANDOM}};
  reg_pmp_6_cfg_a = _RAND_83[1:0];
  _RAND_84 = {1{`RANDOM}};
  reg_pmp_6_cfg_x = _RAND_84[0:0];
  _RAND_85 = {1{`RANDOM}};
  reg_pmp_6_cfg_w = _RAND_85[0:0];
  _RAND_86 = {1{`RANDOM}};
  reg_pmp_6_cfg_r = _RAND_86[0:0];
  _RAND_87 = {1{`RANDOM}};
  reg_pmp_6_addr = _RAND_87[28:0];
  _RAND_88 = {1{`RANDOM}};
  reg_pmp_7_cfg_l = _RAND_88[0:0];
  _RAND_89 = {1{`RANDOM}};
  reg_pmp_7_cfg_a = _RAND_89[1:0];
  _RAND_90 = {1{`RANDOM}};
  reg_pmp_7_cfg_x = _RAND_90[0:0];
  _RAND_91 = {1{`RANDOM}};
  reg_pmp_7_cfg_w = _RAND_91[0:0];
  _RAND_92 = {1{`RANDOM}};
  reg_pmp_7_cfg_r = _RAND_92[0:0];
  _RAND_93 = {1{`RANDOM}};
  reg_pmp_7_addr = _RAND_93[28:0];
  _RAND_94 = {1{`RANDOM}};
  reg_mie = _RAND_94[31:0];
  _RAND_95 = {1{`RANDOM}};
  reg_mip_seip = _RAND_95[0:0];
  _RAND_96 = {1{`RANDOM}};
  reg_mip_stip = _RAND_96[0:0];
  _RAND_97 = {1{`RANDOM}};
  reg_mip_ssip = _RAND_97[0:0];
  _RAND_98 = {1{`RANDOM}};
  reg_mepc = _RAND_98[31:0];
  _RAND_99 = {1{`RANDOM}};
  reg_mcause = _RAND_99[31:0];
  _RAND_100 = {1{`RANDOM}};
  reg_mtval = _RAND_100[31:0];
  _RAND_101 = {1{`RANDOM}};
  reg_mscratch = _RAND_101[31:0];
  _RAND_102 = {1{`RANDOM}};
  reg_mtvec = _RAND_102[30:0];
  _RAND_103 = {1{`RANDOM}};
  reg_mcounteren = _RAND_103[31:0];
  _RAND_104 = {1{`RANDOM}};
  reg_scounteren = _RAND_104[31:0];
  _RAND_105 = {1{`RANDOM}};
  reg_sepc = _RAND_105[31:0];
  _RAND_106 = {1{`RANDOM}};
  reg_scause = _RAND_106[31:0];
  _RAND_107 = {1{`RANDOM}};
  reg_stval = _RAND_107[31:0];
  _RAND_108 = {1{`RANDOM}};
  reg_sscratch = _RAND_108[31:0];
  _RAND_109 = {1{`RANDOM}};
  reg_stvec = _RAND_109[31:0];
  _RAND_110 = {1{`RANDOM}};
  reg_wfi = _RAND_110[0:0];
  _RAND_111 = {1{`RANDOM}};
  reg_mcountinhibit = _RAND_111[2:0];
  _RAND_112 = {1{`RANDOM}};
  small_ = _RAND_112[5:0];
  _RAND_113 = {2{`RANDOM}};
  large_ = _RAND_113[57:0];
  _RAND_114 = {1{`RANDOM}};
  small_1 = _RAND_114[5:0];
  _RAND_115 = {2{`RANDOM}};
  large_1 = _RAND_115[57:0];
  _RAND_116 = {1{`RANDOM}};
  reg_misa = _RAND_116[31:0];
  _RAND_117 = {1{`RANDOM}};
  reg_custom_0 = _RAND_117[31:0];
  _RAND_118 = {1{`RANDOM}};
  io_status_cease_r = _RAND_118[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module BreakpointUnit(
  input         io_status_debug,
  input  [1:0]  io_status_prv,
  input         io_bp_0_control_action,
  input         io_bp_0_control_chain,
  input  [1:0]  io_bp_0_control_tmatch,
  input         io_bp_0_control_m,
  input         io_bp_0_control_s,
  input         io_bp_0_control_u,
  input         io_bp_0_control_x,
  input         io_bp_0_control_w,
  input         io_bp_0_control_r,
  input  [31:0] io_bp_0_address,
  input         io_bp_1_control_action,
  input  [1:0]  io_bp_1_control_tmatch,
  input         io_bp_1_control_m,
  input         io_bp_1_control_s,
  input         io_bp_1_control_u,
  input         io_bp_1_control_x,
  input         io_bp_1_control_w,
  input         io_bp_1_control_r,
  input  [31:0] io_bp_1_address,
  input  [31:0] io_pc,
  input  [31:0] io_ea,
  output        io_xcpt_if,
  output        io_xcpt_ld,
  output        io_xcpt_st,
  output        io_debug_if,
  output        io_debug_ld,
  output        io_debug_st
);
  wire [3:0] _en_T_1 = {io_bp_0_control_m,1'h0,io_bp_0_control_s,io_bp_0_control_u}; // @[Cat.scala 31:58]
  wire [3:0] _en_T_2 = _en_T_1 >> io_status_prv; // @[Breakpoint.scala 31:68]
  wire  en = ~io_status_debug & _en_T_2[0]; // @[Breakpoint.scala 31:50]
  wire  _r_T_4 = io_ea >= io_bp_0_address ^ io_bp_0_control_tmatch[0]; // @[Breakpoint.scala 66:20]
  wire [31:0] _r_T_5 = ~io_ea; // @[Breakpoint.scala 63:6]
  wire  _r_T_8 = io_bp_0_control_tmatch[0] & io_bp_0_address[0]; // @[Breakpoint.scala 60:73]
  wire  _r_T_10 = io_bp_0_control_tmatch[0] & io_bp_0_address[0] & io_bp_0_address[1]; // @[Breakpoint.scala 60:73]
  wire  _r_T_12 = io_bp_0_control_tmatch[0] & io_bp_0_address[0] & io_bp_0_address[1] & io_bp_0_address[2]; // @[Breakpoint.scala 60:73]
  wire [3:0] _r_T_13 = {_r_T_12,_r_T_10,_r_T_8,io_bp_0_control_tmatch[0]}; // @[Cat.scala 31:58]
  wire [31:0] _GEN_22 = {{28'd0}, _r_T_13}; // @[Breakpoint.scala 63:9]
  wire [31:0] _r_T_14 = _r_T_5 | _GEN_22; // @[Breakpoint.scala 63:9]
  wire [31:0] _r_T_15 = ~io_bp_0_address; // @[Breakpoint.scala 63:24]
  wire [31:0] _r_T_24 = _r_T_15 | _GEN_22; // @[Breakpoint.scala 63:33]
  wire  _r_T_25 = _r_T_14 == _r_T_24; // @[Breakpoint.scala 63:19]
  wire  _r_T_26 = io_bp_0_control_tmatch[1] ? _r_T_4 : _r_T_25; // @[Breakpoint.scala 69:8]
  wire  r = en & io_bp_0_control_r & _r_T_26; // @[Breakpoint.scala 107:32]
  wire  w = en & io_bp_0_control_w & _r_T_26; // @[Breakpoint.scala 108:32]
  wire  _x_T_4 = io_pc >= io_bp_0_address ^ io_bp_0_control_tmatch[0]; // @[Breakpoint.scala 66:20]
  wire [31:0] _x_T_5 = ~io_pc; // @[Breakpoint.scala 63:6]
  wire [31:0] _x_T_14 = _x_T_5 | _GEN_22; // @[Breakpoint.scala 63:9]
  wire  _x_T_25 = _x_T_14 == _r_T_24; // @[Breakpoint.scala 63:19]
  wire  _x_T_26 = io_bp_0_control_tmatch[1] ? _x_T_4 : _x_T_25; // @[Breakpoint.scala 69:8]
  wire  x = en & io_bp_0_control_x & _x_T_26; // @[Breakpoint.scala 109:32]
  wire  end_ = ~io_bp_0_control_chain; // @[Breakpoint.scala 110:15]
  wire  _io_xcpt_ld_T = ~io_bp_0_control_action; // @[Breakpoint.scala 119:51]
  wire  _GEN_0 = end_ & r & ~io_bp_0_control_action; // @[Breakpoint.scala 119:{27,40} 98:14]
  wire  _GEN_1 = end_ & r & io_bp_0_control_action; // @[Breakpoint.scala 101:15 119:{27,73}]
  wire  _GEN_3 = end_ & w & _io_xcpt_ld_T; // @[Breakpoint.scala 120:{27,40} 99:14]
  wire  _GEN_4 = end_ & w & io_bp_0_control_action; // @[Breakpoint.scala 102:15 120:{27,73}]
  wire  _GEN_7 = end_ & x & _io_xcpt_ld_T; // @[Breakpoint.scala 121:{27,40} 97:14]
  wire  _GEN_8 = end_ & x & io_bp_0_control_action; // @[Breakpoint.scala 100:15 121:{27,73}]
  wire  _T_6 = end_ | r; // @[Breakpoint.scala 123:10]
  wire  _T_7 = end_ | w; // @[Breakpoint.scala 123:20]
  wire  _T_8 = end_ | x; // @[Breakpoint.scala 123:30]
  wire [3:0] _en_T_5 = {io_bp_1_control_m,1'h0,io_bp_1_control_s,io_bp_1_control_u}; // @[Cat.scala 31:58]
  wire [3:0] _en_T_6 = _en_T_5 >> io_status_prv; // @[Breakpoint.scala 31:68]
  wire  en_1 = ~io_status_debug & _en_T_6[0]; // @[Breakpoint.scala 31:50]
  wire  _r_T_32 = io_ea >= io_bp_1_address ^ io_bp_1_control_tmatch[0]; // @[Breakpoint.scala 66:20]
  wire  _r_T_36 = io_bp_1_control_tmatch[0] & io_bp_1_address[0]; // @[Breakpoint.scala 60:73]
  wire  _r_T_38 = io_bp_1_control_tmatch[0] & io_bp_1_address[0] & io_bp_1_address[1]; // @[Breakpoint.scala 60:73]
  wire  _r_T_40 = io_bp_1_control_tmatch[0] & io_bp_1_address[0] & io_bp_1_address[1] & io_bp_1_address[2]; // @[Breakpoint.scala 60:73]
  wire [3:0] _r_T_41 = {_r_T_40,_r_T_38,_r_T_36,io_bp_1_control_tmatch[0]}; // @[Cat.scala 31:58]
  wire [31:0] _GEN_28 = {{28'd0}, _r_T_41}; // @[Breakpoint.scala 63:9]
  wire [31:0] _r_T_42 = _r_T_5 | _GEN_28; // @[Breakpoint.scala 63:9]
  wire [31:0] _r_T_43 = ~io_bp_1_address; // @[Breakpoint.scala 63:24]
  wire [31:0] _r_T_52 = _r_T_43 | _GEN_28; // @[Breakpoint.scala 63:33]
  wire  _r_T_53 = _r_T_42 == _r_T_52; // @[Breakpoint.scala 63:19]
  wire  _r_T_54 = io_bp_1_control_tmatch[1] ? _r_T_32 : _r_T_53; // @[Breakpoint.scala 69:8]
  wire  r_1 = en_1 & io_bp_1_control_r & _r_T_54; // @[Breakpoint.scala 107:32]
  wire  w_1 = en_1 & io_bp_1_control_w & _r_T_54; // @[Breakpoint.scala 108:32]
  wire  _x_T_32 = io_pc >= io_bp_1_address ^ io_bp_1_control_tmatch[0]; // @[Breakpoint.scala 66:20]
  wire [31:0] _x_T_42 = _x_T_5 | _GEN_28; // @[Breakpoint.scala 63:9]
  wire  _x_T_53 = _x_T_42 == _r_T_52; // @[Breakpoint.scala 63:19]
  wire  _x_T_54 = io_bp_1_control_tmatch[1] ? _x_T_32 : _x_T_53; // @[Breakpoint.scala 69:8]
  wire  x_1 = en_1 & io_bp_1_control_x & _x_T_54; // @[Breakpoint.scala 109:32]
  wire  _io_xcpt_ld_T_1 = ~io_bp_1_control_action; // @[Breakpoint.scala 119:51]
  assign io_xcpt_if = x_1 & _T_8 ? _io_xcpt_ld_T_1 : _GEN_7; // @[Breakpoint.scala 121:{27,40}]
  assign io_xcpt_ld = r_1 & _T_6 ? ~io_bp_1_control_action : _GEN_0; // @[Breakpoint.scala 119:{27,40}]
  assign io_xcpt_st = w_1 & _T_7 ? _io_xcpt_ld_T_1 : _GEN_3; // @[Breakpoint.scala 120:{27,40}]
  assign io_debug_if = x_1 & _T_8 ? io_bp_1_control_action : _GEN_8; // @[Breakpoint.scala 121:{27,73}]
  assign io_debug_ld = r_1 & _T_6 ? io_bp_1_control_action : _GEN_1; // @[Breakpoint.scala 119:{27,73}]
  assign io_debug_st = w_1 & _T_7 ? io_bp_1_control_action : _GEN_4; // @[Breakpoint.scala 120:{27,73}]
endmodule
module ALU(
  input  [3:0]  io_fn,
  input  [31:0] io_in2,
  input  [31:0] io_in1,
  output [31:0] io_out,
  output [31:0] io_adder_out,
  output        io_cmp_out
);
  wire [31:0] _in2_inv_T_1 = ~io_in2; // @[ALU.scala 61:35]
  wire [31:0] in2_inv = io_fn[3] ? _in2_inv_T_1 : io_in2; // @[ALU.scala 61:20]
  wire [31:0] in1_xor_in2 = io_in1 ^ in2_inv; // @[ALU.scala 62:28]
  wire [31:0] _io_adder_out_T_1 = io_in1 + in2_inv; // @[ALU.scala 63:26]
  wire [31:0] _GEN_0 = {{31'd0}, io_fn[3]}; // @[ALU.scala 63:36]
  wire  _slt_T_7 = io_fn[1] ? io_in2[31] : io_in1[31]; // @[ALU.scala 68:8]
  wire  slt = io_in1[31] == io_in2[31] ? io_adder_out[31] : _slt_T_7; // @[ALU.scala 67:8]
  wire  _io_cmp_out_T_2 = ~io_fn[3]; // @[ALU.scala 44:26]
  wire  _io_cmp_out_T_4 = _io_cmp_out_T_2 ? in1_xor_in2 == 32'h0 : slt; // @[ALU.scala 69:41]
  wire [4:0] shamt = io_in2[4:0]; // @[ALU.scala 73:28]
  wire  _shin_T_2 = io_fn == 4'h5 | io_fn == 4'hb; // @[ALU.scala 81:35]
  wire [31:0] _GEN_1 = {{16'd0}, io_in1[31:16]}; // @[Bitwise.scala 105:31]
  wire [31:0] _shin_T_6 = _GEN_1 & 32'hffff; // @[Bitwise.scala 105:31]
  wire [31:0] _shin_T_8 = {io_in1[15:0], 16'h0}; // @[Bitwise.scala 105:70]
  wire [31:0] _shin_T_10 = _shin_T_8 & 32'hffff0000; // @[Bitwise.scala 105:80]
  wire [31:0] _shin_T_11 = _shin_T_6 | _shin_T_10; // @[Bitwise.scala 105:39]
  wire [31:0] _GEN_2 = {{8'd0}, _shin_T_11[31:8]}; // @[Bitwise.scala 105:31]
  wire [31:0] _shin_T_16 = _GEN_2 & 32'hff00ff; // @[Bitwise.scala 105:31]
  wire [31:0] _shin_T_18 = {_shin_T_11[23:0], 8'h0}; // @[Bitwise.scala 105:70]
  wire [31:0] _shin_T_20 = _shin_T_18 & 32'hff00ff00; // @[Bitwise.scala 105:80]
  wire [31:0] _shin_T_21 = _shin_T_16 | _shin_T_20; // @[Bitwise.scala 105:39]
  wire [31:0] _GEN_3 = {{4'd0}, _shin_T_21[31:4]}; // @[Bitwise.scala 105:31]
  wire [31:0] _shin_T_26 = _GEN_3 & 32'hf0f0f0f; // @[Bitwise.scala 105:31]
  wire [31:0] _shin_T_28 = {_shin_T_21[27:0], 4'h0}; // @[Bitwise.scala 105:70]
  wire [31:0] _shin_T_30 = _shin_T_28 & 32'hf0f0f0f0; // @[Bitwise.scala 105:80]
  wire [31:0] _shin_T_31 = _shin_T_26 | _shin_T_30; // @[Bitwise.scala 105:39]
  wire [31:0] _GEN_4 = {{2'd0}, _shin_T_31[31:2]}; // @[Bitwise.scala 105:31]
  wire [31:0] _shin_T_36 = _GEN_4 & 32'h33333333; // @[Bitwise.scala 105:31]
  wire [31:0] _shin_T_38 = {_shin_T_31[29:0], 2'h0}; // @[Bitwise.scala 105:70]
  wire [31:0] _shin_T_40 = _shin_T_38 & 32'hcccccccc; // @[Bitwise.scala 105:80]
  wire [31:0] _shin_T_41 = _shin_T_36 | _shin_T_40; // @[Bitwise.scala 105:39]
  wire [31:0] _GEN_5 = {{1'd0}, _shin_T_41[31:1]}; // @[Bitwise.scala 105:31]
  wire [31:0] _shin_T_46 = _GEN_5 & 32'h55555555; // @[Bitwise.scala 105:31]
  wire [31:0] _shin_T_48 = {_shin_T_41[30:0], 1'h0}; // @[Bitwise.scala 105:70]
  wire [31:0] _shin_T_50 = _shin_T_48 & 32'haaaaaaaa; // @[Bitwise.scala 105:80]
  wire [31:0] _shin_T_51 = _shin_T_46 | _shin_T_50; // @[Bitwise.scala 105:39]
  wire [31:0] shin = io_fn == 4'h5 | io_fn == 4'hb ? io_in1 : _shin_T_51; // @[ALU.scala 81:17]
  wire  _shout_r_T_2 = io_fn[3] & shin[31]; // @[ALU.scala 82:35]
  wire [32:0] _shout_r_T_4 = {_shout_r_T_2,shin}; // @[ALU.scala 82:57]
  wire [32:0] _shout_r_T_5 = $signed(_shout_r_T_4) >>> shamt; // @[ALU.scala 82:64]
  wire [31:0] shout_r = _shout_r_T_5[31:0]; // @[ALU.scala 82:73]
  wire [31:0] _GEN_6 = {{16'd0}, shout_r[31:16]}; // @[Bitwise.scala 105:31]
  wire [31:0] _shout_l_T_3 = _GEN_6 & 32'hffff; // @[Bitwise.scala 105:31]
  wire [31:0] _shout_l_T_5 = {shout_r[15:0], 16'h0}; // @[Bitwise.scala 105:70]
  wire [31:0] _shout_l_T_7 = _shout_l_T_5 & 32'hffff0000; // @[Bitwise.scala 105:80]
  wire [31:0] _shout_l_T_8 = _shout_l_T_3 | _shout_l_T_7; // @[Bitwise.scala 105:39]
  wire [31:0] _GEN_7 = {{8'd0}, _shout_l_T_8[31:8]}; // @[Bitwise.scala 105:31]
  wire [31:0] _shout_l_T_13 = _GEN_7 & 32'hff00ff; // @[Bitwise.scala 105:31]
  wire [31:0] _shout_l_T_15 = {_shout_l_T_8[23:0], 8'h0}; // @[Bitwise.scala 105:70]
  wire [31:0] _shout_l_T_17 = _shout_l_T_15 & 32'hff00ff00; // @[Bitwise.scala 105:80]
  wire [31:0] _shout_l_T_18 = _shout_l_T_13 | _shout_l_T_17; // @[Bitwise.scala 105:39]
  wire [31:0] _GEN_8 = {{4'd0}, _shout_l_T_18[31:4]}; // @[Bitwise.scala 105:31]
  wire [31:0] _shout_l_T_23 = _GEN_8 & 32'hf0f0f0f; // @[Bitwise.scala 105:31]
  wire [31:0] _shout_l_T_25 = {_shout_l_T_18[27:0], 4'h0}; // @[Bitwise.scala 105:70]
  wire [31:0] _shout_l_T_27 = _shout_l_T_25 & 32'hf0f0f0f0; // @[Bitwise.scala 105:80]
  wire [31:0] _shout_l_T_28 = _shout_l_T_23 | _shout_l_T_27; // @[Bitwise.scala 105:39]
  wire [31:0] _GEN_9 = {{2'd0}, _shout_l_T_28[31:2]}; // @[Bitwise.scala 105:31]
  wire [31:0] _shout_l_T_33 = _GEN_9 & 32'h33333333; // @[Bitwise.scala 105:31]
  wire [31:0] _shout_l_T_35 = {_shout_l_T_28[29:0], 2'h0}; // @[Bitwise.scala 105:70]
  wire [31:0] _shout_l_T_37 = _shout_l_T_35 & 32'hcccccccc; // @[Bitwise.scala 105:80]
  wire [31:0] _shout_l_T_38 = _shout_l_T_33 | _shout_l_T_37; // @[Bitwise.scala 105:39]
  wire [31:0] _GEN_10 = {{1'd0}, _shout_l_T_38[31:1]}; // @[Bitwise.scala 105:31]
  wire [31:0] _shout_l_T_43 = _GEN_10 & 32'h55555555; // @[Bitwise.scala 105:31]
  wire [31:0] _shout_l_T_45 = {_shout_l_T_38[30:0], 1'h0}; // @[Bitwise.scala 105:70]
  wire [31:0] _shout_l_T_47 = _shout_l_T_45 & 32'haaaaaaaa; // @[Bitwise.scala 105:80]
  wire [31:0] shout_l = _shout_l_T_43 | _shout_l_T_47; // @[Bitwise.scala 105:39]
  wire [31:0] _shout_T_3 = _shin_T_2 ? shout_r : 32'h0; // @[ALU.scala 84:18]
  wire [31:0] _shout_T_5 = io_fn == 4'h1 ? shout_l : 32'h0; // @[ALU.scala 85:18]
  wire [31:0] shout = _shout_T_3 | _shout_T_5; // @[ALU.scala 84:74]
  wire  _logic_T_1 = io_fn == 4'h6; // @[ALU.scala 88:45]
  wire [31:0] _logic_T_3 = io_fn == 4'h4 | io_fn == 4'h6 ? in1_xor_in2 : 32'h0; // @[ALU.scala 88:18]
  wire [31:0] _logic_T_7 = io_in1 & io_in2; // @[ALU.scala 89:63]
  wire [31:0] _logic_T_8 = _logic_T_1 | io_fn == 4'h7 ? _logic_T_7 : 32'h0; // @[ALU.scala 89:18]
  wire [31:0] logic_ = _logic_T_3 | _logic_T_8; // @[ALU.scala 88:78]
  wire  _shift_logic_T = io_fn >= 4'hc; // @[ALU.scala 41:30]
  wire  _shift_logic_T_1 = _shift_logic_T & slt; // @[ALU.scala 90:35]
  wire [31:0] _GEN_11 = {{31'd0}, _shift_logic_T_1}; // @[ALU.scala 90:43]
  wire [31:0] _shift_logic_T_2 = _GEN_11 | logic_; // @[ALU.scala 90:43]
  wire [31:0] shift_logic = _shift_logic_T_2 | shout; // @[ALU.scala 90:51]
  assign io_out = io_fn == 4'h0 | io_fn == 4'ha ? io_adder_out : shift_logic; // @[ALU.scala 91:16]
  assign io_adder_out = _io_adder_out_T_1 + _GEN_0; // @[ALU.scala 63:36]
  assign io_cmp_out = io_fn[0] ^ _io_cmp_out_T_4; // @[ALU.scala 69:36]
endmodule
module MulDiv(
  input         clock,
  input         reset,
  output        io_req_ready,
  input         io_req_valid,
  input  [3:0]  io_req_bits_fn,
  input  [31:0] io_req_bits_in1,
  input  [31:0] io_req_bits_in2,
  input  [4:0]  io_req_bits_tag,
  input         io_kill,
  input         io_resp_ready,
  output        io_resp_valid,
  output [31:0] io_resp_bits_data,
  output [4:0]  io_resp_bits_tag
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [63:0] _RAND_6;
  reg [95:0] _RAND_7;
`endif // RANDOMIZE_REG_INIT
  reg [2:0] state; // @[Multiplier.scala 50:22]
  reg [4:0] req_tag; // @[Multiplier.scala 52:16]
  reg [5:0] count; // @[Multiplier.scala 53:18]
  reg  neg_out; // @[Multiplier.scala 56:20]
  reg  isHi; // @[Multiplier.scala 57:17]
  reg  resHi; // @[Multiplier.scala 58:18]
  reg [32:0] divisor; // @[Multiplier.scala 59:20]
  reg [65:0] remainder; // @[Multiplier.scala 60:22]
  wire [3:0] _T = io_req_bits_fn & 4'h4; // @[Decode.scala 14:65]
  wire  cmdMul = _T == 4'h0; // @[Decode.scala 14:121]
  wire [3:0] _T_3 = io_req_bits_fn & 4'h5; // @[Decode.scala 14:65]
  wire  _T_4 = _T_3 == 4'h1; // @[Decode.scala 14:121]
  wire [3:0] _T_5 = io_req_bits_fn & 4'h2; // @[Decode.scala 14:65]
  wire  _T_6 = _T_5 == 4'h2; // @[Decode.scala 14:121]
  wire  cmdHi = _T_4 | _T_6; // @[Decode.scala 15:30]
  wire [3:0] _T_9 = io_req_bits_fn & 4'h6; // @[Decode.scala 14:65]
  wire  _T_10 = _T_9 == 4'h0; // @[Decode.scala 14:121]
  wire [3:0] _T_11 = io_req_bits_fn & 4'h1; // @[Decode.scala 14:65]
  wire  _T_12 = _T_11 == 4'h0; // @[Decode.scala 14:121]
  wire  lhsSigned = _T_10 | _T_12; // @[Decode.scala 15:30]
  wire  _T_16 = _T_3 == 4'h4; // @[Decode.scala 14:121]
  wire  rhsSigned = _T_10 | _T_16; // @[Decode.scala 15:30]
  wire  lhs_sign = lhsSigned & io_req_bits_in1[31]; // @[Multiplier.scala 80:23]
  wire [15:0] hi = io_req_bits_in1[31:16]; // @[Multiplier.scala 81:43]
  wire [31:0] lhs_in = {hi,io_req_bits_in1[15:0]}; // @[Cat.scala 31:58]
  wire  rhs_sign = rhsSigned & io_req_bits_in2[31]; // @[Multiplier.scala 80:23]
  wire [15:0] hi_1 = io_req_bits_in2[31:16]; // @[Multiplier.scala 81:43]
  wire [32:0] subtractor = remainder[64:32] - divisor; // @[Multiplier.scala 87:37]
  wire [31:0] result = resHi ? remainder[64:33] : remainder[31:0]; // @[Multiplier.scala 88:19]
  wire [31:0] negated_remainder = 32'h0 - result; // @[Multiplier.scala 89:27]
  wire [65:0] _GEN_0 = remainder[31] ? {{34'd0}, negated_remainder} : remainder; // @[Multiplier.scala 92:27 93:17 60:22]
  wire [65:0] _GEN_2 = state == 3'h1 ? _GEN_0 : remainder; // @[Multiplier.scala 60:22 91:57]
  wire [2:0] _GEN_4 = state == 3'h1 ? 3'h3 : state; // @[Multiplier.scala 91:57 98:11 50:22]
  wire [2:0] _GEN_6 = state == 3'h5 ? 3'h7 : _GEN_4; // @[Multiplier.scala 100:57 102:11]
  wire  _GEN_7 = state == 3'h5 ? 1'h0 : resHi; // @[Multiplier.scala 100:57 103:11 58:18]
  wire [64:0] mulReg = {remainder[65:33],remainder[31:0]}; // @[Cat.scala 31:58]
  wire  mplierSign = remainder[32]; // @[Multiplier.scala 107:31]
  wire [31:0] mplier = mulReg[31:0]; // @[Multiplier.scala 108:24]
  wire [32:0] accum = mulReg[64:32]; // @[Multiplier.scala 109:37]
  wire [8:0] _prod_T_2 = {mplierSign,mplier[7:0]}; // @[Multiplier.scala 111:60]
  wire [41:0] _prod_T_3 = $signed(_prod_T_2) * $signed(divisor); // @[Multiplier.scala 111:67]
  wire [41:0] _GEN_35 = {{9{accum[32]}},accum}; // @[Multiplier.scala 111:76]
  wire [41:0] nextMulReg_hi = $signed(_prod_T_3) + $signed(_GEN_35); // @[Cat.scala 31:58]
  wire [65:0] nextMulReg = {nextMulReg_hi,mplier[31:8]}; // @[Cat.scala 31:58]
  wire  nextMplierSign = count == 6'h2 & neg_out; // @[Multiplier.scala 113:57]
  wire  _eOut_T_4 = ~isHi; // @[Multiplier.scala 117:7]
  wire [64:0] nextMulReg1 = {nextMulReg[64:32],nextMulReg[31:0]}; // @[Cat.scala 31:58]
  wire [65:0] _remainder_T_2 = {nextMulReg1[64:32],nextMplierSign,nextMulReg1[31:0]}; // @[Cat.scala 31:58]
  wire [5:0] _count_T_1 = count + 6'h1; // @[Multiplier.scala 122:20]
  wire [2:0] _GEN_8 = count == 6'h3 ? 3'h6 : _GEN_6; // @[Multiplier.scala 123:51 124:13]
  wire  _GEN_9 = count == 6'h3 ? isHi : _GEN_7; // @[Multiplier.scala 123:51 125:13]
  wire [2:0] _GEN_12 = state == 3'h2 ? _GEN_8 : _GEN_6; // @[Multiplier.scala 105:50]
  wire  _GEN_13 = state == 3'h2 ? _GEN_9 : _GEN_7; // @[Multiplier.scala 105:50]
  wire  unrolls_less = subtractor[32]; // @[Multiplier.scala 132:28]
  wire [31:0] _unrolls_T_2 = unrolls_less ? remainder[63:32] : subtractor[31:0]; // @[Multiplier.scala 133:14]
  wire  _unrolls_T_4 = ~unrolls_less; // @[Multiplier.scala 133:67]
  wire [64:0] unrolls_0 = {_unrolls_T_2,remainder[31:0],_unrolls_T_4}; // @[Cat.scala 31:58]
  wire [2:0] _state_T = neg_out ? 3'h5 : 3'h7; // @[Multiplier.scala 138:19]
  wire [2:0] _GEN_14 = count == 6'h20 ? _state_T : _GEN_12; // @[Multiplier.scala 137:38 138:13]
  wire  divby0 = count == 6'h0 & _unrolls_T_4; // @[Multiplier.scala 145:30]
  wire  _T_36 = io_resp_ready & io_resp_valid; // @[Decoupled.scala 50:35]
  wire  _T_38 = io_req_ready & io_req_valid; // @[Decoupled.scala 50:35]
  wire [32:0] _divisor_T = {rhs_sign,hi_1,io_req_bits_in2[15:0]}; // @[Cat.scala 31:58]
  wire [15:0] loOut = result[15:0]; // @[Multiplier.scala 175:82]
  assign io_req_ready = state == 3'h0; // @[Multiplier.scala 181:25]
  assign io_resp_valid = state == 3'h6 | state == 3'h7; // @[Multiplier.scala 180:42]
  assign io_resp_bits_data = {result[31:16],loOut}; // @[Cat.scala 31:58]
  assign io_resp_bits_tag = req_tag; // @[Multiplier.scala 177:20]
  always @(posedge clock) begin
    if (reset) begin // @[Multiplier.scala 50:22]
      state <= 3'h0; // @[Multiplier.scala 50:22]
    end else if (_T_38) begin // @[Multiplier.scala 163:24]
      if (cmdMul) begin // @[Multiplier.scala 164:17]
        state <= 3'h2;
      end else if (lhs_sign | rhs_sign) begin // @[Multiplier.scala 164:36]
        state <= 3'h1;
      end else begin
        state <= 3'h3;
      end
    end else if (_T_36 | io_kill) begin // @[Multiplier.scala 160:36]
      state <= 3'h0; // @[Multiplier.scala 161:11]
    end else if (state == 3'h3) begin // @[Multiplier.scala 128:50]
      state <= _GEN_14;
    end else begin
      state <= _GEN_12;
    end
    if (_T_38) begin // @[Multiplier.scala 163:24]
      req_tag <= io_req_bits_tag; // @[Multiplier.scala 171:9]
    end
    if (_T_38) begin // @[Multiplier.scala 163:24]
      count <= 6'h0; // @[Multiplier.scala 167:11]
    end else if (state == 3'h3) begin // @[Multiplier.scala 128:50]
      count <= _count_T_1; // @[Multiplier.scala 143:11]
    end else if (state == 3'h2) begin // @[Multiplier.scala 105:50]
      count <= _count_T_1; // @[Multiplier.scala 122:11]
    end
    if (_T_38) begin // @[Multiplier.scala 163:24]
      if (cmdHi) begin // @[Multiplier.scala 168:19]
        neg_out <= lhs_sign;
      end else begin
        neg_out <= lhs_sign != rhs_sign;
      end
    end else if (state == 3'h3) begin // @[Multiplier.scala 128:50]
      if (divby0 & _eOut_T_4) begin // @[Multiplier.scala 158:28]
        neg_out <= 1'h0; // @[Multiplier.scala 158:38]
      end
    end
    if (_T_38) begin // @[Multiplier.scala 163:24]
      isHi <= cmdHi; // @[Multiplier.scala 165:10]
    end
    if (_T_38) begin // @[Multiplier.scala 163:24]
      resHi <= 1'h0; // @[Multiplier.scala 166:11]
    end else if (state == 3'h3) begin // @[Multiplier.scala 128:50]
      if (count == 6'h20) begin // @[Multiplier.scala 137:38]
        resHi <= isHi; // @[Multiplier.scala 139:13]
      end else begin
        resHi <= _GEN_13;
      end
    end else begin
      resHi <= _GEN_13;
    end
    if (_T_38) begin // @[Multiplier.scala 163:24]
      divisor <= _divisor_T; // @[Multiplier.scala 169:13]
    end else if (state == 3'h1) begin // @[Multiplier.scala 91:57]
      if (divisor[31]) begin // @[Multiplier.scala 95:25]
        divisor <= subtractor; // @[Multiplier.scala 96:15]
      end
    end
    if (_T_38) begin // @[Multiplier.scala 163:24]
      remainder <= {{34'd0}, lhs_in}; // @[Multiplier.scala 170:15]
    end else if (state == 3'h3) begin // @[Multiplier.scala 128:50]
      remainder <= {{1'd0}, unrolls_0}; // @[Multiplier.scala 136:15]
    end else if (state == 3'h2) begin // @[Multiplier.scala 105:50]
      remainder <= _remainder_T_2; // @[Multiplier.scala 120:15]
    end else if (state == 3'h5) begin // @[Multiplier.scala 100:57]
      remainder <= {{34'd0}, negated_remainder}; // @[Multiplier.scala 101:15]
    end else begin
      remainder <= _GEN_2;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  state = _RAND_0[2:0];
  _RAND_1 = {1{`RANDOM}};
  req_tag = _RAND_1[4:0];
  _RAND_2 = {1{`RANDOM}};
  count = _RAND_2[5:0];
  _RAND_3 = {1{`RANDOM}};
  neg_out = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  isHi = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  resHi = _RAND_5[0:0];
  _RAND_6 = {2{`RANDOM}};
  divisor = _RAND_6[32:0];
  _RAND_7 = {3{`RANDOM}};
  remainder = _RAND_7[65:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module PlusArgTimeout(
  input         clock,
  input         reset,
  input  [31:0] io_count
);
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 62:19]
  wire  _T = plusarg_reader_out > 32'h0; // @[PlusArg.scala 63:13]
  plusarg_reader #(.FORMAT("max_core_cycles=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 62:19]
    .out(plusarg_reader_out)
  );
  always @(posedge clock) begin
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(io_count < plusarg_reader_out) & (_T & ~reset)) begin
          $fatal; // @[PlusArg.scala 64:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T & ~reset & ~(io_count < plusarg_reader_out)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Timeout exceeded: Kill the emulation after INT rdtime cycles. Off if 0.\n    at PlusArg.scala:64 assert (io.count < max, s\"Timeout exceeded: $docstring\")\n"
            ); // @[PlusArg.scala 64:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
endmodule
module Rocket(
  input         clock,
  input         reset,
  input         io_hartid,
  input         io_interrupts_debug,
  input         io_interrupts_mtip,
  input         io_interrupts_msip,
  input         io_interrupts_meip,
  input         io_interrupts_seip,
  output        io_imem_might_request,
  output        io_imem_req_valid,
  output [31:0] io_imem_req_bits_pc,
  output        io_imem_req_bits_speculative,
  output        io_imem_resp_ready,
  input         io_imem_resp_valid,
  input         io_imem_resp_bits_btb_taken,
  input         io_imem_resp_bits_btb_bridx,
  input  [4:0]  io_imem_resp_bits_btb_entry,
  input  [7:0]  io_imem_resp_bits_btb_bht_history,
  input  [31:0] io_imem_resp_bits_pc,
  input  [31:0] io_imem_resp_bits_data,
  input         io_imem_resp_bits_xcpt_ae_inst,
  input         io_imem_resp_bits_replay,
  output        io_imem_btb_update_valid,
  output [4:0]  io_imem_btb_update_bits_prediction_entry,
  output [31:0] io_imem_btb_update_bits_pc,
  output        io_imem_btb_update_bits_isValid,
  output [31:0] io_imem_btb_update_bits_br_pc,
  output [1:0]  io_imem_btb_update_bits_cfiType,
  output        io_imem_bht_update_valid,
  output [7:0]  io_imem_bht_update_bits_prediction_history,
  output [31:0] io_imem_bht_update_bits_pc,
  output        io_imem_bht_update_bits_branch,
  output        io_imem_bht_update_bits_taken,
  output        io_imem_bht_update_bits_mispredict,
  output        io_imem_flush_icache,
  input         io_dmem_req_ready,
  output        io_dmem_req_valid,
  output [31:0] io_dmem_req_bits_addr,
  output [5:0]  io_dmem_req_bits_tag,
  output [4:0]  io_dmem_req_bits_cmd,
  output [1:0]  io_dmem_req_bits_size,
  output        io_dmem_req_bits_signed,
  output [1:0]  io_dmem_req_bits_dprv,
  output        io_dmem_req_bits_dv,
  output        io_dmem_s1_kill,
  output [31:0] io_dmem_s1_data_data,
  input         io_dmem_s2_nack,
  input         io_dmem_resp_valid,
  input  [5:0]  io_dmem_resp_bits_tag,
  input  [31:0] io_dmem_resp_bits_data,
  input         io_dmem_resp_bits_replay,
  input         io_dmem_resp_bits_has_data,
  input  [31:0] io_dmem_resp_bits_data_word_bypass,
  input         io_dmem_replay_next,
  input         io_dmem_s2_xcpt_ma_ld,
  input         io_dmem_s2_xcpt_ma_st,
  input         io_dmem_s2_xcpt_pf_ld,
  input         io_dmem_s2_xcpt_pf_st,
  input         io_dmem_s2_xcpt_ae_ld,
  input         io_dmem_s2_xcpt_ae_st,
  input         io_dmem_ordered,
  input         io_dmem_perf_release,
  input         io_dmem_perf_grant,
  output        io_ptw_status_debug,
  output [1:0]  io_ptw_status_prv,
  output        io_ptw_pmp_0_cfg_l,
  output [1:0]  io_ptw_pmp_0_cfg_a,
  output        io_ptw_pmp_0_cfg_x,
  output        io_ptw_pmp_0_cfg_w,
  output        io_ptw_pmp_0_cfg_r,
  output [28:0] io_ptw_pmp_0_addr,
  output [30:0] io_ptw_pmp_0_mask,
  output        io_ptw_pmp_1_cfg_l,
  output [1:0]  io_ptw_pmp_1_cfg_a,
  output        io_ptw_pmp_1_cfg_x,
  output        io_ptw_pmp_1_cfg_w,
  output        io_ptw_pmp_1_cfg_r,
  output [28:0] io_ptw_pmp_1_addr,
  output [30:0] io_ptw_pmp_1_mask,
  output        io_ptw_pmp_2_cfg_l,
  output [1:0]  io_ptw_pmp_2_cfg_a,
  output        io_ptw_pmp_2_cfg_x,
  output        io_ptw_pmp_2_cfg_w,
  output        io_ptw_pmp_2_cfg_r,
  output [28:0] io_ptw_pmp_2_addr,
  output [30:0] io_ptw_pmp_2_mask,
  output        io_ptw_pmp_3_cfg_l,
  output [1:0]  io_ptw_pmp_3_cfg_a,
  output        io_ptw_pmp_3_cfg_x,
  output        io_ptw_pmp_3_cfg_w,
  output        io_ptw_pmp_3_cfg_r,
  output [28:0] io_ptw_pmp_3_addr,
  output [30:0] io_ptw_pmp_3_mask,
  output        io_ptw_pmp_4_cfg_l,
  output [1:0]  io_ptw_pmp_4_cfg_a,
  output        io_ptw_pmp_4_cfg_x,
  output        io_ptw_pmp_4_cfg_w,
  output        io_ptw_pmp_4_cfg_r,
  output [28:0] io_ptw_pmp_4_addr,
  output [30:0] io_ptw_pmp_4_mask,
  output        io_ptw_pmp_5_cfg_l,
  output [1:0]  io_ptw_pmp_5_cfg_a,
  output        io_ptw_pmp_5_cfg_x,
  output        io_ptw_pmp_5_cfg_w,
  output        io_ptw_pmp_5_cfg_r,
  output [28:0] io_ptw_pmp_5_addr,
  output [30:0] io_ptw_pmp_5_mask,
  output        io_ptw_pmp_6_cfg_l,
  output [1:0]  io_ptw_pmp_6_cfg_a,
  output        io_ptw_pmp_6_cfg_x,
  output        io_ptw_pmp_6_cfg_w,
  output        io_ptw_pmp_6_cfg_r,
  output [28:0] io_ptw_pmp_6_addr,
  output [30:0] io_ptw_pmp_6_mask,
  output        io_ptw_pmp_7_cfg_l,
  output [1:0]  io_ptw_pmp_7_cfg_a,
  output        io_ptw_pmp_7_cfg_x,
  output        io_ptw_pmp_7_cfg_w,
  output        io_ptw_pmp_7_cfg_r,
  output [28:0] io_ptw_pmp_7_addr,
  output [30:0] io_ptw_pmp_7_mask,
  output [31:0] io_ptw_customCSRs_csrs_0_value,
  output        io_wfi
);
`ifdef RANDOMIZE_GARBAGE_ASSIGN
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif // RANDOMIZE_GARBAGE_ASSIGN
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [31:0] _RAND_33;
  reg [31:0] _RAND_34;
  reg [31:0] _RAND_35;
  reg [31:0] _RAND_36;
  reg [31:0] _RAND_37;
  reg [31:0] _RAND_38;
  reg [31:0] _RAND_39;
  reg [31:0] _RAND_40;
  reg [31:0] _RAND_41;
  reg [31:0] _RAND_42;
  reg [31:0] _RAND_43;
  reg [31:0] _RAND_44;
  reg [31:0] _RAND_45;
  reg [31:0] _RAND_46;
  reg [31:0] _RAND_47;
  reg [31:0] _RAND_48;
  reg [31:0] _RAND_49;
  reg [31:0] _RAND_50;
  reg [31:0] _RAND_51;
  reg [31:0] _RAND_52;
  reg [31:0] _RAND_53;
  reg [31:0] _RAND_54;
  reg [31:0] _RAND_55;
  reg [31:0] _RAND_56;
  reg [31:0] _RAND_57;
  reg [31:0] _RAND_58;
  reg [31:0] _RAND_59;
  reg [31:0] _RAND_60;
  reg [31:0] _RAND_61;
  reg [31:0] _RAND_62;
  reg [31:0] _RAND_63;
  reg [31:0] _RAND_64;
  reg [31:0] _RAND_65;
  reg [31:0] _RAND_66;
  reg [31:0] _RAND_67;
  reg [31:0] _RAND_68;
  reg [31:0] _RAND_69;
  reg [31:0] _RAND_70;
  reg [31:0] _RAND_71;
  reg [31:0] _RAND_72;
  reg [31:0] _RAND_73;
  reg [31:0] _RAND_74;
  reg [31:0] _RAND_75;
  reg [31:0] _RAND_76;
  reg [31:0] _RAND_77;
  reg [31:0] _RAND_78;
  reg [31:0] _RAND_79;
  reg [31:0] _RAND_80;
  reg [31:0] _RAND_81;
  reg [31:0] _RAND_82;
  reg [31:0] _RAND_83;
  reg [31:0] _RAND_84;
  reg [31:0] _RAND_85;
  reg [31:0] _RAND_86;
  reg [31:0] _RAND_87;
  reg [31:0] _RAND_88;
  reg [31:0] _RAND_89;
  reg [31:0] _RAND_90;
  reg [31:0] _RAND_91;
  reg [31:0] _RAND_92;
  reg [31:0] _RAND_93;
`endif // RANDOMIZE_REG_INIT
  wire  ibuf_clock; // @[RocketCore.scala 263:20]
  wire  ibuf_reset; // @[RocketCore.scala 263:20]
  wire  ibuf_io_imem_ready; // @[RocketCore.scala 263:20]
  wire  ibuf_io_imem_valid; // @[RocketCore.scala 263:20]
  wire  ibuf_io_imem_bits_btb_taken; // @[RocketCore.scala 263:20]
  wire  ibuf_io_imem_bits_btb_bridx; // @[RocketCore.scala 263:20]
  wire [4:0] ibuf_io_imem_bits_btb_entry; // @[RocketCore.scala 263:20]
  wire [7:0] ibuf_io_imem_bits_btb_bht_history; // @[RocketCore.scala 263:20]
  wire [31:0] ibuf_io_imem_bits_pc; // @[RocketCore.scala 263:20]
  wire [31:0] ibuf_io_imem_bits_data; // @[RocketCore.scala 263:20]
  wire  ibuf_io_imem_bits_xcpt_ae_inst; // @[RocketCore.scala 263:20]
  wire  ibuf_io_imem_bits_replay; // @[RocketCore.scala 263:20]
  wire  ibuf_io_kill; // @[RocketCore.scala 263:20]
  wire [31:0] ibuf_io_pc; // @[RocketCore.scala 263:20]
  wire [4:0] ibuf_io_btb_resp_entry; // @[RocketCore.scala 263:20]
  wire [7:0] ibuf_io_btb_resp_bht_history; // @[RocketCore.scala 263:20]
  wire  ibuf_io_inst_0_ready; // @[RocketCore.scala 263:20]
  wire  ibuf_io_inst_0_valid; // @[RocketCore.scala 263:20]
  wire  ibuf_io_inst_0_bits_xcpt0_ae_inst; // @[RocketCore.scala 263:20]
  wire  ibuf_io_inst_0_bits_xcpt1_pf_inst; // @[RocketCore.scala 263:20]
  wire  ibuf_io_inst_0_bits_xcpt1_gf_inst; // @[RocketCore.scala 263:20]
  wire  ibuf_io_inst_0_bits_xcpt1_ae_inst; // @[RocketCore.scala 263:20]
  wire  ibuf_io_inst_0_bits_replay; // @[RocketCore.scala 263:20]
  wire  ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala 263:20]
  wire [31:0] ibuf_io_inst_0_bits_inst_bits; // @[RocketCore.scala 263:20]
  wire [4:0] ibuf_io_inst_0_bits_inst_rd; // @[RocketCore.scala 263:20]
  wire [4:0] ibuf_io_inst_0_bits_inst_rs1; // @[RocketCore.scala 263:20]
  wire [4:0] ibuf_io_inst_0_bits_inst_rs2; // @[RocketCore.scala 263:20]
  wire [31:0] ibuf_io_inst_0_bits_raw; // @[RocketCore.scala 263:20]
  reg [31:0] rf [0:30]; // @[RocketCore.scala 1061:15]
  wire  rf_id_rs_MPORT_en; // @[RocketCore.scala 1061:15]
  wire [4:0] rf_id_rs_MPORT_addr; // @[RocketCore.scala 1061:15]
  wire [31:0] rf_id_rs_MPORT_data; // @[RocketCore.scala 1061:15]
  wire  rf_id_rs_MPORT_1_en; // @[RocketCore.scala 1061:15]
  wire [4:0] rf_id_rs_MPORT_1_addr; // @[RocketCore.scala 1061:15]
  wire [31:0] rf_id_rs_MPORT_1_data; // @[RocketCore.scala 1061:15]
  wire [31:0] rf_MPORT_data; // @[RocketCore.scala 1061:15]
  wire [4:0] rf_MPORT_addr; // @[RocketCore.scala 1061:15]
  wire  rf_MPORT_mask; // @[RocketCore.scala 1061:15]
  wire  rf_MPORT_en; // @[RocketCore.scala 1061:15]
  wire  csr_clock; // @[RocketCore.scala 291:19]
  wire  csr_reset; // @[RocketCore.scala 291:19]
  wire  csr_io_ungated_clock; // @[RocketCore.scala 291:19]
  wire  csr_io_interrupts_debug; // @[RocketCore.scala 291:19]
  wire  csr_io_interrupts_mtip; // @[RocketCore.scala 291:19]
  wire  csr_io_interrupts_msip; // @[RocketCore.scala 291:19]
  wire  csr_io_interrupts_meip; // @[RocketCore.scala 291:19]
  wire  csr_io_interrupts_seip; // @[RocketCore.scala 291:19]
  wire  csr_io_hartid; // @[RocketCore.scala 291:19]
  wire [11:0] csr_io_rw_addr; // @[RocketCore.scala 291:19]
  wire [2:0] csr_io_rw_cmd; // @[RocketCore.scala 291:19]
  wire [31:0] csr_io_rw_rdata; // @[RocketCore.scala 291:19]
  wire [31:0] csr_io_rw_wdata; // @[RocketCore.scala 291:19]
  wire [31:0] csr_io_decode_0_inst; // @[RocketCore.scala 291:19]
  wire  csr_io_decode_0_fp_illegal; // @[RocketCore.scala 291:19]
  wire  csr_io_decode_0_fp_csr; // @[RocketCore.scala 291:19]
  wire  csr_io_decode_0_read_illegal; // @[RocketCore.scala 291:19]
  wire  csr_io_decode_0_write_illegal; // @[RocketCore.scala 291:19]
  wire  csr_io_decode_0_write_flush; // @[RocketCore.scala 291:19]
  wire  csr_io_decode_0_system_illegal; // @[RocketCore.scala 291:19]
  wire  csr_io_csr_stall; // @[RocketCore.scala 291:19]
  wire  csr_io_eret; // @[RocketCore.scala 291:19]
  wire  csr_io_singleStep; // @[RocketCore.scala 291:19]
  wire  csr_io_status_debug; // @[RocketCore.scala 291:19]
  wire  csr_io_status_cease; // @[RocketCore.scala 291:19]
  wire  csr_io_status_wfi; // @[RocketCore.scala 291:19]
  wire [31:0] csr_io_status_isa; // @[RocketCore.scala 291:19]
  wire [1:0] csr_io_status_dprv; // @[RocketCore.scala 291:19]
  wire  csr_io_status_dv; // @[RocketCore.scala 291:19]
  wire [1:0] csr_io_status_prv; // @[RocketCore.scala 291:19]
  wire  csr_io_status_v; // @[RocketCore.scala 291:19]
  wire  csr_io_status_sd; // @[RocketCore.scala 291:19]
  wire [22:0] csr_io_status_zero2; // @[RocketCore.scala 291:19]
  wire  csr_io_status_mpv; // @[RocketCore.scala 291:19]
  wire  csr_io_status_gva; // @[RocketCore.scala 291:19]
  wire  csr_io_status_mbe; // @[RocketCore.scala 291:19]
  wire  csr_io_status_sbe; // @[RocketCore.scala 291:19]
  wire [1:0] csr_io_status_sxl; // @[RocketCore.scala 291:19]
  wire [1:0] csr_io_status_uxl; // @[RocketCore.scala 291:19]
  wire  csr_io_status_sd_rv32; // @[RocketCore.scala 291:19]
  wire [7:0] csr_io_status_zero1; // @[RocketCore.scala 291:19]
  wire  csr_io_status_tsr; // @[RocketCore.scala 291:19]
  wire  csr_io_status_tw; // @[RocketCore.scala 291:19]
  wire  csr_io_status_tvm; // @[RocketCore.scala 291:19]
  wire  csr_io_status_mxr; // @[RocketCore.scala 291:19]
  wire  csr_io_status_sum; // @[RocketCore.scala 291:19]
  wire  csr_io_status_mprv; // @[RocketCore.scala 291:19]
  wire [1:0] csr_io_status_xs; // @[RocketCore.scala 291:19]
  wire [1:0] csr_io_status_fs; // @[RocketCore.scala 291:19]
  wire [1:0] csr_io_status_mpp; // @[RocketCore.scala 291:19]
  wire [1:0] csr_io_status_vs; // @[RocketCore.scala 291:19]
  wire  csr_io_status_spp; // @[RocketCore.scala 291:19]
  wire  csr_io_status_mpie; // @[RocketCore.scala 291:19]
  wire  csr_io_status_ube; // @[RocketCore.scala 291:19]
  wire  csr_io_status_spie; // @[RocketCore.scala 291:19]
  wire  csr_io_status_upie; // @[RocketCore.scala 291:19]
  wire  csr_io_status_mie; // @[RocketCore.scala 291:19]
  wire  csr_io_status_hie; // @[RocketCore.scala 291:19]
  wire  csr_io_status_sie; // @[RocketCore.scala 291:19]
  wire  csr_io_status_uie; // @[RocketCore.scala 291:19]
  wire [31:0] csr_io_evec; // @[RocketCore.scala 291:19]
  wire  csr_io_exception; // @[RocketCore.scala 291:19]
  wire  csr_io_retire; // @[RocketCore.scala 291:19]
  wire [31:0] csr_io_cause; // @[RocketCore.scala 291:19]
  wire [31:0] csr_io_pc; // @[RocketCore.scala 291:19]
  wire [31:0] csr_io_tval; // @[RocketCore.scala 291:19]
  wire  csr_io_gva; // @[RocketCore.scala 291:19]
  wire [31:0] csr_io_time; // @[RocketCore.scala 291:19]
  wire  csr_io_interrupt; // @[RocketCore.scala 291:19]
  wire [31:0] csr_io_interrupt_cause; // @[RocketCore.scala 291:19]
  wire  csr_io_bp_0_control_action; // @[RocketCore.scala 291:19]
  wire  csr_io_bp_0_control_chain; // @[RocketCore.scala 291:19]
  wire [1:0] csr_io_bp_0_control_tmatch; // @[RocketCore.scala 291:19]
  wire  csr_io_bp_0_control_m; // @[RocketCore.scala 291:19]
  wire  csr_io_bp_0_control_s; // @[RocketCore.scala 291:19]
  wire  csr_io_bp_0_control_u; // @[RocketCore.scala 291:19]
  wire  csr_io_bp_0_control_x; // @[RocketCore.scala 291:19]
  wire  csr_io_bp_0_control_w; // @[RocketCore.scala 291:19]
  wire  csr_io_bp_0_control_r; // @[RocketCore.scala 291:19]
  wire [31:0] csr_io_bp_0_address; // @[RocketCore.scala 291:19]
  wire  csr_io_bp_1_control_action; // @[RocketCore.scala 291:19]
  wire [1:0] csr_io_bp_1_control_tmatch; // @[RocketCore.scala 291:19]
  wire  csr_io_bp_1_control_m; // @[RocketCore.scala 291:19]
  wire  csr_io_bp_1_control_s; // @[RocketCore.scala 291:19]
  wire  csr_io_bp_1_control_u; // @[RocketCore.scala 291:19]
  wire  csr_io_bp_1_control_x; // @[RocketCore.scala 291:19]
  wire  csr_io_bp_1_control_w; // @[RocketCore.scala 291:19]
  wire  csr_io_bp_1_control_r; // @[RocketCore.scala 291:19]
  wire [31:0] csr_io_bp_1_address; // @[RocketCore.scala 291:19]
  wire  csr_io_pmp_0_cfg_l; // @[RocketCore.scala 291:19]
  wire [1:0] csr_io_pmp_0_cfg_a; // @[RocketCore.scala 291:19]
  wire  csr_io_pmp_0_cfg_x; // @[RocketCore.scala 291:19]
  wire  csr_io_pmp_0_cfg_w; // @[RocketCore.scala 291:19]
  wire  csr_io_pmp_0_cfg_r; // @[RocketCore.scala 291:19]
  wire [28:0] csr_io_pmp_0_addr; // @[RocketCore.scala 291:19]
  wire [30:0] csr_io_pmp_0_mask; // @[RocketCore.scala 291:19]
  wire  csr_io_pmp_1_cfg_l; // @[RocketCore.scala 291:19]
  wire [1:0] csr_io_pmp_1_cfg_a; // @[RocketCore.scala 291:19]
  wire  csr_io_pmp_1_cfg_x; // @[RocketCore.scala 291:19]
  wire  csr_io_pmp_1_cfg_w; // @[RocketCore.scala 291:19]
  wire  csr_io_pmp_1_cfg_r; // @[RocketCore.scala 291:19]
  wire [28:0] csr_io_pmp_1_addr; // @[RocketCore.scala 291:19]
  wire [30:0] csr_io_pmp_1_mask; // @[RocketCore.scala 291:19]
  wire  csr_io_pmp_2_cfg_l; // @[RocketCore.scala 291:19]
  wire [1:0] csr_io_pmp_2_cfg_a; // @[RocketCore.scala 291:19]
  wire  csr_io_pmp_2_cfg_x; // @[RocketCore.scala 291:19]
  wire  csr_io_pmp_2_cfg_w; // @[RocketCore.scala 291:19]
  wire  csr_io_pmp_2_cfg_r; // @[RocketCore.scala 291:19]
  wire [28:0] csr_io_pmp_2_addr; // @[RocketCore.scala 291:19]
  wire [30:0] csr_io_pmp_2_mask; // @[RocketCore.scala 291:19]
  wire  csr_io_pmp_3_cfg_l; // @[RocketCore.scala 291:19]
  wire [1:0] csr_io_pmp_3_cfg_a; // @[RocketCore.scala 291:19]
  wire  csr_io_pmp_3_cfg_x; // @[RocketCore.scala 291:19]
  wire  csr_io_pmp_3_cfg_w; // @[RocketCore.scala 291:19]
  wire  csr_io_pmp_3_cfg_r; // @[RocketCore.scala 291:19]
  wire [28:0] csr_io_pmp_3_addr; // @[RocketCore.scala 291:19]
  wire [30:0] csr_io_pmp_3_mask; // @[RocketCore.scala 291:19]
  wire  csr_io_pmp_4_cfg_l; // @[RocketCore.scala 291:19]
  wire [1:0] csr_io_pmp_4_cfg_a; // @[RocketCore.scala 291:19]
  wire  csr_io_pmp_4_cfg_x; // @[RocketCore.scala 291:19]
  wire  csr_io_pmp_4_cfg_w; // @[RocketCore.scala 291:19]
  wire  csr_io_pmp_4_cfg_r; // @[RocketCore.scala 291:19]
  wire [28:0] csr_io_pmp_4_addr; // @[RocketCore.scala 291:19]
  wire [30:0] csr_io_pmp_4_mask; // @[RocketCore.scala 291:19]
  wire  csr_io_pmp_5_cfg_l; // @[RocketCore.scala 291:19]
  wire [1:0] csr_io_pmp_5_cfg_a; // @[RocketCore.scala 291:19]
  wire  csr_io_pmp_5_cfg_x; // @[RocketCore.scala 291:19]
  wire  csr_io_pmp_5_cfg_w; // @[RocketCore.scala 291:19]
  wire  csr_io_pmp_5_cfg_r; // @[RocketCore.scala 291:19]
  wire [28:0] csr_io_pmp_5_addr; // @[RocketCore.scala 291:19]
  wire [30:0] csr_io_pmp_5_mask; // @[RocketCore.scala 291:19]
  wire  csr_io_pmp_6_cfg_l; // @[RocketCore.scala 291:19]
  wire [1:0] csr_io_pmp_6_cfg_a; // @[RocketCore.scala 291:19]
  wire  csr_io_pmp_6_cfg_x; // @[RocketCore.scala 291:19]
  wire  csr_io_pmp_6_cfg_w; // @[RocketCore.scala 291:19]
  wire  csr_io_pmp_6_cfg_r; // @[RocketCore.scala 291:19]
  wire [28:0] csr_io_pmp_6_addr; // @[RocketCore.scala 291:19]
  wire [30:0] csr_io_pmp_6_mask; // @[RocketCore.scala 291:19]
  wire  csr_io_pmp_7_cfg_l; // @[RocketCore.scala 291:19]
  wire [1:0] csr_io_pmp_7_cfg_a; // @[RocketCore.scala 291:19]
  wire  csr_io_pmp_7_cfg_x; // @[RocketCore.scala 291:19]
  wire  csr_io_pmp_7_cfg_w; // @[RocketCore.scala 291:19]
  wire  csr_io_pmp_7_cfg_r; // @[RocketCore.scala 291:19]
  wire [28:0] csr_io_pmp_7_addr; // @[RocketCore.scala 291:19]
  wire [30:0] csr_io_pmp_7_mask; // @[RocketCore.scala 291:19]
  wire  csr_io_inhibit_cycle; // @[RocketCore.scala 291:19]
  wire [31:0] csr_io_inst_0; // @[RocketCore.scala 291:19]
  wire  csr_io_trace_0_valid; // @[RocketCore.scala 291:19]
  wire [31:0] csr_io_trace_0_iaddr; // @[RocketCore.scala 291:19]
  wire [31:0] csr_io_trace_0_insn; // @[RocketCore.scala 291:19]
  wire  csr_io_trace_0_exception; // @[RocketCore.scala 291:19]
  wire [31:0] csr_io_customCSRs_0_value; // @[RocketCore.scala 291:19]
  wire  bpu_io_status_debug; // @[RocketCore.scala 334:19]
  wire [1:0] bpu_io_status_prv; // @[RocketCore.scala 334:19]
  wire  bpu_io_bp_0_control_action; // @[RocketCore.scala 334:19]
  wire  bpu_io_bp_0_control_chain; // @[RocketCore.scala 334:19]
  wire [1:0] bpu_io_bp_0_control_tmatch; // @[RocketCore.scala 334:19]
  wire  bpu_io_bp_0_control_m; // @[RocketCore.scala 334:19]
  wire  bpu_io_bp_0_control_s; // @[RocketCore.scala 334:19]
  wire  bpu_io_bp_0_control_u; // @[RocketCore.scala 334:19]
  wire  bpu_io_bp_0_control_x; // @[RocketCore.scala 334:19]
  wire  bpu_io_bp_0_control_w; // @[RocketCore.scala 334:19]
  wire  bpu_io_bp_0_control_r; // @[RocketCore.scala 334:19]
  wire [31:0] bpu_io_bp_0_address; // @[RocketCore.scala 334:19]
  wire  bpu_io_bp_1_control_action; // @[RocketCore.scala 334:19]
  wire [1:0] bpu_io_bp_1_control_tmatch; // @[RocketCore.scala 334:19]
  wire  bpu_io_bp_1_control_m; // @[RocketCore.scala 334:19]
  wire  bpu_io_bp_1_control_s; // @[RocketCore.scala 334:19]
  wire  bpu_io_bp_1_control_u; // @[RocketCore.scala 334:19]
  wire  bpu_io_bp_1_control_x; // @[RocketCore.scala 334:19]
  wire  bpu_io_bp_1_control_w; // @[RocketCore.scala 334:19]
  wire  bpu_io_bp_1_control_r; // @[RocketCore.scala 334:19]
  wire [31:0] bpu_io_bp_1_address; // @[RocketCore.scala 334:19]
  wire [31:0] bpu_io_pc; // @[RocketCore.scala 334:19]
  wire [31:0] bpu_io_ea; // @[RocketCore.scala 334:19]
  wire  bpu_io_xcpt_if; // @[RocketCore.scala 334:19]
  wire  bpu_io_xcpt_ld; // @[RocketCore.scala 334:19]
  wire  bpu_io_xcpt_st; // @[RocketCore.scala 334:19]
  wire  bpu_io_debug_if; // @[RocketCore.scala 334:19]
  wire  bpu_io_debug_ld; // @[RocketCore.scala 334:19]
  wire  bpu_io_debug_st; // @[RocketCore.scala 334:19]
  wire [3:0] alu_io_fn; // @[RocketCore.scala 399:19]
  wire [31:0] alu_io_in2; // @[RocketCore.scala 399:19]
  wire [31:0] alu_io_in1; // @[RocketCore.scala 399:19]
  wire [31:0] alu_io_out; // @[RocketCore.scala 399:19]
  wire [31:0] alu_io_adder_out; // @[RocketCore.scala 399:19]
  wire  alu_io_cmp_out; // @[RocketCore.scala 399:19]
  wire  div_clock; // @[RocketCore.scala 423:19]
  wire  div_reset; // @[RocketCore.scala 423:19]
  wire  div_io_req_ready; // @[RocketCore.scala 423:19]
  wire  div_io_req_valid; // @[RocketCore.scala 423:19]
  wire [3:0] div_io_req_bits_fn; // @[RocketCore.scala 423:19]
  wire [31:0] div_io_req_bits_in1; // @[RocketCore.scala 423:19]
  wire [31:0] div_io_req_bits_in2; // @[RocketCore.scala 423:19]
  wire [4:0] div_io_req_bits_tag; // @[RocketCore.scala 423:19]
  wire  div_io_kill; // @[RocketCore.scala 423:19]
  wire  div_io_resp_ready; // @[RocketCore.scala 423:19]
  wire  div_io_resp_valid; // @[RocketCore.scala 423:19]
  wire [31:0] div_io_resp_bits_data; // @[RocketCore.scala 423:19]
  wire [4:0] div_io_resp_bits_tag; // @[RocketCore.scala 423:19]
  wire  PlusArgTimeout_clock; // @[PlusArg.scala 89:11]
  wire  PlusArgTimeout_reset; // @[PlusArg.scala 89:11]
  wire [31:0] PlusArgTimeout_io_count; // @[PlusArg.scala 89:11]
  reg  id_reg_pause; // @[RocketCore.scala 116:25]
  reg  imem_might_request_reg; // @[RocketCore.scala 117:35]
  reg  ex_ctrl_branch; // @[RocketCore.scala 194:20]
  reg  ex_ctrl_jal; // @[RocketCore.scala 194:20]
  reg  ex_ctrl_jalr; // @[RocketCore.scala 194:20]
  reg  ex_ctrl_rxs2; // @[RocketCore.scala 194:20]
  reg  ex_ctrl_rxs1; // @[RocketCore.scala 194:20]
  reg [1:0] ex_ctrl_sel_alu2; // @[RocketCore.scala 194:20]
  reg [1:0] ex_ctrl_sel_alu1; // @[RocketCore.scala 194:20]
  reg [2:0] ex_ctrl_sel_imm; // @[RocketCore.scala 194:20]
  reg [3:0] ex_ctrl_alu_fn; // @[RocketCore.scala 194:20]
  reg  ex_ctrl_mem; // @[RocketCore.scala 194:20]
  reg [4:0] ex_ctrl_mem_cmd; // @[RocketCore.scala 194:20]
  reg  ex_ctrl_div; // @[RocketCore.scala 194:20]
  reg  ex_ctrl_wxd; // @[RocketCore.scala 194:20]
  reg [2:0] ex_ctrl_csr; // @[RocketCore.scala 194:20]
  reg  ex_ctrl_fence_i; // @[RocketCore.scala 194:20]
  reg  mem_ctrl_branch; // @[RocketCore.scala 195:21]
  reg  mem_ctrl_jal; // @[RocketCore.scala 195:21]
  reg  mem_ctrl_jalr; // @[RocketCore.scala 195:21]
  reg  mem_ctrl_rxs2; // @[RocketCore.scala 195:21]
  reg  mem_ctrl_rxs1; // @[RocketCore.scala 195:21]
  reg  mem_ctrl_mem; // @[RocketCore.scala 195:21]
  reg  mem_ctrl_div; // @[RocketCore.scala 195:21]
  reg  mem_ctrl_wxd; // @[RocketCore.scala 195:21]
  reg [2:0] mem_ctrl_csr; // @[RocketCore.scala 195:21]
  reg  mem_ctrl_fence_i; // @[RocketCore.scala 195:21]
  reg  wb_ctrl_rxs2; // @[RocketCore.scala 196:20]
  reg  wb_ctrl_rxs1; // @[RocketCore.scala 196:20]
  reg  wb_ctrl_mem; // @[RocketCore.scala 196:20]
  reg  wb_ctrl_div; // @[RocketCore.scala 196:20]
  reg  wb_ctrl_wxd; // @[RocketCore.scala 196:20]
  reg [2:0] wb_ctrl_csr; // @[RocketCore.scala 196:20]
  reg  wb_ctrl_fence_i; // @[RocketCore.scala 196:20]
  reg  ex_reg_xcpt_interrupt; // @[RocketCore.scala 198:35]
  reg  ex_reg_valid; // @[RocketCore.scala 199:35]
  reg  ex_reg_rvc; // @[RocketCore.scala 200:35]
  reg [4:0] ex_reg_btb_resp_entry; // @[RocketCore.scala 201:35]
  reg [7:0] ex_reg_btb_resp_bht_history; // @[RocketCore.scala 201:35]
  reg  ex_reg_xcpt; // @[RocketCore.scala 202:35]
  reg  ex_reg_flush_pipe; // @[RocketCore.scala 203:35]
  reg  ex_reg_load_use; // @[RocketCore.scala 204:35]
  reg [31:0] ex_reg_cause; // @[RocketCore.scala 205:35]
  reg  ex_reg_replay; // @[RocketCore.scala 206:26]
  reg [31:0] ex_reg_pc; // @[RocketCore.scala 207:22]
  reg [1:0] ex_reg_mem_size; // @[RocketCore.scala 208:28]
  reg [31:0] ex_reg_inst; // @[RocketCore.scala 210:24]
  reg [31:0] ex_reg_raw_inst; // @[RocketCore.scala 211:28]
  reg  mem_reg_xcpt_interrupt; // @[RocketCore.scala 216:36]
  reg  mem_reg_valid; // @[RocketCore.scala 217:36]
  reg  mem_reg_rvc; // @[RocketCore.scala 218:36]
  reg [4:0] mem_reg_btb_resp_entry; // @[RocketCore.scala 219:36]
  reg [7:0] mem_reg_btb_resp_bht_history; // @[RocketCore.scala 219:36]
  reg  mem_reg_xcpt; // @[RocketCore.scala 220:36]
  reg  mem_reg_replay; // @[RocketCore.scala 221:36]
  reg  mem_reg_flush_pipe; // @[RocketCore.scala 222:36]
  reg [31:0] mem_reg_cause; // @[RocketCore.scala 223:36]
  reg  mem_reg_slow_bypass; // @[RocketCore.scala 224:36]
  reg  mem_reg_load; // @[RocketCore.scala 225:36]
  reg  mem_reg_store; // @[RocketCore.scala 226:36]
  reg [31:0] mem_reg_pc; // @[RocketCore.scala 228:23]
  reg [31:0] mem_reg_inst; // @[RocketCore.scala 229:25]
  reg  mem_reg_hls_or_dv; // @[RocketCore.scala 231:30]
  reg [31:0] mem_reg_raw_inst; // @[RocketCore.scala 232:29]
  reg [31:0] mem_reg_wdata; // @[RocketCore.scala 235:26]
  reg [31:0] mem_reg_rs2; // @[RocketCore.scala 236:24]
  reg  mem_br_taken; // @[RocketCore.scala 237:25]
  reg  wb_reg_valid; // @[RocketCore.scala 241:35]
  reg  wb_reg_xcpt; // @[RocketCore.scala 242:35]
  reg  wb_reg_replay; // @[RocketCore.scala 243:35]
  reg  wb_reg_flush_pipe; // @[RocketCore.scala 244:35]
  reg [31:0] wb_reg_cause; // @[RocketCore.scala 245:35]
  reg [31:0] wb_reg_pc; // @[RocketCore.scala 247:22]
  reg  wb_reg_hls_or_dv; // @[RocketCore.scala 249:29]
  reg [31:0] wb_reg_inst; // @[RocketCore.scala 252:24]
  reg [31:0] wb_reg_raw_inst; // @[RocketCore.scala 253:28]
  reg [31:0] wb_reg_wdata; // @[RocketCore.scala 254:25]
  wire  replay_wb_common = io_dmem_s2_nack | wb_reg_replay; // @[RocketCore.scala 664:42]
  wire  _T_94 = wb_reg_valid & wb_ctrl_mem; // @[RocketCore.scala 637:19]
  wire  _T_95 = wb_reg_valid & wb_ctrl_mem & io_dmem_s2_xcpt_pf_st; // @[RocketCore.scala 637:34]
  wire  _T_97 = _T_94 & io_dmem_s2_xcpt_pf_ld; // @[RocketCore.scala 638:34]
  wire  _T_103 = _T_94 & io_dmem_s2_xcpt_ae_st; // @[RocketCore.scala 641:34]
  wire  _T_105 = _T_94 & io_dmem_s2_xcpt_ae_ld; // @[RocketCore.scala 642:34]
  wire  _T_107 = _T_94 & io_dmem_s2_xcpt_ma_st; // @[RocketCore.scala 643:34]
  wire  _T_109 = _T_94 & io_dmem_s2_xcpt_ma_ld; // @[RocketCore.scala 644:34]
  wire  wb_xcpt = wb_reg_xcpt | _T_95 | _T_97 | _T_103 | _T_105 | _T_107 | _T_109; // @[RocketCore.scala 1021:26]
  wire  take_pc_wb = replay_wb_common | wb_xcpt | csr_io_eret | wb_reg_flush_pipe; // @[RocketCore.scala 667:53]
  wire  _take_pc_mem_T = ~mem_reg_xcpt; // @[RocketCore.scala 541:35]
  wire  ex_pc_valid = ex_reg_valid | ex_reg_replay | ex_reg_xcpt_interrupt; // @[RocketCore.scala 508:51]
  wire  _mem_br_target_T_1 = mem_ctrl_branch & mem_br_taken; // @[RocketCore.scala 528:25]
  wire  mem_br_target_sign = mem_reg_inst[31]; // @[RocketCore.scala 1083:53]
  wire  mem_br_target_hi_hi_hi = mem_reg_inst[31]; // @[Cat.scala 31:58]
  wire [10:0] mem_br_target_hi_hi_lo = {11{mem_br_target_sign}}; // @[Cat.scala 31:58]
  wire [7:0] mem_br_target_hi_lo_hi = {8{mem_br_target_sign}}; // @[Cat.scala 31:58]
  wire  mem_br_target_hi_lo_lo = mem_reg_inst[7]; // @[Cat.scala 31:58]
  wire [5:0] mem_br_target_b10_5 = mem_reg_inst[30:25]; // @[RocketCore.scala 1089:66]
  wire [3:0] mem_br_target_b4_1 = mem_reg_inst[11:8]; // @[RocketCore.scala 1091:57]
  wire [31:0] _mem_br_target_T_3 = {mem_br_target_hi_hi_hi,mem_br_target_hi_hi_lo,mem_br_target_hi_lo_hi,
    mem_br_target_hi_lo_lo,mem_br_target_b10_5,mem_br_target_b4_1,1'h0}; // @[RocketCore.scala 1097:53]
  wire [7:0] mem_br_target_hi_lo_hi_1 = mem_reg_inst[19:12]; // @[Cat.scala 31:58]
  wire  mem_br_target_hi_lo_lo_1 = mem_reg_inst[20]; // @[Cat.scala 31:58]
  wire [31:0] _mem_br_target_T_5 = {mem_br_target_hi_hi_hi,mem_br_target_hi_hi_lo,mem_br_target_hi_lo_hi_1,
    mem_br_target_hi_lo_lo_1,mem_br_target_b10_5,mem_reg_inst[24:21],1'h0}; // @[RocketCore.scala 1097:53]
  wire [3:0] _mem_br_target_T_6 = mem_reg_rvc ? $signed(4'sh2) : $signed(4'sh4); // @[RocketCore.scala 530:8]
  wire [31:0] _mem_br_target_T_7 = mem_ctrl_jal ? $signed(_mem_br_target_T_5) : $signed({{28{_mem_br_target_T_6[3]}},
    _mem_br_target_T_6}); // @[RocketCore.scala 529:8]
  wire [31:0] _mem_br_target_T_8 = mem_ctrl_branch & mem_br_taken ? $signed(_mem_br_target_T_3) : $signed(
    _mem_br_target_T_7); // @[RocketCore.scala 528:8]
  wire [31:0] mem_br_target = $signed(mem_reg_pc) + $signed(_mem_br_target_T_8); // @[RocketCore.scala 527:41]
  wire [31:0] _mem_npc_T_2 = mem_ctrl_jalr ? $signed(mem_reg_wdata) : $signed(mem_br_target); // @[RocketCore.scala 531:21]
  wire [31:0] mem_npc = $signed(_mem_npc_T_2) & -32'sh2; // @[RocketCore.scala 531:141]
  wire  _mem_wrong_npc_T_3 = ibuf_io_inst_0_valid | ibuf_io_imem_valid ? mem_npc != ibuf_io_pc : 1'h1; // @[RocketCore.scala 534:8]
  wire  mem_wrong_npc = ex_pc_valid ? mem_npc != ex_reg_pc : _mem_wrong_npc_T_3; // @[RocketCore.scala 533:8]
  wire  take_pc_mem = mem_reg_valid & ~mem_reg_xcpt & mem_wrong_npc; // @[RocketCore.scala 541:49]
  wire  take_pc_mem_wb = take_pc_wb | take_pc_mem; // @[RocketCore.scala 259:35]
  wire [31:0] _id_ctrl_decoder_bit_T = ibuf_io_inst_0_bits_inst_bits & 32'hfe00707f; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_bit_T_1 = _id_ctrl_decoder_bit_T == 32'h2000033; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_3 = _id_ctrl_decoder_bit_T == 32'h2001033; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_5 = _id_ctrl_decoder_bit_T == 32'h2003033; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_7 = _id_ctrl_decoder_bit_T == 32'h2002033; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_9 = _id_ctrl_decoder_bit_T == 32'h2004033; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_11 = _id_ctrl_decoder_bit_T == 32'h2005033; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_13 = _id_ctrl_decoder_bit_T == 32'h2006033; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_15 = _id_ctrl_decoder_bit_T == 32'h2007033; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_bit_T_16 = ibuf_io_inst_0_bits_inst_bits & 32'hf800707f; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_bit_T_17 = _id_ctrl_decoder_bit_T_16 == 32'h202f; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_19 = _id_ctrl_decoder_bit_T_16 == 32'h2000202f; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_21 = _id_ctrl_decoder_bit_T_16 == 32'h800202f; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_23 = _id_ctrl_decoder_bit_T_16 == 32'h6000202f; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_25 = _id_ctrl_decoder_bit_T_16 == 32'h4000202f; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_27 = _id_ctrl_decoder_bit_T_16 == 32'h8000202f; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_29 = _id_ctrl_decoder_bit_T_16 == 32'hc000202f; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_31 = _id_ctrl_decoder_bit_T_16 == 32'ha000202f; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_33 = _id_ctrl_decoder_bit_T_16 == 32'he000202f; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_bit_T_34 = ibuf_io_inst_0_bits_inst_bits & 32'hf9f0707f; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_bit_T_35 = _id_ctrl_decoder_bit_T_34 == 32'h1000202f; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_37 = _id_ctrl_decoder_bit_T_16 == 32'h1800202f; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_39 = _id_ctrl_decoder_bit_T == 32'h1013; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_41 = _id_ctrl_decoder_bit_T == 32'h5013; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_43 = _id_ctrl_decoder_bit_T == 32'h40005013; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_44 = ibuf_io_inst_0_bits_inst_bits == 32'h10200073; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_45 = ibuf_io_inst_0_bits_inst_bits == 32'h7b200073; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_bit_T_46 = ibuf_io_inst_0_bits_inst_bits & 32'h707f; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_bit_T_47 = _id_ctrl_decoder_bit_T_46 == 32'h100f; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_49 = _id_ctrl_decoder_bit_T_46 == 32'h1063; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_51 = _id_ctrl_decoder_bit_T_46 == 32'h63; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_53 = _id_ctrl_decoder_bit_T_46 == 32'h4063; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_55 = _id_ctrl_decoder_bit_T_46 == 32'h6063; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_57 = _id_ctrl_decoder_bit_T_46 == 32'h5063; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_59 = _id_ctrl_decoder_bit_T_46 == 32'h7063; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_bit_T_60 = ibuf_io_inst_0_bits_inst_bits & 32'h7f; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_bit_T_61 = _id_ctrl_decoder_bit_T_60 == 32'h6f; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_63 = _id_ctrl_decoder_bit_T_46 == 32'h67; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_65 = _id_ctrl_decoder_bit_T_60 == 32'h17; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_67 = _id_ctrl_decoder_bit_T_46 == 32'h3; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_69 = _id_ctrl_decoder_bit_T_46 == 32'h1003; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_71 = _id_ctrl_decoder_bit_T_46 == 32'h2003; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_73 = _id_ctrl_decoder_bit_T_46 == 32'h4003; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_75 = _id_ctrl_decoder_bit_T_46 == 32'h5003; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_77 = _id_ctrl_decoder_bit_T_46 == 32'h23; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_79 = _id_ctrl_decoder_bit_T_46 == 32'h1023; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_81 = _id_ctrl_decoder_bit_T_46 == 32'h2023; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_83 = _id_ctrl_decoder_bit_T_60 == 32'h37; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_85 = _id_ctrl_decoder_bit_T_46 == 32'h13; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_87 = _id_ctrl_decoder_bit_T_46 == 32'h2013; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_89 = _id_ctrl_decoder_bit_T_46 == 32'h3013; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_91 = _id_ctrl_decoder_bit_T_46 == 32'h7013; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_93 = _id_ctrl_decoder_bit_T_46 == 32'h6013; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_95 = _id_ctrl_decoder_bit_T_46 == 32'h4013; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_97 = _id_ctrl_decoder_bit_T == 32'h33; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_99 = _id_ctrl_decoder_bit_T == 32'h40000033; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_101 = _id_ctrl_decoder_bit_T == 32'h2033; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_103 = _id_ctrl_decoder_bit_T == 32'h3033; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_105 = _id_ctrl_decoder_bit_T == 32'h7033; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_107 = _id_ctrl_decoder_bit_T == 32'h6033; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_109 = _id_ctrl_decoder_bit_T == 32'h4033; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_111 = _id_ctrl_decoder_bit_T == 32'h1033; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_113 = _id_ctrl_decoder_bit_T == 32'h5033; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_115 = _id_ctrl_decoder_bit_T == 32'h40005033; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_117 = _id_ctrl_decoder_bit_T_46 == 32'hf; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_118 = ibuf_io_inst_0_bits_inst_bits == 32'h73; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_119 = ibuf_io_inst_0_bits_inst_bits == 32'h100073; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_120 = ibuf_io_inst_0_bits_inst_bits == 32'h30200073; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_121 = ibuf_io_inst_0_bits_inst_bits == 32'h10500073; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_122 = ibuf_io_inst_0_bits_inst_bits == 32'h30500073; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_124 = _id_ctrl_decoder_bit_T_46 == 32'h1073; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_126 = _id_ctrl_decoder_bit_T_46 == 32'h2073; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_128 = _id_ctrl_decoder_bit_T_46 == 32'h3073; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_130 = _id_ctrl_decoder_bit_T_46 == 32'h5073; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_132 = _id_ctrl_decoder_bit_T_46 == 32'h6073; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_134 = _id_ctrl_decoder_bit_T_46 == 32'h7073; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_bit_T_165 = _id_ctrl_decoder_bit_T_1 | _id_ctrl_decoder_bit_T_3 | _id_ctrl_decoder_bit_T_5 |
    _id_ctrl_decoder_bit_T_7 | _id_ctrl_decoder_bit_T_9 | _id_ctrl_decoder_bit_T_11 | _id_ctrl_decoder_bit_T_13 |
    _id_ctrl_decoder_bit_T_15 | _id_ctrl_decoder_bit_T_17 | _id_ctrl_decoder_bit_T_19 | _id_ctrl_decoder_bit_T_21 |
    _id_ctrl_decoder_bit_T_23 | _id_ctrl_decoder_bit_T_25 | _id_ctrl_decoder_bit_T_27 | _id_ctrl_decoder_bit_T_29 |
    _id_ctrl_decoder_bit_T_31 | _id_ctrl_decoder_bit_T_33 | _id_ctrl_decoder_bit_T_35 | _id_ctrl_decoder_bit_T_37 |
    _id_ctrl_decoder_bit_T_39 | _id_ctrl_decoder_bit_T_41 | _id_ctrl_decoder_bit_T_43 | _id_ctrl_decoder_bit_T_44 |
    _id_ctrl_decoder_bit_T_45 | _id_ctrl_decoder_bit_T_47 | _id_ctrl_decoder_bit_T_49 | _id_ctrl_decoder_bit_T_51 |
    _id_ctrl_decoder_bit_T_53 | _id_ctrl_decoder_bit_T_55 | _id_ctrl_decoder_bit_T_57 | _id_ctrl_decoder_bit_T_59; // @[Decode.scala 15:30]
  wire  _id_ctrl_decoder_bit_T_195 = _id_ctrl_decoder_bit_T_165 | _id_ctrl_decoder_bit_T_61 | _id_ctrl_decoder_bit_T_63
     | _id_ctrl_decoder_bit_T_65 | _id_ctrl_decoder_bit_T_67 | _id_ctrl_decoder_bit_T_69 | _id_ctrl_decoder_bit_T_71 |
    _id_ctrl_decoder_bit_T_73 | _id_ctrl_decoder_bit_T_75 | _id_ctrl_decoder_bit_T_77 | _id_ctrl_decoder_bit_T_79 |
    _id_ctrl_decoder_bit_T_81 | _id_ctrl_decoder_bit_T_83 | _id_ctrl_decoder_bit_T_85 | _id_ctrl_decoder_bit_T_87 |
    _id_ctrl_decoder_bit_T_89 | _id_ctrl_decoder_bit_T_91 | _id_ctrl_decoder_bit_T_93 | _id_ctrl_decoder_bit_T_95 |
    _id_ctrl_decoder_bit_T_97 | _id_ctrl_decoder_bit_T_99 | _id_ctrl_decoder_bit_T_101 | _id_ctrl_decoder_bit_T_103 |
    _id_ctrl_decoder_bit_T_105 | _id_ctrl_decoder_bit_T_107 | _id_ctrl_decoder_bit_T_109 | _id_ctrl_decoder_bit_T_111 |
    _id_ctrl_decoder_bit_T_113 | _id_ctrl_decoder_bit_T_115 | _id_ctrl_decoder_bit_T_117 | _id_ctrl_decoder_bit_T_118; // @[Decode.scala 15:30]
  wire  id_ctrl_decoder_0 = _id_ctrl_decoder_bit_T_195 | _id_ctrl_decoder_bit_T_119 | _id_ctrl_decoder_bit_T_120 |
    _id_ctrl_decoder_bit_T_121 | _id_ctrl_decoder_bit_T_122 | _id_ctrl_decoder_bit_T_124 | _id_ctrl_decoder_bit_T_126 |
    _id_ctrl_decoder_bit_T_128 | _id_ctrl_decoder_bit_T_130 | _id_ctrl_decoder_bit_T_132 | _id_ctrl_decoder_bit_T_134; // @[Decode.scala 15:30]
  wire [31:0] _id_ctrl_decoder_T = ibuf_io_inst_0_bits_inst_bits & 32'h54; // @[Decode.scala 14:65]
  wire  id_ctrl_decoder_3 = _id_ctrl_decoder_T == 32'h40; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_T_2 = ibuf_io_inst_0_bits_inst_bits & 32'h48; // @[Decode.scala 14:65]
  wire  id_ctrl_decoder_4 = _id_ctrl_decoder_T_2 == 32'h48; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_T_4 = ibuf_io_inst_0_bits_inst_bits & 32'h1c; // @[Decode.scala 14:65]
  wire  id_ctrl_decoder_5 = _id_ctrl_decoder_T_4 == 32'h4; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_T_6 = ibuf_io_inst_0_bits_inst_bits & 32'h70; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_7 = _id_ctrl_decoder_T_6 == 32'h20; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_T_8 = ibuf_io_inst_0_bits_inst_bits & 32'h64; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_9 = _id_ctrl_decoder_T_8 == 32'h20; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_T_10 = ibuf_io_inst_0_bits_inst_bits & 32'h34; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_11 = _id_ctrl_decoder_T_10 == 32'h20; // @[Decode.scala 14:121]
  wire  id_ctrl_decoder_6 = _id_ctrl_decoder_T_7 | _id_ctrl_decoder_T_9 | _id_ctrl_decoder_T_11; // @[Decode.scala 15:30]
  wire [31:0] _id_ctrl_decoder_T_14 = ibuf_io_inst_0_bits_inst_bits & 32'h4004; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_15 = _id_ctrl_decoder_T_14 == 32'h0; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_T_16 = ibuf_io_inst_0_bits_inst_bits & 32'h44; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_17 = _id_ctrl_decoder_T_16 == 32'h0; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_T_18 = ibuf_io_inst_0_bits_inst_bits & 32'h18; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_19 = _id_ctrl_decoder_T_18 == 32'h0; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_T_20 = ibuf_io_inst_0_bits_inst_bits & 32'h2050; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_21 = _id_ctrl_decoder_T_20 == 32'h2000; // @[Decode.scala 14:121]
  wire  id_ctrl_decoder_7 = _id_ctrl_decoder_T_15 | _id_ctrl_decoder_T_17 | _id_ctrl_decoder_T_19 |
    _id_ctrl_decoder_T_21; // @[Decode.scala 15:30]
  wire [31:0] _id_ctrl_decoder_T_25 = ibuf_io_inst_0_bits_inst_bits & 32'h58; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_26 = _id_ctrl_decoder_T_25 == 32'h0; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_T_27 = ibuf_io_inst_0_bits_inst_bits & 32'h20; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_28 = _id_ctrl_decoder_T_27 == 32'h0; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_T_29 = ibuf_io_inst_0_bits_inst_bits & 32'hc; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_30 = _id_ctrl_decoder_T_29 == 32'h4; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_T_31 = ibuf_io_inst_0_bits_inst_bits & 32'h4050; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_32 = _id_ctrl_decoder_T_31 == 32'h4050; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_T_37 = _id_ctrl_decoder_T_26 | _id_ctrl_decoder_T_28 | _id_ctrl_decoder_T_30 |
    id_ctrl_decoder_4 | _id_ctrl_decoder_T_32; // @[Decode.scala 15:30]
  wire  _id_ctrl_decoder_T_39 = _id_ctrl_decoder_T_2 == 32'h0; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_T_40 = ibuf_io_inst_0_bits_inst_bits & 32'h4008; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_41 = _id_ctrl_decoder_T_40 == 32'h4000; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_T_44 = _id_ctrl_decoder_T_39 | _id_ctrl_decoder_T_19 | _id_ctrl_decoder_T_41; // @[Decode.scala 15:30]
  wire [1:0] id_ctrl_decoder_9 = {_id_ctrl_decoder_T_44,_id_ctrl_decoder_T_37}; // @[Cat.scala 31:58]
  wire [31:0] _id_ctrl_decoder_T_45 = ibuf_io_inst_0_bits_inst_bits & 32'h50; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_46 = _id_ctrl_decoder_T_45 == 32'h0; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_T_50 = _id_ctrl_decoder_T_15 | _id_ctrl_decoder_T_46 | _id_ctrl_decoder_T_17 |
    _id_ctrl_decoder_T_19; // @[Decode.scala 15:30]
  wire [31:0] _id_ctrl_decoder_T_51 = ibuf_io_inst_0_bits_inst_bits & 32'h24; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_52 = _id_ctrl_decoder_T_51 == 32'h4; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_T_54 = _id_ctrl_decoder_T_52 | id_ctrl_decoder_4; // @[Decode.scala 15:30]
  wire [1:0] id_ctrl_decoder_10 = {_id_ctrl_decoder_T_54,_id_ctrl_decoder_T_50}; // @[Cat.scala 31:58]
  wire [31:0] _id_ctrl_decoder_T_55 = ibuf_io_inst_0_bits_inst_bits & 32'h8; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_56 = _id_ctrl_decoder_T_55 == 32'h8; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_T_58 = _id_ctrl_decoder_T_16 == 32'h40; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_T_60 = _id_ctrl_decoder_T_56 | _id_ctrl_decoder_T_58; // @[Decode.scala 15:30]
  wire  _id_ctrl_decoder_T_62 = _id_ctrl_decoder_T_16 == 32'h4; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_T_64 = _id_ctrl_decoder_T_62 | _id_ctrl_decoder_T_56; // @[Decode.scala 15:30]
  wire [31:0] _id_ctrl_decoder_T_65 = ibuf_io_inst_0_bits_inst_bits & 32'h14; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_66 = _id_ctrl_decoder_T_65 == 32'h10; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_T_67 = ibuf_io_inst_0_bits_inst_bits & 32'h30; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_68 = _id_ctrl_decoder_T_67 == 32'h0; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_T_71 = id_ctrl_decoder_5 | _id_ctrl_decoder_T_66 | _id_ctrl_decoder_T_68; // @[Decode.scala 15:30]
  wire [2:0] id_ctrl_decoder_11 = {_id_ctrl_decoder_T_71,_id_ctrl_decoder_T_64,_id_ctrl_decoder_T_60}; // @[Cat.scala 31:58]
  wire [31:0] _id_ctrl_decoder_T_74 = ibuf_io_inst_0_bits_inst_bits & 32'h3054; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_75 = _id_ctrl_decoder_T_74 == 32'h1010; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_T_76 = ibuf_io_inst_0_bits_inst_bits & 32'h1058; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_77 = _id_ctrl_decoder_T_76 == 32'h1040; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_T_78 = ibuf_io_inst_0_bits_inst_bits & 32'h7044; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_79 = _id_ctrl_decoder_T_78 == 32'h7000; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_T_80 = ibuf_io_inst_0_bits_inst_bits & 32'h2001074; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_81 = _id_ctrl_decoder_T_80 == 32'h2001030; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_T_85 = _id_ctrl_decoder_T_75 | _id_ctrl_decoder_T_77 | _id_ctrl_decoder_T_79 |
    _id_ctrl_decoder_T_81; // @[Decode.scala 15:30]
  wire [31:0] _id_ctrl_decoder_T_86 = ibuf_io_inst_0_bits_inst_bits & 32'h4054; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_87 = _id_ctrl_decoder_T_86 == 32'h40; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_T_88 = ibuf_io_inst_0_bits_inst_bits & 32'h3044; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_89 = _id_ctrl_decoder_T_88 == 32'h3000; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_T_90 = ibuf_io_inst_0_bits_inst_bits & 32'h6044; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_91 = _id_ctrl_decoder_T_90 == 32'h6000; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_T_92 = ibuf_io_inst_0_bits_inst_bits & 32'h6018; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_93 = _id_ctrl_decoder_T_92 == 32'h6000; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_T_94 = ibuf_io_inst_0_bits_inst_bits & 32'h2002074; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_95 = _id_ctrl_decoder_T_94 == 32'h2002030; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_T_96 = ibuf_io_inst_0_bits_inst_bits & 32'h40003034; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_97 = _id_ctrl_decoder_T_96 == 32'h40000030; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_T_98 = ibuf_io_inst_0_bits_inst_bits & 32'h40001054; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_99 = _id_ctrl_decoder_T_98 == 32'h40001010; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_T_106 = _id_ctrl_decoder_T_87 | _id_ctrl_decoder_T_89 | _id_ctrl_decoder_T_91 |
    _id_ctrl_decoder_T_93 | _id_ctrl_decoder_T_95 | _id_ctrl_decoder_T_97 | _id_ctrl_decoder_T_99; // @[Decode.scala 15:30]
  wire [31:0] _id_ctrl_decoder_T_107 = ibuf_io_inst_0_bits_inst_bits & 32'h2002054; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_108 = _id_ctrl_decoder_T_107 == 32'h2010; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_T_109 = ibuf_io_inst_0_bits_inst_bits & 32'h2034; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_110 = _id_ctrl_decoder_T_109 == 32'h2010; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_T_111 = ibuf_io_inst_0_bits_inst_bits & 32'h40004054; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_112 = _id_ctrl_decoder_T_111 == 32'h4010; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_T_113 = ibuf_io_inst_0_bits_inst_bits & 32'h5054; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_114 = _id_ctrl_decoder_T_113 == 32'h4010; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_T_115 = ibuf_io_inst_0_bits_inst_bits & 32'h4058; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_116 = _id_ctrl_decoder_T_115 == 32'h4040; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_T_121 = _id_ctrl_decoder_T_108 | _id_ctrl_decoder_T_110 | _id_ctrl_decoder_T_112 |
    _id_ctrl_decoder_T_114 | _id_ctrl_decoder_T_116; // @[Decode.scala 15:30]
  wire [31:0] _id_ctrl_decoder_T_122 = ibuf_io_inst_0_bits_inst_bits & 32'h2006054; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_123 = _id_ctrl_decoder_T_122 == 32'h2010; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_T_124 = ibuf_io_inst_0_bits_inst_bits & 32'h6034; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_125 = _id_ctrl_decoder_T_124 == 32'h2010; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_T_126 = ibuf_io_inst_0_bits_inst_bits & 32'h40003054; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_127 = _id_ctrl_decoder_T_126 == 32'h40001010; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_T_132 = _id_ctrl_decoder_T_123 | _id_ctrl_decoder_T_125 | _id_ctrl_decoder_T_116 |
    _id_ctrl_decoder_T_97 | _id_ctrl_decoder_T_127; // @[Decode.scala 15:30]
  wire [3:0] id_ctrl_decoder_13 = {_id_ctrl_decoder_T_132,_id_ctrl_decoder_T_121,_id_ctrl_decoder_T_106,
    _id_ctrl_decoder_T_85}; // @[Cat.scala 31:58]
  wire  id_ctrl_decoder_14 = _id_ctrl_decoder_bit_T_17 | _id_ctrl_decoder_bit_T_19 | _id_ctrl_decoder_bit_T_21 |
    _id_ctrl_decoder_bit_T_23 | _id_ctrl_decoder_bit_T_25 | _id_ctrl_decoder_bit_T_27 | _id_ctrl_decoder_bit_T_29 |
    _id_ctrl_decoder_bit_T_31 | _id_ctrl_decoder_bit_T_33 | _id_ctrl_decoder_bit_T_35 | _id_ctrl_decoder_bit_T_37 |
    _id_ctrl_decoder_bit_T_67 | _id_ctrl_decoder_bit_T_69 | _id_ctrl_decoder_bit_T_71 | _id_ctrl_decoder_bit_T_73 |
    _id_ctrl_decoder_bit_T_75 | _id_ctrl_decoder_bit_T_77 | _id_ctrl_decoder_bit_T_79 | _id_ctrl_decoder_bit_T_81; // @[Decode.scala 15:30]
  wire [31:0] _id_ctrl_decoder_T_133 = ibuf_io_inst_0_bits_inst_bits & 32'h28; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_134 = _id_ctrl_decoder_T_133 == 32'h20; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_T_135 = ibuf_io_inst_0_bits_inst_bits & 32'h18000020; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_136 = _id_ctrl_decoder_T_135 == 32'h18000020; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_T_137 = ibuf_io_inst_0_bits_inst_bits & 32'h20000020; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_138 = _id_ctrl_decoder_T_137 == 32'h20000020; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_T_141 = _id_ctrl_decoder_T_134 | _id_ctrl_decoder_T_136 | _id_ctrl_decoder_T_138; // @[Decode.scala 15:30]
  wire [31:0] _id_ctrl_decoder_T_142 = ibuf_io_inst_0_bits_inst_bits & 32'h10000008; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_143 = _id_ctrl_decoder_T_142 == 32'h10000008; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_T_144 = ibuf_io_inst_0_bits_inst_bits & 32'h40000008; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_145 = _id_ctrl_decoder_T_144 == 32'h40000008; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_T_147 = _id_ctrl_decoder_T_143 | _id_ctrl_decoder_T_145; // @[Decode.scala 15:30]
  wire [31:0] _id_ctrl_decoder_T_148 = ibuf_io_inst_0_bits_inst_bits & 32'h8000008; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_149 = _id_ctrl_decoder_T_148 == 32'h8000008; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_T_150 = ibuf_io_inst_0_bits_inst_bits & 32'h80000008; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_151 = _id_ctrl_decoder_T_150 == 32'h80000008; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_T_154 = _id_ctrl_decoder_T_149 | _id_ctrl_decoder_T_143 | _id_ctrl_decoder_T_151; // @[Decode.scala 15:30]
  wire [31:0] _id_ctrl_decoder_T_155 = ibuf_io_inst_0_bits_inst_bits & 32'h18000008; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_156 = _id_ctrl_decoder_T_155 == 32'h8; // @[Decode.scala 14:121]
  wire [4:0] id_ctrl_decoder_15 = {1'h0,_id_ctrl_decoder_T_156,_id_ctrl_decoder_T_154,_id_ctrl_decoder_T_147,
    _id_ctrl_decoder_T_141}; // @[Cat.scala 31:58]
  wire [31:0] _id_ctrl_decoder_T_158 = ibuf_io_inst_0_bits_inst_bits & 32'h2000074; // @[Decode.scala 14:65]
  wire  id_ctrl_decoder_21 = _id_ctrl_decoder_T_158 == 32'h2000030; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_T_161 = _id_ctrl_decoder_T_133 == 32'h0; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_T_163 = _id_ctrl_decoder_T_45 == 32'h10; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_T_164 = ibuf_io_inst_0_bits_inst_bits & 32'h1010; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_165 = _id_ctrl_decoder_T_164 == 32'h1010; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_T_166 = ibuf_io_inst_0_bits_inst_bits & 32'h2008; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_167 = _id_ctrl_decoder_T_166 == 32'h2008; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_T_168 = ibuf_io_inst_0_bits_inst_bits & 32'h2010; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_169 = _id_ctrl_decoder_T_168 == 32'h2010; // @[Decode.scala 14:121]
  wire  id_ctrl_decoder_22 = _id_ctrl_decoder_T_161 | _id_ctrl_decoder_T_30 | _id_ctrl_decoder_T_163 | id_ctrl_decoder_4
     | _id_ctrl_decoder_T_165 | _id_ctrl_decoder_T_167 | _id_ctrl_decoder_T_169; // @[Decode.scala 15:30]
  wire [31:0] _id_ctrl_decoder_T_176 = ibuf_io_inst_0_bits_inst_bits & 32'h1050; // @[Decode.scala 14:65]
  wire  _id_ctrl_decoder_T_177 = _id_ctrl_decoder_T_176 == 32'h1050; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_T_180 = _id_ctrl_decoder_T_20 == 32'h2050; // @[Decode.scala 14:121]
  wire  _id_ctrl_decoder_T_183 = _id_ctrl_decoder_T_45 == 32'h50; // @[Decode.scala 14:121]
  wire [2:0] id_ctrl_decoder_23 = {_id_ctrl_decoder_T_183,_id_ctrl_decoder_T_180,_id_ctrl_decoder_T_177}; // @[Cat.scala 31:58]
  wire [31:0] _id_ctrl_decoder_T_185 = ibuf_io_inst_0_bits_inst_bits & 32'h1048; // @[Decode.scala 14:65]
  wire  id_ctrl_decoder_24 = _id_ctrl_decoder_T_185 == 32'h1008; // @[Decode.scala 14:121]
  wire [31:0] _id_ctrl_decoder_T_187 = ibuf_io_inst_0_bits_inst_bits & 32'h2048; // @[Decode.scala 14:65]
  wire  id_ctrl_decoder_25 = _id_ctrl_decoder_T_187 == 32'h8; // @[Decode.scala 14:121]
  wire  id_ctrl_decoder_26 = _id_ctrl_decoder_T_187 == 32'h2008; // @[Decode.scala 14:121]
  wire [4:0] id_raddr2 = ibuf_io_inst_0_bits_inst_rs2; // @[RocketCore.scala 276:72]
  wire [4:0] id_raddr1 = ibuf_io_inst_0_bits_inst_rs1; // @[RocketCore.scala 276:72]
  wire [4:0] id_waddr = ibuf_io_inst_0_bits_inst_rd; // @[RocketCore.scala 276:72]
  reg  id_reg_fence; // @[RocketCore.scala 283:25]
  wire [31:0] _id_rs_T_4 = rf_id_rs_MPORT_data; // @[RocketCore.scala 1068:25]
  wire [31:0] _id_rs_T_9 = rf_id_rs_MPORT_1_data; // @[RocketCore.scala 1068:25]
  wire  _id_csr_en_T = id_ctrl_decoder_23 == 3'h6; // @[package.scala 15:47]
  wire  _id_csr_en_T_1 = id_ctrl_decoder_23 == 3'h7; // @[package.scala 15:47]
  wire  _id_csr_en_T_2 = id_ctrl_decoder_23 == 3'h5; // @[package.scala 15:47]
  wire  _id_csr_en_T_3 = _id_csr_en_T | _id_csr_en_T_1; // @[package.scala 72:59]
  wire  id_csr_en = _id_csr_en_T | _id_csr_en_T_1 | _id_csr_en_T_2; // @[package.scala 72:59]
  wire  id_system_insn = id_ctrl_decoder_23 == 3'h4; // @[RocketCore.scala 293:36]
  wire  id_csr_ren = _id_csr_en_T_3 & ibuf_io_inst_0_bits_inst_rs1 == 5'h0; // @[RocketCore.scala 294:54]
  wire  _id_csr_flush_T = ~id_csr_ren; // @[RocketCore.scala 296:54]
  wire  id_csr_flush = id_system_insn | id_csr_en & ~id_csr_ren & csr_io_decode_0_write_flush; // @[RocketCore.scala 296:37]
  wire  _id_illegal_insn_T_4 = id_ctrl_decoder_21 & ~csr_io_status_isa[12]; // @[RocketCore.scala 305:34]
  wire  _id_illegal_insn_T_5 = ~id_ctrl_decoder_0 | _id_illegal_insn_T_4; // @[RocketCore.scala 304:40]
  wire  _id_illegal_insn_T_8 = id_ctrl_decoder_26 & ~csr_io_status_isa[0]; // @[RocketCore.scala 306:17]
  wire  _id_illegal_insn_T_9 = _id_illegal_insn_T_5 | _id_illegal_insn_T_8; // @[RocketCore.scala 305:65]
  wire  _id_illegal_insn_T_18 = ~csr_io_status_isa[2]; // @[RocketCore.scala 309:33]
  wire  _id_illegal_insn_T_19 = ibuf_io_inst_0_bits_rvc & ~csr_io_status_isa[2]; // @[RocketCore.scala 309:30]
  wire  _id_illegal_insn_T_20 = _id_illegal_insn_T_9 | _id_illegal_insn_T_19; // @[RocketCore.scala 308:47]
  wire  _id_illegal_insn_T_42 = id_csr_en & (csr_io_decode_0_read_illegal | _id_csr_flush_T &
    csr_io_decode_0_write_illegal); // @[RocketCore.scala 315:15]
  wire  _id_illegal_insn_T_43 = _id_illegal_insn_T_20 | _id_illegal_insn_T_42; // @[RocketCore.scala 314:81]
  wire  _id_illegal_insn_T_46 = ~ibuf_io_inst_0_bits_rvc & (id_system_insn & csr_io_decode_0_system_illegal); // @[RocketCore.scala 316:31]
  wire  id_illegal_insn = _id_illegal_insn_T_43 | _id_illegal_insn_T_46; // @[RocketCore.scala 315:99]
  wire  id_amo_aq = ibuf_io_inst_0_bits_inst_bits[26]; // @[RocketCore.scala 321:29]
  wire  id_amo_rl = ibuf_io_inst_0_bits_inst_bits[25]; // @[RocketCore.scala 322:29]
  wire [3:0] id_fence_succ = ibuf_io_inst_0_bits_inst_bits[23:20]; // @[RocketCore.scala 324:33]
  wire  id_fence_next = id_ctrl_decoder_25 | id_ctrl_decoder_26 & id_amo_aq; // @[RocketCore.scala 325:37]
  wire  id_mem_busy = ~io_dmem_ordered | io_dmem_req_valid; // @[RocketCore.scala 326:38]
  wire  _GEN_0 = ~id_mem_busy ? 1'h0 : id_reg_fence; // @[RocketCore.scala 327:23 283:25 327:38]
  wire  id_do_fence_x9 = id_mem_busy & (id_ctrl_decoder_26 & id_amo_rl | id_ctrl_decoder_24 | id_reg_fence &
    id_ctrl_decoder_14); // @[RocketCore.scala 332:17]
  wire  id_xcpt = csr_io_interrupt | bpu_io_debug_if | bpu_io_xcpt_if | ibuf_io_inst_0_bits_xcpt0_ae_inst |
    ibuf_io_inst_0_bits_xcpt1_pf_inst | ibuf_io_inst_0_bits_xcpt1_gf_inst | ibuf_io_inst_0_bits_xcpt1_ae_inst |
    id_illegal_insn; // @[RocketCore.scala 1021:26]
  wire [4:0] _T_11 = ibuf_io_inst_0_bits_xcpt1_ae_inst ? 5'h1 : 5'h2; // @[Mux.scala 47:70]
  wire [4:0] _T_12 = ibuf_io_inst_0_bits_xcpt1_gf_inst ? 5'h14 : _T_11; // @[Mux.scala 47:70]
  wire [4:0] _T_13 = ibuf_io_inst_0_bits_xcpt1_pf_inst ? 5'hc : _T_12; // @[Mux.scala 47:70]
  wire [4:0] _T_14 = ibuf_io_inst_0_bits_xcpt0_ae_inst ? 5'h1 : _T_13; // @[Mux.scala 47:70]
  wire [4:0] _T_17 = bpu_io_xcpt_if ? 5'h3 : _T_14; // @[Mux.scala 47:70]
  wire [4:0] _T_18 = bpu_io_debug_if ? 5'he : _T_17; // @[Mux.scala 47:70]
  wire [4:0] ex_waddr = ex_reg_inst[11:7]; // @[RocketCore.scala 373:29]
  wire [4:0] mem_waddr = mem_reg_inst[11:7]; // @[RocketCore.scala 374:31]
  wire [4:0] wb_waddr = wb_reg_inst[11:7]; // @[RocketCore.scala 375:29]
  wire  _T_27 = ex_reg_valid & ex_ctrl_wxd; // @[RocketCore.scala 378:19]
  wire  _T_28 = mem_reg_valid & mem_ctrl_wxd; // @[RocketCore.scala 379:20]
  wire  _T_30 = mem_reg_valid & mem_ctrl_wxd & ~mem_ctrl_mem; // @[RocketCore.scala 379:36]
  wire  id_bypass_src_0_0 = 5'h0 == id_raddr1; // @[RocketCore.scala 381:82]
  wire  id_bypass_src_0_1 = _T_27 & ex_waddr == id_raddr1; // @[RocketCore.scala 381:74]
  wire  id_bypass_src_0_2 = _T_30 & mem_waddr == id_raddr1; // @[RocketCore.scala 381:74]
  wire  id_bypass_src_0_3 = _T_28 & mem_waddr == id_raddr1; // @[RocketCore.scala 381:74]
  wire  id_bypass_src_1_0 = 5'h0 == id_raddr2; // @[RocketCore.scala 381:82]
  wire  id_bypass_src_1_1 = _T_27 & ex_waddr == id_raddr2; // @[RocketCore.scala 381:74]
  wire  id_bypass_src_1_2 = _T_30 & mem_waddr == id_raddr2; // @[RocketCore.scala 381:74]
  wire  id_bypass_src_1_3 = _T_28 & mem_waddr == id_raddr2; // @[RocketCore.scala 381:74]
  reg  ex_reg_rs_bypass_0; // @[RocketCore.scala 385:29]
  reg  ex_reg_rs_bypass_1; // @[RocketCore.scala 385:29]
  reg [1:0] ex_reg_rs_lsb_0; // @[RocketCore.scala 386:26]
  reg [1:0] ex_reg_rs_lsb_1; // @[RocketCore.scala 386:26]
  reg [29:0] ex_reg_rs_msb_0; // @[RocketCore.scala 387:26]
  reg [29:0] ex_reg_rs_msb_1; // @[RocketCore.scala 387:26]
  wire [31:0] _ex_rs_T_1 = ex_reg_rs_lsb_0 == 2'h1 ? mem_reg_wdata : 32'h0; // @[package.scala 32:76]
  wire [31:0] _ex_rs_T_3 = ex_reg_rs_lsb_0 == 2'h2 ? wb_reg_wdata : _ex_rs_T_1; // @[package.scala 32:76]
  wire [31:0] _ex_rs_T_5 = ex_reg_rs_lsb_0 == 2'h3 ? io_dmem_resp_bits_data_word_bypass : _ex_rs_T_3; // @[package.scala 32:76]
  wire [31:0] _ex_rs_T_6 = {ex_reg_rs_msb_0,ex_reg_rs_lsb_0}; // @[Cat.scala 31:58]
  wire [31:0] _ex_rs_T_8 = ex_reg_rs_lsb_1 == 2'h1 ? mem_reg_wdata : 32'h0; // @[package.scala 32:76]
  wire [31:0] _ex_rs_T_10 = ex_reg_rs_lsb_1 == 2'h2 ? wb_reg_wdata : _ex_rs_T_8; // @[package.scala 32:76]
  wire [31:0] _ex_rs_T_12 = ex_reg_rs_lsb_1 == 2'h3 ? io_dmem_resp_bits_data_word_bypass : _ex_rs_T_10; // @[package.scala 32:76]
  wire [31:0] _ex_rs_T_13 = {ex_reg_rs_msb_1,ex_reg_rs_lsb_1}; // @[Cat.scala 31:58]
  wire [31:0] ex_rs_1 = ex_reg_rs_bypass_1 ? _ex_rs_T_12 : _ex_rs_T_13; // @[RocketCore.scala 389:14]
  wire  _ex_imm_sign_T = ex_ctrl_sel_imm == 3'h5; // @[RocketCore.scala 1083:24]
  wire  _ex_imm_sign_T_2 = ex_reg_inst[31]; // @[RocketCore.scala 1083:53]
  wire  ex_imm_sign = ex_ctrl_sel_imm == 3'h5 ? $signed(1'sh0) : $signed(_ex_imm_sign_T_2); // @[RocketCore.scala 1083:19]
  wire  _ex_imm_b30_20_T = ex_ctrl_sel_imm == 3'h2; // @[RocketCore.scala 1084:26]
  wire [10:0] _ex_imm_b30_20_T_2 = ex_reg_inst[30:20]; // @[RocketCore.scala 1084:49]
  wire [7:0] _ex_imm_b19_12_T_4 = ex_reg_inst[19:12]; // @[RocketCore.scala 1085:73]
  wire  _ex_imm_b11_T_2 = _ex_imm_b30_20_T | _ex_imm_sign_T; // @[RocketCore.scala 1086:33]
  wire  _ex_imm_b11_T_5 = ex_reg_inst[20]; // @[RocketCore.scala 1087:44]
  wire  _ex_imm_b11_T_6 = ex_ctrl_sel_imm == 3'h1; // @[RocketCore.scala 1088:23]
  wire  _ex_imm_b11_T_8 = ex_reg_inst[7]; // @[RocketCore.scala 1088:43]
  wire  _ex_imm_b11_T_9 = ex_ctrl_sel_imm == 3'h1 ? $signed(_ex_imm_b11_T_8) : $signed(ex_imm_sign); // @[RocketCore.scala 1088:18]
  wire  _ex_imm_b11_T_10 = ex_ctrl_sel_imm == 3'h3 ? $signed(_ex_imm_b11_T_5) : $signed(_ex_imm_b11_T_9); // @[RocketCore.scala 1087:18]
  wire [5:0] ex_imm_b10_5 = _ex_imm_b11_T_2 ? 6'h0 : ex_reg_inst[30:25]; // @[RocketCore.scala 1089:20]
  wire  _ex_imm_b4_1_T_1 = ex_ctrl_sel_imm == 3'h0; // @[RocketCore.scala 1091:24]
  wire [3:0] _ex_imm_b4_1_T_8 = _ex_imm_sign_T ? ex_reg_inst[19:16] : ex_reg_inst[24:21]; // @[RocketCore.scala 1092:19]
  wire [3:0] _ex_imm_b4_1_T_9 = ex_ctrl_sel_imm == 3'h0 | _ex_imm_b11_T_6 ? ex_reg_inst[11:8] : _ex_imm_b4_1_T_8; // @[RocketCore.scala 1091:19]
  wire [3:0] ex_imm_b4_1 = _ex_imm_b30_20_T ? 4'h0 : _ex_imm_b4_1_T_9; // @[RocketCore.scala 1090:19]
  wire  _ex_imm_b0_T_6 = _ex_imm_sign_T & ex_reg_inst[15]; // @[RocketCore.scala 1095:17]
  wire  _ex_imm_b0_T_7 = ex_ctrl_sel_imm == 3'h4 ? ex_reg_inst[20] : _ex_imm_b0_T_6; // @[RocketCore.scala 1094:17]
  wire  ex_imm_b0 = _ex_imm_b4_1_T_1 ? ex_reg_inst[7] : _ex_imm_b0_T_7; // @[RocketCore.scala 1093:17]
  wire  ex_imm_hi_lo_lo = _ex_imm_b30_20_T | _ex_imm_sign_T ? $signed(1'sh0) : $signed(_ex_imm_b11_T_10); // @[Cat.scala 31:58]
  wire [7:0] ex_imm_hi_lo_hi = ex_ctrl_sel_imm != 3'h2 & ex_ctrl_sel_imm != 3'h3 ? $signed({8{ex_imm_sign}}) : $signed(
    _ex_imm_b19_12_T_4); // @[Cat.scala 31:58]
  wire [10:0] ex_imm_hi_hi_lo = ex_ctrl_sel_imm == 3'h2 ? $signed(_ex_imm_b30_20_T_2) : $signed({11{ex_imm_sign}}); // @[Cat.scala 31:58]
  wire  ex_imm_hi_hi_hi = ex_ctrl_sel_imm == 3'h5 ? $signed(1'sh0) : $signed(_ex_imm_sign_T_2); // @[Cat.scala 31:58]
  wire [31:0] ex_imm = {ex_imm_hi_hi_hi,ex_imm_hi_hi_lo,ex_imm_hi_lo_hi,ex_imm_hi_lo_lo,ex_imm_b10_5,ex_imm_b4_1,
    ex_imm_b0}; // @[RocketCore.scala 1097:53]
  wire [31:0] _ex_op1_T = ex_reg_rs_bypass_0 ? _ex_rs_T_5 : _ex_rs_T_6; // @[RocketCore.scala 392:24]
  wire [31:0] _ex_op1_T_3 = 2'h1 == ex_ctrl_sel_alu1 ? $signed(_ex_op1_T) : $signed(32'sh0); // @[Mux.scala 81:58]
  wire [31:0] _ex_op2_T = ex_reg_rs_bypass_1 ? _ex_rs_T_12 : _ex_rs_T_13; // @[RocketCore.scala 395:24]
  wire [3:0] _ex_op2_T_1 = ex_reg_rvc ? $signed(4'sh2) : $signed(4'sh4); // @[RocketCore.scala 397:19]
  wire [31:0] _ex_op2_T_3 = 2'h2 == ex_ctrl_sel_alu2 ? $signed(_ex_op2_T) : $signed(32'sh0); // @[Mux.scala 81:58]
  wire [31:0] _ex_op2_T_5 = 2'h3 == ex_ctrl_sel_alu2 ? $signed(ex_imm) : $signed(_ex_op2_T_3); // @[Mux.scala 81:58]
  wire  _T_138 = id_raddr1 != 5'h0; // @[RocketCore.scala 757:55]
  wire  _T_139 = id_ctrl_decoder_7 & id_raddr1 != 5'h0; // @[RocketCore.scala 757:42]
  wire  _data_hazard_ex_T = id_raddr1 == ex_waddr; // @[RocketCore.scala 777:70]
  wire  _T_140 = id_raddr2 != 5'h0; // @[RocketCore.scala 758:55]
  wire  _T_141 = id_ctrl_decoder_6 & id_raddr2 != 5'h0; // @[RocketCore.scala 758:42]
  wire  _data_hazard_ex_T_2 = id_raddr2 == ex_waddr; // @[RocketCore.scala 777:70]
  wire  _T_143 = id_ctrl_decoder_22 & id_waddr != 5'h0; // @[RocketCore.scala 759:42]
  wire  _data_hazard_ex_T_4 = id_waddr == ex_waddr; // @[RocketCore.scala 777:70]
  wire  _data_hazard_ex_T_7 = _T_139 & _data_hazard_ex_T | _T_141 & _data_hazard_ex_T_2 | _T_143 & _data_hazard_ex_T_4; // @[RocketCore.scala 1030:50]
  wire  data_hazard_ex = ex_ctrl_wxd & _data_hazard_ex_T_7; // @[RocketCore.scala 777:36]
  wire  ex_cannot_bypass = ex_ctrl_csr != 3'h0 | ex_ctrl_jalr | ex_ctrl_mem | ex_ctrl_div; // @[RocketCore.scala 776:94]
  wire  id_ex_hazard = ex_reg_valid & (data_hazard_ex & ex_cannot_bypass); // @[RocketCore.scala 779:35]
  wire  _data_hazard_mem_T = id_raddr1 == mem_waddr; // @[RocketCore.scala 786:72]
  wire  _data_hazard_mem_T_2 = id_raddr2 == mem_waddr; // @[RocketCore.scala 786:72]
  wire  _data_hazard_mem_T_4 = id_waddr == mem_waddr; // @[RocketCore.scala 786:72]
  wire  _data_hazard_mem_T_7 = _T_139 & _data_hazard_mem_T | _T_141 & _data_hazard_mem_T_2 | _T_143 &
    _data_hazard_mem_T_4; // @[RocketCore.scala 1030:50]
  wire  data_hazard_mem = mem_ctrl_wxd & _data_hazard_mem_T_7; // @[RocketCore.scala 786:38]
  wire  mem_cannot_bypass = mem_ctrl_csr != 3'h0 | mem_ctrl_mem & mem_reg_slow_bypass | mem_ctrl_div; // @[RocketCore.scala 785:100]
  wire  id_mem_hazard = mem_reg_valid & (data_hazard_mem & mem_cannot_bypass); // @[RocketCore.scala 788:37]
  wire  _data_hazard_wb_T = id_raddr1 == wb_waddr; // @[RocketCore.scala 792:70]
  wire  _data_hazard_wb_T_2 = id_raddr2 == wb_waddr; // @[RocketCore.scala 792:70]
  wire  _data_hazard_wb_T_4 = id_waddr == wb_waddr; // @[RocketCore.scala 792:70]
  wire  _data_hazard_wb_T_7 = _T_139 & _data_hazard_wb_T | _T_141 & _data_hazard_wb_T_2 | _T_143 & _data_hazard_wb_T_4; // @[RocketCore.scala 1030:50]
  wire  data_hazard_wb = wb_ctrl_wxd & _data_hazard_wb_T_7; // @[RocketCore.scala 792:36]
  wire  wb_dcache_miss = wb_ctrl_mem & ~io_dmem_resp_valid; // @[RocketCore.scala 509:36]
  wire  wb_set_sboard = wb_ctrl_div | wb_dcache_miss; // @[RocketCore.scala 663:35]
  wire  id_wb_hazard = wb_reg_valid & (data_hazard_wb & wb_set_sboard); // @[RocketCore.scala 794:35]
  reg [31:0] _r; // @[RocketCore.scala 1047:25]
  wire [31:0] r = {_r[31:1], 1'h0}; // @[RocketCore.scala 1048:40]
  wire [31:0] _id_sboard_hazard_T = r >> id_raddr1; // @[RocketCore.scala 1044:35]
  wire  dmem_resp_valid = io_dmem_resp_valid & io_dmem_resp_bits_has_data; // @[RocketCore.scala 673:44]
  wire  dmem_resp_replay = dmem_resp_valid & io_dmem_resp_bits_replay; // @[RocketCore.scala 674:42]
  wire  dmem_resp_xpu = ~io_dmem_resp_bits_tag[0]; // @[RocketCore.scala 670:23]
  wire  ll_wen_x2 = div_io_resp_ready & div_io_resp_valid; // @[Decoupled.scala 50:35]
  wire  ll_wen = dmem_resp_replay & dmem_resp_xpu | ll_wen_x2; // @[RocketCore.scala 689:44 694:12]
  wire [4:0] dmem_resp_waddr = io_dmem_resp_bits_tag[5:1]; // @[RocketCore.scala 672:46]
  wire [4:0] ll_waddr = dmem_resp_replay & dmem_resp_xpu ? dmem_resp_waddr : div_io_resp_bits_tag; // @[RocketCore.scala 689:44 693:14]
  wire  _id_sboard_hazard_T_3 = ll_wen & ll_waddr == id_raddr1; // @[RocketCore.scala 769:58]
  wire  _id_sboard_hazard_T_5 = _id_sboard_hazard_T[0] & ~_id_sboard_hazard_T_3; // @[RocketCore.scala 772:77]
  wire [31:0] _id_sboard_hazard_T_7 = r >> id_raddr2; // @[RocketCore.scala 1044:35]
  wire  _id_sboard_hazard_T_10 = ll_wen & ll_waddr == id_raddr2; // @[RocketCore.scala 769:58]
  wire  _id_sboard_hazard_T_12 = _id_sboard_hazard_T_7[0] & ~_id_sboard_hazard_T_10; // @[RocketCore.scala 772:77]
  wire [31:0] _id_sboard_hazard_T_14 = r >> id_waddr; // @[RocketCore.scala 1044:35]
  wire  _id_sboard_hazard_T_17 = ll_wen & ll_waddr == id_waddr; // @[RocketCore.scala 769:58]
  wire  _id_sboard_hazard_T_19 = _id_sboard_hazard_T_14[0] & ~_id_sboard_hazard_T_17; // @[RocketCore.scala 772:77]
  wire  id_sboard_hazard = _T_139 & _id_sboard_hazard_T_5 | _T_141 & _id_sboard_hazard_T_12 | _T_143 &
    _id_sboard_hazard_T_19; // @[RocketCore.scala 1030:50]
  wire  _ctrl_stalld_T_5 = csr_io_singleStep & (ex_reg_valid | mem_reg_valid | wb_reg_valid); // @[RocketCore.scala 816:23]
  wire  _ctrl_stalld_T_6 = id_ex_hazard | id_mem_hazard | id_wb_hazard | id_sboard_hazard | _ctrl_stalld_T_5; // @[RocketCore.scala 815:71]
  reg  blocked; // @[RocketCore.scala 807:22]
  wire  _dcache_blocked_T = ~io_dmem_perf_grant; // @[RocketCore.scala 809:16]
  wire  dcache_blocked = blocked & ~io_dmem_perf_grant; // @[RocketCore.scala 809:13]
  wire  _ctrl_stalld_T_13 = id_ctrl_decoder_14 & dcache_blocked; // @[RocketCore.scala 819:17]
  wire  _ctrl_stalld_T_14 = _ctrl_stalld_T_6 | _ctrl_stalld_T_13; // @[RocketCore.scala 818:32]
  wire  wb_wxd = wb_reg_valid & wb_ctrl_wxd; // @[RocketCore.scala 662:29]
  wire  _ctrl_stalld_T_17 = ~wb_wxd; // @[RocketCore.scala 821:65]
  wire  _ctrl_stalld_T_22 = id_ctrl_decoder_21 & (~(div_io_req_ready | div_io_resp_valid & ~wb_wxd) | div_io_req_valid); // @[RocketCore.scala 821:17]
  wire  _ctrl_stalld_T_23 = _ctrl_stalld_T_14 | _ctrl_stalld_T_22; // @[RocketCore.scala 820:34]
  wire  _ctrl_stalld_T_26 = _ctrl_stalld_T_23 | id_do_fence_x9; // @[RocketCore.scala 822:15]
  wire  _ctrl_stalld_T_27 = _ctrl_stalld_T_26 | csr_io_csr_stall; // @[RocketCore.scala 823:17]
  wire  ctrl_stalld = _ctrl_stalld_T_27 | id_reg_pause; // @[RocketCore.scala 824:22]
  wire  ctrl_killd = ~ibuf_io_inst_0_valid | ibuf_io_inst_0_bits_replay | take_pc_mem_wb | ctrl_stalld |
    csr_io_interrupt; // @[RocketCore.scala 827:104]
  wire  _ex_reg_valid_T = ~ctrl_killd; // @[RocketCore.scala 437:19]
  wire  _ex_reg_replay_T = ~take_pc_mem_wb; // @[RocketCore.scala 438:20]
  wire  _ex_reg_replay_T_1 = ~take_pc_mem_wb & ibuf_io_inst_0_valid; // @[RocketCore.scala 438:29]
  wire  _GEN_1 = id_ctrl_decoder_25 & id_fence_succ == 4'h0 | id_reg_pause; // @[RocketCore.scala 116:25 448:{49,64}]
  wire  _GEN_2 = id_fence_next | _GEN_0; // @[RocketCore.scala 449:{26,41}]
  wire [2:0] _T_35 = {ibuf_io_inst_0_bits_xcpt1_pf_inst,ibuf_io_inst_0_bits_xcpt1_gf_inst,
    ibuf_io_inst_0_bits_xcpt1_ae_inst}; // @[RocketCore.scala 455:22]
  wire  _GEN_5 = |_T_35 | ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala 444:16 455:34 458:20]
  wire [2:0] _T_37 = {2'h0,ibuf_io_inst_0_bits_xcpt0_ae_inst}; // @[RocketCore.scala 460:40]
  wire  _T_40 = id_ctrl_decoder_15 == 5'h14; // @[package.scala 15:47]
  wire  _T_41 = id_ctrl_decoder_15 == 5'h15; // @[package.scala 15:47]
  wire  _T_42 = id_ctrl_decoder_15 == 5'h16; // @[package.scala 15:47]
  wire  _T_43 = id_ctrl_decoder_15 == 5'h5; // @[package.scala 15:47]
  wire  _T_46 = _T_40 | _T_41 | _T_42 | _T_43; // @[package.scala 72:59]
  wire [1:0] _ex_reg_mem_size_T_6 = {_T_140,_T_138}; // @[Cat.scala 31:58]
  wire  do_bypass = id_bypass_src_0_0 | id_bypass_src_0_1 | id_bypass_src_0_2 | id_bypass_src_0_3; // @[RocketCore.scala 482:48]
  wire [1:0] _bypass_src_T = id_bypass_src_0_2 ? 2'h2 : 2'h3; // @[Mux.scala 47:70]
  wire [1:0] _bypass_src_T_1 = id_bypass_src_0_1 ? 2'h1 : _bypass_src_T; // @[Mux.scala 47:70]
  wire  wb_valid = wb_reg_valid & ~replay_wb_common & ~wb_xcpt; // @[RocketCore.scala 697:45]
  wire  wb_wen = wb_valid & wb_ctrl_wxd; // @[RocketCore.scala 698:25]
  wire  rf_wen = wb_wen | ll_wen; // @[RocketCore.scala 699:23]
  wire [4:0] rf_waddr = ll_wen ? ll_waddr : wb_waddr; // @[RocketCore.scala 700:21]
  wire  _T_133 = rf_waddr != 5'h0; // @[RocketCore.scala 1073:16]
  wire  _rf_wdata_T = dmem_resp_valid & dmem_resp_xpu; // @[RocketCore.scala 701:38]
  wire [31:0] ll_wdata = div_io_resp_bits_data;
  wire [31:0] _rf_wdata_T_4 = wb_ctrl_csr != 3'h0 ? csr_io_rw_rdata : wb_reg_wdata; // @[RocketCore.scala 703:21]
  wire [31:0] _rf_wdata_T_5 = ll_wen ? ll_wdata : _rf_wdata_T_4; // @[RocketCore.scala 702:21]
  wire [31:0] rf_wdata = dmem_resp_valid & dmem_resp_xpu ? io_dmem_resp_bits_data : _rf_wdata_T_5; // @[RocketCore.scala 701:21]
  wire [31:0] _GEN_237 = rf_waddr == id_raddr1 ? rf_wdata : _id_rs_T_4; // @[RocketCore.scala 1068:19 1076:{31,39}]
  wire [31:0] _GEN_244 = rf_waddr != 5'h0 ? _GEN_237 : _id_rs_T_4; // @[RocketCore.scala 1068:19 1073:29]
  wire [31:0] id_rs_0 = rf_wen ? _GEN_244 : _id_rs_T_4; // @[RocketCore.scala 706:17 1068:19]
  wire  do_bypass_1 = id_bypass_src_1_0 | id_bypass_src_1_1 | id_bypass_src_1_2 | id_bypass_src_1_3; // @[RocketCore.scala 482:48]
  wire [1:0] _bypass_src_T_2 = id_bypass_src_1_2 ? 2'h2 : 2'h3; // @[Mux.scala 47:70]
  wire [31:0] _GEN_238 = rf_waddr == id_raddr2 ? rf_wdata : _id_rs_T_9; // @[RocketCore.scala 1068:19 1076:{31,39}]
  wire [31:0] _GEN_245 = rf_waddr != 5'h0 ? _GEN_238 : _id_rs_T_9; // @[RocketCore.scala 1068:19 1073:29]
  wire [31:0] id_rs_1 = rf_wen ? _GEN_245 : _id_rs_T_9; // @[RocketCore.scala 706:17 1068:19]
  wire [31:0] inst = ibuf_io_inst_0_bits_rvc ? {{16'd0}, ibuf_io_inst_0_bits_raw[15:0]} : ibuf_io_inst_0_bits_raw; // @[RocketCore.scala 492:21]
  wire  id_load_use = mem_reg_valid & data_hazard_mem & mem_ctrl_mem; // @[RocketCore.scala 789:51]
  wire  _replay_ex_structural_T = ~io_dmem_req_ready; // @[RocketCore.scala 510:45]
  wire  _replay_ex_structural_T_3 = ex_ctrl_div & ~div_io_req_ready; // @[RocketCore.scala 511:42]
  wire  replay_ex_structural = ex_ctrl_mem & ~io_dmem_req_ready | _replay_ex_structural_T_3; // @[RocketCore.scala 510:64]
  wire  replay_ex_load_use = wb_dcache_miss & ex_reg_load_use; // @[RocketCore.scala 512:43]
  wire  replay_ex = ex_reg_replay | ex_reg_valid & (replay_ex_structural | replay_ex_load_use); // @[RocketCore.scala 513:33]
  wire  ctrl_killx = take_pc_mem_wb | replay_ex | ~ex_reg_valid; // @[RocketCore.scala 514:48]
  wire  _ex_slow_bypass_T = ex_ctrl_mem_cmd == 5'h7; // @[RocketCore.scala 516:40]
  wire  ex_slow_bypass = ex_ctrl_mem_cmd == 5'h7 | ex_reg_mem_size < 2'h2; // @[RocketCore.scala 516:50]
  wire  ex_xcpt = ex_reg_xcpt_interrupt | ex_reg_xcpt; // @[RocketCore.scala 520:28]
  wire  mem_pc_valid = mem_reg_valid | mem_reg_replay | mem_reg_xcpt_interrupt; // @[RocketCore.scala 526:54]
  wire  mem_npc_misaligned = _id_illegal_insn_T_18 & mem_npc[1]; // @[RocketCore.scala 535:56]
  wire [31:0] mem_int_wdata = _take_pc_mem_T & (mem_ctrl_jalr ^ mem_npc_misaligned) ? $signed(mem_br_target) : $signed(
    mem_reg_wdata); // @[RocketCore.scala 536:119]
  wire  mem_cfi = mem_ctrl_branch | mem_ctrl_jalr | mem_ctrl_jal; // @[RocketCore.scala 537:50]
  wire  mem_cfi_taken = _mem_br_target_T_1 | mem_ctrl_jalr | mem_ctrl_jal; // @[RocketCore.scala 538:74]
  wire  _mem_reg_valid_T = ~ctrl_killx; // @[RocketCore.scala 543:20]
  wire  _mem_reg_load_T = ex_ctrl_mem_cmd == 5'h0; // @[package.scala 15:47]
  wire  _mem_reg_load_T_1 = ex_ctrl_mem_cmd == 5'h10; // @[package.scala 15:47]
  wire  _mem_reg_load_T_2 = ex_ctrl_mem_cmd == 5'h6; // @[package.scala 15:47]
  wire  _mem_reg_load_T_6 = _mem_reg_load_T | _mem_reg_load_T_1 | _mem_reg_load_T_2 | _ex_slow_bypass_T; // @[package.scala 72:59]
  wire  _mem_reg_load_T_7 = ex_ctrl_mem_cmd == 5'h4; // @[package.scala 15:47]
  wire  _mem_reg_load_T_8 = ex_ctrl_mem_cmd == 5'h9; // @[package.scala 15:47]
  wire  _mem_reg_load_T_9 = ex_ctrl_mem_cmd == 5'ha; // @[package.scala 15:47]
  wire  _mem_reg_load_T_10 = ex_ctrl_mem_cmd == 5'hb; // @[package.scala 15:47]
  wire  _mem_reg_load_T_13 = _mem_reg_load_T_7 | _mem_reg_load_T_8 | _mem_reg_load_T_9 | _mem_reg_load_T_10; // @[package.scala 72:59]
  wire  _mem_reg_load_T_14 = ex_ctrl_mem_cmd == 5'h8; // @[package.scala 15:47]
  wire  _mem_reg_load_T_15 = ex_ctrl_mem_cmd == 5'hc; // @[package.scala 15:47]
  wire  _mem_reg_load_T_16 = ex_ctrl_mem_cmd == 5'hd; // @[package.scala 15:47]
  wire  _mem_reg_load_T_17 = ex_ctrl_mem_cmd == 5'he; // @[package.scala 15:47]
  wire  _mem_reg_load_T_18 = ex_ctrl_mem_cmd == 5'hf; // @[package.scala 15:47]
  wire  _mem_reg_load_T_22 = _mem_reg_load_T_14 | _mem_reg_load_T_15 | _mem_reg_load_T_16 | _mem_reg_load_T_17 |
    _mem_reg_load_T_18; // @[package.scala 72:59]
  wire  _mem_reg_load_T_23 = _mem_reg_load_T_13 | _mem_reg_load_T_22; // @[Consts.scala 82:44]
  wire  _mem_reg_load_T_24 = _mem_reg_load_T_6 | _mem_reg_load_T_23; // @[Consts.scala 84:68]
  wire  _mem_reg_store_T_22 = ex_ctrl_mem_cmd == 5'h1 | ex_ctrl_mem_cmd == 5'h11 | _ex_slow_bypass_T |
    _mem_reg_load_T_23; // @[Consts.scala 85:76]
  wire [31:0] _mem_reg_wdata_T = alu_io_out; // @[RocketCore.scala 571:25]
  wire [31:0] _mem_reg_rs2_T_3 = {ex_rs_1[7:0],ex_rs_1[7:0],ex_rs_1[7:0],ex_rs_1[7:0]}; // @[Cat.scala 31:58]
  wire [31:0] _mem_reg_rs2_T_6 = {ex_rs_1[15:0],ex_rs_1[15:0]}; // @[Cat.scala 31:58]
  wire [31:0] _mem_reg_rs2_T_7 = ex_reg_mem_size == 2'h1 ? _mem_reg_rs2_T_6 : ex_rs_1; // @[AMOALU.scala 26:13]
  wire  _GEN_80 = ex_ctrl_jalr & csr_io_status_debug | ex_ctrl_fence_i; // @[RocketCore.scala 553:14 578:48 580:24]
  wire  _GEN_81 = ex_ctrl_jalr & csr_io_status_debug | ex_reg_flush_pipe; // @[RocketCore.scala 561:24 578:48 581:26]
  wire  mem_breakpoint = mem_reg_load & bpu_io_xcpt_ld | mem_reg_store & bpu_io_xcpt_st; // @[RocketCore.scala 585:57]
  wire  mem_debug_breakpoint = mem_reg_load & bpu_io_debug_ld | mem_reg_store & bpu_io_debug_st; // @[RocketCore.scala 586:64]
  wire  mem_ldst_xcpt = mem_debug_breakpoint | mem_breakpoint; // @[RocketCore.scala 1021:26]
  wire [3:0] mem_ldst_cause = mem_debug_breakpoint ? 4'he : 4'h3; // @[Mux.scala 47:70]
  wire  _T_70 = mem_reg_xcpt_interrupt | mem_reg_xcpt; // @[RocketCore.scala 592:29]
  wire  _T_71 = mem_reg_valid & mem_npc_misaligned; // @[RocketCore.scala 593:20]
  wire  _T_72 = mem_reg_valid & mem_ldst_xcpt; // @[RocketCore.scala 594:20]
  wire  mem_xcpt = _T_70 | _T_71 | _T_72; // @[RocketCore.scala 1021:26]
  wire [3:0] _T_74 = _T_71 ? 4'h0 : mem_ldst_cause; // @[Mux.scala 47:70]
  wire  dcache_kill_mem = _T_28 & io_dmem_replay_next; // @[RocketCore.scala 603:55]
  wire  replay_mem = dcache_kill_mem | mem_reg_replay; // @[RocketCore.scala 605:37]
  wire  killm_common = dcache_kill_mem | take_pc_wb | mem_reg_xcpt | ~mem_reg_valid; // @[RocketCore.scala 606:68]
  reg  div_io_kill_REG; // @[RocketCore.scala 607:37]
  wire  ctrl_killm = killm_common | mem_xcpt; // @[RocketCore.scala 608:33]
  wire  _wb_reg_valid_T = ~ctrl_killm; // @[RocketCore.scala 611:19]
  wire  _wb_reg_replay_T = ~take_pc_wb; // @[RocketCore.scala 612:34]
  wire [2:0] _T_117 = _T_107 ? 3'h6 : 3'h4; // @[Mux.scala 47:70]
  wire [2:0] _T_118 = _T_105 ? 3'h5 : _T_117; // @[Mux.scala 47:70]
  wire [2:0] _T_119 = _T_103 ? 3'h7 : _T_118; // @[Mux.scala 47:70]
  wire [4:0] _T_120 = {{2'd0}, _T_119}; // @[Mux.scala 47:70]
  wire [4:0] _T_122 = _T_97 ? 5'hd : _T_120; // @[Mux.scala 47:70]
  wire [4:0] _T_123 = _T_95 ? 5'hf : _T_122; // @[Mux.scala 47:70]
  wire [15:0] _csr_io_inst_0_T_3 = &wb_reg_raw_inst[1:0] ? wb_reg_inst[31:16] : 16'h0; // @[RocketCore.scala 714:50]
  wire [31:0] _io_fpu_time_T = csr_io_time; // @[RocketCore.scala 719:29]
  wire  tval_dmem_addr = ~wb_reg_xcpt; // @[RocketCore.scala 723:24]
  wire  _tval_any_addr_T = wb_reg_cause == 32'h3; // @[package.scala 15:47]
  wire  _tval_any_addr_T_1 = wb_reg_cause == 32'h1; // @[package.scala 15:47]
  wire  _tval_any_addr_T_2 = wb_reg_cause == 32'hc; // @[package.scala 15:47]
  wire  _tval_any_addr_T_3 = wb_reg_cause == 32'h14; // @[package.scala 15:47]
  wire  _tval_any_addr_T_6 = _tval_any_addr_T | _tval_any_addr_T_1 | _tval_any_addr_T_2 | _tval_any_addr_T_3; // @[package.scala 72:59]
  wire  tval_any_addr = tval_dmem_addr | _tval_any_addr_T_6; // @[RocketCore.scala 724:38]
  wire  tval_inst = wb_reg_cause == 32'h2; // @[RocketCore.scala 726:32]
  wire  tval_valid = wb_xcpt & (tval_any_addr | tval_inst); // @[RocketCore.scala 727:28]
  wire  htval_valid_imem = wb_reg_xcpt & _tval_any_addr_T_3; // @[RocketCore.scala 731:40]
  wire  _csr_io_htval_T_3 = ~reset; // @[RocketCore.scala 733:11]
  wire [2:0] _csr_io_rw_cmd_T = wb_reg_valid ? 3'h0 : 3'h4; // @[CSR.scala 167:15]
  wire [2:0] _csr_io_rw_cmd_T_1 = ~_csr_io_rw_cmd_T; // @[CSR.scala 167:11]
  wire [31:0] _T_144 = 32'h1 << ll_waddr; // @[RocketCore.scala 1051:62]
  wire [31:0] _T_145 = ll_wen ? _T_144 : 32'h0; // @[RocketCore.scala 1051:49]
  wire [31:0] _T_146 = ~_T_145; // @[RocketCore.scala 1043:64]
  wire [31:0] _T_147 = r & _T_146; // @[RocketCore.scala 1043:62]
  wire  _T_149 = wb_set_sboard & wb_wen; // @[RocketCore.scala 773:28]
  wire [31:0] _T_150 = 32'h1 << wb_waddr; // @[RocketCore.scala 1051:62]
  wire [31:0] _T_151 = _T_149 ? _T_150 : 32'h0; // @[RocketCore.scala 1051:49]
  wire [31:0] _T_152 = _T_147 | _T_151; // @[RocketCore.scala 1042:60]
  wire  _T_153 = ll_wen | _T_149; // @[RocketCore.scala 1054:17]
  wire [31:0] _io_imem_req_bits_pc_T_1 = replay_wb_common ? wb_reg_pc : mem_npc; // @[RocketCore.scala 833:8]
  wire  _io_imem_btb_update_bits_cfiType_T = mem_ctrl_jal | mem_ctrl_jalr; // @[RocketCore.scala 854:23]
  wire [4:0] _io_imem_btb_update_bits_cfiType_T_5 = mem_reg_inst[19:15] & 5'h1b; // @[RocketCore.scala 855:62]
  wire [1:0] _io_imem_btb_update_bits_cfiType_T_10 = mem_ctrl_jalr & 5'h1 == _io_imem_btb_update_bits_cfiType_T_5 ? 2'h3
     : {{1'd0}, _io_imem_btb_update_bits_cfiType_T}; // @[RocketCore.scala 855:8]
  wire [1:0] _io_imem_btb_update_bits_br_pc_T = mem_reg_rvc ? 2'h0 : 2'h2; // @[RocketCore.scala 859:74]
  wire [31:0] _GEN_256 = {{30'd0}, _io_imem_btb_update_bits_br_pc_T}; // @[RocketCore.scala 859:69]
  wire [31:0] _io_imem_btb_update_bits_pc_T = ~io_imem_btb_update_bits_br_pc; // @[RocketCore.scala 860:35]
  wire [31:0] _io_imem_btb_update_bits_pc_T_1 = _io_imem_btb_update_bits_pc_T | 32'h3; // @[RocketCore.scala 860:66]
  wire  unpause = csr_io_time[4:0] == 5'h0 | csr_io_inhibit_cycle | io_dmem_perf_release | take_pc_mem_wb; // @[RocketCore.scala 907:116]
  wire  coreMonitorBundle_valid = csr_io_trace_0_valid & ~csr_io_trace_0_exception; // @[RocketCore.scala 935:52]
  wire [31:0] coreMonitorBundle_pc = csr_io_trace_0_iaddr; // @[RocketCore.scala 936:48]
  wire  coreMonitorBundle_wrenx = wb_wen & ~wb_set_sboard; // @[RocketCore.scala 937:37]
  reg [31:0] coreMonitorBundle_rd0val_x23; // @[RocketCore.scala 942:43]
  reg [31:0] coreMonitorBundle_rd0val_REG; // @[RocketCore.scala 942:34]
  reg [31:0] coreMonitorBundle_rd1val_x29; // @[RocketCore.scala 944:43]
  reg [31:0] coreMonitorBundle_rd1val_REG; // @[RocketCore.scala 944:34]
  wire [4:0] _T_155 = wb_ctrl_wxd ? wb_waddr : 5'h0; // @[RocketCore.scala 980:13]
  wire [31:0] _T_156 = coreMonitorBundle_wrenx ? rf_wdata : 32'h0; // @[RocketCore.scala 981:13]
  wire [4:0] _T_158 = wb_ctrl_rxs1 ? wb_reg_inst[19:15] : 5'h0; // @[RocketCore.scala 983:13]
  wire [31:0] _T_160 = wb_ctrl_rxs1 ? coreMonitorBundle_rd0val_REG : 32'h0; // @[RocketCore.scala 984:13]
  wire [4:0] _T_162 = wb_ctrl_rxs2 ? wb_reg_inst[24:20] : 5'h0; // @[RocketCore.scala 985:13]
  wire [31:0] _T_164 = wb_ctrl_rxs2 ? coreMonitorBundle_rd1val_REG : 32'h0; // @[RocketCore.scala 986:13]
  wire [31:0] coreMonitorBundle_inst = csr_io_trace_0_insn; // @[RocketCore.scala 929:31 945:26]
  IBuf ibuf ( // @[RocketCore.scala 263:20]
    .clock(ibuf_clock),
    .reset(ibuf_reset),
    .io_imem_ready(ibuf_io_imem_ready),
    .io_imem_valid(ibuf_io_imem_valid),
    .io_imem_bits_btb_taken(ibuf_io_imem_bits_btb_taken),
    .io_imem_bits_btb_bridx(ibuf_io_imem_bits_btb_bridx),
    .io_imem_bits_btb_entry(ibuf_io_imem_bits_btb_entry),
    .io_imem_bits_btb_bht_history(ibuf_io_imem_bits_btb_bht_history),
    .io_imem_bits_pc(ibuf_io_imem_bits_pc),
    .io_imem_bits_data(ibuf_io_imem_bits_data),
    .io_imem_bits_xcpt_ae_inst(ibuf_io_imem_bits_xcpt_ae_inst),
    .io_imem_bits_replay(ibuf_io_imem_bits_replay),
    .io_kill(ibuf_io_kill),
    .io_pc(ibuf_io_pc),
    .io_btb_resp_entry(ibuf_io_btb_resp_entry),
    .io_btb_resp_bht_history(ibuf_io_btb_resp_bht_history),
    .io_inst_0_ready(ibuf_io_inst_0_ready),
    .io_inst_0_valid(ibuf_io_inst_0_valid),
    .io_inst_0_bits_xcpt0_ae_inst(ibuf_io_inst_0_bits_xcpt0_ae_inst),
    .io_inst_0_bits_xcpt1_pf_inst(ibuf_io_inst_0_bits_xcpt1_pf_inst),
    .io_inst_0_bits_xcpt1_gf_inst(ibuf_io_inst_0_bits_xcpt1_gf_inst),
    .io_inst_0_bits_xcpt1_ae_inst(ibuf_io_inst_0_bits_xcpt1_ae_inst),
    .io_inst_0_bits_replay(ibuf_io_inst_0_bits_replay),
    .io_inst_0_bits_rvc(ibuf_io_inst_0_bits_rvc),
    .io_inst_0_bits_inst_bits(ibuf_io_inst_0_bits_inst_bits),
    .io_inst_0_bits_inst_rd(ibuf_io_inst_0_bits_inst_rd),
    .io_inst_0_bits_inst_rs1(ibuf_io_inst_0_bits_inst_rs1),
    .io_inst_0_bits_inst_rs2(ibuf_io_inst_0_bits_inst_rs2),
    .io_inst_0_bits_raw(ibuf_io_inst_0_bits_raw)
  );
  CSRFile csr ( // @[RocketCore.scala 291:19]
    .clock(csr_clock),
    .reset(csr_reset),
    .io_ungated_clock(csr_io_ungated_clock),
    .io_interrupts_debug(csr_io_interrupts_debug),
    .io_interrupts_mtip(csr_io_interrupts_mtip),
    .io_interrupts_msip(csr_io_interrupts_msip),
    .io_interrupts_meip(csr_io_interrupts_meip),
    .io_interrupts_seip(csr_io_interrupts_seip),
    .io_hartid(csr_io_hartid),
    .io_rw_addr(csr_io_rw_addr),
    .io_rw_cmd(csr_io_rw_cmd),
    .io_rw_rdata(csr_io_rw_rdata),
    .io_rw_wdata(csr_io_rw_wdata),
    .io_decode_0_inst(csr_io_decode_0_inst),
    .io_decode_0_fp_illegal(csr_io_decode_0_fp_illegal),
    .io_decode_0_fp_csr(csr_io_decode_0_fp_csr),
    .io_decode_0_read_illegal(csr_io_decode_0_read_illegal),
    .io_decode_0_write_illegal(csr_io_decode_0_write_illegal),
    .io_decode_0_write_flush(csr_io_decode_0_write_flush),
    .io_decode_0_system_illegal(csr_io_decode_0_system_illegal),
    .io_csr_stall(csr_io_csr_stall),
    .io_eret(csr_io_eret),
    .io_singleStep(csr_io_singleStep),
    .io_status_debug(csr_io_status_debug),
    .io_status_cease(csr_io_status_cease),
    .io_status_wfi(csr_io_status_wfi),
    .io_status_isa(csr_io_status_isa),
    .io_status_dprv(csr_io_status_dprv),
    .io_status_dv(csr_io_status_dv),
    .io_status_prv(csr_io_status_prv),
    .io_status_v(csr_io_status_v),
    .io_status_sd(csr_io_status_sd),
    .io_status_zero2(csr_io_status_zero2),
    .io_status_mpv(csr_io_status_mpv),
    .io_status_gva(csr_io_status_gva),
    .io_status_mbe(csr_io_status_mbe),
    .io_status_sbe(csr_io_status_sbe),
    .io_status_sxl(csr_io_status_sxl),
    .io_status_uxl(csr_io_status_uxl),
    .io_status_sd_rv32(csr_io_status_sd_rv32),
    .io_status_zero1(csr_io_status_zero1),
    .io_status_tsr(csr_io_status_tsr),
    .io_status_tw(csr_io_status_tw),
    .io_status_tvm(csr_io_status_tvm),
    .io_status_mxr(csr_io_status_mxr),
    .io_status_sum(csr_io_status_sum),
    .io_status_mprv(csr_io_status_mprv),
    .io_status_xs(csr_io_status_xs),
    .io_status_fs(csr_io_status_fs),
    .io_status_mpp(csr_io_status_mpp),
    .io_status_vs(csr_io_status_vs),
    .io_status_spp(csr_io_status_spp),
    .io_status_mpie(csr_io_status_mpie),
    .io_status_ube(csr_io_status_ube),
    .io_status_spie(csr_io_status_spie),
    .io_status_upie(csr_io_status_upie),
    .io_status_mie(csr_io_status_mie),
    .io_status_hie(csr_io_status_hie),
    .io_status_sie(csr_io_status_sie),
    .io_status_uie(csr_io_status_uie),
    .io_evec(csr_io_evec),
    .io_exception(csr_io_exception),
    .io_retire(csr_io_retire),
    .io_cause(csr_io_cause),
    .io_pc(csr_io_pc),
    .io_tval(csr_io_tval),
    .io_gva(csr_io_gva),
    .io_time(csr_io_time),
    .io_interrupt(csr_io_interrupt),
    .io_interrupt_cause(csr_io_interrupt_cause),
    .io_bp_0_control_action(csr_io_bp_0_control_action),
    .io_bp_0_control_chain(csr_io_bp_0_control_chain),
    .io_bp_0_control_tmatch(csr_io_bp_0_control_tmatch),
    .io_bp_0_control_m(csr_io_bp_0_control_m),
    .io_bp_0_control_s(csr_io_bp_0_control_s),
    .io_bp_0_control_u(csr_io_bp_0_control_u),
    .io_bp_0_control_x(csr_io_bp_0_control_x),
    .io_bp_0_control_w(csr_io_bp_0_control_w),
    .io_bp_0_control_r(csr_io_bp_0_control_r),
    .io_bp_0_address(csr_io_bp_0_address),
    .io_bp_1_control_action(csr_io_bp_1_control_action),
    .io_bp_1_control_tmatch(csr_io_bp_1_control_tmatch),
    .io_bp_1_control_m(csr_io_bp_1_control_m),
    .io_bp_1_control_s(csr_io_bp_1_control_s),
    .io_bp_1_control_u(csr_io_bp_1_control_u),
    .io_bp_1_control_x(csr_io_bp_1_control_x),
    .io_bp_1_control_w(csr_io_bp_1_control_w),
    .io_bp_1_control_r(csr_io_bp_1_control_r),
    .io_bp_1_address(csr_io_bp_1_address),
    .io_pmp_0_cfg_l(csr_io_pmp_0_cfg_l),
    .io_pmp_0_cfg_a(csr_io_pmp_0_cfg_a),
    .io_pmp_0_cfg_x(csr_io_pmp_0_cfg_x),
    .io_pmp_0_cfg_w(csr_io_pmp_0_cfg_w),
    .io_pmp_0_cfg_r(csr_io_pmp_0_cfg_r),
    .io_pmp_0_addr(csr_io_pmp_0_addr),
    .io_pmp_0_mask(csr_io_pmp_0_mask),
    .io_pmp_1_cfg_l(csr_io_pmp_1_cfg_l),
    .io_pmp_1_cfg_a(csr_io_pmp_1_cfg_a),
    .io_pmp_1_cfg_x(csr_io_pmp_1_cfg_x),
    .io_pmp_1_cfg_w(csr_io_pmp_1_cfg_w),
    .io_pmp_1_cfg_r(csr_io_pmp_1_cfg_r),
    .io_pmp_1_addr(csr_io_pmp_1_addr),
    .io_pmp_1_mask(csr_io_pmp_1_mask),
    .io_pmp_2_cfg_l(csr_io_pmp_2_cfg_l),
    .io_pmp_2_cfg_a(csr_io_pmp_2_cfg_a),
    .io_pmp_2_cfg_x(csr_io_pmp_2_cfg_x),
    .io_pmp_2_cfg_w(csr_io_pmp_2_cfg_w),
    .io_pmp_2_cfg_r(csr_io_pmp_2_cfg_r),
    .io_pmp_2_addr(csr_io_pmp_2_addr),
    .io_pmp_2_mask(csr_io_pmp_2_mask),
    .io_pmp_3_cfg_l(csr_io_pmp_3_cfg_l),
    .io_pmp_3_cfg_a(csr_io_pmp_3_cfg_a),
    .io_pmp_3_cfg_x(csr_io_pmp_3_cfg_x),
    .io_pmp_3_cfg_w(csr_io_pmp_3_cfg_w),
    .io_pmp_3_cfg_r(csr_io_pmp_3_cfg_r),
    .io_pmp_3_addr(csr_io_pmp_3_addr),
    .io_pmp_3_mask(csr_io_pmp_3_mask),
    .io_pmp_4_cfg_l(csr_io_pmp_4_cfg_l),
    .io_pmp_4_cfg_a(csr_io_pmp_4_cfg_a),
    .io_pmp_4_cfg_x(csr_io_pmp_4_cfg_x),
    .io_pmp_4_cfg_w(csr_io_pmp_4_cfg_w),
    .io_pmp_4_cfg_r(csr_io_pmp_4_cfg_r),
    .io_pmp_4_addr(csr_io_pmp_4_addr),
    .io_pmp_4_mask(csr_io_pmp_4_mask),
    .io_pmp_5_cfg_l(csr_io_pmp_5_cfg_l),
    .io_pmp_5_cfg_a(csr_io_pmp_5_cfg_a),
    .io_pmp_5_cfg_x(csr_io_pmp_5_cfg_x),
    .io_pmp_5_cfg_w(csr_io_pmp_5_cfg_w),
    .io_pmp_5_cfg_r(csr_io_pmp_5_cfg_r),
    .io_pmp_5_addr(csr_io_pmp_5_addr),
    .io_pmp_5_mask(csr_io_pmp_5_mask),
    .io_pmp_6_cfg_l(csr_io_pmp_6_cfg_l),
    .io_pmp_6_cfg_a(csr_io_pmp_6_cfg_a),
    .io_pmp_6_cfg_x(csr_io_pmp_6_cfg_x),
    .io_pmp_6_cfg_w(csr_io_pmp_6_cfg_w),
    .io_pmp_6_cfg_r(csr_io_pmp_6_cfg_r),
    .io_pmp_6_addr(csr_io_pmp_6_addr),
    .io_pmp_6_mask(csr_io_pmp_6_mask),
    .io_pmp_7_cfg_l(csr_io_pmp_7_cfg_l),
    .io_pmp_7_cfg_a(csr_io_pmp_7_cfg_a),
    .io_pmp_7_cfg_x(csr_io_pmp_7_cfg_x),
    .io_pmp_7_cfg_w(csr_io_pmp_7_cfg_w),
    .io_pmp_7_cfg_r(csr_io_pmp_7_cfg_r),
    .io_pmp_7_addr(csr_io_pmp_7_addr),
    .io_pmp_7_mask(csr_io_pmp_7_mask),
    .io_inhibit_cycle(csr_io_inhibit_cycle),
    .io_inst_0(csr_io_inst_0),
    .io_trace_0_valid(csr_io_trace_0_valid),
    .io_trace_0_iaddr(csr_io_trace_0_iaddr),
    .io_trace_0_insn(csr_io_trace_0_insn),
    .io_trace_0_exception(csr_io_trace_0_exception),
    .io_customCSRs_0_value(csr_io_customCSRs_0_value)
  );
  BreakpointUnit bpu ( // @[RocketCore.scala 334:19]
    .io_status_debug(bpu_io_status_debug),
    .io_status_prv(bpu_io_status_prv),
    .io_bp_0_control_action(bpu_io_bp_0_control_action),
    .io_bp_0_control_chain(bpu_io_bp_0_control_chain),
    .io_bp_0_control_tmatch(bpu_io_bp_0_control_tmatch),
    .io_bp_0_control_m(bpu_io_bp_0_control_m),
    .io_bp_0_control_s(bpu_io_bp_0_control_s),
    .io_bp_0_control_u(bpu_io_bp_0_control_u),
    .io_bp_0_control_x(bpu_io_bp_0_control_x),
    .io_bp_0_control_w(bpu_io_bp_0_control_w),
    .io_bp_0_control_r(bpu_io_bp_0_control_r),
    .io_bp_0_address(bpu_io_bp_0_address),
    .io_bp_1_control_action(bpu_io_bp_1_control_action),
    .io_bp_1_control_tmatch(bpu_io_bp_1_control_tmatch),
    .io_bp_1_control_m(bpu_io_bp_1_control_m),
    .io_bp_1_control_s(bpu_io_bp_1_control_s),
    .io_bp_1_control_u(bpu_io_bp_1_control_u),
    .io_bp_1_control_x(bpu_io_bp_1_control_x),
    .io_bp_1_control_w(bpu_io_bp_1_control_w),
    .io_bp_1_control_r(bpu_io_bp_1_control_r),
    .io_bp_1_address(bpu_io_bp_1_address),
    .io_pc(bpu_io_pc),
    .io_ea(bpu_io_ea),
    .io_xcpt_if(bpu_io_xcpt_if),
    .io_xcpt_ld(bpu_io_xcpt_ld),
    .io_xcpt_st(bpu_io_xcpt_st),
    .io_debug_if(bpu_io_debug_if),
    .io_debug_ld(bpu_io_debug_ld),
    .io_debug_st(bpu_io_debug_st)
  );
  ALU alu ( // @[RocketCore.scala 399:19]
    .io_fn(alu_io_fn),
    .io_in2(alu_io_in2),
    .io_in1(alu_io_in1),
    .io_out(alu_io_out),
    .io_adder_out(alu_io_adder_out),
    .io_cmp_out(alu_io_cmp_out)
  );
  MulDiv div ( // @[RocketCore.scala 423:19]
    .clock(div_clock),
    .reset(div_reset),
    .io_req_ready(div_io_req_ready),
    .io_req_valid(div_io_req_valid),
    .io_req_bits_fn(div_io_req_bits_fn),
    .io_req_bits_in1(div_io_req_bits_in1),
    .io_req_bits_in2(div_io_req_bits_in2),
    .io_req_bits_tag(div_io_req_bits_tag),
    .io_kill(div_io_kill),
    .io_resp_ready(div_io_resp_ready),
    .io_resp_valid(div_io_resp_valid),
    .io_resp_bits_data(div_io_resp_bits_data),
    .io_resp_bits_tag(div_io_resp_bits_tag)
  );
  PlusArgTimeout PlusArgTimeout ( // @[PlusArg.scala 89:11]
    .clock(PlusArgTimeout_clock),
    .reset(PlusArgTimeout_reset),
    .io_count(PlusArgTimeout_io_count)
  );
  assign rf_id_rs_MPORT_en = 1'h1;
  assign rf_id_rs_MPORT_addr = ~id_raddr1;
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign rf_id_rs_MPORT_data = rf[rf_id_rs_MPORT_addr]; // @[RocketCore.scala 1061:15]
  `else
  assign rf_id_rs_MPORT_data = rf_id_rs_MPORT_addr >= 5'h1f ? _RAND_1[31:0] : rf[rf_id_rs_MPORT_addr]; // @[RocketCore.scala 1061:15]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign rf_id_rs_MPORT_1_en = 1'h1;
  assign rf_id_rs_MPORT_1_addr = ~id_raddr2;
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign rf_id_rs_MPORT_1_data = rf[rf_id_rs_MPORT_1_addr]; // @[RocketCore.scala 1061:15]
  `else
  assign rf_id_rs_MPORT_1_data = rf_id_rs_MPORT_1_addr >= 5'h1f ? _RAND_2[31:0] : rf[rf_id_rs_MPORT_1_addr]; // @[RocketCore.scala 1061:15]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign rf_MPORT_data = _rf_wdata_T ? io_dmem_resp_bits_data : _rf_wdata_T_5;
  assign rf_MPORT_addr = ~rf_waddr;
  assign rf_MPORT_mask = 1'h1;
  assign rf_MPORT_en = rf_wen & _T_133;
  assign io_imem_might_request = imem_might_request_reg; // @[RocketCore.scala 836:25]
  assign io_imem_req_valid = take_pc_wb | take_pc_mem; // @[RocketCore.scala 259:35]
  assign io_imem_req_bits_pc = wb_xcpt | csr_io_eret ? csr_io_evec : _io_imem_req_bits_pc_T_1; // @[RocketCore.scala 832:8]
  assign io_imem_req_bits_speculative = ~take_pc_wb; // @[RocketCore.scala 830:35]
  assign io_imem_resp_ready = ibuf_io_imem_ready; // @[RocketCore.scala 267:16]
  assign io_imem_btb_update_valid = mem_reg_valid & _wb_reg_replay_T & mem_wrong_npc & (~mem_cfi | mem_cfi_taken); // @[RocketCore.scala 851:77]
  assign io_imem_btb_update_bits_prediction_entry = mem_reg_btb_resp_entry; // @[RocketCore.scala 861:38]
  assign io_imem_btb_update_bits_pc = ~_io_imem_btb_update_bits_pc_T_1; // @[RocketCore.scala 860:33]
  assign io_imem_btb_update_bits_isValid = mem_ctrl_branch | mem_ctrl_jalr | mem_ctrl_jal; // @[RocketCore.scala 537:50]
  assign io_imem_btb_update_bits_br_pc = mem_reg_pc + _GEN_256; // @[RocketCore.scala 859:69]
  assign io_imem_btb_update_bits_cfiType = (mem_ctrl_jal | mem_ctrl_jalr) & mem_waddr[0] ? 2'h2 :
    _io_imem_btb_update_bits_cfiType_T_10; // @[RocketCore.scala 854:8]
  assign io_imem_bht_update_valid = mem_reg_valid & _wb_reg_replay_T; // @[RocketCore.scala 863:45]
  assign io_imem_bht_update_bits_prediction_history = mem_reg_btb_resp_bht_history; // @[RocketCore.scala 868:38]
  assign io_imem_bht_update_bits_pc = io_imem_btb_update_bits_pc; // @[RocketCore.scala 864:30]
  assign io_imem_bht_update_bits_branch = mem_ctrl_branch; // @[RocketCore.scala 867:34]
  assign io_imem_bht_update_bits_taken = mem_br_taken; // @[RocketCore.scala 865:33]
  assign io_imem_bht_update_bits_mispredict = ex_pc_valid ? mem_npc != ex_reg_pc : _mem_wrong_npc_T_3; // @[RocketCore.scala 533:8]
  assign io_imem_flush_icache = wb_reg_valid & wb_ctrl_fence_i & ~io_dmem_s2_nack; // @[RocketCore.scala 835:59]
  assign io_dmem_req_valid = ex_reg_valid & ex_ctrl_mem; // @[RocketCore.scala 881:41]
  assign io_dmem_req_bits_addr = alu_io_adder_out; // @[RocketCore.scala 889:25]
  assign io_dmem_req_bits_tag = {ex_waddr,1'h0}; // @[Cat.scala 31:58]
  assign io_dmem_req_bits_cmd = ex_ctrl_mem_cmd; // @[RocketCore.scala 885:25]
  assign io_dmem_req_bits_size = ex_reg_mem_size; // @[RocketCore.scala 886:25]
  assign io_dmem_req_bits_signed = ~ex_reg_inst[14]; // @[RocketCore.scala 887:30]
  assign io_dmem_req_bits_dprv = csr_io_status_dprv; // @[RocketCore.scala 891:31]
  assign io_dmem_req_bits_dv = 1'h0; // @[RocketCore.scala 892:37]
  assign io_dmem_s1_kill = killm_common | mem_ldst_xcpt; // @[RocketCore.scala 894:35]
  assign io_dmem_s1_data_data = mem_reg_rs2; // @[RocketCore.scala 893:24]
  assign io_ptw_status_debug = csr_io_status_debug; // @[RocketCore.scala 744:17]
  assign io_ptw_status_prv = csr_io_status_prv; // @[RocketCore.scala 744:17]
  assign io_ptw_pmp_0_cfg_l = csr_io_pmp_0_cfg_l; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_0_cfg_a = csr_io_pmp_0_cfg_a; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_0_cfg_x = csr_io_pmp_0_cfg_x; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_0_cfg_w = csr_io_pmp_0_cfg_w; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_0_cfg_r = csr_io_pmp_0_cfg_r; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_0_addr = csr_io_pmp_0_addr; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_0_mask = csr_io_pmp_0_mask; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_1_cfg_l = csr_io_pmp_1_cfg_l; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_1_cfg_a = csr_io_pmp_1_cfg_a; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_1_cfg_x = csr_io_pmp_1_cfg_x; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_1_cfg_w = csr_io_pmp_1_cfg_w; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_1_cfg_r = csr_io_pmp_1_cfg_r; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_1_addr = csr_io_pmp_1_addr; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_1_mask = csr_io_pmp_1_mask; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_2_cfg_l = csr_io_pmp_2_cfg_l; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_2_cfg_a = csr_io_pmp_2_cfg_a; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_2_cfg_x = csr_io_pmp_2_cfg_x; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_2_cfg_w = csr_io_pmp_2_cfg_w; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_2_cfg_r = csr_io_pmp_2_cfg_r; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_2_addr = csr_io_pmp_2_addr; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_2_mask = csr_io_pmp_2_mask; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_3_cfg_l = csr_io_pmp_3_cfg_l; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_3_cfg_a = csr_io_pmp_3_cfg_a; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_3_cfg_x = csr_io_pmp_3_cfg_x; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_3_cfg_w = csr_io_pmp_3_cfg_w; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_3_cfg_r = csr_io_pmp_3_cfg_r; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_3_addr = csr_io_pmp_3_addr; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_3_mask = csr_io_pmp_3_mask; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_4_cfg_l = csr_io_pmp_4_cfg_l; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_4_cfg_a = csr_io_pmp_4_cfg_a; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_4_cfg_x = csr_io_pmp_4_cfg_x; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_4_cfg_w = csr_io_pmp_4_cfg_w; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_4_cfg_r = csr_io_pmp_4_cfg_r; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_4_addr = csr_io_pmp_4_addr; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_4_mask = csr_io_pmp_4_mask; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_5_cfg_l = csr_io_pmp_5_cfg_l; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_5_cfg_a = csr_io_pmp_5_cfg_a; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_5_cfg_x = csr_io_pmp_5_cfg_x; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_5_cfg_w = csr_io_pmp_5_cfg_w; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_5_cfg_r = csr_io_pmp_5_cfg_r; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_5_addr = csr_io_pmp_5_addr; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_5_mask = csr_io_pmp_5_mask; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_6_cfg_l = csr_io_pmp_6_cfg_l; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_6_cfg_a = csr_io_pmp_6_cfg_a; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_6_cfg_x = csr_io_pmp_6_cfg_x; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_6_cfg_w = csr_io_pmp_6_cfg_w; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_6_cfg_r = csr_io_pmp_6_cfg_r; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_6_addr = csr_io_pmp_6_addr; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_6_mask = csr_io_pmp_6_mask; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_7_cfg_l = csr_io_pmp_7_cfg_l; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_7_cfg_a = csr_io_pmp_7_cfg_a; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_7_cfg_x = csr_io_pmp_7_cfg_x; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_7_cfg_w = csr_io_pmp_7_cfg_w; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_7_cfg_r = csr_io_pmp_7_cfg_r; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_7_addr = csr_io_pmp_7_addr; // @[RocketCore.scala 747:14]
  assign io_ptw_pmp_7_mask = csr_io_pmp_7_mask; // @[RocketCore.scala 747:14]
  assign io_ptw_customCSRs_csrs_0_value = csr_io_customCSRs_0_value; // @[RocketCore.scala 743:79]
  assign io_wfi = csr_io_status_wfi; // @[RocketCore.scala 910:10]
  assign ibuf_clock = clock;
  assign ibuf_reset = reset;
  assign ibuf_io_imem_valid = io_imem_resp_valid; // @[RocketCore.scala 267:16]
  assign ibuf_io_imem_bits_btb_taken = io_imem_resp_bits_btb_taken; // @[RocketCore.scala 267:16]
  assign ibuf_io_imem_bits_btb_bridx = io_imem_resp_bits_btb_bridx; // @[RocketCore.scala 267:16]
  assign ibuf_io_imem_bits_btb_entry = io_imem_resp_bits_btb_entry; // @[RocketCore.scala 267:16]
  assign ibuf_io_imem_bits_btb_bht_history = io_imem_resp_bits_btb_bht_history; // @[RocketCore.scala 267:16]
  assign ibuf_io_imem_bits_pc = io_imem_resp_bits_pc; // @[RocketCore.scala 267:16]
  assign ibuf_io_imem_bits_data = io_imem_resp_bits_data; // @[RocketCore.scala 267:16]
  assign ibuf_io_imem_bits_xcpt_ae_inst = io_imem_resp_bits_xcpt_ae_inst; // @[RocketCore.scala 267:16]
  assign ibuf_io_imem_bits_replay = io_imem_resp_bits_replay; // @[RocketCore.scala 267:16]
  assign ibuf_io_kill = take_pc_wb | take_pc_mem; // @[RocketCore.scala 259:35]
  assign ibuf_io_inst_0_ready = ~ctrl_stalld; // @[RocketCore.scala 849:28]
  assign csr_clock = clock;
  assign csr_reset = reset;
  assign csr_io_ungated_clock = clock; // @[RocketCore.scala 709:24]
  assign csr_io_interrupts_debug = io_interrupts_debug; // @[RocketCore.scala 715:21]
  assign csr_io_interrupts_mtip = io_interrupts_mtip; // @[RocketCore.scala 715:21]
  assign csr_io_interrupts_msip = io_interrupts_msip; // @[RocketCore.scala 715:21]
  assign csr_io_interrupts_meip = io_interrupts_meip; // @[RocketCore.scala 715:21]
  assign csr_io_interrupts_seip = io_interrupts_seip; // @[RocketCore.scala 715:21]
  assign csr_io_hartid = io_hartid; // @[RocketCore.scala 716:17]
  assign csr_io_rw_addr = wb_reg_inst[31:20]; // @[RocketCore.scala 748:32]
  assign csr_io_rw_cmd = wb_ctrl_csr & _csr_io_rw_cmd_T_1; // @[CSR.scala 167:9]
  assign csr_io_rw_wdata = wb_reg_wdata; // @[RocketCore.scala 750:19]
  assign csr_io_decode_0_inst = ibuf_io_inst_0_bits_inst_bits; // @[RocketCore.scala 710:25]
  assign csr_io_exception = wb_reg_xcpt | _T_95 | _T_97 | _T_103 | _T_105 | _T_107 | _T_109; // @[RocketCore.scala 1021:26]
  assign csr_io_retire = wb_reg_valid & ~replay_wb_common & ~wb_xcpt; // @[RocketCore.scala 697:45]
  assign csr_io_cause = wb_reg_xcpt ? wb_reg_cause : {{27'd0}, _T_123}; // @[Mux.scala 47:70]
  assign csr_io_pc = wb_reg_pc; // @[RocketCore.scala 722:13]
  assign csr_io_tval = tval_valid ? wb_reg_wdata : 32'h0; // @[RocketCore.scala 729:21]
  assign csr_io_gva = wb_xcpt & (tval_dmem_addr & wb_reg_hls_or_dv); // @[RocketCore.scala 728:25]
  assign csr_io_inst_0 = {_csr_io_inst_0_T_3,wb_reg_raw_inst[15:0]}; // @[Cat.scala 31:58]
  assign bpu_io_status_debug = csr_io_status_debug; // @[RocketCore.scala 335:17]
  assign bpu_io_status_prv = csr_io_status_prv; // @[RocketCore.scala 335:17]
  assign bpu_io_bp_0_control_action = csr_io_bp_0_control_action; // @[RocketCore.scala 336:13]
  assign bpu_io_bp_0_control_chain = csr_io_bp_0_control_chain; // @[RocketCore.scala 336:13]
  assign bpu_io_bp_0_control_tmatch = csr_io_bp_0_control_tmatch; // @[RocketCore.scala 336:13]
  assign bpu_io_bp_0_control_m = csr_io_bp_0_control_m; // @[RocketCore.scala 336:13]
  assign bpu_io_bp_0_control_s = csr_io_bp_0_control_s; // @[RocketCore.scala 336:13]
  assign bpu_io_bp_0_control_u = csr_io_bp_0_control_u; // @[RocketCore.scala 336:13]
  assign bpu_io_bp_0_control_x = csr_io_bp_0_control_x; // @[RocketCore.scala 336:13]
  assign bpu_io_bp_0_control_w = csr_io_bp_0_control_w; // @[RocketCore.scala 336:13]
  assign bpu_io_bp_0_control_r = csr_io_bp_0_control_r; // @[RocketCore.scala 336:13]
  assign bpu_io_bp_0_address = csr_io_bp_0_address; // @[RocketCore.scala 336:13]
  assign bpu_io_bp_1_control_action = csr_io_bp_1_control_action; // @[RocketCore.scala 336:13]
  assign bpu_io_bp_1_control_tmatch = csr_io_bp_1_control_tmatch; // @[RocketCore.scala 336:13]
  assign bpu_io_bp_1_control_m = csr_io_bp_1_control_m; // @[RocketCore.scala 336:13]
  assign bpu_io_bp_1_control_s = csr_io_bp_1_control_s; // @[RocketCore.scala 336:13]
  assign bpu_io_bp_1_control_u = csr_io_bp_1_control_u; // @[RocketCore.scala 336:13]
  assign bpu_io_bp_1_control_x = csr_io_bp_1_control_x; // @[RocketCore.scala 336:13]
  assign bpu_io_bp_1_control_w = csr_io_bp_1_control_w; // @[RocketCore.scala 336:13]
  assign bpu_io_bp_1_control_r = csr_io_bp_1_control_r; // @[RocketCore.scala 336:13]
  assign bpu_io_bp_1_address = csr_io_bp_1_address; // @[RocketCore.scala 336:13]
  assign bpu_io_pc = ibuf_io_pc; // @[RocketCore.scala 337:13]
  assign bpu_io_ea = mem_reg_wdata; // @[RocketCore.scala 338:13]
  assign alu_io_fn = ex_ctrl_alu_fn; // @[RocketCore.scala 401:13]
  assign alu_io_in2 = 2'h1 == ex_ctrl_sel_alu2 ? $signed({{28{_ex_op2_T_1[3]}},_ex_op2_T_1}) : $signed(_ex_op2_T_5); // @[RocketCore.scala 402:24]
  assign alu_io_in1 = 2'h2 == ex_ctrl_sel_alu1 ? $signed(ex_reg_pc) : $signed(_ex_op1_T_3); // @[RocketCore.scala 403:24]
  assign div_clock = clock;
  assign div_reset = reset;
  assign div_io_req_valid = ex_reg_valid & ex_ctrl_div; // @[RocketCore.scala 424:36]
  assign div_io_req_bits_fn = ex_ctrl_alu_fn; // @[RocketCore.scala 426:22]
  assign div_io_req_bits_in1 = ex_reg_rs_bypass_0 ? _ex_rs_T_5 : _ex_rs_T_6; // @[RocketCore.scala 389:14]
  assign div_io_req_bits_in2 = ex_reg_rs_bypass_1 ? _ex_rs_T_12 : _ex_rs_T_13; // @[RocketCore.scala 389:14]
  assign div_io_req_bits_tag = ex_reg_inst[11:7]; // @[RocketCore.scala 373:29]
  assign div_io_kill = killm_common & div_io_kill_REG; // @[RocketCore.scala 607:31]
  assign div_io_resp_ready = dmem_resp_replay & dmem_resp_xpu ? 1'h0 : _ctrl_stalld_T_17; // @[RocketCore.scala 676:21 689:44 690:23]
  assign PlusArgTimeout_clock = clock;
  assign PlusArgTimeout_reset = reset;
  assign PlusArgTimeout_io_count = csr_io_time; // @[PlusArg.scala 89:82]
  always @(posedge clock) begin
    if (rf_MPORT_en & rf_MPORT_mask) begin
      rf[rf_MPORT_addr] <= rf_MPORT_data; // @[RocketCore.scala 1061:15]
    end
    if (unpause) begin // @[RocketCore.scala 908:18]
      id_reg_pause <= 1'h0; // @[RocketCore.scala 908:33]
    end else if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
      id_reg_pause <= _GEN_1;
    end
    imem_might_request_reg <= ex_pc_valid | mem_pc_valid | io_ptw_customCSRs_csrs_0_value[1]; // @[RocketCore.scala 837:59]
    if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
      ex_ctrl_branch <= id_ctrl_decoder_3; // @[RocketCore.scala 443:13]
    end
    if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
      ex_ctrl_jal <= id_ctrl_decoder_4; // @[RocketCore.scala 443:13]
    end
    if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
      ex_ctrl_jalr <= id_ctrl_decoder_5; // @[RocketCore.scala 443:13]
    end
    if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
      ex_ctrl_rxs2 <= id_ctrl_decoder_6; // @[RocketCore.scala 443:13]
    end
    if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
      ex_ctrl_rxs1 <= id_ctrl_decoder_7; // @[RocketCore.scala 443:13]
    end
    if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
      if (id_xcpt) begin // @[RocketCore.scala 450:20]
        if (bpu_io_xcpt_if | |_T_37) begin // @[RocketCore.scala 460:52]
          ex_ctrl_sel_alu2 <= 2'h0; // @[RocketCore.scala 462:26]
        end else if (|_T_35) begin // @[RocketCore.scala 455:34]
          ex_ctrl_sel_alu2 <= 2'h1; // @[RocketCore.scala 457:26]
        end else begin
          ex_ctrl_sel_alu2 <= 2'h0; // @[RocketCore.scala 454:24]
        end
      end else begin
        ex_ctrl_sel_alu2 <= id_ctrl_decoder_9; // @[RocketCore.scala 443:13]
      end
    end
    if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
      if (id_xcpt) begin // @[RocketCore.scala 450:20]
        if (bpu_io_xcpt_if | |_T_37) begin // @[RocketCore.scala 460:52]
          ex_ctrl_sel_alu1 <= 2'h2; // @[RocketCore.scala 461:26]
        end else if (|_T_35) begin // @[RocketCore.scala 455:34]
          ex_ctrl_sel_alu1 <= 2'h2; // @[RocketCore.scala 456:26]
        end else begin
          ex_ctrl_sel_alu1 <= 2'h1; // @[RocketCore.scala 453:24]
        end
      end else begin
        ex_ctrl_sel_alu1 <= id_ctrl_decoder_10; // @[RocketCore.scala 443:13]
      end
    end
    if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
      ex_ctrl_sel_imm <= id_ctrl_decoder_11; // @[RocketCore.scala 443:13]
    end
    if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
      if (id_xcpt) begin // @[RocketCore.scala 450:20]
        ex_ctrl_alu_fn <= 4'h0; // @[RocketCore.scala 451:22]
      end else begin
        ex_ctrl_alu_fn <= id_ctrl_decoder_13; // @[RocketCore.scala 443:13]
      end
    end
    if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
      ex_ctrl_mem <= id_ctrl_decoder_14; // @[RocketCore.scala 443:13]
    end
    if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
      ex_ctrl_mem_cmd <= id_ctrl_decoder_15;
    end
    if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
      ex_ctrl_div <= id_ctrl_decoder_21; // @[RocketCore.scala 443:13]
    end
    if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
      ex_ctrl_wxd <= id_ctrl_decoder_22; // @[RocketCore.scala 443:13]
    end
    if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
      if (id_system_insn & id_ctrl_decoder_14) begin // @[RocketCore.scala 295:19]
        ex_ctrl_csr <= 3'h0;
      end else if (id_csr_ren) begin // @[RocketCore.scala 295:61]
        ex_ctrl_csr <= 3'h2;
      end else begin
        ex_ctrl_csr <= id_ctrl_decoder_23;
      end
    end
    if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
      ex_ctrl_fence_i <= id_ctrl_decoder_24; // @[RocketCore.scala 443:13]
    end
    if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
      if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
        mem_ctrl_branch <= ex_ctrl_branch; // @[RocketCore.scala 553:14]
      end
    end
    if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
      if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
        mem_ctrl_jal <= ex_ctrl_jal; // @[RocketCore.scala 553:14]
      end
    end
    if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
      if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
        mem_ctrl_jalr <= ex_ctrl_jalr; // @[RocketCore.scala 553:14]
      end
    end
    if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
      if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
        mem_ctrl_rxs2 <= ex_ctrl_rxs2; // @[RocketCore.scala 553:14]
      end
    end
    if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
      if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
        mem_ctrl_rxs1 <= ex_ctrl_rxs1; // @[RocketCore.scala 553:14]
      end
    end
    if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
      if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
        mem_ctrl_mem <= ex_ctrl_mem; // @[RocketCore.scala 553:14]
      end
    end
    if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
      if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
        mem_ctrl_div <= ex_ctrl_div; // @[RocketCore.scala 553:14]
      end
    end
    if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
      if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
        mem_ctrl_wxd <= ex_ctrl_wxd; // @[RocketCore.scala 553:14]
      end
    end
    if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
      if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
        mem_ctrl_csr <= ex_ctrl_csr; // @[RocketCore.scala 553:14]
      end
    end
    if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
      if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
        mem_ctrl_fence_i <= _GEN_80;
      end
    end
    if (mem_pc_valid) begin // @[RocketCore.scala 615:23]
      wb_ctrl_rxs2 <= mem_ctrl_rxs2; // @[RocketCore.scala 616:13]
    end
    if (mem_pc_valid) begin // @[RocketCore.scala 615:23]
      wb_ctrl_rxs1 <= mem_ctrl_rxs1; // @[RocketCore.scala 616:13]
    end
    if (mem_pc_valid) begin // @[RocketCore.scala 615:23]
      wb_ctrl_mem <= mem_ctrl_mem; // @[RocketCore.scala 616:13]
    end
    if (mem_pc_valid) begin // @[RocketCore.scala 615:23]
      wb_ctrl_div <= mem_ctrl_div; // @[RocketCore.scala 616:13]
    end
    if (mem_pc_valid) begin // @[RocketCore.scala 615:23]
      wb_ctrl_wxd <= mem_ctrl_wxd; // @[RocketCore.scala 616:13]
    end
    if (mem_pc_valid) begin // @[RocketCore.scala 615:23]
      wb_ctrl_csr <= mem_ctrl_csr; // @[RocketCore.scala 616:13]
    end
    if (mem_pc_valid) begin // @[RocketCore.scala 615:23]
      wb_ctrl_fence_i <= mem_ctrl_fence_i; // @[RocketCore.scala 616:13]
    end
    ex_reg_xcpt_interrupt <= _ex_reg_replay_T_1 & csr_io_interrupt; // @[RocketCore.scala 440:62]
    ex_reg_valid <= ~ctrl_killd; // @[RocketCore.scala 437:19]
    if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
      if (id_xcpt) begin // @[RocketCore.scala 450:20]
        ex_reg_rvc <= _GEN_5;
      end else begin
        ex_reg_rvc <= ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala 444:16]
      end
    end
    if (_ex_reg_valid_T | csr_io_interrupt | ibuf_io_inst_0_bits_replay) begin // @[RocketCore.scala 498:73]
      ex_reg_btb_resp_entry <= ibuf_io_btb_resp_entry; // @[RocketCore.scala 503:21]
    end
    if (_ex_reg_valid_T | csr_io_interrupt | ibuf_io_inst_0_bits_replay) begin // @[RocketCore.scala 498:73]
      ex_reg_btb_resp_bht_history <= ibuf_io_btb_resp_bht_history; // @[RocketCore.scala 503:21]
    end
    ex_reg_xcpt <= _ex_reg_valid_T & id_xcpt; // @[RocketCore.scala 439:30]
    if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
      ex_reg_flush_pipe <= id_ctrl_decoder_24 | id_csr_flush; // @[RocketCore.scala 465:23]
    end
    if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
      ex_reg_load_use <= id_load_use; // @[RocketCore.scala 466:21]
    end
    if (_ex_reg_valid_T | csr_io_interrupt | ibuf_io_inst_0_bits_replay) begin // @[RocketCore.scala 498:73]
      if (csr_io_interrupt) begin // @[Mux.scala 47:70]
        ex_reg_cause <= csr_io_interrupt_cause;
      end else begin
        ex_reg_cause <= {{27'd0}, _T_18};
      end
    end
    ex_reg_replay <= ~take_pc_mem_wb & ibuf_io_inst_0_valid & ibuf_io_inst_0_bits_replay; // @[RocketCore.scala 438:54]
    if (_ex_reg_valid_T | csr_io_interrupt | ibuf_io_inst_0_bits_replay) begin // @[RocketCore.scala 498:73]
      ex_reg_pc <= ibuf_io_pc; // @[RocketCore.scala 502:15]
    end
    if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
      if (_T_46) begin // @[RocketCore.scala 469:81]
        ex_reg_mem_size <= _ex_reg_mem_size_T_6; // @[RocketCore.scala 470:23]
      end else begin
        ex_reg_mem_size <= ibuf_io_inst_0_bits_inst_bits[13:12]; // @[RocketCore.scala 468:21]
      end
    end
    if (_ex_reg_valid_T | csr_io_interrupt | ibuf_io_inst_0_bits_replay) begin // @[RocketCore.scala 498:73]
      ex_reg_inst <= ibuf_io_inst_0_bits_inst_bits; // @[RocketCore.scala 500:17]
    end
    if (_ex_reg_valid_T | csr_io_interrupt | ibuf_io_inst_0_bits_replay) begin // @[RocketCore.scala 498:73]
      ex_reg_raw_inst <= ibuf_io_inst_0_bits_raw; // @[RocketCore.scala 501:21]
    end
    mem_reg_xcpt_interrupt <= _ex_reg_replay_T & ex_reg_xcpt_interrupt; // @[RocketCore.scala 546:45]
    mem_reg_valid <= ~ctrl_killx; // @[RocketCore.scala 543:20]
    if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
      if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
        mem_reg_rvc <= ex_reg_rvc; // @[RocketCore.scala 556:17]
      end
    end
    if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
      if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
        mem_reg_btb_resp_entry <= ex_reg_btb_resp_entry; // @[RocketCore.scala 560:22]
      end
    end
    if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
      if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
        mem_reg_btb_resp_bht_history <= ex_reg_btb_resp_bht_history; // @[RocketCore.scala 560:22]
      end
    end
    mem_reg_xcpt <= _mem_reg_valid_T & ex_xcpt; // @[RocketCore.scala 545:31]
    mem_reg_replay <= _ex_reg_replay_T & replay_ex; // @[RocketCore.scala 544:37]
    if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
      if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
        mem_reg_flush_pipe <= _GEN_81;
      end
    end
    if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
      if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
        mem_reg_cause <= ex_reg_cause; // @[RocketCore.scala 565:19]
      end
    end
    if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
      if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
        mem_reg_slow_bypass <= ex_slow_bypass; // @[RocketCore.scala 562:25]
      end
    end
    if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
      if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
        mem_reg_load <= ex_ctrl_mem & _mem_reg_load_T_24; // @[RocketCore.scala 557:18]
      end
    end
    if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
      if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
        mem_reg_store <= ex_ctrl_mem & _mem_reg_store_T_22; // @[RocketCore.scala 558:19]
      end
    end
    if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
      if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
        mem_reg_pc <= ex_reg_pc; // @[RocketCore.scala 570:16]
      end
    end
    if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
      if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
        mem_reg_inst <= ex_reg_inst; // @[RocketCore.scala 566:18]
      end
    end
    if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
      if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
        mem_reg_hls_or_dv <= io_dmem_req_bits_dv; // @[RocketCore.scala 569:23]
      end
    end
    if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
      if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
        mem_reg_raw_inst <= ex_reg_raw_inst; // @[RocketCore.scala 567:22]
      end
    end
    if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
      if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
        mem_reg_wdata <= _mem_reg_wdata_T; // @[RocketCore.scala 571:19]
      end
    end
    if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
      if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
        if (ex_ctrl_rxs2 & ex_ctrl_mem) begin // @[RocketCore.scala 574:71]
          if (ex_reg_mem_size == 2'h0) begin // @[AMOALU.scala 26:13]
            mem_reg_rs2 <= _mem_reg_rs2_T_3;
          end else begin
            mem_reg_rs2 <= _mem_reg_rs2_T_7;
          end
        end
      end
    end
    if (!(mem_reg_valid & mem_reg_flush_pipe)) begin // @[RocketCore.scala 550:46]
      if (ex_pc_valid) begin // @[RocketCore.scala 552:28]
        mem_br_taken <= alu_io_cmp_out; // @[RocketCore.scala 572:18]
      end
    end
    wb_reg_valid <= ~ctrl_killm; // @[RocketCore.scala 611:19]
    wb_reg_xcpt <= mem_xcpt & _wb_reg_replay_T; // @[RocketCore.scala 613:27]
    wb_reg_replay <= replay_mem & ~take_pc_wb; // @[RocketCore.scala 612:31]
    wb_reg_flush_pipe <= _wb_reg_valid_T & mem_reg_flush_pipe; // @[RocketCore.scala 614:36]
    if (mem_pc_valid) begin // @[RocketCore.scala 615:23]
      if (_T_70) begin // @[Mux.scala 47:70]
        wb_reg_cause <= mem_reg_cause;
      end else begin
        wb_reg_cause <= {{28'd0}, _T_74};
      end
    end
    if (mem_pc_valid) begin // @[RocketCore.scala 615:23]
      wb_reg_pc <= mem_reg_pc; // @[RocketCore.scala 630:15]
    end
    if (mem_pc_valid) begin // @[RocketCore.scala 615:23]
      wb_reg_hls_or_dv <= mem_reg_hls_or_dv; // @[RocketCore.scala 627:22]
    end
    if (mem_pc_valid) begin // @[RocketCore.scala 615:23]
      wb_reg_inst <= mem_reg_inst; // @[RocketCore.scala 624:17]
    end
    if (mem_pc_valid) begin // @[RocketCore.scala 615:23]
      wb_reg_raw_inst <= mem_reg_raw_inst; // @[RocketCore.scala 625:21]
    end
    if (mem_pc_valid) begin // @[RocketCore.scala 615:23]
      wb_reg_wdata <= mem_int_wdata; // @[RocketCore.scala 618:18]
    end
    if (reset) begin // @[RocketCore.scala 283:25]
      id_reg_fence <= 1'h0; // @[RocketCore.scala 283:25]
    end else if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
      id_reg_fence <= _GEN_2;
    end else if (~id_mem_busy) begin // @[RocketCore.scala 327:23]
      id_reg_fence <= 1'h0; // @[RocketCore.scala 327:38]
    end
    if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
      if (id_illegal_insn) begin // @[RocketCore.scala 491:47]
        ex_reg_rs_bypass_0 <= 1'h0; // @[RocketCore.scala 493:27]
      end else begin
        ex_reg_rs_bypass_0 <= do_bypass; // @[RocketCore.scala 484:27]
      end
    end
    if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
      ex_reg_rs_bypass_1 <= do_bypass_1; // @[RocketCore.scala 484:27]
    end
    if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
      if (id_illegal_insn) begin // @[RocketCore.scala 491:47]
        ex_reg_rs_lsb_0 <= inst[1:0]; // @[RocketCore.scala 494:24]
      end else if (id_ctrl_decoder_7 & ~do_bypass) begin // @[RocketCore.scala 486:38]
        ex_reg_rs_lsb_0 <= id_rs_0[1:0]; // @[RocketCore.scala 487:26]
      end else if (id_bypass_src_0_0) begin // @[Mux.scala 47:70]
        ex_reg_rs_lsb_0 <= 2'h0;
      end else begin
        ex_reg_rs_lsb_0 <= _bypass_src_T_1;
      end
    end
    if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
      if (id_ctrl_decoder_6 & ~do_bypass_1) begin // @[RocketCore.scala 486:38]
        ex_reg_rs_lsb_1 <= id_rs_1[1:0]; // @[RocketCore.scala 487:26]
      end else if (id_bypass_src_1_0) begin // @[Mux.scala 47:70]
        ex_reg_rs_lsb_1 <= 2'h0;
      end else if (id_bypass_src_1_1) begin // @[Mux.scala 47:70]
        ex_reg_rs_lsb_1 <= 2'h1;
      end else begin
        ex_reg_rs_lsb_1 <= _bypass_src_T_2;
      end
    end
    if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
      if (id_illegal_insn) begin // @[RocketCore.scala 491:47]
        ex_reg_rs_msb_0 <= inst[31:2]; // @[RocketCore.scala 495:24]
      end else if (id_ctrl_decoder_7 & ~do_bypass) begin // @[RocketCore.scala 486:38]
        ex_reg_rs_msb_0 <= id_rs_0[31:2]; // @[RocketCore.scala 488:26]
      end
    end
    if (_ex_reg_valid_T) begin // @[RocketCore.scala 442:22]
      if (id_ctrl_decoder_6 & ~do_bypass_1) begin // @[RocketCore.scala 486:38]
        ex_reg_rs_msb_1 <= id_rs_1[31:2]; // @[RocketCore.scala 488:26]
      end
    end
    if (reset) begin // @[RocketCore.scala 1047:25]
      _r <= 32'h0; // @[RocketCore.scala 1047:25]
    end else if (_T_153) begin // @[RocketCore.scala 1055:18]
      _r <= _T_152; // @[RocketCore.scala 1055:23]
    end else if (ll_wen) begin // @[RocketCore.scala 1055:18]
      _r <= _T_147; // @[RocketCore.scala 1055:23]
    end
    blocked <= _replay_ex_structural_T & _dcache_blocked_T & (blocked | io_dmem_req_valid | io_dmem_s2_nack); // @[RocketCore.scala 808:83]
    div_io_kill_REG <= div_io_req_ready & div_io_req_valid; // @[Decoupled.scala 50:35]
    if (ex_reg_rs_bypass_0) begin // @[RocketCore.scala 389:14]
      if (ex_reg_rs_lsb_0 == 2'h3) begin // @[package.scala 32:76]
        coreMonitorBundle_rd0val_x23 <= io_dmem_resp_bits_data_word_bypass;
      end else if (ex_reg_rs_lsb_0 == 2'h2) begin // @[package.scala 32:76]
        coreMonitorBundle_rd0val_x23 <= wb_reg_wdata;
      end else if (ex_reg_rs_lsb_0 == 2'h1) begin // @[package.scala 32:76]
        coreMonitorBundle_rd0val_x23 <= mem_reg_wdata;
      end else begin
        coreMonitorBundle_rd0val_x23 <= 32'h0;
      end
    end else begin
      coreMonitorBundle_rd0val_x23 <= _ex_rs_T_6;
    end
    coreMonitorBundle_rd0val_REG <= coreMonitorBundle_rd0val_x23; // @[RocketCore.scala 942:34]
    if (ex_reg_rs_bypass_1) begin // @[RocketCore.scala 389:14]
      if (ex_reg_rs_lsb_1 == 2'h3) begin // @[package.scala 32:76]
        coreMonitorBundle_rd1val_x29 <= io_dmem_resp_bits_data_word_bypass;
      end else if (ex_reg_rs_lsb_1 == 2'h2) begin // @[package.scala 32:76]
        coreMonitorBundle_rd1val_x29 <= wb_reg_wdata;
      end else if (ex_reg_rs_lsb_1 == 2'h1) begin // @[package.scala 32:76]
        coreMonitorBundle_rd1val_x29 <= mem_reg_wdata;
      end else begin
        coreMonitorBundle_rd1val_x29 <= 32'h0;
      end
    end else begin
      coreMonitorBundle_rd1val_x29 <= _ex_rs_T_13;
    end
    coreMonitorBundle_rd1val_REG <= coreMonitorBundle_rd1val_x29; // @[RocketCore.scala 944:34]
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~htval_valid_imem) & ~reset) begin
          $fatal; // @[RocketCore.scala 733:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(~htval_valid_imem)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at RocketCore.scala:733 assert(!htval_valid_imem || io.imem.gpa.valid)\n"); // @[RocketCore.scala 733:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (csr_io_trace_0_valid & _csr_io_htval_T_3) begin
          $fwrite(32'h80000002,"C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n",io_hartid,
            _io_fpu_time_T,coreMonitorBundle_valid,coreMonitorBundle_pc,_T_155,_T_156,coreMonitorBundle_wrenx,_T_158,
            _T_160,_T_162,_T_164,coreMonitorBundle_inst,coreMonitorBundle_inst); // @[RocketCore.scala 977:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_GARBAGE_ASSIGN
  _RAND_1 = {1{`RANDOM}};
  _RAND_2 = {1{`RANDOM}};
`endif // RANDOMIZE_GARBAGE_ASSIGN
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 31; initvar = initvar+1)
    rf[initvar] = _RAND_0[31:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_3 = {1{`RANDOM}};
  id_reg_pause = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  imem_might_request_reg = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  ex_ctrl_branch = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  ex_ctrl_jal = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  ex_ctrl_jalr = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  ex_ctrl_rxs2 = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  ex_ctrl_rxs1 = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  ex_ctrl_sel_alu2 = _RAND_10[1:0];
  _RAND_11 = {1{`RANDOM}};
  ex_ctrl_sel_alu1 = _RAND_11[1:0];
  _RAND_12 = {1{`RANDOM}};
  ex_ctrl_sel_imm = _RAND_12[2:0];
  _RAND_13 = {1{`RANDOM}};
  ex_ctrl_alu_fn = _RAND_13[3:0];
  _RAND_14 = {1{`RANDOM}};
  ex_ctrl_mem = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  ex_ctrl_mem_cmd = _RAND_15[4:0];
  _RAND_16 = {1{`RANDOM}};
  ex_ctrl_div = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  ex_ctrl_wxd = _RAND_17[0:0];
  _RAND_18 = {1{`RANDOM}};
  ex_ctrl_csr = _RAND_18[2:0];
  _RAND_19 = {1{`RANDOM}};
  ex_ctrl_fence_i = _RAND_19[0:0];
  _RAND_20 = {1{`RANDOM}};
  mem_ctrl_branch = _RAND_20[0:0];
  _RAND_21 = {1{`RANDOM}};
  mem_ctrl_jal = _RAND_21[0:0];
  _RAND_22 = {1{`RANDOM}};
  mem_ctrl_jalr = _RAND_22[0:0];
  _RAND_23 = {1{`RANDOM}};
  mem_ctrl_rxs2 = _RAND_23[0:0];
  _RAND_24 = {1{`RANDOM}};
  mem_ctrl_rxs1 = _RAND_24[0:0];
  _RAND_25 = {1{`RANDOM}};
  mem_ctrl_mem = _RAND_25[0:0];
  _RAND_26 = {1{`RANDOM}};
  mem_ctrl_div = _RAND_26[0:0];
  _RAND_27 = {1{`RANDOM}};
  mem_ctrl_wxd = _RAND_27[0:0];
  _RAND_28 = {1{`RANDOM}};
  mem_ctrl_csr = _RAND_28[2:0];
  _RAND_29 = {1{`RANDOM}};
  mem_ctrl_fence_i = _RAND_29[0:0];
  _RAND_30 = {1{`RANDOM}};
  wb_ctrl_rxs2 = _RAND_30[0:0];
  _RAND_31 = {1{`RANDOM}};
  wb_ctrl_rxs1 = _RAND_31[0:0];
  _RAND_32 = {1{`RANDOM}};
  wb_ctrl_mem = _RAND_32[0:0];
  _RAND_33 = {1{`RANDOM}};
  wb_ctrl_div = _RAND_33[0:0];
  _RAND_34 = {1{`RANDOM}};
  wb_ctrl_wxd = _RAND_34[0:0];
  _RAND_35 = {1{`RANDOM}};
  wb_ctrl_csr = _RAND_35[2:0];
  _RAND_36 = {1{`RANDOM}};
  wb_ctrl_fence_i = _RAND_36[0:0];
  _RAND_37 = {1{`RANDOM}};
  ex_reg_xcpt_interrupt = _RAND_37[0:0];
  _RAND_38 = {1{`RANDOM}};
  ex_reg_valid = _RAND_38[0:0];
  _RAND_39 = {1{`RANDOM}};
  ex_reg_rvc = _RAND_39[0:0];
  _RAND_40 = {1{`RANDOM}};
  ex_reg_btb_resp_entry = _RAND_40[4:0];
  _RAND_41 = {1{`RANDOM}};
  ex_reg_btb_resp_bht_history = _RAND_41[7:0];
  _RAND_42 = {1{`RANDOM}};
  ex_reg_xcpt = _RAND_42[0:0];
  _RAND_43 = {1{`RANDOM}};
  ex_reg_flush_pipe = _RAND_43[0:0];
  _RAND_44 = {1{`RANDOM}};
  ex_reg_load_use = _RAND_44[0:0];
  _RAND_45 = {1{`RANDOM}};
  ex_reg_cause = _RAND_45[31:0];
  _RAND_46 = {1{`RANDOM}};
  ex_reg_replay = _RAND_46[0:0];
  _RAND_47 = {1{`RANDOM}};
  ex_reg_pc = _RAND_47[31:0];
  _RAND_48 = {1{`RANDOM}};
  ex_reg_mem_size = _RAND_48[1:0];
  _RAND_49 = {1{`RANDOM}};
  ex_reg_inst = _RAND_49[31:0];
  _RAND_50 = {1{`RANDOM}};
  ex_reg_raw_inst = _RAND_50[31:0];
  _RAND_51 = {1{`RANDOM}};
  mem_reg_xcpt_interrupt = _RAND_51[0:0];
  _RAND_52 = {1{`RANDOM}};
  mem_reg_valid = _RAND_52[0:0];
  _RAND_53 = {1{`RANDOM}};
  mem_reg_rvc = _RAND_53[0:0];
  _RAND_54 = {1{`RANDOM}};
  mem_reg_btb_resp_entry = _RAND_54[4:0];
  _RAND_55 = {1{`RANDOM}};
  mem_reg_btb_resp_bht_history = _RAND_55[7:0];
  _RAND_56 = {1{`RANDOM}};
  mem_reg_xcpt = _RAND_56[0:0];
  _RAND_57 = {1{`RANDOM}};
  mem_reg_replay = _RAND_57[0:0];
  _RAND_58 = {1{`RANDOM}};
  mem_reg_flush_pipe = _RAND_58[0:0];
  _RAND_59 = {1{`RANDOM}};
  mem_reg_cause = _RAND_59[31:0];
  _RAND_60 = {1{`RANDOM}};
  mem_reg_slow_bypass = _RAND_60[0:0];
  _RAND_61 = {1{`RANDOM}};
  mem_reg_load = _RAND_61[0:0];
  _RAND_62 = {1{`RANDOM}};
  mem_reg_store = _RAND_62[0:0];
  _RAND_63 = {1{`RANDOM}};
  mem_reg_pc = _RAND_63[31:0];
  _RAND_64 = {1{`RANDOM}};
  mem_reg_inst = _RAND_64[31:0];
  _RAND_65 = {1{`RANDOM}};
  mem_reg_hls_or_dv = _RAND_65[0:0];
  _RAND_66 = {1{`RANDOM}};
  mem_reg_raw_inst = _RAND_66[31:0];
  _RAND_67 = {1{`RANDOM}};
  mem_reg_wdata = _RAND_67[31:0];
  _RAND_68 = {1{`RANDOM}};
  mem_reg_rs2 = _RAND_68[31:0];
  _RAND_69 = {1{`RANDOM}};
  mem_br_taken = _RAND_69[0:0];
  _RAND_70 = {1{`RANDOM}};
  wb_reg_valid = _RAND_70[0:0];
  _RAND_71 = {1{`RANDOM}};
  wb_reg_xcpt = _RAND_71[0:0];
  _RAND_72 = {1{`RANDOM}};
  wb_reg_replay = _RAND_72[0:0];
  _RAND_73 = {1{`RANDOM}};
  wb_reg_flush_pipe = _RAND_73[0:0];
  _RAND_74 = {1{`RANDOM}};
  wb_reg_cause = _RAND_74[31:0];
  _RAND_75 = {1{`RANDOM}};
  wb_reg_pc = _RAND_75[31:0];
  _RAND_76 = {1{`RANDOM}};
  wb_reg_hls_or_dv = _RAND_76[0:0];
  _RAND_77 = {1{`RANDOM}};
  wb_reg_inst = _RAND_77[31:0];
  _RAND_78 = {1{`RANDOM}};
  wb_reg_raw_inst = _RAND_78[31:0];
  _RAND_79 = {1{`RANDOM}};
  wb_reg_wdata = _RAND_79[31:0];
  _RAND_80 = {1{`RANDOM}};
  id_reg_fence = _RAND_80[0:0];
  _RAND_81 = {1{`RANDOM}};
  ex_reg_rs_bypass_0 = _RAND_81[0:0];
  _RAND_82 = {1{`RANDOM}};
  ex_reg_rs_bypass_1 = _RAND_82[0:0];
  _RAND_83 = {1{`RANDOM}};
  ex_reg_rs_lsb_0 = _RAND_83[1:0];
  _RAND_84 = {1{`RANDOM}};
  ex_reg_rs_lsb_1 = _RAND_84[1:0];
  _RAND_85 = {1{`RANDOM}};
  ex_reg_rs_msb_0 = _RAND_85[29:0];
  _RAND_86 = {1{`RANDOM}};
  ex_reg_rs_msb_1 = _RAND_86[29:0];
  _RAND_87 = {1{`RANDOM}};
  _r = _RAND_87[31:0];
  _RAND_88 = {1{`RANDOM}};
  blocked = _RAND_88[0:0];
  _RAND_89 = {1{`RANDOM}};
  div_io_kill_REG = _RAND_89[0:0];
  _RAND_90 = {1{`RANDOM}};
  coreMonitorBundle_rd0val_x23 = _RAND_90[31:0];
  _RAND_91 = {1{`RANDOM}};
  coreMonitorBundle_rd0val_REG = _RAND_91[31:0];
  _RAND_92 = {1{`RANDOM}};
  coreMonitorBundle_rd1val_x29 = _RAND_92[31:0];
  _RAND_93 = {1{`RANDOM}};
  coreMonitorBundle_rd1val_REG = _RAND_93[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module RocketTile(
  input         clock,
  input         reset,
  output        auto_slave_in_a_ready,
  input         auto_slave_in_a_valid,
  input  [2:0]  auto_slave_in_a_bits_opcode,
  input  [2:0]  auto_slave_in_a_bits_param,
  input  [2:0]  auto_slave_in_a_bits_size,
  input  [1:0]  auto_slave_in_a_bits_source,
  input  [27:0] auto_slave_in_a_bits_address,
  input  [3:0]  auto_slave_in_a_bits_mask,
  input  [31:0] auto_slave_in_a_bits_data,
  input         auto_slave_in_a_bits_corrupt,
  input         auto_slave_in_d_ready,
  output        auto_slave_in_d_valid,
  output [2:0]  auto_slave_in_d_bits_opcode,
  output [2:0]  auto_slave_in_d_bits_size,
  output [1:0]  auto_slave_in_d_bits_source,
  output [31:0] auto_slave_in_d_bits_data,
  output        auto_wfi_out_0,
  input         auto_int_local_in_3_0,
  input         auto_int_local_in_2_0,
  input         auto_int_local_in_1_0,
  input         auto_int_local_in_1_1,
  input         auto_int_local_in_0_0,
  input         auto_hartid_in,
  input         auto_tl_other_masters_out_a_ready,
  output        auto_tl_other_masters_out_a_valid,
  output [2:0]  auto_tl_other_masters_out_a_bits_opcode,
  output [2:0]  auto_tl_other_masters_out_a_bits_param,
  output [3:0]  auto_tl_other_masters_out_a_bits_size,
  output [1:0]  auto_tl_other_masters_out_a_bits_source,
  output [30:0] auto_tl_other_masters_out_a_bits_address,
  output [3:0]  auto_tl_other_masters_out_a_bits_mask,
  output [31:0] auto_tl_other_masters_out_a_bits_data,
  output        auto_tl_other_masters_out_b_ready,
  input         auto_tl_other_masters_out_b_valid,
  input  [2:0]  auto_tl_other_masters_out_b_bits_opcode,
  input  [1:0]  auto_tl_other_masters_out_b_bits_param,
  input  [3:0]  auto_tl_other_masters_out_b_bits_size,
  input  [1:0]  auto_tl_other_masters_out_b_bits_source,
  input  [30:0] auto_tl_other_masters_out_b_bits_address,
  input  [3:0]  auto_tl_other_masters_out_b_bits_mask,
  input         auto_tl_other_masters_out_b_bits_corrupt,
  input         auto_tl_other_masters_out_c_ready,
  output        auto_tl_other_masters_out_c_valid,
  output [2:0]  auto_tl_other_masters_out_c_bits_opcode,
  output [2:0]  auto_tl_other_masters_out_c_bits_param,
  output [3:0]  auto_tl_other_masters_out_c_bits_size,
  output [1:0]  auto_tl_other_masters_out_c_bits_source,
  output [30:0] auto_tl_other_masters_out_c_bits_address,
  output [31:0] auto_tl_other_masters_out_c_bits_data,
  output        auto_tl_other_masters_out_d_ready,
  input         auto_tl_other_masters_out_d_valid,
  input  [2:0]  auto_tl_other_masters_out_d_bits_opcode,
  input  [1:0]  auto_tl_other_masters_out_d_bits_param,
  input  [3:0]  auto_tl_other_masters_out_d_bits_size,
  input  [1:0]  auto_tl_other_masters_out_d_bits_source,
  input  [1:0]  auto_tl_other_masters_out_d_bits_sink,
  input         auto_tl_other_masters_out_d_bits_denied,
  input  [31:0] auto_tl_other_masters_out_d_bits_data,
  input         auto_tl_other_masters_out_d_bits_corrupt,
  input         auto_tl_other_masters_out_e_ready,
  output        auto_tl_other_masters_out_e_valid,
  output [1:0]  auto_tl_other_masters_out_e_bits_sink
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  wire  tlMasterXbar_clock; // @[BaseTile.scala 210:42]
  wire  tlMasterXbar_reset; // @[BaseTile.scala 210:42]
  wire  tlMasterXbar_auto_in_1_a_ready; // @[BaseTile.scala 210:42]
  wire  tlMasterXbar_auto_in_1_a_valid; // @[BaseTile.scala 210:42]
  wire [30:0] tlMasterXbar_auto_in_1_a_bits_address; // @[BaseTile.scala 210:42]
  wire  tlMasterXbar_auto_in_1_d_ready; // @[BaseTile.scala 210:42]
  wire  tlMasterXbar_auto_in_1_d_valid; // @[BaseTile.scala 210:42]
  wire [2:0] tlMasterXbar_auto_in_1_d_bits_opcode; // @[BaseTile.scala 210:42]
  wire [3:0] tlMasterXbar_auto_in_1_d_bits_size; // @[BaseTile.scala 210:42]
  wire [31:0] tlMasterXbar_auto_in_1_d_bits_data; // @[BaseTile.scala 210:42]
  wire  tlMasterXbar_auto_in_1_d_bits_corrupt; // @[BaseTile.scala 210:42]
  wire  tlMasterXbar_auto_in_0_a_ready; // @[BaseTile.scala 210:42]
  wire  tlMasterXbar_auto_in_0_a_valid; // @[BaseTile.scala 210:42]
  wire [2:0] tlMasterXbar_auto_in_0_a_bits_opcode; // @[BaseTile.scala 210:42]
  wire [2:0] tlMasterXbar_auto_in_0_a_bits_param; // @[BaseTile.scala 210:42]
  wire [3:0] tlMasterXbar_auto_in_0_a_bits_size; // @[BaseTile.scala 210:42]
  wire  tlMasterXbar_auto_in_0_a_bits_source; // @[BaseTile.scala 210:42]
  wire [30:0] tlMasterXbar_auto_in_0_a_bits_address; // @[BaseTile.scala 210:42]
  wire [3:0] tlMasterXbar_auto_in_0_a_bits_mask; // @[BaseTile.scala 210:42]
  wire [31:0] tlMasterXbar_auto_in_0_a_bits_data; // @[BaseTile.scala 210:42]
  wire  tlMasterXbar_auto_in_0_b_ready; // @[BaseTile.scala 210:42]
  wire  tlMasterXbar_auto_in_0_b_valid; // @[BaseTile.scala 210:42]
  wire [1:0] tlMasterXbar_auto_in_0_b_bits_param; // @[BaseTile.scala 210:42]
  wire [3:0] tlMasterXbar_auto_in_0_b_bits_size; // @[BaseTile.scala 210:42]
  wire  tlMasterXbar_auto_in_0_b_bits_source; // @[BaseTile.scala 210:42]
  wire [30:0] tlMasterXbar_auto_in_0_b_bits_address; // @[BaseTile.scala 210:42]
  wire  tlMasterXbar_auto_in_0_c_ready; // @[BaseTile.scala 210:42]
  wire  tlMasterXbar_auto_in_0_c_valid; // @[BaseTile.scala 210:42]
  wire [2:0] tlMasterXbar_auto_in_0_c_bits_opcode; // @[BaseTile.scala 210:42]
  wire [2:0] tlMasterXbar_auto_in_0_c_bits_param; // @[BaseTile.scala 210:42]
  wire [3:0] tlMasterXbar_auto_in_0_c_bits_size; // @[BaseTile.scala 210:42]
  wire  tlMasterXbar_auto_in_0_c_bits_source; // @[BaseTile.scala 210:42]
  wire [30:0] tlMasterXbar_auto_in_0_c_bits_address; // @[BaseTile.scala 210:42]
  wire [31:0] tlMasterXbar_auto_in_0_c_bits_data; // @[BaseTile.scala 210:42]
  wire  tlMasterXbar_auto_in_0_d_ready; // @[BaseTile.scala 210:42]
  wire  tlMasterXbar_auto_in_0_d_valid; // @[BaseTile.scala 210:42]
  wire [2:0] tlMasterXbar_auto_in_0_d_bits_opcode; // @[BaseTile.scala 210:42]
  wire [1:0] tlMasterXbar_auto_in_0_d_bits_param; // @[BaseTile.scala 210:42]
  wire [3:0] tlMasterXbar_auto_in_0_d_bits_size; // @[BaseTile.scala 210:42]
  wire  tlMasterXbar_auto_in_0_d_bits_source; // @[BaseTile.scala 210:42]
  wire [1:0] tlMasterXbar_auto_in_0_d_bits_sink; // @[BaseTile.scala 210:42]
  wire  tlMasterXbar_auto_in_0_d_bits_denied; // @[BaseTile.scala 210:42]
  wire [31:0] tlMasterXbar_auto_in_0_d_bits_data; // @[BaseTile.scala 210:42]
  wire  tlMasterXbar_auto_in_0_e_ready; // @[BaseTile.scala 210:42]
  wire  tlMasterXbar_auto_in_0_e_valid; // @[BaseTile.scala 210:42]
  wire [1:0] tlMasterXbar_auto_in_0_e_bits_sink; // @[BaseTile.scala 210:42]
  wire  tlMasterXbar_auto_out_a_ready; // @[BaseTile.scala 210:42]
  wire  tlMasterXbar_auto_out_a_valid; // @[BaseTile.scala 210:42]
  wire [2:0] tlMasterXbar_auto_out_a_bits_opcode; // @[BaseTile.scala 210:42]
  wire [2:0] tlMasterXbar_auto_out_a_bits_param; // @[BaseTile.scala 210:42]
  wire [3:0] tlMasterXbar_auto_out_a_bits_size; // @[BaseTile.scala 210:42]
  wire [1:0] tlMasterXbar_auto_out_a_bits_source; // @[BaseTile.scala 210:42]
  wire [30:0] tlMasterXbar_auto_out_a_bits_address; // @[BaseTile.scala 210:42]
  wire [3:0] tlMasterXbar_auto_out_a_bits_mask; // @[BaseTile.scala 210:42]
  wire [31:0] tlMasterXbar_auto_out_a_bits_data; // @[BaseTile.scala 210:42]
  wire  tlMasterXbar_auto_out_b_ready; // @[BaseTile.scala 210:42]
  wire  tlMasterXbar_auto_out_b_valid; // @[BaseTile.scala 210:42]
  wire [2:0] tlMasterXbar_auto_out_b_bits_opcode; // @[BaseTile.scala 210:42]
  wire [1:0] tlMasterXbar_auto_out_b_bits_param; // @[BaseTile.scala 210:42]
  wire [3:0] tlMasterXbar_auto_out_b_bits_size; // @[BaseTile.scala 210:42]
  wire [1:0] tlMasterXbar_auto_out_b_bits_source; // @[BaseTile.scala 210:42]
  wire [30:0] tlMasterXbar_auto_out_b_bits_address; // @[BaseTile.scala 210:42]
  wire [3:0] tlMasterXbar_auto_out_b_bits_mask; // @[BaseTile.scala 210:42]
  wire  tlMasterXbar_auto_out_b_bits_corrupt; // @[BaseTile.scala 210:42]
  wire  tlMasterXbar_auto_out_c_ready; // @[BaseTile.scala 210:42]
  wire  tlMasterXbar_auto_out_c_valid; // @[BaseTile.scala 210:42]
  wire [2:0] tlMasterXbar_auto_out_c_bits_opcode; // @[BaseTile.scala 210:42]
  wire [2:0] tlMasterXbar_auto_out_c_bits_param; // @[BaseTile.scala 210:42]
  wire [3:0] tlMasterXbar_auto_out_c_bits_size; // @[BaseTile.scala 210:42]
  wire [1:0] tlMasterXbar_auto_out_c_bits_source; // @[BaseTile.scala 210:42]
  wire [30:0] tlMasterXbar_auto_out_c_bits_address; // @[BaseTile.scala 210:42]
  wire [31:0] tlMasterXbar_auto_out_c_bits_data; // @[BaseTile.scala 210:42]
  wire  tlMasterXbar_auto_out_d_ready; // @[BaseTile.scala 210:42]
  wire  tlMasterXbar_auto_out_d_valid; // @[BaseTile.scala 210:42]
  wire [2:0] tlMasterXbar_auto_out_d_bits_opcode; // @[BaseTile.scala 210:42]
  wire [1:0] tlMasterXbar_auto_out_d_bits_param; // @[BaseTile.scala 210:42]
  wire [3:0] tlMasterXbar_auto_out_d_bits_size; // @[BaseTile.scala 210:42]
  wire [1:0] tlMasterXbar_auto_out_d_bits_source; // @[BaseTile.scala 210:42]
  wire [1:0] tlMasterXbar_auto_out_d_bits_sink; // @[BaseTile.scala 210:42]
  wire  tlMasterXbar_auto_out_d_bits_denied; // @[BaseTile.scala 210:42]
  wire [31:0] tlMasterXbar_auto_out_d_bits_data; // @[BaseTile.scala 210:42]
  wire  tlMasterXbar_auto_out_d_bits_corrupt; // @[BaseTile.scala 210:42]
  wire  tlMasterXbar_auto_out_e_ready; // @[BaseTile.scala 210:42]
  wire  tlMasterXbar_auto_out_e_valid; // @[BaseTile.scala 210:42]
  wire [1:0] tlMasterXbar_auto_out_e_bits_sink; // @[BaseTile.scala 210:42]
  wire  tlSlaveXbar_auto_in_a_ready; // @[BaseTile.scala 211:41]
  wire  tlSlaveXbar_auto_in_a_valid; // @[BaseTile.scala 211:41]
  wire [2:0] tlSlaveXbar_auto_in_a_bits_opcode; // @[BaseTile.scala 211:41]
  wire [2:0] tlSlaveXbar_auto_in_a_bits_param; // @[BaseTile.scala 211:41]
  wire [2:0] tlSlaveXbar_auto_in_a_bits_size; // @[BaseTile.scala 211:41]
  wire [1:0] tlSlaveXbar_auto_in_a_bits_source; // @[BaseTile.scala 211:41]
  wire [27:0] tlSlaveXbar_auto_in_a_bits_address; // @[BaseTile.scala 211:41]
  wire [3:0] tlSlaveXbar_auto_in_a_bits_mask; // @[BaseTile.scala 211:41]
  wire [31:0] tlSlaveXbar_auto_in_a_bits_data; // @[BaseTile.scala 211:41]
  wire  tlSlaveXbar_auto_in_a_bits_corrupt; // @[BaseTile.scala 211:41]
  wire  tlSlaveXbar_auto_in_d_ready; // @[BaseTile.scala 211:41]
  wire  tlSlaveXbar_auto_in_d_valid; // @[BaseTile.scala 211:41]
  wire [2:0] tlSlaveXbar_auto_in_d_bits_opcode; // @[BaseTile.scala 211:41]
  wire [2:0] tlSlaveXbar_auto_in_d_bits_size; // @[BaseTile.scala 211:41]
  wire [1:0] tlSlaveXbar_auto_in_d_bits_source; // @[BaseTile.scala 211:41]
  wire [31:0] tlSlaveXbar_auto_in_d_bits_data; // @[BaseTile.scala 211:41]
  wire  tlSlaveXbar_auto_out_a_ready; // @[BaseTile.scala 211:41]
  wire  tlSlaveXbar_auto_out_a_valid; // @[BaseTile.scala 211:41]
  wire [2:0] tlSlaveXbar_auto_out_a_bits_opcode; // @[BaseTile.scala 211:41]
  wire [2:0] tlSlaveXbar_auto_out_a_bits_param; // @[BaseTile.scala 211:41]
  wire [2:0] tlSlaveXbar_auto_out_a_bits_size; // @[BaseTile.scala 211:41]
  wire [1:0] tlSlaveXbar_auto_out_a_bits_source; // @[BaseTile.scala 211:41]
  wire [27:0] tlSlaveXbar_auto_out_a_bits_address; // @[BaseTile.scala 211:41]
  wire [3:0] tlSlaveXbar_auto_out_a_bits_mask; // @[BaseTile.scala 211:41]
  wire [31:0] tlSlaveXbar_auto_out_a_bits_data; // @[BaseTile.scala 211:41]
  wire  tlSlaveXbar_auto_out_a_bits_corrupt; // @[BaseTile.scala 211:41]
  wire  tlSlaveXbar_auto_out_d_ready; // @[BaseTile.scala 211:41]
  wire  tlSlaveXbar_auto_out_d_valid; // @[BaseTile.scala 211:41]
  wire [2:0] tlSlaveXbar_auto_out_d_bits_opcode; // @[BaseTile.scala 211:41]
  wire [2:0] tlSlaveXbar_auto_out_d_bits_size; // @[BaseTile.scala 211:41]
  wire [1:0] tlSlaveXbar_auto_out_d_bits_source; // @[BaseTile.scala 211:41]
  wire [31:0] tlSlaveXbar_auto_out_d_bits_data; // @[BaseTile.scala 211:41]
  wire  intXbar_auto_int_in_3_0; // @[BaseTile.scala 212:37]
  wire  intXbar_auto_int_in_2_0; // @[BaseTile.scala 212:37]
  wire  intXbar_auto_int_in_1_0; // @[BaseTile.scala 212:37]
  wire  intXbar_auto_int_in_1_1; // @[BaseTile.scala 212:37]
  wire  intXbar_auto_int_in_0_0; // @[BaseTile.scala 212:37]
  wire  intXbar_auto_int_out_0; // @[BaseTile.scala 212:37]
  wire  intXbar_auto_int_out_1; // @[BaseTile.scala 212:37]
  wire  intXbar_auto_int_out_2; // @[BaseTile.scala 212:37]
  wire  intXbar_auto_int_out_3; // @[BaseTile.scala 212:37]
  wire  intXbar_auto_int_out_4; // @[BaseTile.scala 212:37]
  wire  broadcast_auto_in; // @[BundleBridge.scala 196:31]
  wire  broadcast_auto_out_0; // @[BundleBridge.scala 196:31]
  wire  dcache_clock; // @[HellaCache.scala 269:43]
  wire  dcache_reset; // @[HellaCache.scala 269:43]
  wire  dcache_auto_out_a_ready; // @[HellaCache.scala 269:43]
  wire  dcache_auto_out_a_valid; // @[HellaCache.scala 269:43]
  wire [2:0] dcache_auto_out_a_bits_opcode; // @[HellaCache.scala 269:43]
  wire [2:0] dcache_auto_out_a_bits_param; // @[HellaCache.scala 269:43]
  wire [3:0] dcache_auto_out_a_bits_size; // @[HellaCache.scala 269:43]
  wire  dcache_auto_out_a_bits_source; // @[HellaCache.scala 269:43]
  wire [30:0] dcache_auto_out_a_bits_address; // @[HellaCache.scala 269:43]
  wire [3:0] dcache_auto_out_a_bits_mask; // @[HellaCache.scala 269:43]
  wire [31:0] dcache_auto_out_a_bits_data; // @[HellaCache.scala 269:43]
  wire  dcache_auto_out_b_ready; // @[HellaCache.scala 269:43]
  wire  dcache_auto_out_b_valid; // @[HellaCache.scala 269:43]
  wire [1:0] dcache_auto_out_b_bits_param; // @[HellaCache.scala 269:43]
  wire [3:0] dcache_auto_out_b_bits_size; // @[HellaCache.scala 269:43]
  wire  dcache_auto_out_b_bits_source; // @[HellaCache.scala 269:43]
  wire [30:0] dcache_auto_out_b_bits_address; // @[HellaCache.scala 269:43]
  wire  dcache_auto_out_c_ready; // @[HellaCache.scala 269:43]
  wire  dcache_auto_out_c_valid; // @[HellaCache.scala 269:43]
  wire [2:0] dcache_auto_out_c_bits_opcode; // @[HellaCache.scala 269:43]
  wire [2:0] dcache_auto_out_c_bits_param; // @[HellaCache.scala 269:43]
  wire [3:0] dcache_auto_out_c_bits_size; // @[HellaCache.scala 269:43]
  wire  dcache_auto_out_c_bits_source; // @[HellaCache.scala 269:43]
  wire [30:0] dcache_auto_out_c_bits_address; // @[HellaCache.scala 269:43]
  wire [31:0] dcache_auto_out_c_bits_data; // @[HellaCache.scala 269:43]
  wire  dcache_auto_out_d_ready; // @[HellaCache.scala 269:43]
  wire  dcache_auto_out_d_valid; // @[HellaCache.scala 269:43]
  wire [2:0] dcache_auto_out_d_bits_opcode; // @[HellaCache.scala 269:43]
  wire [1:0] dcache_auto_out_d_bits_param; // @[HellaCache.scala 269:43]
  wire [3:0] dcache_auto_out_d_bits_size; // @[HellaCache.scala 269:43]
  wire  dcache_auto_out_d_bits_source; // @[HellaCache.scala 269:43]
  wire [1:0] dcache_auto_out_d_bits_sink; // @[HellaCache.scala 269:43]
  wire  dcache_auto_out_d_bits_denied; // @[HellaCache.scala 269:43]
  wire [31:0] dcache_auto_out_d_bits_data; // @[HellaCache.scala 269:43]
  wire  dcache_auto_out_e_ready; // @[HellaCache.scala 269:43]
  wire  dcache_auto_out_e_valid; // @[HellaCache.scala 269:43]
  wire [1:0] dcache_auto_out_e_bits_sink; // @[HellaCache.scala 269:43]
  wire  dcache_io_cpu_req_ready; // @[HellaCache.scala 269:43]
  wire  dcache_io_cpu_req_valid; // @[HellaCache.scala 269:43]
  wire [31:0] dcache_io_cpu_req_bits_addr; // @[HellaCache.scala 269:43]
  wire [5:0] dcache_io_cpu_req_bits_tag; // @[HellaCache.scala 269:43]
  wire [4:0] dcache_io_cpu_req_bits_cmd; // @[HellaCache.scala 269:43]
  wire [1:0] dcache_io_cpu_req_bits_size; // @[HellaCache.scala 269:43]
  wire  dcache_io_cpu_req_bits_signed; // @[HellaCache.scala 269:43]
  wire [1:0] dcache_io_cpu_req_bits_dprv; // @[HellaCache.scala 269:43]
  wire  dcache_io_cpu_s1_kill; // @[HellaCache.scala 269:43]
  wire [31:0] dcache_io_cpu_s1_data_data; // @[HellaCache.scala 269:43]
  wire [3:0] dcache_io_cpu_s1_data_mask; // @[HellaCache.scala 269:43]
  wire  dcache_io_cpu_s2_nack; // @[HellaCache.scala 269:43]
  wire  dcache_io_cpu_resp_valid; // @[HellaCache.scala 269:43]
  wire [31:0] dcache_io_cpu_resp_bits_addr; // @[HellaCache.scala 269:43]
  wire [5:0] dcache_io_cpu_resp_bits_tag; // @[HellaCache.scala 269:43]
  wire [4:0] dcache_io_cpu_resp_bits_cmd; // @[HellaCache.scala 269:43]
  wire [1:0] dcache_io_cpu_resp_bits_size; // @[HellaCache.scala 269:43]
  wire  dcache_io_cpu_resp_bits_signed; // @[HellaCache.scala 269:43]
  wire [1:0] dcache_io_cpu_resp_bits_dprv; // @[HellaCache.scala 269:43]
  wire  dcache_io_cpu_resp_bits_dv; // @[HellaCache.scala 269:43]
  wire [31:0] dcache_io_cpu_resp_bits_data; // @[HellaCache.scala 269:43]
  wire [3:0] dcache_io_cpu_resp_bits_mask; // @[HellaCache.scala 269:43]
  wire  dcache_io_cpu_resp_bits_replay; // @[HellaCache.scala 269:43]
  wire  dcache_io_cpu_resp_bits_has_data; // @[HellaCache.scala 269:43]
  wire [31:0] dcache_io_cpu_resp_bits_data_word_bypass; // @[HellaCache.scala 269:43]
  wire [31:0] dcache_io_cpu_resp_bits_data_raw; // @[HellaCache.scala 269:43]
  wire [31:0] dcache_io_cpu_resp_bits_store_data; // @[HellaCache.scala 269:43]
  wire  dcache_io_cpu_replay_next; // @[HellaCache.scala 269:43]
  wire  dcache_io_cpu_s2_xcpt_ma_ld; // @[HellaCache.scala 269:43]
  wire  dcache_io_cpu_s2_xcpt_ma_st; // @[HellaCache.scala 269:43]
  wire  dcache_io_cpu_s2_xcpt_pf_ld; // @[HellaCache.scala 269:43]
  wire  dcache_io_cpu_s2_xcpt_pf_st; // @[HellaCache.scala 269:43]
  wire  dcache_io_cpu_s2_xcpt_gf_ld; // @[HellaCache.scala 269:43]
  wire  dcache_io_cpu_s2_xcpt_gf_st; // @[HellaCache.scala 269:43]
  wire  dcache_io_cpu_s2_xcpt_ae_ld; // @[HellaCache.scala 269:43]
  wire  dcache_io_cpu_s2_xcpt_ae_st; // @[HellaCache.scala 269:43]
  wire  dcache_io_cpu_ordered; // @[HellaCache.scala 269:43]
  wire  dcache_io_cpu_perf_release; // @[HellaCache.scala 269:43]
  wire  dcache_io_cpu_perf_grant; // @[HellaCache.scala 269:43]
  wire  dcache_io_ptw_status_debug; // @[HellaCache.scala 269:43]
  wire  dcache_io_ptw_pmp_0_cfg_l; // @[HellaCache.scala 269:43]
  wire [1:0] dcache_io_ptw_pmp_0_cfg_a; // @[HellaCache.scala 269:43]
  wire  dcache_io_ptw_pmp_0_cfg_x; // @[HellaCache.scala 269:43]
  wire  dcache_io_ptw_pmp_0_cfg_w; // @[HellaCache.scala 269:43]
  wire  dcache_io_ptw_pmp_0_cfg_r; // @[HellaCache.scala 269:43]
  wire [28:0] dcache_io_ptw_pmp_0_addr; // @[HellaCache.scala 269:43]
  wire [30:0] dcache_io_ptw_pmp_0_mask; // @[HellaCache.scala 269:43]
  wire  dcache_io_ptw_pmp_1_cfg_l; // @[HellaCache.scala 269:43]
  wire [1:0] dcache_io_ptw_pmp_1_cfg_a; // @[HellaCache.scala 269:43]
  wire  dcache_io_ptw_pmp_1_cfg_x; // @[HellaCache.scala 269:43]
  wire  dcache_io_ptw_pmp_1_cfg_w; // @[HellaCache.scala 269:43]
  wire  dcache_io_ptw_pmp_1_cfg_r; // @[HellaCache.scala 269:43]
  wire [28:0] dcache_io_ptw_pmp_1_addr; // @[HellaCache.scala 269:43]
  wire [30:0] dcache_io_ptw_pmp_1_mask; // @[HellaCache.scala 269:43]
  wire  dcache_io_ptw_pmp_2_cfg_l; // @[HellaCache.scala 269:43]
  wire [1:0] dcache_io_ptw_pmp_2_cfg_a; // @[HellaCache.scala 269:43]
  wire  dcache_io_ptw_pmp_2_cfg_x; // @[HellaCache.scala 269:43]
  wire  dcache_io_ptw_pmp_2_cfg_w; // @[HellaCache.scala 269:43]
  wire  dcache_io_ptw_pmp_2_cfg_r; // @[HellaCache.scala 269:43]
  wire [28:0] dcache_io_ptw_pmp_2_addr; // @[HellaCache.scala 269:43]
  wire [30:0] dcache_io_ptw_pmp_2_mask; // @[HellaCache.scala 269:43]
  wire  dcache_io_ptw_pmp_3_cfg_l; // @[HellaCache.scala 269:43]
  wire [1:0] dcache_io_ptw_pmp_3_cfg_a; // @[HellaCache.scala 269:43]
  wire  dcache_io_ptw_pmp_3_cfg_x; // @[HellaCache.scala 269:43]
  wire  dcache_io_ptw_pmp_3_cfg_w; // @[HellaCache.scala 269:43]
  wire  dcache_io_ptw_pmp_3_cfg_r; // @[HellaCache.scala 269:43]
  wire [28:0] dcache_io_ptw_pmp_3_addr; // @[HellaCache.scala 269:43]
  wire [30:0] dcache_io_ptw_pmp_3_mask; // @[HellaCache.scala 269:43]
  wire  dcache_io_ptw_pmp_4_cfg_l; // @[HellaCache.scala 269:43]
  wire [1:0] dcache_io_ptw_pmp_4_cfg_a; // @[HellaCache.scala 269:43]
  wire  dcache_io_ptw_pmp_4_cfg_x; // @[HellaCache.scala 269:43]
  wire  dcache_io_ptw_pmp_4_cfg_w; // @[HellaCache.scala 269:43]
  wire  dcache_io_ptw_pmp_4_cfg_r; // @[HellaCache.scala 269:43]
  wire [28:0] dcache_io_ptw_pmp_4_addr; // @[HellaCache.scala 269:43]
  wire [30:0] dcache_io_ptw_pmp_4_mask; // @[HellaCache.scala 269:43]
  wire  dcache_io_ptw_pmp_5_cfg_l; // @[HellaCache.scala 269:43]
  wire [1:0] dcache_io_ptw_pmp_5_cfg_a; // @[HellaCache.scala 269:43]
  wire  dcache_io_ptw_pmp_5_cfg_x; // @[HellaCache.scala 269:43]
  wire  dcache_io_ptw_pmp_5_cfg_w; // @[HellaCache.scala 269:43]
  wire  dcache_io_ptw_pmp_5_cfg_r; // @[HellaCache.scala 269:43]
  wire [28:0] dcache_io_ptw_pmp_5_addr; // @[HellaCache.scala 269:43]
  wire [30:0] dcache_io_ptw_pmp_5_mask; // @[HellaCache.scala 269:43]
  wire  dcache_io_ptw_pmp_6_cfg_l; // @[HellaCache.scala 269:43]
  wire [1:0] dcache_io_ptw_pmp_6_cfg_a; // @[HellaCache.scala 269:43]
  wire  dcache_io_ptw_pmp_6_cfg_x; // @[HellaCache.scala 269:43]
  wire  dcache_io_ptw_pmp_6_cfg_w; // @[HellaCache.scala 269:43]
  wire  dcache_io_ptw_pmp_6_cfg_r; // @[HellaCache.scala 269:43]
  wire [28:0] dcache_io_ptw_pmp_6_addr; // @[HellaCache.scala 269:43]
  wire [30:0] dcache_io_ptw_pmp_6_mask; // @[HellaCache.scala 269:43]
  wire  dcache_io_ptw_pmp_7_cfg_l; // @[HellaCache.scala 269:43]
  wire [1:0] dcache_io_ptw_pmp_7_cfg_a; // @[HellaCache.scala 269:43]
  wire  dcache_io_ptw_pmp_7_cfg_x; // @[HellaCache.scala 269:43]
  wire  dcache_io_ptw_pmp_7_cfg_w; // @[HellaCache.scala 269:43]
  wire  dcache_io_ptw_pmp_7_cfg_r; // @[HellaCache.scala 269:43]
  wire [28:0] dcache_io_ptw_pmp_7_addr; // @[HellaCache.scala 269:43]
  wire [30:0] dcache_io_ptw_pmp_7_mask; // @[HellaCache.scala 269:43]
  wire  frontend_clock; // @[Frontend.scala 371:28]
  wire  frontend_reset; // @[Frontend.scala 371:28]
  wire  frontend_auto_icache_slave_in_a_ready; // @[Frontend.scala 371:28]
  wire  frontend_auto_icache_slave_in_a_valid; // @[Frontend.scala 371:28]
  wire [2:0] frontend_auto_icache_slave_in_a_bits_opcode; // @[Frontend.scala 371:28]
  wire [1:0] frontend_auto_icache_slave_in_a_bits_size; // @[Frontend.scala 371:28]
  wire [7:0] frontend_auto_icache_slave_in_a_bits_source; // @[Frontend.scala 371:28]
  wire [27:0] frontend_auto_icache_slave_in_a_bits_address; // @[Frontend.scala 371:28]
  wire [3:0] frontend_auto_icache_slave_in_a_bits_mask; // @[Frontend.scala 371:28]
  wire [31:0] frontend_auto_icache_slave_in_a_bits_data; // @[Frontend.scala 371:28]
  wire  frontend_auto_icache_slave_in_d_ready; // @[Frontend.scala 371:28]
  wire  frontend_auto_icache_slave_in_d_valid; // @[Frontend.scala 371:28]
  wire [2:0] frontend_auto_icache_slave_in_d_bits_opcode; // @[Frontend.scala 371:28]
  wire [1:0] frontend_auto_icache_slave_in_d_bits_size; // @[Frontend.scala 371:28]
  wire [7:0] frontend_auto_icache_slave_in_d_bits_source; // @[Frontend.scala 371:28]
  wire [31:0] frontend_auto_icache_slave_in_d_bits_data; // @[Frontend.scala 371:28]
  wire  frontend_auto_icache_master_out_a_ready; // @[Frontend.scala 371:28]
  wire  frontend_auto_icache_master_out_a_valid; // @[Frontend.scala 371:28]
  wire [30:0] frontend_auto_icache_master_out_a_bits_address; // @[Frontend.scala 371:28]
  wire  frontend_auto_icache_master_out_d_ready; // @[Frontend.scala 371:28]
  wire  frontend_auto_icache_master_out_d_valid; // @[Frontend.scala 371:28]
  wire [2:0] frontend_auto_icache_master_out_d_bits_opcode; // @[Frontend.scala 371:28]
  wire [3:0] frontend_auto_icache_master_out_d_bits_size; // @[Frontend.scala 371:28]
  wire [31:0] frontend_auto_icache_master_out_d_bits_data; // @[Frontend.scala 371:28]
  wire  frontend_auto_icache_master_out_d_bits_corrupt; // @[Frontend.scala 371:28]
  wire  frontend_io_cpu_might_request; // @[Frontend.scala 371:28]
  wire  frontend_io_cpu_req_valid; // @[Frontend.scala 371:28]
  wire [31:0] frontend_io_cpu_req_bits_pc; // @[Frontend.scala 371:28]
  wire  frontend_io_cpu_req_bits_speculative; // @[Frontend.scala 371:28]
  wire  frontend_io_cpu_resp_ready; // @[Frontend.scala 371:28]
  wire  frontend_io_cpu_resp_valid; // @[Frontend.scala 371:28]
  wire  frontend_io_cpu_resp_bits_btb_taken; // @[Frontend.scala 371:28]
  wire  frontend_io_cpu_resp_bits_btb_bridx; // @[Frontend.scala 371:28]
  wire [4:0] frontend_io_cpu_resp_bits_btb_entry; // @[Frontend.scala 371:28]
  wire [7:0] frontend_io_cpu_resp_bits_btb_bht_history; // @[Frontend.scala 371:28]
  wire [31:0] frontend_io_cpu_resp_bits_pc; // @[Frontend.scala 371:28]
  wire [31:0] frontend_io_cpu_resp_bits_data; // @[Frontend.scala 371:28]
  wire  frontend_io_cpu_resp_bits_xcpt_ae_inst; // @[Frontend.scala 371:28]
  wire  frontend_io_cpu_resp_bits_replay; // @[Frontend.scala 371:28]
  wire  frontend_io_cpu_btb_update_valid; // @[Frontend.scala 371:28]
  wire [4:0] frontend_io_cpu_btb_update_bits_prediction_entry; // @[Frontend.scala 371:28]
  wire [31:0] frontend_io_cpu_btb_update_bits_pc; // @[Frontend.scala 371:28]
  wire  frontend_io_cpu_btb_update_bits_isValid; // @[Frontend.scala 371:28]
  wire [31:0] frontend_io_cpu_btb_update_bits_br_pc; // @[Frontend.scala 371:28]
  wire [1:0] frontend_io_cpu_btb_update_bits_cfiType; // @[Frontend.scala 371:28]
  wire  frontend_io_cpu_bht_update_valid; // @[Frontend.scala 371:28]
  wire [7:0] frontend_io_cpu_bht_update_bits_prediction_history; // @[Frontend.scala 371:28]
  wire [31:0] frontend_io_cpu_bht_update_bits_pc; // @[Frontend.scala 371:28]
  wire  frontend_io_cpu_bht_update_bits_branch; // @[Frontend.scala 371:28]
  wire  frontend_io_cpu_bht_update_bits_taken; // @[Frontend.scala 371:28]
  wire  frontend_io_cpu_bht_update_bits_mispredict; // @[Frontend.scala 371:28]
  wire  frontend_io_cpu_flush_icache; // @[Frontend.scala 371:28]
  wire [31:0] frontend_io_cpu_npc; // @[Frontend.scala 371:28]
  wire  frontend_io_ptw_status_debug; // @[Frontend.scala 371:28]
  wire [1:0] frontend_io_ptw_status_prv; // @[Frontend.scala 371:28]
  wire  frontend_io_ptw_pmp_0_cfg_l; // @[Frontend.scala 371:28]
  wire [1:0] frontend_io_ptw_pmp_0_cfg_a; // @[Frontend.scala 371:28]
  wire  frontend_io_ptw_pmp_0_cfg_x; // @[Frontend.scala 371:28]
  wire  frontend_io_ptw_pmp_0_cfg_w; // @[Frontend.scala 371:28]
  wire  frontend_io_ptw_pmp_0_cfg_r; // @[Frontend.scala 371:28]
  wire [28:0] frontend_io_ptw_pmp_0_addr; // @[Frontend.scala 371:28]
  wire [30:0] frontend_io_ptw_pmp_0_mask; // @[Frontend.scala 371:28]
  wire  frontend_io_ptw_pmp_1_cfg_l; // @[Frontend.scala 371:28]
  wire [1:0] frontend_io_ptw_pmp_1_cfg_a; // @[Frontend.scala 371:28]
  wire  frontend_io_ptw_pmp_1_cfg_x; // @[Frontend.scala 371:28]
  wire  frontend_io_ptw_pmp_1_cfg_w; // @[Frontend.scala 371:28]
  wire  frontend_io_ptw_pmp_1_cfg_r; // @[Frontend.scala 371:28]
  wire [28:0] frontend_io_ptw_pmp_1_addr; // @[Frontend.scala 371:28]
  wire [30:0] frontend_io_ptw_pmp_1_mask; // @[Frontend.scala 371:28]
  wire  frontend_io_ptw_pmp_2_cfg_l; // @[Frontend.scala 371:28]
  wire [1:0] frontend_io_ptw_pmp_2_cfg_a; // @[Frontend.scala 371:28]
  wire  frontend_io_ptw_pmp_2_cfg_x; // @[Frontend.scala 371:28]
  wire  frontend_io_ptw_pmp_2_cfg_w; // @[Frontend.scala 371:28]
  wire  frontend_io_ptw_pmp_2_cfg_r; // @[Frontend.scala 371:28]
  wire [28:0] frontend_io_ptw_pmp_2_addr; // @[Frontend.scala 371:28]
  wire [30:0] frontend_io_ptw_pmp_2_mask; // @[Frontend.scala 371:28]
  wire  frontend_io_ptw_pmp_3_cfg_l; // @[Frontend.scala 371:28]
  wire [1:0] frontend_io_ptw_pmp_3_cfg_a; // @[Frontend.scala 371:28]
  wire  frontend_io_ptw_pmp_3_cfg_x; // @[Frontend.scala 371:28]
  wire  frontend_io_ptw_pmp_3_cfg_w; // @[Frontend.scala 371:28]
  wire  frontend_io_ptw_pmp_3_cfg_r; // @[Frontend.scala 371:28]
  wire [28:0] frontend_io_ptw_pmp_3_addr; // @[Frontend.scala 371:28]
  wire [30:0] frontend_io_ptw_pmp_3_mask; // @[Frontend.scala 371:28]
  wire  frontend_io_ptw_pmp_4_cfg_l; // @[Frontend.scala 371:28]
  wire [1:0] frontend_io_ptw_pmp_4_cfg_a; // @[Frontend.scala 371:28]
  wire  frontend_io_ptw_pmp_4_cfg_x; // @[Frontend.scala 371:28]
  wire  frontend_io_ptw_pmp_4_cfg_w; // @[Frontend.scala 371:28]
  wire  frontend_io_ptw_pmp_4_cfg_r; // @[Frontend.scala 371:28]
  wire [28:0] frontend_io_ptw_pmp_4_addr; // @[Frontend.scala 371:28]
  wire [30:0] frontend_io_ptw_pmp_4_mask; // @[Frontend.scala 371:28]
  wire  frontend_io_ptw_pmp_5_cfg_l; // @[Frontend.scala 371:28]
  wire [1:0] frontend_io_ptw_pmp_5_cfg_a; // @[Frontend.scala 371:28]
  wire  frontend_io_ptw_pmp_5_cfg_x; // @[Frontend.scala 371:28]
  wire  frontend_io_ptw_pmp_5_cfg_w; // @[Frontend.scala 371:28]
  wire  frontend_io_ptw_pmp_5_cfg_r; // @[Frontend.scala 371:28]
  wire [28:0] frontend_io_ptw_pmp_5_addr; // @[Frontend.scala 371:28]
  wire [30:0] frontend_io_ptw_pmp_5_mask; // @[Frontend.scala 371:28]
  wire  frontend_io_ptw_pmp_6_cfg_l; // @[Frontend.scala 371:28]
  wire [1:0] frontend_io_ptw_pmp_6_cfg_a; // @[Frontend.scala 371:28]
  wire  frontend_io_ptw_pmp_6_cfg_x; // @[Frontend.scala 371:28]
  wire  frontend_io_ptw_pmp_6_cfg_w; // @[Frontend.scala 371:28]
  wire  frontend_io_ptw_pmp_6_cfg_r; // @[Frontend.scala 371:28]
  wire [28:0] frontend_io_ptw_pmp_6_addr; // @[Frontend.scala 371:28]
  wire [30:0] frontend_io_ptw_pmp_6_mask; // @[Frontend.scala 371:28]
  wire  frontend_io_ptw_pmp_7_cfg_l; // @[Frontend.scala 371:28]
  wire [1:0] frontend_io_ptw_pmp_7_cfg_a; // @[Frontend.scala 371:28]
  wire  frontend_io_ptw_pmp_7_cfg_x; // @[Frontend.scala 371:28]
  wire  frontend_io_ptw_pmp_7_cfg_w; // @[Frontend.scala 371:28]
  wire  frontend_io_ptw_pmp_7_cfg_r; // @[Frontend.scala 371:28]
  wire [28:0] frontend_io_ptw_pmp_7_addr; // @[Frontend.scala 371:28]
  wire [30:0] frontend_io_ptw_pmp_7_mask; // @[Frontend.scala 371:28]
  wire [31:0] frontend_io_ptw_customCSRs_csrs_0_value; // @[Frontend.scala 371:28]
  wire  fragmenter_clock; // @[Fragmenter.scala 333:34]
  wire  fragmenter_reset; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [27:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_in_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_a_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 333:34]
  wire [7:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 333:34]
  wire [27:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 333:34]
  wire [3:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_ready; // @[Fragmenter.scala 333:34]
  wire  fragmenter_auto_out_d_valid; // @[Fragmenter.scala 333:34]
  wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 333:34]
  wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 333:34]
  wire [7:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 333:34]
  wire [31:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 333:34]
  wire  dcacheArb_io_requestor_0_req_ready; // @[HellaCache.scala 280:25]
  wire  dcacheArb_io_requestor_0_req_valid; // @[HellaCache.scala 280:25]
  wire [31:0] dcacheArb_io_requestor_0_req_bits_addr; // @[HellaCache.scala 280:25]
  wire [5:0] dcacheArb_io_requestor_0_req_bits_tag; // @[HellaCache.scala 280:25]
  wire [4:0] dcacheArb_io_requestor_0_req_bits_cmd; // @[HellaCache.scala 280:25]
  wire [1:0] dcacheArb_io_requestor_0_req_bits_size; // @[HellaCache.scala 280:25]
  wire  dcacheArb_io_requestor_0_req_bits_signed; // @[HellaCache.scala 280:25]
  wire [1:0] dcacheArb_io_requestor_0_req_bits_dprv; // @[HellaCache.scala 280:25]
  wire  dcacheArb_io_requestor_0_s1_kill; // @[HellaCache.scala 280:25]
  wire [31:0] dcacheArb_io_requestor_0_s1_data_data; // @[HellaCache.scala 280:25]
  wire  dcacheArb_io_requestor_0_s2_nack; // @[HellaCache.scala 280:25]
  wire  dcacheArb_io_requestor_0_resp_valid; // @[HellaCache.scala 280:25]
  wire [5:0] dcacheArb_io_requestor_0_resp_bits_tag; // @[HellaCache.scala 280:25]
  wire [31:0] dcacheArb_io_requestor_0_resp_bits_data; // @[HellaCache.scala 280:25]
  wire  dcacheArb_io_requestor_0_resp_bits_replay; // @[HellaCache.scala 280:25]
  wire  dcacheArb_io_requestor_0_resp_bits_has_data; // @[HellaCache.scala 280:25]
  wire [31:0] dcacheArb_io_requestor_0_resp_bits_data_word_bypass; // @[HellaCache.scala 280:25]
  wire  dcacheArb_io_requestor_0_replay_next; // @[HellaCache.scala 280:25]
  wire  dcacheArb_io_requestor_0_s2_xcpt_ma_ld; // @[HellaCache.scala 280:25]
  wire  dcacheArb_io_requestor_0_s2_xcpt_ma_st; // @[HellaCache.scala 280:25]
  wire  dcacheArb_io_requestor_0_s2_xcpt_pf_ld; // @[HellaCache.scala 280:25]
  wire  dcacheArb_io_requestor_0_s2_xcpt_pf_st; // @[HellaCache.scala 280:25]
  wire  dcacheArb_io_requestor_0_s2_xcpt_ae_ld; // @[HellaCache.scala 280:25]
  wire  dcacheArb_io_requestor_0_s2_xcpt_ae_st; // @[HellaCache.scala 280:25]
  wire  dcacheArb_io_requestor_0_ordered; // @[HellaCache.scala 280:25]
  wire  dcacheArb_io_requestor_0_perf_release; // @[HellaCache.scala 280:25]
  wire  dcacheArb_io_requestor_0_perf_grant; // @[HellaCache.scala 280:25]
  wire  dcacheArb_io_mem_req_ready; // @[HellaCache.scala 280:25]
  wire  dcacheArb_io_mem_req_valid; // @[HellaCache.scala 280:25]
  wire [31:0] dcacheArb_io_mem_req_bits_addr; // @[HellaCache.scala 280:25]
  wire [5:0] dcacheArb_io_mem_req_bits_tag; // @[HellaCache.scala 280:25]
  wire [4:0] dcacheArb_io_mem_req_bits_cmd; // @[HellaCache.scala 280:25]
  wire [1:0] dcacheArb_io_mem_req_bits_size; // @[HellaCache.scala 280:25]
  wire  dcacheArb_io_mem_req_bits_signed; // @[HellaCache.scala 280:25]
  wire [1:0] dcacheArb_io_mem_req_bits_dprv; // @[HellaCache.scala 280:25]
  wire  dcacheArb_io_mem_s1_kill; // @[HellaCache.scala 280:25]
  wire [31:0] dcacheArb_io_mem_s1_data_data; // @[HellaCache.scala 280:25]
  wire  dcacheArb_io_mem_s2_nack; // @[HellaCache.scala 280:25]
  wire  dcacheArb_io_mem_resp_valid; // @[HellaCache.scala 280:25]
  wire [5:0] dcacheArb_io_mem_resp_bits_tag; // @[HellaCache.scala 280:25]
  wire [31:0] dcacheArb_io_mem_resp_bits_data; // @[HellaCache.scala 280:25]
  wire  dcacheArb_io_mem_resp_bits_replay; // @[HellaCache.scala 280:25]
  wire  dcacheArb_io_mem_resp_bits_has_data; // @[HellaCache.scala 280:25]
  wire [31:0] dcacheArb_io_mem_resp_bits_data_word_bypass; // @[HellaCache.scala 280:25]
  wire  dcacheArb_io_mem_replay_next; // @[HellaCache.scala 280:25]
  wire  dcacheArb_io_mem_s2_xcpt_ma_ld; // @[HellaCache.scala 280:25]
  wire  dcacheArb_io_mem_s2_xcpt_ma_st; // @[HellaCache.scala 280:25]
  wire  dcacheArb_io_mem_s2_xcpt_pf_ld; // @[HellaCache.scala 280:25]
  wire  dcacheArb_io_mem_s2_xcpt_pf_st; // @[HellaCache.scala 280:25]
  wire  dcacheArb_io_mem_s2_xcpt_ae_ld; // @[HellaCache.scala 280:25]
  wire  dcacheArb_io_mem_s2_xcpt_ae_st; // @[HellaCache.scala 280:25]
  wire  dcacheArb_io_mem_ordered; // @[HellaCache.scala 280:25]
  wire  dcacheArb_io_mem_perf_release; // @[HellaCache.scala 280:25]
  wire  dcacheArb_io_mem_perf_grant; // @[HellaCache.scala 280:25]
  wire  ptw_clock; // @[PTW.scala 604:19]
  wire  ptw_reset; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_0_status_debug; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_0_pmp_0_cfg_l; // @[PTW.scala 604:19]
  wire [1:0] ptw_io_requestor_0_pmp_0_cfg_a; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_0_pmp_0_cfg_x; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_0_pmp_0_cfg_w; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_0_pmp_0_cfg_r; // @[PTW.scala 604:19]
  wire [28:0] ptw_io_requestor_0_pmp_0_addr; // @[PTW.scala 604:19]
  wire [30:0] ptw_io_requestor_0_pmp_0_mask; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_0_pmp_1_cfg_l; // @[PTW.scala 604:19]
  wire [1:0] ptw_io_requestor_0_pmp_1_cfg_a; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_0_pmp_1_cfg_x; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_0_pmp_1_cfg_w; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_0_pmp_1_cfg_r; // @[PTW.scala 604:19]
  wire [28:0] ptw_io_requestor_0_pmp_1_addr; // @[PTW.scala 604:19]
  wire [30:0] ptw_io_requestor_0_pmp_1_mask; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_0_pmp_2_cfg_l; // @[PTW.scala 604:19]
  wire [1:0] ptw_io_requestor_0_pmp_2_cfg_a; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_0_pmp_2_cfg_x; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_0_pmp_2_cfg_w; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_0_pmp_2_cfg_r; // @[PTW.scala 604:19]
  wire [28:0] ptw_io_requestor_0_pmp_2_addr; // @[PTW.scala 604:19]
  wire [30:0] ptw_io_requestor_0_pmp_2_mask; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_0_pmp_3_cfg_l; // @[PTW.scala 604:19]
  wire [1:0] ptw_io_requestor_0_pmp_3_cfg_a; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_0_pmp_3_cfg_x; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_0_pmp_3_cfg_w; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_0_pmp_3_cfg_r; // @[PTW.scala 604:19]
  wire [28:0] ptw_io_requestor_0_pmp_3_addr; // @[PTW.scala 604:19]
  wire [30:0] ptw_io_requestor_0_pmp_3_mask; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_0_pmp_4_cfg_l; // @[PTW.scala 604:19]
  wire [1:0] ptw_io_requestor_0_pmp_4_cfg_a; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_0_pmp_4_cfg_x; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_0_pmp_4_cfg_w; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_0_pmp_4_cfg_r; // @[PTW.scala 604:19]
  wire [28:0] ptw_io_requestor_0_pmp_4_addr; // @[PTW.scala 604:19]
  wire [30:0] ptw_io_requestor_0_pmp_4_mask; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_0_pmp_5_cfg_l; // @[PTW.scala 604:19]
  wire [1:0] ptw_io_requestor_0_pmp_5_cfg_a; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_0_pmp_5_cfg_x; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_0_pmp_5_cfg_w; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_0_pmp_5_cfg_r; // @[PTW.scala 604:19]
  wire [28:0] ptw_io_requestor_0_pmp_5_addr; // @[PTW.scala 604:19]
  wire [30:0] ptw_io_requestor_0_pmp_5_mask; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_0_pmp_6_cfg_l; // @[PTW.scala 604:19]
  wire [1:0] ptw_io_requestor_0_pmp_6_cfg_a; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_0_pmp_6_cfg_x; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_0_pmp_6_cfg_w; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_0_pmp_6_cfg_r; // @[PTW.scala 604:19]
  wire [28:0] ptw_io_requestor_0_pmp_6_addr; // @[PTW.scala 604:19]
  wire [30:0] ptw_io_requestor_0_pmp_6_mask; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_0_pmp_7_cfg_l; // @[PTW.scala 604:19]
  wire [1:0] ptw_io_requestor_0_pmp_7_cfg_a; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_0_pmp_7_cfg_x; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_0_pmp_7_cfg_w; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_0_pmp_7_cfg_r; // @[PTW.scala 604:19]
  wire [28:0] ptw_io_requestor_0_pmp_7_addr; // @[PTW.scala 604:19]
  wire [30:0] ptw_io_requestor_0_pmp_7_mask; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_1_status_debug; // @[PTW.scala 604:19]
  wire [1:0] ptw_io_requestor_1_status_prv; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_1_pmp_0_cfg_l; // @[PTW.scala 604:19]
  wire [1:0] ptw_io_requestor_1_pmp_0_cfg_a; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_1_pmp_0_cfg_x; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_1_pmp_0_cfg_w; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_1_pmp_0_cfg_r; // @[PTW.scala 604:19]
  wire [28:0] ptw_io_requestor_1_pmp_0_addr; // @[PTW.scala 604:19]
  wire [30:0] ptw_io_requestor_1_pmp_0_mask; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_1_pmp_1_cfg_l; // @[PTW.scala 604:19]
  wire [1:0] ptw_io_requestor_1_pmp_1_cfg_a; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_1_pmp_1_cfg_x; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_1_pmp_1_cfg_w; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_1_pmp_1_cfg_r; // @[PTW.scala 604:19]
  wire [28:0] ptw_io_requestor_1_pmp_1_addr; // @[PTW.scala 604:19]
  wire [30:0] ptw_io_requestor_1_pmp_1_mask; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_1_pmp_2_cfg_l; // @[PTW.scala 604:19]
  wire [1:0] ptw_io_requestor_1_pmp_2_cfg_a; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_1_pmp_2_cfg_x; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_1_pmp_2_cfg_w; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_1_pmp_2_cfg_r; // @[PTW.scala 604:19]
  wire [28:0] ptw_io_requestor_1_pmp_2_addr; // @[PTW.scala 604:19]
  wire [30:0] ptw_io_requestor_1_pmp_2_mask; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_1_pmp_3_cfg_l; // @[PTW.scala 604:19]
  wire [1:0] ptw_io_requestor_1_pmp_3_cfg_a; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_1_pmp_3_cfg_x; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_1_pmp_3_cfg_w; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_1_pmp_3_cfg_r; // @[PTW.scala 604:19]
  wire [28:0] ptw_io_requestor_1_pmp_3_addr; // @[PTW.scala 604:19]
  wire [30:0] ptw_io_requestor_1_pmp_3_mask; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_1_pmp_4_cfg_l; // @[PTW.scala 604:19]
  wire [1:0] ptw_io_requestor_1_pmp_4_cfg_a; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_1_pmp_4_cfg_x; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_1_pmp_4_cfg_w; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_1_pmp_4_cfg_r; // @[PTW.scala 604:19]
  wire [28:0] ptw_io_requestor_1_pmp_4_addr; // @[PTW.scala 604:19]
  wire [30:0] ptw_io_requestor_1_pmp_4_mask; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_1_pmp_5_cfg_l; // @[PTW.scala 604:19]
  wire [1:0] ptw_io_requestor_1_pmp_5_cfg_a; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_1_pmp_5_cfg_x; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_1_pmp_5_cfg_w; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_1_pmp_5_cfg_r; // @[PTW.scala 604:19]
  wire [28:0] ptw_io_requestor_1_pmp_5_addr; // @[PTW.scala 604:19]
  wire [30:0] ptw_io_requestor_1_pmp_5_mask; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_1_pmp_6_cfg_l; // @[PTW.scala 604:19]
  wire [1:0] ptw_io_requestor_1_pmp_6_cfg_a; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_1_pmp_6_cfg_x; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_1_pmp_6_cfg_w; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_1_pmp_6_cfg_r; // @[PTW.scala 604:19]
  wire [28:0] ptw_io_requestor_1_pmp_6_addr; // @[PTW.scala 604:19]
  wire [30:0] ptw_io_requestor_1_pmp_6_mask; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_1_pmp_7_cfg_l; // @[PTW.scala 604:19]
  wire [1:0] ptw_io_requestor_1_pmp_7_cfg_a; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_1_pmp_7_cfg_x; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_1_pmp_7_cfg_w; // @[PTW.scala 604:19]
  wire  ptw_io_requestor_1_pmp_7_cfg_r; // @[PTW.scala 604:19]
  wire [28:0] ptw_io_requestor_1_pmp_7_addr; // @[PTW.scala 604:19]
  wire [30:0] ptw_io_requestor_1_pmp_7_mask; // @[PTW.scala 604:19]
  wire [31:0] ptw_io_requestor_1_customCSRs_csrs_0_value; // @[PTW.scala 604:19]
  wire  ptw_io_dpath_status_debug; // @[PTW.scala 604:19]
  wire [1:0] ptw_io_dpath_status_prv; // @[PTW.scala 604:19]
  wire  ptw_io_dpath_pmp_0_cfg_l; // @[PTW.scala 604:19]
  wire [1:0] ptw_io_dpath_pmp_0_cfg_a; // @[PTW.scala 604:19]
  wire  ptw_io_dpath_pmp_0_cfg_x; // @[PTW.scala 604:19]
  wire  ptw_io_dpath_pmp_0_cfg_w; // @[PTW.scala 604:19]
  wire  ptw_io_dpath_pmp_0_cfg_r; // @[PTW.scala 604:19]
  wire [28:0] ptw_io_dpath_pmp_0_addr; // @[PTW.scala 604:19]
  wire [30:0] ptw_io_dpath_pmp_0_mask; // @[PTW.scala 604:19]
  wire  ptw_io_dpath_pmp_1_cfg_l; // @[PTW.scala 604:19]
  wire [1:0] ptw_io_dpath_pmp_1_cfg_a; // @[PTW.scala 604:19]
  wire  ptw_io_dpath_pmp_1_cfg_x; // @[PTW.scala 604:19]
  wire  ptw_io_dpath_pmp_1_cfg_w; // @[PTW.scala 604:19]
  wire  ptw_io_dpath_pmp_1_cfg_r; // @[PTW.scala 604:19]
  wire [28:0] ptw_io_dpath_pmp_1_addr; // @[PTW.scala 604:19]
  wire [30:0] ptw_io_dpath_pmp_1_mask; // @[PTW.scala 604:19]
  wire  ptw_io_dpath_pmp_2_cfg_l; // @[PTW.scala 604:19]
  wire [1:0] ptw_io_dpath_pmp_2_cfg_a; // @[PTW.scala 604:19]
  wire  ptw_io_dpath_pmp_2_cfg_x; // @[PTW.scala 604:19]
  wire  ptw_io_dpath_pmp_2_cfg_w; // @[PTW.scala 604:19]
  wire  ptw_io_dpath_pmp_2_cfg_r; // @[PTW.scala 604:19]
  wire [28:0] ptw_io_dpath_pmp_2_addr; // @[PTW.scala 604:19]
  wire [30:0] ptw_io_dpath_pmp_2_mask; // @[PTW.scala 604:19]
  wire  ptw_io_dpath_pmp_3_cfg_l; // @[PTW.scala 604:19]
  wire [1:0] ptw_io_dpath_pmp_3_cfg_a; // @[PTW.scala 604:19]
  wire  ptw_io_dpath_pmp_3_cfg_x; // @[PTW.scala 604:19]
  wire  ptw_io_dpath_pmp_3_cfg_w; // @[PTW.scala 604:19]
  wire  ptw_io_dpath_pmp_3_cfg_r; // @[PTW.scala 604:19]
  wire [28:0] ptw_io_dpath_pmp_3_addr; // @[PTW.scala 604:19]
  wire [30:0] ptw_io_dpath_pmp_3_mask; // @[PTW.scala 604:19]
  wire  ptw_io_dpath_pmp_4_cfg_l; // @[PTW.scala 604:19]
  wire [1:0] ptw_io_dpath_pmp_4_cfg_a; // @[PTW.scala 604:19]
  wire  ptw_io_dpath_pmp_4_cfg_x; // @[PTW.scala 604:19]
  wire  ptw_io_dpath_pmp_4_cfg_w; // @[PTW.scala 604:19]
  wire  ptw_io_dpath_pmp_4_cfg_r; // @[PTW.scala 604:19]
  wire [28:0] ptw_io_dpath_pmp_4_addr; // @[PTW.scala 604:19]
  wire [30:0] ptw_io_dpath_pmp_4_mask; // @[PTW.scala 604:19]
  wire  ptw_io_dpath_pmp_5_cfg_l; // @[PTW.scala 604:19]
  wire [1:0] ptw_io_dpath_pmp_5_cfg_a; // @[PTW.scala 604:19]
  wire  ptw_io_dpath_pmp_5_cfg_x; // @[PTW.scala 604:19]
  wire  ptw_io_dpath_pmp_5_cfg_w; // @[PTW.scala 604:19]
  wire  ptw_io_dpath_pmp_5_cfg_r; // @[PTW.scala 604:19]
  wire [28:0] ptw_io_dpath_pmp_5_addr; // @[PTW.scala 604:19]
  wire [30:0] ptw_io_dpath_pmp_5_mask; // @[PTW.scala 604:19]
  wire  ptw_io_dpath_pmp_6_cfg_l; // @[PTW.scala 604:19]
  wire [1:0] ptw_io_dpath_pmp_6_cfg_a; // @[PTW.scala 604:19]
  wire  ptw_io_dpath_pmp_6_cfg_x; // @[PTW.scala 604:19]
  wire  ptw_io_dpath_pmp_6_cfg_w; // @[PTW.scala 604:19]
  wire  ptw_io_dpath_pmp_6_cfg_r; // @[PTW.scala 604:19]
  wire [28:0] ptw_io_dpath_pmp_6_addr; // @[PTW.scala 604:19]
  wire [30:0] ptw_io_dpath_pmp_6_mask; // @[PTW.scala 604:19]
  wire  ptw_io_dpath_pmp_7_cfg_l; // @[PTW.scala 604:19]
  wire [1:0] ptw_io_dpath_pmp_7_cfg_a; // @[PTW.scala 604:19]
  wire  ptw_io_dpath_pmp_7_cfg_x; // @[PTW.scala 604:19]
  wire  ptw_io_dpath_pmp_7_cfg_w; // @[PTW.scala 604:19]
  wire  ptw_io_dpath_pmp_7_cfg_r; // @[PTW.scala 604:19]
  wire [28:0] ptw_io_dpath_pmp_7_addr; // @[PTW.scala 604:19]
  wire [30:0] ptw_io_dpath_pmp_7_mask; // @[PTW.scala 604:19]
  wire  ptw_io_dpath_perf_l2hit; // @[PTW.scala 604:19]
  wire  ptw_io_dpath_perf_pte_miss; // @[PTW.scala 604:19]
  wire  ptw_io_dpath_perf_pte_hit; // @[PTW.scala 604:19]
  wire [31:0] ptw_io_dpath_customCSRs_csrs_0_value; // @[PTW.scala 604:19]
  wire  core_clock; // @[RocketTile.scala 140:20]
  wire  core_reset; // @[RocketTile.scala 140:20]
  wire  core_io_hartid; // @[RocketTile.scala 140:20]
  wire  core_io_interrupts_debug; // @[RocketTile.scala 140:20]
  wire  core_io_interrupts_mtip; // @[RocketTile.scala 140:20]
  wire  core_io_interrupts_msip; // @[RocketTile.scala 140:20]
  wire  core_io_interrupts_meip; // @[RocketTile.scala 140:20]
  wire  core_io_interrupts_seip; // @[RocketTile.scala 140:20]
  wire  core_io_imem_might_request; // @[RocketTile.scala 140:20]
  wire  core_io_imem_req_valid; // @[RocketTile.scala 140:20]
  wire [31:0] core_io_imem_req_bits_pc; // @[RocketTile.scala 140:20]
  wire  core_io_imem_req_bits_speculative; // @[RocketTile.scala 140:20]
  wire  core_io_imem_resp_ready; // @[RocketTile.scala 140:20]
  wire  core_io_imem_resp_valid; // @[RocketTile.scala 140:20]
  wire  core_io_imem_resp_bits_btb_taken; // @[RocketTile.scala 140:20]
  wire  core_io_imem_resp_bits_btb_bridx; // @[RocketTile.scala 140:20]
  wire [4:0] core_io_imem_resp_bits_btb_entry; // @[RocketTile.scala 140:20]
  wire [7:0] core_io_imem_resp_bits_btb_bht_history; // @[RocketTile.scala 140:20]
  wire [31:0] core_io_imem_resp_bits_pc; // @[RocketTile.scala 140:20]
  wire [31:0] core_io_imem_resp_bits_data; // @[RocketTile.scala 140:20]
  wire  core_io_imem_resp_bits_xcpt_ae_inst; // @[RocketTile.scala 140:20]
  wire  core_io_imem_resp_bits_replay; // @[RocketTile.scala 140:20]
  wire  core_io_imem_btb_update_valid; // @[RocketTile.scala 140:20]
  wire [4:0] core_io_imem_btb_update_bits_prediction_entry; // @[RocketTile.scala 140:20]
  wire [31:0] core_io_imem_btb_update_bits_pc; // @[RocketTile.scala 140:20]
  wire  core_io_imem_btb_update_bits_isValid; // @[RocketTile.scala 140:20]
  wire [31:0] core_io_imem_btb_update_bits_br_pc; // @[RocketTile.scala 140:20]
  wire [1:0] core_io_imem_btb_update_bits_cfiType; // @[RocketTile.scala 140:20]
  wire  core_io_imem_bht_update_valid; // @[RocketTile.scala 140:20]
  wire [7:0] core_io_imem_bht_update_bits_prediction_history; // @[RocketTile.scala 140:20]
  wire [31:0] core_io_imem_bht_update_bits_pc; // @[RocketTile.scala 140:20]
  wire  core_io_imem_bht_update_bits_branch; // @[RocketTile.scala 140:20]
  wire  core_io_imem_bht_update_bits_taken; // @[RocketTile.scala 140:20]
  wire  core_io_imem_bht_update_bits_mispredict; // @[RocketTile.scala 140:20]
  wire  core_io_imem_flush_icache; // @[RocketTile.scala 140:20]
  wire  core_io_dmem_req_ready; // @[RocketTile.scala 140:20]
  wire  core_io_dmem_req_valid; // @[RocketTile.scala 140:20]
  wire [31:0] core_io_dmem_req_bits_addr; // @[RocketTile.scala 140:20]
  wire [5:0] core_io_dmem_req_bits_tag; // @[RocketTile.scala 140:20]
  wire [4:0] core_io_dmem_req_bits_cmd; // @[RocketTile.scala 140:20]
  wire [1:0] core_io_dmem_req_bits_size; // @[RocketTile.scala 140:20]
  wire  core_io_dmem_req_bits_signed; // @[RocketTile.scala 140:20]
  wire [1:0] core_io_dmem_req_bits_dprv; // @[RocketTile.scala 140:20]
  wire  core_io_dmem_req_bits_dv; // @[RocketTile.scala 140:20]
  wire  core_io_dmem_s1_kill; // @[RocketTile.scala 140:20]
  wire [31:0] core_io_dmem_s1_data_data; // @[RocketTile.scala 140:20]
  wire  core_io_dmem_s2_nack; // @[RocketTile.scala 140:20]
  wire  core_io_dmem_resp_valid; // @[RocketTile.scala 140:20]
  wire [5:0] core_io_dmem_resp_bits_tag; // @[RocketTile.scala 140:20]
  wire [31:0] core_io_dmem_resp_bits_data; // @[RocketTile.scala 140:20]
  wire  core_io_dmem_resp_bits_replay; // @[RocketTile.scala 140:20]
  wire  core_io_dmem_resp_bits_has_data; // @[RocketTile.scala 140:20]
  wire [31:0] core_io_dmem_resp_bits_data_word_bypass; // @[RocketTile.scala 140:20]
  wire  core_io_dmem_replay_next; // @[RocketTile.scala 140:20]
  wire  core_io_dmem_s2_xcpt_ma_ld; // @[RocketTile.scala 140:20]
  wire  core_io_dmem_s2_xcpt_ma_st; // @[RocketTile.scala 140:20]
  wire  core_io_dmem_s2_xcpt_pf_ld; // @[RocketTile.scala 140:20]
  wire  core_io_dmem_s2_xcpt_pf_st; // @[RocketTile.scala 140:20]
  wire  core_io_dmem_s2_xcpt_ae_ld; // @[RocketTile.scala 140:20]
  wire  core_io_dmem_s2_xcpt_ae_st; // @[RocketTile.scala 140:20]
  wire  core_io_dmem_ordered; // @[RocketTile.scala 140:20]
  wire  core_io_dmem_perf_release; // @[RocketTile.scala 140:20]
  wire  core_io_dmem_perf_grant; // @[RocketTile.scala 140:20]
  wire  core_io_ptw_status_debug; // @[RocketTile.scala 140:20]
  wire [1:0] core_io_ptw_status_prv; // @[RocketTile.scala 140:20]
  wire  core_io_ptw_pmp_0_cfg_l; // @[RocketTile.scala 140:20]
  wire [1:0] core_io_ptw_pmp_0_cfg_a; // @[RocketTile.scala 140:20]
  wire  core_io_ptw_pmp_0_cfg_x; // @[RocketTile.scala 140:20]
  wire  core_io_ptw_pmp_0_cfg_w; // @[RocketTile.scala 140:20]
  wire  core_io_ptw_pmp_0_cfg_r; // @[RocketTile.scala 140:20]
  wire [28:0] core_io_ptw_pmp_0_addr; // @[RocketTile.scala 140:20]
  wire [30:0] core_io_ptw_pmp_0_mask; // @[RocketTile.scala 140:20]
  wire  core_io_ptw_pmp_1_cfg_l; // @[RocketTile.scala 140:20]
  wire [1:0] core_io_ptw_pmp_1_cfg_a; // @[RocketTile.scala 140:20]
  wire  core_io_ptw_pmp_1_cfg_x; // @[RocketTile.scala 140:20]
  wire  core_io_ptw_pmp_1_cfg_w; // @[RocketTile.scala 140:20]
  wire  core_io_ptw_pmp_1_cfg_r; // @[RocketTile.scala 140:20]
  wire [28:0] core_io_ptw_pmp_1_addr; // @[RocketTile.scala 140:20]
  wire [30:0] core_io_ptw_pmp_1_mask; // @[RocketTile.scala 140:20]
  wire  core_io_ptw_pmp_2_cfg_l; // @[RocketTile.scala 140:20]
  wire [1:0] core_io_ptw_pmp_2_cfg_a; // @[RocketTile.scala 140:20]
  wire  core_io_ptw_pmp_2_cfg_x; // @[RocketTile.scala 140:20]
  wire  core_io_ptw_pmp_2_cfg_w; // @[RocketTile.scala 140:20]
  wire  core_io_ptw_pmp_2_cfg_r; // @[RocketTile.scala 140:20]
  wire [28:0] core_io_ptw_pmp_2_addr; // @[RocketTile.scala 140:20]
  wire [30:0] core_io_ptw_pmp_2_mask; // @[RocketTile.scala 140:20]
  wire  core_io_ptw_pmp_3_cfg_l; // @[RocketTile.scala 140:20]
  wire [1:0] core_io_ptw_pmp_3_cfg_a; // @[RocketTile.scala 140:20]
  wire  core_io_ptw_pmp_3_cfg_x; // @[RocketTile.scala 140:20]
  wire  core_io_ptw_pmp_3_cfg_w; // @[RocketTile.scala 140:20]
  wire  core_io_ptw_pmp_3_cfg_r; // @[RocketTile.scala 140:20]
  wire [28:0] core_io_ptw_pmp_3_addr; // @[RocketTile.scala 140:20]
  wire [30:0] core_io_ptw_pmp_3_mask; // @[RocketTile.scala 140:20]
  wire  core_io_ptw_pmp_4_cfg_l; // @[RocketTile.scala 140:20]
  wire [1:0] core_io_ptw_pmp_4_cfg_a; // @[RocketTile.scala 140:20]
  wire  core_io_ptw_pmp_4_cfg_x; // @[RocketTile.scala 140:20]
  wire  core_io_ptw_pmp_4_cfg_w; // @[RocketTile.scala 140:20]
  wire  core_io_ptw_pmp_4_cfg_r; // @[RocketTile.scala 140:20]
  wire [28:0] core_io_ptw_pmp_4_addr; // @[RocketTile.scala 140:20]
  wire [30:0] core_io_ptw_pmp_4_mask; // @[RocketTile.scala 140:20]
  wire  core_io_ptw_pmp_5_cfg_l; // @[RocketTile.scala 140:20]
  wire [1:0] core_io_ptw_pmp_5_cfg_a; // @[RocketTile.scala 140:20]
  wire  core_io_ptw_pmp_5_cfg_x; // @[RocketTile.scala 140:20]
  wire  core_io_ptw_pmp_5_cfg_w; // @[RocketTile.scala 140:20]
  wire  core_io_ptw_pmp_5_cfg_r; // @[RocketTile.scala 140:20]
  wire [28:0] core_io_ptw_pmp_5_addr; // @[RocketTile.scala 140:20]
  wire [30:0] core_io_ptw_pmp_5_mask; // @[RocketTile.scala 140:20]
  wire  core_io_ptw_pmp_6_cfg_l; // @[RocketTile.scala 140:20]
  wire [1:0] core_io_ptw_pmp_6_cfg_a; // @[RocketTile.scala 140:20]
  wire  core_io_ptw_pmp_6_cfg_x; // @[RocketTile.scala 140:20]
  wire  core_io_ptw_pmp_6_cfg_w; // @[RocketTile.scala 140:20]
  wire  core_io_ptw_pmp_6_cfg_r; // @[RocketTile.scala 140:20]
  wire [28:0] core_io_ptw_pmp_6_addr; // @[RocketTile.scala 140:20]
  wire [30:0] core_io_ptw_pmp_6_mask; // @[RocketTile.scala 140:20]
  wire  core_io_ptw_pmp_7_cfg_l; // @[RocketTile.scala 140:20]
  wire [1:0] core_io_ptw_pmp_7_cfg_a; // @[RocketTile.scala 140:20]
  wire  core_io_ptw_pmp_7_cfg_x; // @[RocketTile.scala 140:20]
  wire  core_io_ptw_pmp_7_cfg_w; // @[RocketTile.scala 140:20]
  wire  core_io_ptw_pmp_7_cfg_r; // @[RocketTile.scala 140:20]
  wire [28:0] core_io_ptw_pmp_7_addr; // @[RocketTile.scala 140:20]
  wire [30:0] core_io_ptw_pmp_7_mask; // @[RocketTile.scala 140:20]
  wire [31:0] core_io_ptw_customCSRs_csrs_0_value; // @[RocketTile.scala 140:20]
  wire  core_io_wfi; // @[RocketTile.scala 140:20]
  reg  bundleOut_0_0_REG; // @[Interrupts.scala 126:36]
  TLXbar_7 tlMasterXbar ( // @[BaseTile.scala 210:42]
    .clock(tlMasterXbar_clock),
    .reset(tlMasterXbar_reset),
    .auto_in_1_a_ready(tlMasterXbar_auto_in_1_a_ready),
    .auto_in_1_a_valid(tlMasterXbar_auto_in_1_a_valid),
    .auto_in_1_a_bits_address(tlMasterXbar_auto_in_1_a_bits_address),
    .auto_in_1_d_ready(tlMasterXbar_auto_in_1_d_ready),
    .auto_in_1_d_valid(tlMasterXbar_auto_in_1_d_valid),
    .auto_in_1_d_bits_opcode(tlMasterXbar_auto_in_1_d_bits_opcode),
    .auto_in_1_d_bits_size(tlMasterXbar_auto_in_1_d_bits_size),
    .auto_in_1_d_bits_data(tlMasterXbar_auto_in_1_d_bits_data),
    .auto_in_1_d_bits_corrupt(tlMasterXbar_auto_in_1_d_bits_corrupt),
    .auto_in_0_a_ready(tlMasterXbar_auto_in_0_a_ready),
    .auto_in_0_a_valid(tlMasterXbar_auto_in_0_a_valid),
    .auto_in_0_a_bits_opcode(tlMasterXbar_auto_in_0_a_bits_opcode),
    .auto_in_0_a_bits_param(tlMasterXbar_auto_in_0_a_bits_param),
    .auto_in_0_a_bits_size(tlMasterXbar_auto_in_0_a_bits_size),
    .auto_in_0_a_bits_source(tlMasterXbar_auto_in_0_a_bits_source),
    .auto_in_0_a_bits_address(tlMasterXbar_auto_in_0_a_bits_address),
    .auto_in_0_a_bits_mask(tlMasterXbar_auto_in_0_a_bits_mask),
    .auto_in_0_a_bits_data(tlMasterXbar_auto_in_0_a_bits_data),
    .auto_in_0_b_ready(tlMasterXbar_auto_in_0_b_ready),
    .auto_in_0_b_valid(tlMasterXbar_auto_in_0_b_valid),
    .auto_in_0_b_bits_param(tlMasterXbar_auto_in_0_b_bits_param),
    .auto_in_0_b_bits_size(tlMasterXbar_auto_in_0_b_bits_size),
    .auto_in_0_b_bits_source(tlMasterXbar_auto_in_0_b_bits_source),
    .auto_in_0_b_bits_address(tlMasterXbar_auto_in_0_b_bits_address),
    .auto_in_0_c_ready(tlMasterXbar_auto_in_0_c_ready),
    .auto_in_0_c_valid(tlMasterXbar_auto_in_0_c_valid),
    .auto_in_0_c_bits_opcode(tlMasterXbar_auto_in_0_c_bits_opcode),
    .auto_in_0_c_bits_param(tlMasterXbar_auto_in_0_c_bits_param),
    .auto_in_0_c_bits_size(tlMasterXbar_auto_in_0_c_bits_size),
    .auto_in_0_c_bits_source(tlMasterXbar_auto_in_0_c_bits_source),
    .auto_in_0_c_bits_address(tlMasterXbar_auto_in_0_c_bits_address),
    .auto_in_0_c_bits_data(tlMasterXbar_auto_in_0_c_bits_data),
    .auto_in_0_d_ready(tlMasterXbar_auto_in_0_d_ready),
    .auto_in_0_d_valid(tlMasterXbar_auto_in_0_d_valid),
    .auto_in_0_d_bits_opcode(tlMasterXbar_auto_in_0_d_bits_opcode),
    .auto_in_0_d_bits_param(tlMasterXbar_auto_in_0_d_bits_param),
    .auto_in_0_d_bits_size(tlMasterXbar_auto_in_0_d_bits_size),
    .auto_in_0_d_bits_source(tlMasterXbar_auto_in_0_d_bits_source),
    .auto_in_0_d_bits_sink(tlMasterXbar_auto_in_0_d_bits_sink),
    .auto_in_0_d_bits_denied(tlMasterXbar_auto_in_0_d_bits_denied),
    .auto_in_0_d_bits_data(tlMasterXbar_auto_in_0_d_bits_data),
    .auto_in_0_e_ready(tlMasterXbar_auto_in_0_e_ready),
    .auto_in_0_e_valid(tlMasterXbar_auto_in_0_e_valid),
    .auto_in_0_e_bits_sink(tlMasterXbar_auto_in_0_e_bits_sink),
    .auto_out_a_ready(tlMasterXbar_auto_out_a_ready),
    .auto_out_a_valid(tlMasterXbar_auto_out_a_valid),
    .auto_out_a_bits_opcode(tlMasterXbar_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(tlMasterXbar_auto_out_a_bits_param),
    .auto_out_a_bits_size(tlMasterXbar_auto_out_a_bits_size),
    .auto_out_a_bits_source(tlMasterXbar_auto_out_a_bits_source),
    .auto_out_a_bits_address(tlMasterXbar_auto_out_a_bits_address),
    .auto_out_a_bits_mask(tlMasterXbar_auto_out_a_bits_mask),
    .auto_out_a_bits_data(tlMasterXbar_auto_out_a_bits_data),
    .auto_out_b_ready(tlMasterXbar_auto_out_b_ready),
    .auto_out_b_valid(tlMasterXbar_auto_out_b_valid),
    .auto_out_b_bits_opcode(tlMasterXbar_auto_out_b_bits_opcode),
    .auto_out_b_bits_param(tlMasterXbar_auto_out_b_bits_param),
    .auto_out_b_bits_size(tlMasterXbar_auto_out_b_bits_size),
    .auto_out_b_bits_source(tlMasterXbar_auto_out_b_bits_source),
    .auto_out_b_bits_address(tlMasterXbar_auto_out_b_bits_address),
    .auto_out_b_bits_mask(tlMasterXbar_auto_out_b_bits_mask),
    .auto_out_b_bits_corrupt(tlMasterXbar_auto_out_b_bits_corrupt),
    .auto_out_c_ready(tlMasterXbar_auto_out_c_ready),
    .auto_out_c_valid(tlMasterXbar_auto_out_c_valid),
    .auto_out_c_bits_opcode(tlMasterXbar_auto_out_c_bits_opcode),
    .auto_out_c_bits_param(tlMasterXbar_auto_out_c_bits_param),
    .auto_out_c_bits_size(tlMasterXbar_auto_out_c_bits_size),
    .auto_out_c_bits_source(tlMasterXbar_auto_out_c_bits_source),
    .auto_out_c_bits_address(tlMasterXbar_auto_out_c_bits_address),
    .auto_out_c_bits_data(tlMasterXbar_auto_out_c_bits_data),
    .auto_out_d_ready(tlMasterXbar_auto_out_d_ready),
    .auto_out_d_valid(tlMasterXbar_auto_out_d_valid),
    .auto_out_d_bits_opcode(tlMasterXbar_auto_out_d_bits_opcode),
    .auto_out_d_bits_param(tlMasterXbar_auto_out_d_bits_param),
    .auto_out_d_bits_size(tlMasterXbar_auto_out_d_bits_size),
    .auto_out_d_bits_source(tlMasterXbar_auto_out_d_bits_source),
    .auto_out_d_bits_sink(tlMasterXbar_auto_out_d_bits_sink),
    .auto_out_d_bits_denied(tlMasterXbar_auto_out_d_bits_denied),
    .auto_out_d_bits_data(tlMasterXbar_auto_out_d_bits_data),
    .auto_out_d_bits_corrupt(tlMasterXbar_auto_out_d_bits_corrupt),
    .auto_out_e_ready(tlMasterXbar_auto_out_e_ready),
    .auto_out_e_valid(tlMasterXbar_auto_out_e_valid),
    .auto_out_e_bits_sink(tlMasterXbar_auto_out_e_bits_sink)
  );
  TLXbar_8 tlSlaveXbar ( // @[BaseTile.scala 211:41]
    .auto_in_a_ready(tlSlaveXbar_auto_in_a_ready),
    .auto_in_a_valid(tlSlaveXbar_auto_in_a_valid),
    .auto_in_a_bits_opcode(tlSlaveXbar_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(tlSlaveXbar_auto_in_a_bits_param),
    .auto_in_a_bits_size(tlSlaveXbar_auto_in_a_bits_size),
    .auto_in_a_bits_source(tlSlaveXbar_auto_in_a_bits_source),
    .auto_in_a_bits_address(tlSlaveXbar_auto_in_a_bits_address),
    .auto_in_a_bits_mask(tlSlaveXbar_auto_in_a_bits_mask),
    .auto_in_a_bits_data(tlSlaveXbar_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(tlSlaveXbar_auto_in_a_bits_corrupt),
    .auto_in_d_ready(tlSlaveXbar_auto_in_d_ready),
    .auto_in_d_valid(tlSlaveXbar_auto_in_d_valid),
    .auto_in_d_bits_opcode(tlSlaveXbar_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(tlSlaveXbar_auto_in_d_bits_size),
    .auto_in_d_bits_source(tlSlaveXbar_auto_in_d_bits_source),
    .auto_in_d_bits_data(tlSlaveXbar_auto_in_d_bits_data),
    .auto_out_a_ready(tlSlaveXbar_auto_out_a_ready),
    .auto_out_a_valid(tlSlaveXbar_auto_out_a_valid),
    .auto_out_a_bits_opcode(tlSlaveXbar_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(tlSlaveXbar_auto_out_a_bits_param),
    .auto_out_a_bits_size(tlSlaveXbar_auto_out_a_bits_size),
    .auto_out_a_bits_source(tlSlaveXbar_auto_out_a_bits_source),
    .auto_out_a_bits_address(tlSlaveXbar_auto_out_a_bits_address),
    .auto_out_a_bits_mask(tlSlaveXbar_auto_out_a_bits_mask),
    .auto_out_a_bits_data(tlSlaveXbar_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(tlSlaveXbar_auto_out_a_bits_corrupt),
    .auto_out_d_ready(tlSlaveXbar_auto_out_d_ready),
    .auto_out_d_valid(tlSlaveXbar_auto_out_d_valid),
    .auto_out_d_bits_opcode(tlSlaveXbar_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(tlSlaveXbar_auto_out_d_bits_size),
    .auto_out_d_bits_source(tlSlaveXbar_auto_out_d_bits_source),
    .auto_out_d_bits_data(tlSlaveXbar_auto_out_d_bits_data)
  );
  IntXbar_1 intXbar ( // @[BaseTile.scala 212:37]
    .auto_int_in_3_0(intXbar_auto_int_in_3_0),
    .auto_int_in_2_0(intXbar_auto_int_in_2_0),
    .auto_int_in_1_0(intXbar_auto_int_in_1_0),
    .auto_int_in_1_1(intXbar_auto_int_in_1_1),
    .auto_int_in_0_0(intXbar_auto_int_in_0_0),
    .auto_int_out_0(intXbar_auto_int_out_0),
    .auto_int_out_1(intXbar_auto_int_out_1),
    .auto_int_out_2(intXbar_auto_int_out_2),
    .auto_int_out_3(intXbar_auto_int_out_3),
    .auto_int_out_4(intXbar_auto_int_out_4)
  );
  BundleBridgeNexus_6 broadcast ( // @[BundleBridge.scala 196:31]
    .auto_in(broadcast_auto_in),
    .auto_out_0(broadcast_auto_out_0)
  );
  DCache dcache ( // @[HellaCache.scala 269:43]
    .clock(dcache_clock),
    .reset(dcache_reset),
    .auto_out_a_ready(dcache_auto_out_a_ready),
    .auto_out_a_valid(dcache_auto_out_a_valid),
    .auto_out_a_bits_opcode(dcache_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(dcache_auto_out_a_bits_param),
    .auto_out_a_bits_size(dcache_auto_out_a_bits_size),
    .auto_out_a_bits_source(dcache_auto_out_a_bits_source),
    .auto_out_a_bits_address(dcache_auto_out_a_bits_address),
    .auto_out_a_bits_mask(dcache_auto_out_a_bits_mask),
    .auto_out_a_bits_data(dcache_auto_out_a_bits_data),
    .auto_out_b_ready(dcache_auto_out_b_ready),
    .auto_out_b_valid(dcache_auto_out_b_valid),
    .auto_out_b_bits_param(dcache_auto_out_b_bits_param),
    .auto_out_b_bits_size(dcache_auto_out_b_bits_size),
    .auto_out_b_bits_source(dcache_auto_out_b_bits_source),
    .auto_out_b_bits_address(dcache_auto_out_b_bits_address),
    .auto_out_c_ready(dcache_auto_out_c_ready),
    .auto_out_c_valid(dcache_auto_out_c_valid),
    .auto_out_c_bits_opcode(dcache_auto_out_c_bits_opcode),
    .auto_out_c_bits_param(dcache_auto_out_c_bits_param),
    .auto_out_c_bits_size(dcache_auto_out_c_bits_size),
    .auto_out_c_bits_source(dcache_auto_out_c_bits_source),
    .auto_out_c_bits_address(dcache_auto_out_c_bits_address),
    .auto_out_c_bits_data(dcache_auto_out_c_bits_data),
    .auto_out_d_ready(dcache_auto_out_d_ready),
    .auto_out_d_valid(dcache_auto_out_d_valid),
    .auto_out_d_bits_opcode(dcache_auto_out_d_bits_opcode),
    .auto_out_d_bits_param(dcache_auto_out_d_bits_param),
    .auto_out_d_bits_size(dcache_auto_out_d_bits_size),
    .auto_out_d_bits_source(dcache_auto_out_d_bits_source),
    .auto_out_d_bits_sink(dcache_auto_out_d_bits_sink),
    .auto_out_d_bits_denied(dcache_auto_out_d_bits_denied),
    .auto_out_d_bits_data(dcache_auto_out_d_bits_data),
    .auto_out_e_ready(dcache_auto_out_e_ready),
    .auto_out_e_valid(dcache_auto_out_e_valid),
    .auto_out_e_bits_sink(dcache_auto_out_e_bits_sink),
    .io_cpu_req_ready(dcache_io_cpu_req_ready),
    .io_cpu_req_valid(dcache_io_cpu_req_valid),
    .io_cpu_req_bits_addr(dcache_io_cpu_req_bits_addr),
    .io_cpu_req_bits_tag(dcache_io_cpu_req_bits_tag),
    .io_cpu_req_bits_cmd(dcache_io_cpu_req_bits_cmd),
    .io_cpu_req_bits_size(dcache_io_cpu_req_bits_size),
    .io_cpu_req_bits_signed(dcache_io_cpu_req_bits_signed),
    .io_cpu_req_bits_dprv(dcache_io_cpu_req_bits_dprv),
    .io_cpu_s1_kill(dcache_io_cpu_s1_kill),
    .io_cpu_s1_data_data(dcache_io_cpu_s1_data_data),
    .io_cpu_s1_data_mask(dcache_io_cpu_s1_data_mask),
    .io_cpu_s2_nack(dcache_io_cpu_s2_nack),
    .io_cpu_resp_valid(dcache_io_cpu_resp_valid),
    .io_cpu_resp_bits_addr(dcache_io_cpu_resp_bits_addr),
    .io_cpu_resp_bits_tag(dcache_io_cpu_resp_bits_tag),
    .io_cpu_resp_bits_cmd(dcache_io_cpu_resp_bits_cmd),
    .io_cpu_resp_bits_size(dcache_io_cpu_resp_bits_size),
    .io_cpu_resp_bits_signed(dcache_io_cpu_resp_bits_signed),
    .io_cpu_resp_bits_dprv(dcache_io_cpu_resp_bits_dprv),
    .io_cpu_resp_bits_dv(dcache_io_cpu_resp_bits_dv),
    .io_cpu_resp_bits_data(dcache_io_cpu_resp_bits_data),
    .io_cpu_resp_bits_mask(dcache_io_cpu_resp_bits_mask),
    .io_cpu_resp_bits_replay(dcache_io_cpu_resp_bits_replay),
    .io_cpu_resp_bits_has_data(dcache_io_cpu_resp_bits_has_data),
    .io_cpu_resp_bits_data_word_bypass(dcache_io_cpu_resp_bits_data_word_bypass),
    .io_cpu_resp_bits_data_raw(dcache_io_cpu_resp_bits_data_raw),
    .io_cpu_resp_bits_store_data(dcache_io_cpu_resp_bits_store_data),
    .io_cpu_replay_next(dcache_io_cpu_replay_next),
    .io_cpu_s2_xcpt_ma_ld(dcache_io_cpu_s2_xcpt_ma_ld),
    .io_cpu_s2_xcpt_ma_st(dcache_io_cpu_s2_xcpt_ma_st),
    .io_cpu_s2_xcpt_pf_ld(dcache_io_cpu_s2_xcpt_pf_ld),
    .io_cpu_s2_xcpt_pf_st(dcache_io_cpu_s2_xcpt_pf_st),
    .io_cpu_s2_xcpt_gf_ld(dcache_io_cpu_s2_xcpt_gf_ld),
    .io_cpu_s2_xcpt_gf_st(dcache_io_cpu_s2_xcpt_gf_st),
    .io_cpu_s2_xcpt_ae_ld(dcache_io_cpu_s2_xcpt_ae_ld),
    .io_cpu_s2_xcpt_ae_st(dcache_io_cpu_s2_xcpt_ae_st),
    .io_cpu_ordered(dcache_io_cpu_ordered),
    .io_cpu_perf_release(dcache_io_cpu_perf_release),
    .io_cpu_perf_grant(dcache_io_cpu_perf_grant),
    .io_ptw_status_debug(dcache_io_ptw_status_debug),
    .io_ptw_pmp_0_cfg_l(dcache_io_ptw_pmp_0_cfg_l),
    .io_ptw_pmp_0_cfg_a(dcache_io_ptw_pmp_0_cfg_a),
    .io_ptw_pmp_0_cfg_x(dcache_io_ptw_pmp_0_cfg_x),
    .io_ptw_pmp_0_cfg_w(dcache_io_ptw_pmp_0_cfg_w),
    .io_ptw_pmp_0_cfg_r(dcache_io_ptw_pmp_0_cfg_r),
    .io_ptw_pmp_0_addr(dcache_io_ptw_pmp_0_addr),
    .io_ptw_pmp_0_mask(dcache_io_ptw_pmp_0_mask),
    .io_ptw_pmp_1_cfg_l(dcache_io_ptw_pmp_1_cfg_l),
    .io_ptw_pmp_1_cfg_a(dcache_io_ptw_pmp_1_cfg_a),
    .io_ptw_pmp_1_cfg_x(dcache_io_ptw_pmp_1_cfg_x),
    .io_ptw_pmp_1_cfg_w(dcache_io_ptw_pmp_1_cfg_w),
    .io_ptw_pmp_1_cfg_r(dcache_io_ptw_pmp_1_cfg_r),
    .io_ptw_pmp_1_addr(dcache_io_ptw_pmp_1_addr),
    .io_ptw_pmp_1_mask(dcache_io_ptw_pmp_1_mask),
    .io_ptw_pmp_2_cfg_l(dcache_io_ptw_pmp_2_cfg_l),
    .io_ptw_pmp_2_cfg_a(dcache_io_ptw_pmp_2_cfg_a),
    .io_ptw_pmp_2_cfg_x(dcache_io_ptw_pmp_2_cfg_x),
    .io_ptw_pmp_2_cfg_w(dcache_io_ptw_pmp_2_cfg_w),
    .io_ptw_pmp_2_cfg_r(dcache_io_ptw_pmp_2_cfg_r),
    .io_ptw_pmp_2_addr(dcache_io_ptw_pmp_2_addr),
    .io_ptw_pmp_2_mask(dcache_io_ptw_pmp_2_mask),
    .io_ptw_pmp_3_cfg_l(dcache_io_ptw_pmp_3_cfg_l),
    .io_ptw_pmp_3_cfg_a(dcache_io_ptw_pmp_3_cfg_a),
    .io_ptw_pmp_3_cfg_x(dcache_io_ptw_pmp_3_cfg_x),
    .io_ptw_pmp_3_cfg_w(dcache_io_ptw_pmp_3_cfg_w),
    .io_ptw_pmp_3_cfg_r(dcache_io_ptw_pmp_3_cfg_r),
    .io_ptw_pmp_3_addr(dcache_io_ptw_pmp_3_addr),
    .io_ptw_pmp_3_mask(dcache_io_ptw_pmp_3_mask),
    .io_ptw_pmp_4_cfg_l(dcache_io_ptw_pmp_4_cfg_l),
    .io_ptw_pmp_4_cfg_a(dcache_io_ptw_pmp_4_cfg_a),
    .io_ptw_pmp_4_cfg_x(dcache_io_ptw_pmp_4_cfg_x),
    .io_ptw_pmp_4_cfg_w(dcache_io_ptw_pmp_4_cfg_w),
    .io_ptw_pmp_4_cfg_r(dcache_io_ptw_pmp_4_cfg_r),
    .io_ptw_pmp_4_addr(dcache_io_ptw_pmp_4_addr),
    .io_ptw_pmp_4_mask(dcache_io_ptw_pmp_4_mask),
    .io_ptw_pmp_5_cfg_l(dcache_io_ptw_pmp_5_cfg_l),
    .io_ptw_pmp_5_cfg_a(dcache_io_ptw_pmp_5_cfg_a),
    .io_ptw_pmp_5_cfg_x(dcache_io_ptw_pmp_5_cfg_x),
    .io_ptw_pmp_5_cfg_w(dcache_io_ptw_pmp_5_cfg_w),
    .io_ptw_pmp_5_cfg_r(dcache_io_ptw_pmp_5_cfg_r),
    .io_ptw_pmp_5_addr(dcache_io_ptw_pmp_5_addr),
    .io_ptw_pmp_5_mask(dcache_io_ptw_pmp_5_mask),
    .io_ptw_pmp_6_cfg_l(dcache_io_ptw_pmp_6_cfg_l),
    .io_ptw_pmp_6_cfg_a(dcache_io_ptw_pmp_6_cfg_a),
    .io_ptw_pmp_6_cfg_x(dcache_io_ptw_pmp_6_cfg_x),
    .io_ptw_pmp_6_cfg_w(dcache_io_ptw_pmp_6_cfg_w),
    .io_ptw_pmp_6_cfg_r(dcache_io_ptw_pmp_6_cfg_r),
    .io_ptw_pmp_6_addr(dcache_io_ptw_pmp_6_addr),
    .io_ptw_pmp_6_mask(dcache_io_ptw_pmp_6_mask),
    .io_ptw_pmp_7_cfg_l(dcache_io_ptw_pmp_7_cfg_l),
    .io_ptw_pmp_7_cfg_a(dcache_io_ptw_pmp_7_cfg_a),
    .io_ptw_pmp_7_cfg_x(dcache_io_ptw_pmp_7_cfg_x),
    .io_ptw_pmp_7_cfg_w(dcache_io_ptw_pmp_7_cfg_w),
    .io_ptw_pmp_7_cfg_r(dcache_io_ptw_pmp_7_cfg_r),
    .io_ptw_pmp_7_addr(dcache_io_ptw_pmp_7_addr),
    .io_ptw_pmp_7_mask(dcache_io_ptw_pmp_7_mask)
  );
  Frontend frontend ( // @[Frontend.scala 371:28]
    .clock(frontend_clock),
    .reset(frontend_reset),
    .auto_icache_slave_in_a_ready(frontend_auto_icache_slave_in_a_ready),
    .auto_icache_slave_in_a_valid(frontend_auto_icache_slave_in_a_valid),
    .auto_icache_slave_in_a_bits_opcode(frontend_auto_icache_slave_in_a_bits_opcode),
    .auto_icache_slave_in_a_bits_size(frontend_auto_icache_slave_in_a_bits_size),
    .auto_icache_slave_in_a_bits_source(frontend_auto_icache_slave_in_a_bits_source),
    .auto_icache_slave_in_a_bits_address(frontend_auto_icache_slave_in_a_bits_address),
    .auto_icache_slave_in_a_bits_mask(frontend_auto_icache_slave_in_a_bits_mask),
    .auto_icache_slave_in_a_bits_data(frontend_auto_icache_slave_in_a_bits_data),
    .auto_icache_slave_in_d_ready(frontend_auto_icache_slave_in_d_ready),
    .auto_icache_slave_in_d_valid(frontend_auto_icache_slave_in_d_valid),
    .auto_icache_slave_in_d_bits_opcode(frontend_auto_icache_slave_in_d_bits_opcode),
    .auto_icache_slave_in_d_bits_size(frontend_auto_icache_slave_in_d_bits_size),
    .auto_icache_slave_in_d_bits_source(frontend_auto_icache_slave_in_d_bits_source),
    .auto_icache_slave_in_d_bits_data(frontend_auto_icache_slave_in_d_bits_data),
    .auto_icache_master_out_a_ready(frontend_auto_icache_master_out_a_ready),
    .auto_icache_master_out_a_valid(frontend_auto_icache_master_out_a_valid),
    .auto_icache_master_out_a_bits_address(frontend_auto_icache_master_out_a_bits_address),
    .auto_icache_master_out_d_ready(frontend_auto_icache_master_out_d_ready),
    .auto_icache_master_out_d_valid(frontend_auto_icache_master_out_d_valid),
    .auto_icache_master_out_d_bits_opcode(frontend_auto_icache_master_out_d_bits_opcode),
    .auto_icache_master_out_d_bits_size(frontend_auto_icache_master_out_d_bits_size),
    .auto_icache_master_out_d_bits_data(frontend_auto_icache_master_out_d_bits_data),
    .auto_icache_master_out_d_bits_corrupt(frontend_auto_icache_master_out_d_bits_corrupt),
    .io_cpu_might_request(frontend_io_cpu_might_request),
    .io_cpu_req_valid(frontend_io_cpu_req_valid),
    .io_cpu_req_bits_pc(frontend_io_cpu_req_bits_pc),
    .io_cpu_req_bits_speculative(frontend_io_cpu_req_bits_speculative),
    .io_cpu_resp_ready(frontend_io_cpu_resp_ready),
    .io_cpu_resp_valid(frontend_io_cpu_resp_valid),
    .io_cpu_resp_bits_btb_taken(frontend_io_cpu_resp_bits_btb_taken),
    .io_cpu_resp_bits_btb_bridx(frontend_io_cpu_resp_bits_btb_bridx),
    .io_cpu_resp_bits_btb_entry(frontend_io_cpu_resp_bits_btb_entry),
    .io_cpu_resp_bits_btb_bht_history(frontend_io_cpu_resp_bits_btb_bht_history),
    .io_cpu_resp_bits_pc(frontend_io_cpu_resp_bits_pc),
    .io_cpu_resp_bits_data(frontend_io_cpu_resp_bits_data),
    .io_cpu_resp_bits_xcpt_ae_inst(frontend_io_cpu_resp_bits_xcpt_ae_inst),
    .io_cpu_resp_bits_replay(frontend_io_cpu_resp_bits_replay),
    .io_cpu_btb_update_valid(frontend_io_cpu_btb_update_valid),
    .io_cpu_btb_update_bits_prediction_entry(frontend_io_cpu_btb_update_bits_prediction_entry),
    .io_cpu_btb_update_bits_pc(frontend_io_cpu_btb_update_bits_pc),
    .io_cpu_btb_update_bits_isValid(frontend_io_cpu_btb_update_bits_isValid),
    .io_cpu_btb_update_bits_br_pc(frontend_io_cpu_btb_update_bits_br_pc),
    .io_cpu_btb_update_bits_cfiType(frontend_io_cpu_btb_update_bits_cfiType),
    .io_cpu_bht_update_valid(frontend_io_cpu_bht_update_valid),
    .io_cpu_bht_update_bits_prediction_history(frontend_io_cpu_bht_update_bits_prediction_history),
    .io_cpu_bht_update_bits_pc(frontend_io_cpu_bht_update_bits_pc),
    .io_cpu_bht_update_bits_branch(frontend_io_cpu_bht_update_bits_branch),
    .io_cpu_bht_update_bits_taken(frontend_io_cpu_bht_update_bits_taken),
    .io_cpu_bht_update_bits_mispredict(frontend_io_cpu_bht_update_bits_mispredict),
    .io_cpu_flush_icache(frontend_io_cpu_flush_icache),
    .io_cpu_npc(frontend_io_cpu_npc),
    .io_ptw_status_debug(frontend_io_ptw_status_debug),
    .io_ptw_status_prv(frontend_io_ptw_status_prv),
    .io_ptw_pmp_0_cfg_l(frontend_io_ptw_pmp_0_cfg_l),
    .io_ptw_pmp_0_cfg_a(frontend_io_ptw_pmp_0_cfg_a),
    .io_ptw_pmp_0_cfg_x(frontend_io_ptw_pmp_0_cfg_x),
    .io_ptw_pmp_0_cfg_w(frontend_io_ptw_pmp_0_cfg_w),
    .io_ptw_pmp_0_cfg_r(frontend_io_ptw_pmp_0_cfg_r),
    .io_ptw_pmp_0_addr(frontend_io_ptw_pmp_0_addr),
    .io_ptw_pmp_0_mask(frontend_io_ptw_pmp_0_mask),
    .io_ptw_pmp_1_cfg_l(frontend_io_ptw_pmp_1_cfg_l),
    .io_ptw_pmp_1_cfg_a(frontend_io_ptw_pmp_1_cfg_a),
    .io_ptw_pmp_1_cfg_x(frontend_io_ptw_pmp_1_cfg_x),
    .io_ptw_pmp_1_cfg_w(frontend_io_ptw_pmp_1_cfg_w),
    .io_ptw_pmp_1_cfg_r(frontend_io_ptw_pmp_1_cfg_r),
    .io_ptw_pmp_1_addr(frontend_io_ptw_pmp_1_addr),
    .io_ptw_pmp_1_mask(frontend_io_ptw_pmp_1_mask),
    .io_ptw_pmp_2_cfg_l(frontend_io_ptw_pmp_2_cfg_l),
    .io_ptw_pmp_2_cfg_a(frontend_io_ptw_pmp_2_cfg_a),
    .io_ptw_pmp_2_cfg_x(frontend_io_ptw_pmp_2_cfg_x),
    .io_ptw_pmp_2_cfg_w(frontend_io_ptw_pmp_2_cfg_w),
    .io_ptw_pmp_2_cfg_r(frontend_io_ptw_pmp_2_cfg_r),
    .io_ptw_pmp_2_addr(frontend_io_ptw_pmp_2_addr),
    .io_ptw_pmp_2_mask(frontend_io_ptw_pmp_2_mask),
    .io_ptw_pmp_3_cfg_l(frontend_io_ptw_pmp_3_cfg_l),
    .io_ptw_pmp_3_cfg_a(frontend_io_ptw_pmp_3_cfg_a),
    .io_ptw_pmp_3_cfg_x(frontend_io_ptw_pmp_3_cfg_x),
    .io_ptw_pmp_3_cfg_w(frontend_io_ptw_pmp_3_cfg_w),
    .io_ptw_pmp_3_cfg_r(frontend_io_ptw_pmp_3_cfg_r),
    .io_ptw_pmp_3_addr(frontend_io_ptw_pmp_3_addr),
    .io_ptw_pmp_3_mask(frontend_io_ptw_pmp_3_mask),
    .io_ptw_pmp_4_cfg_l(frontend_io_ptw_pmp_4_cfg_l),
    .io_ptw_pmp_4_cfg_a(frontend_io_ptw_pmp_4_cfg_a),
    .io_ptw_pmp_4_cfg_x(frontend_io_ptw_pmp_4_cfg_x),
    .io_ptw_pmp_4_cfg_w(frontend_io_ptw_pmp_4_cfg_w),
    .io_ptw_pmp_4_cfg_r(frontend_io_ptw_pmp_4_cfg_r),
    .io_ptw_pmp_4_addr(frontend_io_ptw_pmp_4_addr),
    .io_ptw_pmp_4_mask(frontend_io_ptw_pmp_4_mask),
    .io_ptw_pmp_5_cfg_l(frontend_io_ptw_pmp_5_cfg_l),
    .io_ptw_pmp_5_cfg_a(frontend_io_ptw_pmp_5_cfg_a),
    .io_ptw_pmp_5_cfg_x(frontend_io_ptw_pmp_5_cfg_x),
    .io_ptw_pmp_5_cfg_w(frontend_io_ptw_pmp_5_cfg_w),
    .io_ptw_pmp_5_cfg_r(frontend_io_ptw_pmp_5_cfg_r),
    .io_ptw_pmp_5_addr(frontend_io_ptw_pmp_5_addr),
    .io_ptw_pmp_5_mask(frontend_io_ptw_pmp_5_mask),
    .io_ptw_pmp_6_cfg_l(frontend_io_ptw_pmp_6_cfg_l),
    .io_ptw_pmp_6_cfg_a(frontend_io_ptw_pmp_6_cfg_a),
    .io_ptw_pmp_6_cfg_x(frontend_io_ptw_pmp_6_cfg_x),
    .io_ptw_pmp_6_cfg_w(frontend_io_ptw_pmp_6_cfg_w),
    .io_ptw_pmp_6_cfg_r(frontend_io_ptw_pmp_6_cfg_r),
    .io_ptw_pmp_6_addr(frontend_io_ptw_pmp_6_addr),
    .io_ptw_pmp_6_mask(frontend_io_ptw_pmp_6_mask),
    .io_ptw_pmp_7_cfg_l(frontend_io_ptw_pmp_7_cfg_l),
    .io_ptw_pmp_7_cfg_a(frontend_io_ptw_pmp_7_cfg_a),
    .io_ptw_pmp_7_cfg_x(frontend_io_ptw_pmp_7_cfg_x),
    .io_ptw_pmp_7_cfg_w(frontend_io_ptw_pmp_7_cfg_w),
    .io_ptw_pmp_7_cfg_r(frontend_io_ptw_pmp_7_cfg_r),
    .io_ptw_pmp_7_addr(frontend_io_ptw_pmp_7_addr),
    .io_ptw_pmp_7_mask(frontend_io_ptw_pmp_7_mask),
    .io_ptw_customCSRs_csrs_0_value(frontend_io_ptw_customCSRs_csrs_0_value)
  );
  TLFragmenter_21 fragmenter ( // @[Fragmenter.scala 333:34]
    .clock(fragmenter_clock),
    .reset(fragmenter_reset),
    .auto_in_a_ready(fragmenter_auto_in_a_ready),
    .auto_in_a_valid(fragmenter_auto_in_a_valid),
    .auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
    .auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
    .auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
    .auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
    .auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
    .auto_in_a_bits_data(fragmenter_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
    .auto_in_d_ready(fragmenter_auto_in_d_ready),
    .auto_in_d_valid(fragmenter_auto_in_d_valid),
    .auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
    .auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
    .auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
    .auto_out_a_ready(fragmenter_auto_out_a_ready),
    .auto_out_a_valid(fragmenter_auto_out_a_valid),
    .auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
    .auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
    .auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
    .auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
    .auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
    .auto_out_a_bits_data(fragmenter_auto_out_a_bits_data),
    .auto_out_d_ready(fragmenter_auto_out_d_ready),
    .auto_out_d_valid(fragmenter_auto_out_d_valid),
    .auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
    .auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
    .auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
  );
  HellaCacheArbiter dcacheArb ( // @[HellaCache.scala 280:25]
    .io_requestor_0_req_ready(dcacheArb_io_requestor_0_req_ready),
    .io_requestor_0_req_valid(dcacheArb_io_requestor_0_req_valid),
    .io_requestor_0_req_bits_addr(dcacheArb_io_requestor_0_req_bits_addr),
    .io_requestor_0_req_bits_tag(dcacheArb_io_requestor_0_req_bits_tag),
    .io_requestor_0_req_bits_cmd(dcacheArb_io_requestor_0_req_bits_cmd),
    .io_requestor_0_req_bits_size(dcacheArb_io_requestor_0_req_bits_size),
    .io_requestor_0_req_bits_signed(dcacheArb_io_requestor_0_req_bits_signed),
    .io_requestor_0_req_bits_dprv(dcacheArb_io_requestor_0_req_bits_dprv),
    .io_requestor_0_s1_kill(dcacheArb_io_requestor_0_s1_kill),
    .io_requestor_0_s1_data_data(dcacheArb_io_requestor_0_s1_data_data),
    .io_requestor_0_s2_nack(dcacheArb_io_requestor_0_s2_nack),
    .io_requestor_0_resp_valid(dcacheArb_io_requestor_0_resp_valid),
    .io_requestor_0_resp_bits_tag(dcacheArb_io_requestor_0_resp_bits_tag),
    .io_requestor_0_resp_bits_data(dcacheArb_io_requestor_0_resp_bits_data),
    .io_requestor_0_resp_bits_replay(dcacheArb_io_requestor_0_resp_bits_replay),
    .io_requestor_0_resp_bits_has_data(dcacheArb_io_requestor_0_resp_bits_has_data),
    .io_requestor_0_resp_bits_data_word_bypass(dcacheArb_io_requestor_0_resp_bits_data_word_bypass),
    .io_requestor_0_replay_next(dcacheArb_io_requestor_0_replay_next),
    .io_requestor_0_s2_xcpt_ma_ld(dcacheArb_io_requestor_0_s2_xcpt_ma_ld),
    .io_requestor_0_s2_xcpt_ma_st(dcacheArb_io_requestor_0_s2_xcpt_ma_st),
    .io_requestor_0_s2_xcpt_pf_ld(dcacheArb_io_requestor_0_s2_xcpt_pf_ld),
    .io_requestor_0_s2_xcpt_pf_st(dcacheArb_io_requestor_0_s2_xcpt_pf_st),
    .io_requestor_0_s2_xcpt_ae_ld(dcacheArb_io_requestor_0_s2_xcpt_ae_ld),
    .io_requestor_0_s2_xcpt_ae_st(dcacheArb_io_requestor_0_s2_xcpt_ae_st),
    .io_requestor_0_ordered(dcacheArb_io_requestor_0_ordered),
    .io_requestor_0_perf_release(dcacheArb_io_requestor_0_perf_release),
    .io_requestor_0_perf_grant(dcacheArb_io_requestor_0_perf_grant),
    .io_mem_req_ready(dcacheArb_io_mem_req_ready),
    .io_mem_req_valid(dcacheArb_io_mem_req_valid),
    .io_mem_req_bits_addr(dcacheArb_io_mem_req_bits_addr),
    .io_mem_req_bits_tag(dcacheArb_io_mem_req_bits_tag),
    .io_mem_req_bits_cmd(dcacheArb_io_mem_req_bits_cmd),
    .io_mem_req_bits_size(dcacheArb_io_mem_req_bits_size),
    .io_mem_req_bits_signed(dcacheArb_io_mem_req_bits_signed),
    .io_mem_req_bits_dprv(dcacheArb_io_mem_req_bits_dprv),
    .io_mem_s1_kill(dcacheArb_io_mem_s1_kill),
    .io_mem_s1_data_data(dcacheArb_io_mem_s1_data_data),
    .io_mem_s2_nack(dcacheArb_io_mem_s2_nack),
    .io_mem_resp_valid(dcacheArb_io_mem_resp_valid),
    .io_mem_resp_bits_tag(dcacheArb_io_mem_resp_bits_tag),
    .io_mem_resp_bits_data(dcacheArb_io_mem_resp_bits_data),
    .io_mem_resp_bits_replay(dcacheArb_io_mem_resp_bits_replay),
    .io_mem_resp_bits_has_data(dcacheArb_io_mem_resp_bits_has_data),
    .io_mem_resp_bits_data_word_bypass(dcacheArb_io_mem_resp_bits_data_word_bypass),
    .io_mem_replay_next(dcacheArb_io_mem_replay_next),
    .io_mem_s2_xcpt_ma_ld(dcacheArb_io_mem_s2_xcpt_ma_ld),
    .io_mem_s2_xcpt_ma_st(dcacheArb_io_mem_s2_xcpt_ma_st),
    .io_mem_s2_xcpt_pf_ld(dcacheArb_io_mem_s2_xcpt_pf_ld),
    .io_mem_s2_xcpt_pf_st(dcacheArb_io_mem_s2_xcpt_pf_st),
    .io_mem_s2_xcpt_ae_ld(dcacheArb_io_mem_s2_xcpt_ae_ld),
    .io_mem_s2_xcpt_ae_st(dcacheArb_io_mem_s2_xcpt_ae_st),
    .io_mem_ordered(dcacheArb_io_mem_ordered),
    .io_mem_perf_release(dcacheArb_io_mem_perf_release),
    .io_mem_perf_grant(dcacheArb_io_mem_perf_grant)
  );
  PTW ptw ( // @[PTW.scala 604:19]
    .clock(ptw_clock),
    .reset(ptw_reset),
    .io_requestor_0_status_debug(ptw_io_requestor_0_status_debug),
    .io_requestor_0_pmp_0_cfg_l(ptw_io_requestor_0_pmp_0_cfg_l),
    .io_requestor_0_pmp_0_cfg_a(ptw_io_requestor_0_pmp_0_cfg_a),
    .io_requestor_0_pmp_0_cfg_x(ptw_io_requestor_0_pmp_0_cfg_x),
    .io_requestor_0_pmp_0_cfg_w(ptw_io_requestor_0_pmp_0_cfg_w),
    .io_requestor_0_pmp_0_cfg_r(ptw_io_requestor_0_pmp_0_cfg_r),
    .io_requestor_0_pmp_0_addr(ptw_io_requestor_0_pmp_0_addr),
    .io_requestor_0_pmp_0_mask(ptw_io_requestor_0_pmp_0_mask),
    .io_requestor_0_pmp_1_cfg_l(ptw_io_requestor_0_pmp_1_cfg_l),
    .io_requestor_0_pmp_1_cfg_a(ptw_io_requestor_0_pmp_1_cfg_a),
    .io_requestor_0_pmp_1_cfg_x(ptw_io_requestor_0_pmp_1_cfg_x),
    .io_requestor_0_pmp_1_cfg_w(ptw_io_requestor_0_pmp_1_cfg_w),
    .io_requestor_0_pmp_1_cfg_r(ptw_io_requestor_0_pmp_1_cfg_r),
    .io_requestor_0_pmp_1_addr(ptw_io_requestor_0_pmp_1_addr),
    .io_requestor_0_pmp_1_mask(ptw_io_requestor_0_pmp_1_mask),
    .io_requestor_0_pmp_2_cfg_l(ptw_io_requestor_0_pmp_2_cfg_l),
    .io_requestor_0_pmp_2_cfg_a(ptw_io_requestor_0_pmp_2_cfg_a),
    .io_requestor_0_pmp_2_cfg_x(ptw_io_requestor_0_pmp_2_cfg_x),
    .io_requestor_0_pmp_2_cfg_w(ptw_io_requestor_0_pmp_2_cfg_w),
    .io_requestor_0_pmp_2_cfg_r(ptw_io_requestor_0_pmp_2_cfg_r),
    .io_requestor_0_pmp_2_addr(ptw_io_requestor_0_pmp_2_addr),
    .io_requestor_0_pmp_2_mask(ptw_io_requestor_0_pmp_2_mask),
    .io_requestor_0_pmp_3_cfg_l(ptw_io_requestor_0_pmp_3_cfg_l),
    .io_requestor_0_pmp_3_cfg_a(ptw_io_requestor_0_pmp_3_cfg_a),
    .io_requestor_0_pmp_3_cfg_x(ptw_io_requestor_0_pmp_3_cfg_x),
    .io_requestor_0_pmp_3_cfg_w(ptw_io_requestor_0_pmp_3_cfg_w),
    .io_requestor_0_pmp_3_cfg_r(ptw_io_requestor_0_pmp_3_cfg_r),
    .io_requestor_0_pmp_3_addr(ptw_io_requestor_0_pmp_3_addr),
    .io_requestor_0_pmp_3_mask(ptw_io_requestor_0_pmp_3_mask),
    .io_requestor_0_pmp_4_cfg_l(ptw_io_requestor_0_pmp_4_cfg_l),
    .io_requestor_0_pmp_4_cfg_a(ptw_io_requestor_0_pmp_4_cfg_a),
    .io_requestor_0_pmp_4_cfg_x(ptw_io_requestor_0_pmp_4_cfg_x),
    .io_requestor_0_pmp_4_cfg_w(ptw_io_requestor_0_pmp_4_cfg_w),
    .io_requestor_0_pmp_4_cfg_r(ptw_io_requestor_0_pmp_4_cfg_r),
    .io_requestor_0_pmp_4_addr(ptw_io_requestor_0_pmp_4_addr),
    .io_requestor_0_pmp_4_mask(ptw_io_requestor_0_pmp_4_mask),
    .io_requestor_0_pmp_5_cfg_l(ptw_io_requestor_0_pmp_5_cfg_l),
    .io_requestor_0_pmp_5_cfg_a(ptw_io_requestor_0_pmp_5_cfg_a),
    .io_requestor_0_pmp_5_cfg_x(ptw_io_requestor_0_pmp_5_cfg_x),
    .io_requestor_0_pmp_5_cfg_w(ptw_io_requestor_0_pmp_5_cfg_w),
    .io_requestor_0_pmp_5_cfg_r(ptw_io_requestor_0_pmp_5_cfg_r),
    .io_requestor_0_pmp_5_addr(ptw_io_requestor_0_pmp_5_addr),
    .io_requestor_0_pmp_5_mask(ptw_io_requestor_0_pmp_5_mask),
    .io_requestor_0_pmp_6_cfg_l(ptw_io_requestor_0_pmp_6_cfg_l),
    .io_requestor_0_pmp_6_cfg_a(ptw_io_requestor_0_pmp_6_cfg_a),
    .io_requestor_0_pmp_6_cfg_x(ptw_io_requestor_0_pmp_6_cfg_x),
    .io_requestor_0_pmp_6_cfg_w(ptw_io_requestor_0_pmp_6_cfg_w),
    .io_requestor_0_pmp_6_cfg_r(ptw_io_requestor_0_pmp_6_cfg_r),
    .io_requestor_0_pmp_6_addr(ptw_io_requestor_0_pmp_6_addr),
    .io_requestor_0_pmp_6_mask(ptw_io_requestor_0_pmp_6_mask),
    .io_requestor_0_pmp_7_cfg_l(ptw_io_requestor_0_pmp_7_cfg_l),
    .io_requestor_0_pmp_7_cfg_a(ptw_io_requestor_0_pmp_7_cfg_a),
    .io_requestor_0_pmp_7_cfg_x(ptw_io_requestor_0_pmp_7_cfg_x),
    .io_requestor_0_pmp_7_cfg_w(ptw_io_requestor_0_pmp_7_cfg_w),
    .io_requestor_0_pmp_7_cfg_r(ptw_io_requestor_0_pmp_7_cfg_r),
    .io_requestor_0_pmp_7_addr(ptw_io_requestor_0_pmp_7_addr),
    .io_requestor_0_pmp_7_mask(ptw_io_requestor_0_pmp_7_mask),
    .io_requestor_1_status_debug(ptw_io_requestor_1_status_debug),
    .io_requestor_1_status_prv(ptw_io_requestor_1_status_prv),
    .io_requestor_1_pmp_0_cfg_l(ptw_io_requestor_1_pmp_0_cfg_l),
    .io_requestor_1_pmp_0_cfg_a(ptw_io_requestor_1_pmp_0_cfg_a),
    .io_requestor_1_pmp_0_cfg_x(ptw_io_requestor_1_pmp_0_cfg_x),
    .io_requestor_1_pmp_0_cfg_w(ptw_io_requestor_1_pmp_0_cfg_w),
    .io_requestor_1_pmp_0_cfg_r(ptw_io_requestor_1_pmp_0_cfg_r),
    .io_requestor_1_pmp_0_addr(ptw_io_requestor_1_pmp_0_addr),
    .io_requestor_1_pmp_0_mask(ptw_io_requestor_1_pmp_0_mask),
    .io_requestor_1_pmp_1_cfg_l(ptw_io_requestor_1_pmp_1_cfg_l),
    .io_requestor_1_pmp_1_cfg_a(ptw_io_requestor_1_pmp_1_cfg_a),
    .io_requestor_1_pmp_1_cfg_x(ptw_io_requestor_1_pmp_1_cfg_x),
    .io_requestor_1_pmp_1_cfg_w(ptw_io_requestor_1_pmp_1_cfg_w),
    .io_requestor_1_pmp_1_cfg_r(ptw_io_requestor_1_pmp_1_cfg_r),
    .io_requestor_1_pmp_1_addr(ptw_io_requestor_1_pmp_1_addr),
    .io_requestor_1_pmp_1_mask(ptw_io_requestor_1_pmp_1_mask),
    .io_requestor_1_pmp_2_cfg_l(ptw_io_requestor_1_pmp_2_cfg_l),
    .io_requestor_1_pmp_2_cfg_a(ptw_io_requestor_1_pmp_2_cfg_a),
    .io_requestor_1_pmp_2_cfg_x(ptw_io_requestor_1_pmp_2_cfg_x),
    .io_requestor_1_pmp_2_cfg_w(ptw_io_requestor_1_pmp_2_cfg_w),
    .io_requestor_1_pmp_2_cfg_r(ptw_io_requestor_1_pmp_2_cfg_r),
    .io_requestor_1_pmp_2_addr(ptw_io_requestor_1_pmp_2_addr),
    .io_requestor_1_pmp_2_mask(ptw_io_requestor_1_pmp_2_mask),
    .io_requestor_1_pmp_3_cfg_l(ptw_io_requestor_1_pmp_3_cfg_l),
    .io_requestor_1_pmp_3_cfg_a(ptw_io_requestor_1_pmp_3_cfg_a),
    .io_requestor_1_pmp_3_cfg_x(ptw_io_requestor_1_pmp_3_cfg_x),
    .io_requestor_1_pmp_3_cfg_w(ptw_io_requestor_1_pmp_3_cfg_w),
    .io_requestor_1_pmp_3_cfg_r(ptw_io_requestor_1_pmp_3_cfg_r),
    .io_requestor_1_pmp_3_addr(ptw_io_requestor_1_pmp_3_addr),
    .io_requestor_1_pmp_3_mask(ptw_io_requestor_1_pmp_3_mask),
    .io_requestor_1_pmp_4_cfg_l(ptw_io_requestor_1_pmp_4_cfg_l),
    .io_requestor_1_pmp_4_cfg_a(ptw_io_requestor_1_pmp_4_cfg_a),
    .io_requestor_1_pmp_4_cfg_x(ptw_io_requestor_1_pmp_4_cfg_x),
    .io_requestor_1_pmp_4_cfg_w(ptw_io_requestor_1_pmp_4_cfg_w),
    .io_requestor_1_pmp_4_cfg_r(ptw_io_requestor_1_pmp_4_cfg_r),
    .io_requestor_1_pmp_4_addr(ptw_io_requestor_1_pmp_4_addr),
    .io_requestor_1_pmp_4_mask(ptw_io_requestor_1_pmp_4_mask),
    .io_requestor_1_pmp_5_cfg_l(ptw_io_requestor_1_pmp_5_cfg_l),
    .io_requestor_1_pmp_5_cfg_a(ptw_io_requestor_1_pmp_5_cfg_a),
    .io_requestor_1_pmp_5_cfg_x(ptw_io_requestor_1_pmp_5_cfg_x),
    .io_requestor_1_pmp_5_cfg_w(ptw_io_requestor_1_pmp_5_cfg_w),
    .io_requestor_1_pmp_5_cfg_r(ptw_io_requestor_1_pmp_5_cfg_r),
    .io_requestor_1_pmp_5_addr(ptw_io_requestor_1_pmp_5_addr),
    .io_requestor_1_pmp_5_mask(ptw_io_requestor_1_pmp_5_mask),
    .io_requestor_1_pmp_6_cfg_l(ptw_io_requestor_1_pmp_6_cfg_l),
    .io_requestor_1_pmp_6_cfg_a(ptw_io_requestor_1_pmp_6_cfg_a),
    .io_requestor_1_pmp_6_cfg_x(ptw_io_requestor_1_pmp_6_cfg_x),
    .io_requestor_1_pmp_6_cfg_w(ptw_io_requestor_1_pmp_6_cfg_w),
    .io_requestor_1_pmp_6_cfg_r(ptw_io_requestor_1_pmp_6_cfg_r),
    .io_requestor_1_pmp_6_addr(ptw_io_requestor_1_pmp_6_addr),
    .io_requestor_1_pmp_6_mask(ptw_io_requestor_1_pmp_6_mask),
    .io_requestor_1_pmp_7_cfg_l(ptw_io_requestor_1_pmp_7_cfg_l),
    .io_requestor_1_pmp_7_cfg_a(ptw_io_requestor_1_pmp_7_cfg_a),
    .io_requestor_1_pmp_7_cfg_x(ptw_io_requestor_1_pmp_7_cfg_x),
    .io_requestor_1_pmp_7_cfg_w(ptw_io_requestor_1_pmp_7_cfg_w),
    .io_requestor_1_pmp_7_cfg_r(ptw_io_requestor_1_pmp_7_cfg_r),
    .io_requestor_1_pmp_7_addr(ptw_io_requestor_1_pmp_7_addr),
    .io_requestor_1_pmp_7_mask(ptw_io_requestor_1_pmp_7_mask),
    .io_requestor_1_customCSRs_csrs_0_value(ptw_io_requestor_1_customCSRs_csrs_0_value),
    .io_dpath_status_debug(ptw_io_dpath_status_debug),
    .io_dpath_status_prv(ptw_io_dpath_status_prv),
    .io_dpath_pmp_0_cfg_l(ptw_io_dpath_pmp_0_cfg_l),
    .io_dpath_pmp_0_cfg_a(ptw_io_dpath_pmp_0_cfg_a),
    .io_dpath_pmp_0_cfg_x(ptw_io_dpath_pmp_0_cfg_x),
    .io_dpath_pmp_0_cfg_w(ptw_io_dpath_pmp_0_cfg_w),
    .io_dpath_pmp_0_cfg_r(ptw_io_dpath_pmp_0_cfg_r),
    .io_dpath_pmp_0_addr(ptw_io_dpath_pmp_0_addr),
    .io_dpath_pmp_0_mask(ptw_io_dpath_pmp_0_mask),
    .io_dpath_pmp_1_cfg_l(ptw_io_dpath_pmp_1_cfg_l),
    .io_dpath_pmp_1_cfg_a(ptw_io_dpath_pmp_1_cfg_a),
    .io_dpath_pmp_1_cfg_x(ptw_io_dpath_pmp_1_cfg_x),
    .io_dpath_pmp_1_cfg_w(ptw_io_dpath_pmp_1_cfg_w),
    .io_dpath_pmp_1_cfg_r(ptw_io_dpath_pmp_1_cfg_r),
    .io_dpath_pmp_1_addr(ptw_io_dpath_pmp_1_addr),
    .io_dpath_pmp_1_mask(ptw_io_dpath_pmp_1_mask),
    .io_dpath_pmp_2_cfg_l(ptw_io_dpath_pmp_2_cfg_l),
    .io_dpath_pmp_2_cfg_a(ptw_io_dpath_pmp_2_cfg_a),
    .io_dpath_pmp_2_cfg_x(ptw_io_dpath_pmp_2_cfg_x),
    .io_dpath_pmp_2_cfg_w(ptw_io_dpath_pmp_2_cfg_w),
    .io_dpath_pmp_2_cfg_r(ptw_io_dpath_pmp_2_cfg_r),
    .io_dpath_pmp_2_addr(ptw_io_dpath_pmp_2_addr),
    .io_dpath_pmp_2_mask(ptw_io_dpath_pmp_2_mask),
    .io_dpath_pmp_3_cfg_l(ptw_io_dpath_pmp_3_cfg_l),
    .io_dpath_pmp_3_cfg_a(ptw_io_dpath_pmp_3_cfg_a),
    .io_dpath_pmp_3_cfg_x(ptw_io_dpath_pmp_3_cfg_x),
    .io_dpath_pmp_3_cfg_w(ptw_io_dpath_pmp_3_cfg_w),
    .io_dpath_pmp_3_cfg_r(ptw_io_dpath_pmp_3_cfg_r),
    .io_dpath_pmp_3_addr(ptw_io_dpath_pmp_3_addr),
    .io_dpath_pmp_3_mask(ptw_io_dpath_pmp_3_mask),
    .io_dpath_pmp_4_cfg_l(ptw_io_dpath_pmp_4_cfg_l),
    .io_dpath_pmp_4_cfg_a(ptw_io_dpath_pmp_4_cfg_a),
    .io_dpath_pmp_4_cfg_x(ptw_io_dpath_pmp_4_cfg_x),
    .io_dpath_pmp_4_cfg_w(ptw_io_dpath_pmp_4_cfg_w),
    .io_dpath_pmp_4_cfg_r(ptw_io_dpath_pmp_4_cfg_r),
    .io_dpath_pmp_4_addr(ptw_io_dpath_pmp_4_addr),
    .io_dpath_pmp_4_mask(ptw_io_dpath_pmp_4_mask),
    .io_dpath_pmp_5_cfg_l(ptw_io_dpath_pmp_5_cfg_l),
    .io_dpath_pmp_5_cfg_a(ptw_io_dpath_pmp_5_cfg_a),
    .io_dpath_pmp_5_cfg_x(ptw_io_dpath_pmp_5_cfg_x),
    .io_dpath_pmp_5_cfg_w(ptw_io_dpath_pmp_5_cfg_w),
    .io_dpath_pmp_5_cfg_r(ptw_io_dpath_pmp_5_cfg_r),
    .io_dpath_pmp_5_addr(ptw_io_dpath_pmp_5_addr),
    .io_dpath_pmp_5_mask(ptw_io_dpath_pmp_5_mask),
    .io_dpath_pmp_6_cfg_l(ptw_io_dpath_pmp_6_cfg_l),
    .io_dpath_pmp_6_cfg_a(ptw_io_dpath_pmp_6_cfg_a),
    .io_dpath_pmp_6_cfg_x(ptw_io_dpath_pmp_6_cfg_x),
    .io_dpath_pmp_6_cfg_w(ptw_io_dpath_pmp_6_cfg_w),
    .io_dpath_pmp_6_cfg_r(ptw_io_dpath_pmp_6_cfg_r),
    .io_dpath_pmp_6_addr(ptw_io_dpath_pmp_6_addr),
    .io_dpath_pmp_6_mask(ptw_io_dpath_pmp_6_mask),
    .io_dpath_pmp_7_cfg_l(ptw_io_dpath_pmp_7_cfg_l),
    .io_dpath_pmp_7_cfg_a(ptw_io_dpath_pmp_7_cfg_a),
    .io_dpath_pmp_7_cfg_x(ptw_io_dpath_pmp_7_cfg_x),
    .io_dpath_pmp_7_cfg_w(ptw_io_dpath_pmp_7_cfg_w),
    .io_dpath_pmp_7_cfg_r(ptw_io_dpath_pmp_7_cfg_r),
    .io_dpath_pmp_7_addr(ptw_io_dpath_pmp_7_addr),
    .io_dpath_pmp_7_mask(ptw_io_dpath_pmp_7_mask),
    .io_dpath_perf_l2hit(ptw_io_dpath_perf_l2hit),
    .io_dpath_perf_pte_miss(ptw_io_dpath_perf_pte_miss),
    .io_dpath_perf_pte_hit(ptw_io_dpath_perf_pte_hit),
    .io_dpath_customCSRs_csrs_0_value(ptw_io_dpath_customCSRs_csrs_0_value)
  );
  Rocket core ( // @[RocketTile.scala 140:20]
    .clock(core_clock),
    .reset(core_reset),
    .io_hartid(core_io_hartid),
    .io_interrupts_debug(core_io_interrupts_debug),
    .io_interrupts_mtip(core_io_interrupts_mtip),
    .io_interrupts_msip(core_io_interrupts_msip),
    .io_interrupts_meip(core_io_interrupts_meip),
    .io_interrupts_seip(core_io_interrupts_seip),
    .io_imem_might_request(core_io_imem_might_request),
    .io_imem_req_valid(core_io_imem_req_valid),
    .io_imem_req_bits_pc(core_io_imem_req_bits_pc),
    .io_imem_req_bits_speculative(core_io_imem_req_bits_speculative),
    .io_imem_resp_ready(core_io_imem_resp_ready),
    .io_imem_resp_valid(core_io_imem_resp_valid),
    .io_imem_resp_bits_btb_taken(core_io_imem_resp_bits_btb_taken),
    .io_imem_resp_bits_btb_bridx(core_io_imem_resp_bits_btb_bridx),
    .io_imem_resp_bits_btb_entry(core_io_imem_resp_bits_btb_entry),
    .io_imem_resp_bits_btb_bht_history(core_io_imem_resp_bits_btb_bht_history),
    .io_imem_resp_bits_pc(core_io_imem_resp_bits_pc),
    .io_imem_resp_bits_data(core_io_imem_resp_bits_data),
    .io_imem_resp_bits_xcpt_ae_inst(core_io_imem_resp_bits_xcpt_ae_inst),
    .io_imem_resp_bits_replay(core_io_imem_resp_bits_replay),
    .io_imem_btb_update_valid(core_io_imem_btb_update_valid),
    .io_imem_btb_update_bits_prediction_entry(core_io_imem_btb_update_bits_prediction_entry),
    .io_imem_btb_update_bits_pc(core_io_imem_btb_update_bits_pc),
    .io_imem_btb_update_bits_isValid(core_io_imem_btb_update_bits_isValid),
    .io_imem_btb_update_bits_br_pc(core_io_imem_btb_update_bits_br_pc),
    .io_imem_btb_update_bits_cfiType(core_io_imem_btb_update_bits_cfiType),
    .io_imem_bht_update_valid(core_io_imem_bht_update_valid),
    .io_imem_bht_update_bits_prediction_history(core_io_imem_bht_update_bits_prediction_history),
    .io_imem_bht_update_bits_pc(core_io_imem_bht_update_bits_pc),
    .io_imem_bht_update_bits_branch(core_io_imem_bht_update_bits_branch),
    .io_imem_bht_update_bits_taken(core_io_imem_bht_update_bits_taken),
    .io_imem_bht_update_bits_mispredict(core_io_imem_bht_update_bits_mispredict),
    .io_imem_flush_icache(core_io_imem_flush_icache),
    .io_dmem_req_ready(core_io_dmem_req_ready),
    .io_dmem_req_valid(core_io_dmem_req_valid),
    .io_dmem_req_bits_addr(core_io_dmem_req_bits_addr),
    .io_dmem_req_bits_tag(core_io_dmem_req_bits_tag),
    .io_dmem_req_bits_cmd(core_io_dmem_req_bits_cmd),
    .io_dmem_req_bits_size(core_io_dmem_req_bits_size),
    .io_dmem_req_bits_signed(core_io_dmem_req_bits_signed),
    .io_dmem_req_bits_dprv(core_io_dmem_req_bits_dprv),
    .io_dmem_req_bits_dv(core_io_dmem_req_bits_dv),
    .io_dmem_s1_kill(core_io_dmem_s1_kill),
    .io_dmem_s1_data_data(core_io_dmem_s1_data_data),
    .io_dmem_s2_nack(core_io_dmem_s2_nack),
    .io_dmem_resp_valid(core_io_dmem_resp_valid),
    .io_dmem_resp_bits_tag(core_io_dmem_resp_bits_tag),
    .io_dmem_resp_bits_data(core_io_dmem_resp_bits_data),
    .io_dmem_resp_bits_replay(core_io_dmem_resp_bits_replay),
    .io_dmem_resp_bits_has_data(core_io_dmem_resp_bits_has_data),
    .io_dmem_resp_bits_data_word_bypass(core_io_dmem_resp_bits_data_word_bypass),
    .io_dmem_replay_next(core_io_dmem_replay_next),
    .io_dmem_s2_xcpt_ma_ld(core_io_dmem_s2_xcpt_ma_ld),
    .io_dmem_s2_xcpt_ma_st(core_io_dmem_s2_xcpt_ma_st),
    .io_dmem_s2_xcpt_pf_ld(core_io_dmem_s2_xcpt_pf_ld),
    .io_dmem_s2_xcpt_pf_st(core_io_dmem_s2_xcpt_pf_st),
    .io_dmem_s2_xcpt_ae_ld(core_io_dmem_s2_xcpt_ae_ld),
    .io_dmem_s2_xcpt_ae_st(core_io_dmem_s2_xcpt_ae_st),
    .io_dmem_ordered(core_io_dmem_ordered),
    .io_dmem_perf_release(core_io_dmem_perf_release),
    .io_dmem_perf_grant(core_io_dmem_perf_grant),
    .io_ptw_status_debug(core_io_ptw_status_debug),
    .io_ptw_status_prv(core_io_ptw_status_prv),
    .io_ptw_pmp_0_cfg_l(core_io_ptw_pmp_0_cfg_l),
    .io_ptw_pmp_0_cfg_a(core_io_ptw_pmp_0_cfg_a),
    .io_ptw_pmp_0_cfg_x(core_io_ptw_pmp_0_cfg_x),
    .io_ptw_pmp_0_cfg_w(core_io_ptw_pmp_0_cfg_w),
    .io_ptw_pmp_0_cfg_r(core_io_ptw_pmp_0_cfg_r),
    .io_ptw_pmp_0_addr(core_io_ptw_pmp_0_addr),
    .io_ptw_pmp_0_mask(core_io_ptw_pmp_0_mask),
    .io_ptw_pmp_1_cfg_l(core_io_ptw_pmp_1_cfg_l),
    .io_ptw_pmp_1_cfg_a(core_io_ptw_pmp_1_cfg_a),
    .io_ptw_pmp_1_cfg_x(core_io_ptw_pmp_1_cfg_x),
    .io_ptw_pmp_1_cfg_w(core_io_ptw_pmp_1_cfg_w),
    .io_ptw_pmp_1_cfg_r(core_io_ptw_pmp_1_cfg_r),
    .io_ptw_pmp_1_addr(core_io_ptw_pmp_1_addr),
    .io_ptw_pmp_1_mask(core_io_ptw_pmp_1_mask),
    .io_ptw_pmp_2_cfg_l(core_io_ptw_pmp_2_cfg_l),
    .io_ptw_pmp_2_cfg_a(core_io_ptw_pmp_2_cfg_a),
    .io_ptw_pmp_2_cfg_x(core_io_ptw_pmp_2_cfg_x),
    .io_ptw_pmp_2_cfg_w(core_io_ptw_pmp_2_cfg_w),
    .io_ptw_pmp_2_cfg_r(core_io_ptw_pmp_2_cfg_r),
    .io_ptw_pmp_2_addr(core_io_ptw_pmp_2_addr),
    .io_ptw_pmp_2_mask(core_io_ptw_pmp_2_mask),
    .io_ptw_pmp_3_cfg_l(core_io_ptw_pmp_3_cfg_l),
    .io_ptw_pmp_3_cfg_a(core_io_ptw_pmp_3_cfg_a),
    .io_ptw_pmp_3_cfg_x(core_io_ptw_pmp_3_cfg_x),
    .io_ptw_pmp_3_cfg_w(core_io_ptw_pmp_3_cfg_w),
    .io_ptw_pmp_3_cfg_r(core_io_ptw_pmp_3_cfg_r),
    .io_ptw_pmp_3_addr(core_io_ptw_pmp_3_addr),
    .io_ptw_pmp_3_mask(core_io_ptw_pmp_3_mask),
    .io_ptw_pmp_4_cfg_l(core_io_ptw_pmp_4_cfg_l),
    .io_ptw_pmp_4_cfg_a(core_io_ptw_pmp_4_cfg_a),
    .io_ptw_pmp_4_cfg_x(core_io_ptw_pmp_4_cfg_x),
    .io_ptw_pmp_4_cfg_w(core_io_ptw_pmp_4_cfg_w),
    .io_ptw_pmp_4_cfg_r(core_io_ptw_pmp_4_cfg_r),
    .io_ptw_pmp_4_addr(core_io_ptw_pmp_4_addr),
    .io_ptw_pmp_4_mask(core_io_ptw_pmp_4_mask),
    .io_ptw_pmp_5_cfg_l(core_io_ptw_pmp_5_cfg_l),
    .io_ptw_pmp_5_cfg_a(core_io_ptw_pmp_5_cfg_a),
    .io_ptw_pmp_5_cfg_x(core_io_ptw_pmp_5_cfg_x),
    .io_ptw_pmp_5_cfg_w(core_io_ptw_pmp_5_cfg_w),
    .io_ptw_pmp_5_cfg_r(core_io_ptw_pmp_5_cfg_r),
    .io_ptw_pmp_5_addr(core_io_ptw_pmp_5_addr),
    .io_ptw_pmp_5_mask(core_io_ptw_pmp_5_mask),
    .io_ptw_pmp_6_cfg_l(core_io_ptw_pmp_6_cfg_l),
    .io_ptw_pmp_6_cfg_a(core_io_ptw_pmp_6_cfg_a),
    .io_ptw_pmp_6_cfg_x(core_io_ptw_pmp_6_cfg_x),
    .io_ptw_pmp_6_cfg_w(core_io_ptw_pmp_6_cfg_w),
    .io_ptw_pmp_6_cfg_r(core_io_ptw_pmp_6_cfg_r),
    .io_ptw_pmp_6_addr(core_io_ptw_pmp_6_addr),
    .io_ptw_pmp_6_mask(core_io_ptw_pmp_6_mask),
    .io_ptw_pmp_7_cfg_l(core_io_ptw_pmp_7_cfg_l),
    .io_ptw_pmp_7_cfg_a(core_io_ptw_pmp_7_cfg_a),
    .io_ptw_pmp_7_cfg_x(core_io_ptw_pmp_7_cfg_x),
    .io_ptw_pmp_7_cfg_w(core_io_ptw_pmp_7_cfg_w),
    .io_ptw_pmp_7_cfg_r(core_io_ptw_pmp_7_cfg_r),
    .io_ptw_pmp_7_addr(core_io_ptw_pmp_7_addr),
    .io_ptw_pmp_7_mask(core_io_ptw_pmp_7_mask),
    .io_ptw_customCSRs_csrs_0_value(core_io_ptw_customCSRs_csrs_0_value),
    .io_wfi(core_io_wfi)
  );
  assign auto_slave_in_a_ready = tlSlaveXbar_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_slave_in_d_valid = tlSlaveXbar_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_slave_in_d_bits_opcode = tlSlaveXbar_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_slave_in_d_bits_size = tlSlaveXbar_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_slave_in_d_bits_source = tlSlaveXbar_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_slave_in_d_bits_data = tlSlaveXbar_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_wfi_out_0 = bundleOut_0_0_REG; // @[Nodes.scala 1207:84 Interrupts.scala 126:12]
  assign auto_tl_other_masters_out_a_valid = tlMasterXbar_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_other_masters_out_a_bits_opcode = tlMasterXbar_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_other_masters_out_a_bits_param = tlMasterXbar_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_other_masters_out_a_bits_size = tlMasterXbar_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_other_masters_out_a_bits_source = tlMasterXbar_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_other_masters_out_a_bits_address = tlMasterXbar_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_other_masters_out_a_bits_mask = tlMasterXbar_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_other_masters_out_a_bits_data = tlMasterXbar_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_other_masters_out_b_ready = tlMasterXbar_auto_out_b_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_other_masters_out_c_valid = tlMasterXbar_auto_out_c_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_other_masters_out_c_bits_opcode = tlMasterXbar_auto_out_c_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_other_masters_out_c_bits_param = tlMasterXbar_auto_out_c_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_other_masters_out_c_bits_size = tlMasterXbar_auto_out_c_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_other_masters_out_c_bits_source = tlMasterXbar_auto_out_c_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_other_masters_out_c_bits_address = tlMasterXbar_auto_out_c_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_other_masters_out_c_bits_data = tlMasterXbar_auto_out_c_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_other_masters_out_d_ready = tlMasterXbar_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_other_masters_out_e_valid = tlMasterXbar_auto_out_e_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_other_masters_out_e_bits_sink = tlMasterXbar_auto_out_e_bits_sink; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign tlMasterXbar_clock = clock;
  assign tlMasterXbar_reset = reset;
  assign tlMasterXbar_auto_in_1_a_valid = frontend_auto_icache_master_out_a_valid; // @[LazyModule.scala 296:16]
  assign tlMasterXbar_auto_in_1_a_bits_address = frontend_auto_icache_master_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign tlMasterXbar_auto_in_1_d_ready = frontend_auto_icache_master_out_d_ready; // @[LazyModule.scala 296:16]
  assign tlMasterXbar_auto_in_0_a_valid = dcache_auto_out_a_valid; // @[LazyModule.scala 296:16]
  assign tlMasterXbar_auto_in_0_a_bits_opcode = dcache_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign tlMasterXbar_auto_in_0_a_bits_param = dcache_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
  assign tlMasterXbar_auto_in_0_a_bits_size = dcache_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign tlMasterXbar_auto_in_0_a_bits_source = dcache_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign tlMasterXbar_auto_in_0_a_bits_address = dcache_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign tlMasterXbar_auto_in_0_a_bits_mask = dcache_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign tlMasterXbar_auto_in_0_a_bits_data = dcache_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign tlMasterXbar_auto_in_0_b_ready = dcache_auto_out_b_ready; // @[LazyModule.scala 296:16]
  assign tlMasterXbar_auto_in_0_c_valid = dcache_auto_out_c_valid; // @[LazyModule.scala 296:16]
  assign tlMasterXbar_auto_in_0_c_bits_opcode = dcache_auto_out_c_bits_opcode; // @[LazyModule.scala 296:16]
  assign tlMasterXbar_auto_in_0_c_bits_param = dcache_auto_out_c_bits_param; // @[LazyModule.scala 296:16]
  assign tlMasterXbar_auto_in_0_c_bits_size = dcache_auto_out_c_bits_size; // @[LazyModule.scala 296:16]
  assign tlMasterXbar_auto_in_0_c_bits_source = dcache_auto_out_c_bits_source; // @[LazyModule.scala 296:16]
  assign tlMasterXbar_auto_in_0_c_bits_address = dcache_auto_out_c_bits_address; // @[LazyModule.scala 296:16]
  assign tlMasterXbar_auto_in_0_c_bits_data = dcache_auto_out_c_bits_data; // @[LazyModule.scala 296:16]
  assign tlMasterXbar_auto_in_0_d_ready = dcache_auto_out_d_ready; // @[LazyModule.scala 296:16]
  assign tlMasterXbar_auto_in_0_e_valid = dcache_auto_out_e_valid; // @[LazyModule.scala 296:16]
  assign tlMasterXbar_auto_in_0_e_bits_sink = dcache_auto_out_e_bits_sink; // @[LazyModule.scala 296:16]
  assign tlMasterXbar_auto_out_a_ready = auto_tl_other_masters_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign tlMasterXbar_auto_out_b_valid = auto_tl_other_masters_out_b_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign tlMasterXbar_auto_out_b_bits_opcode = auto_tl_other_masters_out_b_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign tlMasterXbar_auto_out_b_bits_param = auto_tl_other_masters_out_b_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign tlMasterXbar_auto_out_b_bits_size = auto_tl_other_masters_out_b_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign tlMasterXbar_auto_out_b_bits_source = auto_tl_other_masters_out_b_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign tlMasterXbar_auto_out_b_bits_address = auto_tl_other_masters_out_b_bits_address; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign tlMasterXbar_auto_out_b_bits_mask = auto_tl_other_masters_out_b_bits_mask; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign tlMasterXbar_auto_out_b_bits_corrupt = auto_tl_other_masters_out_b_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign tlMasterXbar_auto_out_c_ready = auto_tl_other_masters_out_c_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign tlMasterXbar_auto_out_d_valid = auto_tl_other_masters_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign tlMasterXbar_auto_out_d_bits_opcode = auto_tl_other_masters_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign tlMasterXbar_auto_out_d_bits_param = auto_tl_other_masters_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign tlMasterXbar_auto_out_d_bits_size = auto_tl_other_masters_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign tlMasterXbar_auto_out_d_bits_source = auto_tl_other_masters_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign tlMasterXbar_auto_out_d_bits_sink = auto_tl_other_masters_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign tlMasterXbar_auto_out_d_bits_denied = auto_tl_other_masters_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign tlMasterXbar_auto_out_d_bits_data = auto_tl_other_masters_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign tlMasterXbar_auto_out_d_bits_corrupt = auto_tl_other_masters_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign tlMasterXbar_auto_out_e_ready = auto_tl_other_masters_out_e_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign tlSlaveXbar_auto_in_a_valid = auto_slave_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign tlSlaveXbar_auto_in_a_bits_opcode = auto_slave_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign tlSlaveXbar_auto_in_a_bits_param = auto_slave_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign tlSlaveXbar_auto_in_a_bits_size = auto_slave_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign tlSlaveXbar_auto_in_a_bits_source = auto_slave_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign tlSlaveXbar_auto_in_a_bits_address = auto_slave_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign tlSlaveXbar_auto_in_a_bits_mask = auto_slave_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign tlSlaveXbar_auto_in_a_bits_data = auto_slave_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign tlSlaveXbar_auto_in_a_bits_corrupt = auto_slave_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign tlSlaveXbar_auto_in_d_ready = auto_slave_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign tlSlaveXbar_auto_out_a_ready = fragmenter_auto_in_a_ready; // @[LazyModule.scala 298:16]
  assign tlSlaveXbar_auto_out_d_valid = fragmenter_auto_in_d_valid; // @[LazyModule.scala 298:16]
  assign tlSlaveXbar_auto_out_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign tlSlaveXbar_auto_out_d_bits_size = fragmenter_auto_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign tlSlaveXbar_auto_out_d_bits_source = fragmenter_auto_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign tlSlaveXbar_auto_out_d_bits_data = fragmenter_auto_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign intXbar_auto_int_in_3_0 = auto_int_local_in_3_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign intXbar_auto_int_in_2_0 = auto_int_local_in_2_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign intXbar_auto_int_in_1_0 = auto_int_local_in_1_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign intXbar_auto_int_in_1_1 = auto_int_local_in_1_1; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign intXbar_auto_int_in_0_0 = auto_int_local_in_0_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign broadcast_auto_in = auto_hartid_in; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign dcache_clock = clock;
  assign dcache_reset = reset;
  assign dcache_auto_out_a_ready = tlMasterXbar_auto_in_0_a_ready; // @[LazyModule.scala 296:16]
  assign dcache_auto_out_b_valid = tlMasterXbar_auto_in_0_b_valid; // @[LazyModule.scala 296:16]
  assign dcache_auto_out_b_bits_param = tlMasterXbar_auto_in_0_b_bits_param; // @[LazyModule.scala 296:16]
  assign dcache_auto_out_b_bits_size = tlMasterXbar_auto_in_0_b_bits_size; // @[LazyModule.scala 296:16]
  assign dcache_auto_out_b_bits_source = tlMasterXbar_auto_in_0_b_bits_source; // @[LazyModule.scala 296:16]
  assign dcache_auto_out_b_bits_address = tlMasterXbar_auto_in_0_b_bits_address; // @[LazyModule.scala 296:16]
  assign dcache_auto_out_c_ready = tlMasterXbar_auto_in_0_c_ready; // @[LazyModule.scala 296:16]
  assign dcache_auto_out_d_valid = tlMasterXbar_auto_in_0_d_valid; // @[LazyModule.scala 296:16]
  assign dcache_auto_out_d_bits_opcode = tlMasterXbar_auto_in_0_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign dcache_auto_out_d_bits_param = tlMasterXbar_auto_in_0_d_bits_param; // @[LazyModule.scala 296:16]
  assign dcache_auto_out_d_bits_size = tlMasterXbar_auto_in_0_d_bits_size; // @[LazyModule.scala 296:16]
  assign dcache_auto_out_d_bits_source = tlMasterXbar_auto_in_0_d_bits_source; // @[LazyModule.scala 296:16]
  assign dcache_auto_out_d_bits_sink = tlMasterXbar_auto_in_0_d_bits_sink; // @[LazyModule.scala 296:16]
  assign dcache_auto_out_d_bits_denied = tlMasterXbar_auto_in_0_d_bits_denied; // @[LazyModule.scala 296:16]
  assign dcache_auto_out_d_bits_data = tlMasterXbar_auto_in_0_d_bits_data; // @[LazyModule.scala 296:16]
  assign dcache_auto_out_e_ready = tlMasterXbar_auto_in_0_e_ready; // @[LazyModule.scala 296:16]
  assign dcache_io_cpu_req_valid = dcacheArb_io_mem_req_valid; // @[HellaCache.scala 281:30]
  assign dcache_io_cpu_req_bits_addr = dcacheArb_io_mem_req_bits_addr; // @[HellaCache.scala 281:30]
  assign dcache_io_cpu_req_bits_tag = dcacheArb_io_mem_req_bits_tag; // @[HellaCache.scala 281:30]
  assign dcache_io_cpu_req_bits_cmd = dcacheArb_io_mem_req_bits_cmd; // @[HellaCache.scala 281:30]
  assign dcache_io_cpu_req_bits_size = dcacheArb_io_mem_req_bits_size; // @[HellaCache.scala 281:30]
  assign dcache_io_cpu_req_bits_signed = dcacheArb_io_mem_req_bits_signed; // @[HellaCache.scala 281:30]
  assign dcache_io_cpu_req_bits_dprv = dcacheArb_io_mem_req_bits_dprv; // @[HellaCache.scala 281:30]
  assign dcache_io_cpu_s1_kill = dcacheArb_io_mem_s1_kill; // @[HellaCache.scala 281:30]
  assign dcache_io_cpu_s1_data_data = dcacheArb_io_mem_s1_data_data; // @[HellaCache.scala 281:30]
  assign dcache_io_cpu_s1_data_mask = 4'h0; // @[HellaCache.scala 281:30]
  assign dcache_io_ptw_status_debug = ptw_io_requestor_0_status_debug; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_0_cfg_l = ptw_io_requestor_0_pmp_0_cfg_l; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_0_cfg_a = ptw_io_requestor_0_pmp_0_cfg_a; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_0_cfg_x = ptw_io_requestor_0_pmp_0_cfg_x; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_0_cfg_w = ptw_io_requestor_0_pmp_0_cfg_w; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_0_cfg_r = ptw_io_requestor_0_pmp_0_cfg_r; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_0_addr = ptw_io_requestor_0_pmp_0_addr; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_0_mask = ptw_io_requestor_0_pmp_0_mask; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_1_cfg_l = ptw_io_requestor_0_pmp_1_cfg_l; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_1_cfg_a = ptw_io_requestor_0_pmp_1_cfg_a; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_1_cfg_x = ptw_io_requestor_0_pmp_1_cfg_x; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_1_cfg_w = ptw_io_requestor_0_pmp_1_cfg_w; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_1_cfg_r = ptw_io_requestor_0_pmp_1_cfg_r; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_1_addr = ptw_io_requestor_0_pmp_1_addr; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_1_mask = ptw_io_requestor_0_pmp_1_mask; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_2_cfg_l = ptw_io_requestor_0_pmp_2_cfg_l; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_2_cfg_a = ptw_io_requestor_0_pmp_2_cfg_a; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_2_cfg_x = ptw_io_requestor_0_pmp_2_cfg_x; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_2_cfg_w = ptw_io_requestor_0_pmp_2_cfg_w; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_2_cfg_r = ptw_io_requestor_0_pmp_2_cfg_r; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_2_addr = ptw_io_requestor_0_pmp_2_addr; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_2_mask = ptw_io_requestor_0_pmp_2_mask; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_3_cfg_l = ptw_io_requestor_0_pmp_3_cfg_l; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_3_cfg_a = ptw_io_requestor_0_pmp_3_cfg_a; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_3_cfg_x = ptw_io_requestor_0_pmp_3_cfg_x; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_3_cfg_w = ptw_io_requestor_0_pmp_3_cfg_w; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_3_cfg_r = ptw_io_requestor_0_pmp_3_cfg_r; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_3_addr = ptw_io_requestor_0_pmp_3_addr; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_3_mask = ptw_io_requestor_0_pmp_3_mask; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_4_cfg_l = ptw_io_requestor_0_pmp_4_cfg_l; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_4_cfg_a = ptw_io_requestor_0_pmp_4_cfg_a; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_4_cfg_x = ptw_io_requestor_0_pmp_4_cfg_x; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_4_cfg_w = ptw_io_requestor_0_pmp_4_cfg_w; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_4_cfg_r = ptw_io_requestor_0_pmp_4_cfg_r; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_4_addr = ptw_io_requestor_0_pmp_4_addr; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_4_mask = ptw_io_requestor_0_pmp_4_mask; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_5_cfg_l = ptw_io_requestor_0_pmp_5_cfg_l; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_5_cfg_a = ptw_io_requestor_0_pmp_5_cfg_a; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_5_cfg_x = ptw_io_requestor_0_pmp_5_cfg_x; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_5_cfg_w = ptw_io_requestor_0_pmp_5_cfg_w; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_5_cfg_r = ptw_io_requestor_0_pmp_5_cfg_r; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_5_addr = ptw_io_requestor_0_pmp_5_addr; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_5_mask = ptw_io_requestor_0_pmp_5_mask; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_6_cfg_l = ptw_io_requestor_0_pmp_6_cfg_l; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_6_cfg_a = ptw_io_requestor_0_pmp_6_cfg_a; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_6_cfg_x = ptw_io_requestor_0_pmp_6_cfg_x; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_6_cfg_w = ptw_io_requestor_0_pmp_6_cfg_w; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_6_cfg_r = ptw_io_requestor_0_pmp_6_cfg_r; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_6_addr = ptw_io_requestor_0_pmp_6_addr; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_6_mask = ptw_io_requestor_0_pmp_6_mask; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_7_cfg_l = ptw_io_requestor_0_pmp_7_cfg_l; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_7_cfg_a = ptw_io_requestor_0_pmp_7_cfg_a; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_7_cfg_x = ptw_io_requestor_0_pmp_7_cfg_x; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_7_cfg_w = ptw_io_requestor_0_pmp_7_cfg_w; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_7_cfg_r = ptw_io_requestor_0_pmp_7_cfg_r; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_7_addr = ptw_io_requestor_0_pmp_7_addr; // @[RocketTile.scala 198:20]
  assign dcache_io_ptw_pmp_7_mask = ptw_io_requestor_0_pmp_7_mask; // @[RocketTile.scala 198:20]
  assign frontend_clock = clock;
  assign frontend_reset = reset;
  assign frontend_auto_icache_slave_in_a_valid = fragmenter_auto_out_a_valid; // @[LazyModule.scala 296:16]
  assign frontend_auto_icache_slave_in_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign frontend_auto_icache_slave_in_a_bits_size = fragmenter_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign frontend_auto_icache_slave_in_a_bits_source = fragmenter_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign frontend_auto_icache_slave_in_a_bits_address = fragmenter_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign frontend_auto_icache_slave_in_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign frontend_auto_icache_slave_in_a_bits_data = fragmenter_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign frontend_auto_icache_slave_in_d_ready = fragmenter_auto_out_d_ready; // @[LazyModule.scala 296:16]
  assign frontend_auto_icache_master_out_a_ready = tlMasterXbar_auto_in_1_a_ready; // @[LazyModule.scala 296:16]
  assign frontend_auto_icache_master_out_d_valid = tlMasterXbar_auto_in_1_d_valid; // @[LazyModule.scala 296:16]
  assign frontend_auto_icache_master_out_d_bits_opcode = tlMasterXbar_auto_in_1_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign frontend_auto_icache_master_out_d_bits_size = tlMasterXbar_auto_in_1_d_bits_size; // @[LazyModule.scala 296:16]
  assign frontend_auto_icache_master_out_d_bits_data = tlMasterXbar_auto_in_1_d_bits_data; // @[LazyModule.scala 296:16]
  assign frontend_auto_icache_master_out_d_bits_corrupt = tlMasterXbar_auto_in_1_d_bits_corrupt; // @[LazyModule.scala 296:16]
  assign frontend_io_cpu_might_request = core_io_imem_might_request; // @[RocketTile.scala 173:32]
  assign frontend_io_cpu_req_valid = core_io_imem_req_valid; // @[RocketTile.scala 173:32]
  assign frontend_io_cpu_req_bits_pc = core_io_imem_req_bits_pc; // @[RocketTile.scala 173:32]
  assign frontend_io_cpu_req_bits_speculative = core_io_imem_req_bits_speculative; // @[RocketTile.scala 173:32]
  assign frontend_io_cpu_resp_ready = core_io_imem_resp_ready; // @[RocketTile.scala 173:32]
  assign frontend_io_cpu_btb_update_valid = core_io_imem_btb_update_valid; // @[RocketTile.scala 173:32]
  assign frontend_io_cpu_btb_update_bits_prediction_entry = core_io_imem_btb_update_bits_prediction_entry; // @[RocketTile.scala 173:32]
  assign frontend_io_cpu_btb_update_bits_pc = core_io_imem_btb_update_bits_pc; // @[RocketTile.scala 173:32]
  assign frontend_io_cpu_btb_update_bits_isValid = core_io_imem_btb_update_bits_isValid; // @[RocketTile.scala 173:32]
  assign frontend_io_cpu_btb_update_bits_br_pc = core_io_imem_btb_update_bits_br_pc; // @[RocketTile.scala 173:32]
  assign frontend_io_cpu_btb_update_bits_cfiType = core_io_imem_btb_update_bits_cfiType; // @[RocketTile.scala 173:32]
  assign frontend_io_cpu_bht_update_valid = core_io_imem_bht_update_valid; // @[RocketTile.scala 173:32]
  assign frontend_io_cpu_bht_update_bits_prediction_history = core_io_imem_bht_update_bits_prediction_history; // @[RocketTile.scala 173:32]
  assign frontend_io_cpu_bht_update_bits_pc = core_io_imem_bht_update_bits_pc; // @[RocketTile.scala 173:32]
  assign frontend_io_cpu_bht_update_bits_branch = core_io_imem_bht_update_bits_branch; // @[RocketTile.scala 173:32]
  assign frontend_io_cpu_bht_update_bits_taken = core_io_imem_bht_update_bits_taken; // @[RocketTile.scala 173:32]
  assign frontend_io_cpu_bht_update_bits_mispredict = core_io_imem_bht_update_bits_mispredict; // @[RocketTile.scala 173:32]
  assign frontend_io_cpu_flush_icache = core_io_imem_flush_icache; // @[RocketTile.scala 173:32]
  assign frontend_io_ptw_status_debug = ptw_io_requestor_1_status_debug; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_status_prv = ptw_io_requestor_1_status_prv; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_0_cfg_l = ptw_io_requestor_1_pmp_0_cfg_l; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_0_cfg_a = ptw_io_requestor_1_pmp_0_cfg_a; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_0_cfg_x = ptw_io_requestor_1_pmp_0_cfg_x; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_0_cfg_w = ptw_io_requestor_1_pmp_0_cfg_w; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_0_cfg_r = ptw_io_requestor_1_pmp_0_cfg_r; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_0_addr = ptw_io_requestor_1_pmp_0_addr; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_0_mask = ptw_io_requestor_1_pmp_0_mask; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_1_cfg_l = ptw_io_requestor_1_pmp_1_cfg_l; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_1_cfg_a = ptw_io_requestor_1_pmp_1_cfg_a; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_1_cfg_x = ptw_io_requestor_1_pmp_1_cfg_x; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_1_cfg_w = ptw_io_requestor_1_pmp_1_cfg_w; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_1_cfg_r = ptw_io_requestor_1_pmp_1_cfg_r; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_1_addr = ptw_io_requestor_1_pmp_1_addr; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_1_mask = ptw_io_requestor_1_pmp_1_mask; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_2_cfg_l = ptw_io_requestor_1_pmp_2_cfg_l; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_2_cfg_a = ptw_io_requestor_1_pmp_2_cfg_a; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_2_cfg_x = ptw_io_requestor_1_pmp_2_cfg_x; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_2_cfg_w = ptw_io_requestor_1_pmp_2_cfg_w; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_2_cfg_r = ptw_io_requestor_1_pmp_2_cfg_r; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_2_addr = ptw_io_requestor_1_pmp_2_addr; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_2_mask = ptw_io_requestor_1_pmp_2_mask; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_3_cfg_l = ptw_io_requestor_1_pmp_3_cfg_l; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_3_cfg_a = ptw_io_requestor_1_pmp_3_cfg_a; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_3_cfg_x = ptw_io_requestor_1_pmp_3_cfg_x; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_3_cfg_w = ptw_io_requestor_1_pmp_3_cfg_w; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_3_cfg_r = ptw_io_requestor_1_pmp_3_cfg_r; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_3_addr = ptw_io_requestor_1_pmp_3_addr; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_3_mask = ptw_io_requestor_1_pmp_3_mask; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_4_cfg_l = ptw_io_requestor_1_pmp_4_cfg_l; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_4_cfg_a = ptw_io_requestor_1_pmp_4_cfg_a; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_4_cfg_x = ptw_io_requestor_1_pmp_4_cfg_x; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_4_cfg_w = ptw_io_requestor_1_pmp_4_cfg_w; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_4_cfg_r = ptw_io_requestor_1_pmp_4_cfg_r; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_4_addr = ptw_io_requestor_1_pmp_4_addr; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_4_mask = ptw_io_requestor_1_pmp_4_mask; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_5_cfg_l = ptw_io_requestor_1_pmp_5_cfg_l; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_5_cfg_a = ptw_io_requestor_1_pmp_5_cfg_a; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_5_cfg_x = ptw_io_requestor_1_pmp_5_cfg_x; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_5_cfg_w = ptw_io_requestor_1_pmp_5_cfg_w; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_5_cfg_r = ptw_io_requestor_1_pmp_5_cfg_r; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_5_addr = ptw_io_requestor_1_pmp_5_addr; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_5_mask = ptw_io_requestor_1_pmp_5_mask; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_6_cfg_l = ptw_io_requestor_1_pmp_6_cfg_l; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_6_cfg_a = ptw_io_requestor_1_pmp_6_cfg_a; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_6_cfg_x = ptw_io_requestor_1_pmp_6_cfg_x; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_6_cfg_w = ptw_io_requestor_1_pmp_6_cfg_w; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_6_cfg_r = ptw_io_requestor_1_pmp_6_cfg_r; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_6_addr = ptw_io_requestor_1_pmp_6_addr; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_6_mask = ptw_io_requestor_1_pmp_6_mask; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_7_cfg_l = ptw_io_requestor_1_pmp_7_cfg_l; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_7_cfg_a = ptw_io_requestor_1_pmp_7_cfg_a; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_7_cfg_x = ptw_io_requestor_1_pmp_7_cfg_x; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_7_cfg_w = ptw_io_requestor_1_pmp_7_cfg_w; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_7_cfg_r = ptw_io_requestor_1_pmp_7_cfg_r; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_7_addr = ptw_io_requestor_1_pmp_7_addr; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_pmp_7_mask = ptw_io_requestor_1_pmp_7_mask; // @[RocketTile.scala 198:20]
  assign frontend_io_ptw_customCSRs_csrs_0_value = ptw_io_requestor_1_customCSRs_csrs_0_value; // @[RocketTile.scala 198:20]
  assign fragmenter_clock = clock;
  assign fragmenter_reset = reset;
  assign fragmenter_auto_in_a_valid = tlSlaveXbar_auto_out_a_valid; // @[LazyModule.scala 298:16]
  assign fragmenter_auto_in_a_bits_opcode = tlSlaveXbar_auto_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign fragmenter_auto_in_a_bits_param = tlSlaveXbar_auto_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign fragmenter_auto_in_a_bits_size = tlSlaveXbar_auto_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign fragmenter_auto_in_a_bits_source = tlSlaveXbar_auto_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign fragmenter_auto_in_a_bits_address = tlSlaveXbar_auto_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign fragmenter_auto_in_a_bits_mask = tlSlaveXbar_auto_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign fragmenter_auto_in_a_bits_data = tlSlaveXbar_auto_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign fragmenter_auto_in_a_bits_corrupt = tlSlaveXbar_auto_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign fragmenter_auto_in_d_ready = tlSlaveXbar_auto_out_d_ready; // @[LazyModule.scala 298:16]
  assign fragmenter_auto_out_a_ready = frontend_auto_icache_slave_in_a_ready; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_out_d_valid = frontend_auto_icache_slave_in_d_valid; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_out_d_bits_opcode = frontend_auto_icache_slave_in_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_out_d_bits_size = frontend_auto_icache_slave_in_d_bits_size; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_out_d_bits_source = frontend_auto_icache_slave_in_d_bits_source; // @[LazyModule.scala 296:16]
  assign fragmenter_auto_out_d_bits_data = frontend_auto_icache_slave_in_d_bits_data; // @[LazyModule.scala 296:16]
  assign dcacheArb_io_requestor_0_req_valid = core_io_dmem_req_valid; // @[RocketTile.scala 197:26]
  assign dcacheArb_io_requestor_0_req_bits_addr = core_io_dmem_req_bits_addr; // @[RocketTile.scala 197:26]
  assign dcacheArb_io_requestor_0_req_bits_tag = core_io_dmem_req_bits_tag; // @[RocketTile.scala 197:26]
  assign dcacheArb_io_requestor_0_req_bits_cmd = core_io_dmem_req_bits_cmd; // @[RocketTile.scala 197:26]
  assign dcacheArb_io_requestor_0_req_bits_size = core_io_dmem_req_bits_size; // @[RocketTile.scala 197:26]
  assign dcacheArb_io_requestor_0_req_bits_signed = core_io_dmem_req_bits_signed; // @[RocketTile.scala 197:26]
  assign dcacheArb_io_requestor_0_req_bits_dprv = core_io_dmem_req_bits_dprv; // @[RocketTile.scala 197:26]
  assign dcacheArb_io_requestor_0_s1_kill = core_io_dmem_s1_kill; // @[RocketTile.scala 197:26]
  assign dcacheArb_io_requestor_0_s1_data_data = core_io_dmem_s1_data_data; // @[RocketTile.scala 197:26]
  assign dcacheArb_io_mem_req_ready = dcache_io_cpu_req_ready; // @[HellaCache.scala 281:30]
  assign dcacheArb_io_mem_s2_nack = dcache_io_cpu_s2_nack; // @[HellaCache.scala 281:30]
  assign dcacheArb_io_mem_resp_valid = dcache_io_cpu_resp_valid; // @[HellaCache.scala 281:30]
  assign dcacheArb_io_mem_resp_bits_tag = dcache_io_cpu_resp_bits_tag; // @[HellaCache.scala 281:30]
  assign dcacheArb_io_mem_resp_bits_data = dcache_io_cpu_resp_bits_data; // @[HellaCache.scala 281:30]
  assign dcacheArb_io_mem_resp_bits_replay = dcache_io_cpu_resp_bits_replay; // @[HellaCache.scala 281:30]
  assign dcacheArb_io_mem_resp_bits_has_data = dcache_io_cpu_resp_bits_has_data; // @[HellaCache.scala 281:30]
  assign dcacheArb_io_mem_resp_bits_data_word_bypass = dcache_io_cpu_resp_bits_data_word_bypass; // @[HellaCache.scala 281:30]
  assign dcacheArb_io_mem_replay_next = dcache_io_cpu_replay_next; // @[HellaCache.scala 281:30]
  assign dcacheArb_io_mem_s2_xcpt_ma_ld = dcache_io_cpu_s2_xcpt_ma_ld; // @[HellaCache.scala 281:30]
  assign dcacheArb_io_mem_s2_xcpt_ma_st = dcache_io_cpu_s2_xcpt_ma_st; // @[HellaCache.scala 281:30]
  assign dcacheArb_io_mem_s2_xcpt_pf_ld = dcache_io_cpu_s2_xcpt_pf_ld; // @[HellaCache.scala 281:30]
  assign dcacheArb_io_mem_s2_xcpt_pf_st = dcache_io_cpu_s2_xcpt_pf_st; // @[HellaCache.scala 281:30]
  assign dcacheArb_io_mem_s2_xcpt_ae_ld = dcache_io_cpu_s2_xcpt_ae_ld; // @[HellaCache.scala 281:30]
  assign dcacheArb_io_mem_s2_xcpt_ae_st = dcache_io_cpu_s2_xcpt_ae_st; // @[HellaCache.scala 281:30]
  assign dcacheArb_io_mem_ordered = dcache_io_cpu_ordered; // @[HellaCache.scala 281:30]
  assign dcacheArb_io_mem_perf_release = dcache_io_cpu_perf_release; // @[HellaCache.scala 281:30]
  assign dcacheArb_io_mem_perf_grant = dcache_io_cpu_perf_grant; // @[HellaCache.scala 281:30]
  assign ptw_clock = clock;
  assign ptw_reset = reset;
  assign ptw_io_dpath_status_debug = core_io_ptw_status_debug; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_status_prv = core_io_ptw_status_prv; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_0_cfg_l = core_io_ptw_pmp_0_cfg_l; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_0_cfg_a = core_io_ptw_pmp_0_cfg_a; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_0_cfg_x = core_io_ptw_pmp_0_cfg_x; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_0_cfg_w = core_io_ptw_pmp_0_cfg_w; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_0_cfg_r = core_io_ptw_pmp_0_cfg_r; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_0_addr = core_io_ptw_pmp_0_addr; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_0_mask = core_io_ptw_pmp_0_mask; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_1_cfg_l = core_io_ptw_pmp_1_cfg_l; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_1_cfg_a = core_io_ptw_pmp_1_cfg_a; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_1_cfg_x = core_io_ptw_pmp_1_cfg_x; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_1_cfg_w = core_io_ptw_pmp_1_cfg_w; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_1_cfg_r = core_io_ptw_pmp_1_cfg_r; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_1_addr = core_io_ptw_pmp_1_addr; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_1_mask = core_io_ptw_pmp_1_mask; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_2_cfg_l = core_io_ptw_pmp_2_cfg_l; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_2_cfg_a = core_io_ptw_pmp_2_cfg_a; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_2_cfg_x = core_io_ptw_pmp_2_cfg_x; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_2_cfg_w = core_io_ptw_pmp_2_cfg_w; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_2_cfg_r = core_io_ptw_pmp_2_cfg_r; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_2_addr = core_io_ptw_pmp_2_addr; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_2_mask = core_io_ptw_pmp_2_mask; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_3_cfg_l = core_io_ptw_pmp_3_cfg_l; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_3_cfg_a = core_io_ptw_pmp_3_cfg_a; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_3_cfg_x = core_io_ptw_pmp_3_cfg_x; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_3_cfg_w = core_io_ptw_pmp_3_cfg_w; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_3_cfg_r = core_io_ptw_pmp_3_cfg_r; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_3_addr = core_io_ptw_pmp_3_addr; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_3_mask = core_io_ptw_pmp_3_mask; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_4_cfg_l = core_io_ptw_pmp_4_cfg_l; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_4_cfg_a = core_io_ptw_pmp_4_cfg_a; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_4_cfg_x = core_io_ptw_pmp_4_cfg_x; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_4_cfg_w = core_io_ptw_pmp_4_cfg_w; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_4_cfg_r = core_io_ptw_pmp_4_cfg_r; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_4_addr = core_io_ptw_pmp_4_addr; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_4_mask = core_io_ptw_pmp_4_mask; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_5_cfg_l = core_io_ptw_pmp_5_cfg_l; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_5_cfg_a = core_io_ptw_pmp_5_cfg_a; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_5_cfg_x = core_io_ptw_pmp_5_cfg_x; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_5_cfg_w = core_io_ptw_pmp_5_cfg_w; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_5_cfg_r = core_io_ptw_pmp_5_cfg_r; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_5_addr = core_io_ptw_pmp_5_addr; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_5_mask = core_io_ptw_pmp_5_mask; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_6_cfg_l = core_io_ptw_pmp_6_cfg_l; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_6_cfg_a = core_io_ptw_pmp_6_cfg_a; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_6_cfg_x = core_io_ptw_pmp_6_cfg_x; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_6_cfg_w = core_io_ptw_pmp_6_cfg_w; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_6_cfg_r = core_io_ptw_pmp_6_cfg_r; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_6_addr = core_io_ptw_pmp_6_addr; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_6_mask = core_io_ptw_pmp_6_mask; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_7_cfg_l = core_io_ptw_pmp_7_cfg_l; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_7_cfg_a = core_io_ptw_pmp_7_cfg_a; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_7_cfg_x = core_io_ptw_pmp_7_cfg_x; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_7_cfg_w = core_io_ptw_pmp_7_cfg_w; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_7_cfg_r = core_io_ptw_pmp_7_cfg_r; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_7_addr = core_io_ptw_pmp_7_addr; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_pmp_7_mask = core_io_ptw_pmp_7_mask; // @[RocketTile.scala 176:15]
  assign ptw_io_dpath_customCSRs_csrs_0_value = core_io_ptw_customCSRs_csrs_0_value; // @[RocketTile.scala 176:15]
  assign core_clock = clock;
  assign core_reset = reset;
  assign core_io_hartid = broadcast_auto_out_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign core_io_interrupts_debug = intXbar_auto_int_out_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign core_io_interrupts_mtip = intXbar_auto_int_out_2; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign core_io_interrupts_msip = intXbar_auto_int_out_1; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign core_io_interrupts_meip = intXbar_auto_int_out_3; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign core_io_interrupts_seip = intXbar_auto_int_out_4; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign core_io_imem_resp_valid = frontend_io_cpu_resp_valid; // @[RocketTile.scala 173:32]
  assign core_io_imem_resp_bits_btb_taken = frontend_io_cpu_resp_bits_btb_taken; // @[RocketTile.scala 173:32]
  assign core_io_imem_resp_bits_btb_bridx = frontend_io_cpu_resp_bits_btb_bridx; // @[RocketTile.scala 173:32]
  assign core_io_imem_resp_bits_btb_entry = frontend_io_cpu_resp_bits_btb_entry; // @[RocketTile.scala 173:32]
  assign core_io_imem_resp_bits_btb_bht_history = frontend_io_cpu_resp_bits_btb_bht_history; // @[RocketTile.scala 173:32]
  assign core_io_imem_resp_bits_pc = frontend_io_cpu_resp_bits_pc; // @[RocketTile.scala 173:32]
  assign core_io_imem_resp_bits_data = frontend_io_cpu_resp_bits_data; // @[RocketTile.scala 173:32]
  assign core_io_imem_resp_bits_xcpt_ae_inst = frontend_io_cpu_resp_bits_xcpt_ae_inst; // @[RocketTile.scala 173:32]
  assign core_io_imem_resp_bits_replay = frontend_io_cpu_resp_bits_replay; // @[RocketTile.scala 173:32]
  assign core_io_dmem_req_ready = dcacheArb_io_requestor_0_req_ready; // @[RocketTile.scala 197:26]
  assign core_io_dmem_s2_nack = dcacheArb_io_requestor_0_s2_nack; // @[RocketTile.scala 197:26]
  assign core_io_dmem_resp_valid = dcacheArb_io_requestor_0_resp_valid; // @[RocketTile.scala 197:26]
  assign core_io_dmem_resp_bits_tag = dcacheArb_io_requestor_0_resp_bits_tag; // @[RocketTile.scala 197:26]
  assign core_io_dmem_resp_bits_data = dcacheArb_io_requestor_0_resp_bits_data; // @[RocketTile.scala 197:26]
  assign core_io_dmem_resp_bits_replay = dcacheArb_io_requestor_0_resp_bits_replay; // @[RocketTile.scala 197:26]
  assign core_io_dmem_resp_bits_has_data = dcacheArb_io_requestor_0_resp_bits_has_data; // @[RocketTile.scala 197:26]
  assign core_io_dmem_resp_bits_data_word_bypass = dcacheArb_io_requestor_0_resp_bits_data_word_bypass; // @[RocketTile.scala 197:26]
  assign core_io_dmem_replay_next = dcacheArb_io_requestor_0_replay_next; // @[RocketTile.scala 197:26]
  assign core_io_dmem_s2_xcpt_ma_ld = dcacheArb_io_requestor_0_s2_xcpt_ma_ld; // @[RocketTile.scala 197:26]
  assign core_io_dmem_s2_xcpt_ma_st = dcacheArb_io_requestor_0_s2_xcpt_ma_st; // @[RocketTile.scala 197:26]
  assign core_io_dmem_s2_xcpt_pf_ld = dcacheArb_io_requestor_0_s2_xcpt_pf_ld; // @[RocketTile.scala 197:26]
  assign core_io_dmem_s2_xcpt_pf_st = dcacheArb_io_requestor_0_s2_xcpt_pf_st; // @[RocketTile.scala 197:26]
  assign core_io_dmem_s2_xcpt_ae_ld = dcacheArb_io_requestor_0_s2_xcpt_ae_ld; // @[RocketTile.scala 197:26]
  assign core_io_dmem_s2_xcpt_ae_st = dcacheArb_io_requestor_0_s2_xcpt_ae_st; // @[RocketTile.scala 197:26]
  assign core_io_dmem_ordered = dcacheArb_io_requestor_0_ordered; // @[RocketTile.scala 197:26]
  assign core_io_dmem_perf_release = dcacheArb_io_requestor_0_perf_release; // @[RocketTile.scala 197:26]
  assign core_io_dmem_perf_grant = dcacheArb_io_requestor_0_perf_grant; // @[RocketTile.scala 197:26]
  always @(posedge clock) begin
    if (reset) begin // @[Interrupts.scala 126:36]
      bundleOut_0_0_REG <= 1'h0; // @[Interrupts.scala 126:36]
    end else begin
      bundleOut_0_0_REG <= core_io_wfi; // @[Interrupts.scala 126:36]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  bundleOut_0_0_REG = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TileResetDomain(
  output        auto_tile_slave_in_a_ready,
  input         auto_tile_slave_in_a_valid,
  input  [2:0]  auto_tile_slave_in_a_bits_opcode,
  input  [2:0]  auto_tile_slave_in_a_bits_param,
  input  [2:0]  auto_tile_slave_in_a_bits_size,
  input  [1:0]  auto_tile_slave_in_a_bits_source,
  input  [27:0] auto_tile_slave_in_a_bits_address,
  input  [3:0]  auto_tile_slave_in_a_bits_mask,
  input  [31:0] auto_tile_slave_in_a_bits_data,
  input         auto_tile_slave_in_a_bits_corrupt,
  input         auto_tile_slave_in_d_ready,
  output        auto_tile_slave_in_d_valid,
  output [2:0]  auto_tile_slave_in_d_bits_opcode,
  output [2:0]  auto_tile_slave_in_d_bits_size,
  output [1:0]  auto_tile_slave_in_d_bits_source,
  output [31:0] auto_tile_slave_in_d_bits_data,
  output        auto_tile_wfi_out_0,
  input         auto_tile_int_local_in_3_0,
  input         auto_tile_int_local_in_2_0,
  input         auto_tile_int_local_in_1_0,
  input         auto_tile_int_local_in_1_1,
  input         auto_tile_int_local_in_0_0,
  input         auto_tile_hartid_in,
  input         auto_tile_tl_other_masters_out_a_ready,
  output        auto_tile_tl_other_masters_out_a_valid,
  output [2:0]  auto_tile_tl_other_masters_out_a_bits_opcode,
  output [2:0]  auto_tile_tl_other_masters_out_a_bits_param,
  output [3:0]  auto_tile_tl_other_masters_out_a_bits_size,
  output [1:0]  auto_tile_tl_other_masters_out_a_bits_source,
  output [30:0] auto_tile_tl_other_masters_out_a_bits_address,
  output [3:0]  auto_tile_tl_other_masters_out_a_bits_mask,
  output [31:0] auto_tile_tl_other_masters_out_a_bits_data,
  output        auto_tile_tl_other_masters_out_b_ready,
  input         auto_tile_tl_other_masters_out_b_valid,
  input  [2:0]  auto_tile_tl_other_masters_out_b_bits_opcode,
  input  [1:0]  auto_tile_tl_other_masters_out_b_bits_param,
  input  [3:0]  auto_tile_tl_other_masters_out_b_bits_size,
  input  [1:0]  auto_tile_tl_other_masters_out_b_bits_source,
  input  [30:0] auto_tile_tl_other_masters_out_b_bits_address,
  input  [3:0]  auto_tile_tl_other_masters_out_b_bits_mask,
  input         auto_tile_tl_other_masters_out_b_bits_corrupt,
  input         auto_tile_tl_other_masters_out_c_ready,
  output        auto_tile_tl_other_masters_out_c_valid,
  output [2:0]  auto_tile_tl_other_masters_out_c_bits_opcode,
  output [2:0]  auto_tile_tl_other_masters_out_c_bits_param,
  output [3:0]  auto_tile_tl_other_masters_out_c_bits_size,
  output [1:0]  auto_tile_tl_other_masters_out_c_bits_source,
  output [30:0] auto_tile_tl_other_masters_out_c_bits_address,
  output [31:0] auto_tile_tl_other_masters_out_c_bits_data,
  output        auto_tile_tl_other_masters_out_d_ready,
  input         auto_tile_tl_other_masters_out_d_valid,
  input  [2:0]  auto_tile_tl_other_masters_out_d_bits_opcode,
  input  [1:0]  auto_tile_tl_other_masters_out_d_bits_param,
  input  [3:0]  auto_tile_tl_other_masters_out_d_bits_size,
  input  [1:0]  auto_tile_tl_other_masters_out_d_bits_source,
  input  [1:0]  auto_tile_tl_other_masters_out_d_bits_sink,
  input         auto_tile_tl_other_masters_out_d_bits_denied,
  input  [31:0] auto_tile_tl_other_masters_out_d_bits_data,
  input         auto_tile_tl_other_masters_out_d_bits_corrupt,
  input         auto_tile_tl_other_masters_out_e_ready,
  output        auto_tile_tl_other_masters_out_e_valid,
  output [1:0]  auto_tile_tl_other_masters_out_e_bits_sink,
  input         auto_clock_in_clock,
  input         auto_clock_in_reset
);
  wire  tile_clock; // @[HasTiles.scala 253:53]
  wire  tile_reset; // @[HasTiles.scala 253:53]
  wire  tile_auto_slave_in_a_ready; // @[HasTiles.scala 253:53]
  wire  tile_auto_slave_in_a_valid; // @[HasTiles.scala 253:53]
  wire [2:0] tile_auto_slave_in_a_bits_opcode; // @[HasTiles.scala 253:53]
  wire [2:0] tile_auto_slave_in_a_bits_param; // @[HasTiles.scala 253:53]
  wire [2:0] tile_auto_slave_in_a_bits_size; // @[HasTiles.scala 253:53]
  wire [1:0] tile_auto_slave_in_a_bits_source; // @[HasTiles.scala 253:53]
  wire [27:0] tile_auto_slave_in_a_bits_address; // @[HasTiles.scala 253:53]
  wire [3:0] tile_auto_slave_in_a_bits_mask; // @[HasTiles.scala 253:53]
  wire [31:0] tile_auto_slave_in_a_bits_data; // @[HasTiles.scala 253:53]
  wire  tile_auto_slave_in_a_bits_corrupt; // @[HasTiles.scala 253:53]
  wire  tile_auto_slave_in_d_ready; // @[HasTiles.scala 253:53]
  wire  tile_auto_slave_in_d_valid; // @[HasTiles.scala 253:53]
  wire [2:0] tile_auto_slave_in_d_bits_opcode; // @[HasTiles.scala 253:53]
  wire [2:0] tile_auto_slave_in_d_bits_size; // @[HasTiles.scala 253:53]
  wire [1:0] tile_auto_slave_in_d_bits_source; // @[HasTiles.scala 253:53]
  wire [31:0] tile_auto_slave_in_d_bits_data; // @[HasTiles.scala 253:53]
  wire  tile_auto_wfi_out_0; // @[HasTiles.scala 253:53]
  wire  tile_auto_int_local_in_3_0; // @[HasTiles.scala 253:53]
  wire  tile_auto_int_local_in_2_0; // @[HasTiles.scala 253:53]
  wire  tile_auto_int_local_in_1_0; // @[HasTiles.scala 253:53]
  wire  tile_auto_int_local_in_1_1; // @[HasTiles.scala 253:53]
  wire  tile_auto_int_local_in_0_0; // @[HasTiles.scala 253:53]
  wire  tile_auto_hartid_in; // @[HasTiles.scala 253:53]
  wire  tile_auto_tl_other_masters_out_a_ready; // @[HasTiles.scala 253:53]
  wire  tile_auto_tl_other_masters_out_a_valid; // @[HasTiles.scala 253:53]
  wire [2:0] tile_auto_tl_other_masters_out_a_bits_opcode; // @[HasTiles.scala 253:53]
  wire [2:0] tile_auto_tl_other_masters_out_a_bits_param; // @[HasTiles.scala 253:53]
  wire [3:0] tile_auto_tl_other_masters_out_a_bits_size; // @[HasTiles.scala 253:53]
  wire [1:0] tile_auto_tl_other_masters_out_a_bits_source; // @[HasTiles.scala 253:53]
  wire [30:0] tile_auto_tl_other_masters_out_a_bits_address; // @[HasTiles.scala 253:53]
  wire [3:0] tile_auto_tl_other_masters_out_a_bits_mask; // @[HasTiles.scala 253:53]
  wire [31:0] tile_auto_tl_other_masters_out_a_bits_data; // @[HasTiles.scala 253:53]
  wire  tile_auto_tl_other_masters_out_b_ready; // @[HasTiles.scala 253:53]
  wire  tile_auto_tl_other_masters_out_b_valid; // @[HasTiles.scala 253:53]
  wire [2:0] tile_auto_tl_other_masters_out_b_bits_opcode; // @[HasTiles.scala 253:53]
  wire [1:0] tile_auto_tl_other_masters_out_b_bits_param; // @[HasTiles.scala 253:53]
  wire [3:0] tile_auto_tl_other_masters_out_b_bits_size; // @[HasTiles.scala 253:53]
  wire [1:0] tile_auto_tl_other_masters_out_b_bits_source; // @[HasTiles.scala 253:53]
  wire [30:0] tile_auto_tl_other_masters_out_b_bits_address; // @[HasTiles.scala 253:53]
  wire [3:0] tile_auto_tl_other_masters_out_b_bits_mask; // @[HasTiles.scala 253:53]
  wire  tile_auto_tl_other_masters_out_b_bits_corrupt; // @[HasTiles.scala 253:53]
  wire  tile_auto_tl_other_masters_out_c_ready; // @[HasTiles.scala 253:53]
  wire  tile_auto_tl_other_masters_out_c_valid; // @[HasTiles.scala 253:53]
  wire [2:0] tile_auto_tl_other_masters_out_c_bits_opcode; // @[HasTiles.scala 253:53]
  wire [2:0] tile_auto_tl_other_masters_out_c_bits_param; // @[HasTiles.scala 253:53]
  wire [3:0] tile_auto_tl_other_masters_out_c_bits_size; // @[HasTiles.scala 253:53]
  wire [1:0] tile_auto_tl_other_masters_out_c_bits_source; // @[HasTiles.scala 253:53]
  wire [30:0] tile_auto_tl_other_masters_out_c_bits_address; // @[HasTiles.scala 253:53]
  wire [31:0] tile_auto_tl_other_masters_out_c_bits_data; // @[HasTiles.scala 253:53]
  wire  tile_auto_tl_other_masters_out_d_ready; // @[HasTiles.scala 253:53]
  wire  tile_auto_tl_other_masters_out_d_valid; // @[HasTiles.scala 253:53]
  wire [2:0] tile_auto_tl_other_masters_out_d_bits_opcode; // @[HasTiles.scala 253:53]
  wire [1:0] tile_auto_tl_other_masters_out_d_bits_param; // @[HasTiles.scala 253:53]
  wire [3:0] tile_auto_tl_other_masters_out_d_bits_size; // @[HasTiles.scala 253:53]
  wire [1:0] tile_auto_tl_other_masters_out_d_bits_source; // @[HasTiles.scala 253:53]
  wire [1:0] tile_auto_tl_other_masters_out_d_bits_sink; // @[HasTiles.scala 253:53]
  wire  tile_auto_tl_other_masters_out_d_bits_denied; // @[HasTiles.scala 253:53]
  wire [31:0] tile_auto_tl_other_masters_out_d_bits_data; // @[HasTiles.scala 253:53]
  wire  tile_auto_tl_other_masters_out_d_bits_corrupt; // @[HasTiles.scala 253:53]
  wire  tile_auto_tl_other_masters_out_e_ready; // @[HasTiles.scala 253:53]
  wire  tile_auto_tl_other_masters_out_e_valid; // @[HasTiles.scala 253:53]
  wire [1:0] tile_auto_tl_other_masters_out_e_bits_sink; // @[HasTiles.scala 253:53]
  RocketTile tile ( // @[HasTiles.scala 253:53]
    .clock(tile_clock),
    .reset(tile_reset),
    .auto_slave_in_a_ready(tile_auto_slave_in_a_ready),
    .auto_slave_in_a_valid(tile_auto_slave_in_a_valid),
    .auto_slave_in_a_bits_opcode(tile_auto_slave_in_a_bits_opcode),
    .auto_slave_in_a_bits_param(tile_auto_slave_in_a_bits_param),
    .auto_slave_in_a_bits_size(tile_auto_slave_in_a_bits_size),
    .auto_slave_in_a_bits_source(tile_auto_slave_in_a_bits_source),
    .auto_slave_in_a_bits_address(tile_auto_slave_in_a_bits_address),
    .auto_slave_in_a_bits_mask(tile_auto_slave_in_a_bits_mask),
    .auto_slave_in_a_bits_data(tile_auto_slave_in_a_bits_data),
    .auto_slave_in_a_bits_corrupt(tile_auto_slave_in_a_bits_corrupt),
    .auto_slave_in_d_ready(tile_auto_slave_in_d_ready),
    .auto_slave_in_d_valid(tile_auto_slave_in_d_valid),
    .auto_slave_in_d_bits_opcode(tile_auto_slave_in_d_bits_opcode),
    .auto_slave_in_d_bits_size(tile_auto_slave_in_d_bits_size),
    .auto_slave_in_d_bits_source(tile_auto_slave_in_d_bits_source),
    .auto_slave_in_d_bits_data(tile_auto_slave_in_d_bits_data),
    .auto_wfi_out_0(tile_auto_wfi_out_0),
    .auto_int_local_in_3_0(tile_auto_int_local_in_3_0),
    .auto_int_local_in_2_0(tile_auto_int_local_in_2_0),
    .auto_int_local_in_1_0(tile_auto_int_local_in_1_0),
    .auto_int_local_in_1_1(tile_auto_int_local_in_1_1),
    .auto_int_local_in_0_0(tile_auto_int_local_in_0_0),
    .auto_hartid_in(tile_auto_hartid_in),
    .auto_tl_other_masters_out_a_ready(tile_auto_tl_other_masters_out_a_ready),
    .auto_tl_other_masters_out_a_valid(tile_auto_tl_other_masters_out_a_valid),
    .auto_tl_other_masters_out_a_bits_opcode(tile_auto_tl_other_masters_out_a_bits_opcode),
    .auto_tl_other_masters_out_a_bits_param(tile_auto_tl_other_masters_out_a_bits_param),
    .auto_tl_other_masters_out_a_bits_size(tile_auto_tl_other_masters_out_a_bits_size),
    .auto_tl_other_masters_out_a_bits_source(tile_auto_tl_other_masters_out_a_bits_source),
    .auto_tl_other_masters_out_a_bits_address(tile_auto_tl_other_masters_out_a_bits_address),
    .auto_tl_other_masters_out_a_bits_mask(tile_auto_tl_other_masters_out_a_bits_mask),
    .auto_tl_other_masters_out_a_bits_data(tile_auto_tl_other_masters_out_a_bits_data),
    .auto_tl_other_masters_out_b_ready(tile_auto_tl_other_masters_out_b_ready),
    .auto_tl_other_masters_out_b_valid(tile_auto_tl_other_masters_out_b_valid),
    .auto_tl_other_masters_out_b_bits_opcode(tile_auto_tl_other_masters_out_b_bits_opcode),
    .auto_tl_other_masters_out_b_bits_param(tile_auto_tl_other_masters_out_b_bits_param),
    .auto_tl_other_masters_out_b_bits_size(tile_auto_tl_other_masters_out_b_bits_size),
    .auto_tl_other_masters_out_b_bits_source(tile_auto_tl_other_masters_out_b_bits_source),
    .auto_tl_other_masters_out_b_bits_address(tile_auto_tl_other_masters_out_b_bits_address),
    .auto_tl_other_masters_out_b_bits_mask(tile_auto_tl_other_masters_out_b_bits_mask),
    .auto_tl_other_masters_out_b_bits_corrupt(tile_auto_tl_other_masters_out_b_bits_corrupt),
    .auto_tl_other_masters_out_c_ready(tile_auto_tl_other_masters_out_c_ready),
    .auto_tl_other_masters_out_c_valid(tile_auto_tl_other_masters_out_c_valid),
    .auto_tl_other_masters_out_c_bits_opcode(tile_auto_tl_other_masters_out_c_bits_opcode),
    .auto_tl_other_masters_out_c_bits_param(tile_auto_tl_other_masters_out_c_bits_param),
    .auto_tl_other_masters_out_c_bits_size(tile_auto_tl_other_masters_out_c_bits_size),
    .auto_tl_other_masters_out_c_bits_source(tile_auto_tl_other_masters_out_c_bits_source),
    .auto_tl_other_masters_out_c_bits_address(tile_auto_tl_other_masters_out_c_bits_address),
    .auto_tl_other_masters_out_c_bits_data(tile_auto_tl_other_masters_out_c_bits_data),
    .auto_tl_other_masters_out_d_ready(tile_auto_tl_other_masters_out_d_ready),
    .auto_tl_other_masters_out_d_valid(tile_auto_tl_other_masters_out_d_valid),
    .auto_tl_other_masters_out_d_bits_opcode(tile_auto_tl_other_masters_out_d_bits_opcode),
    .auto_tl_other_masters_out_d_bits_param(tile_auto_tl_other_masters_out_d_bits_param),
    .auto_tl_other_masters_out_d_bits_size(tile_auto_tl_other_masters_out_d_bits_size),
    .auto_tl_other_masters_out_d_bits_source(tile_auto_tl_other_masters_out_d_bits_source),
    .auto_tl_other_masters_out_d_bits_sink(tile_auto_tl_other_masters_out_d_bits_sink),
    .auto_tl_other_masters_out_d_bits_denied(tile_auto_tl_other_masters_out_d_bits_denied),
    .auto_tl_other_masters_out_d_bits_data(tile_auto_tl_other_masters_out_d_bits_data),
    .auto_tl_other_masters_out_d_bits_corrupt(tile_auto_tl_other_masters_out_d_bits_corrupt),
    .auto_tl_other_masters_out_e_ready(tile_auto_tl_other_masters_out_e_ready),
    .auto_tl_other_masters_out_e_valid(tile_auto_tl_other_masters_out_e_valid),
    .auto_tl_other_masters_out_e_bits_sink(tile_auto_tl_other_masters_out_e_bits_sink)
  );
  assign auto_tile_slave_in_a_ready = tile_auto_slave_in_a_ready; // @[LazyModule.scala 309:16]
  assign auto_tile_slave_in_d_valid = tile_auto_slave_in_d_valid; // @[LazyModule.scala 309:16]
  assign auto_tile_slave_in_d_bits_opcode = tile_auto_slave_in_d_bits_opcode; // @[LazyModule.scala 309:16]
  assign auto_tile_slave_in_d_bits_size = tile_auto_slave_in_d_bits_size; // @[LazyModule.scala 309:16]
  assign auto_tile_slave_in_d_bits_source = tile_auto_slave_in_d_bits_source; // @[LazyModule.scala 309:16]
  assign auto_tile_slave_in_d_bits_data = tile_auto_slave_in_d_bits_data; // @[LazyModule.scala 309:16]
  assign auto_tile_wfi_out_0 = tile_auto_wfi_out_0; // @[LazyModule.scala 311:12]
  assign auto_tile_tl_other_masters_out_a_valid = tile_auto_tl_other_masters_out_a_valid; // @[LazyModule.scala 311:12]
  assign auto_tile_tl_other_masters_out_a_bits_opcode = tile_auto_tl_other_masters_out_a_bits_opcode; // @[LazyModule.scala 311:12]
  assign auto_tile_tl_other_masters_out_a_bits_param = tile_auto_tl_other_masters_out_a_bits_param; // @[LazyModule.scala 311:12]
  assign auto_tile_tl_other_masters_out_a_bits_size = tile_auto_tl_other_masters_out_a_bits_size; // @[LazyModule.scala 311:12]
  assign auto_tile_tl_other_masters_out_a_bits_source = tile_auto_tl_other_masters_out_a_bits_source; // @[LazyModule.scala 311:12]
  assign auto_tile_tl_other_masters_out_a_bits_address = tile_auto_tl_other_masters_out_a_bits_address; // @[LazyModule.scala 311:12]
  assign auto_tile_tl_other_masters_out_a_bits_mask = tile_auto_tl_other_masters_out_a_bits_mask; // @[LazyModule.scala 311:12]
  assign auto_tile_tl_other_masters_out_a_bits_data = tile_auto_tl_other_masters_out_a_bits_data; // @[LazyModule.scala 311:12]
  assign auto_tile_tl_other_masters_out_b_ready = tile_auto_tl_other_masters_out_b_ready; // @[LazyModule.scala 311:12]
  assign auto_tile_tl_other_masters_out_c_valid = tile_auto_tl_other_masters_out_c_valid; // @[LazyModule.scala 311:12]
  assign auto_tile_tl_other_masters_out_c_bits_opcode = tile_auto_tl_other_masters_out_c_bits_opcode; // @[LazyModule.scala 311:12]
  assign auto_tile_tl_other_masters_out_c_bits_param = tile_auto_tl_other_masters_out_c_bits_param; // @[LazyModule.scala 311:12]
  assign auto_tile_tl_other_masters_out_c_bits_size = tile_auto_tl_other_masters_out_c_bits_size; // @[LazyModule.scala 311:12]
  assign auto_tile_tl_other_masters_out_c_bits_source = tile_auto_tl_other_masters_out_c_bits_source; // @[LazyModule.scala 311:12]
  assign auto_tile_tl_other_masters_out_c_bits_address = tile_auto_tl_other_masters_out_c_bits_address; // @[LazyModule.scala 311:12]
  assign auto_tile_tl_other_masters_out_c_bits_data = tile_auto_tl_other_masters_out_c_bits_data; // @[LazyModule.scala 311:12]
  assign auto_tile_tl_other_masters_out_d_ready = tile_auto_tl_other_masters_out_d_ready; // @[LazyModule.scala 311:12]
  assign auto_tile_tl_other_masters_out_e_valid = tile_auto_tl_other_masters_out_e_valid; // @[LazyModule.scala 311:12]
  assign auto_tile_tl_other_masters_out_e_bits_sink = tile_auto_tl_other_masters_out_e_bits_sink; // @[LazyModule.scala 311:12]
  assign tile_clock = auto_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign tile_reset = auto_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign tile_auto_slave_in_a_valid = auto_tile_slave_in_a_valid; // @[LazyModule.scala 309:16]
  assign tile_auto_slave_in_a_bits_opcode = auto_tile_slave_in_a_bits_opcode; // @[LazyModule.scala 309:16]
  assign tile_auto_slave_in_a_bits_param = auto_tile_slave_in_a_bits_param; // @[LazyModule.scala 309:16]
  assign tile_auto_slave_in_a_bits_size = auto_tile_slave_in_a_bits_size; // @[LazyModule.scala 309:16]
  assign tile_auto_slave_in_a_bits_source = auto_tile_slave_in_a_bits_source; // @[LazyModule.scala 309:16]
  assign tile_auto_slave_in_a_bits_address = auto_tile_slave_in_a_bits_address; // @[LazyModule.scala 309:16]
  assign tile_auto_slave_in_a_bits_mask = auto_tile_slave_in_a_bits_mask; // @[LazyModule.scala 309:16]
  assign tile_auto_slave_in_a_bits_data = auto_tile_slave_in_a_bits_data; // @[LazyModule.scala 309:16]
  assign tile_auto_slave_in_a_bits_corrupt = auto_tile_slave_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
  assign tile_auto_slave_in_d_ready = auto_tile_slave_in_d_ready; // @[LazyModule.scala 309:16]
  assign tile_auto_int_local_in_3_0 = auto_tile_int_local_in_3_0; // @[LazyModule.scala 309:16]
  assign tile_auto_int_local_in_2_0 = auto_tile_int_local_in_2_0; // @[LazyModule.scala 309:16]
  assign tile_auto_int_local_in_1_0 = auto_tile_int_local_in_1_0; // @[LazyModule.scala 309:16]
  assign tile_auto_int_local_in_1_1 = auto_tile_int_local_in_1_1; // @[LazyModule.scala 309:16]
  assign tile_auto_int_local_in_0_0 = auto_tile_int_local_in_0_0; // @[LazyModule.scala 309:16]
  assign tile_auto_hartid_in = auto_tile_hartid_in; // @[LazyModule.scala 309:16]
  assign tile_auto_tl_other_masters_out_a_ready = auto_tile_tl_other_masters_out_a_ready; // @[LazyModule.scala 311:12]
  assign tile_auto_tl_other_masters_out_b_valid = auto_tile_tl_other_masters_out_b_valid; // @[LazyModule.scala 311:12]
  assign tile_auto_tl_other_masters_out_b_bits_opcode = auto_tile_tl_other_masters_out_b_bits_opcode; // @[LazyModule.scala 311:12]
  assign tile_auto_tl_other_masters_out_b_bits_param = auto_tile_tl_other_masters_out_b_bits_param; // @[LazyModule.scala 311:12]
  assign tile_auto_tl_other_masters_out_b_bits_size = auto_tile_tl_other_masters_out_b_bits_size; // @[LazyModule.scala 311:12]
  assign tile_auto_tl_other_masters_out_b_bits_source = auto_tile_tl_other_masters_out_b_bits_source; // @[LazyModule.scala 311:12]
  assign tile_auto_tl_other_masters_out_b_bits_address = auto_tile_tl_other_masters_out_b_bits_address; // @[LazyModule.scala 311:12]
  assign tile_auto_tl_other_masters_out_b_bits_mask = auto_tile_tl_other_masters_out_b_bits_mask; // @[LazyModule.scala 311:12]
  assign tile_auto_tl_other_masters_out_b_bits_corrupt = auto_tile_tl_other_masters_out_b_bits_corrupt; // @[LazyModule.scala 311:12]
  assign tile_auto_tl_other_masters_out_c_ready = auto_tile_tl_other_masters_out_c_ready; // @[LazyModule.scala 311:12]
  assign tile_auto_tl_other_masters_out_d_valid = auto_tile_tl_other_masters_out_d_valid; // @[LazyModule.scala 311:12]
  assign tile_auto_tl_other_masters_out_d_bits_opcode = auto_tile_tl_other_masters_out_d_bits_opcode; // @[LazyModule.scala 311:12]
  assign tile_auto_tl_other_masters_out_d_bits_param = auto_tile_tl_other_masters_out_d_bits_param; // @[LazyModule.scala 311:12]
  assign tile_auto_tl_other_masters_out_d_bits_size = auto_tile_tl_other_masters_out_d_bits_size; // @[LazyModule.scala 311:12]
  assign tile_auto_tl_other_masters_out_d_bits_source = auto_tile_tl_other_masters_out_d_bits_source; // @[LazyModule.scala 311:12]
  assign tile_auto_tl_other_masters_out_d_bits_sink = auto_tile_tl_other_masters_out_d_bits_sink; // @[LazyModule.scala 311:12]
  assign tile_auto_tl_other_masters_out_d_bits_denied = auto_tile_tl_other_masters_out_d_bits_denied; // @[LazyModule.scala 311:12]
  assign tile_auto_tl_other_masters_out_d_bits_data = auto_tile_tl_other_masters_out_d_bits_data; // @[LazyModule.scala 311:12]
  assign tile_auto_tl_other_masters_out_d_bits_corrupt = auto_tile_tl_other_masters_out_d_bits_corrupt; // @[LazyModule.scala 311:12]
  assign tile_auto_tl_other_masters_out_e_ready = auto_tile_tl_other_masters_out_e_ready; // @[LazyModule.scala 311:12]
endmodule
module TLBuffer_9(
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [3:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [30:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_b_ready,
  output        auto_in_b_valid,
  output [2:0]  auto_in_b_bits_opcode,
  output [1:0]  auto_in_b_bits_param,
  output [3:0]  auto_in_b_bits_size,
  output [1:0]  auto_in_b_bits_source,
  output [30:0] auto_in_b_bits_address,
  output [3:0]  auto_in_b_bits_mask,
  output        auto_in_b_bits_corrupt,
  output        auto_in_c_ready,
  input         auto_in_c_valid,
  input  [2:0]  auto_in_c_bits_opcode,
  input  [2:0]  auto_in_c_bits_param,
  input  [3:0]  auto_in_c_bits_size,
  input  [1:0]  auto_in_c_bits_source,
  input  [30:0] auto_in_c_bits_address,
  input  [31:0] auto_in_c_bits_data,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [1:0]  auto_in_d_bits_param,
  output [3:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output [1:0]  auto_in_d_bits_sink,
  output        auto_in_d_bits_denied,
  output [31:0] auto_in_d_bits_data,
  output        auto_in_d_bits_corrupt,
  output        auto_in_e_ready,
  input         auto_in_e_valid,
  input  [1:0]  auto_in_e_bits_sink,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [3:0]  auto_out_a_bits_size,
  output [1:0]  auto_out_a_bits_source,
  output [30:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_b_ready,
  input         auto_out_b_valid,
  input  [2:0]  auto_out_b_bits_opcode,
  input  [1:0]  auto_out_b_bits_param,
  input  [3:0]  auto_out_b_bits_size,
  input  [1:0]  auto_out_b_bits_source,
  input  [30:0] auto_out_b_bits_address,
  input  [3:0]  auto_out_b_bits_mask,
  input         auto_out_b_bits_corrupt,
  input         auto_out_c_ready,
  output        auto_out_c_valid,
  output [2:0]  auto_out_c_bits_opcode,
  output [2:0]  auto_out_c_bits_param,
  output [3:0]  auto_out_c_bits_size,
  output [1:0]  auto_out_c_bits_source,
  output [30:0] auto_out_c_bits_address,
  output [31:0] auto_out_c_bits_data,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_param,
  input  [3:0]  auto_out_d_bits_size,
  input  [1:0]  auto_out_d_bits_source,
  input  [1:0]  auto_out_d_bits_sink,
  input         auto_out_d_bits_denied,
  input  [31:0] auto_out_d_bits_data,
  input         auto_out_d_bits_corrupt,
  input         auto_out_e_ready,
  output        auto_out_e_valid,
  output [1:0]  auto_out_e_bits_sink
);
  assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_b_valid = auto_out_b_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_b_bits_opcode = auto_out_b_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_b_bits_param = auto_out_b_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_b_bits_size = auto_out_b_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_b_bits_source = auto_out_b_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_b_bits_address = auto_out_b_bits_address; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_b_bits_mask = auto_out_b_bits_mask; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_b_bits_corrupt = auto_out_b_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_c_ready = auto_out_c_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_e_ready = auto_out_e_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_b_ready = auto_in_b_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_valid = auto_in_c_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_bits_opcode = auto_in_c_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_bits_param = auto_in_c_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_bits_size = auto_in_c_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_bits_source = auto_in_c_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_bits_address = auto_in_c_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_c_bits_data = auto_in_c_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_e_valid = auto_in_e_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_e_bits_sink = auto_in_e_bits_sink; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module TLMonitor_45(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [3:0]  io_in_a_bits_size,
  input  [1:0]  io_in_a_bits_source,
  input  [30:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_b_ready,
  input         io_in_b_valid,
  input  [2:0]  io_in_b_bits_opcode,
  input  [1:0]  io_in_b_bits_param,
  input  [3:0]  io_in_b_bits_size,
  input  [1:0]  io_in_b_bits_source,
  input  [30:0] io_in_b_bits_address,
  input  [3:0]  io_in_b_bits_mask,
  input         io_in_b_bits_corrupt,
  input         io_in_c_ready,
  input         io_in_c_valid,
  input  [2:0]  io_in_c_bits_opcode,
  input  [2:0]  io_in_c_bits_param,
  input  [3:0]  io_in_c_bits_size,
  input  [1:0]  io_in_c_bits_source,
  input  [30:0] io_in_c_bits_address,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_param,
  input  [3:0]  io_in_d_bits_size,
  input  [1:0]  io_in_d_bits_source,
  input  [1:0]  io_in_d_bits_sink,
  input         io_in_d_bits_denied,
  input         io_in_d_bits_corrupt,
  input         io_in_e_ready,
  input         io_in_e_valid,
  input  [1:0]  io_in_e_bits_sink
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [31:0] _RAND_33;
  reg [31:0] _RAND_34;
  reg [31:0] _RAND_35;
  reg [31:0] _RAND_36;
  reg [31:0] _RAND_37;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T = io_in_a_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_1 = io_in_a_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_2 = io_in_a_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok = _source_ok_T | _source_ok_T_1 | _source_ok_T_2; // @[Parameters.scala 1125:46]
  wire [26:0] _is_aligned_mask_T_1 = 27'hfff << io_in_a_bits_size; // @[package.scala 234:77]
  wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1[11:0]; // @[package.scala 234:46]
  wire [30:0] _GEN_86 = {{19'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [30:0] _is_aligned_T = io_in_a_bits_address & _GEN_86; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 31'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 4'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire [31:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
  wire  _T_33 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire  _T_35 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 92:42]
  wire  _T_42 = _T_35 & source_ok; // @[Parameters.scala 1160:30]
  wire [31:0] _T_48 = $signed(_T_7) & -32'sh10001000; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_50 = io_in_a_bits_address ^ 31'h3000; // @[Parameters.scala 137:31]
  wire [31:0] _T_51 = {1'b0,$signed(_T_50)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_53 = $signed(_T_51) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _T_54 = $signed(_T_53) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_55 = io_in_a_bits_address ^ 31'h10000; // @[Parameters.scala 137:31]
  wire [31:0] _T_56 = {1'b0,$signed(_T_55)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_58 = $signed(_T_56) & -32'sh10000; // @[Parameters.scala 137:52]
  wire  _T_59 = $signed(_T_58) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_60 = io_in_a_bits_address ^ 31'h2000000; // @[Parameters.scala 137:31]
  wire [31:0] _T_61 = {1'b0,$signed(_T_60)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_63 = $signed(_T_61) & -32'sh10000; // @[Parameters.scala 137:52]
  wire  _T_64 = $signed(_T_63) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_65 = io_in_a_bits_address ^ 31'h8000000; // @[Parameters.scala 137:31]
  wire [31:0] _T_66 = {1'b0,$signed(_T_65)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_68 = $signed(_T_66) & -32'sh4000; // @[Parameters.scala 137:52]
  wire  _T_69 = $signed(_T_68) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_70 = io_in_a_bits_address ^ 31'hc000000; // @[Parameters.scala 137:31]
  wire [31:0] _T_71 = {1'b0,$signed(_T_70)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_73 = $signed(_T_71) & -32'sh4000000; // @[Parameters.scala 137:52]
  wire  _T_74 = $signed(_T_73) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_75 = io_in_a_bits_address ^ 31'h10012000; // @[Parameters.scala 137:31]
  wire [31:0] _T_76 = {1'b0,$signed(_T_75)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_78 = $signed(_T_76) & -32'sh2000; // @[Parameters.scala 137:52]
  wire  _T_79 = $signed(_T_78) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_80 = io_in_a_bits_address ^ 31'h10014000; // @[Parameters.scala 137:31]
  wire [31:0] _T_81 = {1'b0,$signed(_T_80)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_83 = $signed(_T_81) & -32'sh2000; // @[Parameters.scala 137:52]
  wire  _T_84 = $signed(_T_83) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_85 = io_in_a_bits_address ^ 31'h10016000; // @[Parameters.scala 137:31]
  wire [31:0] _T_86 = {1'b0,$signed(_T_85)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_88 = $signed(_T_86) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _T_89 = $signed(_T_88) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_90 = io_in_a_bits_address ^ 31'h10023000; // @[Parameters.scala 137:31]
  wire [31:0] _T_91 = {1'b0,$signed(_T_90)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_93 = $signed(_T_91) & -32'sh11000; // @[Parameters.scala 137:52]
  wire  _T_94 = $signed(_T_93) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_95 = io_in_a_bits_address ^ 31'h10024000; // @[Parameters.scala 137:31]
  wire [31:0] _T_96 = {1'b0,$signed(_T_95)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_98 = $signed(_T_96) & -32'sh12000; // @[Parameters.scala 137:52]
  wire  _T_99 = $signed(_T_98) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_100 = io_in_a_bits_address ^ 31'h10026000; // @[Parameters.scala 137:31]
  wire [31:0] _T_101 = {1'b0,$signed(_T_100)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_103 = $signed(_T_101) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _T_104 = $signed(_T_103) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_105 = io_in_a_bits_address ^ 31'h10043000; // @[Parameters.scala 137:31]
  wire [31:0] _T_106 = {1'b0,$signed(_T_105)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_108 = $signed(_T_106) & -32'sh11000; // @[Parameters.scala 137:52]
  wire  _T_109 = $signed(_T_108) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _T_110 = io_in_a_bits_address ^ 31'h20000000; // @[Parameters.scala 137:31]
  wire [31:0] _T_111 = {1'b0,$signed(_T_110)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_113 = $signed(_T_111) & -32'sh20000000; // @[Parameters.scala 137:52]
  wire  _T_114 = $signed(_T_113) == 32'sh0; // @[Parameters.scala 137:67]
  wire  _T_130 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 92:42]
  wire [30:0] _T_133 = io_in_a_bits_address ^ 31'h40000000; // @[Parameters.scala 137:31]
  wire [31:0] _T_134 = {1'b0,$signed(_T_133)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_136 = $signed(_T_134) & -32'sh20000000; // @[Parameters.scala 137:52]
  wire  _T_137 = $signed(_T_136) == 32'sh0; // @[Parameters.scala 137:67]
  wire  _T_138 = _T_130 & _T_137; // @[Parameters.scala 670:56]
  wire  _T_141 = _T_42 & _T_138; // @[Monitor.scala 82:72]
  wire  _T_148 = 4'h6 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_149 = _source_ok_T & _T_148; // @[Mux.scala 27:73]
  wire  _T_246 = _T_49 | _T_54 | _T_59 | _T_64 | _T_69 | _T_74 | _T_79 | _T_84 | _T_89 | _T_94 | _T_99 | _T_104 | _T_109
     | _T_114 | _T_137; // @[Parameters.scala 671:42]
  wire  _T_247 = _T_35 & _T_246; // @[Parameters.scala 670:56]
  wire  _T_249 = _T_149 & _T_247; // @[Monitor.scala 83:78]
  wire  _T_263 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_267 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_268 = _T_267 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_276 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_510 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_523 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_546 = _T_35 & _T_54; // @[Parameters.scala 670:56]
  wire  _T_633 = _T_49 | _T_59 | _T_64 | _T_69 | _T_74 | _T_79 | _T_84 | _T_89 | _T_94 | _T_99 | _T_104 | _T_109 |
    _T_114 | _T_137; // @[Parameters.scala 671:42]
  wire  _T_634 = _T_130 & _T_633; // @[Parameters.scala 670:56]
  wire  _T_636 = _T_546 | _T_634; // @[Parameters.scala 672:30]
  wire  _T_646 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_650 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_658 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_752 = _T_49 | _T_64 | _T_69 | _T_74 | _T_79 | _T_84 | _T_89 | _T_94 | _T_99 | _T_104 | _T_109; // @[Parameters.scala 671:42]
  wire  _T_753 = _T_49 | _T_64 | _T_69 | _T_74 | _T_79 | _T_84 | _T_89 | _T_94 | _T_99 | _T_104 | _T_109 | _T_137; // @[Parameters.scala 671:42]
  wire  _T_754 = _T_130 & _T_753; // @[Parameters.scala 670:56]
  wire  _T_769 = _T_546 | _T_754; // @[Parameters.scala 672:30]
  wire  _T_771 = _T_42 & _T_769; // @[Monitor.scala 115:71]
  wire  _T_789 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire  _T_879 = _T_130 & _T_752; // @[Parameters.scala 670:56]
  wire  _T_900 = _T_546 | _T_879; // @[Parameters.scala 672:30]
  wire  _T_902 = _T_42 & _T_900; // @[Monitor.scala 123:74]
  wire [3:0] _T_916 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_917 = io_in_a_bits_mask & _T_916; // @[Monitor.scala 127:31]
  wire  _T_918 = _T_917 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_922 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_934 = io_in_a_bits_size <= 4'h2; // @[Parameters.scala 92:42]
  wire  _T_1007 = _T_49 | _T_54 | _T_64 | _T_69 | _T_74 | _T_79 | _T_84 | _T_89 | _T_94 | _T_99 | _T_104 | _T_109; // @[Parameters.scala 671:42]
  wire  _T_1008 = _T_934 & _T_1007; // @[Parameters.scala 670:56]
  wire  _T_1030 = _T_42 & _T_1008; // @[Monitor.scala 131:74]
  wire  _T_1040 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_1048 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_1166 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_1174 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_1282 = _T_42 & _T_546; // @[Monitor.scala 147:68]
  wire  _T_1292 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_1304 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_4 = io_in_d_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_5 = io_in_d_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_6 = io_in_d_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_1 = _source_ok_T_4 | _source_ok_T_5 | _source_ok_T_6; // @[Parameters.scala 1125:46]
  wire  _T_1308 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_1312 = io_in_d_bits_size >= 4'h2; // @[Monitor.scala 312:27]
  wire  _T_1316 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
  wire  _T_1320 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
  wire  _T_1324 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
  wire  _T_1328 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_1339 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
  wire  _T_1343 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
  wire  _T_1356 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_1376 = _T_1324 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
  wire  _T_1385 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_1402 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_1420 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  _T_1437 = io_in_b_bits_opcode <= 3'h6; // @[Bundles.scala 40:24]
  wire  _T_1441 = io_in_b_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire [31:0] _T_1444 = {1'b0,$signed(io_in_b_bits_address)}; // @[Parameters.scala 137:49]
  wire  _T_1449 = io_in_b_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _T_1457 = io_in_b_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire [30:0] _address_ok_T = io_in_b_bits_address ^ 31'h3000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_1 = {1'b0,$signed(_address_ok_T)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_3 = $signed(_address_ok_T_1) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_4 = $signed(_address_ok_T_3) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_5 = io_in_b_bits_address ^ 31'h10013000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_6 = {1'b0,$signed(_address_ok_T_5)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_8 = $signed(_address_ok_T_6) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_9 = $signed(_address_ok_T_8) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_10 = io_in_b_bits_address ^ 31'h10023000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_11 = {1'b0,$signed(_address_ok_T_10)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_13 = $signed(_address_ok_T_11) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_14 = $signed(_address_ok_T_13) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_15 = io_in_b_bits_address ^ 31'h10033000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_16 = {1'b0,$signed(_address_ok_T_15)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_18 = $signed(_address_ok_T_16) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_19 = $signed(_address_ok_T_18) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_20 = io_in_b_bits_address ^ 31'h10043000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_21 = {1'b0,$signed(_address_ok_T_20)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_23 = $signed(_address_ok_T_21) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_24 = $signed(_address_ok_T_23) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_25 = io_in_b_bits_address ^ 31'h10053000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_26 = {1'b0,$signed(_address_ok_T_25)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_28 = $signed(_address_ok_T_26) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_29 = $signed(_address_ok_T_28) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_30 = io_in_b_bits_address ^ 31'h10014000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_31 = {1'b0,$signed(_address_ok_T_30)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_33 = $signed(_address_ok_T_31) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_34 = $signed(_address_ok_T_33) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_35 = io_in_b_bits_address ^ 31'h20000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_36 = {1'b0,$signed(_address_ok_T_35)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_38 = $signed(_address_ok_T_36) & -32'sh20000000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_39 = $signed(_address_ok_T_38) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_40 = io_in_b_bits_address ^ 31'h10034000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_41 = {1'b0,$signed(_address_ok_T_40)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_43 = $signed(_address_ok_T_41) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_44 = $signed(_address_ok_T_43) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_45 = io_in_b_bits_address ^ 31'h10024000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_46 = {1'b0,$signed(_address_ok_T_45)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_48 = $signed(_address_ok_T_46) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_49 = $signed(_address_ok_T_48) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_50 = io_in_b_bits_address ^ 31'h10012000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_51 = {1'b0,$signed(_address_ok_T_50)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_53 = $signed(_address_ok_T_51) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_54 = $signed(_address_ok_T_53) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_55 = io_in_b_bits_address ^ 31'h10015000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_56 = {1'b0,$signed(_address_ok_T_55)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_58 = $signed(_address_ok_T_56) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_59 = $signed(_address_ok_T_58) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_60 = io_in_b_bits_address ^ 31'h10025000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_61 = {1'b0,$signed(_address_ok_T_60)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_63 = $signed(_address_ok_T_61) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_64 = $signed(_address_ok_T_63) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_65 = io_in_b_bits_address ^ 31'h10035000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_66 = {1'b0,$signed(_address_ok_T_65)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_68 = $signed(_address_ok_T_66) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_69 = $signed(_address_ok_T_68) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_70 = io_in_b_bits_address ^ 31'h10016000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_71 = {1'b0,$signed(_address_ok_T_70)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_73 = $signed(_address_ok_T_71) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_74 = $signed(_address_ok_T_73) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_75 = io_in_b_bits_address ^ 31'h10026000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_76 = {1'b0,$signed(_address_ok_T_75)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_78 = $signed(_address_ok_T_76) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_79 = $signed(_address_ok_T_78) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_80 = io_in_b_bits_address ^ 31'hc000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_81 = {1'b0,$signed(_address_ok_T_80)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_83 = $signed(_address_ok_T_81) & -32'sh4000000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_84 = $signed(_address_ok_T_83) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_85 = io_in_b_bits_address ^ 31'h2000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_86 = {1'b0,$signed(_address_ok_T_85)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_88 = $signed(_address_ok_T_86) & -32'sh10000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_89 = $signed(_address_ok_T_88) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _address_ok_T_93 = $signed(_T_1444) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_94 = $signed(_address_ok_T_93) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_95 = io_in_b_bits_address ^ 31'h8000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_96 = {1'b0,$signed(_address_ok_T_95)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_98 = $signed(_address_ok_T_96) & -32'sh4000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_99 = $signed(_address_ok_T_98) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_100 = io_in_b_bits_address ^ 31'h10000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_101 = {1'b0,$signed(_address_ok_T_100)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_103 = $signed(_address_ok_T_101) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_104 = $signed(_address_ok_T_103) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_105 = io_in_b_bits_address ^ 31'h10000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_106 = {1'b0,$signed(_address_ok_T_105)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_108 = $signed(_address_ok_T_106) & -32'sh10000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_109 = $signed(_address_ok_T_108) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_110 = io_in_b_bits_address ^ 31'h40000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_111 = {1'b0,$signed(_address_ok_T_110)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_113 = $signed(_address_ok_T_111) & -32'sh20000000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_114 = $signed(_address_ok_T_113) == 32'sh0; // @[Parameters.scala 137:67]
  wire  address_ok = _address_ok_T_4 | _address_ok_T_9 | _address_ok_T_14 | _address_ok_T_19 | _address_ok_T_24 |
    _address_ok_T_29 | _address_ok_T_34 | _address_ok_T_39 | _address_ok_T_44 | _address_ok_T_49 | _address_ok_T_54 |
    _address_ok_T_59 | _address_ok_T_64 | _address_ok_T_69 | _address_ok_T_74 | _address_ok_T_79 | _address_ok_T_84 |
    _address_ok_T_89 | _address_ok_T_94 | _address_ok_T_99 | _address_ok_T_104 | _address_ok_T_109 | _address_ok_T_114; // @[Parameters.scala 622:64]
  wire [26:0] _is_aligned_mask_T_4 = 27'hfff << io_in_b_bits_size; // @[package.scala 234:77]
  wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_4[11:0]; // @[package.scala 234:46]
  wire [30:0] _GEN_87 = {{19'd0}, is_aligned_mask_1}; // @[Edges.scala 20:16]
  wire [30:0] _is_aligned_T_1 = io_in_b_bits_address & _GEN_87; // @[Edges.scala 20:16]
  wire  is_aligned_1 = _is_aligned_T_1 == 31'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount_1 = io_in_b_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_4 = 2'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH_1 = _mask_sizeOH_T_4 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T_1 = io_in_b_bits_size >= 4'h2; // @[Misc.scala 205:21]
  wire  mask_size_2 = mask_sizeOH_1[1]; // @[Misc.scala 208:26]
  wire  mask_bit_2 = io_in_b_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit_2 = ~mask_bit_2; // @[Misc.scala 210:20]
  wire  mask_acc_6 = _mask_T_1 | mask_size_2 & mask_nbit_2; // @[Misc.scala 214:29]
  wire  mask_acc_7 = _mask_T_1 | mask_size_2 & mask_bit_2; // @[Misc.scala 214:29]
  wire  mask_size_3 = mask_sizeOH_1[0]; // @[Misc.scala 208:26]
  wire  mask_bit_3 = io_in_b_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_3 = ~mask_bit_3; // @[Misc.scala 210:20]
  wire  mask_eq_8 = mask_nbit_2 & mask_nbit_3; // @[Misc.scala 213:27]
  wire  mask_acc_8 = mask_acc_6 | mask_size_3 & mask_eq_8; // @[Misc.scala 214:29]
  wire  mask_eq_9 = mask_nbit_2 & mask_bit_3; // @[Misc.scala 213:27]
  wire  mask_acc_9 = mask_acc_6 | mask_size_3 & mask_eq_9; // @[Misc.scala 214:29]
  wire  mask_eq_10 = mask_bit_2 & mask_nbit_3; // @[Misc.scala 213:27]
  wire  mask_acc_10 = mask_acc_7 | mask_size_3 & mask_eq_10; // @[Misc.scala 214:29]
  wire  mask_eq_11 = mask_bit_2 & mask_bit_3; // @[Misc.scala 213:27]
  wire  mask_acc_11 = mask_acc_7 | mask_size_3 & mask_eq_11; // @[Misc.scala 214:29]
  wire [3:0] mask_1 = {mask_acc_11,mask_acc_10,mask_acc_9,mask_acc_8}; // @[Cat.scala 31:58]
  wire [1:0] _legal_source_T_5 = _T_1457 ? 2'h2 : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _GEN_88 = {{1'd0}, _T_1449}; // @[Mux.scala 27:73]
  wire [1:0] _legal_source_T_7 = _GEN_88 | _legal_source_T_5; // @[Mux.scala 27:73]
  wire  legal_source = _legal_source_T_7 == io_in_b_bits_source; // @[Monitor.scala 165:113]
  wire  _T_1470 = io_in_b_bits_opcode == 3'h6; // @[Monitor.scala 167:25]
  wire  _T_1474 = 4'h6 == io_in_b_bits_size; // @[Parameters.scala 91:48]
  wire  _T_1475 = _T_1441 & _T_1474; // @[Mux.scala 27:73]
  wire  _T_1481 = io_in_b_bits_size <= 4'hc; // @[Parameters.scala 92:42]
  wire [31:0] _T_1487 = $signed(_T_1444) & -32'sh10001000; // @[Parameters.scala 137:52]
  wire  _T_1488 = $signed(_T_1487) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_1517 = $signed(_address_ok_T_51) & -32'sh2000; // @[Parameters.scala 137:52]
  wire  _T_1518 = $signed(_T_1517) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_1522 = $signed(_address_ok_T_31) & -32'sh2000; // @[Parameters.scala 137:52]
  wire  _T_1523 = $signed(_T_1522) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_1532 = $signed(_address_ok_T_11) & -32'sh11000; // @[Parameters.scala 137:52]
  wire  _T_1533 = $signed(_T_1532) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_1537 = $signed(_address_ok_T_46) & -32'sh12000; // @[Parameters.scala 137:52]
  wire  _T_1538 = $signed(_T_1537) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_1547 = $signed(_address_ok_T_21) & -32'sh11000; // @[Parameters.scala 137:52]
  wire  _T_1548 = $signed(_T_1547) == 32'sh0; // @[Parameters.scala 137:67]
  wire  _T_1572 = _T_1488 | _address_ok_T_4 | _address_ok_T_109 | _address_ok_T_89 | _address_ok_T_99 | _address_ok_T_84
     | _T_1518 | _T_1523 | _address_ok_T_74 | _T_1533 | _T_1538 | _address_ok_T_79 | _T_1548 | _address_ok_T_39 |
    _address_ok_T_114; // @[Parameters.scala 671:42]
  wire  _T_1573 = _T_1481 & _T_1572; // @[Parameters.scala 670:56]
  wire  _T_1575 = _T_1475 & _T_1573; // @[Monitor.scala 168:75]
  wire  _T_1581 = ~address_ok; // @[Monitor.scala 49:11]
  wire  _T_1584 = ~legal_source; // @[Monitor.scala 49:11]
  wire  _T_1587 = ~is_aligned_1; // @[Monitor.scala 49:11]
  wire  _T_1588 = io_in_b_bits_param <= 2'h2; // @[Bundles.scala 102:26]
  wire  _T_1592 = io_in_b_bits_mask == mask_1; // @[Monitor.scala 173:27]
  wire  _T_1595 = ~_T_1592; // @[Monitor.scala 49:11]
  wire  _T_1596 = ~io_in_b_bits_corrupt; // @[Monitor.scala 174:15]
  wire  _T_1599 = ~_T_1596; // @[Monitor.scala 49:11]
  wire  _T_1600 = io_in_b_bits_opcode == 3'h4; // @[Monitor.scala 177:25]
  wire  _T_1709 = io_in_b_bits_param == 2'h0; // @[Monitor.scala 182:31]
  wire  _T_1721 = io_in_b_bits_opcode == 3'h0; // @[Monitor.scala 187:25]
  wire  _T_1838 = io_in_b_bits_opcode == 3'h1; // @[Monitor.scala 196:25]
  wire [3:0] _T_1951 = ~mask_1; // @[Monitor.scala 202:33]
  wire [3:0] _T_1952 = io_in_b_bits_mask & _T_1951; // @[Monitor.scala 202:31]
  wire  _T_1953 = _T_1952 == 4'h0; // @[Monitor.scala 202:40]
  wire  _T_1957 = io_in_b_bits_opcode == 3'h2; // @[Monitor.scala 205:25]
  wire  _T_2074 = io_in_b_bits_opcode == 3'h3; // @[Monitor.scala 214:25]
  wire  _T_2191 = io_in_b_bits_opcode == 3'h5; // @[Monitor.scala 223:25]
  wire  _source_ok_T_8 = io_in_c_bits_source == 2'h0; // @[Parameters.scala 46:9]
  wire  _source_ok_T_9 = io_in_c_bits_source == 2'h1; // @[Parameters.scala 46:9]
  wire  _source_ok_T_10 = io_in_c_bits_source == 2'h2; // @[Parameters.scala 46:9]
  wire  source_ok_2 = _source_ok_T_8 | _source_ok_T_9 | _source_ok_T_10; // @[Parameters.scala 1125:46]
  wire [26:0] _is_aligned_mask_T_7 = 27'hfff << io_in_c_bits_size; // @[package.scala 234:77]
  wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_7[11:0]; // @[package.scala 234:46]
  wire [30:0] _GEN_89 = {{19'd0}, is_aligned_mask_2}; // @[Edges.scala 20:16]
  wire [30:0] _is_aligned_T_2 = io_in_c_bits_address & _GEN_89; // @[Edges.scala 20:16]
  wire  is_aligned_2 = _is_aligned_T_2 == 31'h0; // @[Edges.scala 20:24]
  wire [30:0] _address_ok_T_136 = io_in_c_bits_address ^ 31'h3000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_137 = {1'b0,$signed(_address_ok_T_136)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_139 = $signed(_address_ok_T_137) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_140 = $signed(_address_ok_T_139) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_141 = io_in_c_bits_address ^ 31'h10013000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_142 = {1'b0,$signed(_address_ok_T_141)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_144 = $signed(_address_ok_T_142) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_145 = $signed(_address_ok_T_144) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_146 = io_in_c_bits_address ^ 31'h10023000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_147 = {1'b0,$signed(_address_ok_T_146)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_149 = $signed(_address_ok_T_147) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_150 = $signed(_address_ok_T_149) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_151 = io_in_c_bits_address ^ 31'h10033000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_152 = {1'b0,$signed(_address_ok_T_151)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_154 = $signed(_address_ok_T_152) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_155 = $signed(_address_ok_T_154) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_156 = io_in_c_bits_address ^ 31'h10043000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_157 = {1'b0,$signed(_address_ok_T_156)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_159 = $signed(_address_ok_T_157) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_160 = $signed(_address_ok_T_159) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_161 = io_in_c_bits_address ^ 31'h10053000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_162 = {1'b0,$signed(_address_ok_T_161)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_164 = $signed(_address_ok_T_162) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_165 = $signed(_address_ok_T_164) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_166 = io_in_c_bits_address ^ 31'h10014000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_167 = {1'b0,$signed(_address_ok_T_166)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_169 = $signed(_address_ok_T_167) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_170 = $signed(_address_ok_T_169) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_171 = io_in_c_bits_address ^ 31'h20000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_172 = {1'b0,$signed(_address_ok_T_171)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_174 = $signed(_address_ok_T_172) & -32'sh20000000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_175 = $signed(_address_ok_T_174) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_176 = io_in_c_bits_address ^ 31'h10034000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_177 = {1'b0,$signed(_address_ok_T_176)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_179 = $signed(_address_ok_T_177) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_180 = $signed(_address_ok_T_179) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_181 = io_in_c_bits_address ^ 31'h10024000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_182 = {1'b0,$signed(_address_ok_T_181)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_184 = $signed(_address_ok_T_182) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_185 = $signed(_address_ok_T_184) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_186 = io_in_c_bits_address ^ 31'h10012000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_187 = {1'b0,$signed(_address_ok_T_186)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_189 = $signed(_address_ok_T_187) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_190 = $signed(_address_ok_T_189) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_191 = io_in_c_bits_address ^ 31'h10015000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_192 = {1'b0,$signed(_address_ok_T_191)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_194 = $signed(_address_ok_T_192) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_195 = $signed(_address_ok_T_194) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_196 = io_in_c_bits_address ^ 31'h10025000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_197 = {1'b0,$signed(_address_ok_T_196)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_199 = $signed(_address_ok_T_197) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_200 = $signed(_address_ok_T_199) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_201 = io_in_c_bits_address ^ 31'h10035000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_202 = {1'b0,$signed(_address_ok_T_201)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_204 = $signed(_address_ok_T_202) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_205 = $signed(_address_ok_T_204) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_206 = io_in_c_bits_address ^ 31'h10016000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_207 = {1'b0,$signed(_address_ok_T_206)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_209 = $signed(_address_ok_T_207) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_210 = $signed(_address_ok_T_209) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_211 = io_in_c_bits_address ^ 31'h10026000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_212 = {1'b0,$signed(_address_ok_T_211)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_214 = $signed(_address_ok_T_212) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_215 = $signed(_address_ok_T_214) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_216 = io_in_c_bits_address ^ 31'hc000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_217 = {1'b0,$signed(_address_ok_T_216)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_219 = $signed(_address_ok_T_217) & -32'sh4000000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_220 = $signed(_address_ok_T_219) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_221 = io_in_c_bits_address ^ 31'h2000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_222 = {1'b0,$signed(_address_ok_T_221)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_224 = $signed(_address_ok_T_222) & -32'sh10000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_225 = $signed(_address_ok_T_224) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _address_ok_T_227 = {1'b0,$signed(io_in_c_bits_address)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_229 = $signed(_address_ok_T_227) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_230 = $signed(_address_ok_T_229) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_231 = io_in_c_bits_address ^ 31'h8000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_232 = {1'b0,$signed(_address_ok_T_231)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_234 = $signed(_address_ok_T_232) & -32'sh4000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_235 = $signed(_address_ok_T_234) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_236 = io_in_c_bits_address ^ 31'h10000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_237 = {1'b0,$signed(_address_ok_T_236)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_239 = $signed(_address_ok_T_237) & -32'sh1000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_240 = $signed(_address_ok_T_239) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_241 = io_in_c_bits_address ^ 31'h10000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_242 = {1'b0,$signed(_address_ok_T_241)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_244 = $signed(_address_ok_T_242) & -32'sh10000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_245 = $signed(_address_ok_T_244) == 32'sh0; // @[Parameters.scala 137:67]
  wire [30:0] _address_ok_T_246 = io_in_c_bits_address ^ 31'h40000000; // @[Parameters.scala 137:31]
  wire [31:0] _address_ok_T_247 = {1'b0,$signed(_address_ok_T_246)}; // @[Parameters.scala 137:49]
  wire [31:0] _address_ok_T_249 = $signed(_address_ok_T_247) & -32'sh20000000; // @[Parameters.scala 137:52]
  wire  _address_ok_T_250 = $signed(_address_ok_T_249) == 32'sh0; // @[Parameters.scala 137:67]
  wire  address_ok_1 = _address_ok_T_140 | _address_ok_T_145 | _address_ok_T_150 | _address_ok_T_155 | _address_ok_T_160
     | _address_ok_T_165 | _address_ok_T_170 | _address_ok_T_175 | _address_ok_T_180 | _address_ok_T_185 |
    _address_ok_T_190 | _address_ok_T_195 | _address_ok_T_200 | _address_ok_T_205 | _address_ok_T_210 |
    _address_ok_T_215 | _address_ok_T_220 | _address_ok_T_225 | _address_ok_T_230 | _address_ok_T_235 |
    _address_ok_T_240 | _address_ok_T_245 | _address_ok_T_250; // @[Parameters.scala 622:64]
  wire  _T_2341 = io_in_c_bits_opcode == 3'h4; // @[Monitor.scala 242:25]
  wire  _T_2348 = io_in_c_bits_size >= 4'h2; // @[Monitor.scala 245:30]
  wire  _T_2355 = io_in_c_bits_param <= 3'h5; // @[Bundles.scala 120:29]
  wire  _T_2363 = io_in_c_bits_opcode == 3'h5; // @[Monitor.scala 251:25]
  wire  _T_2381 = io_in_c_bits_opcode == 3'h6; // @[Monitor.scala 259:25]
  wire  _T_2383 = io_in_c_bits_size <= 4'hc; // @[Parameters.scala 92:42]
  wire  _T_2390 = _T_2383 & source_ok_2; // @[Parameters.scala 1160:30]
  wire [31:0] _T_2396 = $signed(_address_ok_T_227) & -32'sh10001000; // @[Parameters.scala 137:52]
  wire  _T_2397 = $signed(_T_2396) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_2426 = $signed(_address_ok_T_187) & -32'sh2000; // @[Parameters.scala 137:52]
  wire  _T_2427 = $signed(_T_2426) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_2431 = $signed(_address_ok_T_167) & -32'sh2000; // @[Parameters.scala 137:52]
  wire  _T_2432 = $signed(_T_2431) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_2441 = $signed(_address_ok_T_147) & -32'sh11000; // @[Parameters.scala 137:52]
  wire  _T_2442 = $signed(_T_2441) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_2446 = $signed(_address_ok_T_182) & -32'sh12000; // @[Parameters.scala 137:52]
  wire  _T_2447 = $signed(_T_2446) == 32'sh0; // @[Parameters.scala 137:67]
  wire [31:0] _T_2456 = $signed(_address_ok_T_157) & -32'sh11000; // @[Parameters.scala 137:52]
  wire  _T_2457 = $signed(_T_2456) == 32'sh0; // @[Parameters.scala 137:67]
  wire  _T_2478 = io_in_c_bits_size <= 4'h6; // @[Parameters.scala 92:42]
  wire  _T_2486 = _T_2478 & _address_ok_T_250; // @[Parameters.scala 670:56]
  wire  _T_2489 = _T_2390 & _T_2486; // @[Monitor.scala 260:78]
  wire  _T_2496 = 4'h6 == io_in_c_bits_size; // @[Parameters.scala 91:48]
  wire  _T_2497 = _source_ok_T_8 & _T_2496; // @[Mux.scala 27:73]
  wire  _T_2594 = _T_2397 | _address_ok_T_140 | _address_ok_T_245 | _address_ok_T_225 | _address_ok_T_235 |
    _address_ok_T_220 | _T_2427 | _T_2432 | _address_ok_T_210 | _T_2442 | _T_2447 | _address_ok_T_215 | _T_2457 |
    _address_ok_T_175 | _address_ok_T_250; // @[Parameters.scala 671:42]
  wire  _T_2595 = _T_2383 & _T_2594; // @[Parameters.scala 670:56]
  wire  _T_2597 = _T_2497 & _T_2595; // @[Monitor.scala 261:78]
  wire  _T_2619 = io_in_c_bits_opcode == 3'h7; // @[Monitor.scala 269:25]
  wire  _T_2853 = io_in_c_bits_opcode == 3'h0; // @[Monitor.scala 278:25]
  wire  _T_2863 = io_in_c_bits_param == 3'h0; // @[Monitor.scala 282:31]
  wire  _T_2871 = io_in_c_bits_opcode == 3'h1; // @[Monitor.scala 286:25]
  wire  _T_2885 = io_in_c_bits_opcode == 3'h2; // @[Monitor.scala 293:25]
  wire  _a_first_T = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  wire [9:0] a_first_beats1_decode = is_aligned_mask[11:2]; // @[Edges.scala 219:59]
  wire  a_first_beats1_opdata = ~io_in_a_bits_opcode[2]; // @[Edges.scala 91:28]
  reg [9:0] a_first_counter; // @[Edges.scala 228:27]
  wire [9:0] a_first_counter1 = a_first_counter - 10'h1; // @[Edges.scala 229:28]
  wire  a_first = a_first_counter == 10'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [3:0] size; // @[Monitor.scala 386:22]
  reg [1:0] source; // @[Monitor.scala 387:22]
  reg [30:0] address; // @[Monitor.scala 388:22]
  wire  _T_2907 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_2908 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_2912 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_2916 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_2920 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_2924 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  _d_first_T = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  wire [26:0] _d_first_beats1_decode_T_1 = 27'hfff << io_in_d_bits_size; // @[package.scala 234:77]
  wire [11:0] _d_first_beats1_decode_T_3 = ~_d_first_beats1_decode_T_1[11:0]; // @[package.scala 234:46]
  wire [9:0] d_first_beats1_decode = _d_first_beats1_decode_T_3[11:2]; // @[Edges.scala 219:59]
  wire  d_first_beats1_opdata = io_in_d_bits_opcode[0]; // @[Edges.scala 105:36]
  reg [9:0] d_first_counter; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1 = d_first_counter - 10'h1; // @[Edges.scala 229:28]
  wire  d_first = d_first_counter == 10'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] param_1; // @[Monitor.scala 536:22]
  reg [3:0] size_1; // @[Monitor.scala 537:22]
  reg [1:0] source_1; // @[Monitor.scala 538:22]
  reg [1:0] sink; // @[Monitor.scala 539:22]
  reg  denied; // @[Monitor.scala 540:22]
  wire  _T_2931 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_2932 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_2936 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
  wire  _T_2940 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_2944 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  wire  _T_2948 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
  wire  _T_2952 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
  wire  b_first_done = io_in_b_ready & io_in_b_valid; // @[Decoupled.scala 50:35]
  reg [9:0] b_first_counter; // @[Edges.scala 228:27]
  wire [9:0] b_first_counter1 = b_first_counter - 10'h1; // @[Edges.scala 229:28]
  wire  b_first = b_first_counter == 10'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_2; // @[Monitor.scala 407:22]
  reg [1:0] param_2; // @[Monitor.scala 408:22]
  reg [3:0] size_2; // @[Monitor.scala 409:22]
  reg [1:0] source_2; // @[Monitor.scala 410:22]
  reg [30:0] address_1; // @[Monitor.scala 411:22]
  wire  _T_2959 = io_in_b_valid & ~b_first; // @[Monitor.scala 412:19]
  wire  _T_2960 = io_in_b_bits_opcode == opcode_2; // @[Monitor.scala 413:32]
  wire  _T_2964 = io_in_b_bits_param == param_2; // @[Monitor.scala 414:32]
  wire  _T_2968 = io_in_b_bits_size == size_2; // @[Monitor.scala 415:32]
  wire  _T_2972 = io_in_b_bits_source == source_2; // @[Monitor.scala 416:32]
  wire  _T_2976 = io_in_b_bits_address == address_1; // @[Monitor.scala 417:32]
  wire  _c_first_T = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala 50:35]
  wire [9:0] c_first_beats1_decode = is_aligned_mask_2[11:2]; // @[Edges.scala 219:59]
  wire  c_first_beats1_opdata = io_in_c_bits_opcode[0]; // @[Edges.scala 101:36]
  reg [9:0] c_first_counter; // @[Edges.scala 228:27]
  wire [9:0] c_first_counter1 = c_first_counter - 10'h1; // @[Edges.scala 229:28]
  wire  c_first = c_first_counter == 10'h0; // @[Edges.scala 230:25]
  reg [2:0] opcode_3; // @[Monitor.scala 512:22]
  reg [2:0] param_3; // @[Monitor.scala 513:22]
  reg [3:0] size_3; // @[Monitor.scala 514:22]
  reg [1:0] source_3; // @[Monitor.scala 515:22]
  reg [30:0] address_2; // @[Monitor.scala 516:22]
  wire  _T_2983 = io_in_c_valid & ~c_first; // @[Monitor.scala 517:19]
  wire  _T_2984 = io_in_c_bits_opcode == opcode_3; // @[Monitor.scala 518:32]
  wire  _T_2988 = io_in_c_bits_param == param_3; // @[Monitor.scala 519:32]
  wire  _T_2992 = io_in_c_bits_size == size_3; // @[Monitor.scala 520:32]
  wire  _T_2996 = io_in_c_bits_source == source_3; // @[Monitor.scala 521:32]
  wire  _T_3000 = io_in_c_bits_address == address_2; // @[Monitor.scala 522:32]
  reg [2:0] inflight; // @[Monitor.scala 611:27]
  reg [11:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [23:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg [9:0] a_first_counter_1; // @[Edges.scala 228:27]
  wire [9:0] a_first_counter1_1 = a_first_counter_1 - 10'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = a_first_counter_1 == 10'h0; // @[Edges.scala 230:25]
  reg [9:0] d_first_counter_1; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1_1 = d_first_counter_1 - 10'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = d_first_counter_1 == 10'h0; // @[Edges.scala 230:25]
  wire [3:0] _GEN_90 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [4:0] _a_opcode_lookup_T = {{1'd0}, _GEN_90}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_91 = {{4'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_91 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [4:0] _a_size_lookup_T = {io_in_d_bits_source, 3'h0}; // @[Monitor.scala 638:65]
  wire [23:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _a_size_lookup_T_5 = 16'h100 - 16'h1; // @[Monitor.scala 609:57]
  wire [23:0] _GEN_93 = {{8'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 638:91]
  wire [23:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_93; // @[Monitor.scala 638:91]
  wire [23:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[23:1]}; // @[Monitor.scala 638:144]
  wire  _T_3006 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [3:0] _a_set_wo_ready_T = 4'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _GEN_27 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_3009 = _a_first_T & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [4:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 5'h1; // @[Monitor.scala 655:59]
  wire [3:0] _GEN_95 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [4:0] _a_opcodes_set_T = {{1'd0}, _GEN_95}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = _a_first_T & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [34:0] _GEN_1 = {{31'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [34:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [4:0] _a_sizes_set_T = {io_in_a_bits_source, 3'h0}; // @[Monitor.scala 657:77]
  wire [4:0] a_sizes_set_interm = _a_first_T & a_first_1 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala 652:72 655:28]
  wire [35:0] _GEN_2 = {{31'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [35:0] _a_sizes_set_T_1 = _GEN_2 << _a_sizes_set_T; // @[Monitor.scala 657:52]
  wire [2:0] _T_3011 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_3013 = ~_T_3011[0]; // @[Monitor.scala 658:17]
  wire [3:0] _GEN_28 = _a_first_T & a_first_1 ? _a_set_wo_ready_T : 4'h0; // @[Monitor.scala 652:72 653:28]
  wire [34:0] _GEN_31 = _a_first_T & a_first_1 ? _a_opcodes_set_T_1 : 35'h0; // @[Monitor.scala 652:72 656:28]
  wire [35:0] _GEN_32 = _a_first_T & a_first_1 ? _a_sizes_set_T_1 : 36'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_3017 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_3019 = ~_T_1308; // @[Monitor.scala 671:74]
  wire  _T_3020 = io_in_d_valid & d_first_1 & ~_T_1308; // @[Monitor.scala 671:71]
  wire [3:0] _d_clr_wo_ready_T = 4'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _GEN_33 = io_in_d_valid & d_first_1 & ~_T_1308 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 671:90 672:22]
  wire [46:0] _GEN_3 = {{31'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [46:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [46:0] _GEN_4 = {{31'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 678:74]
  wire [46:0] _d_sizes_clr_T_5 = _GEN_4 << _a_size_lookup_T; // @[Monitor.scala 678:74]
  wire [3:0] _GEN_34 = _d_first_T & d_first_1 & _T_3019 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 675:91 676:21]
  wire [46:0] _GEN_35 = _d_first_T & d_first_1 & _T_3019 ? _d_opcodes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 677:21]
  wire [46:0] _GEN_36 = _d_first_T & d_first_1 & _T_3019 ? _d_sizes_clr_T_5 : 47'h0; // @[Monitor.scala 675:91 678:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_3006 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2:0] _T_3030 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_3032 = _T_3030[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_39 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_40 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_39; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_41 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_40; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_42 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_41; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_43 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_42; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_44 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_43; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_51 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_42; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_52 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_51; // @[Monitor.scala 686:{39,39}]
  wire  _T_3037 = io_in_d_bits_opcode == _GEN_52; // @[Monitor.scala 686:39]
  wire  _T_3038 = io_in_d_bits_opcode == _GEN_44 | _T_3037; // @[Monitor.scala 685:77]
  wire  _T_3042 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_55 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_56 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_55; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_57 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_56; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_58 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_57; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_59 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_58; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_60 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_59; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_67 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_58; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_68 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_67; // @[Monitor.scala 690:{38,38}]
  wire  _T_3049 = io_in_d_bits_opcode == _GEN_68; // @[Monitor.scala 690:38]
  wire  _T_3050 = io_in_d_bits_opcode == _GEN_60 | _T_3049; // @[Monitor.scala 689:72]
  wire [7:0] a_size_lookup = _a_size_lookup_T_7[7:0];
  wire [7:0] _GEN_97 = {{4'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_3054 = _GEN_97 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_3064 = _T_3017 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_3019; // @[Monitor.scala 694:116]
  wire  _T_3065 = ~io_in_d_ready; // @[Monitor.scala 695:15]
  wire  _T_3066 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2:0] a_set_wo_ready = _GEN_27[2:0];
  wire [2:0] d_clr_wo_ready = _GEN_33[2:0];
  wire  _T_3073 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire [2:0] a_set = _GEN_28[2:0];
  wire [2:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2:0] d_clr = _GEN_34[2:0];
  wire [2:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [11:0] a_opcodes_set = _GEN_31[11:0];
  wire [11:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [11:0] d_opcodes_clr = _GEN_35[11:0];
  wire [11:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [11:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [23:0] a_sizes_set = _GEN_32[23:0];
  wire [23:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [23:0] d_sizes_clr = _GEN_36[23:0];
  wire [23:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala 704:56]
  wire [23:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_3082 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [2:0] inflight_1; // @[Monitor.scala 723:35]
  reg [23:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg [9:0] c_first_counter_1; // @[Edges.scala 228:27]
  wire [9:0] c_first_counter1_1 = c_first_counter_1 - 10'h1; // @[Edges.scala 229:28]
  wire  c_first_1 = c_first_counter_1 == 10'h0; // @[Edges.scala 230:25]
  reg [9:0] d_first_counter_2; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1_2 = d_first_counter_2 - 10'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = d_first_counter_2 == 10'h0; // @[Edges.scala 230:25]
  wire [23:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_size_lookup_T; // @[Monitor.scala 747:42]
  wire [23:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_93; // @[Monitor.scala 747:93]
  wire [23:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[23:1]}; // @[Monitor.scala 747:146]
  wire  _T_3092 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala 67:40]
  wire  _T_3093 = io_in_c_valid & c_first_1 & _T_3092; // @[Monitor.scala 756:37]
  wire [3:0] _c_set_wo_ready_T = 4'h1 << io_in_c_bits_source; // @[OneHot.scala 57:35]
  wire [3:0] _GEN_72 = io_in_c_valid & c_first_1 & _T_3092 ? _c_set_wo_ready_T : 4'h0; // @[Monitor.scala 756:71 757:22]
  wire  _T_3099 = _c_first_T & c_first_1 & _T_3092; // @[Monitor.scala 760:38]
  wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size, 1'h0}; // @[Monitor.scala 763:51]
  wire [4:0] _c_sizes_set_interm_T_1 = _c_sizes_set_interm_T | 5'h1; // @[Monitor.scala 763:59]
  wire [4:0] _c_sizes_set_T = {io_in_c_bits_source, 3'h0}; // @[Monitor.scala 765:77]
  wire [4:0] c_sizes_set_interm = _c_first_T & c_first_1 & _T_3092 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala 760:72 763:28]
  wire [35:0] _GEN_5 = {{31'd0}, c_sizes_set_interm}; // @[Monitor.scala 765:52]
  wire [35:0] _c_sizes_set_T_1 = _GEN_5 << _c_sizes_set_T; // @[Monitor.scala 765:52]
  wire [2:0] _T_3100 = inflight_1 >> io_in_c_bits_source; // @[Monitor.scala 766:26]
  wire  _T_3102 = ~_T_3100[0]; // @[Monitor.scala 766:17]
  wire [3:0] _GEN_73 = _c_first_T & c_first_1 & _T_3092 ? _c_set_wo_ready_T : 4'h0; // @[Monitor.scala 760:72 761:28]
  wire [35:0] _GEN_77 = _c_first_T & c_first_1 & _T_3092 ? _c_sizes_set_T_1 : 36'h0; // @[Monitor.scala 760:72 765:28]
  wire  _T_3106 = io_in_d_valid & d_first_2; // @[Monitor.scala 779:26]
  wire  _T_3108 = io_in_d_valid & d_first_2 & _T_1308; // @[Monitor.scala 779:71]
  wire [3:0] _GEN_78 = io_in_d_valid & d_first_2 & _T_1308 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 779:89 780:22]
  wire [3:0] _GEN_79 = _d_first_T & d_first_2 & _T_1308 ? _d_clr_wo_ready_T : 4'h0; // @[Monitor.scala 783:90 784:21]
  wire [46:0] _GEN_81 = _d_first_T & d_first_2 & _T_1308 ? _d_sizes_clr_T_5 : 47'h0; // @[Monitor.scala 783:90 786:21]
  wire  _same_cycle_resp_T_8 = io_in_c_bits_source == io_in_d_bits_source; // @[Monitor.scala 790:113]
  wire  same_cycle_resp_1 = _T_3093 & io_in_c_bits_source == io_in_d_bits_source; // @[Monitor.scala 790:88]
  wire [2:0] _T_3116 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire  _T_3118 = _T_3116[0] | same_cycle_resp_1; // @[Monitor.scala 791:49]
  wire  _T_3122 = io_in_d_bits_size == io_in_c_bits_size; // @[Monitor.scala 793:36]
  wire [7:0] c_size_lookup = _c_size_lookup_T_7[7:0];
  wire  _T_3126 = _GEN_97 == c_size_lookup; // @[Monitor.scala 795:36]
  wire  _T_3135 = _T_3106 & c_first_1 & io_in_c_valid & _same_cycle_resp_T_8 & _T_1308; // @[Monitor.scala 799:116]
  wire  _T_3137 = _T_3065 | io_in_c_ready; // @[Monitor.scala 800:32]
  wire [2:0] c_set_wo_ready = _GEN_72[2:0];
  wire  _T_3141 = |c_set_wo_ready; // @[Monitor.scala 804:28]
  wire [2:0] d_clr_wo_ready_1 = _GEN_78[2:0];
  wire  _T_3142 = c_set_wo_ready != d_clr_wo_ready_1; // @[Monitor.scala 805:31]
  wire [2:0] c_set = _GEN_73[2:0];
  wire [2:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala 809:35]
  wire [2:0] d_clr_1 = _GEN_79[2:0];
  wire [2:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [2:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [23:0] c_sizes_set = _GEN_77[23:0];
  wire [23:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala 811:41]
  wire [23:0] d_sizes_clr_1 = _GEN_81[23:0];
  wire [23:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
  wire [23:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_3151 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  reg [3:0] inflight_2; // @[Monitor.scala 823:27]
  reg [9:0] d_first_counter_3; // @[Edges.scala 228:27]
  wire [9:0] d_first_counter1_3 = d_first_counter_3 - 10'h1; // @[Edges.scala 229:28]
  wire  d_first_3 = d_first_counter_3 == 10'h0; // @[Edges.scala 230:25]
  wire  _T_3163 = io_in_d_bits_opcode[2] & ~io_in_d_bits_opcode[1]; // @[Edges.scala 70:40]
  wire  _T_3164 = _d_first_T & d_first_3 & _T_3163; // @[Monitor.scala 829:38]
  wire [3:0] _d_set_T = 4'h1 << io_in_d_bits_sink; // @[OneHot.scala 57:35]
  wire [3:0] _T_3165 = inflight_2 >> io_in_d_bits_sink; // @[Monitor.scala 831:23]
  wire  _T_3167 = ~_T_3165[0]; // @[Monitor.scala 831:14]
  wire [3:0] d_set = _d_first_T & d_first_3 & _T_3163 ? _d_set_T : 4'h0; // @[Monitor.scala 829:72 830:13]
  wire  _T_3171 = io_in_e_ready & io_in_e_valid; // @[Decoupled.scala 50:35]
  wire [3:0] _e_clr_T = 4'h1 << io_in_e_bits_sink; // @[OneHot.scala 57:35]
  wire [3:0] _T_3174 = d_set | inflight_2; // @[Monitor.scala 837:24]
  wire [3:0] _T_3175 = _T_3174 >> io_in_e_bits_sink; // @[Monitor.scala 837:35]
  wire [3:0] e_clr = _T_3171 ? _e_clr_T : 4'h0; // @[Monitor.scala 835:73 836:13]
  wire [3:0] _inflight_T_6 = inflight_2 | d_set; // @[Monitor.scala 842:27]
  wire [3:0] _inflight_T_7 = ~e_clr; // @[Monitor.scala 842:38]
  wire [3:0] _inflight_T_8 = _inflight_T_6 & _inflight_T_7; // @[Monitor.scala 842:36]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 10'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter <= a_first_beats1_decode;
        end else begin
          a_first_counter <= 10'h0;
        end
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (_a_first_T & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter <= d_first_beats1_decode;
        end else begin
          d_first_counter <= 10'h0;
        end
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
    end
    if (_d_first_T & d_first) begin // @[Monitor.scala 549:32]
      denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      b_first_counter <= 10'h0; // @[Edges.scala 228:27]
    end else if (b_first_done) begin // @[Edges.scala 234:17]
      if (b_first) begin // @[Edges.scala 235:21]
        b_first_counter <= 10'h0;
      end else begin
        b_first_counter <= b_first_counter1;
      end
    end
    if (b_first_done & b_first) begin // @[Monitor.scala 419:32]
      opcode_2 <= io_in_b_bits_opcode; // @[Monitor.scala 420:15]
    end
    if (b_first_done & b_first) begin // @[Monitor.scala 419:32]
      param_2 <= io_in_b_bits_param; // @[Monitor.scala 421:15]
    end
    if (b_first_done & b_first) begin // @[Monitor.scala 419:32]
      size_2 <= io_in_b_bits_size; // @[Monitor.scala 422:15]
    end
    if (b_first_done & b_first) begin // @[Monitor.scala 419:32]
      source_2 <= io_in_b_bits_source; // @[Monitor.scala 423:15]
    end
    if (b_first_done & b_first) begin // @[Monitor.scala 419:32]
      address_1 <= io_in_b_bits_address; // @[Monitor.scala 424:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      c_first_counter <= 10'h0; // @[Edges.scala 228:27]
    end else if (_c_first_T) begin // @[Edges.scala 234:17]
      if (c_first) begin // @[Edges.scala 235:21]
        if (c_first_beats1_opdata) begin // @[Edges.scala 220:14]
          c_first_counter <= c_first_beats1_decode;
        end else begin
          c_first_counter <= 10'h0;
        end
      end else begin
        c_first_counter <= c_first_counter1;
      end
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      opcode_3 <= io_in_c_bits_opcode; // @[Monitor.scala 525:15]
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      param_3 <= io_in_c_bits_param; // @[Monitor.scala 526:15]
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      size_3 <= io_in_c_bits_size; // @[Monitor.scala 527:15]
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      source_3 <= io_in_c_bits_source; // @[Monitor.scala 528:15]
    end
    if (_c_first_T & c_first) begin // @[Monitor.scala 524:32]
      address_2 <= io_in_c_bits_address; // @[Monitor.scala 529:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 3'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 12'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 24'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_a_first_T) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        if (a_first_beats1_opdata) begin // @[Edges.scala 220:14]
          a_first_counter_1 <= a_first_beats1_decode;
        end else begin
          a_first_counter_1 <= 10'h0;
        end
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_1 <= d_first_beats1_decode;
        end else begin
          d_first_counter_1 <= 10'h0;
        end
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (_a_first_T | _d_first_T) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 3'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 24'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      c_first_counter_1 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_c_first_T) begin // @[Edges.scala 234:17]
      if (c_first_1) begin // @[Edges.scala 235:21]
        if (c_first_beats1_opdata) begin // @[Edges.scala 220:14]
          c_first_counter_1 <= c_first_beats1_decode;
        end else begin
          c_first_counter_1 <= 10'h0;
        end
      end else begin
        c_first_counter_1 <= c_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_2 <= d_first_beats1_decode;
        end else begin
          d_first_counter_2 <= 10'h0;
        end
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (_c_first_T | _d_first_T) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    if (reset) begin // @[Monitor.scala 823:27]
      inflight_2 <= 4'h0; // @[Monitor.scala 823:27]
    end else begin
      inflight_2 <= _inflight_T_8; // @[Monitor.scala 842:14]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_3 <= 10'h0; // @[Edges.scala 228:27]
    end else if (_d_first_T) begin // @[Edges.scala 234:17]
      if (d_first_3) begin // @[Edges.scala 235:21]
        if (d_first_beats1_opdata) begin // @[Edges.scala 220:14]
          d_first_counter_3 <= d_first_beats1_decode;
        end else begin
          d_first_counter_3 <= 10'h0;
        end
      end else begin
        d_first_counter_3 <= d_first_counter1_3;
      end
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_141 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_141) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_249 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_249) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_263 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_263) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_268 & (io_in_a_valid & _T_33 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_33 & ~reset & ~_T_268) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_141 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_T_141) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_249 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_T_249) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_263 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_T_263) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_510 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_T_510) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_268 & (io_in_a_valid & _T_276 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_276 & ~reset & ~_T_268) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_42 & (io_in_a_valid & _T_523 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_523 & ~reset & ~_T_42) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_636 & (io_in_a_valid & _T_523 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_523 & ~reset & ~_T_636) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_523 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_523 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_523 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_523 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_646 & (io_in_a_valid & _T_523 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_523 & ~reset & ~_T_646) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_650 & (io_in_a_valid & _T_523 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_523 & ~reset & ~_T_650) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_771 & (io_in_a_valid & _T_658 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_658 & ~reset & ~_T_771) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_658 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_658 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_658 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_658 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_646 & (io_in_a_valid & _T_658 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_658 & ~reset & ~_T_646) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_650 & (io_in_a_valid & _T_658 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_658 & ~reset & ~_T_650) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_902 & (io_in_a_valid & _T_789 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_789 & ~reset & ~_T_902) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_789 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_789 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_789 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_789 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_646 & (io_in_a_valid & _T_789 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_789 & ~reset & ~_T_646) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_918 & (io_in_a_valid & _T_789 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_789 & ~reset & ~_T_918) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1030 & (io_in_a_valid & _T_922 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_922 & ~reset & ~_T_1030) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_922 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_922 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_922 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_922 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1040 & (io_in_a_valid & _T_922 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_922 & ~reset & ~_T_1040) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_650 & (io_in_a_valid & _T_922 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_922 & ~reset & ~_T_650) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1030 & (io_in_a_valid & _T_1048 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1048 & ~reset & ~_T_1030) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_1048 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1048 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_1048 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1048 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1166 & (io_in_a_valid & _T_1048 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1048 & ~reset & ~_T_1166) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_650 & (io_in_a_valid & _T_1048 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1048 & ~reset & ~_T_650) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1282 & (io_in_a_valid & _T_1174 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1174 & ~reset & ~_T_1282) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok & (io_in_a_valid & _T_1174 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1174 & ~reset & ~source_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_1174 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1174 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1292 & (io_in_a_valid & _T_1174 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1174 & ~reset & ~_T_1292) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_650 & (io_in_a_valid & _T_1174 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_1174 & ~reset & ~_T_650) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1304 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_1304) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1308 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1308 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1312 & (io_in_d_valid & _T_1308 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1308 & _T_2 & ~_T_1312) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1316 & (io_in_d_valid & _T_1308 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1308 & _T_2 & ~_T_1316) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1320 & (io_in_d_valid & _T_1308 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1308 & _T_2 & ~_T_1320) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1324 & (io_in_d_valid & _T_1308 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1308 & _T_2 & ~_T_1324) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is denied (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1328 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1328 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1312 & (io_in_d_valid & _T_1328 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1328 & _T_2 & ~_T_1312) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1339 & (io_in_d_valid & _T_1328 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1328 & _T_2 & ~_T_1339) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid cap param (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1343 & (io_in_d_valid & _T_1328 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1328 & _T_2 & ~_T_1343) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries toN param (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1320 & (io_in_d_valid & _T_1328 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1328 & _T_2 & ~_T_1320) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is corrupt (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1356 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1356 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1312 & (io_in_d_valid & _T_1356 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1356 & _T_2 & ~_T_1312) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1339 & (io_in_d_valid & _T_1356 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1356 & _T_2 & ~_T_1339) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1343 & (io_in_d_valid & _T_1356 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1356 & _T_2 & ~_T_1343) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries toN param (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1376 & (io_in_d_valid & _T_1356 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1356 & _T_2 & ~_T_1376) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1385 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1385 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1316 & (io_in_d_valid & _T_1385 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1385 & _T_2 & ~_T_1316) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid param (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1320 & (io_in_d_valid & _T_1385 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1385 & _T_2 & ~_T_1320) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is corrupt (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1402 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1402 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1316 & (io_in_d_valid & _T_1402 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1402 & _T_2 & ~_T_1316) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1376 & (io_in_d_valid & _T_1402 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1402 & _T_2 & ~_T_1376) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_1 & (io_in_d_valid & _T_1420 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1420 & _T_2 & ~source_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1316 & (io_in_d_valid & _T_1420 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1420 & _T_2 & ~_T_1316) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid param (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1320 & (io_in_d_valid & _T_1420 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_1420 & _T_2 & ~_T_1320) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is corrupt (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1437 & (io_in_b_valid & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & ~reset & ~_T_1437) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel has invalid opcode (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1575 & (io_in_b_valid & _T_1470 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1470 & _T_2 & ~_T_1575) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~address_ok & (io_in_b_valid & _T_1470 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1470 & _T_2 & ~address_ok) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Probe carries unmanaged address (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~legal_source & (io_in_b_valid & _T_1470 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1470 & _T_2 & ~legal_source) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Probe carries source that is not first source (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_1 & (io_in_b_valid & _T_1470 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1470 & _T_2 & ~is_aligned_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Probe address not aligned to size (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1588 & (io_in_b_valid & _T_1470 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1470 & _T_2 & ~_T_1588) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Probe carries invalid cap param (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1592 & (io_in_b_valid & _T_1470 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1470 & _T_2 & ~_T_1592) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Probe contains invalid mask (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1596 & (io_in_b_valid & _T_1470 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1470 & _T_2 & ~_T_1596) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Probe is corrupt (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_b_valid & _T_1600 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1600 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1581 & (io_in_b_valid & _T_1600 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1600 & ~reset & _T_1581) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Get carries unmanaged address (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1584 & (io_in_b_valid & _T_1600 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1600 & ~reset & _T_1584) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Get carries source that is not first source (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1587 & (io_in_b_valid & _T_1600 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1600 & ~reset & _T_1587) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Get address not aligned to size (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1709 & (io_in_b_valid & _T_1600 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1600 & ~reset & ~_T_1709) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Get carries invalid param (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1595 & (io_in_b_valid & _T_1600 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1600 & ~reset & _T_1595) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Get contains invalid mask (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1599 & (io_in_b_valid & _T_1600 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1600 & ~reset & _T_1599) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Get is corrupt (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_b_valid & _T_1721 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1721 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1581 & (io_in_b_valid & _T_1721 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1721 & ~reset & _T_1581) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1584 & (io_in_b_valid & _T_1721 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1721 & ~reset & _T_1584) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1587 & (io_in_b_valid & _T_1721 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1721 & ~reset & _T_1587) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel PutFull address not aligned to size (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1709 & (io_in_b_valid & _T_1721 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1721 & ~reset & ~_T_1709) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel PutFull carries invalid param (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1595 & (io_in_b_valid & _T_1721 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1721 & ~reset & _T_1595) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel PutFull contains invalid mask (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_b_valid & _T_1838 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1838 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1581 & (io_in_b_valid & _T_1838 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1838 & ~reset & _T_1581) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1584 & (io_in_b_valid & _T_1838 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1838 & ~reset & _T_1584) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1587 & (io_in_b_valid & _T_1838 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1838 & ~reset & _T_1587) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1709 & (io_in_b_valid & _T_1838 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1838 & ~reset & ~_T_1709) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel PutPartial carries invalid param (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_1953 & (io_in_b_valid & _T_1838 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1838 & ~reset & ~_T_1953) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_b_valid & _T_1957 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1957 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1581 & (io_in_b_valid & _T_1957 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1957 & ~reset & _T_1581) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1584 & (io_in_b_valid & _T_1957 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1957 & ~reset & _T_1584) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1587 & (io_in_b_valid & _T_1957 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1957 & ~reset & _T_1587) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1595 & (io_in_b_valid & _T_1957 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_1957 & ~reset & _T_1595) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_b_valid & _T_2074 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2074 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1581 & (io_in_b_valid & _T_2074 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2074 & ~reset & _T_1581) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Logical carries unmanaged address (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1584 & (io_in_b_valid & _T_2074 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2074 & ~reset & _T_1584) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Logical carries source that is not first source (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1587 & (io_in_b_valid & _T_2074 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2074 & ~reset & _T_1587) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Logical address not aligned to size (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1595 & (io_in_b_valid & _T_2074 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2074 & ~reset & _T_1595) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Logical contains invalid mask (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_b_valid & _T_2191 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2191 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1581 & (io_in_b_valid & _T_2191 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2191 & ~reset & _T_1581) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Hint carries unmanaged address (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1584 & (io_in_b_valid & _T_2191 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2191 & ~reset & _T_1584) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Hint carries source that is not first source (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1587 & (io_in_b_valid & _T_2191 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2191 & ~reset & _T_1587) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Hint address not aligned to size (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1595 & (io_in_b_valid & _T_2191 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2191 & ~reset & _T_1595) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Hint contains invalid mask (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_1599 & (io_in_b_valid & _T_2191 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_b_valid & _T_2191 & ~reset & _T_1599) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel Hint is corrupt (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~address_ok_1 & (io_in_c_valid & _T_2341 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2341 & ~reset & ~address_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_2 & (io_in_c_valid & _T_2341 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2341 & ~reset & ~source_ok_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2348 & (io_in_c_valid & _T_2341 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2341 & ~reset & ~_T_2348) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_2341 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2341 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2355 & (io_in_c_valid & _T_2341 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2341 & ~reset & ~_T_2355) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~address_ok_1 & (io_in_c_valid & _T_2363 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2363 & ~reset & ~address_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_2 & (io_in_c_valid & _T_2363 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2363 & ~reset & ~source_ok_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2348 & (io_in_c_valid & _T_2363 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2363 & ~reset & ~_T_2348) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_2363 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2363 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2355 & (io_in_c_valid & _T_2363 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2363 & ~reset & ~_T_2355) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2489 & (io_in_c_valid & _T_2381 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2381 & ~reset & ~_T_2489) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2597 & (io_in_c_valid & _T_2381 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2381 & ~reset & ~_T_2597) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_2 & (io_in_c_valid & _T_2381 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2381 & ~reset & ~source_ok_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release carries invalid source ID (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2348 & (io_in_c_valid & _T_2381 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2381 & ~reset & ~_T_2348) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release smaller than a beat (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_2381 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2381 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release address not aligned to size (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2355 & (io_in_c_valid & _T_2381 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2381 & ~reset & ~_T_2355) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel Release carries invalid report param (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2489 & (io_in_c_valid & _T_2619 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2619 & ~reset & ~_T_2489) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2597 & (io_in_c_valid & _T_2619 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2619 & ~reset & ~_T_2597) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_2 & (io_in_c_valid & _T_2619 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2619 & ~reset & ~source_ok_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2348 & (io_in_c_valid & _T_2619 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2619 & ~reset & ~_T_2348) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_2619 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2619 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2355 & (io_in_c_valid & _T_2619 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2619 & ~reset & ~_T_2355) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~address_ok_1 & (io_in_c_valid & _T_2853 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2853 & ~reset & ~address_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_2 & (io_in_c_valid & _T_2853 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2853 & ~reset & ~source_ok_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_2853 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2853 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2863 & (io_in_c_valid & _T_2853 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2853 & ~reset & ~_T_2863) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAck carries invalid param (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~address_ok_1 & (io_in_c_valid & _T_2871 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2871 & ~reset & ~address_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_2 & (io_in_c_valid & _T_2871 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2871 & ~reset & ~source_ok_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_2871 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2871 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2863 & (io_in_c_valid & _T_2871 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2871 & ~reset & ~_T_2863) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~address_ok_1 & (io_in_c_valid & _T_2885 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2885 & ~reset & ~address_ok_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~source_ok_2 & (io_in_c_valid & _T_2885 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2885 & ~reset & ~source_ok_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned_2 & (io_in_c_valid & _T_2885 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2885 & ~reset & ~is_aligned_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck address not aligned to size (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2863 & (io_in_c_valid & _T_2885 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_c_valid & _T_2885 & ~reset & ~_T_2863) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel HintAck carries invalid param (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2908 & (_T_2907 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2907 & ~reset & ~_T_2908) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2912 & (_T_2907 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2907 & ~reset & ~_T_2912) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2916 & (_T_2907 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2907 & ~reset & ~_T_2916) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2920 & (_T_2907 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2907 & ~reset & ~_T_2920) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2924 & (_T_2907 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2907 & ~reset & ~_T_2924) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2932 & (_T_2931 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2931 & _T_2 & ~_T_2932) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2936 & (_T_2931 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2931 & _T_2 & ~_T_2936) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel param changed within multibeat operation (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2940 & (_T_2931 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2931 & _T_2 & ~_T_2940) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2944 & (_T_2931 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2931 & _T_2 & ~_T_2944) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2948 & (_T_2931 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2931 & _T_2 & ~_T_2948) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel sink changed with multibeat operation (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2952 & (_T_2931 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2931 & _T_2 & ~_T_2952) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel denied changed with multibeat operation (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2960 & (_T_2959 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2959 & ~reset & ~_T_2960) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2964 & (_T_2959 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2959 & ~reset & ~_T_2964) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel param changed within multibeat operation (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2968 & (_T_2959 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2959 & ~reset & ~_T_2968) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel size changed within multibeat operation (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2972 & (_T_2959 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2959 & ~reset & ~_T_2972) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel source changed within multibeat operation (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2976 & (_T_2959 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2959 & ~reset & ~_T_2976) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2984 & (_T_2983 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2983 & ~reset & ~_T_2984) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2988 & (_T_2983 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2983 & ~reset & ~_T_2988) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel param changed within multibeat operation (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2992 & (_T_2983 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2983 & ~reset & ~_T_2992) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel size changed within multibeat operation (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_2996 & (_T_2983 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2983 & ~reset & ~_T_2996) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel source changed within multibeat operation (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3000 & (_T_2983 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2983 & ~reset & ~_T_3000) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel address changed with multibeat operation (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3013 & (_T_3009 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3009 & ~reset & ~_T_3013) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3032 & (_T_3020 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3020 & _T_2 & ~_T_3032) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3038 & (_T_3020 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3020 & same_cycle_resp & _T_2 & ~_T_3038) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3042 & (_T_3020 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3020 & same_cycle_resp & _T_2 & ~_T_3042) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3050 & (_T_3020 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3020 & ~same_cycle_resp & _T_2 & ~_T_3050) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3054 & (_T_3020 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3020 & ~same_cycle_resp & _T_2 & ~_T_3054) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3066 & (_T_3064 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3064 & _T_2 & ~_T_3066) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3073 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_3073) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 3 (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3082 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_3082) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3102 & (_T_3099 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3099 & ~reset & ~_T_3102) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' channel re-used a source ID (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3118 & (_T_3108 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3108 & _T_2 & ~_T_3118) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3122 & (_T_3108 & same_cycle_resp_1 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3108 & same_cycle_resp_1 & _T_2 & ~_T_3122) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3126 & (_T_3108 & ~same_cycle_resp_1 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3108 & ~same_cycle_resp_1 & _T_2 & ~_T_3126) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3137 & (_T_3135 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3135 & _T_2 & ~_T_3137) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3142 & (_T_3141 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3141 & _T_2 & ~_T_3142) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'C' and 'D' concurrent, despite minlatency 3 (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3151 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_3151) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3167 & (_T_3164 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3164 & _T_2 & ~_T_3167) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel re-used a sink ID (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_3175[0] & (_T_3171 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3171 & ~reset & ~_T_3175[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:61:80)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[9:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[30:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[9:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  param_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  size_1 = _RAND_9[3:0];
  _RAND_10 = {1{`RANDOM}};
  source_1 = _RAND_10[1:0];
  _RAND_11 = {1{`RANDOM}};
  sink = _RAND_11[1:0];
  _RAND_12 = {1{`RANDOM}};
  denied = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  b_first_counter = _RAND_13[9:0];
  _RAND_14 = {1{`RANDOM}};
  opcode_2 = _RAND_14[2:0];
  _RAND_15 = {1{`RANDOM}};
  param_2 = _RAND_15[1:0];
  _RAND_16 = {1{`RANDOM}};
  size_2 = _RAND_16[3:0];
  _RAND_17 = {1{`RANDOM}};
  source_2 = _RAND_17[1:0];
  _RAND_18 = {1{`RANDOM}};
  address_1 = _RAND_18[30:0];
  _RAND_19 = {1{`RANDOM}};
  c_first_counter = _RAND_19[9:0];
  _RAND_20 = {1{`RANDOM}};
  opcode_3 = _RAND_20[2:0];
  _RAND_21 = {1{`RANDOM}};
  param_3 = _RAND_21[2:0];
  _RAND_22 = {1{`RANDOM}};
  size_3 = _RAND_22[3:0];
  _RAND_23 = {1{`RANDOM}};
  source_3 = _RAND_23[1:0];
  _RAND_24 = {1{`RANDOM}};
  address_2 = _RAND_24[30:0];
  _RAND_25 = {1{`RANDOM}};
  inflight = _RAND_25[2:0];
  _RAND_26 = {1{`RANDOM}};
  inflight_opcodes = _RAND_26[11:0];
  _RAND_27 = {1{`RANDOM}};
  inflight_sizes = _RAND_27[23:0];
  _RAND_28 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_28[9:0];
  _RAND_29 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_29[9:0];
  _RAND_30 = {1{`RANDOM}};
  watchdog = _RAND_30[31:0];
  _RAND_31 = {1{`RANDOM}};
  inflight_1 = _RAND_31[2:0];
  _RAND_32 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_32[23:0];
  _RAND_33 = {1{`RANDOM}};
  c_first_counter_1 = _RAND_33[9:0];
  _RAND_34 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_34[9:0];
  _RAND_35 = {1{`RANDOM}};
  watchdog_1 = _RAND_35[31:0];
  _RAND_36 = {1{`RANDOM}};
  inflight_2 = _RAND_36[3:0];
  _RAND_37 = {1{`RANDOM}};
  d_first_counter_3 = _RAND_37[9:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_15(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [2:0]  io_enq_bits_opcode,
  input  [2:0]  io_enq_bits_param,
  input  [3:0]  io_enq_bits_size,
  input  [1:0]  io_enq_bits_source,
  input  [30:0] io_enq_bits_address,
  input  [3:0]  io_enq_bits_mask,
  input  [31:0] io_enq_bits_data,
  input         io_deq_ready,
  output        io_deq_valid,
  output [2:0]  io_deq_bits_opcode,
  output [2:0]  io_deq_bits_param,
  output [3:0]  io_deq_bits_size,
  output [1:0]  io_deq_bits_source,
  output [30:0] io_deq_bits_address,
  output [3:0]  io_deq_bits_mask,
  output [31:0] io_deq_bits_data,
  output        io_deq_bits_corrupt
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
`endif // RANDOMIZE_REG_INIT
  reg [2:0] ram_opcode [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_opcode_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_opcode_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [2:0] ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_en; // @[Decoupled.scala 259:95]
  reg [2:0] ram_param [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_param_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_param_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [2:0] ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_param_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_param_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_param_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_param_MPORT_en; // @[Decoupled.scala 259:95]
  reg [3:0] ram_size [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [3:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [3:0] ram_size_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_en; // @[Decoupled.scala 259:95]
  reg [1:0] ram_source [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [1:0] ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [1:0] ram_source_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_en; // @[Decoupled.scala 259:95]
  reg [30:0] ram_address [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_address_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_address_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [30:0] ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [30:0] ram_address_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_address_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_address_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_address_MPORT_en; // @[Decoupled.scala 259:95]
  reg [3:0] ram_mask [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_mask_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_mask_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [3:0] ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [3:0] ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_mask_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_mask_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_mask_MPORT_en; // @[Decoupled.scala 259:95]
  reg [31:0] ram_data [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_data_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_data_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [31:0] ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [31:0] ram_data_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_data_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_data_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_data_MPORT_en; // @[Decoupled.scala 259:95]
  reg  ram_corrupt [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_en; // @[Decoupled.scala 259:95]
  reg  value; // @[Counter.scala 62:40]
  reg  value_1; // @[Counter.scala 62:40]
  reg  maybe_full; // @[Decoupled.scala 262:27]
  wire  ptr_match = value == value_1; // @[Decoupled.scala 263:33]
  wire  empty = ptr_match & ~maybe_full; // @[Decoupled.scala 264:25]
  wire  full = ptr_match & maybe_full; // @[Decoupled.scala 265:24]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
  wire  do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
  assign ram_opcode_io_deq_bits_MPORT_en = 1'h1;
  assign ram_opcode_io_deq_bits_MPORT_addr = value_1;
  assign ram_opcode_io_deq_bits_MPORT_data = ram_opcode[ram_opcode_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_opcode_MPORT_data = io_enq_bits_opcode;
  assign ram_opcode_MPORT_addr = value;
  assign ram_opcode_MPORT_mask = 1'h1;
  assign ram_opcode_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_param_io_deq_bits_MPORT_en = 1'h1;
  assign ram_param_io_deq_bits_MPORT_addr = value_1;
  assign ram_param_io_deq_bits_MPORT_data = ram_param[ram_param_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_param_MPORT_data = io_enq_bits_param;
  assign ram_param_MPORT_addr = value;
  assign ram_param_MPORT_mask = 1'h1;
  assign ram_param_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_size_io_deq_bits_MPORT_en = 1'h1;
  assign ram_size_io_deq_bits_MPORT_addr = value_1;
  assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_size_MPORT_data = io_enq_bits_size;
  assign ram_size_MPORT_addr = value;
  assign ram_size_MPORT_mask = 1'h1;
  assign ram_size_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_source_io_deq_bits_MPORT_en = 1'h1;
  assign ram_source_io_deq_bits_MPORT_addr = value_1;
  assign ram_source_io_deq_bits_MPORT_data = ram_source[ram_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_source_MPORT_data = io_enq_bits_source;
  assign ram_source_MPORT_addr = value;
  assign ram_source_MPORT_mask = 1'h1;
  assign ram_source_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_address_io_deq_bits_MPORT_en = 1'h1;
  assign ram_address_io_deq_bits_MPORT_addr = value_1;
  assign ram_address_io_deq_bits_MPORT_data = ram_address[ram_address_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_address_MPORT_data = io_enq_bits_address;
  assign ram_address_MPORT_addr = value;
  assign ram_address_MPORT_mask = 1'h1;
  assign ram_address_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_mask_io_deq_bits_MPORT_en = 1'h1;
  assign ram_mask_io_deq_bits_MPORT_addr = value_1;
  assign ram_mask_io_deq_bits_MPORT_data = ram_mask[ram_mask_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_mask_MPORT_data = io_enq_bits_mask;
  assign ram_mask_MPORT_addr = value;
  assign ram_mask_MPORT_mask = 1'h1;
  assign ram_mask_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_data_io_deq_bits_MPORT_en = 1'h1;
  assign ram_data_io_deq_bits_MPORT_addr = value_1;
  assign ram_data_io_deq_bits_MPORT_data = ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_data_MPORT_data = io_enq_bits_data;
  assign ram_data_MPORT_addr = value;
  assign ram_data_MPORT_mask = 1'h1;
  assign ram_data_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_corrupt_io_deq_bits_MPORT_en = 1'h1;
  assign ram_corrupt_io_deq_bits_MPORT_addr = value_1;
  assign ram_corrupt_io_deq_bits_MPORT_data = ram_corrupt[ram_corrupt_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_corrupt_MPORT_data = 1'h0;
  assign ram_corrupt_MPORT_addr = value;
  assign ram_corrupt_MPORT_mask = 1'h1;
  assign ram_corrupt_MPORT_en = io_enq_ready & io_enq_valid;
  assign io_enq_ready = ~full; // @[Decoupled.scala 289:19]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 288:19]
  assign io_deq_bits_opcode = ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_param = ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_size = ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_source = ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_address = ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_mask = ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_data = ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_corrupt = ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  always @(posedge clock) begin
    if (ram_opcode_MPORT_en & ram_opcode_MPORT_mask) begin
      ram_opcode[ram_opcode_MPORT_addr] <= ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_param_MPORT_en & ram_param_MPORT_mask) begin
      ram_param[ram_param_MPORT_addr] <= ram_param_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
      ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_source_MPORT_en & ram_source_MPORT_mask) begin
      ram_source[ram_source_MPORT_addr] <= ram_source_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_address_MPORT_en & ram_address_MPORT_mask) begin
      ram_address[ram_address_MPORT_addr] <= ram_address_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_mask_MPORT_en & ram_mask_MPORT_mask) begin
      ram_mask[ram_mask_MPORT_addr] <= ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_data_MPORT_en & ram_data_MPORT_mask) begin
      ram_data[ram_data_MPORT_addr] <= ram_data_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_corrupt_MPORT_en & ram_corrupt_MPORT_mask) begin
      ram_corrupt[ram_corrupt_MPORT_addr] <= ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (reset) begin // @[Counter.scala 62:40]
      value <= 1'h0; // @[Counter.scala 62:40]
    end else if (do_enq) begin // @[Decoupled.scala 272:16]
      value <= value + 1'h1; // @[Counter.scala 78:15]
    end
    if (reset) begin // @[Counter.scala 62:40]
      value_1 <= 1'h0; // @[Counter.scala 62:40]
    end else if (do_deq) begin // @[Decoupled.scala 276:16]
      value_1 <= value_1 + 1'h1; // @[Counter.scala 78:15]
    end
    if (reset) begin // @[Decoupled.scala 262:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 262:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 279:27]
      maybe_full <= do_enq; // @[Decoupled.scala 280:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_opcode[initvar] = _RAND_0[2:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_param[initvar] = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_size[initvar] = _RAND_2[3:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_source[initvar] = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_address[initvar] = _RAND_4[30:0];
  _RAND_5 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_mask[initvar] = _RAND_5[3:0];
  _RAND_6 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_data[initvar] = _RAND_6[31:0];
  _RAND_7 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_corrupt[initvar] = _RAND_7[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_8 = {1{`RANDOM}};
  value = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  value_1 = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  maybe_full = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_16(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [2:0]  io_enq_bits_opcode,
  input  [1:0]  io_enq_bits_param,
  input  [3:0]  io_enq_bits_size,
  input  [1:0]  io_enq_bits_source,
  input  [1:0]  io_enq_bits_sink,
  input         io_enq_bits_denied,
  input  [31:0] io_enq_bits_data,
  input         io_enq_bits_corrupt,
  input         io_deq_ready,
  output        io_deq_valid,
  output [2:0]  io_deq_bits_opcode,
  output [1:0]  io_deq_bits_param,
  output [3:0]  io_deq_bits_size,
  output [1:0]  io_deq_bits_source,
  output [1:0]  io_deq_bits_sink,
  output        io_deq_bits_denied,
  output [31:0] io_deq_bits_data,
  output        io_deq_bits_corrupt
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
`endif // RANDOMIZE_REG_INIT
  reg [2:0] ram_opcode [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_opcode_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_opcode_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [2:0] ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_en; // @[Decoupled.scala 259:95]
  reg [1:0] ram_param [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_param_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_param_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [1:0] ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [1:0] ram_param_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_param_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_param_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_param_MPORT_en; // @[Decoupled.scala 259:95]
  reg [3:0] ram_size [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [3:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [3:0] ram_size_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_en; // @[Decoupled.scala 259:95]
  reg [1:0] ram_source [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [1:0] ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [1:0] ram_source_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_en; // @[Decoupled.scala 259:95]
  reg [1:0] ram_sink [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_sink_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_sink_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [1:0] ram_sink_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [1:0] ram_sink_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_sink_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_sink_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_sink_MPORT_en; // @[Decoupled.scala 259:95]
  reg  ram_denied [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_denied_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_denied_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_denied_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_denied_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_denied_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_denied_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_denied_MPORT_en; // @[Decoupled.scala 259:95]
  reg [31:0] ram_data [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_data_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_data_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [31:0] ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [31:0] ram_data_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_data_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_data_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_data_MPORT_en; // @[Decoupled.scala 259:95]
  reg  ram_corrupt [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_en; // @[Decoupled.scala 259:95]
  reg  value; // @[Counter.scala 62:40]
  reg  value_1; // @[Counter.scala 62:40]
  reg  maybe_full; // @[Decoupled.scala 262:27]
  wire  ptr_match = value == value_1; // @[Decoupled.scala 263:33]
  wire  empty = ptr_match & ~maybe_full; // @[Decoupled.scala 264:25]
  wire  full = ptr_match & maybe_full; // @[Decoupled.scala 265:24]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
  wire  do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
  assign ram_opcode_io_deq_bits_MPORT_en = 1'h1;
  assign ram_opcode_io_deq_bits_MPORT_addr = value_1;
  assign ram_opcode_io_deq_bits_MPORT_data = ram_opcode[ram_opcode_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_opcode_MPORT_data = io_enq_bits_opcode;
  assign ram_opcode_MPORT_addr = value;
  assign ram_opcode_MPORT_mask = 1'h1;
  assign ram_opcode_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_param_io_deq_bits_MPORT_en = 1'h1;
  assign ram_param_io_deq_bits_MPORT_addr = value_1;
  assign ram_param_io_deq_bits_MPORT_data = ram_param[ram_param_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_param_MPORT_data = io_enq_bits_param;
  assign ram_param_MPORT_addr = value;
  assign ram_param_MPORT_mask = 1'h1;
  assign ram_param_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_size_io_deq_bits_MPORT_en = 1'h1;
  assign ram_size_io_deq_bits_MPORT_addr = value_1;
  assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_size_MPORT_data = io_enq_bits_size;
  assign ram_size_MPORT_addr = value;
  assign ram_size_MPORT_mask = 1'h1;
  assign ram_size_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_source_io_deq_bits_MPORT_en = 1'h1;
  assign ram_source_io_deq_bits_MPORT_addr = value_1;
  assign ram_source_io_deq_bits_MPORT_data = ram_source[ram_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_source_MPORT_data = io_enq_bits_source;
  assign ram_source_MPORT_addr = value;
  assign ram_source_MPORT_mask = 1'h1;
  assign ram_source_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_sink_io_deq_bits_MPORT_en = 1'h1;
  assign ram_sink_io_deq_bits_MPORT_addr = value_1;
  assign ram_sink_io_deq_bits_MPORT_data = ram_sink[ram_sink_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_sink_MPORT_data = io_enq_bits_sink;
  assign ram_sink_MPORT_addr = value;
  assign ram_sink_MPORT_mask = 1'h1;
  assign ram_sink_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_denied_io_deq_bits_MPORT_en = 1'h1;
  assign ram_denied_io_deq_bits_MPORT_addr = value_1;
  assign ram_denied_io_deq_bits_MPORT_data = ram_denied[ram_denied_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_denied_MPORT_data = io_enq_bits_denied;
  assign ram_denied_MPORT_addr = value;
  assign ram_denied_MPORT_mask = 1'h1;
  assign ram_denied_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_data_io_deq_bits_MPORT_en = 1'h1;
  assign ram_data_io_deq_bits_MPORT_addr = value_1;
  assign ram_data_io_deq_bits_MPORT_data = ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_data_MPORT_data = io_enq_bits_data;
  assign ram_data_MPORT_addr = value;
  assign ram_data_MPORT_mask = 1'h1;
  assign ram_data_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_corrupt_io_deq_bits_MPORT_en = 1'h1;
  assign ram_corrupt_io_deq_bits_MPORT_addr = value_1;
  assign ram_corrupt_io_deq_bits_MPORT_data = ram_corrupt[ram_corrupt_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_corrupt_MPORT_data = io_enq_bits_corrupt;
  assign ram_corrupt_MPORT_addr = value;
  assign ram_corrupt_MPORT_mask = 1'h1;
  assign ram_corrupt_MPORT_en = io_enq_ready & io_enq_valid;
  assign io_enq_ready = ~full; // @[Decoupled.scala 289:19]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 288:19]
  assign io_deq_bits_opcode = ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_param = ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_size = ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_source = ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_sink = ram_sink_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_denied = ram_denied_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_data = ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_corrupt = ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  always @(posedge clock) begin
    if (ram_opcode_MPORT_en & ram_opcode_MPORT_mask) begin
      ram_opcode[ram_opcode_MPORT_addr] <= ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_param_MPORT_en & ram_param_MPORT_mask) begin
      ram_param[ram_param_MPORT_addr] <= ram_param_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
      ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_source_MPORT_en & ram_source_MPORT_mask) begin
      ram_source[ram_source_MPORT_addr] <= ram_source_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_sink_MPORT_en & ram_sink_MPORT_mask) begin
      ram_sink[ram_sink_MPORT_addr] <= ram_sink_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_denied_MPORT_en & ram_denied_MPORT_mask) begin
      ram_denied[ram_denied_MPORT_addr] <= ram_denied_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_data_MPORT_en & ram_data_MPORT_mask) begin
      ram_data[ram_data_MPORT_addr] <= ram_data_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_corrupt_MPORT_en & ram_corrupt_MPORT_mask) begin
      ram_corrupt[ram_corrupt_MPORT_addr] <= ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (reset) begin // @[Counter.scala 62:40]
      value <= 1'h0; // @[Counter.scala 62:40]
    end else if (do_enq) begin // @[Decoupled.scala 272:16]
      value <= value + 1'h1; // @[Counter.scala 78:15]
    end
    if (reset) begin // @[Counter.scala 62:40]
      value_1 <= 1'h0; // @[Counter.scala 62:40]
    end else if (do_deq) begin // @[Decoupled.scala 276:16]
      value_1 <= value_1 + 1'h1; // @[Counter.scala 78:15]
    end
    if (reset) begin // @[Decoupled.scala 262:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 262:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 279:27]
      maybe_full <= do_enq; // @[Decoupled.scala 280:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_opcode[initvar] = _RAND_0[2:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_param[initvar] = _RAND_1[1:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_size[initvar] = _RAND_2[3:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_source[initvar] = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_sink[initvar] = _RAND_4[1:0];
  _RAND_5 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_denied[initvar] = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_data[initvar] = _RAND_6[31:0];
  _RAND_7 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_corrupt[initvar] = _RAND_7[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_8 = {1{`RANDOM}};
  value = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  value_1 = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  maybe_full = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_17(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [1:0]  io_enq_bits_param,
  input  [30:0] io_enq_bits_address,
  input         io_deq_ready,
  output        io_deq_valid,
  output [2:0]  io_deq_bits_opcode,
  output [1:0]  io_deq_bits_param,
  output [3:0]  io_deq_bits_size,
  output [1:0]  io_deq_bits_source,
  output [30:0] io_deq_bits_address,
  output [3:0]  io_deq_bits_mask,
  output        io_deq_bits_corrupt
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
`endif // RANDOMIZE_REG_INIT
  reg [2:0] ram_opcode [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_opcode_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_opcode_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [2:0] ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_en; // @[Decoupled.scala 259:95]
  reg [1:0] ram_param [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_param_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_param_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [1:0] ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [1:0] ram_param_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_param_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_param_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_param_MPORT_en; // @[Decoupled.scala 259:95]
  reg [3:0] ram_size [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [3:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [3:0] ram_size_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_en; // @[Decoupled.scala 259:95]
  reg [1:0] ram_source [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [1:0] ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [1:0] ram_source_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_en; // @[Decoupled.scala 259:95]
  reg [30:0] ram_address [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_address_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_address_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [30:0] ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [30:0] ram_address_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_address_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_address_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_address_MPORT_en; // @[Decoupled.scala 259:95]
  reg [3:0] ram_mask [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_mask_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_mask_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [3:0] ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [3:0] ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_mask_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_mask_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_mask_MPORT_en; // @[Decoupled.scala 259:95]
  reg  ram_corrupt [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_en; // @[Decoupled.scala 259:95]
  reg  value; // @[Counter.scala 62:40]
  reg  value_1; // @[Counter.scala 62:40]
  reg  maybe_full; // @[Decoupled.scala 262:27]
  wire  ptr_match = value == value_1; // @[Decoupled.scala 263:33]
  wire  empty = ptr_match & ~maybe_full; // @[Decoupled.scala 264:25]
  wire  full = ptr_match & maybe_full; // @[Decoupled.scala 265:24]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
  wire  do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
  assign ram_opcode_io_deq_bits_MPORT_en = 1'h1;
  assign ram_opcode_io_deq_bits_MPORT_addr = value_1;
  assign ram_opcode_io_deq_bits_MPORT_data = ram_opcode[ram_opcode_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_opcode_MPORT_data = 3'h6;
  assign ram_opcode_MPORT_addr = value;
  assign ram_opcode_MPORT_mask = 1'h1;
  assign ram_opcode_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_param_io_deq_bits_MPORT_en = 1'h1;
  assign ram_param_io_deq_bits_MPORT_addr = value_1;
  assign ram_param_io_deq_bits_MPORT_data = ram_param[ram_param_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_param_MPORT_data = io_enq_bits_param;
  assign ram_param_MPORT_addr = value;
  assign ram_param_MPORT_mask = 1'h1;
  assign ram_param_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_size_io_deq_bits_MPORT_en = 1'h1;
  assign ram_size_io_deq_bits_MPORT_addr = value_1;
  assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_size_MPORT_data = 4'h6;
  assign ram_size_MPORT_addr = value;
  assign ram_size_MPORT_mask = 1'h1;
  assign ram_size_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_source_io_deq_bits_MPORT_en = 1'h1;
  assign ram_source_io_deq_bits_MPORT_addr = value_1;
  assign ram_source_io_deq_bits_MPORT_data = ram_source[ram_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_source_MPORT_data = 2'h0;
  assign ram_source_MPORT_addr = value;
  assign ram_source_MPORT_mask = 1'h1;
  assign ram_source_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_address_io_deq_bits_MPORT_en = 1'h1;
  assign ram_address_io_deq_bits_MPORT_addr = value_1;
  assign ram_address_io_deq_bits_MPORT_data = ram_address[ram_address_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_address_MPORT_data = io_enq_bits_address;
  assign ram_address_MPORT_addr = value;
  assign ram_address_MPORT_mask = 1'h1;
  assign ram_address_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_mask_io_deq_bits_MPORT_en = 1'h1;
  assign ram_mask_io_deq_bits_MPORT_addr = value_1;
  assign ram_mask_io_deq_bits_MPORT_data = ram_mask[ram_mask_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_mask_MPORT_data = 4'hf;
  assign ram_mask_MPORT_addr = value;
  assign ram_mask_MPORT_mask = 1'h1;
  assign ram_mask_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_corrupt_io_deq_bits_MPORT_en = 1'h1;
  assign ram_corrupt_io_deq_bits_MPORT_addr = value_1;
  assign ram_corrupt_io_deq_bits_MPORT_data = ram_corrupt[ram_corrupt_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_corrupt_MPORT_data = 1'h0;
  assign ram_corrupt_MPORT_addr = value;
  assign ram_corrupt_MPORT_mask = 1'h1;
  assign ram_corrupt_MPORT_en = io_enq_ready & io_enq_valid;
  assign io_enq_ready = ~full; // @[Decoupled.scala 289:19]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 288:19]
  assign io_deq_bits_opcode = ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_param = ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_size = ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_source = ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_address = ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_mask = ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_corrupt = ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  always @(posedge clock) begin
    if (ram_opcode_MPORT_en & ram_opcode_MPORT_mask) begin
      ram_opcode[ram_opcode_MPORT_addr] <= ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_param_MPORT_en & ram_param_MPORT_mask) begin
      ram_param[ram_param_MPORT_addr] <= ram_param_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
      ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_source_MPORT_en & ram_source_MPORT_mask) begin
      ram_source[ram_source_MPORT_addr] <= ram_source_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_address_MPORT_en & ram_address_MPORT_mask) begin
      ram_address[ram_address_MPORT_addr] <= ram_address_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_mask_MPORT_en & ram_mask_MPORT_mask) begin
      ram_mask[ram_mask_MPORT_addr] <= ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_corrupt_MPORT_en & ram_corrupt_MPORT_mask) begin
      ram_corrupt[ram_corrupt_MPORT_addr] <= ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (reset) begin // @[Counter.scala 62:40]
      value <= 1'h0; // @[Counter.scala 62:40]
    end else if (do_enq) begin // @[Decoupled.scala 272:16]
      value <= value + 1'h1; // @[Counter.scala 78:15]
    end
    if (reset) begin // @[Counter.scala 62:40]
      value_1 <= 1'h0; // @[Counter.scala 62:40]
    end else if (do_deq) begin // @[Decoupled.scala 276:16]
      value_1 <= value_1 + 1'h1; // @[Counter.scala 78:15]
    end
    if (reset) begin // @[Decoupled.scala 262:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 262:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 279:27]
      maybe_full <= do_enq; // @[Decoupled.scala 280:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_opcode[initvar] = _RAND_0[2:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_param[initvar] = _RAND_1[1:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_size[initvar] = _RAND_2[3:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_source[initvar] = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_address[initvar] = _RAND_4[30:0];
  _RAND_5 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_mask[initvar] = _RAND_5[3:0];
  _RAND_6 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_corrupt[initvar] = _RAND_6[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_7 = {1{`RANDOM}};
  value = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  value_1 = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  maybe_full = _RAND_9[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_18(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [2:0]  io_enq_bits_opcode,
  input  [2:0]  io_enq_bits_param,
  input  [3:0]  io_enq_bits_size,
  input  [1:0]  io_enq_bits_source,
  input  [30:0] io_enq_bits_address,
  input  [31:0] io_enq_bits_data,
  input         io_deq_ready,
  output        io_deq_valid,
  output [2:0]  io_deq_bits_opcode,
  output [2:0]  io_deq_bits_param,
  output [3:0]  io_deq_bits_size,
  output [1:0]  io_deq_bits_source,
  output [30:0] io_deq_bits_address,
  output [31:0] io_deq_bits_data,
  output        io_deq_bits_corrupt
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
`endif // RANDOMIZE_REG_INIT
  reg [2:0] ram_opcode [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_opcode_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_opcode_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [2:0] ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_en; // @[Decoupled.scala 259:95]
  reg [2:0] ram_param [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_param_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_param_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [2:0] ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_param_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_param_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_param_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_param_MPORT_en; // @[Decoupled.scala 259:95]
  reg [3:0] ram_size [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [3:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [3:0] ram_size_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_en; // @[Decoupled.scala 259:95]
  reg [1:0] ram_source [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [1:0] ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [1:0] ram_source_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_en; // @[Decoupled.scala 259:95]
  reg [30:0] ram_address [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_address_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_address_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [30:0] ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [30:0] ram_address_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_address_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_address_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_address_MPORT_en; // @[Decoupled.scala 259:95]
  reg [31:0] ram_data [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_data_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_data_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [31:0] ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [31:0] ram_data_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_data_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_data_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_data_MPORT_en; // @[Decoupled.scala 259:95]
  reg  ram_corrupt [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_en; // @[Decoupled.scala 259:95]
  reg  value; // @[Counter.scala 62:40]
  reg  value_1; // @[Counter.scala 62:40]
  reg  maybe_full; // @[Decoupled.scala 262:27]
  wire  ptr_match = value == value_1; // @[Decoupled.scala 263:33]
  wire  empty = ptr_match & ~maybe_full; // @[Decoupled.scala 264:25]
  wire  full = ptr_match & maybe_full; // @[Decoupled.scala 265:24]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
  wire  do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
  assign ram_opcode_io_deq_bits_MPORT_en = 1'h1;
  assign ram_opcode_io_deq_bits_MPORT_addr = value_1;
  assign ram_opcode_io_deq_bits_MPORT_data = ram_opcode[ram_opcode_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_opcode_MPORT_data = io_enq_bits_opcode;
  assign ram_opcode_MPORT_addr = value;
  assign ram_opcode_MPORT_mask = 1'h1;
  assign ram_opcode_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_param_io_deq_bits_MPORT_en = 1'h1;
  assign ram_param_io_deq_bits_MPORT_addr = value_1;
  assign ram_param_io_deq_bits_MPORT_data = ram_param[ram_param_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_param_MPORT_data = io_enq_bits_param;
  assign ram_param_MPORT_addr = value;
  assign ram_param_MPORT_mask = 1'h1;
  assign ram_param_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_size_io_deq_bits_MPORT_en = 1'h1;
  assign ram_size_io_deq_bits_MPORT_addr = value_1;
  assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_size_MPORT_data = io_enq_bits_size;
  assign ram_size_MPORT_addr = value;
  assign ram_size_MPORT_mask = 1'h1;
  assign ram_size_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_source_io_deq_bits_MPORT_en = 1'h1;
  assign ram_source_io_deq_bits_MPORT_addr = value_1;
  assign ram_source_io_deq_bits_MPORT_data = ram_source[ram_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_source_MPORT_data = io_enq_bits_source;
  assign ram_source_MPORT_addr = value;
  assign ram_source_MPORT_mask = 1'h1;
  assign ram_source_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_address_io_deq_bits_MPORT_en = 1'h1;
  assign ram_address_io_deq_bits_MPORT_addr = value_1;
  assign ram_address_io_deq_bits_MPORT_data = ram_address[ram_address_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_address_MPORT_data = io_enq_bits_address;
  assign ram_address_MPORT_addr = value;
  assign ram_address_MPORT_mask = 1'h1;
  assign ram_address_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_data_io_deq_bits_MPORT_en = 1'h1;
  assign ram_data_io_deq_bits_MPORT_addr = value_1;
  assign ram_data_io_deq_bits_MPORT_data = ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_data_MPORT_data = io_enq_bits_data;
  assign ram_data_MPORT_addr = value;
  assign ram_data_MPORT_mask = 1'h1;
  assign ram_data_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_corrupt_io_deq_bits_MPORT_en = 1'h1;
  assign ram_corrupt_io_deq_bits_MPORT_addr = value_1;
  assign ram_corrupt_io_deq_bits_MPORT_data = ram_corrupt[ram_corrupt_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_corrupt_MPORT_data = 1'h0;
  assign ram_corrupt_MPORT_addr = value;
  assign ram_corrupt_MPORT_mask = 1'h1;
  assign ram_corrupt_MPORT_en = io_enq_ready & io_enq_valid;
  assign io_enq_ready = ~full; // @[Decoupled.scala 289:19]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 288:19]
  assign io_deq_bits_opcode = ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_param = ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_size = ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_source = ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_address = ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_data = ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_corrupt = ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  always @(posedge clock) begin
    if (ram_opcode_MPORT_en & ram_opcode_MPORT_mask) begin
      ram_opcode[ram_opcode_MPORT_addr] <= ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_param_MPORT_en & ram_param_MPORT_mask) begin
      ram_param[ram_param_MPORT_addr] <= ram_param_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
      ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_source_MPORT_en & ram_source_MPORT_mask) begin
      ram_source[ram_source_MPORT_addr] <= ram_source_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_address_MPORT_en & ram_address_MPORT_mask) begin
      ram_address[ram_address_MPORT_addr] <= ram_address_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_data_MPORT_en & ram_data_MPORT_mask) begin
      ram_data[ram_data_MPORT_addr] <= ram_data_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_corrupt_MPORT_en & ram_corrupt_MPORT_mask) begin
      ram_corrupt[ram_corrupt_MPORT_addr] <= ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (reset) begin // @[Counter.scala 62:40]
      value <= 1'h0; // @[Counter.scala 62:40]
    end else if (do_enq) begin // @[Decoupled.scala 272:16]
      value <= value + 1'h1; // @[Counter.scala 78:15]
    end
    if (reset) begin // @[Counter.scala 62:40]
      value_1 <= 1'h0; // @[Counter.scala 62:40]
    end else if (do_deq) begin // @[Decoupled.scala 276:16]
      value_1 <= value_1 + 1'h1; // @[Counter.scala 78:15]
    end
    if (reset) begin // @[Decoupled.scala 262:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 262:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 279:27]
      maybe_full <= do_enq; // @[Decoupled.scala 280:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_opcode[initvar] = _RAND_0[2:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_param[initvar] = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_size[initvar] = _RAND_2[3:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_source[initvar] = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_address[initvar] = _RAND_4[30:0];
  _RAND_5 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_data[initvar] = _RAND_5[31:0];
  _RAND_6 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_corrupt[initvar] = _RAND_6[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_7 = {1{`RANDOM}};
  value = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  value_1 = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  maybe_full = _RAND_9[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_19(
  input        clock,
  input        reset,
  output       io_enq_ready,
  input        io_enq_valid,
  input  [1:0] io_enq_bits_sink,
  output       io_deq_valid,
  output [1:0] io_deq_bits_sink
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif // RANDOMIZE_REG_INIT
  reg [1:0] ram_sink [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_sink_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_sink_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [1:0] ram_sink_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [1:0] ram_sink_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_sink_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_sink_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_sink_MPORT_en; // @[Decoupled.scala 259:95]
  reg  value; // @[Counter.scala 62:40]
  reg  value_1; // @[Counter.scala 62:40]
  reg  maybe_full; // @[Decoupled.scala 262:27]
  wire  ptr_match = value == value_1; // @[Decoupled.scala 263:33]
  wire  empty = ptr_match & ~maybe_full; // @[Decoupled.scala 264:25]
  wire  full = ptr_match & maybe_full; // @[Decoupled.scala 265:24]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
  assign ram_sink_io_deq_bits_MPORT_en = 1'h1;
  assign ram_sink_io_deq_bits_MPORT_addr = value_1;
  assign ram_sink_io_deq_bits_MPORT_data = ram_sink[ram_sink_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_sink_MPORT_data = io_enq_bits_sink;
  assign ram_sink_MPORT_addr = value;
  assign ram_sink_MPORT_mask = 1'h1;
  assign ram_sink_MPORT_en = io_enq_ready & io_enq_valid;
  assign io_enq_ready = ~full; // @[Decoupled.scala 289:19]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 288:19]
  assign io_deq_bits_sink = ram_sink_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  always @(posedge clock) begin
    if (ram_sink_MPORT_en & ram_sink_MPORT_mask) begin
      ram_sink[ram_sink_MPORT_addr] <= ram_sink_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (reset) begin // @[Counter.scala 62:40]
      value <= 1'h0; // @[Counter.scala 62:40]
    end else if (do_enq) begin // @[Decoupled.scala 272:16]
      value <= value + 1'h1; // @[Counter.scala 78:15]
    end
    if (reset) begin // @[Counter.scala 62:40]
      value_1 <= 1'h0; // @[Counter.scala 62:40]
    end else if (io_deq_valid) begin // @[Decoupled.scala 276:16]
      value_1 <= value_1 + 1'h1; // @[Counter.scala 78:15]
    end
    if (reset) begin // @[Decoupled.scala 262:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 262:27]
    end else if (do_enq != io_deq_valid) begin // @[Decoupled.scala 279:27]
      maybe_full <= do_enq; // @[Decoupled.scala 280:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_sink[initvar] = _RAND_0[1:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_1 = {1{`RANDOM}};
  value = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  value_1 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  maybe_full = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLBuffer_10(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [3:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [30:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_b_ready,
  output        auto_in_b_valid,
  output [2:0]  auto_in_b_bits_opcode,
  output [1:0]  auto_in_b_bits_param,
  output [3:0]  auto_in_b_bits_size,
  output [1:0]  auto_in_b_bits_source,
  output [30:0] auto_in_b_bits_address,
  output [3:0]  auto_in_b_bits_mask,
  output        auto_in_b_bits_corrupt,
  output        auto_in_c_ready,
  input         auto_in_c_valid,
  input  [2:0]  auto_in_c_bits_opcode,
  input  [2:0]  auto_in_c_bits_param,
  input  [3:0]  auto_in_c_bits_size,
  input  [1:0]  auto_in_c_bits_source,
  input  [30:0] auto_in_c_bits_address,
  input  [31:0] auto_in_c_bits_data,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [1:0]  auto_in_d_bits_param,
  output [3:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output [1:0]  auto_in_d_bits_sink,
  output        auto_in_d_bits_denied,
  output [31:0] auto_in_d_bits_data,
  output        auto_in_d_bits_corrupt,
  output        auto_in_e_ready,
  input         auto_in_e_valid,
  input  [1:0]  auto_in_e_bits_sink,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [3:0]  auto_out_a_bits_size,
  output [1:0]  auto_out_a_bits_source,
  output [30:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_b_ready,
  input         auto_out_b_valid,
  input  [1:0]  auto_out_b_bits_param,
  input  [30:0] auto_out_b_bits_address,
  input         auto_out_c_ready,
  output        auto_out_c_valid,
  output [2:0]  auto_out_c_bits_opcode,
  output [2:0]  auto_out_c_bits_param,
  output [3:0]  auto_out_c_bits_size,
  output [1:0]  auto_out_c_bits_source,
  output [30:0] auto_out_c_bits_address,
  output [31:0] auto_out_c_bits_data,
  output        auto_out_c_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_param,
  input  [3:0]  auto_out_d_bits_size,
  input  [1:0]  auto_out_d_bits_source,
  input  [1:0]  auto_out_d_bits_sink,
  input         auto_out_d_bits_denied,
  input  [31:0] auto_out_d_bits_data,
  input         auto_out_d_bits_corrupt,
  output        auto_out_e_valid,
  output [1:0]  auto_out_e_bits_sink
);
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [30:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_b_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_b_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_b_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_b_bits_param; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_b_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_b_bits_source; // @[Nodes.scala 24:25]
  wire [30:0] monitor_io_in_b_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_b_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_b_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_c_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_c_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_c_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_c_bits_param; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_c_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_c_bits_source; // @[Nodes.scala 24:25]
  wire [30:0] monitor_io_in_c_bits_address; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_e_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_e_valid; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_e_bits_sink; // @[Nodes.scala 24:25]
  wire  bundleOut_0_a_q_clock; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_reset; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_enq_ready; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_enq_valid; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
  wire [3:0] bundleOut_0_a_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
  wire [1:0] bundleOut_0_a_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
  wire [30:0] bundleOut_0_a_q_io_enq_bits_address; // @[Decoupled.scala 361:21]
  wire [3:0] bundleOut_0_a_q_io_enq_bits_mask; // @[Decoupled.scala 361:21]
  wire [31:0] bundleOut_0_a_q_io_enq_bits_data; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_deq_ready; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_deq_valid; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
  wire [3:0] bundleOut_0_a_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
  wire [1:0] bundleOut_0_a_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
  wire [30:0] bundleOut_0_a_q_io_deq_bits_address; // @[Decoupled.scala 361:21]
  wire [3:0] bundleOut_0_a_q_io_deq_bits_mask; // @[Decoupled.scala 361:21]
  wire [31:0] bundleOut_0_a_q_io_deq_bits_data; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_clock; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_reset; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_enq_ready; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_enq_valid; // @[Decoupled.scala 361:21]
  wire [2:0] bundleIn_0_d_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
  wire [1:0] bundleIn_0_d_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
  wire [3:0] bundleIn_0_d_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
  wire [1:0] bundleIn_0_d_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
  wire [1:0] bundleIn_0_d_q_io_enq_bits_sink; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_enq_bits_denied; // @[Decoupled.scala 361:21]
  wire [31:0] bundleIn_0_d_q_io_enq_bits_data; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_enq_bits_corrupt; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_deq_ready; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_deq_valid; // @[Decoupled.scala 361:21]
  wire [2:0] bundleIn_0_d_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
  wire [1:0] bundleIn_0_d_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
  wire [3:0] bundleIn_0_d_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
  wire [1:0] bundleIn_0_d_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
  wire [1:0] bundleIn_0_d_q_io_deq_bits_sink; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_deq_bits_denied; // @[Decoupled.scala 361:21]
  wire [31:0] bundleIn_0_d_q_io_deq_bits_data; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_b_q_clock; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_b_q_reset; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_b_q_io_enq_ready; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_b_q_io_enq_valid; // @[Decoupled.scala 361:21]
  wire [1:0] bundleIn_0_b_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
  wire [30:0] bundleIn_0_b_q_io_enq_bits_address; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_b_q_io_deq_ready; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_b_q_io_deq_valid; // @[Decoupled.scala 361:21]
  wire [2:0] bundleIn_0_b_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
  wire [1:0] bundleIn_0_b_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
  wire [3:0] bundleIn_0_b_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
  wire [1:0] bundleIn_0_b_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
  wire [30:0] bundleIn_0_b_q_io_deq_bits_address; // @[Decoupled.scala 361:21]
  wire [3:0] bundleIn_0_b_q_io_deq_bits_mask; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_b_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_c_q_clock; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_c_q_reset; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_c_q_io_enq_ready; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_c_q_io_enq_valid; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_c_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_c_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
  wire [3:0] bundleOut_0_c_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
  wire [1:0] bundleOut_0_c_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
  wire [30:0] bundleOut_0_c_q_io_enq_bits_address; // @[Decoupled.scala 361:21]
  wire [31:0] bundleOut_0_c_q_io_enq_bits_data; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_c_q_io_deq_ready; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_c_q_io_deq_valid; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_c_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_c_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
  wire [3:0] bundleOut_0_c_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
  wire [1:0] bundleOut_0_c_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
  wire [30:0] bundleOut_0_c_q_io_deq_bits_address; // @[Decoupled.scala 361:21]
  wire [31:0] bundleOut_0_c_q_io_deq_bits_data; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_c_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_e_q_clock; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_e_q_reset; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_e_q_io_enq_ready; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_e_q_io_enq_valid; // @[Decoupled.scala 361:21]
  wire [1:0] bundleOut_0_e_q_io_enq_bits_sink; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_e_q_io_deq_valid; // @[Decoupled.scala 361:21]
  wire [1:0] bundleOut_0_e_q_io_deq_bits_sink; // @[Decoupled.scala 361:21]
  TLMonitor_45 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_b_ready(monitor_io_in_b_ready),
    .io_in_b_valid(monitor_io_in_b_valid),
    .io_in_b_bits_opcode(monitor_io_in_b_bits_opcode),
    .io_in_b_bits_param(monitor_io_in_b_bits_param),
    .io_in_b_bits_size(monitor_io_in_b_bits_size),
    .io_in_b_bits_source(monitor_io_in_b_bits_source),
    .io_in_b_bits_address(monitor_io_in_b_bits_address),
    .io_in_b_bits_mask(monitor_io_in_b_bits_mask),
    .io_in_b_bits_corrupt(monitor_io_in_b_bits_corrupt),
    .io_in_c_ready(monitor_io_in_c_ready),
    .io_in_c_valid(monitor_io_in_c_valid),
    .io_in_c_bits_opcode(monitor_io_in_c_bits_opcode),
    .io_in_c_bits_param(monitor_io_in_c_bits_param),
    .io_in_c_bits_size(monitor_io_in_c_bits_size),
    .io_in_c_bits_source(monitor_io_in_c_bits_source),
    .io_in_c_bits_address(monitor_io_in_c_bits_address),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_param(monitor_io_in_d_bits_param),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source),
    .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
    .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
    .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt),
    .io_in_e_ready(monitor_io_in_e_ready),
    .io_in_e_valid(monitor_io_in_e_valid),
    .io_in_e_bits_sink(monitor_io_in_e_bits_sink)
  );
  Queue_15 bundleOut_0_a_q ( // @[Decoupled.scala 361:21]
    .clock(bundleOut_0_a_q_clock),
    .reset(bundleOut_0_a_q_reset),
    .io_enq_ready(bundleOut_0_a_q_io_enq_ready),
    .io_enq_valid(bundleOut_0_a_q_io_enq_valid),
    .io_enq_bits_opcode(bundleOut_0_a_q_io_enq_bits_opcode),
    .io_enq_bits_param(bundleOut_0_a_q_io_enq_bits_param),
    .io_enq_bits_size(bundleOut_0_a_q_io_enq_bits_size),
    .io_enq_bits_source(bundleOut_0_a_q_io_enq_bits_source),
    .io_enq_bits_address(bundleOut_0_a_q_io_enq_bits_address),
    .io_enq_bits_mask(bundleOut_0_a_q_io_enq_bits_mask),
    .io_enq_bits_data(bundleOut_0_a_q_io_enq_bits_data),
    .io_deq_ready(bundleOut_0_a_q_io_deq_ready),
    .io_deq_valid(bundleOut_0_a_q_io_deq_valid),
    .io_deq_bits_opcode(bundleOut_0_a_q_io_deq_bits_opcode),
    .io_deq_bits_param(bundleOut_0_a_q_io_deq_bits_param),
    .io_deq_bits_size(bundleOut_0_a_q_io_deq_bits_size),
    .io_deq_bits_source(bundleOut_0_a_q_io_deq_bits_source),
    .io_deq_bits_address(bundleOut_0_a_q_io_deq_bits_address),
    .io_deq_bits_mask(bundleOut_0_a_q_io_deq_bits_mask),
    .io_deq_bits_data(bundleOut_0_a_q_io_deq_bits_data),
    .io_deq_bits_corrupt(bundleOut_0_a_q_io_deq_bits_corrupt)
  );
  Queue_16 bundleIn_0_d_q ( // @[Decoupled.scala 361:21]
    .clock(bundleIn_0_d_q_clock),
    .reset(bundleIn_0_d_q_reset),
    .io_enq_ready(bundleIn_0_d_q_io_enq_ready),
    .io_enq_valid(bundleIn_0_d_q_io_enq_valid),
    .io_enq_bits_opcode(bundleIn_0_d_q_io_enq_bits_opcode),
    .io_enq_bits_param(bundleIn_0_d_q_io_enq_bits_param),
    .io_enq_bits_size(bundleIn_0_d_q_io_enq_bits_size),
    .io_enq_bits_source(bundleIn_0_d_q_io_enq_bits_source),
    .io_enq_bits_sink(bundleIn_0_d_q_io_enq_bits_sink),
    .io_enq_bits_denied(bundleIn_0_d_q_io_enq_bits_denied),
    .io_enq_bits_data(bundleIn_0_d_q_io_enq_bits_data),
    .io_enq_bits_corrupt(bundleIn_0_d_q_io_enq_bits_corrupt),
    .io_deq_ready(bundleIn_0_d_q_io_deq_ready),
    .io_deq_valid(bundleIn_0_d_q_io_deq_valid),
    .io_deq_bits_opcode(bundleIn_0_d_q_io_deq_bits_opcode),
    .io_deq_bits_param(bundleIn_0_d_q_io_deq_bits_param),
    .io_deq_bits_size(bundleIn_0_d_q_io_deq_bits_size),
    .io_deq_bits_source(bundleIn_0_d_q_io_deq_bits_source),
    .io_deq_bits_sink(bundleIn_0_d_q_io_deq_bits_sink),
    .io_deq_bits_denied(bundleIn_0_d_q_io_deq_bits_denied),
    .io_deq_bits_data(bundleIn_0_d_q_io_deq_bits_data),
    .io_deq_bits_corrupt(bundleIn_0_d_q_io_deq_bits_corrupt)
  );
  Queue_17 bundleIn_0_b_q ( // @[Decoupled.scala 361:21]
    .clock(bundleIn_0_b_q_clock),
    .reset(bundleIn_0_b_q_reset),
    .io_enq_ready(bundleIn_0_b_q_io_enq_ready),
    .io_enq_valid(bundleIn_0_b_q_io_enq_valid),
    .io_enq_bits_param(bundleIn_0_b_q_io_enq_bits_param),
    .io_enq_bits_address(bundleIn_0_b_q_io_enq_bits_address),
    .io_deq_ready(bundleIn_0_b_q_io_deq_ready),
    .io_deq_valid(bundleIn_0_b_q_io_deq_valid),
    .io_deq_bits_opcode(bundleIn_0_b_q_io_deq_bits_opcode),
    .io_deq_bits_param(bundleIn_0_b_q_io_deq_bits_param),
    .io_deq_bits_size(bundleIn_0_b_q_io_deq_bits_size),
    .io_deq_bits_source(bundleIn_0_b_q_io_deq_bits_source),
    .io_deq_bits_address(bundleIn_0_b_q_io_deq_bits_address),
    .io_deq_bits_mask(bundleIn_0_b_q_io_deq_bits_mask),
    .io_deq_bits_corrupt(bundleIn_0_b_q_io_deq_bits_corrupt)
  );
  Queue_18 bundleOut_0_c_q ( // @[Decoupled.scala 361:21]
    .clock(bundleOut_0_c_q_clock),
    .reset(bundleOut_0_c_q_reset),
    .io_enq_ready(bundleOut_0_c_q_io_enq_ready),
    .io_enq_valid(bundleOut_0_c_q_io_enq_valid),
    .io_enq_bits_opcode(bundleOut_0_c_q_io_enq_bits_opcode),
    .io_enq_bits_param(bundleOut_0_c_q_io_enq_bits_param),
    .io_enq_bits_size(bundleOut_0_c_q_io_enq_bits_size),
    .io_enq_bits_source(bundleOut_0_c_q_io_enq_bits_source),
    .io_enq_bits_address(bundleOut_0_c_q_io_enq_bits_address),
    .io_enq_bits_data(bundleOut_0_c_q_io_enq_bits_data),
    .io_deq_ready(bundleOut_0_c_q_io_deq_ready),
    .io_deq_valid(bundleOut_0_c_q_io_deq_valid),
    .io_deq_bits_opcode(bundleOut_0_c_q_io_deq_bits_opcode),
    .io_deq_bits_param(bundleOut_0_c_q_io_deq_bits_param),
    .io_deq_bits_size(bundleOut_0_c_q_io_deq_bits_size),
    .io_deq_bits_source(bundleOut_0_c_q_io_deq_bits_source),
    .io_deq_bits_address(bundleOut_0_c_q_io_deq_bits_address),
    .io_deq_bits_data(bundleOut_0_c_q_io_deq_bits_data),
    .io_deq_bits_corrupt(bundleOut_0_c_q_io_deq_bits_corrupt)
  );
  Queue_19 bundleOut_0_e_q ( // @[Decoupled.scala 361:21]
    .clock(bundleOut_0_e_q_clock),
    .reset(bundleOut_0_e_q_reset),
    .io_enq_ready(bundleOut_0_e_q_io_enq_ready),
    .io_enq_valid(bundleOut_0_e_q_io_enq_valid),
    .io_enq_bits_sink(bundleOut_0_e_q_io_enq_bits_sink),
    .io_deq_valid(bundleOut_0_e_q_io_deq_valid),
    .io_deq_bits_sink(bundleOut_0_e_q_io_deq_bits_sink)
  );
  assign auto_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
  assign auto_in_b_valid = bundleIn_0_b_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 41:15]
  assign auto_in_b_bits_opcode = bundleIn_0_b_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 41:15]
  assign auto_in_b_bits_param = bundleIn_0_b_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 41:15]
  assign auto_in_b_bits_size = bundleIn_0_b_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 41:15]
  assign auto_in_b_bits_source = bundleIn_0_b_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 41:15]
  assign auto_in_b_bits_address = bundleIn_0_b_q_io_deq_bits_address; // @[Nodes.scala 1210:84 Buffer.scala 41:15]
  assign auto_in_b_bits_mask = bundleIn_0_b_q_io_deq_bits_mask; // @[Nodes.scala 1210:84 Buffer.scala 41:15]
  assign auto_in_b_bits_corrupt = bundleIn_0_b_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 41:15]
  assign auto_in_c_ready = bundleOut_0_c_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
  assign auto_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_param = bundleIn_0_d_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_source = bundleIn_0_d_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_sink = bundleIn_0_d_q_io_deq_bits_sink; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_denied = bundleIn_0_d_q_io_deq_bits_denied; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_data = bundleIn_0_d_q_io_deq_bits_data; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_corrupt = bundleIn_0_d_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_e_ready = bundleOut_0_e_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
  assign auto_out_a_valid = bundleOut_0_a_q_io_deq_valid; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_opcode = bundleOut_0_a_q_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_param = bundleOut_0_a_q_io_deq_bits_param; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_size = bundleOut_0_a_q_io_deq_bits_size; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_source = bundleOut_0_a_q_io_deq_bits_source; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_address = bundleOut_0_a_q_io_deq_bits_address; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_mask = bundleOut_0_a_q_io_deq_bits_mask; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_data = bundleOut_0_a_q_io_deq_bits_data; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_corrupt = bundleOut_0_a_q_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_b_ready = bundleIn_0_b_q_io_enq_ready; // @[Nodes.scala 1207:84 Decoupled.scala 365:17]
  assign auto_out_c_valid = bundleOut_0_c_q_io_deq_valid; // @[Nodes.scala 1207:84 Buffer.scala 42:15]
  assign auto_out_c_bits_opcode = bundleOut_0_c_q_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Buffer.scala 42:15]
  assign auto_out_c_bits_param = bundleOut_0_c_q_io_deq_bits_param; // @[Nodes.scala 1207:84 Buffer.scala 42:15]
  assign auto_out_c_bits_size = bundleOut_0_c_q_io_deq_bits_size; // @[Nodes.scala 1207:84 Buffer.scala 42:15]
  assign auto_out_c_bits_source = bundleOut_0_c_q_io_deq_bits_source; // @[Nodes.scala 1207:84 Buffer.scala 42:15]
  assign auto_out_c_bits_address = bundleOut_0_c_q_io_deq_bits_address; // @[Nodes.scala 1207:84 Buffer.scala 42:15]
  assign auto_out_c_bits_data = bundleOut_0_c_q_io_deq_bits_data; // @[Nodes.scala 1207:84 Buffer.scala 42:15]
  assign auto_out_c_bits_corrupt = bundleOut_0_c_q_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Buffer.scala 42:15]
  assign auto_out_d_ready = bundleIn_0_d_q_io_enq_ready; // @[Nodes.scala 1207:84 Decoupled.scala 365:17]
  assign auto_out_e_valid = bundleOut_0_e_q_io_deq_valid; // @[Nodes.scala 1207:84 Buffer.scala 43:15]
  assign auto_out_e_bits_sink = bundleOut_0_e_q_io_deq_bits_sink; // @[Nodes.scala 1207:84 Buffer.scala 43:15]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_b_ready = auto_in_b_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_b_valid = bundleIn_0_b_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 41:15]
  assign monitor_io_in_b_bits_opcode = bundleIn_0_b_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 41:15]
  assign monitor_io_in_b_bits_param = bundleIn_0_b_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 41:15]
  assign monitor_io_in_b_bits_size = bundleIn_0_b_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 41:15]
  assign monitor_io_in_b_bits_source = bundleIn_0_b_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 41:15]
  assign monitor_io_in_b_bits_address = bundleIn_0_b_q_io_deq_bits_address; // @[Nodes.scala 1210:84 Buffer.scala 41:15]
  assign monitor_io_in_b_bits_mask = bundleIn_0_b_q_io_deq_bits_mask; // @[Nodes.scala 1210:84 Buffer.scala 41:15]
  assign monitor_io_in_b_bits_corrupt = bundleIn_0_b_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 41:15]
  assign monitor_io_in_c_ready = bundleOut_0_c_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
  assign monitor_io_in_c_valid = auto_in_c_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_opcode = auto_in_c_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_param = auto_in_c_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_size = auto_in_c_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_source = auto_in_c_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_c_bits_address = auto_in_c_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_param = bundleIn_0_d_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_source = bundleIn_0_d_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_sink = bundleIn_0_d_q_io_deq_bits_sink; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_denied = bundleIn_0_d_q_io_deq_bits_denied; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_d_bits_corrupt = bundleIn_0_d_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign monitor_io_in_e_ready = bundleOut_0_e_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
  assign monitor_io_in_e_valid = auto_in_e_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_e_bits_sink = auto_in_e_bits_sink; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_clock = clock;
  assign bundleOut_0_a_q_reset = reset;
  assign bundleOut_0_a_q_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_clock = clock;
  assign bundleIn_0_d_q_reset = reset;
  assign bundleIn_0_d_q_io_enq_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_param = auto_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_deq_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleIn_0_b_q_clock = clock;
  assign bundleIn_0_b_q_reset = reset;
  assign bundleIn_0_b_q_io_enq_valid = auto_out_b_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_b_q_io_enq_bits_param = auto_out_b_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_b_q_io_enq_bits_address = auto_out_b_bits_address; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_b_q_io_deq_ready = auto_in_b_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_c_q_clock = clock;
  assign bundleOut_0_c_q_reset = reset;
  assign bundleOut_0_c_q_io_enq_valid = auto_in_c_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_c_q_io_enq_bits_opcode = auto_in_c_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_c_q_io_enq_bits_param = auto_in_c_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_c_q_io_enq_bits_size = auto_in_c_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_c_q_io_enq_bits_source = auto_in_c_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_c_q_io_enq_bits_address = auto_in_c_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_c_q_io_enq_bits_data = auto_in_c_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_c_q_io_deq_ready = auto_out_c_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleOut_0_e_q_clock = clock;
  assign bundleOut_0_e_q_reset = reset;
  assign bundleOut_0_e_q_io_enq_valid = auto_in_e_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_e_q_io_enq_bits_sink = auto_in_e_bits_sink; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module TLBuffer_11(
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [27:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output [31:0] auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [2:0]  auto_out_a_bits_size,
  output [1:0]  auto_out_a_bits_source,
  output [27:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [2:0]  auto_out_d_bits_size,
  input  [1:0]  auto_out_d_bits_source,
  input  [31:0] auto_out_d_bits_data
);
  assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module Queue_20(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [2:0]  io_enq_bits_opcode,
  input  [2:0]  io_enq_bits_param,
  input  [2:0]  io_enq_bits_size,
  input  [1:0]  io_enq_bits_source,
  input  [27:0] io_enq_bits_address,
  input  [3:0]  io_enq_bits_mask,
  input  [31:0] io_enq_bits_data,
  input         io_enq_bits_corrupt,
  input         io_deq_ready,
  output        io_deq_valid,
  output [2:0]  io_deq_bits_opcode,
  output [2:0]  io_deq_bits_param,
  output [2:0]  io_deq_bits_size,
  output [1:0]  io_deq_bits_source,
  output [27:0] io_deq_bits_address,
  output [3:0]  io_deq_bits_mask,
  output [31:0] io_deq_bits_data,
  output        io_deq_bits_corrupt
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
`endif // RANDOMIZE_REG_INIT
  reg [2:0] ram_opcode [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_opcode_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_opcode_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [2:0] ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_opcode_MPORT_en; // @[Decoupled.scala 259:95]
  reg [2:0] ram_param [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_param_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_param_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [2:0] ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_param_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_param_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_param_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_param_MPORT_en; // @[Decoupled.scala 259:95]
  reg [2:0] ram_size [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [2:0] ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_size_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_size_MPORT_en; // @[Decoupled.scala 259:95]
  reg [1:0] ram_source [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [1:0] ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [1:0] ram_source_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_source_MPORT_en; // @[Decoupled.scala 259:95]
  reg [27:0] ram_address [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_address_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_address_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [27:0] ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [27:0] ram_address_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_address_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_address_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_address_MPORT_en; // @[Decoupled.scala 259:95]
  reg [3:0] ram_mask [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_mask_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_mask_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [3:0] ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [3:0] ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_mask_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_mask_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_mask_MPORT_en; // @[Decoupled.scala 259:95]
  reg [31:0] ram_data [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_data_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_data_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [31:0] ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [31:0] ram_data_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_data_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_data_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_data_MPORT_en; // @[Decoupled.scala 259:95]
  reg  ram_corrupt [0:1]; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_corrupt_MPORT_en; // @[Decoupled.scala 259:95]
  reg  value; // @[Counter.scala 62:40]
  reg  value_1; // @[Counter.scala 62:40]
  reg  maybe_full; // @[Decoupled.scala 262:27]
  wire  ptr_match = value == value_1; // @[Decoupled.scala 263:33]
  wire  empty = ptr_match & ~maybe_full; // @[Decoupled.scala 264:25]
  wire  full = ptr_match & maybe_full; // @[Decoupled.scala 265:24]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
  wire  do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
  assign ram_opcode_io_deq_bits_MPORT_en = 1'h1;
  assign ram_opcode_io_deq_bits_MPORT_addr = value_1;
  assign ram_opcode_io_deq_bits_MPORT_data = ram_opcode[ram_opcode_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_opcode_MPORT_data = io_enq_bits_opcode;
  assign ram_opcode_MPORT_addr = value;
  assign ram_opcode_MPORT_mask = 1'h1;
  assign ram_opcode_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_param_io_deq_bits_MPORT_en = 1'h1;
  assign ram_param_io_deq_bits_MPORT_addr = value_1;
  assign ram_param_io_deq_bits_MPORT_data = ram_param[ram_param_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_param_MPORT_data = io_enq_bits_param;
  assign ram_param_MPORT_addr = value;
  assign ram_param_MPORT_mask = 1'h1;
  assign ram_param_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_size_io_deq_bits_MPORT_en = 1'h1;
  assign ram_size_io_deq_bits_MPORT_addr = value_1;
  assign ram_size_io_deq_bits_MPORT_data = ram_size[ram_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_size_MPORT_data = io_enq_bits_size;
  assign ram_size_MPORT_addr = value;
  assign ram_size_MPORT_mask = 1'h1;
  assign ram_size_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_source_io_deq_bits_MPORT_en = 1'h1;
  assign ram_source_io_deq_bits_MPORT_addr = value_1;
  assign ram_source_io_deq_bits_MPORT_data = ram_source[ram_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_source_MPORT_data = io_enq_bits_source;
  assign ram_source_MPORT_addr = value;
  assign ram_source_MPORT_mask = 1'h1;
  assign ram_source_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_address_io_deq_bits_MPORT_en = 1'h1;
  assign ram_address_io_deq_bits_MPORT_addr = value_1;
  assign ram_address_io_deq_bits_MPORT_data = ram_address[ram_address_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_address_MPORT_data = io_enq_bits_address;
  assign ram_address_MPORT_addr = value;
  assign ram_address_MPORT_mask = 1'h1;
  assign ram_address_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_mask_io_deq_bits_MPORT_en = 1'h1;
  assign ram_mask_io_deq_bits_MPORT_addr = value_1;
  assign ram_mask_io_deq_bits_MPORT_data = ram_mask[ram_mask_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_mask_MPORT_data = io_enq_bits_mask;
  assign ram_mask_MPORT_addr = value;
  assign ram_mask_MPORT_mask = 1'h1;
  assign ram_mask_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_data_io_deq_bits_MPORT_en = 1'h1;
  assign ram_data_io_deq_bits_MPORT_addr = value_1;
  assign ram_data_io_deq_bits_MPORT_data = ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_data_MPORT_data = io_enq_bits_data;
  assign ram_data_MPORT_addr = value;
  assign ram_data_MPORT_mask = 1'h1;
  assign ram_data_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_corrupt_io_deq_bits_MPORT_en = 1'h1;
  assign ram_corrupt_io_deq_bits_MPORT_addr = value_1;
  assign ram_corrupt_io_deq_bits_MPORT_data = ram_corrupt[ram_corrupt_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_corrupt_MPORT_data = io_enq_bits_corrupt;
  assign ram_corrupt_MPORT_addr = value;
  assign ram_corrupt_MPORT_mask = 1'h1;
  assign ram_corrupt_MPORT_en = io_enq_ready & io_enq_valid;
  assign io_enq_ready = ~full; // @[Decoupled.scala 289:19]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 288:19]
  assign io_deq_bits_opcode = ram_opcode_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_param = ram_param_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_size = ram_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_source = ram_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_address = ram_address_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_mask = ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_data = ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_corrupt = ram_corrupt_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  always @(posedge clock) begin
    if (ram_opcode_MPORT_en & ram_opcode_MPORT_mask) begin
      ram_opcode[ram_opcode_MPORT_addr] <= ram_opcode_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_param_MPORT_en & ram_param_MPORT_mask) begin
      ram_param[ram_param_MPORT_addr] <= ram_param_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_size_MPORT_en & ram_size_MPORT_mask) begin
      ram_size[ram_size_MPORT_addr] <= ram_size_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_source_MPORT_en & ram_source_MPORT_mask) begin
      ram_source[ram_source_MPORT_addr] <= ram_source_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_address_MPORT_en & ram_address_MPORT_mask) begin
      ram_address[ram_address_MPORT_addr] <= ram_address_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_mask_MPORT_en & ram_mask_MPORT_mask) begin
      ram_mask[ram_mask_MPORT_addr] <= ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_data_MPORT_en & ram_data_MPORT_mask) begin
      ram_data[ram_data_MPORT_addr] <= ram_data_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_corrupt_MPORT_en & ram_corrupt_MPORT_mask) begin
      ram_corrupt[ram_corrupt_MPORT_addr] <= ram_corrupt_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (reset) begin // @[Counter.scala 62:40]
      value <= 1'h0; // @[Counter.scala 62:40]
    end else if (do_enq) begin // @[Decoupled.scala 272:16]
      value <= value + 1'h1; // @[Counter.scala 78:15]
    end
    if (reset) begin // @[Counter.scala 62:40]
      value_1 <= 1'h0; // @[Counter.scala 62:40]
    end else if (do_deq) begin // @[Decoupled.scala 276:16]
      value_1 <= value_1 + 1'h1; // @[Counter.scala 78:15]
    end
    if (reset) begin // @[Decoupled.scala 262:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 262:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 279:27]
      maybe_full <= do_enq; // @[Decoupled.scala 280:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_opcode[initvar] = _RAND_0[2:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_param[initvar] = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_size[initvar] = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_source[initvar] = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_address[initvar] = _RAND_4[27:0];
  _RAND_5 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_mask[initvar] = _RAND_5[3:0];
  _RAND_6 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_data[initvar] = _RAND_6[31:0];
  _RAND_7 = {1{`RANDOM}};
  for (initvar = 0; initvar < 2; initvar = initvar+1)
    ram_corrupt[initvar] = _RAND_7[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_8 = {1{`RANDOM}};
  value = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  value_1 = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  maybe_full = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLBuffer_12(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [2:0]  auto_in_a_bits_size,
  input  [1:0]  auto_in_a_bits_source,
  input  [27:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [1:0]  auto_in_d_bits_param,
  output [2:0]  auto_in_d_bits_size,
  output [1:0]  auto_in_d_bits_source,
  output        auto_in_d_bits_sink,
  output        auto_in_d_bits_denied,
  output [31:0] auto_in_d_bits_data,
  output        auto_in_d_bits_corrupt,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [2:0]  auto_out_a_bits_size,
  output [1:0]  auto_out_a_bits_source,
  output [27:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [2:0]  auto_out_d_bits_size,
  input  [1:0]  auto_out_d_bits_source,
  input  [31:0] auto_out_d_bits_data
);
  wire  bundleOut_0_a_q_clock; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_reset; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_enq_ready; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_enq_valid; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
  wire [1:0] bundleOut_0_a_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
  wire [27:0] bundleOut_0_a_q_io_enq_bits_address; // @[Decoupled.scala 361:21]
  wire [3:0] bundleOut_0_a_q_io_enq_bits_mask; // @[Decoupled.scala 361:21]
  wire [31:0] bundleOut_0_a_q_io_enq_bits_data; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_enq_bits_corrupt; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_deq_ready; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_deq_valid; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
  wire [2:0] bundleOut_0_a_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
  wire [1:0] bundleOut_0_a_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
  wire [27:0] bundleOut_0_a_q_io_deq_bits_address; // @[Decoupled.scala 361:21]
  wire [3:0] bundleOut_0_a_q_io_deq_bits_mask; // @[Decoupled.scala 361:21]
  wire [31:0] bundleOut_0_a_q_io_deq_bits_data; // @[Decoupled.scala 361:21]
  wire  bundleOut_0_a_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_clock; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_reset; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_enq_ready; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_enq_valid; // @[Decoupled.scala 361:21]
  wire [2:0] bundleIn_0_d_q_io_enq_bits_opcode; // @[Decoupled.scala 361:21]
  wire [1:0] bundleIn_0_d_q_io_enq_bits_param; // @[Decoupled.scala 361:21]
  wire [2:0] bundleIn_0_d_q_io_enq_bits_size; // @[Decoupled.scala 361:21]
  wire [1:0] bundleIn_0_d_q_io_enq_bits_source; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_enq_bits_sink; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_enq_bits_denied; // @[Decoupled.scala 361:21]
  wire [31:0] bundleIn_0_d_q_io_enq_bits_data; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_enq_bits_corrupt; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_deq_ready; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_deq_valid; // @[Decoupled.scala 361:21]
  wire [2:0] bundleIn_0_d_q_io_deq_bits_opcode; // @[Decoupled.scala 361:21]
  wire [1:0] bundleIn_0_d_q_io_deq_bits_param; // @[Decoupled.scala 361:21]
  wire [2:0] bundleIn_0_d_q_io_deq_bits_size; // @[Decoupled.scala 361:21]
  wire [1:0] bundleIn_0_d_q_io_deq_bits_source; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_deq_bits_sink; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_deq_bits_denied; // @[Decoupled.scala 361:21]
  wire [31:0] bundleIn_0_d_q_io_deq_bits_data; // @[Decoupled.scala 361:21]
  wire  bundleIn_0_d_q_io_deq_bits_corrupt; // @[Decoupled.scala 361:21]
  Queue_20 bundleOut_0_a_q ( // @[Decoupled.scala 361:21]
    .clock(bundleOut_0_a_q_clock),
    .reset(bundleOut_0_a_q_reset),
    .io_enq_ready(bundleOut_0_a_q_io_enq_ready),
    .io_enq_valid(bundleOut_0_a_q_io_enq_valid),
    .io_enq_bits_opcode(bundleOut_0_a_q_io_enq_bits_opcode),
    .io_enq_bits_param(bundleOut_0_a_q_io_enq_bits_param),
    .io_enq_bits_size(bundleOut_0_a_q_io_enq_bits_size),
    .io_enq_bits_source(bundleOut_0_a_q_io_enq_bits_source),
    .io_enq_bits_address(bundleOut_0_a_q_io_enq_bits_address),
    .io_enq_bits_mask(bundleOut_0_a_q_io_enq_bits_mask),
    .io_enq_bits_data(bundleOut_0_a_q_io_enq_bits_data),
    .io_enq_bits_corrupt(bundleOut_0_a_q_io_enq_bits_corrupt),
    .io_deq_ready(bundleOut_0_a_q_io_deq_ready),
    .io_deq_valid(bundleOut_0_a_q_io_deq_valid),
    .io_deq_bits_opcode(bundleOut_0_a_q_io_deq_bits_opcode),
    .io_deq_bits_param(bundleOut_0_a_q_io_deq_bits_param),
    .io_deq_bits_size(bundleOut_0_a_q_io_deq_bits_size),
    .io_deq_bits_source(bundleOut_0_a_q_io_deq_bits_source),
    .io_deq_bits_address(bundleOut_0_a_q_io_deq_bits_address),
    .io_deq_bits_mask(bundleOut_0_a_q_io_deq_bits_mask),
    .io_deq_bits_data(bundleOut_0_a_q_io_deq_bits_data),
    .io_deq_bits_corrupt(bundleOut_0_a_q_io_deq_bits_corrupt)
  );
  Queue_1 bundleIn_0_d_q ( // @[Decoupled.scala 361:21]
    .clock(bundleIn_0_d_q_clock),
    .reset(bundleIn_0_d_q_reset),
    .io_enq_ready(bundleIn_0_d_q_io_enq_ready),
    .io_enq_valid(bundleIn_0_d_q_io_enq_valid),
    .io_enq_bits_opcode(bundleIn_0_d_q_io_enq_bits_opcode),
    .io_enq_bits_param(bundleIn_0_d_q_io_enq_bits_param),
    .io_enq_bits_size(bundleIn_0_d_q_io_enq_bits_size),
    .io_enq_bits_source(bundleIn_0_d_q_io_enq_bits_source),
    .io_enq_bits_sink(bundleIn_0_d_q_io_enq_bits_sink),
    .io_enq_bits_denied(bundleIn_0_d_q_io_enq_bits_denied),
    .io_enq_bits_data(bundleIn_0_d_q_io_enq_bits_data),
    .io_enq_bits_corrupt(bundleIn_0_d_q_io_enq_bits_corrupt),
    .io_deq_ready(bundleIn_0_d_q_io_deq_ready),
    .io_deq_valid(bundleIn_0_d_q_io_deq_valid),
    .io_deq_bits_opcode(bundleIn_0_d_q_io_deq_bits_opcode),
    .io_deq_bits_param(bundleIn_0_d_q_io_deq_bits_param),
    .io_deq_bits_size(bundleIn_0_d_q_io_deq_bits_size),
    .io_deq_bits_source(bundleIn_0_d_q_io_deq_bits_source),
    .io_deq_bits_sink(bundleIn_0_d_q_io_deq_bits_sink),
    .io_deq_bits_denied(bundleIn_0_d_q_io_deq_bits_denied),
    .io_deq_bits_data(bundleIn_0_d_q_io_deq_bits_data),
    .io_deq_bits_corrupt(bundleIn_0_d_q_io_deq_bits_corrupt)
  );
  assign auto_in_a_ready = bundleOut_0_a_q_io_enq_ready; // @[Nodes.scala 1210:84 Decoupled.scala 365:17]
  assign auto_in_d_valid = bundleIn_0_d_q_io_deq_valid; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_opcode = bundleIn_0_d_q_io_deq_bits_opcode; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_param = bundleIn_0_d_q_io_deq_bits_param; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_size = bundleIn_0_d_q_io_deq_bits_size; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_source = bundleIn_0_d_q_io_deq_bits_source; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_sink = bundleIn_0_d_q_io_deq_bits_sink; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_denied = bundleIn_0_d_q_io_deq_bits_denied; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_data = bundleIn_0_d_q_io_deq_bits_data; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_in_d_bits_corrupt = bundleIn_0_d_q_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 Buffer.scala 38:13]
  assign auto_out_a_valid = bundleOut_0_a_q_io_deq_valid; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_opcode = bundleOut_0_a_q_io_deq_bits_opcode; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_param = bundleOut_0_a_q_io_deq_bits_param; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_size = bundleOut_0_a_q_io_deq_bits_size; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_source = bundleOut_0_a_q_io_deq_bits_source; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_address = bundleOut_0_a_q_io_deq_bits_address; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_mask = bundleOut_0_a_q_io_deq_bits_mask; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_data = bundleOut_0_a_q_io_deq_bits_data; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_a_bits_corrupt = bundleOut_0_a_q_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 Buffer.scala 37:13]
  assign auto_out_d_ready = bundleIn_0_d_q_io_enq_ready; // @[Nodes.scala 1207:84 Decoupled.scala 365:17]
  assign bundleOut_0_a_q_clock = clock;
  assign bundleOut_0_a_q_reset = reset;
  assign bundleOut_0_a_q_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_q_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_clock = clock;
  assign bundleIn_0_d_q_reset = reset;
  assign bundleIn_0_d_q_io_enq_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_param = 2'h0; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_sink = 1'h0; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_denied = 1'h0; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_enq_bits_corrupt = 1'h0; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_q_io_deq_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module NonSyncResetSynchronizerPrimitiveShiftReg_d3(
  input   clock,
  input   io_d,
  output  io_q
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
  reg  sync_0; // @[SynchronizerReg.scala 51:66]
  reg  sync_1; // @[SynchronizerReg.scala 51:66]
  reg  sync_2; // @[SynchronizerReg.scala 51:66]
  assign io_q = sync_0; // @[SynchronizerReg.scala 59:8]
  always @(posedge clock) begin
    sync_0 <= sync_1; // @[SynchronizerReg.scala 57:10]
    sync_1 <= sync_2; // @[SynchronizerReg.scala 57:10]
    sync_2 <= io_d; // @[SynchronizerReg.scala 54:22]
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  sync_0 = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  sync_1 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  sync_2 = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module SynchronizerShiftReg_w1_d3(
  input   clock,
  input   io_d,
  output  io_q
);
  wire  output_chain_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_io_q; // @[ShiftReg.scala 45:23]
  NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_clock),
    .io_d(output_chain_io_d),
    .io_q(output_chain_io_q)
  );
  assign io_q = output_chain_io_q; // @[ShiftReg.scala 48:{24,24}]
  assign output_chain_clock = clock;
  assign output_chain_io_d = io_d; // @[SynchronizerReg.scala 173:39]
endmodule
module IntSyncAsyncCrossingSink(
  input   clock,
  input   auto_in_sync_0,
  output  auto_out_0
);
  wire  chain_clock; // @[ShiftReg.scala 45:23]
  wire  chain_io_d; // @[ShiftReg.scala 45:23]
  wire  chain_io_q; // @[ShiftReg.scala 45:23]
  SynchronizerShiftReg_w1_d3 chain ( // @[ShiftReg.scala 45:23]
    .clock(chain_clock),
    .io_d(chain_io_d),
    .io_q(chain_io_q)
  );
  assign auto_out_0 = chain_io_q; // @[ShiftReg.scala 48:24]
  assign chain_clock = clock;
  assign chain_io_d = auto_in_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module IntSyncSyncCrossingSink(
  input   auto_in_sync_0,
  input   auto_in_sync_1,
  output  auto_out_0,
  output  auto_out_1
);
  assign auto_out_0 = auto_in_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1 = auto_in_sync_1; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module IntSyncSyncCrossingSink_1(
  input   auto_in_sync_0,
  output  auto_out_0
);
  assign auto_out_0 = auto_in_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module AsyncResetRegVec_w1_i0(
  input   clock,
  input   reset,
  input   io_d,
  output  io_q,
  input   io_en
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg  reg_; // @[AsyncResetReg.scala 64:50]
  assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[AsyncResetReg.scala 65:16]
      reg_ <= 1'h0; // @[AsyncResetReg.scala 66:9]
    end else if (io_en) begin // @[AsyncResetReg.scala 64:50]
      reg_ <= io_d;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  reg_ = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
  if (reset) begin
    reg_ = 1'h0;
  end
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module IntSyncCrossingSource_1(
  input   clock,
  input   reset,
  input   auto_in_0,
  output  auto_out_sync_0
);
  wire  reg__clock; // @[AsyncResetReg.scala 89:21]
  wire  reg__reset; // @[AsyncResetReg.scala 89:21]
  wire  reg__io_d; // @[AsyncResetReg.scala 89:21]
  wire  reg__io_q; // @[AsyncResetReg.scala 89:21]
  wire  reg__io_en; // @[AsyncResetReg.scala 89:21]
  AsyncResetRegVec_w1_i0 reg_ ( // @[AsyncResetReg.scala 89:21]
    .clock(reg__clock),
    .reset(reg__reset),
    .io_d(reg__io_d),
    .io_q(reg__io_q),
    .io_en(reg__io_en)
  );
  assign auto_out_sync_0 = reg__io_q; // @[Crossing.scala 41:52]
  assign reg__clock = clock;
  assign reg__reset = reset;
  assign reg__io_d = auto_in_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign reg__io_en = 1'h1; // @[AsyncResetReg.scala 92:15]
endmodule
module TilePRCIDomain(
  input         auto_intsink_in_sync_0,
  input         auto_tile_reset_domain_tile_hartid_in,
  output        auto_int_out_clock_xing_out_2_sync_0,
  output        auto_int_out_clock_xing_out_1_sync_0,
  output        auto_int_out_clock_xing_out_0_sync_0,
  input         auto_int_in_clock_xing_in_2_sync_0,
  input         auto_int_in_clock_xing_in_1_sync_0,
  input         auto_int_in_clock_xing_in_0_sync_0,
  input         auto_int_in_clock_xing_in_0_sync_1,
  output        auto_tl_slave_clock_xing_in_a_ready,
  input         auto_tl_slave_clock_xing_in_a_valid,
  input  [2:0]  auto_tl_slave_clock_xing_in_a_bits_opcode,
  input  [2:0]  auto_tl_slave_clock_xing_in_a_bits_param,
  input  [2:0]  auto_tl_slave_clock_xing_in_a_bits_size,
  input  [1:0]  auto_tl_slave_clock_xing_in_a_bits_source,
  input  [27:0] auto_tl_slave_clock_xing_in_a_bits_address,
  input  [3:0]  auto_tl_slave_clock_xing_in_a_bits_mask,
  input  [31:0] auto_tl_slave_clock_xing_in_a_bits_data,
  input         auto_tl_slave_clock_xing_in_a_bits_corrupt,
  input         auto_tl_slave_clock_xing_in_d_ready,
  output        auto_tl_slave_clock_xing_in_d_valid,
  output [2:0]  auto_tl_slave_clock_xing_in_d_bits_opcode,
  output [1:0]  auto_tl_slave_clock_xing_in_d_bits_param,
  output [2:0]  auto_tl_slave_clock_xing_in_d_bits_size,
  output [1:0]  auto_tl_slave_clock_xing_in_d_bits_source,
  output        auto_tl_slave_clock_xing_in_d_bits_sink,
  output        auto_tl_slave_clock_xing_in_d_bits_denied,
  output [31:0] auto_tl_slave_clock_xing_in_d_bits_data,
  output        auto_tl_slave_clock_xing_in_d_bits_corrupt,
  input         auto_tl_master_clock_xing_out_a_ready,
  output        auto_tl_master_clock_xing_out_a_valid,
  output [2:0]  auto_tl_master_clock_xing_out_a_bits_opcode,
  output [2:0]  auto_tl_master_clock_xing_out_a_bits_param,
  output [3:0]  auto_tl_master_clock_xing_out_a_bits_size,
  output [1:0]  auto_tl_master_clock_xing_out_a_bits_source,
  output [30:0] auto_tl_master_clock_xing_out_a_bits_address,
  output [3:0]  auto_tl_master_clock_xing_out_a_bits_mask,
  output [31:0] auto_tl_master_clock_xing_out_a_bits_data,
  output        auto_tl_master_clock_xing_out_a_bits_corrupt,
  output        auto_tl_master_clock_xing_out_b_ready,
  input         auto_tl_master_clock_xing_out_b_valid,
  input  [1:0]  auto_tl_master_clock_xing_out_b_bits_param,
  input  [30:0] auto_tl_master_clock_xing_out_b_bits_address,
  input         auto_tl_master_clock_xing_out_c_ready,
  output        auto_tl_master_clock_xing_out_c_valid,
  output [2:0]  auto_tl_master_clock_xing_out_c_bits_opcode,
  output [2:0]  auto_tl_master_clock_xing_out_c_bits_param,
  output [3:0]  auto_tl_master_clock_xing_out_c_bits_size,
  output [1:0]  auto_tl_master_clock_xing_out_c_bits_source,
  output [30:0] auto_tl_master_clock_xing_out_c_bits_address,
  output [31:0] auto_tl_master_clock_xing_out_c_bits_data,
  output        auto_tl_master_clock_xing_out_c_bits_corrupt,
  output        auto_tl_master_clock_xing_out_d_ready,
  input         auto_tl_master_clock_xing_out_d_valid,
  input  [2:0]  auto_tl_master_clock_xing_out_d_bits_opcode,
  input  [1:0]  auto_tl_master_clock_xing_out_d_bits_param,
  input  [3:0]  auto_tl_master_clock_xing_out_d_bits_size,
  input  [1:0]  auto_tl_master_clock_xing_out_d_bits_source,
  input  [1:0]  auto_tl_master_clock_xing_out_d_bits_sink,
  input         auto_tl_master_clock_xing_out_d_bits_denied,
  input  [31:0] auto_tl_master_clock_xing_out_d_bits_data,
  input         auto_tl_master_clock_xing_out_d_bits_corrupt,
  output        auto_tl_master_clock_xing_out_e_valid,
  output [1:0]  auto_tl_master_clock_xing_out_e_bits_sink,
  input         auto_tap_clock_in_clock,
  input         auto_tap_clock_in_reset
);
  wire  tile_reset_domain_auto_tile_slave_in_a_ready; // @[TilePRCIDomain.scala 45:37]
  wire  tile_reset_domain_auto_tile_slave_in_a_valid; // @[TilePRCIDomain.scala 45:37]
  wire [2:0] tile_reset_domain_auto_tile_slave_in_a_bits_opcode; // @[TilePRCIDomain.scala 45:37]
  wire [2:0] tile_reset_domain_auto_tile_slave_in_a_bits_param; // @[TilePRCIDomain.scala 45:37]
  wire [2:0] tile_reset_domain_auto_tile_slave_in_a_bits_size; // @[TilePRCIDomain.scala 45:37]
  wire [1:0] tile_reset_domain_auto_tile_slave_in_a_bits_source; // @[TilePRCIDomain.scala 45:37]
  wire [27:0] tile_reset_domain_auto_tile_slave_in_a_bits_address; // @[TilePRCIDomain.scala 45:37]
  wire [3:0] tile_reset_domain_auto_tile_slave_in_a_bits_mask; // @[TilePRCIDomain.scala 45:37]
  wire [31:0] tile_reset_domain_auto_tile_slave_in_a_bits_data; // @[TilePRCIDomain.scala 45:37]
  wire  tile_reset_domain_auto_tile_slave_in_a_bits_corrupt; // @[TilePRCIDomain.scala 45:37]
  wire  tile_reset_domain_auto_tile_slave_in_d_ready; // @[TilePRCIDomain.scala 45:37]
  wire  tile_reset_domain_auto_tile_slave_in_d_valid; // @[TilePRCIDomain.scala 45:37]
  wire [2:0] tile_reset_domain_auto_tile_slave_in_d_bits_opcode; // @[TilePRCIDomain.scala 45:37]
  wire [2:0] tile_reset_domain_auto_tile_slave_in_d_bits_size; // @[TilePRCIDomain.scala 45:37]
  wire [1:0] tile_reset_domain_auto_tile_slave_in_d_bits_source; // @[TilePRCIDomain.scala 45:37]
  wire [31:0] tile_reset_domain_auto_tile_slave_in_d_bits_data; // @[TilePRCIDomain.scala 45:37]
  wire  tile_reset_domain_auto_tile_wfi_out_0; // @[TilePRCIDomain.scala 45:37]
  wire  tile_reset_domain_auto_tile_int_local_in_3_0; // @[TilePRCIDomain.scala 45:37]
  wire  tile_reset_domain_auto_tile_int_local_in_2_0; // @[TilePRCIDomain.scala 45:37]
  wire  tile_reset_domain_auto_tile_int_local_in_1_0; // @[TilePRCIDomain.scala 45:37]
  wire  tile_reset_domain_auto_tile_int_local_in_1_1; // @[TilePRCIDomain.scala 45:37]
  wire  tile_reset_domain_auto_tile_int_local_in_0_0; // @[TilePRCIDomain.scala 45:37]
  wire  tile_reset_domain_auto_tile_hartid_in; // @[TilePRCIDomain.scala 45:37]
  wire  tile_reset_domain_auto_tile_tl_other_masters_out_a_ready; // @[TilePRCIDomain.scala 45:37]
  wire  tile_reset_domain_auto_tile_tl_other_masters_out_a_valid; // @[TilePRCIDomain.scala 45:37]
  wire [2:0] tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_opcode; // @[TilePRCIDomain.scala 45:37]
  wire [2:0] tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_param; // @[TilePRCIDomain.scala 45:37]
  wire [3:0] tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_size; // @[TilePRCIDomain.scala 45:37]
  wire [1:0] tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_source; // @[TilePRCIDomain.scala 45:37]
  wire [30:0] tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_address; // @[TilePRCIDomain.scala 45:37]
  wire [3:0] tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_mask; // @[TilePRCIDomain.scala 45:37]
  wire [31:0] tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_data; // @[TilePRCIDomain.scala 45:37]
  wire  tile_reset_domain_auto_tile_tl_other_masters_out_b_ready; // @[TilePRCIDomain.scala 45:37]
  wire  tile_reset_domain_auto_tile_tl_other_masters_out_b_valid; // @[TilePRCIDomain.scala 45:37]
  wire [2:0] tile_reset_domain_auto_tile_tl_other_masters_out_b_bits_opcode; // @[TilePRCIDomain.scala 45:37]
  wire [1:0] tile_reset_domain_auto_tile_tl_other_masters_out_b_bits_param; // @[TilePRCIDomain.scala 45:37]
  wire [3:0] tile_reset_domain_auto_tile_tl_other_masters_out_b_bits_size; // @[TilePRCIDomain.scala 45:37]
  wire [1:0] tile_reset_domain_auto_tile_tl_other_masters_out_b_bits_source; // @[TilePRCIDomain.scala 45:37]
  wire [30:0] tile_reset_domain_auto_tile_tl_other_masters_out_b_bits_address; // @[TilePRCIDomain.scala 45:37]
  wire [3:0] tile_reset_domain_auto_tile_tl_other_masters_out_b_bits_mask; // @[TilePRCIDomain.scala 45:37]
  wire  tile_reset_domain_auto_tile_tl_other_masters_out_b_bits_corrupt; // @[TilePRCIDomain.scala 45:37]
  wire  tile_reset_domain_auto_tile_tl_other_masters_out_c_ready; // @[TilePRCIDomain.scala 45:37]
  wire  tile_reset_domain_auto_tile_tl_other_masters_out_c_valid; // @[TilePRCIDomain.scala 45:37]
  wire [2:0] tile_reset_domain_auto_tile_tl_other_masters_out_c_bits_opcode; // @[TilePRCIDomain.scala 45:37]
  wire [2:0] tile_reset_domain_auto_tile_tl_other_masters_out_c_bits_param; // @[TilePRCIDomain.scala 45:37]
  wire [3:0] tile_reset_domain_auto_tile_tl_other_masters_out_c_bits_size; // @[TilePRCIDomain.scala 45:37]
  wire [1:0] tile_reset_domain_auto_tile_tl_other_masters_out_c_bits_source; // @[TilePRCIDomain.scala 45:37]
  wire [30:0] tile_reset_domain_auto_tile_tl_other_masters_out_c_bits_address; // @[TilePRCIDomain.scala 45:37]
  wire [31:0] tile_reset_domain_auto_tile_tl_other_masters_out_c_bits_data; // @[TilePRCIDomain.scala 45:37]
  wire  tile_reset_domain_auto_tile_tl_other_masters_out_d_ready; // @[TilePRCIDomain.scala 45:37]
  wire  tile_reset_domain_auto_tile_tl_other_masters_out_d_valid; // @[TilePRCIDomain.scala 45:37]
  wire [2:0] tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_opcode; // @[TilePRCIDomain.scala 45:37]
  wire [1:0] tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_param; // @[TilePRCIDomain.scala 45:37]
  wire [3:0] tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_size; // @[TilePRCIDomain.scala 45:37]
  wire [1:0] tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_source; // @[TilePRCIDomain.scala 45:37]
  wire [1:0] tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_sink; // @[TilePRCIDomain.scala 45:37]
  wire  tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_denied; // @[TilePRCIDomain.scala 45:37]
  wire [31:0] tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_data; // @[TilePRCIDomain.scala 45:37]
  wire  tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_corrupt; // @[TilePRCIDomain.scala 45:37]
  wire  tile_reset_domain_auto_tile_tl_other_masters_out_e_ready; // @[TilePRCIDomain.scala 45:37]
  wire  tile_reset_domain_auto_tile_tl_other_masters_out_e_valid; // @[TilePRCIDomain.scala 45:37]
  wire [1:0] tile_reset_domain_auto_tile_tl_other_masters_out_e_bits_sink; // @[TilePRCIDomain.scala 45:37]
  wire  tile_reset_domain_auto_clock_in_clock; // @[TilePRCIDomain.scala 45:37]
  wire  tile_reset_domain_auto_clock_in_reset; // @[TilePRCIDomain.scala 45:37]
  wire  clockNode_auto_in_clock; // @[ClockGroup.scala 106:107]
  wire  clockNode_auto_in_reset; // @[ClockGroup.scala 106:107]
  wire  clockNode_auto_out_clock; // @[ClockGroup.scala 106:107]
  wire  clockNode_auto_out_reset; // @[ClockGroup.scala 106:107]
  wire  buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
  wire [30:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_b_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_b_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_b_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_b_bits_param; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_in_b_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_b_bits_source; // @[Buffer.scala 68:28]
  wire [30:0] buffer_auto_in_b_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_in_b_bits_mask; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_b_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_c_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_c_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_c_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_c_bits_param; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_in_c_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_c_bits_source; // @[Buffer.scala 68:28]
  wire [30:0] buffer_auto_in_c_bits_address; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_c_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_d_bits_sink; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_bits_denied; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_e_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_e_valid; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_e_bits_sink; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
  wire [30:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_b_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_b_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_b_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_b_bits_param; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_out_b_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_b_bits_source; // @[Buffer.scala 68:28]
  wire [30:0] buffer_auto_out_b_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_out_b_bits_mask; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_b_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_c_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_c_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_c_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_c_bits_param; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_out_c_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_c_bits_source; // @[Buffer.scala 68:28]
  wire [30:0] buffer_auto_out_c_bits_address; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_c_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_d_bits_param; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_d_bits_sink; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_bits_denied; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_e_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_e_valid; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_e_bits_sink; // @[Buffer.scala 68:28]
  wire  buffer_1_clock; // @[Buffer.scala 68:28]
  wire  buffer_1_reset; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_in_a_bits_param; // @[Buffer.scala 68:28]
  wire [3:0] buffer_1_auto_in_a_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_1_auto_in_a_bits_source; // @[Buffer.scala 68:28]
  wire [30:0] buffer_1_auto_in_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_1_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_1_auto_in_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_b_ready; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_b_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_in_b_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_1_auto_in_b_bits_param; // @[Buffer.scala 68:28]
  wire [3:0] buffer_1_auto_in_b_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_1_auto_in_b_bits_source; // @[Buffer.scala 68:28]
  wire [30:0] buffer_1_auto_in_b_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_1_auto_in_b_bits_mask; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_b_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_c_ready; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_c_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_in_c_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_in_c_bits_param; // @[Buffer.scala 68:28]
  wire [3:0] buffer_1_auto_in_c_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_1_auto_in_c_bits_source; // @[Buffer.scala 68:28]
  wire [30:0] buffer_1_auto_in_c_bits_address; // @[Buffer.scala 68:28]
  wire [31:0] buffer_1_auto_in_c_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_1_auto_in_d_bits_param; // @[Buffer.scala 68:28]
  wire [3:0] buffer_1_auto_in_d_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_1_auto_in_d_bits_source; // @[Buffer.scala 68:28]
  wire [1:0] buffer_1_auto_in_d_bits_sink; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_d_bits_denied; // @[Buffer.scala 68:28]
  wire [31:0] buffer_1_auto_in_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_d_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_e_ready; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_e_valid; // @[Buffer.scala 68:28]
  wire [1:0] buffer_1_auto_in_e_bits_sink; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_out_a_bits_param; // @[Buffer.scala 68:28]
  wire [3:0] buffer_1_auto_out_a_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_1_auto_out_a_bits_source; // @[Buffer.scala 68:28]
  wire [30:0] buffer_1_auto_out_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_1_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_1_auto_out_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_b_ready; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_b_valid; // @[Buffer.scala 68:28]
  wire [1:0] buffer_1_auto_out_b_bits_param; // @[Buffer.scala 68:28]
  wire [30:0] buffer_1_auto_out_b_bits_address; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_c_ready; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_c_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_out_c_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_out_c_bits_param; // @[Buffer.scala 68:28]
  wire [3:0] buffer_1_auto_out_c_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_1_auto_out_c_bits_source; // @[Buffer.scala 68:28]
  wire [30:0] buffer_1_auto_out_c_bits_address; // @[Buffer.scala 68:28]
  wire [31:0] buffer_1_auto_out_c_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_c_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_1_auto_out_d_bits_param; // @[Buffer.scala 68:28]
  wire [3:0] buffer_1_auto_out_d_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_1_auto_out_d_bits_source; // @[Buffer.scala 68:28]
  wire [1:0] buffer_1_auto_out_d_bits_sink; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_d_bits_denied; // @[Buffer.scala 68:28]
  wire [31:0] buffer_1_auto_out_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_d_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_e_valid; // @[Buffer.scala 68:28]
  wire [1:0] buffer_1_auto_out_e_bits_sink; // @[Buffer.scala 68:28]
  wire  buffer_2_auto_in_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_2_auto_in_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_2_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_2_auto_in_a_bits_param; // @[Buffer.scala 68:28]
  wire [2:0] buffer_2_auto_in_a_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_2_auto_in_a_bits_source; // @[Buffer.scala 68:28]
  wire [27:0] buffer_2_auto_in_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_2_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_2_auto_in_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_2_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_2_auto_in_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_2_auto_in_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_2_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_2_auto_in_d_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_2_auto_in_d_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_2_auto_in_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_2_auto_out_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_2_auto_out_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_2_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_2_auto_out_a_bits_param; // @[Buffer.scala 68:28]
  wire [2:0] buffer_2_auto_out_a_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_2_auto_out_a_bits_source; // @[Buffer.scala 68:28]
  wire [27:0] buffer_2_auto_out_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_2_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_2_auto_out_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_2_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_2_auto_out_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_2_auto_out_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_2_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_2_auto_out_d_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_2_auto_out_d_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_2_auto_out_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_3_clock; // @[Buffer.scala 68:28]
  wire  buffer_3_reset; // @[Buffer.scala 68:28]
  wire  buffer_3_auto_in_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_3_auto_in_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_3_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_3_auto_in_a_bits_param; // @[Buffer.scala 68:28]
  wire [2:0] buffer_3_auto_in_a_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_3_auto_in_a_bits_source; // @[Buffer.scala 68:28]
  wire [27:0] buffer_3_auto_in_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_3_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_3_auto_in_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_3_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_3_auto_in_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_3_auto_in_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_3_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_3_auto_in_d_bits_param; // @[Buffer.scala 68:28]
  wire [2:0] buffer_3_auto_in_d_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_3_auto_in_d_bits_source; // @[Buffer.scala 68:28]
  wire  buffer_3_auto_in_d_bits_sink; // @[Buffer.scala 68:28]
  wire  buffer_3_auto_in_d_bits_denied; // @[Buffer.scala 68:28]
  wire [31:0] buffer_3_auto_in_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_3_auto_in_d_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_3_auto_out_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_3_auto_out_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_3_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_3_auto_out_a_bits_param; // @[Buffer.scala 68:28]
  wire [2:0] buffer_3_auto_out_a_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_3_auto_out_a_bits_source; // @[Buffer.scala 68:28]
  wire [27:0] buffer_3_auto_out_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_3_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_3_auto_out_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_3_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_3_auto_out_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_3_auto_out_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_3_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_3_auto_out_d_bits_size; // @[Buffer.scala 68:28]
  wire [1:0] buffer_3_auto_out_d_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_3_auto_out_d_bits_data; // @[Buffer.scala 68:28]
  wire  intsink_clock; // @[Crossing.scala 74:29]
  wire  intsink_auto_in_sync_0; // @[Crossing.scala 74:29]
  wire  intsink_auto_out_0; // @[Crossing.scala 74:29]
  wire  intsink_1_auto_in_sync_0; // @[Crossing.scala 94:29]
  wire  intsink_1_auto_in_sync_1; // @[Crossing.scala 94:29]
  wire  intsink_1_auto_out_0; // @[Crossing.scala 94:29]
  wire  intsink_1_auto_out_1; // @[Crossing.scala 94:29]
  wire  intsink_2_auto_in_sync_0; // @[Crossing.scala 94:29]
  wire  intsink_2_auto_out_0; // @[Crossing.scala 94:29]
  wire  intsink_3_auto_in_sync_0; // @[Crossing.scala 94:29]
  wire  intsink_3_auto_out_0; // @[Crossing.scala 94:29]
  wire  intsource_1_clock; // @[Crossing.scala 26:31]
  wire  intsource_1_reset; // @[Crossing.scala 26:31]
  wire  intsource_1_auto_in_0; // @[Crossing.scala 26:31]
  wire  intsource_1_auto_out_sync_0; // @[Crossing.scala 26:31]
  wire  intsource_2_clock; // @[Crossing.scala 26:31]
  wire  intsource_2_reset; // @[Crossing.scala 26:31]
  wire  intsource_2_auto_in_0; // @[Crossing.scala 26:31]
  wire  intsource_2_auto_out_sync_0; // @[Crossing.scala 26:31]
  wire  intsource_3_clock; // @[Crossing.scala 26:31]
  wire  intsource_3_reset; // @[Crossing.scala 26:31]
  wire  intsource_3_auto_in_0; // @[Crossing.scala 26:31]
  wire  intsource_3_auto_out_sync_0; // @[Crossing.scala 26:31]
  TileResetDomain tile_reset_domain ( // @[TilePRCIDomain.scala 45:37]
    .auto_tile_slave_in_a_ready(tile_reset_domain_auto_tile_slave_in_a_ready),
    .auto_tile_slave_in_a_valid(tile_reset_domain_auto_tile_slave_in_a_valid),
    .auto_tile_slave_in_a_bits_opcode(tile_reset_domain_auto_tile_slave_in_a_bits_opcode),
    .auto_tile_slave_in_a_bits_param(tile_reset_domain_auto_tile_slave_in_a_bits_param),
    .auto_tile_slave_in_a_bits_size(tile_reset_domain_auto_tile_slave_in_a_bits_size),
    .auto_tile_slave_in_a_bits_source(tile_reset_domain_auto_tile_slave_in_a_bits_source),
    .auto_tile_slave_in_a_bits_address(tile_reset_domain_auto_tile_slave_in_a_bits_address),
    .auto_tile_slave_in_a_bits_mask(tile_reset_domain_auto_tile_slave_in_a_bits_mask),
    .auto_tile_slave_in_a_bits_data(tile_reset_domain_auto_tile_slave_in_a_bits_data),
    .auto_tile_slave_in_a_bits_corrupt(tile_reset_domain_auto_tile_slave_in_a_bits_corrupt),
    .auto_tile_slave_in_d_ready(tile_reset_domain_auto_tile_slave_in_d_ready),
    .auto_tile_slave_in_d_valid(tile_reset_domain_auto_tile_slave_in_d_valid),
    .auto_tile_slave_in_d_bits_opcode(tile_reset_domain_auto_tile_slave_in_d_bits_opcode),
    .auto_tile_slave_in_d_bits_size(tile_reset_domain_auto_tile_slave_in_d_bits_size),
    .auto_tile_slave_in_d_bits_source(tile_reset_domain_auto_tile_slave_in_d_bits_source),
    .auto_tile_slave_in_d_bits_data(tile_reset_domain_auto_tile_slave_in_d_bits_data),
    .auto_tile_wfi_out_0(tile_reset_domain_auto_tile_wfi_out_0),
    .auto_tile_int_local_in_3_0(tile_reset_domain_auto_tile_int_local_in_3_0),
    .auto_tile_int_local_in_2_0(tile_reset_domain_auto_tile_int_local_in_2_0),
    .auto_tile_int_local_in_1_0(tile_reset_domain_auto_tile_int_local_in_1_0),
    .auto_tile_int_local_in_1_1(tile_reset_domain_auto_tile_int_local_in_1_1),
    .auto_tile_int_local_in_0_0(tile_reset_domain_auto_tile_int_local_in_0_0),
    .auto_tile_hartid_in(tile_reset_domain_auto_tile_hartid_in),
    .auto_tile_tl_other_masters_out_a_ready(tile_reset_domain_auto_tile_tl_other_masters_out_a_ready),
    .auto_tile_tl_other_masters_out_a_valid(tile_reset_domain_auto_tile_tl_other_masters_out_a_valid),
    .auto_tile_tl_other_masters_out_a_bits_opcode(tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_opcode),
    .auto_tile_tl_other_masters_out_a_bits_param(tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_param),
    .auto_tile_tl_other_masters_out_a_bits_size(tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_size),
    .auto_tile_tl_other_masters_out_a_bits_source(tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_source),
    .auto_tile_tl_other_masters_out_a_bits_address(tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_address),
    .auto_tile_tl_other_masters_out_a_bits_mask(tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_mask),
    .auto_tile_tl_other_masters_out_a_bits_data(tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_data),
    .auto_tile_tl_other_masters_out_b_ready(tile_reset_domain_auto_tile_tl_other_masters_out_b_ready),
    .auto_tile_tl_other_masters_out_b_valid(tile_reset_domain_auto_tile_tl_other_masters_out_b_valid),
    .auto_tile_tl_other_masters_out_b_bits_opcode(tile_reset_domain_auto_tile_tl_other_masters_out_b_bits_opcode),
    .auto_tile_tl_other_masters_out_b_bits_param(tile_reset_domain_auto_tile_tl_other_masters_out_b_bits_param),
    .auto_tile_tl_other_masters_out_b_bits_size(tile_reset_domain_auto_tile_tl_other_masters_out_b_bits_size),
    .auto_tile_tl_other_masters_out_b_bits_source(tile_reset_domain_auto_tile_tl_other_masters_out_b_bits_source),
    .auto_tile_tl_other_masters_out_b_bits_address(tile_reset_domain_auto_tile_tl_other_masters_out_b_bits_address),
    .auto_tile_tl_other_masters_out_b_bits_mask(tile_reset_domain_auto_tile_tl_other_masters_out_b_bits_mask),
    .auto_tile_tl_other_masters_out_b_bits_corrupt(tile_reset_domain_auto_tile_tl_other_masters_out_b_bits_corrupt),
    .auto_tile_tl_other_masters_out_c_ready(tile_reset_domain_auto_tile_tl_other_masters_out_c_ready),
    .auto_tile_tl_other_masters_out_c_valid(tile_reset_domain_auto_tile_tl_other_masters_out_c_valid),
    .auto_tile_tl_other_masters_out_c_bits_opcode(tile_reset_domain_auto_tile_tl_other_masters_out_c_bits_opcode),
    .auto_tile_tl_other_masters_out_c_bits_param(tile_reset_domain_auto_tile_tl_other_masters_out_c_bits_param),
    .auto_tile_tl_other_masters_out_c_bits_size(tile_reset_domain_auto_tile_tl_other_masters_out_c_bits_size),
    .auto_tile_tl_other_masters_out_c_bits_source(tile_reset_domain_auto_tile_tl_other_masters_out_c_bits_source),
    .auto_tile_tl_other_masters_out_c_bits_address(tile_reset_domain_auto_tile_tl_other_masters_out_c_bits_address),
    .auto_tile_tl_other_masters_out_c_bits_data(tile_reset_domain_auto_tile_tl_other_masters_out_c_bits_data),
    .auto_tile_tl_other_masters_out_d_ready(tile_reset_domain_auto_tile_tl_other_masters_out_d_ready),
    .auto_tile_tl_other_masters_out_d_valid(tile_reset_domain_auto_tile_tl_other_masters_out_d_valid),
    .auto_tile_tl_other_masters_out_d_bits_opcode(tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_opcode),
    .auto_tile_tl_other_masters_out_d_bits_param(tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_param),
    .auto_tile_tl_other_masters_out_d_bits_size(tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_size),
    .auto_tile_tl_other_masters_out_d_bits_source(tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_source),
    .auto_tile_tl_other_masters_out_d_bits_sink(tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_sink),
    .auto_tile_tl_other_masters_out_d_bits_denied(tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_denied),
    .auto_tile_tl_other_masters_out_d_bits_data(tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_data),
    .auto_tile_tl_other_masters_out_d_bits_corrupt(tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_corrupt),
    .auto_tile_tl_other_masters_out_e_ready(tile_reset_domain_auto_tile_tl_other_masters_out_e_ready),
    .auto_tile_tl_other_masters_out_e_valid(tile_reset_domain_auto_tile_tl_other_masters_out_e_valid),
    .auto_tile_tl_other_masters_out_e_bits_sink(tile_reset_domain_auto_tile_tl_other_masters_out_e_bits_sink),
    .auto_clock_in_clock(tile_reset_domain_auto_clock_in_clock),
    .auto_clock_in_reset(tile_reset_domain_auto_clock_in_reset)
  );
  FixedClockBroadcast_2 clockNode ( // @[ClockGroup.scala 106:107]
    .auto_in_clock(clockNode_auto_in_clock),
    .auto_in_reset(clockNode_auto_in_reset),
    .auto_out_clock(clockNode_auto_out_clock),
    .auto_out_reset(clockNode_auto_out_reset)
  );
  TLBuffer_9 buffer ( // @[Buffer.scala 68:28]
    .auto_in_a_ready(buffer_auto_in_a_ready),
    .auto_in_a_valid(buffer_auto_in_a_valid),
    .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
    .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
    .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
    .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
    .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
    .auto_in_a_bits_data(buffer_auto_in_a_bits_data),
    .auto_in_b_ready(buffer_auto_in_b_ready),
    .auto_in_b_valid(buffer_auto_in_b_valid),
    .auto_in_b_bits_opcode(buffer_auto_in_b_bits_opcode),
    .auto_in_b_bits_param(buffer_auto_in_b_bits_param),
    .auto_in_b_bits_size(buffer_auto_in_b_bits_size),
    .auto_in_b_bits_source(buffer_auto_in_b_bits_source),
    .auto_in_b_bits_address(buffer_auto_in_b_bits_address),
    .auto_in_b_bits_mask(buffer_auto_in_b_bits_mask),
    .auto_in_b_bits_corrupt(buffer_auto_in_b_bits_corrupt),
    .auto_in_c_ready(buffer_auto_in_c_ready),
    .auto_in_c_valid(buffer_auto_in_c_valid),
    .auto_in_c_bits_opcode(buffer_auto_in_c_bits_opcode),
    .auto_in_c_bits_param(buffer_auto_in_c_bits_param),
    .auto_in_c_bits_size(buffer_auto_in_c_bits_size),
    .auto_in_c_bits_source(buffer_auto_in_c_bits_source),
    .auto_in_c_bits_address(buffer_auto_in_c_bits_address),
    .auto_in_c_bits_data(buffer_auto_in_c_bits_data),
    .auto_in_d_ready(buffer_auto_in_d_ready),
    .auto_in_d_valid(buffer_auto_in_d_valid),
    .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
    .auto_in_d_bits_param(buffer_auto_in_d_bits_param),
    .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
    .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
    .auto_in_d_bits_sink(buffer_auto_in_d_bits_sink),
    .auto_in_d_bits_denied(buffer_auto_in_d_bits_denied),
    .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
    .auto_in_d_bits_corrupt(buffer_auto_in_d_bits_corrupt),
    .auto_in_e_ready(buffer_auto_in_e_ready),
    .auto_in_e_valid(buffer_auto_in_e_valid),
    .auto_in_e_bits_sink(buffer_auto_in_e_bits_sink),
    .auto_out_a_ready(buffer_auto_out_a_ready),
    .auto_out_a_valid(buffer_auto_out_a_valid),
    .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
    .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
    .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
    .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
    .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
    .auto_out_a_bits_data(buffer_auto_out_a_bits_data),
    .auto_out_b_ready(buffer_auto_out_b_ready),
    .auto_out_b_valid(buffer_auto_out_b_valid),
    .auto_out_b_bits_opcode(buffer_auto_out_b_bits_opcode),
    .auto_out_b_bits_param(buffer_auto_out_b_bits_param),
    .auto_out_b_bits_size(buffer_auto_out_b_bits_size),
    .auto_out_b_bits_source(buffer_auto_out_b_bits_source),
    .auto_out_b_bits_address(buffer_auto_out_b_bits_address),
    .auto_out_b_bits_mask(buffer_auto_out_b_bits_mask),
    .auto_out_b_bits_corrupt(buffer_auto_out_b_bits_corrupt),
    .auto_out_c_ready(buffer_auto_out_c_ready),
    .auto_out_c_valid(buffer_auto_out_c_valid),
    .auto_out_c_bits_opcode(buffer_auto_out_c_bits_opcode),
    .auto_out_c_bits_param(buffer_auto_out_c_bits_param),
    .auto_out_c_bits_size(buffer_auto_out_c_bits_size),
    .auto_out_c_bits_source(buffer_auto_out_c_bits_source),
    .auto_out_c_bits_address(buffer_auto_out_c_bits_address),
    .auto_out_c_bits_data(buffer_auto_out_c_bits_data),
    .auto_out_d_ready(buffer_auto_out_d_ready),
    .auto_out_d_valid(buffer_auto_out_d_valid),
    .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
    .auto_out_d_bits_param(buffer_auto_out_d_bits_param),
    .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
    .auto_out_d_bits_source(buffer_auto_out_d_bits_source),
    .auto_out_d_bits_sink(buffer_auto_out_d_bits_sink),
    .auto_out_d_bits_denied(buffer_auto_out_d_bits_denied),
    .auto_out_d_bits_data(buffer_auto_out_d_bits_data),
    .auto_out_d_bits_corrupt(buffer_auto_out_d_bits_corrupt),
    .auto_out_e_ready(buffer_auto_out_e_ready),
    .auto_out_e_valid(buffer_auto_out_e_valid),
    .auto_out_e_bits_sink(buffer_auto_out_e_bits_sink)
  );
  TLBuffer_10 buffer_1 ( // @[Buffer.scala 68:28]
    .clock(buffer_1_clock),
    .reset(buffer_1_reset),
    .auto_in_a_ready(buffer_1_auto_in_a_ready),
    .auto_in_a_valid(buffer_1_auto_in_a_valid),
    .auto_in_a_bits_opcode(buffer_1_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(buffer_1_auto_in_a_bits_param),
    .auto_in_a_bits_size(buffer_1_auto_in_a_bits_size),
    .auto_in_a_bits_source(buffer_1_auto_in_a_bits_source),
    .auto_in_a_bits_address(buffer_1_auto_in_a_bits_address),
    .auto_in_a_bits_mask(buffer_1_auto_in_a_bits_mask),
    .auto_in_a_bits_data(buffer_1_auto_in_a_bits_data),
    .auto_in_b_ready(buffer_1_auto_in_b_ready),
    .auto_in_b_valid(buffer_1_auto_in_b_valid),
    .auto_in_b_bits_opcode(buffer_1_auto_in_b_bits_opcode),
    .auto_in_b_bits_param(buffer_1_auto_in_b_bits_param),
    .auto_in_b_bits_size(buffer_1_auto_in_b_bits_size),
    .auto_in_b_bits_source(buffer_1_auto_in_b_bits_source),
    .auto_in_b_bits_address(buffer_1_auto_in_b_bits_address),
    .auto_in_b_bits_mask(buffer_1_auto_in_b_bits_mask),
    .auto_in_b_bits_corrupt(buffer_1_auto_in_b_bits_corrupt),
    .auto_in_c_ready(buffer_1_auto_in_c_ready),
    .auto_in_c_valid(buffer_1_auto_in_c_valid),
    .auto_in_c_bits_opcode(buffer_1_auto_in_c_bits_opcode),
    .auto_in_c_bits_param(buffer_1_auto_in_c_bits_param),
    .auto_in_c_bits_size(buffer_1_auto_in_c_bits_size),
    .auto_in_c_bits_source(buffer_1_auto_in_c_bits_source),
    .auto_in_c_bits_address(buffer_1_auto_in_c_bits_address),
    .auto_in_c_bits_data(buffer_1_auto_in_c_bits_data),
    .auto_in_d_ready(buffer_1_auto_in_d_ready),
    .auto_in_d_valid(buffer_1_auto_in_d_valid),
    .auto_in_d_bits_opcode(buffer_1_auto_in_d_bits_opcode),
    .auto_in_d_bits_param(buffer_1_auto_in_d_bits_param),
    .auto_in_d_bits_size(buffer_1_auto_in_d_bits_size),
    .auto_in_d_bits_source(buffer_1_auto_in_d_bits_source),
    .auto_in_d_bits_sink(buffer_1_auto_in_d_bits_sink),
    .auto_in_d_bits_denied(buffer_1_auto_in_d_bits_denied),
    .auto_in_d_bits_data(buffer_1_auto_in_d_bits_data),
    .auto_in_d_bits_corrupt(buffer_1_auto_in_d_bits_corrupt),
    .auto_in_e_ready(buffer_1_auto_in_e_ready),
    .auto_in_e_valid(buffer_1_auto_in_e_valid),
    .auto_in_e_bits_sink(buffer_1_auto_in_e_bits_sink),
    .auto_out_a_ready(buffer_1_auto_out_a_ready),
    .auto_out_a_valid(buffer_1_auto_out_a_valid),
    .auto_out_a_bits_opcode(buffer_1_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(buffer_1_auto_out_a_bits_param),
    .auto_out_a_bits_size(buffer_1_auto_out_a_bits_size),
    .auto_out_a_bits_source(buffer_1_auto_out_a_bits_source),
    .auto_out_a_bits_address(buffer_1_auto_out_a_bits_address),
    .auto_out_a_bits_mask(buffer_1_auto_out_a_bits_mask),
    .auto_out_a_bits_data(buffer_1_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(buffer_1_auto_out_a_bits_corrupt),
    .auto_out_b_ready(buffer_1_auto_out_b_ready),
    .auto_out_b_valid(buffer_1_auto_out_b_valid),
    .auto_out_b_bits_param(buffer_1_auto_out_b_bits_param),
    .auto_out_b_bits_address(buffer_1_auto_out_b_bits_address),
    .auto_out_c_ready(buffer_1_auto_out_c_ready),
    .auto_out_c_valid(buffer_1_auto_out_c_valid),
    .auto_out_c_bits_opcode(buffer_1_auto_out_c_bits_opcode),
    .auto_out_c_bits_param(buffer_1_auto_out_c_bits_param),
    .auto_out_c_bits_size(buffer_1_auto_out_c_bits_size),
    .auto_out_c_bits_source(buffer_1_auto_out_c_bits_source),
    .auto_out_c_bits_address(buffer_1_auto_out_c_bits_address),
    .auto_out_c_bits_data(buffer_1_auto_out_c_bits_data),
    .auto_out_c_bits_corrupt(buffer_1_auto_out_c_bits_corrupt),
    .auto_out_d_ready(buffer_1_auto_out_d_ready),
    .auto_out_d_valid(buffer_1_auto_out_d_valid),
    .auto_out_d_bits_opcode(buffer_1_auto_out_d_bits_opcode),
    .auto_out_d_bits_param(buffer_1_auto_out_d_bits_param),
    .auto_out_d_bits_size(buffer_1_auto_out_d_bits_size),
    .auto_out_d_bits_source(buffer_1_auto_out_d_bits_source),
    .auto_out_d_bits_sink(buffer_1_auto_out_d_bits_sink),
    .auto_out_d_bits_denied(buffer_1_auto_out_d_bits_denied),
    .auto_out_d_bits_data(buffer_1_auto_out_d_bits_data),
    .auto_out_d_bits_corrupt(buffer_1_auto_out_d_bits_corrupt),
    .auto_out_e_valid(buffer_1_auto_out_e_valid),
    .auto_out_e_bits_sink(buffer_1_auto_out_e_bits_sink)
  );
  TLBuffer_11 buffer_2 ( // @[Buffer.scala 68:28]
    .auto_in_a_ready(buffer_2_auto_in_a_ready),
    .auto_in_a_valid(buffer_2_auto_in_a_valid),
    .auto_in_a_bits_opcode(buffer_2_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(buffer_2_auto_in_a_bits_param),
    .auto_in_a_bits_size(buffer_2_auto_in_a_bits_size),
    .auto_in_a_bits_source(buffer_2_auto_in_a_bits_source),
    .auto_in_a_bits_address(buffer_2_auto_in_a_bits_address),
    .auto_in_a_bits_mask(buffer_2_auto_in_a_bits_mask),
    .auto_in_a_bits_data(buffer_2_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(buffer_2_auto_in_a_bits_corrupt),
    .auto_in_d_ready(buffer_2_auto_in_d_ready),
    .auto_in_d_valid(buffer_2_auto_in_d_valid),
    .auto_in_d_bits_opcode(buffer_2_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(buffer_2_auto_in_d_bits_size),
    .auto_in_d_bits_source(buffer_2_auto_in_d_bits_source),
    .auto_in_d_bits_data(buffer_2_auto_in_d_bits_data),
    .auto_out_a_ready(buffer_2_auto_out_a_ready),
    .auto_out_a_valid(buffer_2_auto_out_a_valid),
    .auto_out_a_bits_opcode(buffer_2_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(buffer_2_auto_out_a_bits_param),
    .auto_out_a_bits_size(buffer_2_auto_out_a_bits_size),
    .auto_out_a_bits_source(buffer_2_auto_out_a_bits_source),
    .auto_out_a_bits_address(buffer_2_auto_out_a_bits_address),
    .auto_out_a_bits_mask(buffer_2_auto_out_a_bits_mask),
    .auto_out_a_bits_data(buffer_2_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(buffer_2_auto_out_a_bits_corrupt),
    .auto_out_d_ready(buffer_2_auto_out_d_ready),
    .auto_out_d_valid(buffer_2_auto_out_d_valid),
    .auto_out_d_bits_opcode(buffer_2_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(buffer_2_auto_out_d_bits_size),
    .auto_out_d_bits_source(buffer_2_auto_out_d_bits_source),
    .auto_out_d_bits_data(buffer_2_auto_out_d_bits_data)
  );
  TLBuffer_12 buffer_3 ( // @[Buffer.scala 68:28]
    .clock(buffer_3_clock),
    .reset(buffer_3_reset),
    .auto_in_a_ready(buffer_3_auto_in_a_ready),
    .auto_in_a_valid(buffer_3_auto_in_a_valid),
    .auto_in_a_bits_opcode(buffer_3_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(buffer_3_auto_in_a_bits_param),
    .auto_in_a_bits_size(buffer_3_auto_in_a_bits_size),
    .auto_in_a_bits_source(buffer_3_auto_in_a_bits_source),
    .auto_in_a_bits_address(buffer_3_auto_in_a_bits_address),
    .auto_in_a_bits_mask(buffer_3_auto_in_a_bits_mask),
    .auto_in_a_bits_data(buffer_3_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(buffer_3_auto_in_a_bits_corrupt),
    .auto_in_d_ready(buffer_3_auto_in_d_ready),
    .auto_in_d_valid(buffer_3_auto_in_d_valid),
    .auto_in_d_bits_opcode(buffer_3_auto_in_d_bits_opcode),
    .auto_in_d_bits_param(buffer_3_auto_in_d_bits_param),
    .auto_in_d_bits_size(buffer_3_auto_in_d_bits_size),
    .auto_in_d_bits_source(buffer_3_auto_in_d_bits_source),
    .auto_in_d_bits_sink(buffer_3_auto_in_d_bits_sink),
    .auto_in_d_bits_denied(buffer_3_auto_in_d_bits_denied),
    .auto_in_d_bits_data(buffer_3_auto_in_d_bits_data),
    .auto_in_d_bits_corrupt(buffer_3_auto_in_d_bits_corrupt),
    .auto_out_a_ready(buffer_3_auto_out_a_ready),
    .auto_out_a_valid(buffer_3_auto_out_a_valid),
    .auto_out_a_bits_opcode(buffer_3_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(buffer_3_auto_out_a_bits_param),
    .auto_out_a_bits_size(buffer_3_auto_out_a_bits_size),
    .auto_out_a_bits_source(buffer_3_auto_out_a_bits_source),
    .auto_out_a_bits_address(buffer_3_auto_out_a_bits_address),
    .auto_out_a_bits_mask(buffer_3_auto_out_a_bits_mask),
    .auto_out_a_bits_data(buffer_3_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(buffer_3_auto_out_a_bits_corrupt),
    .auto_out_d_ready(buffer_3_auto_out_d_ready),
    .auto_out_d_valid(buffer_3_auto_out_d_valid),
    .auto_out_d_bits_opcode(buffer_3_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(buffer_3_auto_out_d_bits_size),
    .auto_out_d_bits_source(buffer_3_auto_out_d_bits_source),
    .auto_out_d_bits_data(buffer_3_auto_out_d_bits_data)
  );
  IntSyncAsyncCrossingSink intsink ( // @[Crossing.scala 74:29]
    .clock(intsink_clock),
    .auto_in_sync_0(intsink_auto_in_sync_0),
    .auto_out_0(intsink_auto_out_0)
  );
  IntSyncSyncCrossingSink intsink_1 ( // @[Crossing.scala 94:29]
    .auto_in_sync_0(intsink_1_auto_in_sync_0),
    .auto_in_sync_1(intsink_1_auto_in_sync_1),
    .auto_out_0(intsink_1_auto_out_0),
    .auto_out_1(intsink_1_auto_out_1)
  );
  IntSyncSyncCrossingSink_1 intsink_2 ( // @[Crossing.scala 94:29]
    .auto_in_sync_0(intsink_2_auto_in_sync_0),
    .auto_out_0(intsink_2_auto_out_0)
  );
  IntSyncSyncCrossingSink_1 intsink_3 ( // @[Crossing.scala 94:29]
    .auto_in_sync_0(intsink_3_auto_in_sync_0),
    .auto_out_0(intsink_3_auto_out_0)
  );
  IntSyncCrossingSource_1 intsource_1 ( // @[Crossing.scala 26:31]
    .clock(intsource_1_clock),
    .reset(intsource_1_reset),
    .auto_in_0(intsource_1_auto_in_0),
    .auto_out_sync_0(intsource_1_auto_out_sync_0)
  );
  IntSyncCrossingSource_1 intsource_2 ( // @[Crossing.scala 26:31]
    .clock(intsource_2_clock),
    .reset(intsource_2_reset),
    .auto_in_0(intsource_2_auto_in_0),
    .auto_out_sync_0(intsource_2_auto_out_sync_0)
  );
  IntSyncCrossingSource_1 intsource_3 ( // @[Crossing.scala 26:31]
    .clock(intsource_3_clock),
    .reset(intsource_3_reset),
    .auto_in_0(intsource_3_auto_in_0),
    .auto_out_sync_0(intsource_3_auto_out_sync_0)
  );
  assign auto_int_out_clock_xing_out_2_sync_0 = intsource_3_auto_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_out_clock_xing_out_1_sync_0 = intsource_2_auto_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_out_clock_xing_out_0_sync_0 = intsource_1_auto_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_slave_clock_xing_in_a_ready = buffer_3_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_slave_clock_xing_in_d_valid = buffer_3_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_slave_clock_xing_in_d_bits_opcode = buffer_3_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_slave_clock_xing_in_d_bits_param = buffer_3_auto_in_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_slave_clock_xing_in_d_bits_size = buffer_3_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_slave_clock_xing_in_d_bits_source = buffer_3_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_slave_clock_xing_in_d_bits_sink = buffer_3_auto_in_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_slave_clock_xing_in_d_bits_denied = buffer_3_auto_in_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_slave_clock_xing_in_d_bits_data = buffer_3_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_slave_clock_xing_in_d_bits_corrupt = buffer_3_auto_in_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_tl_master_clock_xing_out_a_valid = buffer_1_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_master_clock_xing_out_a_bits_opcode = buffer_1_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_master_clock_xing_out_a_bits_param = buffer_1_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_master_clock_xing_out_a_bits_size = buffer_1_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_master_clock_xing_out_a_bits_source = buffer_1_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_master_clock_xing_out_a_bits_address = buffer_1_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_master_clock_xing_out_a_bits_mask = buffer_1_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_master_clock_xing_out_a_bits_data = buffer_1_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_master_clock_xing_out_a_bits_corrupt = buffer_1_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_master_clock_xing_out_b_ready = buffer_1_auto_out_b_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_master_clock_xing_out_c_valid = buffer_1_auto_out_c_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_master_clock_xing_out_c_bits_opcode = buffer_1_auto_out_c_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_master_clock_xing_out_c_bits_param = buffer_1_auto_out_c_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_master_clock_xing_out_c_bits_size = buffer_1_auto_out_c_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_master_clock_xing_out_c_bits_source = buffer_1_auto_out_c_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_master_clock_xing_out_c_bits_address = buffer_1_auto_out_c_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_master_clock_xing_out_c_bits_data = buffer_1_auto_out_c_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_master_clock_xing_out_c_bits_corrupt = buffer_1_auto_out_c_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_master_clock_xing_out_d_ready = buffer_1_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_master_clock_xing_out_e_valid = buffer_1_auto_out_e_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_tl_master_clock_xing_out_e_bits_sink = buffer_1_auto_out_e_bits_sink; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign tile_reset_domain_auto_tile_slave_in_a_valid = buffer_2_auto_out_a_valid; // @[LazyModule.scala 296:16]
  assign tile_reset_domain_auto_tile_slave_in_a_bits_opcode = buffer_2_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign tile_reset_domain_auto_tile_slave_in_a_bits_param = buffer_2_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
  assign tile_reset_domain_auto_tile_slave_in_a_bits_size = buffer_2_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign tile_reset_domain_auto_tile_slave_in_a_bits_source = buffer_2_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign tile_reset_domain_auto_tile_slave_in_a_bits_address = buffer_2_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign tile_reset_domain_auto_tile_slave_in_a_bits_mask = buffer_2_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign tile_reset_domain_auto_tile_slave_in_a_bits_data = buffer_2_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign tile_reset_domain_auto_tile_slave_in_a_bits_corrupt = buffer_2_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
  assign tile_reset_domain_auto_tile_slave_in_d_ready = buffer_2_auto_out_d_ready; // @[LazyModule.scala 296:16]
  assign tile_reset_domain_auto_tile_int_local_in_3_0 = intsink_3_auto_out_0; // @[LazyModule.scala 296:16]
  assign tile_reset_domain_auto_tile_int_local_in_2_0 = intsink_2_auto_out_0; // @[LazyModule.scala 296:16]
  assign tile_reset_domain_auto_tile_int_local_in_1_0 = intsink_1_auto_out_0; // @[LazyModule.scala 296:16]
  assign tile_reset_domain_auto_tile_int_local_in_1_1 = intsink_1_auto_out_1; // @[LazyModule.scala 296:16]
  assign tile_reset_domain_auto_tile_int_local_in_0_0 = intsink_auto_out_0; // @[LazyModule.scala 296:16]
  assign tile_reset_domain_auto_tile_hartid_in = auto_tile_reset_domain_tile_hartid_in; // @[LazyModule.scala 309:16]
  assign tile_reset_domain_auto_tile_tl_other_masters_out_a_ready = buffer_auto_in_a_ready; // @[LazyModule.scala 298:16]
  assign tile_reset_domain_auto_tile_tl_other_masters_out_b_valid = buffer_auto_in_b_valid; // @[LazyModule.scala 298:16]
  assign tile_reset_domain_auto_tile_tl_other_masters_out_b_bits_opcode = buffer_auto_in_b_bits_opcode; // @[LazyModule.scala 298:16]
  assign tile_reset_domain_auto_tile_tl_other_masters_out_b_bits_param = buffer_auto_in_b_bits_param; // @[LazyModule.scala 298:16]
  assign tile_reset_domain_auto_tile_tl_other_masters_out_b_bits_size = buffer_auto_in_b_bits_size; // @[LazyModule.scala 298:16]
  assign tile_reset_domain_auto_tile_tl_other_masters_out_b_bits_source = buffer_auto_in_b_bits_source; // @[LazyModule.scala 298:16]
  assign tile_reset_domain_auto_tile_tl_other_masters_out_b_bits_address = buffer_auto_in_b_bits_address; // @[LazyModule.scala 298:16]
  assign tile_reset_domain_auto_tile_tl_other_masters_out_b_bits_mask = buffer_auto_in_b_bits_mask; // @[LazyModule.scala 298:16]
  assign tile_reset_domain_auto_tile_tl_other_masters_out_b_bits_corrupt = buffer_auto_in_b_bits_corrupt; // @[LazyModule.scala 298:16]
  assign tile_reset_domain_auto_tile_tl_other_masters_out_c_ready = buffer_auto_in_c_ready; // @[LazyModule.scala 298:16]
  assign tile_reset_domain_auto_tile_tl_other_masters_out_d_valid = buffer_auto_in_d_valid; // @[LazyModule.scala 298:16]
  assign tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_param = buffer_auto_in_d_bits_param; // @[LazyModule.scala 298:16]
  assign tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_size = buffer_auto_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_source = buffer_auto_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_sink = buffer_auto_in_d_bits_sink; // @[LazyModule.scala 298:16]
  assign tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_denied = buffer_auto_in_d_bits_denied; // @[LazyModule.scala 298:16]
  assign tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_data = buffer_auto_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign tile_reset_domain_auto_tile_tl_other_masters_out_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[LazyModule.scala 298:16]
  assign tile_reset_domain_auto_tile_tl_other_masters_out_e_ready = buffer_auto_in_e_ready; // @[LazyModule.scala 298:16]
  assign tile_reset_domain_auto_clock_in_clock = clockNode_auto_out_clock; // @[LazyModule.scala 296:16]
  assign tile_reset_domain_auto_clock_in_reset = clockNode_auto_out_reset; // @[LazyModule.scala 296:16]
  assign clockNode_auto_in_clock = auto_tap_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign clockNode_auto_in_reset = auto_tap_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_valid = tile_reset_domain_auto_tile_tl_other_masters_out_a_valid; // @[LazyModule.scala 298:16]
  assign buffer_auto_in_a_bits_opcode = tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign buffer_auto_in_a_bits_param = tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign buffer_auto_in_a_bits_size = tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign buffer_auto_in_a_bits_source = tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign buffer_auto_in_a_bits_address = tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign buffer_auto_in_a_bits_mask = tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign buffer_auto_in_a_bits_data = tile_reset_domain_auto_tile_tl_other_masters_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign buffer_auto_in_b_ready = tile_reset_domain_auto_tile_tl_other_masters_out_b_ready; // @[LazyModule.scala 298:16]
  assign buffer_auto_in_c_valid = tile_reset_domain_auto_tile_tl_other_masters_out_c_valid; // @[LazyModule.scala 298:16]
  assign buffer_auto_in_c_bits_opcode = tile_reset_domain_auto_tile_tl_other_masters_out_c_bits_opcode; // @[LazyModule.scala 298:16]
  assign buffer_auto_in_c_bits_param = tile_reset_domain_auto_tile_tl_other_masters_out_c_bits_param; // @[LazyModule.scala 298:16]
  assign buffer_auto_in_c_bits_size = tile_reset_domain_auto_tile_tl_other_masters_out_c_bits_size; // @[LazyModule.scala 298:16]
  assign buffer_auto_in_c_bits_source = tile_reset_domain_auto_tile_tl_other_masters_out_c_bits_source; // @[LazyModule.scala 298:16]
  assign buffer_auto_in_c_bits_address = tile_reset_domain_auto_tile_tl_other_masters_out_c_bits_address; // @[LazyModule.scala 298:16]
  assign buffer_auto_in_c_bits_data = tile_reset_domain_auto_tile_tl_other_masters_out_c_bits_data; // @[LazyModule.scala 298:16]
  assign buffer_auto_in_d_ready = tile_reset_domain_auto_tile_tl_other_masters_out_d_ready; // @[LazyModule.scala 298:16]
  assign buffer_auto_in_e_valid = tile_reset_domain_auto_tile_tl_other_masters_out_e_valid; // @[LazyModule.scala 298:16]
  assign buffer_auto_in_e_bits_sink = tile_reset_domain_auto_tile_tl_other_masters_out_e_bits_sink; // @[LazyModule.scala 298:16]
  assign buffer_auto_out_a_ready = buffer_1_auto_in_a_ready; // @[LazyModule.scala 298:16]
  assign buffer_auto_out_b_valid = buffer_1_auto_in_b_valid; // @[LazyModule.scala 298:16]
  assign buffer_auto_out_b_bits_opcode = buffer_1_auto_in_b_bits_opcode; // @[LazyModule.scala 298:16]
  assign buffer_auto_out_b_bits_param = buffer_1_auto_in_b_bits_param; // @[LazyModule.scala 298:16]
  assign buffer_auto_out_b_bits_size = buffer_1_auto_in_b_bits_size; // @[LazyModule.scala 298:16]
  assign buffer_auto_out_b_bits_source = buffer_1_auto_in_b_bits_source; // @[LazyModule.scala 298:16]
  assign buffer_auto_out_b_bits_address = buffer_1_auto_in_b_bits_address; // @[LazyModule.scala 298:16]
  assign buffer_auto_out_b_bits_mask = buffer_1_auto_in_b_bits_mask; // @[LazyModule.scala 298:16]
  assign buffer_auto_out_b_bits_corrupt = buffer_1_auto_in_b_bits_corrupt; // @[LazyModule.scala 298:16]
  assign buffer_auto_out_c_ready = buffer_1_auto_in_c_ready; // @[LazyModule.scala 298:16]
  assign buffer_auto_out_d_valid = buffer_1_auto_in_d_valid; // @[LazyModule.scala 298:16]
  assign buffer_auto_out_d_bits_opcode = buffer_1_auto_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign buffer_auto_out_d_bits_param = buffer_1_auto_in_d_bits_param; // @[LazyModule.scala 298:16]
  assign buffer_auto_out_d_bits_size = buffer_1_auto_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign buffer_auto_out_d_bits_source = buffer_1_auto_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign buffer_auto_out_d_bits_sink = buffer_1_auto_in_d_bits_sink; // @[LazyModule.scala 298:16]
  assign buffer_auto_out_d_bits_denied = buffer_1_auto_in_d_bits_denied; // @[LazyModule.scala 298:16]
  assign buffer_auto_out_d_bits_data = buffer_1_auto_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign buffer_auto_out_d_bits_corrupt = buffer_1_auto_in_d_bits_corrupt; // @[LazyModule.scala 298:16]
  assign buffer_auto_out_e_ready = buffer_1_auto_in_e_ready; // @[LazyModule.scala 298:16]
  assign buffer_1_clock = auto_tap_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_reset = auto_tap_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_in_a_valid = buffer_auto_out_a_valid; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_a_bits_param = buffer_auto_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_a_bits_size = buffer_auto_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_a_bits_source = buffer_auto_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_a_bits_address = buffer_auto_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_a_bits_data = buffer_auto_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_b_ready = buffer_auto_out_b_ready; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_c_valid = buffer_auto_out_c_valid; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_c_bits_opcode = buffer_auto_out_c_bits_opcode; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_c_bits_param = buffer_auto_out_c_bits_param; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_c_bits_size = buffer_auto_out_c_bits_size; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_c_bits_source = buffer_auto_out_c_bits_source; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_c_bits_address = buffer_auto_out_c_bits_address; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_c_bits_data = buffer_auto_out_c_bits_data; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_d_ready = buffer_auto_out_d_ready; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_e_valid = buffer_auto_out_e_valid; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_in_e_bits_sink = buffer_auto_out_e_bits_sink; // @[LazyModule.scala 298:16]
  assign buffer_1_auto_out_a_ready = auto_tl_master_clock_xing_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign buffer_1_auto_out_b_valid = auto_tl_master_clock_xing_out_b_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign buffer_1_auto_out_b_bits_param = auto_tl_master_clock_xing_out_b_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign buffer_1_auto_out_b_bits_address = auto_tl_master_clock_xing_out_b_bits_address; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign buffer_1_auto_out_c_ready = auto_tl_master_clock_xing_out_c_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign buffer_1_auto_out_d_valid = auto_tl_master_clock_xing_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign buffer_1_auto_out_d_bits_opcode = auto_tl_master_clock_xing_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign buffer_1_auto_out_d_bits_param = auto_tl_master_clock_xing_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign buffer_1_auto_out_d_bits_size = auto_tl_master_clock_xing_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign buffer_1_auto_out_d_bits_source = auto_tl_master_clock_xing_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign buffer_1_auto_out_d_bits_sink = auto_tl_master_clock_xing_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign buffer_1_auto_out_d_bits_denied = auto_tl_master_clock_xing_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign buffer_1_auto_out_d_bits_data = auto_tl_master_clock_xing_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign buffer_1_auto_out_d_bits_corrupt = auto_tl_master_clock_xing_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign buffer_2_auto_in_a_valid = buffer_3_auto_out_a_valid; // @[LazyModule.scala 296:16]
  assign buffer_2_auto_in_a_bits_opcode = buffer_3_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign buffer_2_auto_in_a_bits_param = buffer_3_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
  assign buffer_2_auto_in_a_bits_size = buffer_3_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign buffer_2_auto_in_a_bits_source = buffer_3_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign buffer_2_auto_in_a_bits_address = buffer_3_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign buffer_2_auto_in_a_bits_mask = buffer_3_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign buffer_2_auto_in_a_bits_data = buffer_3_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign buffer_2_auto_in_a_bits_corrupt = buffer_3_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
  assign buffer_2_auto_in_d_ready = buffer_3_auto_out_d_ready; // @[LazyModule.scala 296:16]
  assign buffer_2_auto_out_a_ready = tile_reset_domain_auto_tile_slave_in_a_ready; // @[LazyModule.scala 296:16]
  assign buffer_2_auto_out_d_valid = tile_reset_domain_auto_tile_slave_in_d_valid; // @[LazyModule.scala 296:16]
  assign buffer_2_auto_out_d_bits_opcode = tile_reset_domain_auto_tile_slave_in_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign buffer_2_auto_out_d_bits_size = tile_reset_domain_auto_tile_slave_in_d_bits_size; // @[LazyModule.scala 296:16]
  assign buffer_2_auto_out_d_bits_source = tile_reset_domain_auto_tile_slave_in_d_bits_source; // @[LazyModule.scala 296:16]
  assign buffer_2_auto_out_d_bits_data = tile_reset_domain_auto_tile_slave_in_d_bits_data; // @[LazyModule.scala 296:16]
  assign buffer_3_clock = auto_tap_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_3_reset = auto_tap_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_3_auto_in_a_valid = auto_tl_slave_clock_xing_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_3_auto_in_a_bits_opcode = auto_tl_slave_clock_xing_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_3_auto_in_a_bits_param = auto_tl_slave_clock_xing_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_3_auto_in_a_bits_size = auto_tl_slave_clock_xing_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_3_auto_in_a_bits_source = auto_tl_slave_clock_xing_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_3_auto_in_a_bits_address = auto_tl_slave_clock_xing_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_3_auto_in_a_bits_mask = auto_tl_slave_clock_xing_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_3_auto_in_a_bits_data = auto_tl_slave_clock_xing_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_3_auto_in_a_bits_corrupt = auto_tl_slave_clock_xing_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_3_auto_in_d_ready = auto_tl_slave_clock_xing_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_3_auto_out_a_ready = buffer_2_auto_in_a_ready; // @[LazyModule.scala 296:16]
  assign buffer_3_auto_out_d_valid = buffer_2_auto_in_d_valid; // @[LazyModule.scala 296:16]
  assign buffer_3_auto_out_d_bits_opcode = buffer_2_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign buffer_3_auto_out_d_bits_size = buffer_2_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
  assign buffer_3_auto_out_d_bits_source = buffer_2_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
  assign buffer_3_auto_out_d_bits_data = buffer_2_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
  assign intsink_clock = auto_tap_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign intsink_auto_in_sync_0 = auto_intsink_in_sync_0; // @[LazyModule.scala 309:16]
  assign intsink_1_auto_in_sync_0 = auto_int_in_clock_xing_in_0_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign intsink_1_auto_in_sync_1 = auto_int_in_clock_xing_in_0_sync_1; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign intsink_2_auto_in_sync_0 = auto_int_in_clock_xing_in_1_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign intsink_3_auto_in_sync_0 = auto_int_in_clock_xing_in_2_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign intsource_1_clock = auto_tap_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign intsource_1_reset = auto_tap_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign intsource_1_auto_in_0 = 1'h0; // @[LazyModule.scala 298:16]
  assign intsource_2_clock = auto_tap_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign intsource_2_reset = auto_tap_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign intsource_2_auto_in_0 = tile_reset_domain_auto_tile_wfi_out_0; // @[LazyModule.scala 298:16]
  assign intsource_3_clock = auto_tap_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign intsource_3_reset = auto_tap_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign intsource_3_auto_in_0 = 1'h0; // @[LazyModule.scala 298:16]
endmodule
module TLMonitor_46(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [1:0]  io_in_a_bits_size,
  input  [6:0]  io_in_a_bits_source,
  input  [27:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_size,
  input  [6:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [95:0] _RAND_10;
  reg [383:0] _RAND_11;
  reg [383:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [95:0] _RAND_16;
  reg [383:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T_4 = io_in_a_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire [4:0] _is_aligned_mask_T_1 = 5'h3 << io_in_a_bits_size; // @[package.scala 234:77]
  wire [1:0] is_aligned_mask = ~_is_aligned_mask_T_1[1:0]; // @[package.scala 234:46]
  wire [27:0] _GEN_71 = {{26'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [27:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 2'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [27:0] _T_33 = io_in_a_bits_address ^ 28'hc000000; // @[Parameters.scala 137:31]
  wire [28:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
  wire [28:0] _T_36 = $signed(_T_34) & -29'sh4000000; // @[Parameters.scala 137:52]
  wire  _T_37 = $signed(_T_36) == 29'sh0; // @[Parameters.scala 137:67]
  wire  _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_74 = _T_73 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_164 = io_in_a_bits_size <= 2'h2; // @[Parameters.scala 92:42]
  wire  _T_172 = _T_164 & _T_37; // @[Parameters.scala 670:56]
  wire  _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_218 = _source_ok_T_4 & _T_172; // @[Monitor.scala 115:71]
  wire  _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_273 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_274 = io_in_a_bits_mask & _T_273; // @[Monitor.scala 127:31]
  wire  _T_275 = _T_274 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_279 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_347 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_355 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_385 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_397 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_10 = io_in_d_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire  _T_401 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_405 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 312:27]
  wire  _T_421 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_449 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_478 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_495 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_513 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [1:0] size; // @[Monitor.scala 386:22]
  reg [6:0] source; // @[Monitor.scala 387:22]
  reg [27:0] address; // @[Monitor.scala 388:22]
  wire  _T_543 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_544 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_548 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_552 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_556 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_560 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] size_1; // @[Monitor.scala 537:22]
  reg [6:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_567 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_568 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_576 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_580 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [95:0] inflight; // @[Monitor.scala 611:27]
  reg [383:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [383:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [8:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [9:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [383:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [383:0] _GEN_73 = {{368'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[383:1]}; // @[Monitor.scala 634:152]
  wire [383:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [383:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
  wire [383:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[383:1]}; // @[Monitor.scala 638:144]
  wire  _T_594 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [127:0] _a_set_wo_ready_T = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [127:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_597 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
  wire [8:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [9:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [1026:0] _GEN_1 = {{1023'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [1026:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
  wire [1025:0] _GEN_2 = {{1023'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [1025:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [95:0] _T_599 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_601 = ~_T_599[0]; // @[Monitor.scala 658:17]
  wire [127:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 652:72 653:28]
  wire [1026:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 1027'h0; // @[Monitor.scala 652:72 656:28]
  wire [1025:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 1026'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_605 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_607 = ~_T_401; // @[Monitor.scala 671:74]
  wire  _T_608 = io_in_d_valid & d_first_1 & ~_T_401; // @[Monitor.scala 671:71]
  wire [127:0] _d_clr_wo_ready_T = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [127:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 671:90 672:22]
  wire [1038:0] _GEN_3 = {{1023'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [1038:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [127:0] _GEN_22 = d_first_done & d_first_1 & _T_607 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 675:91 676:21]
  wire [1038:0] _GEN_23 = d_first_done & d_first_1 & _T_607 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_594 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [95:0] _T_618 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_620 = _T_618[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_625 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_626 = io_in_d_bits_opcode == _GEN_32 | _T_625; // @[Monitor.scala 685:77]
  wire  _T_630 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_637 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_638 = io_in_d_bits_opcode == _GEN_48 | _T_637; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_642 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_652 = _T_605 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_607; // @[Monitor.scala 694:116]
  wire  _T_654 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [95:0] a_set_wo_ready = _GEN_15[95:0];
  wire [95:0] d_clr_wo_ready = _GEN_21[95:0];
  wire  _T_661 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire [95:0] a_set = _GEN_16[95:0];
  wire [95:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [95:0] d_clr = _GEN_22[95:0];
  wire [95:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [95:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [383:0] a_opcodes_set = _GEN_19[383:0];
  wire [383:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [383:0] d_opcodes_clr = _GEN_23[383:0];
  wire [383:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [383:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [383:0] a_sizes_set = _GEN_20[383:0];
  wire [383:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [383:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_670 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [95:0] inflight_1; // @[Monitor.scala 723:35]
  reg [383:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [383:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [383:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
  wire [383:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[383:1]}; // @[Monitor.scala 747:146]
  wire  _T_696 = io_in_d_valid & d_first_2 & _T_401; // @[Monitor.scala 779:71]
  wire [127:0] _GEN_67 = d_first_done & d_first_2 & _T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 783:90 784:21]
  wire [1038:0] _GEN_68 = d_first_done & d_first_2 & _T_401 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 783:90 785:21]
  wire [95:0] _T_704 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_714 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [95:0] d_clr_1 = _GEN_67[95:0];
  wire [95:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [95:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [383:0] d_opcodes_clr_1 = _GEN_68[383:0];
  wire [383:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [383:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_739 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 1'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= 1'h0;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 96'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 384'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 384'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 1'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= 1'h0;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 96'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 384'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= 1'h0;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (d_first_done) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_172 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_172) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_275 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_275) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_309 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_309) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_347 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_347) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_385 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_397 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_397) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at Plic.scala:363:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Plic.scala:363:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Plic.scala:363:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at Plic.scala:363:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Plic.scala:363:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at Plic.scala:363:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Plic.scala:363:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Plic.scala:363:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Plic.scala:363:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_478 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_478 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Plic.scala:363:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_495 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_495 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Plic.scala:363:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_513 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_513 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Plic.scala:363:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_544 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_544) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_548 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_548) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_552 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_552) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_556 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_556) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_560 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_560) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_568 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_568) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Plic.scala:363:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_576 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_576) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at Plic.scala:363:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_580 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_580) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at Plic.scala:363:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_601 & (_T_597 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_597 & ~reset & ~_T_601) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_620 & (_T_608 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & _T_2 & ~_T_620) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Plic.scala:363:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_626 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_626) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Plic.scala:363:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_630 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_630) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Plic.scala:363:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_638 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_638) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Plic.scala:363:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_642 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_642) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Plic.scala:363:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_654 & (_T_652 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_652 & _T_2 & ~_T_654) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_661 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_661) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at Plic.scala:363:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_670 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_670) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_704[0] & (_T_696 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_696 & _T_2 & ~_T_704[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Plic.scala:363:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_714 & (_T_696 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_696 & _T_2 & ~_T_714) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Plic.scala:363:15)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_739 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_739) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Plic.scala:363:15)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[6:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[27:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[6:0];
  _RAND_10 = {3{`RANDOM}};
  inflight = _RAND_10[95:0];
  _RAND_11 = {12{`RANDOM}};
  inflight_opcodes = _RAND_11[383:0];
  _RAND_12 = {12{`RANDOM}};
  inflight_sizes = _RAND_12[383:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {3{`RANDOM}};
  inflight_1 = _RAND_16[95:0];
  _RAND_17 = {12{`RANDOM}};
  inflight_sizes_1 = _RAND_17[383:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module LevelGateway(
  input   clock,
  input   reset,
  input   io_interrupt,
  output  io_plic_valid,
  input   io_plic_ready,
  input   io_plic_complete
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg  inFlight; // @[Plic.scala 34:21]
  wire  _GEN_0 = io_interrupt & io_plic_ready | inFlight; // @[Plic.scala 34:21 35:{40,51}]
  assign io_plic_valid = io_interrupt & ~inFlight; // @[Plic.scala 37:33]
  always @(posedge clock) begin
    if (reset) begin // @[Plic.scala 34:21]
      inFlight <= 1'h0; // @[Plic.scala 34:21]
    end else if (io_plic_complete) begin // @[Plic.scala 36:27]
      inFlight <= 1'h0; // @[Plic.scala 36:38]
    end else begin
      inFlight <= _GEN_0;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  inFlight = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module PLICFanIn(
  input  [2:0]  io_prio_0,
  input  [2:0]  io_prio_1,
  input  [2:0]  io_prio_2,
  input  [2:0]  io_prio_3,
  input  [2:0]  io_prio_4,
  input  [2:0]  io_prio_5,
  input  [2:0]  io_prio_6,
  input  [2:0]  io_prio_7,
  input  [2:0]  io_prio_8,
  input  [2:0]  io_prio_9,
  input  [2:0]  io_prio_10,
  input  [2:0]  io_prio_11,
  input  [2:0]  io_prio_12,
  input  [2:0]  io_prio_13,
  input  [2:0]  io_prio_14,
  input  [2:0]  io_prio_15,
  input  [2:0]  io_prio_16,
  input  [2:0]  io_prio_17,
  input  [2:0]  io_prio_18,
  input  [2:0]  io_prio_19,
  input  [2:0]  io_prio_20,
  input  [2:0]  io_prio_21,
  input  [2:0]  io_prio_22,
  input  [2:0]  io_prio_23,
  input  [2:0]  io_prio_24,
  input  [2:0]  io_prio_25,
  input  [2:0]  io_prio_26,
  input  [2:0]  io_prio_27,
  input  [2:0]  io_prio_28,
  input  [2:0]  io_prio_29,
  input  [2:0]  io_prio_30,
  input  [2:0]  io_prio_31,
  input  [2:0]  io_prio_32,
  input  [2:0]  io_prio_33,
  input  [2:0]  io_prio_34,
  input  [2:0]  io_prio_35,
  input  [2:0]  io_prio_36,
  input  [2:0]  io_prio_37,
  input  [2:0]  io_prio_38,
  input  [2:0]  io_prio_39,
  input  [2:0]  io_prio_40,
  input  [2:0]  io_prio_41,
  input  [2:0]  io_prio_42,
  input  [2:0]  io_prio_43,
  input  [2:0]  io_prio_44,
  input  [2:0]  io_prio_45,
  input  [2:0]  io_prio_46,
  input  [2:0]  io_prio_47,
  input  [2:0]  io_prio_48,
  input  [2:0]  io_prio_49,
  input  [2:0]  io_prio_50,
  input  [2:0]  io_prio_51,
  input  [2:0]  io_prio_52,
  input  [2:0]  io_prio_53,
  input  [2:0]  io_prio_54,
  input  [2:0]  io_prio_55,
  input  [55:0] io_ip,
  output [5:0]  io_dev,
  output [2:0]  io_max
);
  wire [3:0] effectivePriority_1 = {io_ip[0],io_prio_0}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_2 = {io_ip[1],io_prio_1}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_3 = {io_ip[2],io_prio_2}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_4 = {io_ip[3],io_prio_3}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_5 = {io_ip[4],io_prio_4}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_6 = {io_ip[5],io_prio_5}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_7 = {io_ip[6],io_prio_6}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_8 = {io_ip[7],io_prio_7}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_9 = {io_ip[8],io_prio_8}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_10 = {io_ip[9],io_prio_9}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_11 = {io_ip[10],io_prio_10}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_12 = {io_ip[11],io_prio_11}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_13 = {io_ip[12],io_prio_12}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_14 = {io_ip[13],io_prio_13}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_15 = {io_ip[14],io_prio_14}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_16 = {io_ip[15],io_prio_15}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_17 = {io_ip[16],io_prio_16}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_18 = {io_ip[17],io_prio_17}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_19 = {io_ip[18],io_prio_18}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_20 = {io_ip[19],io_prio_19}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_21 = {io_ip[20],io_prio_20}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_22 = {io_ip[21],io_prio_21}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_23 = {io_ip[22],io_prio_22}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_24 = {io_ip[23],io_prio_23}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_25 = {io_ip[24],io_prio_24}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_26 = {io_ip[25],io_prio_25}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_27 = {io_ip[26],io_prio_26}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_28 = {io_ip[27],io_prio_27}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_29 = {io_ip[28],io_prio_28}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_30 = {io_ip[29],io_prio_29}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_31 = {io_ip[30],io_prio_30}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_32 = {io_ip[31],io_prio_31}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_33 = {io_ip[32],io_prio_32}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_34 = {io_ip[33],io_prio_33}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_35 = {io_ip[34],io_prio_34}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_36 = {io_ip[35],io_prio_35}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_37 = {io_ip[36],io_prio_36}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_38 = {io_ip[37],io_prio_37}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_39 = {io_ip[38],io_prio_38}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_40 = {io_ip[39],io_prio_39}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_41 = {io_ip[40],io_prio_40}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_42 = {io_ip[41],io_prio_41}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_43 = {io_ip[42],io_prio_42}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_44 = {io_ip[43],io_prio_43}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_45 = {io_ip[44],io_prio_44}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_46 = {io_ip[45],io_prio_45}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_47 = {io_ip[46],io_prio_46}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_48 = {io_ip[47],io_prio_47}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_49 = {io_ip[48],io_prio_48}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_50 = {io_ip[49],io_prio_49}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_51 = {io_ip[50],io_prio_50}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_52 = {io_ip[51],io_prio_51}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_53 = {io_ip[52],io_prio_52}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_54 = {io_ip[53],io_prio_53}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_55 = {io_ip[54],io_prio_54}; // @[Cat.scala 31:58]
  wire [3:0] effectivePriority_56 = {io_ip[55],io_prio_55}; // @[Cat.scala 31:58]
  wire  _T = 4'h8 >= effectivePriority_1; // @[Plic.scala 345:20]
  wire [3:0] _T_2 = _T ? 4'h8 : effectivePriority_1; // @[Misc.scala 34:9]
  wire  _T_3 = _T ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
  wire  _T_4 = effectivePriority_2 >= effectivePriority_3; // @[Plic.scala 345:20]
  wire [3:0] _T_6 = _T_4 ? effectivePriority_2 : effectivePriority_3; // @[Misc.scala 34:9]
  wire  _T_7 = _T_4 ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
  wire  _T_8 = _T_2 >= _T_6; // @[Plic.scala 345:20]
  wire [1:0] _GEN_0 = {{1'd0}, _T_7}; // @[Plic.scala 345:61]
  wire [1:0] _T_9 = 2'h2 | _GEN_0; // @[Plic.scala 345:61]
  wire [3:0] _T_10 = _T_8 ? _T_2 : _T_6; // @[Misc.scala 34:9]
  wire [1:0] _T_11 = _T_8 ? {{1'd0}, _T_3} : _T_9; // @[Misc.scala 34:36]
  wire  _T_12 = effectivePriority_4 >= effectivePriority_5; // @[Plic.scala 345:20]
  wire [3:0] _T_14 = _T_12 ? effectivePriority_4 : effectivePriority_5; // @[Misc.scala 34:9]
  wire  _T_15 = _T_12 ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
  wire  _T_16 = effectivePriority_6 >= effectivePriority_7; // @[Plic.scala 345:20]
  wire [3:0] _T_18 = _T_16 ? effectivePriority_6 : effectivePriority_7; // @[Misc.scala 34:9]
  wire  _T_19 = _T_16 ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
  wire  _T_20 = _T_14 >= _T_18; // @[Plic.scala 345:20]
  wire [1:0] _GEN_1 = {{1'd0}, _T_19}; // @[Plic.scala 345:61]
  wire [1:0] _T_21 = 2'h2 | _GEN_1; // @[Plic.scala 345:61]
  wire [3:0] _T_22 = _T_20 ? _T_14 : _T_18; // @[Misc.scala 34:9]
  wire [1:0] _T_23 = _T_20 ? {{1'd0}, _T_15} : _T_21; // @[Misc.scala 34:36]
  wire  _T_24 = _T_10 >= _T_22; // @[Plic.scala 345:20]
  wire [2:0] _GEN_2 = {{1'd0}, _T_23}; // @[Plic.scala 345:61]
  wire [2:0] _T_25 = 3'h4 | _GEN_2; // @[Plic.scala 345:61]
  wire [3:0] _T_26 = _T_24 ? _T_10 : _T_22; // @[Misc.scala 34:9]
  wire [2:0] _T_27 = _T_24 ? {{1'd0}, _T_11} : _T_25; // @[Misc.scala 34:36]
  wire  _T_28 = effectivePriority_8 >= effectivePriority_9; // @[Plic.scala 345:20]
  wire [3:0] _T_30 = _T_28 ? effectivePriority_8 : effectivePriority_9; // @[Misc.scala 34:9]
  wire  _T_31 = _T_28 ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
  wire  _T_32 = effectivePriority_10 >= effectivePriority_11; // @[Plic.scala 345:20]
  wire [3:0] _T_34 = _T_32 ? effectivePriority_10 : effectivePriority_11; // @[Misc.scala 34:9]
  wire  _T_35 = _T_32 ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
  wire  _T_36 = _T_30 >= _T_34; // @[Plic.scala 345:20]
  wire [1:0] _GEN_3 = {{1'd0}, _T_35}; // @[Plic.scala 345:61]
  wire [1:0] _T_37 = 2'h2 | _GEN_3; // @[Plic.scala 345:61]
  wire [3:0] _T_38 = _T_36 ? _T_30 : _T_34; // @[Misc.scala 34:9]
  wire [1:0] _T_39 = _T_36 ? {{1'd0}, _T_31} : _T_37; // @[Misc.scala 34:36]
  wire  _T_40 = effectivePriority_12 >= effectivePriority_13; // @[Plic.scala 345:20]
  wire [3:0] _T_42 = _T_40 ? effectivePriority_12 : effectivePriority_13; // @[Misc.scala 34:9]
  wire  _T_43 = _T_40 ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
  wire  _T_44 = effectivePriority_14 >= effectivePriority_15; // @[Plic.scala 345:20]
  wire [3:0] _T_46 = _T_44 ? effectivePriority_14 : effectivePriority_15; // @[Misc.scala 34:9]
  wire  _T_47 = _T_44 ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
  wire  _T_48 = _T_42 >= _T_46; // @[Plic.scala 345:20]
  wire [1:0] _GEN_4 = {{1'd0}, _T_47}; // @[Plic.scala 345:61]
  wire [1:0] _T_49 = 2'h2 | _GEN_4; // @[Plic.scala 345:61]
  wire [3:0] _T_50 = _T_48 ? _T_42 : _T_46; // @[Misc.scala 34:9]
  wire [1:0] _T_51 = _T_48 ? {{1'd0}, _T_43} : _T_49; // @[Misc.scala 34:36]
  wire  _T_52 = _T_38 >= _T_50; // @[Plic.scala 345:20]
  wire [2:0] _GEN_5 = {{1'd0}, _T_51}; // @[Plic.scala 345:61]
  wire [2:0] _T_53 = 3'h4 | _GEN_5; // @[Plic.scala 345:61]
  wire [3:0] _T_54 = _T_52 ? _T_38 : _T_50; // @[Misc.scala 34:9]
  wire [2:0] _T_55 = _T_52 ? {{1'd0}, _T_39} : _T_53; // @[Misc.scala 34:36]
  wire  _T_56 = _T_26 >= _T_54; // @[Plic.scala 345:20]
  wire [3:0] _GEN_6 = {{1'd0}, _T_55}; // @[Plic.scala 345:61]
  wire [3:0] _T_57 = 4'h8 | _GEN_6; // @[Plic.scala 345:61]
  wire [3:0] _T_58 = _T_56 ? _T_26 : _T_54; // @[Misc.scala 34:9]
  wire [3:0] _T_59 = _T_56 ? {{1'd0}, _T_27} : _T_57; // @[Misc.scala 34:36]
  wire  _T_60 = effectivePriority_16 >= effectivePriority_17; // @[Plic.scala 345:20]
  wire [3:0] _T_62 = _T_60 ? effectivePriority_16 : effectivePriority_17; // @[Misc.scala 34:9]
  wire  _T_63 = _T_60 ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
  wire  _T_64 = effectivePriority_18 >= effectivePriority_19; // @[Plic.scala 345:20]
  wire [3:0] _T_66 = _T_64 ? effectivePriority_18 : effectivePriority_19; // @[Misc.scala 34:9]
  wire  _T_67 = _T_64 ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
  wire  _T_68 = _T_62 >= _T_66; // @[Plic.scala 345:20]
  wire [1:0] _GEN_7 = {{1'd0}, _T_67}; // @[Plic.scala 345:61]
  wire [1:0] _T_69 = 2'h2 | _GEN_7; // @[Plic.scala 345:61]
  wire [3:0] _T_70 = _T_68 ? _T_62 : _T_66; // @[Misc.scala 34:9]
  wire [1:0] _T_71 = _T_68 ? {{1'd0}, _T_63} : _T_69; // @[Misc.scala 34:36]
  wire  _T_72 = effectivePriority_20 >= effectivePriority_21; // @[Plic.scala 345:20]
  wire [3:0] _T_74 = _T_72 ? effectivePriority_20 : effectivePriority_21; // @[Misc.scala 34:9]
  wire  _T_75 = _T_72 ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
  wire  _T_76 = effectivePriority_22 >= effectivePriority_23; // @[Plic.scala 345:20]
  wire [3:0] _T_78 = _T_76 ? effectivePriority_22 : effectivePriority_23; // @[Misc.scala 34:9]
  wire  _T_79 = _T_76 ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
  wire  _T_80 = _T_74 >= _T_78; // @[Plic.scala 345:20]
  wire [1:0] _GEN_8 = {{1'd0}, _T_79}; // @[Plic.scala 345:61]
  wire [1:0] _T_81 = 2'h2 | _GEN_8; // @[Plic.scala 345:61]
  wire [3:0] _T_82 = _T_80 ? _T_74 : _T_78; // @[Misc.scala 34:9]
  wire [1:0] _T_83 = _T_80 ? {{1'd0}, _T_75} : _T_81; // @[Misc.scala 34:36]
  wire  _T_84 = _T_70 >= _T_82; // @[Plic.scala 345:20]
  wire [2:0] _GEN_9 = {{1'd0}, _T_83}; // @[Plic.scala 345:61]
  wire [2:0] _T_85 = 3'h4 | _GEN_9; // @[Plic.scala 345:61]
  wire [3:0] _T_86 = _T_84 ? _T_70 : _T_82; // @[Misc.scala 34:9]
  wire [2:0] _T_87 = _T_84 ? {{1'd0}, _T_71} : _T_85; // @[Misc.scala 34:36]
  wire  _T_88 = effectivePriority_24 >= effectivePriority_25; // @[Plic.scala 345:20]
  wire [3:0] _T_90 = _T_88 ? effectivePriority_24 : effectivePriority_25; // @[Misc.scala 34:9]
  wire  _T_91 = _T_88 ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
  wire  _T_92 = effectivePriority_26 >= effectivePriority_27; // @[Plic.scala 345:20]
  wire [3:0] _T_94 = _T_92 ? effectivePriority_26 : effectivePriority_27; // @[Misc.scala 34:9]
  wire  _T_95 = _T_92 ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
  wire  _T_96 = _T_90 >= _T_94; // @[Plic.scala 345:20]
  wire [1:0] _GEN_10 = {{1'd0}, _T_95}; // @[Plic.scala 345:61]
  wire [1:0] _T_97 = 2'h2 | _GEN_10; // @[Plic.scala 345:61]
  wire [3:0] _T_98 = _T_96 ? _T_90 : _T_94; // @[Misc.scala 34:9]
  wire [1:0] _T_99 = _T_96 ? {{1'd0}, _T_91} : _T_97; // @[Misc.scala 34:36]
  wire  _T_100 = effectivePriority_28 >= effectivePriority_29; // @[Plic.scala 345:20]
  wire [3:0] _T_102 = _T_100 ? effectivePriority_28 : effectivePriority_29; // @[Misc.scala 34:9]
  wire  _T_103 = _T_100 ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
  wire  _T_104 = effectivePriority_30 >= effectivePriority_31; // @[Plic.scala 345:20]
  wire [3:0] _T_106 = _T_104 ? effectivePriority_30 : effectivePriority_31; // @[Misc.scala 34:9]
  wire  _T_107 = _T_104 ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
  wire  _T_108 = _T_102 >= _T_106; // @[Plic.scala 345:20]
  wire [1:0] _GEN_11 = {{1'd0}, _T_107}; // @[Plic.scala 345:61]
  wire [1:0] _T_109 = 2'h2 | _GEN_11; // @[Plic.scala 345:61]
  wire [3:0] _T_110 = _T_108 ? _T_102 : _T_106; // @[Misc.scala 34:9]
  wire [1:0] _T_111 = _T_108 ? {{1'd0}, _T_103} : _T_109; // @[Misc.scala 34:36]
  wire  _T_112 = _T_98 >= _T_110; // @[Plic.scala 345:20]
  wire [2:0] _GEN_12 = {{1'd0}, _T_111}; // @[Plic.scala 345:61]
  wire [2:0] _T_113 = 3'h4 | _GEN_12; // @[Plic.scala 345:61]
  wire [3:0] _T_114 = _T_112 ? _T_98 : _T_110; // @[Misc.scala 34:9]
  wire [2:0] _T_115 = _T_112 ? {{1'd0}, _T_99} : _T_113; // @[Misc.scala 34:36]
  wire  _T_116 = _T_86 >= _T_114; // @[Plic.scala 345:20]
  wire [3:0] _GEN_13 = {{1'd0}, _T_115}; // @[Plic.scala 345:61]
  wire [3:0] _T_117 = 4'h8 | _GEN_13; // @[Plic.scala 345:61]
  wire [3:0] _T_118 = _T_116 ? _T_86 : _T_114; // @[Misc.scala 34:9]
  wire [3:0] _T_119 = _T_116 ? {{1'd0}, _T_87} : _T_117; // @[Misc.scala 34:36]
  wire  _T_120 = _T_58 >= _T_118; // @[Plic.scala 345:20]
  wire [4:0] _GEN_14 = {{1'd0}, _T_119}; // @[Plic.scala 345:61]
  wire [4:0] _T_121 = 5'h10 | _GEN_14; // @[Plic.scala 345:61]
  wire [3:0] _T_122 = _T_120 ? _T_58 : _T_118; // @[Misc.scala 34:9]
  wire [4:0] _T_123 = _T_120 ? {{1'd0}, _T_59} : _T_121; // @[Misc.scala 34:36]
  wire  _T_124 = effectivePriority_32 >= effectivePriority_33; // @[Plic.scala 345:20]
  wire [3:0] _T_126 = _T_124 ? effectivePriority_32 : effectivePriority_33; // @[Misc.scala 34:9]
  wire  _T_127 = _T_124 ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
  wire  _T_128 = effectivePriority_34 >= effectivePriority_35; // @[Plic.scala 345:20]
  wire [3:0] _T_130 = _T_128 ? effectivePriority_34 : effectivePriority_35; // @[Misc.scala 34:9]
  wire  _T_131 = _T_128 ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
  wire  _T_132 = _T_126 >= _T_130; // @[Plic.scala 345:20]
  wire [1:0] _GEN_15 = {{1'd0}, _T_131}; // @[Plic.scala 345:61]
  wire [1:0] _T_133 = 2'h2 | _GEN_15; // @[Plic.scala 345:61]
  wire [3:0] _T_134 = _T_132 ? _T_126 : _T_130; // @[Misc.scala 34:9]
  wire [1:0] _T_135 = _T_132 ? {{1'd0}, _T_127} : _T_133; // @[Misc.scala 34:36]
  wire  _T_136 = effectivePriority_36 >= effectivePriority_37; // @[Plic.scala 345:20]
  wire [3:0] _T_138 = _T_136 ? effectivePriority_36 : effectivePriority_37; // @[Misc.scala 34:9]
  wire  _T_139 = _T_136 ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
  wire  _T_140 = effectivePriority_38 >= effectivePriority_39; // @[Plic.scala 345:20]
  wire [3:0] _T_142 = _T_140 ? effectivePriority_38 : effectivePriority_39; // @[Misc.scala 34:9]
  wire  _T_143 = _T_140 ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
  wire  _T_144 = _T_138 >= _T_142; // @[Plic.scala 345:20]
  wire [1:0] _GEN_16 = {{1'd0}, _T_143}; // @[Plic.scala 345:61]
  wire [1:0] _T_145 = 2'h2 | _GEN_16; // @[Plic.scala 345:61]
  wire [3:0] _T_146 = _T_144 ? _T_138 : _T_142; // @[Misc.scala 34:9]
  wire [1:0] _T_147 = _T_144 ? {{1'd0}, _T_139} : _T_145; // @[Misc.scala 34:36]
  wire  _T_148 = _T_134 >= _T_146; // @[Plic.scala 345:20]
  wire [2:0] _GEN_17 = {{1'd0}, _T_147}; // @[Plic.scala 345:61]
  wire [2:0] _T_149 = 3'h4 | _GEN_17; // @[Plic.scala 345:61]
  wire [3:0] _T_150 = _T_148 ? _T_134 : _T_146; // @[Misc.scala 34:9]
  wire [2:0] _T_151 = _T_148 ? {{1'd0}, _T_135} : _T_149; // @[Misc.scala 34:36]
  wire  _T_152 = effectivePriority_40 >= effectivePriority_41; // @[Plic.scala 345:20]
  wire [3:0] _T_154 = _T_152 ? effectivePriority_40 : effectivePriority_41; // @[Misc.scala 34:9]
  wire  _T_155 = _T_152 ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
  wire  _T_156 = effectivePriority_42 >= effectivePriority_43; // @[Plic.scala 345:20]
  wire [3:0] _T_158 = _T_156 ? effectivePriority_42 : effectivePriority_43; // @[Misc.scala 34:9]
  wire  _T_159 = _T_156 ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
  wire  _T_160 = _T_154 >= _T_158; // @[Plic.scala 345:20]
  wire [1:0] _GEN_18 = {{1'd0}, _T_159}; // @[Plic.scala 345:61]
  wire [1:0] _T_161 = 2'h2 | _GEN_18; // @[Plic.scala 345:61]
  wire [3:0] _T_162 = _T_160 ? _T_154 : _T_158; // @[Misc.scala 34:9]
  wire [1:0] _T_163 = _T_160 ? {{1'd0}, _T_155} : _T_161; // @[Misc.scala 34:36]
  wire  _T_164 = effectivePriority_44 >= effectivePriority_45; // @[Plic.scala 345:20]
  wire [3:0] _T_166 = _T_164 ? effectivePriority_44 : effectivePriority_45; // @[Misc.scala 34:9]
  wire  _T_167 = _T_164 ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
  wire  _T_168 = effectivePriority_46 >= effectivePriority_47; // @[Plic.scala 345:20]
  wire [3:0] _T_170 = _T_168 ? effectivePriority_46 : effectivePriority_47; // @[Misc.scala 34:9]
  wire  _T_171 = _T_168 ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
  wire  _T_172 = _T_166 >= _T_170; // @[Plic.scala 345:20]
  wire [1:0] _GEN_19 = {{1'd0}, _T_171}; // @[Plic.scala 345:61]
  wire [1:0] _T_173 = 2'h2 | _GEN_19; // @[Plic.scala 345:61]
  wire [3:0] _T_174 = _T_172 ? _T_166 : _T_170; // @[Misc.scala 34:9]
  wire [1:0] _T_175 = _T_172 ? {{1'd0}, _T_167} : _T_173; // @[Misc.scala 34:36]
  wire  _T_176 = _T_162 >= _T_174; // @[Plic.scala 345:20]
  wire [2:0] _GEN_20 = {{1'd0}, _T_175}; // @[Plic.scala 345:61]
  wire [2:0] _T_177 = 3'h4 | _GEN_20; // @[Plic.scala 345:61]
  wire [3:0] _T_178 = _T_176 ? _T_162 : _T_174; // @[Misc.scala 34:9]
  wire [2:0] _T_179 = _T_176 ? {{1'd0}, _T_163} : _T_177; // @[Misc.scala 34:36]
  wire  _T_180 = _T_150 >= _T_178; // @[Plic.scala 345:20]
  wire [3:0] _GEN_21 = {{1'd0}, _T_179}; // @[Plic.scala 345:61]
  wire [3:0] _T_181 = 4'h8 | _GEN_21; // @[Plic.scala 345:61]
  wire [3:0] _T_182 = _T_180 ? _T_150 : _T_178; // @[Misc.scala 34:9]
  wire [3:0] _T_183 = _T_180 ? {{1'd0}, _T_151} : _T_181; // @[Misc.scala 34:36]
  wire  _T_184 = effectivePriority_48 >= effectivePriority_49; // @[Plic.scala 345:20]
  wire [3:0] _T_186 = _T_184 ? effectivePriority_48 : effectivePriority_49; // @[Misc.scala 34:9]
  wire  _T_187 = _T_184 ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
  wire  _T_188 = effectivePriority_50 >= effectivePriority_51; // @[Plic.scala 345:20]
  wire [3:0] _T_190 = _T_188 ? effectivePriority_50 : effectivePriority_51; // @[Misc.scala 34:9]
  wire  _T_191 = _T_188 ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
  wire  _T_192 = _T_186 >= _T_190; // @[Plic.scala 345:20]
  wire [1:0] _GEN_22 = {{1'd0}, _T_191}; // @[Plic.scala 345:61]
  wire [1:0] _T_193 = 2'h2 | _GEN_22; // @[Plic.scala 345:61]
  wire [3:0] _T_194 = _T_192 ? _T_186 : _T_190; // @[Misc.scala 34:9]
  wire [1:0] _T_195 = _T_192 ? {{1'd0}, _T_187} : _T_193; // @[Misc.scala 34:36]
  wire  _T_196 = effectivePriority_52 >= effectivePriority_53; // @[Plic.scala 345:20]
  wire [3:0] _T_198 = _T_196 ? effectivePriority_52 : effectivePriority_53; // @[Misc.scala 34:9]
  wire  _T_199 = _T_196 ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
  wire  _T_200 = effectivePriority_54 >= effectivePriority_55; // @[Plic.scala 345:20]
  wire [3:0] _T_202 = _T_200 ? effectivePriority_54 : effectivePriority_55; // @[Misc.scala 34:9]
  wire  _T_203 = _T_200 ? 1'h0 : 1'h1; // @[Misc.scala 34:36]
  wire  _T_204 = _T_198 >= _T_202; // @[Plic.scala 345:20]
  wire [1:0] _GEN_23 = {{1'd0}, _T_203}; // @[Plic.scala 345:61]
  wire [1:0] _T_205 = 2'h2 | _GEN_23; // @[Plic.scala 345:61]
  wire [3:0] _T_206 = _T_204 ? _T_198 : _T_202; // @[Misc.scala 34:9]
  wire [1:0] _T_207 = _T_204 ? {{1'd0}, _T_199} : _T_205; // @[Misc.scala 34:36]
  wire  _T_208 = _T_194 >= _T_206; // @[Plic.scala 345:20]
  wire [2:0] _GEN_24 = {{1'd0}, _T_207}; // @[Plic.scala 345:61]
  wire [2:0] _T_209 = 3'h4 | _GEN_24; // @[Plic.scala 345:61]
  wire [3:0] _T_210 = _T_208 ? _T_194 : _T_206; // @[Misc.scala 34:9]
  wire [2:0] _T_211 = _T_208 ? {{1'd0}, _T_195} : _T_209; // @[Misc.scala 34:36]
  wire  _T_212 = _T_210 >= effectivePriority_56; // @[Plic.scala 345:20]
  wire [3:0] _T_214 = _T_212 ? _T_210 : effectivePriority_56; // @[Misc.scala 34:9]
  wire [3:0] _T_215 = _T_212 ? {{1'd0}, _T_211} : 4'h8; // @[Misc.scala 34:36]
  wire  _T_216 = _T_182 >= _T_214; // @[Plic.scala 345:20]
  wire [4:0] _GEN_25 = {{1'd0}, _T_215}; // @[Plic.scala 345:61]
  wire [4:0] _T_217 = 5'h10 | _GEN_25; // @[Plic.scala 345:61]
  wire [3:0] _T_218 = _T_216 ? _T_182 : _T_214; // @[Misc.scala 34:9]
  wire [4:0] _T_219 = _T_216 ? {{1'd0}, _T_183} : _T_217; // @[Misc.scala 34:36]
  wire  _T_220 = _T_122 >= _T_218; // @[Plic.scala 345:20]
  wire [5:0] _GEN_26 = {{1'd0}, _T_219}; // @[Plic.scala 345:61]
  wire [5:0] _T_221 = 6'h20 | _GEN_26; // @[Plic.scala 345:61]
  wire [3:0] maxPri = _T_220 ? _T_122 : _T_218; // @[Misc.scala 34:9]
  assign io_dev = _T_220 ? {{1'd0}, _T_123} : _T_221; // @[Misc.scala 34:36]
  assign io_max = maxPri[2:0]; // @[Plic.scala 351:10]
endmodule
module Queue_22(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input         io_enq_bits_read,
  input  [23:0] io_enq_bits_index,
  input  [31:0] io_enq_bits_data,
  input  [3:0]  io_enq_bits_mask,
  input  [6:0]  io_enq_bits_extra_tlrr_extra_source,
  input  [1:0]  io_enq_bits_extra_tlrr_extra_size,
  input         io_deq_ready,
  output        io_deq_valid,
  output        io_deq_bits_read,
  output [23:0] io_deq_bits_index,
  output [31:0] io_deq_bits_data,
  output [3:0]  io_deq_bits_mask,
  output [6:0]  io_deq_bits_extra_tlrr_extra_source,
  output [1:0]  io_deq_bits_extra_tlrr_extra_size
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_6;
`endif // RANDOMIZE_REG_INIT
  reg  ram_read [0:0]; // @[Decoupled.scala 259:95]
  wire  ram_read_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_read_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_read_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_read_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_read_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_read_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_read_MPORT_en; // @[Decoupled.scala 259:95]
  reg [23:0] ram_index [0:0]; // @[Decoupled.scala 259:95]
  wire  ram_index_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_index_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [23:0] ram_index_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [23:0] ram_index_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_index_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_index_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_index_MPORT_en; // @[Decoupled.scala 259:95]
  reg [31:0] ram_data [0:0]; // @[Decoupled.scala 259:95]
  wire  ram_data_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_data_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [31:0] ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [31:0] ram_data_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_data_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_data_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_data_MPORT_en; // @[Decoupled.scala 259:95]
  reg [3:0] ram_mask [0:0]; // @[Decoupled.scala 259:95]
  wire  ram_mask_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_mask_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [3:0] ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [3:0] ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_mask_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_mask_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_mask_MPORT_en; // @[Decoupled.scala 259:95]
  reg [6:0] ram_extra_tlrr_extra_source [0:0]; // @[Decoupled.scala 259:95]
  wire  ram_extra_tlrr_extra_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_extra_tlrr_extra_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [6:0] ram_extra_tlrr_extra_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [6:0] ram_extra_tlrr_extra_source_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_extra_tlrr_extra_source_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_extra_tlrr_extra_source_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_extra_tlrr_extra_source_MPORT_en; // @[Decoupled.scala 259:95]
  reg [1:0] ram_extra_tlrr_extra_size [0:0]; // @[Decoupled.scala 259:95]
  wire  ram_extra_tlrr_extra_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_extra_tlrr_extra_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [1:0] ram_extra_tlrr_extra_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [1:0] ram_extra_tlrr_extra_size_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_extra_tlrr_extra_size_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_extra_tlrr_extra_size_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_extra_tlrr_extra_size_MPORT_en; // @[Decoupled.scala 259:95]
  reg  maybe_full; // @[Decoupled.scala 262:27]
  wire  empty = ~maybe_full; // @[Decoupled.scala 264:28]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
  wire  do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
  assign ram_read_io_deq_bits_MPORT_en = 1'h1;
  assign ram_read_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_read_io_deq_bits_MPORT_data = ram_read[ram_read_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_read_MPORT_data = io_enq_bits_read;
  assign ram_read_MPORT_addr = 1'h0;
  assign ram_read_MPORT_mask = 1'h1;
  assign ram_read_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_index_io_deq_bits_MPORT_en = 1'h1;
  assign ram_index_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_index_io_deq_bits_MPORT_data = ram_index[ram_index_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_index_MPORT_data = io_enq_bits_index;
  assign ram_index_MPORT_addr = 1'h0;
  assign ram_index_MPORT_mask = 1'h1;
  assign ram_index_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_data_io_deq_bits_MPORT_en = 1'h1;
  assign ram_data_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_data_io_deq_bits_MPORT_data = ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_data_MPORT_data = io_enq_bits_data;
  assign ram_data_MPORT_addr = 1'h0;
  assign ram_data_MPORT_mask = 1'h1;
  assign ram_data_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_mask_io_deq_bits_MPORT_en = 1'h1;
  assign ram_mask_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_mask_io_deq_bits_MPORT_data = ram_mask[ram_mask_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_mask_MPORT_data = io_enq_bits_mask;
  assign ram_mask_MPORT_addr = 1'h0;
  assign ram_mask_MPORT_mask = 1'h1;
  assign ram_mask_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_extra_tlrr_extra_source_io_deq_bits_MPORT_en = 1'h1;
  assign ram_extra_tlrr_extra_source_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_extra_tlrr_extra_source_io_deq_bits_MPORT_data =
    ram_extra_tlrr_extra_source[ram_extra_tlrr_extra_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_extra_tlrr_extra_source_MPORT_data = io_enq_bits_extra_tlrr_extra_source;
  assign ram_extra_tlrr_extra_source_MPORT_addr = 1'h0;
  assign ram_extra_tlrr_extra_source_MPORT_mask = 1'h1;
  assign ram_extra_tlrr_extra_source_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_extra_tlrr_extra_size_io_deq_bits_MPORT_en = 1'h1;
  assign ram_extra_tlrr_extra_size_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_extra_tlrr_extra_size_io_deq_bits_MPORT_data =
    ram_extra_tlrr_extra_size[ram_extra_tlrr_extra_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_extra_tlrr_extra_size_MPORT_data = io_enq_bits_extra_tlrr_extra_size;
  assign ram_extra_tlrr_extra_size_MPORT_addr = 1'h0;
  assign ram_extra_tlrr_extra_size_MPORT_mask = 1'h1;
  assign ram_extra_tlrr_extra_size_MPORT_en = io_enq_ready & io_enq_valid;
  assign io_enq_ready = ~maybe_full; // @[Decoupled.scala 289:19]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 288:19]
  assign io_deq_bits_read = ram_read_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_index = ram_index_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_data = ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_mask = ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_extra_tlrr_extra_source = ram_extra_tlrr_extra_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_extra_tlrr_extra_size = ram_extra_tlrr_extra_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  always @(posedge clock) begin
    if (ram_read_MPORT_en & ram_read_MPORT_mask) begin
      ram_read[ram_read_MPORT_addr] <= ram_read_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_index_MPORT_en & ram_index_MPORT_mask) begin
      ram_index[ram_index_MPORT_addr] <= ram_index_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_data_MPORT_en & ram_data_MPORT_mask) begin
      ram_data[ram_data_MPORT_addr] <= ram_data_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_mask_MPORT_en & ram_mask_MPORT_mask) begin
      ram_mask[ram_mask_MPORT_addr] <= ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_extra_tlrr_extra_source_MPORT_en & ram_extra_tlrr_extra_source_MPORT_mask) begin
      ram_extra_tlrr_extra_source[ram_extra_tlrr_extra_source_MPORT_addr] <= ram_extra_tlrr_extra_source_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_extra_tlrr_extra_size_MPORT_en & ram_extra_tlrr_extra_size_MPORT_mask) begin
      ram_extra_tlrr_extra_size[ram_extra_tlrr_extra_size_MPORT_addr] <= ram_extra_tlrr_extra_size_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (reset) begin // @[Decoupled.scala 262:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 262:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 279:27]
      maybe_full <= do_enq; // @[Decoupled.scala 280:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_read[initvar] = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_index[initvar] = _RAND_1[23:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_data[initvar] = _RAND_2[31:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_mask[initvar] = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_extra_tlrr_extra_source[initvar] = _RAND_4[6:0];
  _RAND_5 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_extra_tlrr_extra_size[initvar] = _RAND_5[1:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_6 = {1{`RANDOM}};
  maybe_full = _RAND_6[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLPLIC(
  input         clock,
  input         reset,
  input         auto_int_in_0,
  input         auto_int_in_1,
  input         auto_int_in_2,
  input         auto_int_in_3,
  input         auto_int_in_4,
  input         auto_int_in_5,
  input         auto_int_in_6,
  input         auto_int_in_7,
  input         auto_int_in_8,
  input         auto_int_in_9,
  input         auto_int_in_10,
  input         auto_int_in_11,
  input         auto_int_in_12,
  input         auto_int_in_13,
  input         auto_int_in_14,
  input         auto_int_in_15,
  input         auto_int_in_16,
  input         auto_int_in_17,
  input         auto_int_in_18,
  input         auto_int_in_19,
  input         auto_int_in_20,
  input         auto_int_in_21,
  input         auto_int_in_22,
  input         auto_int_in_23,
  input         auto_int_in_24,
  input         auto_int_in_25,
  input         auto_int_in_26,
  input         auto_int_in_27,
  input         auto_int_in_28,
  input         auto_int_in_29,
  input         auto_int_in_30,
  input         auto_int_in_31,
  input         auto_int_in_32,
  input         auto_int_in_33,
  input         auto_int_in_34,
  input         auto_int_in_35,
  input         auto_int_in_36,
  input         auto_int_in_37,
  input         auto_int_in_38,
  input         auto_int_in_39,
  input         auto_int_in_40,
  input         auto_int_in_41,
  input         auto_int_in_42,
  input         auto_int_in_43,
  input         auto_int_in_44,
  input         auto_int_in_45,
  input         auto_int_in_46,
  input         auto_int_in_47,
  input         auto_int_in_48,
  input         auto_int_in_49,
  input         auto_int_in_50,
  input         auto_int_in_51,
  input         auto_int_in_52,
  input         auto_int_in_53,
  input         auto_int_in_54,
  input         auto_int_in_55,
  output        auto_int_out_1_0,
  output        auto_int_out_0_0,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [1:0]  auto_in_a_bits_size,
  input  [6:0]  auto_in_a_bits_source,
  input  [27:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [1:0]  auto_in_d_bits_size,
  output [6:0]  auto_in_d_bits_source,
  output [31:0] auto_in_d_bits_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [31:0] _RAND_33;
  reg [31:0] _RAND_34;
  reg [31:0] _RAND_35;
  reg [31:0] _RAND_36;
  reg [31:0] _RAND_37;
  reg [31:0] _RAND_38;
  reg [31:0] _RAND_39;
  reg [31:0] _RAND_40;
  reg [31:0] _RAND_41;
  reg [31:0] _RAND_42;
  reg [31:0] _RAND_43;
  reg [31:0] _RAND_44;
  reg [31:0] _RAND_45;
  reg [31:0] _RAND_46;
  reg [31:0] _RAND_47;
  reg [31:0] _RAND_48;
  reg [31:0] _RAND_49;
  reg [31:0] _RAND_50;
  reg [31:0] _RAND_51;
  reg [31:0] _RAND_52;
  reg [31:0] _RAND_53;
  reg [31:0] _RAND_54;
  reg [31:0] _RAND_55;
  reg [31:0] _RAND_56;
  reg [31:0] _RAND_57;
  reg [31:0] _RAND_58;
  reg [31:0] _RAND_59;
  reg [31:0] _RAND_60;
  reg [31:0] _RAND_61;
  reg [31:0] _RAND_62;
  reg [31:0] _RAND_63;
  reg [31:0] _RAND_64;
  reg [31:0] _RAND_65;
  reg [31:0] _RAND_66;
  reg [31:0] _RAND_67;
  reg [31:0] _RAND_68;
  reg [31:0] _RAND_69;
  reg [31:0] _RAND_70;
  reg [31:0] _RAND_71;
  reg [31:0] _RAND_72;
  reg [31:0] _RAND_73;
  reg [31:0] _RAND_74;
  reg [31:0] _RAND_75;
  reg [31:0] _RAND_76;
  reg [31:0] _RAND_77;
  reg [31:0] _RAND_78;
  reg [31:0] _RAND_79;
  reg [31:0] _RAND_80;
  reg [31:0] _RAND_81;
  reg [31:0] _RAND_82;
  reg [31:0] _RAND_83;
  reg [31:0] _RAND_84;
  reg [31:0] _RAND_85;
  reg [31:0] _RAND_86;
  reg [31:0] _RAND_87;
  reg [31:0] _RAND_88;
  reg [31:0] _RAND_89;
  reg [31:0] _RAND_90;
  reg [31:0] _RAND_91;
  reg [31:0] _RAND_92;
  reg [31:0] _RAND_93;
  reg [31:0] _RAND_94;
  reg [31:0] _RAND_95;
  reg [31:0] _RAND_96;
  reg [31:0] _RAND_97;
  reg [31:0] _RAND_98;
  reg [31:0] _RAND_99;
  reg [31:0] _RAND_100;
  reg [31:0] _RAND_101;
  reg [31:0] _RAND_102;
  reg [31:0] _RAND_103;
  reg [31:0] _RAND_104;
  reg [31:0] _RAND_105;
  reg [31:0] _RAND_106;
  reg [31:0] _RAND_107;
  reg [31:0] _RAND_108;
  reg [31:0] _RAND_109;
  reg [31:0] _RAND_110;
  reg [31:0] _RAND_111;
  reg [31:0] _RAND_112;
  reg [31:0] _RAND_113;
  reg [31:0] _RAND_114;
  reg [31:0] _RAND_115;
  reg [31:0] _RAND_116;
  reg [31:0] _RAND_117;
  reg [31:0] _RAND_118;
  reg [31:0] _RAND_119;
  reg [31:0] _RAND_120;
  reg [31:0] _RAND_121;
  reg [31:0] _RAND_122;
  reg [31:0] _RAND_123;
  reg [31:0] _RAND_124;
  reg [31:0] _RAND_125;
  reg [31:0] _RAND_126;
  reg [31:0] _RAND_127;
  reg [31:0] _RAND_128;
  reg [31:0] _RAND_129;
  reg [31:0] _RAND_130;
  reg [31:0] _RAND_131;
  reg [31:0] _RAND_132;
  reg [31:0] _RAND_133;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [27:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  gateways_gateway_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_1_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_1_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_1_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_1_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_1_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_1_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_2_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_2_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_2_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_2_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_2_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_2_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_3_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_3_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_3_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_3_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_3_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_3_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_4_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_4_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_4_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_4_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_4_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_4_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_5_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_5_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_5_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_5_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_5_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_5_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_6_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_6_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_6_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_6_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_6_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_6_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_7_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_7_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_7_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_7_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_7_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_7_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_8_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_8_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_8_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_8_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_8_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_8_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_9_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_9_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_9_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_9_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_9_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_9_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_10_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_10_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_10_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_10_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_10_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_10_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_11_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_11_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_11_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_11_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_11_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_11_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_12_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_12_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_12_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_12_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_12_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_12_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_13_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_13_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_13_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_13_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_13_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_13_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_14_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_14_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_14_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_14_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_14_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_14_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_15_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_15_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_15_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_15_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_15_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_15_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_16_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_16_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_16_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_16_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_16_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_16_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_17_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_17_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_17_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_17_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_17_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_17_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_18_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_18_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_18_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_18_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_18_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_18_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_19_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_19_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_19_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_19_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_19_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_19_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_20_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_20_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_20_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_20_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_20_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_20_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_21_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_21_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_21_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_21_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_21_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_21_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_22_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_22_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_22_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_22_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_22_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_22_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_23_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_23_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_23_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_23_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_23_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_23_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_24_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_24_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_24_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_24_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_24_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_24_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_25_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_25_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_25_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_25_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_25_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_25_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_26_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_26_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_26_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_26_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_26_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_26_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_27_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_27_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_27_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_27_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_27_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_27_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_28_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_28_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_28_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_28_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_28_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_28_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_29_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_29_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_29_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_29_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_29_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_29_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_30_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_30_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_30_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_30_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_30_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_30_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_31_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_31_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_31_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_31_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_31_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_31_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_32_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_32_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_32_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_32_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_32_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_32_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_33_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_33_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_33_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_33_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_33_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_33_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_34_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_34_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_34_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_34_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_34_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_34_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_35_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_35_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_35_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_35_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_35_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_35_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_36_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_36_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_36_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_36_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_36_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_36_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_37_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_37_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_37_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_37_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_37_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_37_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_38_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_38_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_38_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_38_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_38_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_38_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_39_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_39_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_39_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_39_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_39_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_39_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_40_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_40_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_40_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_40_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_40_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_40_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_41_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_41_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_41_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_41_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_41_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_41_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_42_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_42_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_42_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_42_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_42_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_42_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_43_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_43_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_43_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_43_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_43_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_43_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_44_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_44_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_44_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_44_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_44_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_44_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_45_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_45_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_45_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_45_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_45_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_45_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_46_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_46_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_46_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_46_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_46_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_46_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_47_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_47_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_47_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_47_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_47_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_47_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_48_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_48_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_48_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_48_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_48_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_48_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_49_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_49_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_49_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_49_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_49_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_49_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_50_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_50_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_50_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_50_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_50_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_50_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_51_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_51_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_51_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_51_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_51_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_51_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_52_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_52_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_52_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_52_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_52_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_52_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_53_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_53_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_53_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_53_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_53_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_53_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_54_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_54_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_54_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_54_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_54_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_54_io_plic_complete; // @[Plic.scala 156:27]
  wire  gateways_gateway_55_clock; // @[Plic.scala 156:27]
  wire  gateways_gateway_55_reset; // @[Plic.scala 156:27]
  wire  gateways_gateway_55_io_interrupt; // @[Plic.scala 156:27]
  wire  gateways_gateway_55_io_plic_valid; // @[Plic.scala 156:27]
  wire  gateways_gateway_55_io_plic_ready; // @[Plic.scala 156:27]
  wire  gateways_gateway_55_io_plic_complete; // @[Plic.scala 156:27]
  wire [2:0] fanin_io_prio_0; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_1; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_2; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_3; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_4; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_5; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_6; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_7; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_8; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_9; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_10; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_11; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_12; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_13; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_14; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_15; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_16; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_17; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_18; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_19; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_20; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_21; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_22; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_23; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_24; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_25; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_26; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_27; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_28; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_29; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_30; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_31; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_32; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_33; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_34; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_35; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_36; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_37; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_38; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_39; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_40; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_41; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_42; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_43; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_44; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_45; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_46; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_47; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_48; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_49; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_50; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_51; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_52; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_53; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_54; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_prio_55; // @[Plic.scala 184:25]
  wire [55:0] fanin_io_ip; // @[Plic.scala 184:25]
  wire [5:0] fanin_io_dev; // @[Plic.scala 184:25]
  wire [2:0] fanin_io_max; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_0; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_1; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_2; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_3; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_4; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_5; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_6; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_7; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_8; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_9; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_10; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_11; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_12; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_13; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_14; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_15; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_16; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_17; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_18; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_19; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_20; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_21; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_22; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_23; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_24; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_25; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_26; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_27; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_28; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_29; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_30; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_31; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_32; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_33; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_34; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_35; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_36; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_37; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_38; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_39; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_40; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_41; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_42; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_43; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_44; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_45; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_46; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_47; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_48; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_49; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_50; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_51; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_52; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_53; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_54; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_prio_55; // @[Plic.scala 184:25]
  wire [55:0] fanin_1_io_ip; // @[Plic.scala 184:25]
  wire [5:0] fanin_1_io_dev; // @[Plic.scala 184:25]
  wire [2:0] fanin_1_io_max; // @[Plic.scala 184:25]
  wire  out_back_clock; // @[Decoupled.scala 361:21]
  wire  out_back_reset; // @[Decoupled.scala 361:21]
  wire  out_back_io_enq_ready; // @[Decoupled.scala 361:21]
  wire  out_back_io_enq_valid; // @[Decoupled.scala 361:21]
  wire  out_back_io_enq_bits_read; // @[Decoupled.scala 361:21]
  wire [23:0] out_back_io_enq_bits_index; // @[Decoupled.scala 361:21]
  wire [31:0] out_back_io_enq_bits_data; // @[Decoupled.scala 361:21]
  wire [3:0] out_back_io_enq_bits_mask; // @[Decoupled.scala 361:21]
  wire [6:0] out_back_io_enq_bits_extra_tlrr_extra_source; // @[Decoupled.scala 361:21]
  wire [1:0] out_back_io_enq_bits_extra_tlrr_extra_size; // @[Decoupled.scala 361:21]
  wire  out_back_io_deq_ready; // @[Decoupled.scala 361:21]
  wire  out_back_io_deq_valid; // @[Decoupled.scala 361:21]
  wire  out_back_io_deq_bits_read; // @[Decoupled.scala 361:21]
  wire [23:0] out_back_io_deq_bits_index; // @[Decoupled.scala 361:21]
  wire [31:0] out_back_io_deq_bits_data; // @[Decoupled.scala 361:21]
  wire [3:0] out_back_io_deq_bits_mask; // @[Decoupled.scala 361:21]
  wire [6:0] out_back_io_deq_bits_extra_tlrr_extra_source; // @[Decoupled.scala 361:21]
  wire [1:0] out_back_io_deq_bits_extra_tlrr_extra_size; // @[Decoupled.scala 361:21]
  reg [2:0] priority_0; // @[Plic.scala 163:31]
  reg [2:0] priority_1; // @[Plic.scala 163:31]
  reg [2:0] priority_2; // @[Plic.scala 163:31]
  reg [2:0] priority_3; // @[Plic.scala 163:31]
  reg [2:0] priority_4; // @[Plic.scala 163:31]
  reg [2:0] priority_5; // @[Plic.scala 163:31]
  reg [2:0] priority_6; // @[Plic.scala 163:31]
  reg [2:0] priority_7; // @[Plic.scala 163:31]
  reg [2:0] priority_8; // @[Plic.scala 163:31]
  reg [2:0] priority_9; // @[Plic.scala 163:31]
  reg [2:0] priority_10; // @[Plic.scala 163:31]
  reg [2:0] priority_11; // @[Plic.scala 163:31]
  reg [2:0] priority_12; // @[Plic.scala 163:31]
  reg [2:0] priority_13; // @[Plic.scala 163:31]
  reg [2:0] priority_14; // @[Plic.scala 163:31]
  reg [2:0] priority_15; // @[Plic.scala 163:31]
  reg [2:0] priority_16; // @[Plic.scala 163:31]
  reg [2:0] priority_17; // @[Plic.scala 163:31]
  reg [2:0] priority_18; // @[Plic.scala 163:31]
  reg [2:0] priority_19; // @[Plic.scala 163:31]
  reg [2:0] priority_20; // @[Plic.scala 163:31]
  reg [2:0] priority_21; // @[Plic.scala 163:31]
  reg [2:0] priority_22; // @[Plic.scala 163:31]
  reg [2:0] priority_23; // @[Plic.scala 163:31]
  reg [2:0] priority_24; // @[Plic.scala 163:31]
  reg [2:0] priority_25; // @[Plic.scala 163:31]
  reg [2:0] priority_26; // @[Plic.scala 163:31]
  reg [2:0] priority_27; // @[Plic.scala 163:31]
  reg [2:0] priority_28; // @[Plic.scala 163:31]
  reg [2:0] priority_29; // @[Plic.scala 163:31]
  reg [2:0] priority_30; // @[Plic.scala 163:31]
  reg [2:0] priority_31; // @[Plic.scala 163:31]
  reg [2:0] priority_32; // @[Plic.scala 163:31]
  reg [2:0] priority_33; // @[Plic.scala 163:31]
  reg [2:0] priority_34; // @[Plic.scala 163:31]
  reg [2:0] priority_35; // @[Plic.scala 163:31]
  reg [2:0] priority_36; // @[Plic.scala 163:31]
  reg [2:0] priority_37; // @[Plic.scala 163:31]
  reg [2:0] priority_38; // @[Plic.scala 163:31]
  reg [2:0] priority_39; // @[Plic.scala 163:31]
  reg [2:0] priority_40; // @[Plic.scala 163:31]
  reg [2:0] priority_41; // @[Plic.scala 163:31]
  reg [2:0] priority_42; // @[Plic.scala 163:31]
  reg [2:0] priority_43; // @[Plic.scala 163:31]
  reg [2:0] priority_44; // @[Plic.scala 163:31]
  reg [2:0] priority_45; // @[Plic.scala 163:31]
  reg [2:0] priority_46; // @[Plic.scala 163:31]
  reg [2:0] priority_47; // @[Plic.scala 163:31]
  reg [2:0] priority_48; // @[Plic.scala 163:31]
  reg [2:0] priority_49; // @[Plic.scala 163:31]
  reg [2:0] priority_50; // @[Plic.scala 163:31]
  reg [2:0] priority_51; // @[Plic.scala 163:31]
  reg [2:0] priority_52; // @[Plic.scala 163:31]
  reg [2:0] priority_53; // @[Plic.scala 163:31]
  reg [2:0] priority_54; // @[Plic.scala 163:31]
  reg [2:0] priority_55; // @[Plic.scala 163:31]
  reg [2:0] threshold_0; // @[Plic.scala 166:31]
  reg [2:0] threshold_1; // @[Plic.scala 166:31]
  reg  pending_0; // @[Plic.scala 168:22]
  reg  pending_1; // @[Plic.scala 168:22]
  reg  pending_2; // @[Plic.scala 168:22]
  reg  pending_3; // @[Plic.scala 168:22]
  reg  pending_4; // @[Plic.scala 168:22]
  reg  pending_5; // @[Plic.scala 168:22]
  reg  pending_6; // @[Plic.scala 168:22]
  reg  pending_7; // @[Plic.scala 168:22]
  reg  pending_8; // @[Plic.scala 168:22]
  reg  pending_9; // @[Plic.scala 168:22]
  reg  pending_10; // @[Plic.scala 168:22]
  reg  pending_11; // @[Plic.scala 168:22]
  reg  pending_12; // @[Plic.scala 168:22]
  reg  pending_13; // @[Plic.scala 168:22]
  reg  pending_14; // @[Plic.scala 168:22]
  reg  pending_15; // @[Plic.scala 168:22]
  reg  pending_16; // @[Plic.scala 168:22]
  reg  pending_17; // @[Plic.scala 168:22]
  reg  pending_18; // @[Plic.scala 168:22]
  reg  pending_19; // @[Plic.scala 168:22]
  reg  pending_20; // @[Plic.scala 168:22]
  reg  pending_21; // @[Plic.scala 168:22]
  reg  pending_22; // @[Plic.scala 168:22]
  reg  pending_23; // @[Plic.scala 168:22]
  reg  pending_24; // @[Plic.scala 168:22]
  reg  pending_25; // @[Plic.scala 168:22]
  reg  pending_26; // @[Plic.scala 168:22]
  reg  pending_27; // @[Plic.scala 168:22]
  reg  pending_28; // @[Plic.scala 168:22]
  reg  pending_29; // @[Plic.scala 168:22]
  reg  pending_30; // @[Plic.scala 168:22]
  reg  pending_31; // @[Plic.scala 168:22]
  reg  pending_32; // @[Plic.scala 168:22]
  reg  pending_33; // @[Plic.scala 168:22]
  reg  pending_34; // @[Plic.scala 168:22]
  reg  pending_35; // @[Plic.scala 168:22]
  reg  pending_36; // @[Plic.scala 168:22]
  reg  pending_37; // @[Plic.scala 168:22]
  reg  pending_38; // @[Plic.scala 168:22]
  reg  pending_39; // @[Plic.scala 168:22]
  reg  pending_40; // @[Plic.scala 168:22]
  reg  pending_41; // @[Plic.scala 168:22]
  reg  pending_42; // @[Plic.scala 168:22]
  reg  pending_43; // @[Plic.scala 168:22]
  reg  pending_44; // @[Plic.scala 168:22]
  reg  pending_45; // @[Plic.scala 168:22]
  reg  pending_46; // @[Plic.scala 168:22]
  reg  pending_47; // @[Plic.scala 168:22]
  reg  pending_48; // @[Plic.scala 168:22]
  reg  pending_49; // @[Plic.scala 168:22]
  reg  pending_50; // @[Plic.scala 168:22]
  reg  pending_51; // @[Plic.scala 168:22]
  reg  pending_52; // @[Plic.scala 168:22]
  reg  pending_53; // @[Plic.scala 168:22]
  reg  pending_54; // @[Plic.scala 168:22]
  reg  pending_55; // @[Plic.scala 168:22]
  reg [6:0] enables_0_0; // @[Plic.scala 174:26]
  reg [7:0] enables_0_1; // @[Plic.scala 175:50]
  reg [7:0] enables_0_2; // @[Plic.scala 175:50]
  reg [7:0] enables_0_3; // @[Plic.scala 175:50]
  reg [7:0] enables_0_4; // @[Plic.scala 175:50]
  reg [7:0] enables_0_5; // @[Plic.scala 175:50]
  reg [7:0] enables_0_6; // @[Plic.scala 175:50]
  reg  enables_0_7; // @[Plic.scala 176:51]
  reg [6:0] enables_1_0; // @[Plic.scala 174:26]
  reg [7:0] enables_1_1; // @[Plic.scala 175:50]
  reg [7:0] enables_1_2; // @[Plic.scala 175:50]
  reg [7:0] enables_1_3; // @[Plic.scala 175:50]
  reg [7:0] enables_1_4; // @[Plic.scala 175:50]
  reg [7:0] enables_1_5; // @[Plic.scala 175:50]
  reg [7:0] enables_1_6; // @[Plic.scala 175:50]
  reg  enables_1_7; // @[Plic.scala 176:51]
  wire [55:0] enableVec_0 = {enables_0_7,enables_0_6,enables_0_5,enables_0_4,enables_0_3,enables_0_2,enables_0_1,
    enables_0_0}; // @[Cat.scala 31:58]
  wire [55:0] enableVec_1 = {enables_1_7,enables_1_6,enables_1_5,enables_1_4,enables_1_3,enables_1_2,enables_1_1,
    enables_1_0}; // @[Cat.scala 31:58]
  wire [56:0] enableVec0_0 = {enables_0_7,enables_0_6,enables_0_5,enables_0_4,enables_0_3,enables_0_2,enables_0_1,
    enables_0_0,1'h0}; // @[Cat.scala 31:58]
  wire [56:0] enableVec0_1 = {enables_1_7,enables_1_6,enables_1_5,enables_1_4,enables_1_3,enables_1_2,enables_1_1,
    enables_1_0,1'h0}; // @[Cat.scala 31:58]
  reg [5:0] maxDevs_0; // @[Plic.scala 181:22]
  reg [5:0] maxDevs_1; // @[Plic.scala 181:22]
  wire [6:0] pendingUInt_lo_lo_lo = {pending_6,pending_5,pending_4,pending_3,pending_2,pending_1,pending_0}; // @[Cat.scala 31:58]
  wire [13:0] pendingUInt_lo_lo = {pending_13,pending_12,pending_11,pending_10,pending_9,pending_8,pending_7,
    pendingUInt_lo_lo_lo}; // @[Cat.scala 31:58]
  wire [6:0] pendingUInt_lo_hi_lo = {pending_20,pending_19,pending_18,pending_17,pending_16,pending_15,pending_14}; // @[Cat.scala 31:58]
  wire [27:0] pendingUInt_lo = {pending_27,pending_26,pending_25,pending_24,pending_23,pending_22,pending_21,
    pendingUInt_lo_hi_lo,pendingUInt_lo_lo}; // @[Cat.scala 31:58]
  wire [6:0] pendingUInt_hi_lo_lo = {pending_34,pending_33,pending_32,pending_31,pending_30,pending_29,pending_28}; // @[Cat.scala 31:58]
  wire [13:0] pendingUInt_hi_lo = {pending_41,pending_40,pending_39,pending_38,pending_37,pending_36,pending_35,
    pendingUInt_hi_lo_lo}; // @[Cat.scala 31:58]
  wire [6:0] pendingUInt_hi_hi_lo = {pending_48,pending_47,pending_46,pending_45,pending_44,pending_43,pending_42}; // @[Cat.scala 31:58]
  wire [55:0] pendingUInt = {pending_55,pending_54,pending_53,pending_52,pending_51,pending_50,pending_49,
    pendingUInt_hi_hi_lo,pendingUInt_hi_lo,pendingUInt_lo}; // @[Cat.scala 31:58]
  reg [2:0] bundleOut_0_0_REG; // @[Plic.scala 188:41]
  reg [2:0] bundleOut_1_0_REG; // @[Plic.scala 188:41]
  wire [8:0] out_oindex = {out_back_io_deq_bits_index[19],out_back_io_deq_bits_index[11],out_back_io_deq_bits_index[10],
    out_back_io_deq_bits_index[5],out_back_io_deq_bits_index[4],out_back_io_deq_bits_index[3],out_back_io_deq_bits_index
    [2],out_back_io_deq_bits_index[1],out_back_io_deq_bits_index[0]}; // @[Cat.scala 31:58]
  wire [511:0] _out_backSel_T = 512'h1 << out_oindex; // @[OneHot.scala 57:35]
  wire  out_backSel_321 = _out_backSel_T[321]; // @[RegisterRouter.scala 83:24]
  wire [23:0] out_bindex = out_back_io_deq_bits_index & 24'hf7f3c0; // @[RegisterRouter.scala 83:24]
  wire  _out_T_101 = out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_roready_118 = out_back_io_deq_valid & auto_in_d_ready & out_back_io_deq_bits_read & out_backSel_321 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire [7:0] _out_backMask_T_11 = out_back_io_deq_bits_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_backMask_T_9 = out_back_io_deq_bits_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_backMask_T_7 = out_back_io_deq_bits_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_backMask_T_5 = out_back_io_deq_bits_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [31:0] out_backMask = {_out_backMask_T_11,_out_backMask_T_9,_out_backMask_T_7,_out_backMask_T_5}; // @[Cat.scala 31:58]
  wire  out_romask_118 = |out_backMask; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_118 = out_roready_118 & out_romask_118; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_257 = _out_backSel_T[257]; // @[RegisterRouter.scala 83:24]
  wire  out_roready_48 = out_back_io_deq_valid & auto_in_d_ready & out_back_io_deq_bits_read & out_backSel_257 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_48 = out_roready_48 & out_romask_118; // @[RegisterRouter.scala 83:24]
  wire [1:0] _T = {out_f_roready_118,out_f_roready_48}; // @[Plic.scala 245:21]
  wire [1:0] _T_3 = _T - 2'h1; // @[Plic.scala 245:46]
  wire [1:0] _T_4 = _T & _T_3; // @[Plic.scala 245:28]
  wire  _T_7 = ~reset; // @[Plic.scala 245:11]
  wire [5:0] _claiming_T = out_f_roready_48 ? maxDevs_0 : 6'h0; // @[Plic.scala 246:49]
  wire [5:0] _claiming_T_1 = out_f_roready_118 ? maxDevs_1 : 6'h0; // @[Plic.scala 246:49]
  wire [5:0] claiming = _claiming_T | _claiming_T_1; // @[Plic.scala 246:96]
  wire [63:0] _claimedDevs_T = 64'h1 << claiming; // @[OneHot.scala 64:12]
  wire  claimedDevs_1 = _claimedDevs_T[1]; // @[Plic.scala 247:58]
  wire  claimedDevs_2 = _claimedDevs_T[2]; // @[Plic.scala 247:58]
  wire  claimedDevs_3 = _claimedDevs_T[3]; // @[Plic.scala 247:58]
  wire  claimedDevs_4 = _claimedDevs_T[4]; // @[Plic.scala 247:58]
  wire  claimedDevs_5 = _claimedDevs_T[5]; // @[Plic.scala 247:58]
  wire  claimedDevs_6 = _claimedDevs_T[6]; // @[Plic.scala 247:58]
  wire  claimedDevs_7 = _claimedDevs_T[7]; // @[Plic.scala 247:58]
  wire  claimedDevs_8 = _claimedDevs_T[8]; // @[Plic.scala 247:58]
  wire  claimedDevs_9 = _claimedDevs_T[9]; // @[Plic.scala 247:58]
  wire  claimedDevs_10 = _claimedDevs_T[10]; // @[Plic.scala 247:58]
  wire  claimedDevs_11 = _claimedDevs_T[11]; // @[Plic.scala 247:58]
  wire  claimedDevs_12 = _claimedDevs_T[12]; // @[Plic.scala 247:58]
  wire  claimedDevs_13 = _claimedDevs_T[13]; // @[Plic.scala 247:58]
  wire  claimedDevs_14 = _claimedDevs_T[14]; // @[Plic.scala 247:58]
  wire  claimedDevs_15 = _claimedDevs_T[15]; // @[Plic.scala 247:58]
  wire  claimedDevs_16 = _claimedDevs_T[16]; // @[Plic.scala 247:58]
  wire  claimedDevs_17 = _claimedDevs_T[17]; // @[Plic.scala 247:58]
  wire  claimedDevs_18 = _claimedDevs_T[18]; // @[Plic.scala 247:58]
  wire  claimedDevs_19 = _claimedDevs_T[19]; // @[Plic.scala 247:58]
  wire  claimedDevs_20 = _claimedDevs_T[20]; // @[Plic.scala 247:58]
  wire  claimedDevs_21 = _claimedDevs_T[21]; // @[Plic.scala 247:58]
  wire  claimedDevs_22 = _claimedDevs_T[22]; // @[Plic.scala 247:58]
  wire  claimedDevs_23 = _claimedDevs_T[23]; // @[Plic.scala 247:58]
  wire  claimedDevs_24 = _claimedDevs_T[24]; // @[Plic.scala 247:58]
  wire  claimedDevs_25 = _claimedDevs_T[25]; // @[Plic.scala 247:58]
  wire  claimedDevs_26 = _claimedDevs_T[26]; // @[Plic.scala 247:58]
  wire  claimedDevs_27 = _claimedDevs_T[27]; // @[Plic.scala 247:58]
  wire  claimedDevs_28 = _claimedDevs_T[28]; // @[Plic.scala 247:58]
  wire  claimedDevs_29 = _claimedDevs_T[29]; // @[Plic.scala 247:58]
  wire  claimedDevs_30 = _claimedDevs_T[30]; // @[Plic.scala 247:58]
  wire  claimedDevs_31 = _claimedDevs_T[31]; // @[Plic.scala 247:58]
  wire  claimedDevs_32 = _claimedDevs_T[32]; // @[Plic.scala 247:58]
  wire  claimedDevs_33 = _claimedDevs_T[33]; // @[Plic.scala 247:58]
  wire  claimedDevs_34 = _claimedDevs_T[34]; // @[Plic.scala 247:58]
  wire  claimedDevs_35 = _claimedDevs_T[35]; // @[Plic.scala 247:58]
  wire  claimedDevs_36 = _claimedDevs_T[36]; // @[Plic.scala 247:58]
  wire  claimedDevs_37 = _claimedDevs_T[37]; // @[Plic.scala 247:58]
  wire  claimedDevs_38 = _claimedDevs_T[38]; // @[Plic.scala 247:58]
  wire  claimedDevs_39 = _claimedDevs_T[39]; // @[Plic.scala 247:58]
  wire  claimedDevs_40 = _claimedDevs_T[40]; // @[Plic.scala 247:58]
  wire  claimedDevs_41 = _claimedDevs_T[41]; // @[Plic.scala 247:58]
  wire  claimedDevs_42 = _claimedDevs_T[42]; // @[Plic.scala 247:58]
  wire  claimedDevs_43 = _claimedDevs_T[43]; // @[Plic.scala 247:58]
  wire  claimedDevs_44 = _claimedDevs_T[44]; // @[Plic.scala 247:58]
  wire  claimedDevs_45 = _claimedDevs_T[45]; // @[Plic.scala 247:58]
  wire  claimedDevs_46 = _claimedDevs_T[46]; // @[Plic.scala 247:58]
  wire  claimedDevs_47 = _claimedDevs_T[47]; // @[Plic.scala 247:58]
  wire  claimedDevs_48 = _claimedDevs_T[48]; // @[Plic.scala 247:58]
  wire  claimedDevs_49 = _claimedDevs_T[49]; // @[Plic.scala 247:58]
  wire  claimedDevs_50 = _claimedDevs_T[50]; // @[Plic.scala 247:58]
  wire  claimedDevs_51 = _claimedDevs_T[51]; // @[Plic.scala 247:58]
  wire  claimedDevs_52 = _claimedDevs_T[52]; // @[Plic.scala 247:58]
  wire  claimedDevs_53 = _claimedDevs_T[53]; // @[Plic.scala 247:58]
  wire  claimedDevs_54 = _claimedDevs_T[54]; // @[Plic.scala 247:58]
  wire  claimedDevs_55 = _claimedDevs_T[55]; // @[Plic.scala 247:58]
  wire  claimedDevs_56 = _claimedDevs_T[56]; // @[Plic.scala 247:58]
  wire  out_woready_118 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_321 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_womask_118 = &out_backMask; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_118 = out_woready_118 & out_womask_118; // @[RegisterRouter.scala 83:24]
  wire [31:0] _out_T_1313 = out_back_io_deq_bits_data; // @[RegisterRouter.scala 83:24]
  wire [5:0] completerDev = _out_T_1313[5:0]; // @[package.scala 154:13]
  wire [56:0] _out_completer_1_T = enableVec0_1 >> completerDev; // @[Plic.scala 295:51]
  wire  completer_1 = out_f_woready_118 & _out_completer_1_T[0]; // @[Plic.scala 295:35]
  wire  out_woready_48 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_257 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_48 = out_woready_48 & out_womask_118; // @[RegisterRouter.scala 83:24]
  wire [56:0] _out_completer_0_T = enableVec0_0 >> completerDev; // @[Plic.scala 295:51]
  wire  completer_0 = out_f_woready_48 & _out_completer_0_T[0]; // @[Plic.scala 295:35]
  wire [1:0] _T_65 = {completer_1,completer_0}; // @[Plic.scala 262:23]
  wire [1:0] _T_68 = _T_65 - 2'h1; // @[Plic.scala 262:50]
  wire [1:0] _T_69 = _T_65 & _T_68; // @[Plic.scala 262:30]
  wire [63:0] _completedDevs_T_1 = 64'h1 << completerDev; // @[OneHot.scala 64:12]
  wire [56:0] completedDevs = completer_0 | completer_1 ? _completedDevs_T_1[56:0] : 57'h0; // @[Plic.scala 264:28]
  wire [9:0] out_prepend_8 = {pending_8,pending_7,pending_6,pending_5,pending_4,pending_3,pending_2,pending_1,pending_0,1'h0
    }; // @[Cat.scala 31:58]
  wire [18:0] out_prepend_17 = {pending_17,pending_16,pending_15,pending_14,pending_13,pending_12,pending_11,pending_10,
    pending_9,out_prepend_8}; // @[Cat.scala 31:58]
  wire  out_womask_24 = &out_backMask[24]; // @[RegisterRouter.scala 83:24]
  wire [27:0] out_prepend_26 = {pending_26,pending_25,pending_24,pending_23,pending_22,pending_21,pending_20,pending_19,
    pending_18,out_prepend_17}; // @[Cat.scala 31:58]
  wire [31:0] out_prepend_30 = {pending_30,pending_29,pending_28,pending_27,out_prepend_26}; // @[Cat.scala 31:58]
  wire  out_womask_32 = &out_backMask[2:0]; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_5 = _out_backSel_T[5]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_32 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_5 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_32 = out_woready_32 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_10 = _out_backSel_T[10]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_33 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_10 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_33 = out_woready_33 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_56 = _out_backSel_T[56]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_34 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_56 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_34 = out_woready_34 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_42 = _out_backSel_T[42]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_35 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_42 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_35 = out_woready_35 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_24 = _out_backSel_T[24]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_36 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_24 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_36 = out_woready_36 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_37 = _out_backSel_T[37]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_37 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_37 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_37 = out_woready_37 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_25 = _out_backSel_T[25]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_38 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_25 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_38 = out_woready_38 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_52 = _out_backSel_T[52]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_39 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_52 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_39 = out_woready_39 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_14 = _out_backSel_T[14]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_40 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_14 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_40 = out_woready_40 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_20 = _out_backSel_T[20]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_41 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_20 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_41 = out_woready_41 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_womask_42 = &out_backMask[7:0]; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_129 = _out_backSel_T[129]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_42 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_129 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_42 = out_woready_42 & out_womask_42; // @[RegisterRouter.scala 83:24]
  wire  out_womask_43 = &out_backMask[15:8]; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_43 = out_woready_42 & out_womask_43; // @[RegisterRouter.scala 83:24]
  wire  out_womask_44 = &out_backMask[23:16]; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_44 = out_woready_42 & out_womask_44; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_45 = out_woready_42 & out_womask_24; // @[RegisterRouter.scala 83:24]
  wire [24:0] out_prepend_33 = {enables_0_7,enables_0_6,enables_0_5,enables_0_4}; // @[Cat.scala 31:58]
  wire  out_backSel_46 = _out_backSel_T[46]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_46 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_46 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_46 = out_woready_46 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_29 = _out_backSel_T[29]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_47 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_29 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_47 = out_woready_47 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire [31:0] _out_T_610 = {{26'd0}, maxDevs_0}; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_1 = _out_backSel_T[1]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_49 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_1 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_49 = out_woready_49 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_6 = _out_backSel_T[6]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_50 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_6 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_50 = out_woready_50 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_28 = _out_backSel_T[28]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_51 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_28 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_51 = out_woready_51 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_38 = _out_backSel_T[38]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_52 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_38 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_52 = out_woready_52 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_21 = _out_backSel_T[21]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_53 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_21 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_53 = out_woready_53 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_33 = _out_backSel_T[33]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_54 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_33 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_54 = out_woready_54 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_9 = _out_backSel_T[9]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_55 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_9 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_55 = out_woready_55 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_53 = _out_backSel_T[53]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_56 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_53 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_56 = out_woready_56 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_160 = _out_backSel_T[160]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_57 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_160 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_womask_58 = &out_backMask[7:1]; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_58 = out_woready_57 & out_womask_58; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_59 = out_woready_57 & out_womask_43; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_60 = out_woready_57 & out_womask_44; // @[RegisterRouter.scala 83:24]
  wire  out_womask_61 = &out_backMask[31:24]; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_61 = out_woready_57 & out_womask_61; // @[RegisterRouter.scala 83:24]
  wire [31:0] out_prepend_37 = {enables_1_3,enables_1_2,enables_1_1,enables_1_0,1'h0}; // @[Cat.scala 31:58]
  wire  out_backSel_13 = _out_backSel_T[13]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_62 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_13 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_62 = out_woready_62 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_41 = _out_backSel_T[41]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_63 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_41 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_63 = out_woready_63 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_2 = _out_backSel_T[2]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_64 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_2 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_64 = out_woready_64 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_32 = _out_backSel_T[32]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_65 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_32 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_65 = out_woready_65 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_34 = _out_backSel_T[34]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_66 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_34 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_66 = out_woready_66 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_45 = _out_backSel_T[45]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_67 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_45 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_67 = out_woready_67 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_17 = _out_backSel_T[17]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_68 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_17 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_68 = out_woready_68 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_320 = _out_backSel_T[320]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_69 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_320 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_69 = out_woready_69 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire [3:0] out_prepend_38 = {1'h0,threshold_1}; // @[Cat.scala 31:58]
  wire [31:0] _out_T_848 = {{28'd0}, out_prepend_38}; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_256 = _out_backSel_T[256]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_71 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_256 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_71 = out_woready_71 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire [3:0] out_prepend_39 = {1'h0,threshold_0}; // @[Cat.scala 31:58]
  wire [31:0] _out_T_868 = {{28'd0}, out_prepend_39}; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_128 = _out_backSel_T[128]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_73 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_128 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_74 = out_woready_73 & out_womask_58; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_75 = out_woready_73 & out_womask_43; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_76 = out_woready_73 & out_womask_44; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_77 = out_woready_73 & out_womask_61; // @[RegisterRouter.scala 83:24]
  wire [31:0] out_prepend_43 = {enables_0_3,enables_0_2,enables_0_1,enables_0_0,1'h0}; // @[Cat.scala 31:58]
  wire  out_backSel_22 = _out_backSel_T[22]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_78 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_22 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_78 = out_woready_78 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_44 = _out_backSel_T[44]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_79 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_44 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_79 = out_woready_79 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_27 = _out_backSel_T[27]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_80 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_27 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_80 = out_woready_80 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_12 = _out_backSel_T[12]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_81 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_12 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_81 = out_woready_81 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_54 = _out_backSel_T[54]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_82 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_54 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_82 = out_woready_82 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_49 = _out_backSel_T[49]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_83 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_49 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_83 = out_woready_83 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_7 = _out_backSel_T[7]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_84 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_7 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_84 = out_woready_84 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_39 = _out_backSel_T[39]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_85 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_39 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_85 = out_woready_85 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_3 = _out_backSel_T[3]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_86 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_3 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_86 = out_woready_86 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_35 = _out_backSel_T[35]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_87 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_35 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_87 = out_woready_87 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_48 = _out_backSel_T[48]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_88 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_48 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_88 = out_woready_88 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire [9:0] out_prepend_52 = {pending_40,pending_39,pending_38,pending_37,pending_36,pending_35,pending_34,pending_33,
    pending_32,pending_31}; // @[Cat.scala 31:58]
  wire [18:0] out_prepend_61 = {pending_49,pending_48,pending_47,pending_46,pending_45,pending_44,pending_43,pending_42,
    pending_41,out_prepend_52}; // @[Cat.scala 31:58]
  wire [24:0] out_prepend_67 = {pending_55,pending_54,pending_53,pending_52,pending_51,pending_50,out_prepend_61}; // @[Cat.scala 31:58]
  wire  out_backSel_18 = _out_backSel_T[18]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_114 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_18 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_114 = out_woready_114 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_50 = _out_backSel_T[50]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_115 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_50 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_115 = out_woready_115 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_16 = _out_backSel_T[16]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_116 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_16 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_116 = out_woready_116 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_31 = _out_backSel_T[31]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_117 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_31 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_117 = out_woready_117 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire [31:0] _out_T_1327 = {{26'd0}, maxDevs_1}; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_11 = _out_backSel_T[11]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_119 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_11 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_119 = out_woready_119 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_43 = _out_backSel_T[43]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_120 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_43 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_120 = out_woready_120 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_40 = _out_backSel_T[40]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_121 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_40 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_121 = out_woready_121 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_26 = _out_backSel_T[26]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_122 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_26 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_122 = out_woready_122 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_55 = _out_backSel_T[55]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_123 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_55 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_123 = out_woready_123 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_23 = _out_backSel_T[23]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_124 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_23 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_124 = out_woready_124 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_8 = _out_backSel_T[8]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_125 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_8 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_125 = out_woready_125 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_161 = _out_backSel_T[161]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_126 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_161 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_126 = out_woready_126 & out_womask_42; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_127 = out_woready_126 & out_womask_43; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_128 = out_woready_126 & out_womask_44; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_129 = out_woready_126 & out_womask_24; // @[RegisterRouter.scala 83:24]
  wire [24:0] out_prepend_70 = {enables_1_7,enables_1_6,enables_1_5,enables_1_4}; // @[Cat.scala 31:58]
  wire  out_backSel_36 = _out_backSel_T[36]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_130 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_36 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_130 = out_woready_130 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_30 = _out_backSel_T[30]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_131 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_30 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_131 = out_woready_131 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_51 = _out_backSel_T[51]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_132 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_51 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_132 = out_woready_132 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_19 = _out_backSel_T[19]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_133 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_19 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_133 = out_woready_133 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_4 = _out_backSel_T[4]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_134 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_4 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_134 = out_woready_134 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_47 = _out_backSel_T[47]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_135 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_47 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_135 = out_woready_135 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_15 = _out_backSel_T[15]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_136 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_15 &
    out_bindex == 24'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_136 = out_woready_136 & out_womask_32; // @[RegisterRouter.scala 83:24]
  wire  _GEN_2178 = 9'h141 == out_oindex ? _out_T_101 : 1'h1; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2179 = 9'h140 == out_oindex ? _out_T_101 : _GEN_2178; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2180 = 9'h101 == out_oindex ? _out_T_101 : _GEN_2179; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2181 = 9'h100 == out_oindex ? _out_T_101 : _GEN_2180; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2182 = 9'ha1 == out_oindex ? _out_T_101 : _GEN_2181; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2183 = 9'ha0 == out_oindex ? _out_T_101 : _GEN_2182; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2184 = 9'h81 == out_oindex ? _out_T_101 : _GEN_2183; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2185 = 9'h80 == out_oindex ? _out_T_101 : _GEN_2184; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2186 = 9'h41 == out_oindex ? _out_T_101 : _GEN_2185; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2187 = 9'h40 == out_oindex ? _out_T_101 : _GEN_2186; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2188 = 9'h38 == out_oindex ? _out_T_101 : _GEN_2187; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2189 = 9'h37 == out_oindex ? _out_T_101 : _GEN_2188; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2190 = 9'h36 == out_oindex ? _out_T_101 : _GEN_2189; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2191 = 9'h35 == out_oindex ? _out_T_101 : _GEN_2190; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2192 = 9'h34 == out_oindex ? _out_T_101 : _GEN_2191; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2193 = 9'h33 == out_oindex ? _out_T_101 : _GEN_2192; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2194 = 9'h32 == out_oindex ? _out_T_101 : _GEN_2193; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2195 = 9'h31 == out_oindex ? _out_T_101 : _GEN_2194; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2196 = 9'h30 == out_oindex ? _out_T_101 : _GEN_2195; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2197 = 9'h2f == out_oindex ? _out_T_101 : _GEN_2196; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2198 = 9'h2e == out_oindex ? _out_T_101 : _GEN_2197; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2199 = 9'h2d == out_oindex ? _out_T_101 : _GEN_2198; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2200 = 9'h2c == out_oindex ? _out_T_101 : _GEN_2199; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2201 = 9'h2b == out_oindex ? _out_T_101 : _GEN_2200; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2202 = 9'h2a == out_oindex ? _out_T_101 : _GEN_2201; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2203 = 9'h29 == out_oindex ? _out_T_101 : _GEN_2202; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2204 = 9'h28 == out_oindex ? _out_T_101 : _GEN_2203; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2205 = 9'h27 == out_oindex ? _out_T_101 : _GEN_2204; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2206 = 9'h26 == out_oindex ? _out_T_101 : _GEN_2205; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2207 = 9'h25 == out_oindex ? _out_T_101 : _GEN_2206; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2208 = 9'h24 == out_oindex ? _out_T_101 : _GEN_2207; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2209 = 9'h23 == out_oindex ? _out_T_101 : _GEN_2208; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2210 = 9'h22 == out_oindex ? _out_T_101 : _GEN_2209; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2211 = 9'h21 == out_oindex ? _out_T_101 : _GEN_2210; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2212 = 9'h20 == out_oindex ? _out_T_101 : _GEN_2211; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2213 = 9'h1f == out_oindex ? _out_T_101 : _GEN_2212; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2214 = 9'h1e == out_oindex ? _out_T_101 : _GEN_2213; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2215 = 9'h1d == out_oindex ? _out_T_101 : _GEN_2214; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2216 = 9'h1c == out_oindex ? _out_T_101 : _GEN_2215; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2217 = 9'h1b == out_oindex ? _out_T_101 : _GEN_2216; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2218 = 9'h1a == out_oindex ? _out_T_101 : _GEN_2217; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2219 = 9'h19 == out_oindex ? _out_T_101 : _GEN_2218; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2220 = 9'h18 == out_oindex ? _out_T_101 : _GEN_2219; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2221 = 9'h17 == out_oindex ? _out_T_101 : _GEN_2220; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2222 = 9'h16 == out_oindex ? _out_T_101 : _GEN_2221; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2223 = 9'h15 == out_oindex ? _out_T_101 : _GEN_2222; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2224 = 9'h14 == out_oindex ? _out_T_101 : _GEN_2223; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2225 = 9'h13 == out_oindex ? _out_T_101 : _GEN_2224; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2226 = 9'h12 == out_oindex ? _out_T_101 : _GEN_2225; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2227 = 9'h11 == out_oindex ? _out_T_101 : _GEN_2226; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2228 = 9'h10 == out_oindex ? _out_T_101 : _GEN_2227; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2229 = 9'hf == out_oindex ? _out_T_101 : _GEN_2228; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2230 = 9'he == out_oindex ? _out_T_101 : _GEN_2229; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2231 = 9'hd == out_oindex ? _out_T_101 : _GEN_2230; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2232 = 9'hc == out_oindex ? _out_T_101 : _GEN_2231; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2233 = 9'hb == out_oindex ? _out_T_101 : _GEN_2232; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2234 = 9'ha == out_oindex ? _out_T_101 : _GEN_2233; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2235 = 9'h9 == out_oindex ? _out_T_101 : _GEN_2234; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2236 = 9'h8 == out_oindex ? _out_T_101 : _GEN_2235; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2237 = 9'h7 == out_oindex ? _out_T_101 : _GEN_2236; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2238 = 9'h6 == out_oindex ? _out_T_101 : _GEN_2237; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2239 = 9'h5 == out_oindex ? _out_T_101 : _GEN_2238; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2240 = 9'h4 == out_oindex ? _out_T_101 : _GEN_2239; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2241 = 9'h3 == out_oindex ? _out_T_101 : _GEN_2240; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_2242 = 9'h2 == out_oindex ? _out_T_101 : _GEN_2241; // @[MuxLiteral.scala 53:{26,32}]
  wire  out_out_bits_data_out = 9'h1 == out_oindex ? _out_T_101 : _GEN_2242; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2244 = 9'h141 == out_oindex ? _out_T_1327 : 32'h0; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2245 = 9'h140 == out_oindex ? _out_T_848 : _GEN_2244; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2246 = 9'h101 == out_oindex ? _out_T_610 : _GEN_2245; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2247 = 9'h100 == out_oindex ? _out_T_868 : _GEN_2246; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2248 = 9'ha1 == out_oindex ? {{7'd0}, out_prepend_70} : _GEN_2247; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2249 = 9'ha0 == out_oindex ? out_prepend_37 : _GEN_2248; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2250 = 9'h81 == out_oindex ? {{7'd0}, out_prepend_33} : _GEN_2249; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2251 = 9'h80 == out_oindex ? out_prepend_43 : _GEN_2250; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2252 = 9'h41 == out_oindex ? {{7'd0}, out_prepend_67} : _GEN_2251; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2253 = 9'h40 == out_oindex ? out_prepend_30 : _GEN_2252; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2254 = 9'h38 == out_oindex ? {{29'd0}, priority_55} : _GEN_2253; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2255 = 9'h37 == out_oindex ? {{29'd0}, priority_54} : _GEN_2254; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2256 = 9'h36 == out_oindex ? {{29'd0}, priority_53} : _GEN_2255; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2257 = 9'h35 == out_oindex ? {{29'd0}, priority_52} : _GEN_2256; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2258 = 9'h34 == out_oindex ? {{29'd0}, priority_51} : _GEN_2257; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2259 = 9'h33 == out_oindex ? {{29'd0}, priority_50} : _GEN_2258; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2260 = 9'h32 == out_oindex ? {{29'd0}, priority_49} : _GEN_2259; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2261 = 9'h31 == out_oindex ? {{29'd0}, priority_48} : _GEN_2260; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2262 = 9'h30 == out_oindex ? {{29'd0}, priority_47} : _GEN_2261; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2263 = 9'h2f == out_oindex ? {{29'd0}, priority_46} : _GEN_2262; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2264 = 9'h2e == out_oindex ? {{29'd0}, priority_45} : _GEN_2263; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2265 = 9'h2d == out_oindex ? {{29'd0}, priority_44} : _GEN_2264; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2266 = 9'h2c == out_oindex ? {{29'd0}, priority_43} : _GEN_2265; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2267 = 9'h2b == out_oindex ? {{29'd0}, priority_42} : _GEN_2266; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2268 = 9'h2a == out_oindex ? {{29'd0}, priority_41} : _GEN_2267; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2269 = 9'h29 == out_oindex ? {{29'd0}, priority_40} : _GEN_2268; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2270 = 9'h28 == out_oindex ? {{29'd0}, priority_39} : _GEN_2269; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2271 = 9'h27 == out_oindex ? {{29'd0}, priority_38} : _GEN_2270; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2272 = 9'h26 == out_oindex ? {{29'd0}, priority_37} : _GEN_2271; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2273 = 9'h25 == out_oindex ? {{29'd0}, priority_36} : _GEN_2272; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2274 = 9'h24 == out_oindex ? {{29'd0}, priority_35} : _GEN_2273; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2275 = 9'h23 == out_oindex ? {{29'd0}, priority_34} : _GEN_2274; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2276 = 9'h22 == out_oindex ? {{29'd0}, priority_33} : _GEN_2275; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2277 = 9'h21 == out_oindex ? {{29'd0}, priority_32} : _GEN_2276; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2278 = 9'h20 == out_oindex ? {{29'd0}, priority_31} : _GEN_2277; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2279 = 9'h1f == out_oindex ? {{29'd0}, priority_30} : _GEN_2278; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2280 = 9'h1e == out_oindex ? {{29'd0}, priority_29} : _GEN_2279; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2281 = 9'h1d == out_oindex ? {{29'd0}, priority_28} : _GEN_2280; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2282 = 9'h1c == out_oindex ? {{29'd0}, priority_27} : _GEN_2281; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2283 = 9'h1b == out_oindex ? {{29'd0}, priority_26} : _GEN_2282; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2284 = 9'h1a == out_oindex ? {{29'd0}, priority_25} : _GEN_2283; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2285 = 9'h19 == out_oindex ? {{29'd0}, priority_24} : _GEN_2284; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2286 = 9'h18 == out_oindex ? {{29'd0}, priority_23} : _GEN_2285; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2287 = 9'h17 == out_oindex ? {{29'd0}, priority_22} : _GEN_2286; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2288 = 9'h16 == out_oindex ? {{29'd0}, priority_21} : _GEN_2287; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2289 = 9'h15 == out_oindex ? {{29'd0}, priority_20} : _GEN_2288; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2290 = 9'h14 == out_oindex ? {{29'd0}, priority_19} : _GEN_2289; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2291 = 9'h13 == out_oindex ? {{29'd0}, priority_18} : _GEN_2290; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2292 = 9'h12 == out_oindex ? {{29'd0}, priority_17} : _GEN_2291; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2293 = 9'h11 == out_oindex ? {{29'd0}, priority_16} : _GEN_2292; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2294 = 9'h10 == out_oindex ? {{29'd0}, priority_15} : _GEN_2293; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2295 = 9'hf == out_oindex ? {{29'd0}, priority_14} : _GEN_2294; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2296 = 9'he == out_oindex ? {{29'd0}, priority_13} : _GEN_2295; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2297 = 9'hd == out_oindex ? {{29'd0}, priority_12} : _GEN_2296; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2298 = 9'hc == out_oindex ? {{29'd0}, priority_11} : _GEN_2297; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2299 = 9'hb == out_oindex ? {{29'd0}, priority_10} : _GEN_2298; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2300 = 9'ha == out_oindex ? {{29'd0}, priority_9} : _GEN_2299; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2301 = 9'h9 == out_oindex ? {{29'd0}, priority_8} : _GEN_2300; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2302 = 9'h8 == out_oindex ? {{29'd0}, priority_7} : _GEN_2301; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2303 = 9'h7 == out_oindex ? {{29'd0}, priority_6} : _GEN_2302; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2304 = 9'h6 == out_oindex ? {{29'd0}, priority_5} : _GEN_2303; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2305 = 9'h5 == out_oindex ? {{29'd0}, priority_4} : _GEN_2304; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2306 = 9'h4 == out_oindex ? {{29'd0}, priority_3} : _GEN_2305; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2307 = 9'h3 == out_oindex ? {{29'd0}, priority_2} : _GEN_2306; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_2308 = 9'h2 == out_oindex ? {{29'd0}, priority_1} : _GEN_2307; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] out_out_bits_data_out_1 = 9'h1 == out_oindex ? {{29'd0}, priority_0} : _GEN_2308; // @[MuxLiteral.scala 53:{26,32}]
  wire  out_bits_read = out_back_io_deq_bits_read; // @[RegisterRouter.scala 83:{24,24}]
  TLMonitor_46 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  LevelGateway gateways_gateway ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_clock),
    .reset(gateways_gateway_reset),
    .io_interrupt(gateways_gateway_io_interrupt),
    .io_plic_valid(gateways_gateway_io_plic_valid),
    .io_plic_ready(gateways_gateway_io_plic_ready),
    .io_plic_complete(gateways_gateway_io_plic_complete)
  );
  LevelGateway gateways_gateway_1 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_1_clock),
    .reset(gateways_gateway_1_reset),
    .io_interrupt(gateways_gateway_1_io_interrupt),
    .io_plic_valid(gateways_gateway_1_io_plic_valid),
    .io_plic_ready(gateways_gateway_1_io_plic_ready),
    .io_plic_complete(gateways_gateway_1_io_plic_complete)
  );
  LevelGateway gateways_gateway_2 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_2_clock),
    .reset(gateways_gateway_2_reset),
    .io_interrupt(gateways_gateway_2_io_interrupt),
    .io_plic_valid(gateways_gateway_2_io_plic_valid),
    .io_plic_ready(gateways_gateway_2_io_plic_ready),
    .io_plic_complete(gateways_gateway_2_io_plic_complete)
  );
  LevelGateway gateways_gateway_3 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_3_clock),
    .reset(gateways_gateway_3_reset),
    .io_interrupt(gateways_gateway_3_io_interrupt),
    .io_plic_valid(gateways_gateway_3_io_plic_valid),
    .io_plic_ready(gateways_gateway_3_io_plic_ready),
    .io_plic_complete(gateways_gateway_3_io_plic_complete)
  );
  LevelGateway gateways_gateway_4 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_4_clock),
    .reset(gateways_gateway_4_reset),
    .io_interrupt(gateways_gateway_4_io_interrupt),
    .io_plic_valid(gateways_gateway_4_io_plic_valid),
    .io_plic_ready(gateways_gateway_4_io_plic_ready),
    .io_plic_complete(gateways_gateway_4_io_plic_complete)
  );
  LevelGateway gateways_gateway_5 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_5_clock),
    .reset(gateways_gateway_5_reset),
    .io_interrupt(gateways_gateway_5_io_interrupt),
    .io_plic_valid(gateways_gateway_5_io_plic_valid),
    .io_plic_ready(gateways_gateway_5_io_plic_ready),
    .io_plic_complete(gateways_gateway_5_io_plic_complete)
  );
  LevelGateway gateways_gateway_6 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_6_clock),
    .reset(gateways_gateway_6_reset),
    .io_interrupt(gateways_gateway_6_io_interrupt),
    .io_plic_valid(gateways_gateway_6_io_plic_valid),
    .io_plic_ready(gateways_gateway_6_io_plic_ready),
    .io_plic_complete(gateways_gateway_6_io_plic_complete)
  );
  LevelGateway gateways_gateway_7 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_7_clock),
    .reset(gateways_gateway_7_reset),
    .io_interrupt(gateways_gateway_7_io_interrupt),
    .io_plic_valid(gateways_gateway_7_io_plic_valid),
    .io_plic_ready(gateways_gateway_7_io_plic_ready),
    .io_plic_complete(gateways_gateway_7_io_plic_complete)
  );
  LevelGateway gateways_gateway_8 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_8_clock),
    .reset(gateways_gateway_8_reset),
    .io_interrupt(gateways_gateway_8_io_interrupt),
    .io_plic_valid(gateways_gateway_8_io_plic_valid),
    .io_plic_ready(gateways_gateway_8_io_plic_ready),
    .io_plic_complete(gateways_gateway_8_io_plic_complete)
  );
  LevelGateway gateways_gateway_9 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_9_clock),
    .reset(gateways_gateway_9_reset),
    .io_interrupt(gateways_gateway_9_io_interrupt),
    .io_plic_valid(gateways_gateway_9_io_plic_valid),
    .io_plic_ready(gateways_gateway_9_io_plic_ready),
    .io_plic_complete(gateways_gateway_9_io_plic_complete)
  );
  LevelGateway gateways_gateway_10 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_10_clock),
    .reset(gateways_gateway_10_reset),
    .io_interrupt(gateways_gateway_10_io_interrupt),
    .io_plic_valid(gateways_gateway_10_io_plic_valid),
    .io_plic_ready(gateways_gateway_10_io_plic_ready),
    .io_plic_complete(gateways_gateway_10_io_plic_complete)
  );
  LevelGateway gateways_gateway_11 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_11_clock),
    .reset(gateways_gateway_11_reset),
    .io_interrupt(gateways_gateway_11_io_interrupt),
    .io_plic_valid(gateways_gateway_11_io_plic_valid),
    .io_plic_ready(gateways_gateway_11_io_plic_ready),
    .io_plic_complete(gateways_gateway_11_io_plic_complete)
  );
  LevelGateway gateways_gateway_12 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_12_clock),
    .reset(gateways_gateway_12_reset),
    .io_interrupt(gateways_gateway_12_io_interrupt),
    .io_plic_valid(gateways_gateway_12_io_plic_valid),
    .io_plic_ready(gateways_gateway_12_io_plic_ready),
    .io_plic_complete(gateways_gateway_12_io_plic_complete)
  );
  LevelGateway gateways_gateway_13 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_13_clock),
    .reset(gateways_gateway_13_reset),
    .io_interrupt(gateways_gateway_13_io_interrupt),
    .io_plic_valid(gateways_gateway_13_io_plic_valid),
    .io_plic_ready(gateways_gateway_13_io_plic_ready),
    .io_plic_complete(gateways_gateway_13_io_plic_complete)
  );
  LevelGateway gateways_gateway_14 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_14_clock),
    .reset(gateways_gateway_14_reset),
    .io_interrupt(gateways_gateway_14_io_interrupt),
    .io_plic_valid(gateways_gateway_14_io_plic_valid),
    .io_plic_ready(gateways_gateway_14_io_plic_ready),
    .io_plic_complete(gateways_gateway_14_io_plic_complete)
  );
  LevelGateway gateways_gateway_15 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_15_clock),
    .reset(gateways_gateway_15_reset),
    .io_interrupt(gateways_gateway_15_io_interrupt),
    .io_plic_valid(gateways_gateway_15_io_plic_valid),
    .io_plic_ready(gateways_gateway_15_io_plic_ready),
    .io_plic_complete(gateways_gateway_15_io_plic_complete)
  );
  LevelGateway gateways_gateway_16 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_16_clock),
    .reset(gateways_gateway_16_reset),
    .io_interrupt(gateways_gateway_16_io_interrupt),
    .io_plic_valid(gateways_gateway_16_io_plic_valid),
    .io_plic_ready(gateways_gateway_16_io_plic_ready),
    .io_plic_complete(gateways_gateway_16_io_plic_complete)
  );
  LevelGateway gateways_gateway_17 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_17_clock),
    .reset(gateways_gateway_17_reset),
    .io_interrupt(gateways_gateway_17_io_interrupt),
    .io_plic_valid(gateways_gateway_17_io_plic_valid),
    .io_plic_ready(gateways_gateway_17_io_plic_ready),
    .io_plic_complete(gateways_gateway_17_io_plic_complete)
  );
  LevelGateway gateways_gateway_18 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_18_clock),
    .reset(gateways_gateway_18_reset),
    .io_interrupt(gateways_gateway_18_io_interrupt),
    .io_plic_valid(gateways_gateway_18_io_plic_valid),
    .io_plic_ready(gateways_gateway_18_io_plic_ready),
    .io_plic_complete(gateways_gateway_18_io_plic_complete)
  );
  LevelGateway gateways_gateway_19 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_19_clock),
    .reset(gateways_gateway_19_reset),
    .io_interrupt(gateways_gateway_19_io_interrupt),
    .io_plic_valid(gateways_gateway_19_io_plic_valid),
    .io_plic_ready(gateways_gateway_19_io_plic_ready),
    .io_plic_complete(gateways_gateway_19_io_plic_complete)
  );
  LevelGateway gateways_gateway_20 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_20_clock),
    .reset(gateways_gateway_20_reset),
    .io_interrupt(gateways_gateway_20_io_interrupt),
    .io_plic_valid(gateways_gateway_20_io_plic_valid),
    .io_plic_ready(gateways_gateway_20_io_plic_ready),
    .io_plic_complete(gateways_gateway_20_io_plic_complete)
  );
  LevelGateway gateways_gateway_21 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_21_clock),
    .reset(gateways_gateway_21_reset),
    .io_interrupt(gateways_gateway_21_io_interrupt),
    .io_plic_valid(gateways_gateway_21_io_plic_valid),
    .io_plic_ready(gateways_gateway_21_io_plic_ready),
    .io_plic_complete(gateways_gateway_21_io_plic_complete)
  );
  LevelGateway gateways_gateway_22 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_22_clock),
    .reset(gateways_gateway_22_reset),
    .io_interrupt(gateways_gateway_22_io_interrupt),
    .io_plic_valid(gateways_gateway_22_io_plic_valid),
    .io_plic_ready(gateways_gateway_22_io_plic_ready),
    .io_plic_complete(gateways_gateway_22_io_plic_complete)
  );
  LevelGateway gateways_gateway_23 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_23_clock),
    .reset(gateways_gateway_23_reset),
    .io_interrupt(gateways_gateway_23_io_interrupt),
    .io_plic_valid(gateways_gateway_23_io_plic_valid),
    .io_plic_ready(gateways_gateway_23_io_plic_ready),
    .io_plic_complete(gateways_gateway_23_io_plic_complete)
  );
  LevelGateway gateways_gateway_24 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_24_clock),
    .reset(gateways_gateway_24_reset),
    .io_interrupt(gateways_gateway_24_io_interrupt),
    .io_plic_valid(gateways_gateway_24_io_plic_valid),
    .io_plic_ready(gateways_gateway_24_io_plic_ready),
    .io_plic_complete(gateways_gateway_24_io_plic_complete)
  );
  LevelGateway gateways_gateway_25 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_25_clock),
    .reset(gateways_gateway_25_reset),
    .io_interrupt(gateways_gateway_25_io_interrupt),
    .io_plic_valid(gateways_gateway_25_io_plic_valid),
    .io_plic_ready(gateways_gateway_25_io_plic_ready),
    .io_plic_complete(gateways_gateway_25_io_plic_complete)
  );
  LevelGateway gateways_gateway_26 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_26_clock),
    .reset(gateways_gateway_26_reset),
    .io_interrupt(gateways_gateway_26_io_interrupt),
    .io_plic_valid(gateways_gateway_26_io_plic_valid),
    .io_plic_ready(gateways_gateway_26_io_plic_ready),
    .io_plic_complete(gateways_gateway_26_io_plic_complete)
  );
  LevelGateway gateways_gateway_27 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_27_clock),
    .reset(gateways_gateway_27_reset),
    .io_interrupt(gateways_gateway_27_io_interrupt),
    .io_plic_valid(gateways_gateway_27_io_plic_valid),
    .io_plic_ready(gateways_gateway_27_io_plic_ready),
    .io_plic_complete(gateways_gateway_27_io_plic_complete)
  );
  LevelGateway gateways_gateway_28 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_28_clock),
    .reset(gateways_gateway_28_reset),
    .io_interrupt(gateways_gateway_28_io_interrupt),
    .io_plic_valid(gateways_gateway_28_io_plic_valid),
    .io_plic_ready(gateways_gateway_28_io_plic_ready),
    .io_plic_complete(gateways_gateway_28_io_plic_complete)
  );
  LevelGateway gateways_gateway_29 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_29_clock),
    .reset(gateways_gateway_29_reset),
    .io_interrupt(gateways_gateway_29_io_interrupt),
    .io_plic_valid(gateways_gateway_29_io_plic_valid),
    .io_plic_ready(gateways_gateway_29_io_plic_ready),
    .io_plic_complete(gateways_gateway_29_io_plic_complete)
  );
  LevelGateway gateways_gateway_30 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_30_clock),
    .reset(gateways_gateway_30_reset),
    .io_interrupt(gateways_gateway_30_io_interrupt),
    .io_plic_valid(gateways_gateway_30_io_plic_valid),
    .io_plic_ready(gateways_gateway_30_io_plic_ready),
    .io_plic_complete(gateways_gateway_30_io_plic_complete)
  );
  LevelGateway gateways_gateway_31 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_31_clock),
    .reset(gateways_gateway_31_reset),
    .io_interrupt(gateways_gateway_31_io_interrupt),
    .io_plic_valid(gateways_gateway_31_io_plic_valid),
    .io_plic_ready(gateways_gateway_31_io_plic_ready),
    .io_plic_complete(gateways_gateway_31_io_plic_complete)
  );
  LevelGateway gateways_gateway_32 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_32_clock),
    .reset(gateways_gateway_32_reset),
    .io_interrupt(gateways_gateway_32_io_interrupt),
    .io_plic_valid(gateways_gateway_32_io_plic_valid),
    .io_plic_ready(gateways_gateway_32_io_plic_ready),
    .io_plic_complete(gateways_gateway_32_io_plic_complete)
  );
  LevelGateway gateways_gateway_33 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_33_clock),
    .reset(gateways_gateway_33_reset),
    .io_interrupt(gateways_gateway_33_io_interrupt),
    .io_plic_valid(gateways_gateway_33_io_plic_valid),
    .io_plic_ready(gateways_gateway_33_io_plic_ready),
    .io_plic_complete(gateways_gateway_33_io_plic_complete)
  );
  LevelGateway gateways_gateway_34 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_34_clock),
    .reset(gateways_gateway_34_reset),
    .io_interrupt(gateways_gateway_34_io_interrupt),
    .io_plic_valid(gateways_gateway_34_io_plic_valid),
    .io_plic_ready(gateways_gateway_34_io_plic_ready),
    .io_plic_complete(gateways_gateway_34_io_plic_complete)
  );
  LevelGateway gateways_gateway_35 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_35_clock),
    .reset(gateways_gateway_35_reset),
    .io_interrupt(gateways_gateway_35_io_interrupt),
    .io_plic_valid(gateways_gateway_35_io_plic_valid),
    .io_plic_ready(gateways_gateway_35_io_plic_ready),
    .io_plic_complete(gateways_gateway_35_io_plic_complete)
  );
  LevelGateway gateways_gateway_36 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_36_clock),
    .reset(gateways_gateway_36_reset),
    .io_interrupt(gateways_gateway_36_io_interrupt),
    .io_plic_valid(gateways_gateway_36_io_plic_valid),
    .io_plic_ready(gateways_gateway_36_io_plic_ready),
    .io_plic_complete(gateways_gateway_36_io_plic_complete)
  );
  LevelGateway gateways_gateway_37 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_37_clock),
    .reset(gateways_gateway_37_reset),
    .io_interrupt(gateways_gateway_37_io_interrupt),
    .io_plic_valid(gateways_gateway_37_io_plic_valid),
    .io_plic_ready(gateways_gateway_37_io_plic_ready),
    .io_plic_complete(gateways_gateway_37_io_plic_complete)
  );
  LevelGateway gateways_gateway_38 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_38_clock),
    .reset(gateways_gateway_38_reset),
    .io_interrupt(gateways_gateway_38_io_interrupt),
    .io_plic_valid(gateways_gateway_38_io_plic_valid),
    .io_plic_ready(gateways_gateway_38_io_plic_ready),
    .io_plic_complete(gateways_gateway_38_io_plic_complete)
  );
  LevelGateway gateways_gateway_39 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_39_clock),
    .reset(gateways_gateway_39_reset),
    .io_interrupt(gateways_gateway_39_io_interrupt),
    .io_plic_valid(gateways_gateway_39_io_plic_valid),
    .io_plic_ready(gateways_gateway_39_io_plic_ready),
    .io_plic_complete(gateways_gateway_39_io_plic_complete)
  );
  LevelGateway gateways_gateway_40 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_40_clock),
    .reset(gateways_gateway_40_reset),
    .io_interrupt(gateways_gateway_40_io_interrupt),
    .io_plic_valid(gateways_gateway_40_io_plic_valid),
    .io_plic_ready(gateways_gateway_40_io_plic_ready),
    .io_plic_complete(gateways_gateway_40_io_plic_complete)
  );
  LevelGateway gateways_gateway_41 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_41_clock),
    .reset(gateways_gateway_41_reset),
    .io_interrupt(gateways_gateway_41_io_interrupt),
    .io_plic_valid(gateways_gateway_41_io_plic_valid),
    .io_plic_ready(gateways_gateway_41_io_plic_ready),
    .io_plic_complete(gateways_gateway_41_io_plic_complete)
  );
  LevelGateway gateways_gateway_42 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_42_clock),
    .reset(gateways_gateway_42_reset),
    .io_interrupt(gateways_gateway_42_io_interrupt),
    .io_plic_valid(gateways_gateway_42_io_plic_valid),
    .io_plic_ready(gateways_gateway_42_io_plic_ready),
    .io_plic_complete(gateways_gateway_42_io_plic_complete)
  );
  LevelGateway gateways_gateway_43 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_43_clock),
    .reset(gateways_gateway_43_reset),
    .io_interrupt(gateways_gateway_43_io_interrupt),
    .io_plic_valid(gateways_gateway_43_io_plic_valid),
    .io_plic_ready(gateways_gateway_43_io_plic_ready),
    .io_plic_complete(gateways_gateway_43_io_plic_complete)
  );
  LevelGateway gateways_gateway_44 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_44_clock),
    .reset(gateways_gateway_44_reset),
    .io_interrupt(gateways_gateway_44_io_interrupt),
    .io_plic_valid(gateways_gateway_44_io_plic_valid),
    .io_plic_ready(gateways_gateway_44_io_plic_ready),
    .io_plic_complete(gateways_gateway_44_io_plic_complete)
  );
  LevelGateway gateways_gateway_45 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_45_clock),
    .reset(gateways_gateway_45_reset),
    .io_interrupt(gateways_gateway_45_io_interrupt),
    .io_plic_valid(gateways_gateway_45_io_plic_valid),
    .io_plic_ready(gateways_gateway_45_io_plic_ready),
    .io_plic_complete(gateways_gateway_45_io_plic_complete)
  );
  LevelGateway gateways_gateway_46 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_46_clock),
    .reset(gateways_gateway_46_reset),
    .io_interrupt(gateways_gateway_46_io_interrupt),
    .io_plic_valid(gateways_gateway_46_io_plic_valid),
    .io_plic_ready(gateways_gateway_46_io_plic_ready),
    .io_plic_complete(gateways_gateway_46_io_plic_complete)
  );
  LevelGateway gateways_gateway_47 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_47_clock),
    .reset(gateways_gateway_47_reset),
    .io_interrupt(gateways_gateway_47_io_interrupt),
    .io_plic_valid(gateways_gateway_47_io_plic_valid),
    .io_plic_ready(gateways_gateway_47_io_plic_ready),
    .io_plic_complete(gateways_gateway_47_io_plic_complete)
  );
  LevelGateway gateways_gateway_48 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_48_clock),
    .reset(gateways_gateway_48_reset),
    .io_interrupt(gateways_gateway_48_io_interrupt),
    .io_plic_valid(gateways_gateway_48_io_plic_valid),
    .io_plic_ready(gateways_gateway_48_io_plic_ready),
    .io_plic_complete(gateways_gateway_48_io_plic_complete)
  );
  LevelGateway gateways_gateway_49 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_49_clock),
    .reset(gateways_gateway_49_reset),
    .io_interrupt(gateways_gateway_49_io_interrupt),
    .io_plic_valid(gateways_gateway_49_io_plic_valid),
    .io_plic_ready(gateways_gateway_49_io_plic_ready),
    .io_plic_complete(gateways_gateway_49_io_plic_complete)
  );
  LevelGateway gateways_gateway_50 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_50_clock),
    .reset(gateways_gateway_50_reset),
    .io_interrupt(gateways_gateway_50_io_interrupt),
    .io_plic_valid(gateways_gateway_50_io_plic_valid),
    .io_plic_ready(gateways_gateway_50_io_plic_ready),
    .io_plic_complete(gateways_gateway_50_io_plic_complete)
  );
  LevelGateway gateways_gateway_51 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_51_clock),
    .reset(gateways_gateway_51_reset),
    .io_interrupt(gateways_gateway_51_io_interrupt),
    .io_plic_valid(gateways_gateway_51_io_plic_valid),
    .io_plic_ready(gateways_gateway_51_io_plic_ready),
    .io_plic_complete(gateways_gateway_51_io_plic_complete)
  );
  LevelGateway gateways_gateway_52 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_52_clock),
    .reset(gateways_gateway_52_reset),
    .io_interrupt(gateways_gateway_52_io_interrupt),
    .io_plic_valid(gateways_gateway_52_io_plic_valid),
    .io_plic_ready(gateways_gateway_52_io_plic_ready),
    .io_plic_complete(gateways_gateway_52_io_plic_complete)
  );
  LevelGateway gateways_gateway_53 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_53_clock),
    .reset(gateways_gateway_53_reset),
    .io_interrupt(gateways_gateway_53_io_interrupt),
    .io_plic_valid(gateways_gateway_53_io_plic_valid),
    .io_plic_ready(gateways_gateway_53_io_plic_ready),
    .io_plic_complete(gateways_gateway_53_io_plic_complete)
  );
  LevelGateway gateways_gateway_54 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_54_clock),
    .reset(gateways_gateway_54_reset),
    .io_interrupt(gateways_gateway_54_io_interrupt),
    .io_plic_valid(gateways_gateway_54_io_plic_valid),
    .io_plic_ready(gateways_gateway_54_io_plic_ready),
    .io_plic_complete(gateways_gateway_54_io_plic_complete)
  );
  LevelGateway gateways_gateway_55 ( // @[Plic.scala 156:27]
    .clock(gateways_gateway_55_clock),
    .reset(gateways_gateway_55_reset),
    .io_interrupt(gateways_gateway_55_io_interrupt),
    .io_plic_valid(gateways_gateway_55_io_plic_valid),
    .io_plic_ready(gateways_gateway_55_io_plic_ready),
    .io_plic_complete(gateways_gateway_55_io_plic_complete)
  );
  PLICFanIn fanin ( // @[Plic.scala 184:25]
    .io_prio_0(fanin_io_prio_0),
    .io_prio_1(fanin_io_prio_1),
    .io_prio_2(fanin_io_prio_2),
    .io_prio_3(fanin_io_prio_3),
    .io_prio_4(fanin_io_prio_4),
    .io_prio_5(fanin_io_prio_5),
    .io_prio_6(fanin_io_prio_6),
    .io_prio_7(fanin_io_prio_7),
    .io_prio_8(fanin_io_prio_8),
    .io_prio_9(fanin_io_prio_9),
    .io_prio_10(fanin_io_prio_10),
    .io_prio_11(fanin_io_prio_11),
    .io_prio_12(fanin_io_prio_12),
    .io_prio_13(fanin_io_prio_13),
    .io_prio_14(fanin_io_prio_14),
    .io_prio_15(fanin_io_prio_15),
    .io_prio_16(fanin_io_prio_16),
    .io_prio_17(fanin_io_prio_17),
    .io_prio_18(fanin_io_prio_18),
    .io_prio_19(fanin_io_prio_19),
    .io_prio_20(fanin_io_prio_20),
    .io_prio_21(fanin_io_prio_21),
    .io_prio_22(fanin_io_prio_22),
    .io_prio_23(fanin_io_prio_23),
    .io_prio_24(fanin_io_prio_24),
    .io_prio_25(fanin_io_prio_25),
    .io_prio_26(fanin_io_prio_26),
    .io_prio_27(fanin_io_prio_27),
    .io_prio_28(fanin_io_prio_28),
    .io_prio_29(fanin_io_prio_29),
    .io_prio_30(fanin_io_prio_30),
    .io_prio_31(fanin_io_prio_31),
    .io_prio_32(fanin_io_prio_32),
    .io_prio_33(fanin_io_prio_33),
    .io_prio_34(fanin_io_prio_34),
    .io_prio_35(fanin_io_prio_35),
    .io_prio_36(fanin_io_prio_36),
    .io_prio_37(fanin_io_prio_37),
    .io_prio_38(fanin_io_prio_38),
    .io_prio_39(fanin_io_prio_39),
    .io_prio_40(fanin_io_prio_40),
    .io_prio_41(fanin_io_prio_41),
    .io_prio_42(fanin_io_prio_42),
    .io_prio_43(fanin_io_prio_43),
    .io_prio_44(fanin_io_prio_44),
    .io_prio_45(fanin_io_prio_45),
    .io_prio_46(fanin_io_prio_46),
    .io_prio_47(fanin_io_prio_47),
    .io_prio_48(fanin_io_prio_48),
    .io_prio_49(fanin_io_prio_49),
    .io_prio_50(fanin_io_prio_50),
    .io_prio_51(fanin_io_prio_51),
    .io_prio_52(fanin_io_prio_52),
    .io_prio_53(fanin_io_prio_53),
    .io_prio_54(fanin_io_prio_54),
    .io_prio_55(fanin_io_prio_55),
    .io_ip(fanin_io_ip),
    .io_dev(fanin_io_dev),
    .io_max(fanin_io_max)
  );
  PLICFanIn fanin_1 ( // @[Plic.scala 184:25]
    .io_prio_0(fanin_1_io_prio_0),
    .io_prio_1(fanin_1_io_prio_1),
    .io_prio_2(fanin_1_io_prio_2),
    .io_prio_3(fanin_1_io_prio_3),
    .io_prio_4(fanin_1_io_prio_4),
    .io_prio_5(fanin_1_io_prio_5),
    .io_prio_6(fanin_1_io_prio_6),
    .io_prio_7(fanin_1_io_prio_7),
    .io_prio_8(fanin_1_io_prio_8),
    .io_prio_9(fanin_1_io_prio_9),
    .io_prio_10(fanin_1_io_prio_10),
    .io_prio_11(fanin_1_io_prio_11),
    .io_prio_12(fanin_1_io_prio_12),
    .io_prio_13(fanin_1_io_prio_13),
    .io_prio_14(fanin_1_io_prio_14),
    .io_prio_15(fanin_1_io_prio_15),
    .io_prio_16(fanin_1_io_prio_16),
    .io_prio_17(fanin_1_io_prio_17),
    .io_prio_18(fanin_1_io_prio_18),
    .io_prio_19(fanin_1_io_prio_19),
    .io_prio_20(fanin_1_io_prio_20),
    .io_prio_21(fanin_1_io_prio_21),
    .io_prio_22(fanin_1_io_prio_22),
    .io_prio_23(fanin_1_io_prio_23),
    .io_prio_24(fanin_1_io_prio_24),
    .io_prio_25(fanin_1_io_prio_25),
    .io_prio_26(fanin_1_io_prio_26),
    .io_prio_27(fanin_1_io_prio_27),
    .io_prio_28(fanin_1_io_prio_28),
    .io_prio_29(fanin_1_io_prio_29),
    .io_prio_30(fanin_1_io_prio_30),
    .io_prio_31(fanin_1_io_prio_31),
    .io_prio_32(fanin_1_io_prio_32),
    .io_prio_33(fanin_1_io_prio_33),
    .io_prio_34(fanin_1_io_prio_34),
    .io_prio_35(fanin_1_io_prio_35),
    .io_prio_36(fanin_1_io_prio_36),
    .io_prio_37(fanin_1_io_prio_37),
    .io_prio_38(fanin_1_io_prio_38),
    .io_prio_39(fanin_1_io_prio_39),
    .io_prio_40(fanin_1_io_prio_40),
    .io_prio_41(fanin_1_io_prio_41),
    .io_prio_42(fanin_1_io_prio_42),
    .io_prio_43(fanin_1_io_prio_43),
    .io_prio_44(fanin_1_io_prio_44),
    .io_prio_45(fanin_1_io_prio_45),
    .io_prio_46(fanin_1_io_prio_46),
    .io_prio_47(fanin_1_io_prio_47),
    .io_prio_48(fanin_1_io_prio_48),
    .io_prio_49(fanin_1_io_prio_49),
    .io_prio_50(fanin_1_io_prio_50),
    .io_prio_51(fanin_1_io_prio_51),
    .io_prio_52(fanin_1_io_prio_52),
    .io_prio_53(fanin_1_io_prio_53),
    .io_prio_54(fanin_1_io_prio_54),
    .io_prio_55(fanin_1_io_prio_55),
    .io_ip(fanin_1_io_ip),
    .io_dev(fanin_1_io_dev),
    .io_max(fanin_1_io_max)
  );
  Queue_22 out_back ( // @[Decoupled.scala 361:21]
    .clock(out_back_clock),
    .reset(out_back_reset),
    .io_enq_ready(out_back_io_enq_ready),
    .io_enq_valid(out_back_io_enq_valid),
    .io_enq_bits_read(out_back_io_enq_bits_read),
    .io_enq_bits_index(out_back_io_enq_bits_index),
    .io_enq_bits_data(out_back_io_enq_bits_data),
    .io_enq_bits_mask(out_back_io_enq_bits_mask),
    .io_enq_bits_extra_tlrr_extra_source(out_back_io_enq_bits_extra_tlrr_extra_source),
    .io_enq_bits_extra_tlrr_extra_size(out_back_io_enq_bits_extra_tlrr_extra_size),
    .io_deq_ready(out_back_io_deq_ready),
    .io_deq_valid(out_back_io_deq_valid),
    .io_deq_bits_read(out_back_io_deq_bits_read),
    .io_deq_bits_index(out_back_io_deq_bits_index),
    .io_deq_bits_data(out_back_io_deq_bits_data),
    .io_deq_bits_mask(out_back_io_deq_bits_mask),
    .io_deq_bits_extra_tlrr_extra_source(out_back_io_deq_bits_extra_tlrr_extra_source),
    .io_deq_bits_extra_tlrr_extra_size(out_back_io_deq_bits_extra_tlrr_extra_size)
  );
  assign auto_int_out_1_0 = bundleOut_1_0_REG > threshold_1; // @[Plic.scala 188:63]
  assign auto_int_out_0_0 = bundleOut_0_0_REG > threshold_0; // @[Plic.scala 188:63]
  assign auto_in_a_ready = out_back_io_enq_ready; // @[Decoupled.scala 365:17 RegisterRouter.scala 83:24]
  assign auto_in_d_valid = out_back_io_deq_valid; // @[RegisterRouter.scala 83:24]
  assign auto_in_d_bits_opcode = {{2'd0}, out_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign auto_in_d_bits_size = out_back_io_deq_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala 83:{24,24}]
  assign auto_in_d_bits_source = out_back_io_deq_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala 83:{24,24}]
  assign auto_in_d_bits_data = out_out_bits_data_out ? out_out_bits_data_out_1 : 32'h0; // @[RegisterRouter.scala 83:24]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = out_back_io_enq_ready; // @[Decoupled.scala 365:17 RegisterRouter.scala 83:24]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = out_back_io_deq_valid; // @[RegisterRouter.scala 83:24]
  assign monitor_io_in_d_bits_opcode = {{2'd0}, out_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign monitor_io_in_d_bits_size = out_back_io_deq_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala 83:{24,24}]
  assign monitor_io_in_d_bits_source = out_back_io_deq_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala 83:{24,24}]
  assign gateways_gateway_clock = clock;
  assign gateways_gateway_reset = reset;
  assign gateways_gateway_io_interrupt = auto_int_in_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_io_plic_ready = ~pending_0; // @[Plic.scala 250:18]
  assign gateways_gateway_io_plic_complete = completedDevs[1]; // @[Plic.scala 265:33]
  assign gateways_gateway_1_clock = clock;
  assign gateways_gateway_1_reset = reset;
  assign gateways_gateway_1_io_interrupt = auto_int_in_1; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_1_io_plic_ready = ~pending_1; // @[Plic.scala 250:18]
  assign gateways_gateway_1_io_plic_complete = completedDevs[2]; // @[Plic.scala 265:33]
  assign gateways_gateway_2_clock = clock;
  assign gateways_gateway_2_reset = reset;
  assign gateways_gateway_2_io_interrupt = auto_int_in_2; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_2_io_plic_ready = ~pending_2; // @[Plic.scala 250:18]
  assign gateways_gateway_2_io_plic_complete = completedDevs[3]; // @[Plic.scala 265:33]
  assign gateways_gateway_3_clock = clock;
  assign gateways_gateway_3_reset = reset;
  assign gateways_gateway_3_io_interrupt = auto_int_in_3; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_3_io_plic_ready = ~pending_3; // @[Plic.scala 250:18]
  assign gateways_gateway_3_io_plic_complete = completedDevs[4]; // @[Plic.scala 265:33]
  assign gateways_gateway_4_clock = clock;
  assign gateways_gateway_4_reset = reset;
  assign gateways_gateway_4_io_interrupt = auto_int_in_4; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_4_io_plic_ready = ~pending_4; // @[Plic.scala 250:18]
  assign gateways_gateway_4_io_plic_complete = completedDevs[5]; // @[Plic.scala 265:33]
  assign gateways_gateway_5_clock = clock;
  assign gateways_gateway_5_reset = reset;
  assign gateways_gateway_5_io_interrupt = auto_int_in_5; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_5_io_plic_ready = ~pending_5; // @[Plic.scala 250:18]
  assign gateways_gateway_5_io_plic_complete = completedDevs[6]; // @[Plic.scala 265:33]
  assign gateways_gateway_6_clock = clock;
  assign gateways_gateway_6_reset = reset;
  assign gateways_gateway_6_io_interrupt = auto_int_in_6; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_6_io_plic_ready = ~pending_6; // @[Plic.scala 250:18]
  assign gateways_gateway_6_io_plic_complete = completedDevs[7]; // @[Plic.scala 265:33]
  assign gateways_gateway_7_clock = clock;
  assign gateways_gateway_7_reset = reset;
  assign gateways_gateway_7_io_interrupt = auto_int_in_7; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_7_io_plic_ready = ~pending_7; // @[Plic.scala 250:18]
  assign gateways_gateway_7_io_plic_complete = completedDevs[8]; // @[Plic.scala 265:33]
  assign gateways_gateway_8_clock = clock;
  assign gateways_gateway_8_reset = reset;
  assign gateways_gateway_8_io_interrupt = auto_int_in_8; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_8_io_plic_ready = ~pending_8; // @[Plic.scala 250:18]
  assign gateways_gateway_8_io_plic_complete = completedDevs[9]; // @[Plic.scala 265:33]
  assign gateways_gateway_9_clock = clock;
  assign gateways_gateway_9_reset = reset;
  assign gateways_gateway_9_io_interrupt = auto_int_in_9; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_9_io_plic_ready = ~pending_9; // @[Plic.scala 250:18]
  assign gateways_gateway_9_io_plic_complete = completedDevs[10]; // @[Plic.scala 265:33]
  assign gateways_gateway_10_clock = clock;
  assign gateways_gateway_10_reset = reset;
  assign gateways_gateway_10_io_interrupt = auto_int_in_10; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_10_io_plic_ready = ~pending_10; // @[Plic.scala 250:18]
  assign gateways_gateway_10_io_plic_complete = completedDevs[11]; // @[Plic.scala 265:33]
  assign gateways_gateway_11_clock = clock;
  assign gateways_gateway_11_reset = reset;
  assign gateways_gateway_11_io_interrupt = auto_int_in_11; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_11_io_plic_ready = ~pending_11; // @[Plic.scala 250:18]
  assign gateways_gateway_11_io_plic_complete = completedDevs[12]; // @[Plic.scala 265:33]
  assign gateways_gateway_12_clock = clock;
  assign gateways_gateway_12_reset = reset;
  assign gateways_gateway_12_io_interrupt = auto_int_in_12; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_12_io_plic_ready = ~pending_12; // @[Plic.scala 250:18]
  assign gateways_gateway_12_io_plic_complete = completedDevs[13]; // @[Plic.scala 265:33]
  assign gateways_gateway_13_clock = clock;
  assign gateways_gateway_13_reset = reset;
  assign gateways_gateway_13_io_interrupt = auto_int_in_13; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_13_io_plic_ready = ~pending_13; // @[Plic.scala 250:18]
  assign gateways_gateway_13_io_plic_complete = completedDevs[14]; // @[Plic.scala 265:33]
  assign gateways_gateway_14_clock = clock;
  assign gateways_gateway_14_reset = reset;
  assign gateways_gateway_14_io_interrupt = auto_int_in_14; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_14_io_plic_ready = ~pending_14; // @[Plic.scala 250:18]
  assign gateways_gateway_14_io_plic_complete = completedDevs[15]; // @[Plic.scala 265:33]
  assign gateways_gateway_15_clock = clock;
  assign gateways_gateway_15_reset = reset;
  assign gateways_gateway_15_io_interrupt = auto_int_in_15; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_15_io_plic_ready = ~pending_15; // @[Plic.scala 250:18]
  assign gateways_gateway_15_io_plic_complete = completedDevs[16]; // @[Plic.scala 265:33]
  assign gateways_gateway_16_clock = clock;
  assign gateways_gateway_16_reset = reset;
  assign gateways_gateway_16_io_interrupt = auto_int_in_16; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_16_io_plic_ready = ~pending_16; // @[Plic.scala 250:18]
  assign gateways_gateway_16_io_plic_complete = completedDevs[17]; // @[Plic.scala 265:33]
  assign gateways_gateway_17_clock = clock;
  assign gateways_gateway_17_reset = reset;
  assign gateways_gateway_17_io_interrupt = auto_int_in_17; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_17_io_plic_ready = ~pending_17; // @[Plic.scala 250:18]
  assign gateways_gateway_17_io_plic_complete = completedDevs[18]; // @[Plic.scala 265:33]
  assign gateways_gateway_18_clock = clock;
  assign gateways_gateway_18_reset = reset;
  assign gateways_gateway_18_io_interrupt = auto_int_in_18; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_18_io_plic_ready = ~pending_18; // @[Plic.scala 250:18]
  assign gateways_gateway_18_io_plic_complete = completedDevs[19]; // @[Plic.scala 265:33]
  assign gateways_gateway_19_clock = clock;
  assign gateways_gateway_19_reset = reset;
  assign gateways_gateway_19_io_interrupt = auto_int_in_19; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_19_io_plic_ready = ~pending_19; // @[Plic.scala 250:18]
  assign gateways_gateway_19_io_plic_complete = completedDevs[20]; // @[Plic.scala 265:33]
  assign gateways_gateway_20_clock = clock;
  assign gateways_gateway_20_reset = reset;
  assign gateways_gateway_20_io_interrupt = auto_int_in_20; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_20_io_plic_ready = ~pending_20; // @[Plic.scala 250:18]
  assign gateways_gateway_20_io_plic_complete = completedDevs[21]; // @[Plic.scala 265:33]
  assign gateways_gateway_21_clock = clock;
  assign gateways_gateway_21_reset = reset;
  assign gateways_gateway_21_io_interrupt = auto_int_in_21; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_21_io_plic_ready = ~pending_21; // @[Plic.scala 250:18]
  assign gateways_gateway_21_io_plic_complete = completedDevs[22]; // @[Plic.scala 265:33]
  assign gateways_gateway_22_clock = clock;
  assign gateways_gateway_22_reset = reset;
  assign gateways_gateway_22_io_interrupt = auto_int_in_22; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_22_io_plic_ready = ~pending_22; // @[Plic.scala 250:18]
  assign gateways_gateway_22_io_plic_complete = completedDevs[23]; // @[Plic.scala 265:33]
  assign gateways_gateway_23_clock = clock;
  assign gateways_gateway_23_reset = reset;
  assign gateways_gateway_23_io_interrupt = auto_int_in_23; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_23_io_plic_ready = ~pending_23; // @[Plic.scala 250:18]
  assign gateways_gateway_23_io_plic_complete = completedDevs[24]; // @[Plic.scala 265:33]
  assign gateways_gateway_24_clock = clock;
  assign gateways_gateway_24_reset = reset;
  assign gateways_gateway_24_io_interrupt = auto_int_in_24; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_24_io_plic_ready = ~pending_24; // @[Plic.scala 250:18]
  assign gateways_gateway_24_io_plic_complete = completedDevs[25]; // @[Plic.scala 265:33]
  assign gateways_gateway_25_clock = clock;
  assign gateways_gateway_25_reset = reset;
  assign gateways_gateway_25_io_interrupt = auto_int_in_25; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_25_io_plic_ready = ~pending_25; // @[Plic.scala 250:18]
  assign gateways_gateway_25_io_plic_complete = completedDevs[26]; // @[Plic.scala 265:33]
  assign gateways_gateway_26_clock = clock;
  assign gateways_gateway_26_reset = reset;
  assign gateways_gateway_26_io_interrupt = auto_int_in_26; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_26_io_plic_ready = ~pending_26; // @[Plic.scala 250:18]
  assign gateways_gateway_26_io_plic_complete = completedDevs[27]; // @[Plic.scala 265:33]
  assign gateways_gateway_27_clock = clock;
  assign gateways_gateway_27_reset = reset;
  assign gateways_gateway_27_io_interrupt = auto_int_in_27; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_27_io_plic_ready = ~pending_27; // @[Plic.scala 250:18]
  assign gateways_gateway_27_io_plic_complete = completedDevs[28]; // @[Plic.scala 265:33]
  assign gateways_gateway_28_clock = clock;
  assign gateways_gateway_28_reset = reset;
  assign gateways_gateway_28_io_interrupt = auto_int_in_28; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_28_io_plic_ready = ~pending_28; // @[Plic.scala 250:18]
  assign gateways_gateway_28_io_plic_complete = completedDevs[29]; // @[Plic.scala 265:33]
  assign gateways_gateway_29_clock = clock;
  assign gateways_gateway_29_reset = reset;
  assign gateways_gateway_29_io_interrupt = auto_int_in_29; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_29_io_plic_ready = ~pending_29; // @[Plic.scala 250:18]
  assign gateways_gateway_29_io_plic_complete = completedDevs[30]; // @[Plic.scala 265:33]
  assign gateways_gateway_30_clock = clock;
  assign gateways_gateway_30_reset = reset;
  assign gateways_gateway_30_io_interrupt = auto_int_in_30; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_30_io_plic_ready = ~pending_30; // @[Plic.scala 250:18]
  assign gateways_gateway_30_io_plic_complete = completedDevs[31]; // @[Plic.scala 265:33]
  assign gateways_gateway_31_clock = clock;
  assign gateways_gateway_31_reset = reset;
  assign gateways_gateway_31_io_interrupt = auto_int_in_31; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_31_io_plic_ready = ~pending_31; // @[Plic.scala 250:18]
  assign gateways_gateway_31_io_plic_complete = completedDevs[32]; // @[Plic.scala 265:33]
  assign gateways_gateway_32_clock = clock;
  assign gateways_gateway_32_reset = reset;
  assign gateways_gateway_32_io_interrupt = auto_int_in_32; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_32_io_plic_ready = ~pending_32; // @[Plic.scala 250:18]
  assign gateways_gateway_32_io_plic_complete = completedDevs[33]; // @[Plic.scala 265:33]
  assign gateways_gateway_33_clock = clock;
  assign gateways_gateway_33_reset = reset;
  assign gateways_gateway_33_io_interrupt = auto_int_in_33; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_33_io_plic_ready = ~pending_33; // @[Plic.scala 250:18]
  assign gateways_gateway_33_io_plic_complete = completedDevs[34]; // @[Plic.scala 265:33]
  assign gateways_gateway_34_clock = clock;
  assign gateways_gateway_34_reset = reset;
  assign gateways_gateway_34_io_interrupt = auto_int_in_34; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_34_io_plic_ready = ~pending_34; // @[Plic.scala 250:18]
  assign gateways_gateway_34_io_plic_complete = completedDevs[35]; // @[Plic.scala 265:33]
  assign gateways_gateway_35_clock = clock;
  assign gateways_gateway_35_reset = reset;
  assign gateways_gateway_35_io_interrupt = auto_int_in_35; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_35_io_plic_ready = ~pending_35; // @[Plic.scala 250:18]
  assign gateways_gateway_35_io_plic_complete = completedDevs[36]; // @[Plic.scala 265:33]
  assign gateways_gateway_36_clock = clock;
  assign gateways_gateway_36_reset = reset;
  assign gateways_gateway_36_io_interrupt = auto_int_in_36; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_36_io_plic_ready = ~pending_36; // @[Plic.scala 250:18]
  assign gateways_gateway_36_io_plic_complete = completedDevs[37]; // @[Plic.scala 265:33]
  assign gateways_gateway_37_clock = clock;
  assign gateways_gateway_37_reset = reset;
  assign gateways_gateway_37_io_interrupt = auto_int_in_37; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_37_io_plic_ready = ~pending_37; // @[Plic.scala 250:18]
  assign gateways_gateway_37_io_plic_complete = completedDevs[38]; // @[Plic.scala 265:33]
  assign gateways_gateway_38_clock = clock;
  assign gateways_gateway_38_reset = reset;
  assign gateways_gateway_38_io_interrupt = auto_int_in_38; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_38_io_plic_ready = ~pending_38; // @[Plic.scala 250:18]
  assign gateways_gateway_38_io_plic_complete = completedDevs[39]; // @[Plic.scala 265:33]
  assign gateways_gateway_39_clock = clock;
  assign gateways_gateway_39_reset = reset;
  assign gateways_gateway_39_io_interrupt = auto_int_in_39; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_39_io_plic_ready = ~pending_39; // @[Plic.scala 250:18]
  assign gateways_gateway_39_io_plic_complete = completedDevs[40]; // @[Plic.scala 265:33]
  assign gateways_gateway_40_clock = clock;
  assign gateways_gateway_40_reset = reset;
  assign gateways_gateway_40_io_interrupt = auto_int_in_40; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_40_io_plic_ready = ~pending_40; // @[Plic.scala 250:18]
  assign gateways_gateway_40_io_plic_complete = completedDevs[41]; // @[Plic.scala 265:33]
  assign gateways_gateway_41_clock = clock;
  assign gateways_gateway_41_reset = reset;
  assign gateways_gateway_41_io_interrupt = auto_int_in_41; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_41_io_plic_ready = ~pending_41; // @[Plic.scala 250:18]
  assign gateways_gateway_41_io_plic_complete = completedDevs[42]; // @[Plic.scala 265:33]
  assign gateways_gateway_42_clock = clock;
  assign gateways_gateway_42_reset = reset;
  assign gateways_gateway_42_io_interrupt = auto_int_in_42; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_42_io_plic_ready = ~pending_42; // @[Plic.scala 250:18]
  assign gateways_gateway_42_io_plic_complete = completedDevs[43]; // @[Plic.scala 265:33]
  assign gateways_gateway_43_clock = clock;
  assign gateways_gateway_43_reset = reset;
  assign gateways_gateway_43_io_interrupt = auto_int_in_43; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_43_io_plic_ready = ~pending_43; // @[Plic.scala 250:18]
  assign gateways_gateway_43_io_plic_complete = completedDevs[44]; // @[Plic.scala 265:33]
  assign gateways_gateway_44_clock = clock;
  assign gateways_gateway_44_reset = reset;
  assign gateways_gateway_44_io_interrupt = auto_int_in_44; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_44_io_plic_ready = ~pending_44; // @[Plic.scala 250:18]
  assign gateways_gateway_44_io_plic_complete = completedDevs[45]; // @[Plic.scala 265:33]
  assign gateways_gateway_45_clock = clock;
  assign gateways_gateway_45_reset = reset;
  assign gateways_gateway_45_io_interrupt = auto_int_in_45; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_45_io_plic_ready = ~pending_45; // @[Plic.scala 250:18]
  assign gateways_gateway_45_io_plic_complete = completedDevs[46]; // @[Plic.scala 265:33]
  assign gateways_gateway_46_clock = clock;
  assign gateways_gateway_46_reset = reset;
  assign gateways_gateway_46_io_interrupt = auto_int_in_46; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_46_io_plic_ready = ~pending_46; // @[Plic.scala 250:18]
  assign gateways_gateway_46_io_plic_complete = completedDevs[47]; // @[Plic.scala 265:33]
  assign gateways_gateway_47_clock = clock;
  assign gateways_gateway_47_reset = reset;
  assign gateways_gateway_47_io_interrupt = auto_int_in_47; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_47_io_plic_ready = ~pending_47; // @[Plic.scala 250:18]
  assign gateways_gateway_47_io_plic_complete = completedDevs[48]; // @[Plic.scala 265:33]
  assign gateways_gateway_48_clock = clock;
  assign gateways_gateway_48_reset = reset;
  assign gateways_gateway_48_io_interrupt = auto_int_in_48; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_48_io_plic_ready = ~pending_48; // @[Plic.scala 250:18]
  assign gateways_gateway_48_io_plic_complete = completedDevs[49]; // @[Plic.scala 265:33]
  assign gateways_gateway_49_clock = clock;
  assign gateways_gateway_49_reset = reset;
  assign gateways_gateway_49_io_interrupt = auto_int_in_49; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_49_io_plic_ready = ~pending_49; // @[Plic.scala 250:18]
  assign gateways_gateway_49_io_plic_complete = completedDevs[50]; // @[Plic.scala 265:33]
  assign gateways_gateway_50_clock = clock;
  assign gateways_gateway_50_reset = reset;
  assign gateways_gateway_50_io_interrupt = auto_int_in_50; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_50_io_plic_ready = ~pending_50; // @[Plic.scala 250:18]
  assign gateways_gateway_50_io_plic_complete = completedDevs[51]; // @[Plic.scala 265:33]
  assign gateways_gateway_51_clock = clock;
  assign gateways_gateway_51_reset = reset;
  assign gateways_gateway_51_io_interrupt = auto_int_in_51; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_51_io_plic_ready = ~pending_51; // @[Plic.scala 250:18]
  assign gateways_gateway_51_io_plic_complete = completedDevs[52]; // @[Plic.scala 265:33]
  assign gateways_gateway_52_clock = clock;
  assign gateways_gateway_52_reset = reset;
  assign gateways_gateway_52_io_interrupt = auto_int_in_52; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_52_io_plic_ready = ~pending_52; // @[Plic.scala 250:18]
  assign gateways_gateway_52_io_plic_complete = completedDevs[53]; // @[Plic.scala 265:33]
  assign gateways_gateway_53_clock = clock;
  assign gateways_gateway_53_reset = reset;
  assign gateways_gateway_53_io_interrupt = auto_int_in_53; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_53_io_plic_ready = ~pending_53; // @[Plic.scala 250:18]
  assign gateways_gateway_53_io_plic_complete = completedDevs[54]; // @[Plic.scala 265:33]
  assign gateways_gateway_54_clock = clock;
  assign gateways_gateway_54_reset = reset;
  assign gateways_gateway_54_io_interrupt = auto_int_in_54; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_54_io_plic_ready = ~pending_54; // @[Plic.scala 250:18]
  assign gateways_gateway_54_io_plic_complete = completedDevs[55]; // @[Plic.scala 265:33]
  assign gateways_gateway_55_clock = clock;
  assign gateways_gateway_55_reset = reset;
  assign gateways_gateway_55_io_interrupt = auto_int_in_55; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gateways_gateway_55_io_plic_ready = ~pending_55; // @[Plic.scala 250:18]
  assign gateways_gateway_55_io_plic_complete = completedDevs[56]; // @[Plic.scala 265:33]
  assign fanin_io_prio_0 = priority_0; // @[Plic.scala 185:21]
  assign fanin_io_prio_1 = priority_1; // @[Plic.scala 185:21]
  assign fanin_io_prio_2 = priority_2; // @[Plic.scala 185:21]
  assign fanin_io_prio_3 = priority_3; // @[Plic.scala 185:21]
  assign fanin_io_prio_4 = priority_4; // @[Plic.scala 185:21]
  assign fanin_io_prio_5 = priority_5; // @[Plic.scala 185:21]
  assign fanin_io_prio_6 = priority_6; // @[Plic.scala 185:21]
  assign fanin_io_prio_7 = priority_7; // @[Plic.scala 185:21]
  assign fanin_io_prio_8 = priority_8; // @[Plic.scala 185:21]
  assign fanin_io_prio_9 = priority_9; // @[Plic.scala 185:21]
  assign fanin_io_prio_10 = priority_10; // @[Plic.scala 185:21]
  assign fanin_io_prio_11 = priority_11; // @[Plic.scala 185:21]
  assign fanin_io_prio_12 = priority_12; // @[Plic.scala 185:21]
  assign fanin_io_prio_13 = priority_13; // @[Plic.scala 185:21]
  assign fanin_io_prio_14 = priority_14; // @[Plic.scala 185:21]
  assign fanin_io_prio_15 = priority_15; // @[Plic.scala 185:21]
  assign fanin_io_prio_16 = priority_16; // @[Plic.scala 185:21]
  assign fanin_io_prio_17 = priority_17; // @[Plic.scala 185:21]
  assign fanin_io_prio_18 = priority_18; // @[Plic.scala 185:21]
  assign fanin_io_prio_19 = priority_19; // @[Plic.scala 185:21]
  assign fanin_io_prio_20 = priority_20; // @[Plic.scala 185:21]
  assign fanin_io_prio_21 = priority_21; // @[Plic.scala 185:21]
  assign fanin_io_prio_22 = priority_22; // @[Plic.scala 185:21]
  assign fanin_io_prio_23 = priority_23; // @[Plic.scala 185:21]
  assign fanin_io_prio_24 = priority_24; // @[Plic.scala 185:21]
  assign fanin_io_prio_25 = priority_25; // @[Plic.scala 185:21]
  assign fanin_io_prio_26 = priority_26; // @[Plic.scala 185:21]
  assign fanin_io_prio_27 = priority_27; // @[Plic.scala 185:21]
  assign fanin_io_prio_28 = priority_28; // @[Plic.scala 185:21]
  assign fanin_io_prio_29 = priority_29; // @[Plic.scala 185:21]
  assign fanin_io_prio_30 = priority_30; // @[Plic.scala 185:21]
  assign fanin_io_prio_31 = priority_31; // @[Plic.scala 185:21]
  assign fanin_io_prio_32 = priority_32; // @[Plic.scala 185:21]
  assign fanin_io_prio_33 = priority_33; // @[Plic.scala 185:21]
  assign fanin_io_prio_34 = priority_34; // @[Plic.scala 185:21]
  assign fanin_io_prio_35 = priority_35; // @[Plic.scala 185:21]
  assign fanin_io_prio_36 = priority_36; // @[Plic.scala 185:21]
  assign fanin_io_prio_37 = priority_37; // @[Plic.scala 185:21]
  assign fanin_io_prio_38 = priority_38; // @[Plic.scala 185:21]
  assign fanin_io_prio_39 = priority_39; // @[Plic.scala 185:21]
  assign fanin_io_prio_40 = priority_40; // @[Plic.scala 185:21]
  assign fanin_io_prio_41 = priority_41; // @[Plic.scala 185:21]
  assign fanin_io_prio_42 = priority_42; // @[Plic.scala 185:21]
  assign fanin_io_prio_43 = priority_43; // @[Plic.scala 185:21]
  assign fanin_io_prio_44 = priority_44; // @[Plic.scala 185:21]
  assign fanin_io_prio_45 = priority_45; // @[Plic.scala 185:21]
  assign fanin_io_prio_46 = priority_46; // @[Plic.scala 185:21]
  assign fanin_io_prio_47 = priority_47; // @[Plic.scala 185:21]
  assign fanin_io_prio_48 = priority_48; // @[Plic.scala 185:21]
  assign fanin_io_prio_49 = priority_49; // @[Plic.scala 185:21]
  assign fanin_io_prio_50 = priority_50; // @[Plic.scala 185:21]
  assign fanin_io_prio_51 = priority_51; // @[Plic.scala 185:21]
  assign fanin_io_prio_52 = priority_52; // @[Plic.scala 185:21]
  assign fanin_io_prio_53 = priority_53; // @[Plic.scala 185:21]
  assign fanin_io_prio_54 = priority_54; // @[Plic.scala 185:21]
  assign fanin_io_prio_55 = priority_55; // @[Plic.scala 185:21]
  assign fanin_io_ip = enableVec_0 & pendingUInt; // @[Plic.scala 186:40]
  assign fanin_1_io_prio_0 = priority_0; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_1 = priority_1; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_2 = priority_2; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_3 = priority_3; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_4 = priority_4; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_5 = priority_5; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_6 = priority_6; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_7 = priority_7; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_8 = priority_8; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_9 = priority_9; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_10 = priority_10; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_11 = priority_11; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_12 = priority_12; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_13 = priority_13; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_14 = priority_14; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_15 = priority_15; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_16 = priority_16; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_17 = priority_17; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_18 = priority_18; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_19 = priority_19; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_20 = priority_20; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_21 = priority_21; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_22 = priority_22; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_23 = priority_23; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_24 = priority_24; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_25 = priority_25; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_26 = priority_26; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_27 = priority_27; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_28 = priority_28; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_29 = priority_29; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_30 = priority_30; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_31 = priority_31; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_32 = priority_32; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_33 = priority_33; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_34 = priority_34; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_35 = priority_35; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_36 = priority_36; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_37 = priority_37; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_38 = priority_38; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_39 = priority_39; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_40 = priority_40; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_41 = priority_41; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_42 = priority_42; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_43 = priority_43; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_44 = priority_44; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_45 = priority_45; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_46 = priority_46; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_47 = priority_47; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_48 = priority_48; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_49 = priority_49; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_50 = priority_50; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_51 = priority_51; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_52 = priority_52; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_53 = priority_53; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_54 = priority_54; // @[Plic.scala 185:21]
  assign fanin_1_io_prio_55 = priority_55; // @[Plic.scala 185:21]
  assign fanin_1_io_ip = enableVec_1 & pendingUInt; // @[Plic.scala 186:40]
  assign out_back_clock = clock;
  assign out_back_reset = reset;
  assign out_back_io_enq_valid = auto_in_a_valid; // @[RegisterRouter.scala 83:24]
  assign out_back_io_enq_bits_read = auto_in_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 72:36]
  assign out_back_io_enq_bits_index = auto_in_a_bits_address[25:2]; // @[RegisterRouter.scala 71:18 73:19]
  assign out_back_io_enq_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign out_back_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign out_back_io_enq_bits_extra_tlrr_extra_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign out_back_io_enq_bits_extra_tlrr_extra_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign out_back_io_deq_ready = auto_in_d_ready; // @[RegisterRouter.scala 83:24]
  always @(posedge clock) begin
    if (out_f_woready_49) begin // @[RegField.scala 74:88]
      priority_0 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_64) begin // @[RegField.scala 74:88]
      priority_1 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_86) begin // @[RegField.scala 74:88]
      priority_2 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_134) begin // @[RegField.scala 74:88]
      priority_3 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_32) begin // @[RegField.scala 74:88]
      priority_4 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_50) begin // @[RegField.scala 74:88]
      priority_5 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_84) begin // @[RegField.scala 74:88]
      priority_6 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_125) begin // @[RegField.scala 74:88]
      priority_7 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_55) begin // @[RegField.scala 74:88]
      priority_8 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_33) begin // @[RegField.scala 74:88]
      priority_9 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_119) begin // @[RegField.scala 74:88]
      priority_10 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_81) begin // @[RegField.scala 74:88]
      priority_11 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_62) begin // @[RegField.scala 74:88]
      priority_12 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_40) begin // @[RegField.scala 74:88]
      priority_13 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_136) begin // @[RegField.scala 74:88]
      priority_14 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_116) begin // @[RegField.scala 74:88]
      priority_15 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_68) begin // @[RegField.scala 74:88]
      priority_16 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_114) begin // @[RegField.scala 74:88]
      priority_17 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_133) begin // @[RegField.scala 74:88]
      priority_18 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_41) begin // @[RegField.scala 74:88]
      priority_19 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_53) begin // @[RegField.scala 74:88]
      priority_20 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_78) begin // @[RegField.scala 74:88]
      priority_21 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_124) begin // @[RegField.scala 74:88]
      priority_22 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_36) begin // @[RegField.scala 74:88]
      priority_23 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_38) begin // @[RegField.scala 74:88]
      priority_24 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_122) begin // @[RegField.scala 74:88]
      priority_25 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_80) begin // @[RegField.scala 74:88]
      priority_26 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_51) begin // @[RegField.scala 74:88]
      priority_27 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_47) begin // @[RegField.scala 74:88]
      priority_28 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_131) begin // @[RegField.scala 74:88]
      priority_29 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_117) begin // @[RegField.scala 74:88]
      priority_30 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_65) begin // @[RegField.scala 74:88]
      priority_31 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_54) begin // @[RegField.scala 74:88]
      priority_32 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_66) begin // @[RegField.scala 74:88]
      priority_33 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_87) begin // @[RegField.scala 74:88]
      priority_34 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_130) begin // @[RegField.scala 74:88]
      priority_35 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_37) begin // @[RegField.scala 74:88]
      priority_36 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_52) begin // @[RegField.scala 74:88]
      priority_37 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_85) begin // @[RegField.scala 74:88]
      priority_38 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_121) begin // @[RegField.scala 74:88]
      priority_39 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_63) begin // @[RegField.scala 74:88]
      priority_40 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_35) begin // @[RegField.scala 74:88]
      priority_41 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_120) begin // @[RegField.scala 74:88]
      priority_42 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_79) begin // @[RegField.scala 74:88]
      priority_43 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_67) begin // @[RegField.scala 74:88]
      priority_44 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_46) begin // @[RegField.scala 74:88]
      priority_45 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_135) begin // @[RegField.scala 74:88]
      priority_46 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_88) begin // @[RegField.scala 74:88]
      priority_47 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_83) begin // @[RegField.scala 74:88]
      priority_48 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_115) begin // @[RegField.scala 74:88]
      priority_49 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_132) begin // @[RegField.scala 74:88]
      priority_50 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_39) begin // @[RegField.scala 74:88]
      priority_51 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_56) begin // @[RegField.scala 74:88]
      priority_52 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_82) begin // @[RegField.scala 74:88]
      priority_53 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_123) begin // @[RegField.scala 74:88]
      priority_54 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_34) begin // @[RegField.scala 74:88]
      priority_55 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_71) begin // @[RegField.scala 74:88]
      threshold_0 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_69) begin // @[RegField.scala 74:88]
      threshold_1 <= out_back_io_deq_bits_data[2:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_0 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_1 | gateways_gateway_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_0 <= ~claimedDevs_1; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_1 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_2 | gateways_gateway_1_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_1 <= ~claimedDevs_2; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_2 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_3 | gateways_gateway_2_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_2 <= ~claimedDevs_3; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_3 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_4 | gateways_gateway_3_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_3 <= ~claimedDevs_4; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_4 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_5 | gateways_gateway_4_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_4 <= ~claimedDevs_5; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_5 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_6 | gateways_gateway_5_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_5 <= ~claimedDevs_6; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_6 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_7 | gateways_gateway_6_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_6 <= ~claimedDevs_7; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_7 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_8 | gateways_gateway_7_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_7 <= ~claimedDevs_8; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_8 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_9 | gateways_gateway_8_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_8 <= ~claimedDevs_9; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_9 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_10 | gateways_gateway_9_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_9 <= ~claimedDevs_10; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_10 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_11 | gateways_gateway_10_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_10 <= ~claimedDevs_11; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_11 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_12 | gateways_gateway_11_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_11 <= ~claimedDevs_12; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_12 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_13 | gateways_gateway_12_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_12 <= ~claimedDevs_13; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_13 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_14 | gateways_gateway_13_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_13 <= ~claimedDevs_14; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_14 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_15 | gateways_gateway_14_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_14 <= ~claimedDevs_15; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_15 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_16 | gateways_gateway_15_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_15 <= ~claimedDevs_16; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_16 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_17 | gateways_gateway_16_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_16 <= ~claimedDevs_17; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_17 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_18 | gateways_gateway_17_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_17 <= ~claimedDevs_18; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_18 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_19 | gateways_gateway_18_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_18 <= ~claimedDevs_19; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_19 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_20 | gateways_gateway_19_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_19 <= ~claimedDevs_20; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_20 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_21 | gateways_gateway_20_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_20 <= ~claimedDevs_21; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_21 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_22 | gateways_gateway_21_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_21 <= ~claimedDevs_22; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_22 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_23 | gateways_gateway_22_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_22 <= ~claimedDevs_23; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_23 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_24 | gateways_gateway_23_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_23 <= ~claimedDevs_24; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_24 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_25 | gateways_gateway_24_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_24 <= ~claimedDevs_25; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_25 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_26 | gateways_gateway_25_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_25 <= ~claimedDevs_26; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_26 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_27 | gateways_gateway_26_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_26 <= ~claimedDevs_27; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_27 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_28 | gateways_gateway_27_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_27 <= ~claimedDevs_28; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_28 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_29 | gateways_gateway_28_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_28 <= ~claimedDevs_29; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_29 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_30 | gateways_gateway_29_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_29 <= ~claimedDevs_30; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_30 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_31 | gateways_gateway_30_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_30 <= ~claimedDevs_31; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_31 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_32 | gateways_gateway_31_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_31 <= ~claimedDevs_32; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_32 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_33 | gateways_gateway_32_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_32 <= ~claimedDevs_33; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_33 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_34 | gateways_gateway_33_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_33 <= ~claimedDevs_34; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_34 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_35 | gateways_gateway_34_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_34 <= ~claimedDevs_35; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_35 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_36 | gateways_gateway_35_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_35 <= ~claimedDevs_36; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_36 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_37 | gateways_gateway_36_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_36 <= ~claimedDevs_37; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_37 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_38 | gateways_gateway_37_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_37 <= ~claimedDevs_38; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_38 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_39 | gateways_gateway_38_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_38 <= ~claimedDevs_39; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_39 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_40 | gateways_gateway_39_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_39 <= ~claimedDevs_40; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_40 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_41 | gateways_gateway_40_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_40 <= ~claimedDevs_41; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_41 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_42 | gateways_gateway_41_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_41 <= ~claimedDevs_42; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_42 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_43 | gateways_gateway_42_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_42 <= ~claimedDevs_43; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_43 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_44 | gateways_gateway_43_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_43 <= ~claimedDevs_44; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_44 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_45 | gateways_gateway_44_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_44 <= ~claimedDevs_45; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_45 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_46 | gateways_gateway_45_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_45 <= ~claimedDevs_46; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_46 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_47 | gateways_gateway_46_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_46 <= ~claimedDevs_47; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_47 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_48 | gateways_gateway_47_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_47 <= ~claimedDevs_48; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_48 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_49 | gateways_gateway_48_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_48 <= ~claimedDevs_49; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_49 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_50 | gateways_gateway_49_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_49 <= ~claimedDevs_50; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_50 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_51 | gateways_gateway_50_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_50 <= ~claimedDevs_51; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_51 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_52 | gateways_gateway_51_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_51 <= ~claimedDevs_52; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_52 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_53 | gateways_gateway_52_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_52 <= ~claimedDevs_53; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_53 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_54 | gateways_gateway_53_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_53 <= ~claimedDevs_54; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_54 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_55 | gateways_gateway_54_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_54 <= ~claimedDevs_55; // @[Plic.scala 251:31]
    end
    if (reset) begin // @[Plic.scala 168:22]
      pending_55 <= 1'h0; // @[Plic.scala 168:22]
    end else if (claimedDevs_56 | gateways_gateway_55_io_plic_valid) begin // @[Plic.scala 251:27]
      pending_55 <= ~claimedDevs_56; // @[Plic.scala 251:31]
    end
    if (out_f_woready_74) begin // @[RegField.scala 74:88]
      enables_0_0 <= out_back_io_deq_bits_data[7:1]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_75) begin // @[RegField.scala 74:88]
      enables_0_1 <= out_back_io_deq_bits_data[15:8]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_76) begin // @[RegField.scala 74:88]
      enables_0_2 <= out_back_io_deq_bits_data[23:16]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_77) begin // @[RegField.scala 74:88]
      enables_0_3 <= out_back_io_deq_bits_data[31:24]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_42) begin // @[RegField.scala 74:88]
      enables_0_4 <= out_back_io_deq_bits_data[7:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_43) begin // @[RegField.scala 74:88]
      enables_0_5 <= out_back_io_deq_bits_data[15:8]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_44) begin // @[RegField.scala 74:88]
      enables_0_6 <= out_back_io_deq_bits_data[23:16]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_45) begin // @[RegField.scala 74:88]
      enables_0_7 <= out_back_io_deq_bits_data[24]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_58) begin // @[RegField.scala 74:88]
      enables_1_0 <= out_back_io_deq_bits_data[7:1]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_59) begin // @[RegField.scala 74:88]
      enables_1_1 <= out_back_io_deq_bits_data[15:8]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_60) begin // @[RegField.scala 74:88]
      enables_1_2 <= out_back_io_deq_bits_data[23:16]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_61) begin // @[RegField.scala 74:88]
      enables_1_3 <= out_back_io_deq_bits_data[31:24]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_126) begin // @[RegField.scala 74:88]
      enables_1_4 <= out_back_io_deq_bits_data[7:0]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_127) begin // @[RegField.scala 74:88]
      enables_1_5 <= out_back_io_deq_bits_data[15:8]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_128) begin // @[RegField.scala 74:88]
      enables_1_6 <= out_back_io_deq_bits_data[23:16]; // @[RegField.scala 74:92]
    end
    if (out_f_woready_129) begin // @[RegField.scala 74:88]
      enables_1_7 <= out_back_io_deq_bits_data[24]; // @[RegField.scala 74:92]
    end
    maxDevs_0 <= fanin_io_dev; // @[Plic.scala 187:21]
    maxDevs_1 <= fanin_1_io_dev; // @[Plic.scala 187:21]
    bundleOut_0_0_REG <= fanin_io_max; // @[Plic.scala 188:41]
    bundleOut_1_0_REG <= fanin_1_io_max; // @[Plic.scala 188:41]
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_4 == 2'h0) & ~reset) begin
          $fatal; // @[Plic.scala 245:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(_T_4 == 2'h0)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Plic.scala:245 assert((claimer.asUInt & (claimer.asUInt - UInt(1))) === UInt(0)) // One-Hot\n"
            ); // @[Plic.scala 245:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_69 == 2'h0) & _T_7) begin
          $fatal; // @[Plic.scala 262:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_7 & ~(_T_69 == 2'h0)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Plic.scala:262 assert((completer.asUInt & (completer.asUInt - UInt(1))) === UInt(0)) // One-Hot\n"
            ); // @[Plic.scala 262:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(completerDev == completerDev) & _T_7) begin
          $fatal; // @[Plic.scala 292:19]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_7 & ~(completerDev == completerDev)) begin
          $fwrite(32'h80000002,
            "Assertion failed: completerDev should be consistent for all harts\n    at Plic.scala:292 assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0),\n"
            ); // @[Plic.scala 292:19]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(completerDev == completerDev) & _T_7) begin
          $fatal; // @[Plic.scala 292:19]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_7 & ~(completerDev == completerDev)) begin
          $fwrite(32'h80000002,
            "Assertion failed: completerDev should be consistent for all harts\n    at Plic.scala:292 assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0),\n"
            ); // @[Plic.scala 292:19]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  priority_0 = _RAND_0[2:0];
  _RAND_1 = {1{`RANDOM}};
  priority_1 = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  priority_2 = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  priority_3 = _RAND_3[2:0];
  _RAND_4 = {1{`RANDOM}};
  priority_4 = _RAND_4[2:0];
  _RAND_5 = {1{`RANDOM}};
  priority_5 = _RAND_5[2:0];
  _RAND_6 = {1{`RANDOM}};
  priority_6 = _RAND_6[2:0];
  _RAND_7 = {1{`RANDOM}};
  priority_7 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  priority_8 = _RAND_8[2:0];
  _RAND_9 = {1{`RANDOM}};
  priority_9 = _RAND_9[2:0];
  _RAND_10 = {1{`RANDOM}};
  priority_10 = _RAND_10[2:0];
  _RAND_11 = {1{`RANDOM}};
  priority_11 = _RAND_11[2:0];
  _RAND_12 = {1{`RANDOM}};
  priority_12 = _RAND_12[2:0];
  _RAND_13 = {1{`RANDOM}};
  priority_13 = _RAND_13[2:0];
  _RAND_14 = {1{`RANDOM}};
  priority_14 = _RAND_14[2:0];
  _RAND_15 = {1{`RANDOM}};
  priority_15 = _RAND_15[2:0];
  _RAND_16 = {1{`RANDOM}};
  priority_16 = _RAND_16[2:0];
  _RAND_17 = {1{`RANDOM}};
  priority_17 = _RAND_17[2:0];
  _RAND_18 = {1{`RANDOM}};
  priority_18 = _RAND_18[2:0];
  _RAND_19 = {1{`RANDOM}};
  priority_19 = _RAND_19[2:0];
  _RAND_20 = {1{`RANDOM}};
  priority_20 = _RAND_20[2:0];
  _RAND_21 = {1{`RANDOM}};
  priority_21 = _RAND_21[2:0];
  _RAND_22 = {1{`RANDOM}};
  priority_22 = _RAND_22[2:0];
  _RAND_23 = {1{`RANDOM}};
  priority_23 = _RAND_23[2:0];
  _RAND_24 = {1{`RANDOM}};
  priority_24 = _RAND_24[2:0];
  _RAND_25 = {1{`RANDOM}};
  priority_25 = _RAND_25[2:0];
  _RAND_26 = {1{`RANDOM}};
  priority_26 = _RAND_26[2:0];
  _RAND_27 = {1{`RANDOM}};
  priority_27 = _RAND_27[2:0];
  _RAND_28 = {1{`RANDOM}};
  priority_28 = _RAND_28[2:0];
  _RAND_29 = {1{`RANDOM}};
  priority_29 = _RAND_29[2:0];
  _RAND_30 = {1{`RANDOM}};
  priority_30 = _RAND_30[2:0];
  _RAND_31 = {1{`RANDOM}};
  priority_31 = _RAND_31[2:0];
  _RAND_32 = {1{`RANDOM}};
  priority_32 = _RAND_32[2:0];
  _RAND_33 = {1{`RANDOM}};
  priority_33 = _RAND_33[2:0];
  _RAND_34 = {1{`RANDOM}};
  priority_34 = _RAND_34[2:0];
  _RAND_35 = {1{`RANDOM}};
  priority_35 = _RAND_35[2:0];
  _RAND_36 = {1{`RANDOM}};
  priority_36 = _RAND_36[2:0];
  _RAND_37 = {1{`RANDOM}};
  priority_37 = _RAND_37[2:0];
  _RAND_38 = {1{`RANDOM}};
  priority_38 = _RAND_38[2:0];
  _RAND_39 = {1{`RANDOM}};
  priority_39 = _RAND_39[2:0];
  _RAND_40 = {1{`RANDOM}};
  priority_40 = _RAND_40[2:0];
  _RAND_41 = {1{`RANDOM}};
  priority_41 = _RAND_41[2:0];
  _RAND_42 = {1{`RANDOM}};
  priority_42 = _RAND_42[2:0];
  _RAND_43 = {1{`RANDOM}};
  priority_43 = _RAND_43[2:0];
  _RAND_44 = {1{`RANDOM}};
  priority_44 = _RAND_44[2:0];
  _RAND_45 = {1{`RANDOM}};
  priority_45 = _RAND_45[2:0];
  _RAND_46 = {1{`RANDOM}};
  priority_46 = _RAND_46[2:0];
  _RAND_47 = {1{`RANDOM}};
  priority_47 = _RAND_47[2:0];
  _RAND_48 = {1{`RANDOM}};
  priority_48 = _RAND_48[2:0];
  _RAND_49 = {1{`RANDOM}};
  priority_49 = _RAND_49[2:0];
  _RAND_50 = {1{`RANDOM}};
  priority_50 = _RAND_50[2:0];
  _RAND_51 = {1{`RANDOM}};
  priority_51 = _RAND_51[2:0];
  _RAND_52 = {1{`RANDOM}};
  priority_52 = _RAND_52[2:0];
  _RAND_53 = {1{`RANDOM}};
  priority_53 = _RAND_53[2:0];
  _RAND_54 = {1{`RANDOM}};
  priority_54 = _RAND_54[2:0];
  _RAND_55 = {1{`RANDOM}};
  priority_55 = _RAND_55[2:0];
  _RAND_56 = {1{`RANDOM}};
  threshold_0 = _RAND_56[2:0];
  _RAND_57 = {1{`RANDOM}};
  threshold_1 = _RAND_57[2:0];
  _RAND_58 = {1{`RANDOM}};
  pending_0 = _RAND_58[0:0];
  _RAND_59 = {1{`RANDOM}};
  pending_1 = _RAND_59[0:0];
  _RAND_60 = {1{`RANDOM}};
  pending_2 = _RAND_60[0:0];
  _RAND_61 = {1{`RANDOM}};
  pending_3 = _RAND_61[0:0];
  _RAND_62 = {1{`RANDOM}};
  pending_4 = _RAND_62[0:0];
  _RAND_63 = {1{`RANDOM}};
  pending_5 = _RAND_63[0:0];
  _RAND_64 = {1{`RANDOM}};
  pending_6 = _RAND_64[0:0];
  _RAND_65 = {1{`RANDOM}};
  pending_7 = _RAND_65[0:0];
  _RAND_66 = {1{`RANDOM}};
  pending_8 = _RAND_66[0:0];
  _RAND_67 = {1{`RANDOM}};
  pending_9 = _RAND_67[0:0];
  _RAND_68 = {1{`RANDOM}};
  pending_10 = _RAND_68[0:0];
  _RAND_69 = {1{`RANDOM}};
  pending_11 = _RAND_69[0:0];
  _RAND_70 = {1{`RANDOM}};
  pending_12 = _RAND_70[0:0];
  _RAND_71 = {1{`RANDOM}};
  pending_13 = _RAND_71[0:0];
  _RAND_72 = {1{`RANDOM}};
  pending_14 = _RAND_72[0:0];
  _RAND_73 = {1{`RANDOM}};
  pending_15 = _RAND_73[0:0];
  _RAND_74 = {1{`RANDOM}};
  pending_16 = _RAND_74[0:0];
  _RAND_75 = {1{`RANDOM}};
  pending_17 = _RAND_75[0:0];
  _RAND_76 = {1{`RANDOM}};
  pending_18 = _RAND_76[0:0];
  _RAND_77 = {1{`RANDOM}};
  pending_19 = _RAND_77[0:0];
  _RAND_78 = {1{`RANDOM}};
  pending_20 = _RAND_78[0:0];
  _RAND_79 = {1{`RANDOM}};
  pending_21 = _RAND_79[0:0];
  _RAND_80 = {1{`RANDOM}};
  pending_22 = _RAND_80[0:0];
  _RAND_81 = {1{`RANDOM}};
  pending_23 = _RAND_81[0:0];
  _RAND_82 = {1{`RANDOM}};
  pending_24 = _RAND_82[0:0];
  _RAND_83 = {1{`RANDOM}};
  pending_25 = _RAND_83[0:0];
  _RAND_84 = {1{`RANDOM}};
  pending_26 = _RAND_84[0:0];
  _RAND_85 = {1{`RANDOM}};
  pending_27 = _RAND_85[0:0];
  _RAND_86 = {1{`RANDOM}};
  pending_28 = _RAND_86[0:0];
  _RAND_87 = {1{`RANDOM}};
  pending_29 = _RAND_87[0:0];
  _RAND_88 = {1{`RANDOM}};
  pending_30 = _RAND_88[0:0];
  _RAND_89 = {1{`RANDOM}};
  pending_31 = _RAND_89[0:0];
  _RAND_90 = {1{`RANDOM}};
  pending_32 = _RAND_90[0:0];
  _RAND_91 = {1{`RANDOM}};
  pending_33 = _RAND_91[0:0];
  _RAND_92 = {1{`RANDOM}};
  pending_34 = _RAND_92[0:0];
  _RAND_93 = {1{`RANDOM}};
  pending_35 = _RAND_93[0:0];
  _RAND_94 = {1{`RANDOM}};
  pending_36 = _RAND_94[0:0];
  _RAND_95 = {1{`RANDOM}};
  pending_37 = _RAND_95[0:0];
  _RAND_96 = {1{`RANDOM}};
  pending_38 = _RAND_96[0:0];
  _RAND_97 = {1{`RANDOM}};
  pending_39 = _RAND_97[0:0];
  _RAND_98 = {1{`RANDOM}};
  pending_40 = _RAND_98[0:0];
  _RAND_99 = {1{`RANDOM}};
  pending_41 = _RAND_99[0:0];
  _RAND_100 = {1{`RANDOM}};
  pending_42 = _RAND_100[0:0];
  _RAND_101 = {1{`RANDOM}};
  pending_43 = _RAND_101[0:0];
  _RAND_102 = {1{`RANDOM}};
  pending_44 = _RAND_102[0:0];
  _RAND_103 = {1{`RANDOM}};
  pending_45 = _RAND_103[0:0];
  _RAND_104 = {1{`RANDOM}};
  pending_46 = _RAND_104[0:0];
  _RAND_105 = {1{`RANDOM}};
  pending_47 = _RAND_105[0:0];
  _RAND_106 = {1{`RANDOM}};
  pending_48 = _RAND_106[0:0];
  _RAND_107 = {1{`RANDOM}};
  pending_49 = _RAND_107[0:0];
  _RAND_108 = {1{`RANDOM}};
  pending_50 = _RAND_108[0:0];
  _RAND_109 = {1{`RANDOM}};
  pending_51 = _RAND_109[0:0];
  _RAND_110 = {1{`RANDOM}};
  pending_52 = _RAND_110[0:0];
  _RAND_111 = {1{`RANDOM}};
  pending_53 = _RAND_111[0:0];
  _RAND_112 = {1{`RANDOM}};
  pending_54 = _RAND_112[0:0];
  _RAND_113 = {1{`RANDOM}};
  pending_55 = _RAND_113[0:0];
  _RAND_114 = {1{`RANDOM}};
  enables_0_0 = _RAND_114[6:0];
  _RAND_115 = {1{`RANDOM}};
  enables_0_1 = _RAND_115[7:0];
  _RAND_116 = {1{`RANDOM}};
  enables_0_2 = _RAND_116[7:0];
  _RAND_117 = {1{`RANDOM}};
  enables_0_3 = _RAND_117[7:0];
  _RAND_118 = {1{`RANDOM}};
  enables_0_4 = _RAND_118[7:0];
  _RAND_119 = {1{`RANDOM}};
  enables_0_5 = _RAND_119[7:0];
  _RAND_120 = {1{`RANDOM}};
  enables_0_6 = _RAND_120[7:0];
  _RAND_121 = {1{`RANDOM}};
  enables_0_7 = _RAND_121[0:0];
  _RAND_122 = {1{`RANDOM}};
  enables_1_0 = _RAND_122[6:0];
  _RAND_123 = {1{`RANDOM}};
  enables_1_1 = _RAND_123[7:0];
  _RAND_124 = {1{`RANDOM}};
  enables_1_2 = _RAND_124[7:0];
  _RAND_125 = {1{`RANDOM}};
  enables_1_3 = _RAND_125[7:0];
  _RAND_126 = {1{`RANDOM}};
  enables_1_4 = _RAND_126[7:0];
  _RAND_127 = {1{`RANDOM}};
  enables_1_5 = _RAND_127[7:0];
  _RAND_128 = {1{`RANDOM}};
  enables_1_6 = _RAND_128[7:0];
  _RAND_129 = {1{`RANDOM}};
  enables_1_7 = _RAND_129[0:0];
  _RAND_130 = {1{`RANDOM}};
  maxDevs_0 = _RAND_130[5:0];
  _RAND_131 = {1{`RANDOM}};
  maxDevs_1 = _RAND_131[5:0];
  _RAND_132 = {1{`RANDOM}};
  bundleOut_0_0_REG = _RAND_132[2:0];
  _RAND_133 = {1{`RANDOM}};
  bundleOut_1_0_REG = _RAND_133[2:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ClockSinkDomain(
  input         auto_plic_int_in_0,
  input         auto_plic_int_in_1,
  input         auto_plic_int_in_2,
  input         auto_plic_int_in_3,
  input         auto_plic_int_in_4,
  input         auto_plic_int_in_5,
  input         auto_plic_int_in_6,
  input         auto_plic_int_in_7,
  input         auto_plic_int_in_8,
  input         auto_plic_int_in_9,
  input         auto_plic_int_in_10,
  input         auto_plic_int_in_11,
  input         auto_plic_int_in_12,
  input         auto_plic_int_in_13,
  input         auto_plic_int_in_14,
  input         auto_plic_int_in_15,
  input         auto_plic_int_in_16,
  input         auto_plic_int_in_17,
  input         auto_plic_int_in_18,
  input         auto_plic_int_in_19,
  input         auto_plic_int_in_20,
  input         auto_plic_int_in_21,
  input         auto_plic_int_in_22,
  input         auto_plic_int_in_23,
  input         auto_plic_int_in_24,
  input         auto_plic_int_in_25,
  input         auto_plic_int_in_26,
  input         auto_plic_int_in_27,
  input         auto_plic_int_in_28,
  input         auto_plic_int_in_29,
  input         auto_plic_int_in_30,
  input         auto_plic_int_in_31,
  input         auto_plic_int_in_32,
  input         auto_plic_int_in_33,
  input         auto_plic_int_in_34,
  input         auto_plic_int_in_35,
  input         auto_plic_int_in_36,
  input         auto_plic_int_in_37,
  input         auto_plic_int_in_38,
  input         auto_plic_int_in_39,
  input         auto_plic_int_in_40,
  input         auto_plic_int_in_41,
  input         auto_plic_int_in_42,
  input         auto_plic_int_in_43,
  input         auto_plic_int_in_44,
  input         auto_plic_int_in_45,
  input         auto_plic_int_in_46,
  input         auto_plic_int_in_47,
  input         auto_plic_int_in_48,
  input         auto_plic_int_in_49,
  input         auto_plic_int_in_50,
  input         auto_plic_int_in_51,
  input         auto_plic_int_in_52,
  input         auto_plic_int_in_53,
  input         auto_plic_int_in_54,
  input         auto_plic_int_in_55,
  output        auto_plic_int_out_1_0,
  output        auto_plic_int_out_0_0,
  output        auto_plic_in_a_ready,
  input         auto_plic_in_a_valid,
  input  [2:0]  auto_plic_in_a_bits_opcode,
  input  [2:0]  auto_plic_in_a_bits_param,
  input  [1:0]  auto_plic_in_a_bits_size,
  input  [6:0]  auto_plic_in_a_bits_source,
  input  [27:0] auto_plic_in_a_bits_address,
  input  [3:0]  auto_plic_in_a_bits_mask,
  input  [31:0] auto_plic_in_a_bits_data,
  input         auto_plic_in_a_bits_corrupt,
  input         auto_plic_in_d_ready,
  output        auto_plic_in_d_valid,
  output [2:0]  auto_plic_in_d_bits_opcode,
  output [1:0]  auto_plic_in_d_bits_size,
  output [6:0]  auto_plic_in_d_bits_source,
  output [31:0] auto_plic_in_d_bits_data,
  input         auto_clock_in_clock,
  input         auto_clock_in_reset
);
  wire  plic_clock; // @[Plic.scala 362:46]
  wire  plic_reset; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_0; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_1; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_2; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_3; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_4; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_5; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_6; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_7; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_8; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_9; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_10; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_11; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_12; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_13; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_14; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_15; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_16; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_17; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_18; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_19; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_20; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_21; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_22; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_23; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_24; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_25; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_26; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_27; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_28; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_29; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_30; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_31; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_32; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_33; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_34; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_35; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_36; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_37; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_38; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_39; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_40; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_41; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_42; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_43; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_44; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_45; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_46; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_47; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_48; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_49; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_50; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_51; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_52; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_53; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_54; // @[Plic.scala 362:46]
  wire  plic_auto_int_in_55; // @[Plic.scala 362:46]
  wire  plic_auto_int_out_1_0; // @[Plic.scala 362:46]
  wire  plic_auto_int_out_0_0; // @[Plic.scala 362:46]
  wire  plic_auto_in_a_ready; // @[Plic.scala 362:46]
  wire  plic_auto_in_a_valid; // @[Plic.scala 362:46]
  wire [2:0] plic_auto_in_a_bits_opcode; // @[Plic.scala 362:46]
  wire [2:0] plic_auto_in_a_bits_param; // @[Plic.scala 362:46]
  wire [1:0] plic_auto_in_a_bits_size; // @[Plic.scala 362:46]
  wire [6:0] plic_auto_in_a_bits_source; // @[Plic.scala 362:46]
  wire [27:0] plic_auto_in_a_bits_address; // @[Plic.scala 362:46]
  wire [3:0] plic_auto_in_a_bits_mask; // @[Plic.scala 362:46]
  wire [31:0] plic_auto_in_a_bits_data; // @[Plic.scala 362:46]
  wire  plic_auto_in_a_bits_corrupt; // @[Plic.scala 362:46]
  wire  plic_auto_in_d_ready; // @[Plic.scala 362:46]
  wire  plic_auto_in_d_valid; // @[Plic.scala 362:46]
  wire [2:0] plic_auto_in_d_bits_opcode; // @[Plic.scala 362:46]
  wire [1:0] plic_auto_in_d_bits_size; // @[Plic.scala 362:46]
  wire [6:0] plic_auto_in_d_bits_source; // @[Plic.scala 362:46]
  wire [31:0] plic_auto_in_d_bits_data; // @[Plic.scala 362:46]
  TLPLIC plic ( // @[Plic.scala 362:46]
    .clock(plic_clock),
    .reset(plic_reset),
    .auto_int_in_0(plic_auto_int_in_0),
    .auto_int_in_1(plic_auto_int_in_1),
    .auto_int_in_2(plic_auto_int_in_2),
    .auto_int_in_3(plic_auto_int_in_3),
    .auto_int_in_4(plic_auto_int_in_4),
    .auto_int_in_5(plic_auto_int_in_5),
    .auto_int_in_6(plic_auto_int_in_6),
    .auto_int_in_7(plic_auto_int_in_7),
    .auto_int_in_8(plic_auto_int_in_8),
    .auto_int_in_9(plic_auto_int_in_9),
    .auto_int_in_10(plic_auto_int_in_10),
    .auto_int_in_11(plic_auto_int_in_11),
    .auto_int_in_12(plic_auto_int_in_12),
    .auto_int_in_13(plic_auto_int_in_13),
    .auto_int_in_14(plic_auto_int_in_14),
    .auto_int_in_15(plic_auto_int_in_15),
    .auto_int_in_16(plic_auto_int_in_16),
    .auto_int_in_17(plic_auto_int_in_17),
    .auto_int_in_18(plic_auto_int_in_18),
    .auto_int_in_19(plic_auto_int_in_19),
    .auto_int_in_20(plic_auto_int_in_20),
    .auto_int_in_21(plic_auto_int_in_21),
    .auto_int_in_22(plic_auto_int_in_22),
    .auto_int_in_23(plic_auto_int_in_23),
    .auto_int_in_24(plic_auto_int_in_24),
    .auto_int_in_25(plic_auto_int_in_25),
    .auto_int_in_26(plic_auto_int_in_26),
    .auto_int_in_27(plic_auto_int_in_27),
    .auto_int_in_28(plic_auto_int_in_28),
    .auto_int_in_29(plic_auto_int_in_29),
    .auto_int_in_30(plic_auto_int_in_30),
    .auto_int_in_31(plic_auto_int_in_31),
    .auto_int_in_32(plic_auto_int_in_32),
    .auto_int_in_33(plic_auto_int_in_33),
    .auto_int_in_34(plic_auto_int_in_34),
    .auto_int_in_35(plic_auto_int_in_35),
    .auto_int_in_36(plic_auto_int_in_36),
    .auto_int_in_37(plic_auto_int_in_37),
    .auto_int_in_38(plic_auto_int_in_38),
    .auto_int_in_39(plic_auto_int_in_39),
    .auto_int_in_40(plic_auto_int_in_40),
    .auto_int_in_41(plic_auto_int_in_41),
    .auto_int_in_42(plic_auto_int_in_42),
    .auto_int_in_43(plic_auto_int_in_43),
    .auto_int_in_44(plic_auto_int_in_44),
    .auto_int_in_45(plic_auto_int_in_45),
    .auto_int_in_46(plic_auto_int_in_46),
    .auto_int_in_47(plic_auto_int_in_47),
    .auto_int_in_48(plic_auto_int_in_48),
    .auto_int_in_49(plic_auto_int_in_49),
    .auto_int_in_50(plic_auto_int_in_50),
    .auto_int_in_51(plic_auto_int_in_51),
    .auto_int_in_52(plic_auto_int_in_52),
    .auto_int_in_53(plic_auto_int_in_53),
    .auto_int_in_54(plic_auto_int_in_54),
    .auto_int_in_55(plic_auto_int_in_55),
    .auto_int_out_1_0(plic_auto_int_out_1_0),
    .auto_int_out_0_0(plic_auto_int_out_0_0),
    .auto_in_a_ready(plic_auto_in_a_ready),
    .auto_in_a_valid(plic_auto_in_a_valid),
    .auto_in_a_bits_opcode(plic_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(plic_auto_in_a_bits_param),
    .auto_in_a_bits_size(plic_auto_in_a_bits_size),
    .auto_in_a_bits_source(plic_auto_in_a_bits_source),
    .auto_in_a_bits_address(plic_auto_in_a_bits_address),
    .auto_in_a_bits_mask(plic_auto_in_a_bits_mask),
    .auto_in_a_bits_data(plic_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(plic_auto_in_a_bits_corrupt),
    .auto_in_d_ready(plic_auto_in_d_ready),
    .auto_in_d_valid(plic_auto_in_d_valid),
    .auto_in_d_bits_opcode(plic_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(plic_auto_in_d_bits_size),
    .auto_in_d_bits_source(plic_auto_in_d_bits_source),
    .auto_in_d_bits_data(plic_auto_in_d_bits_data)
  );
  assign auto_plic_int_out_1_0 = plic_auto_int_out_1_0; // @[LazyModule.scala 311:12]
  assign auto_plic_int_out_0_0 = plic_auto_int_out_0_0; // @[LazyModule.scala 311:12]
  assign auto_plic_in_a_ready = plic_auto_in_a_ready; // @[LazyModule.scala 309:16]
  assign auto_plic_in_d_valid = plic_auto_in_d_valid; // @[LazyModule.scala 309:16]
  assign auto_plic_in_d_bits_opcode = plic_auto_in_d_bits_opcode; // @[LazyModule.scala 309:16]
  assign auto_plic_in_d_bits_size = plic_auto_in_d_bits_size; // @[LazyModule.scala 309:16]
  assign auto_plic_in_d_bits_source = plic_auto_in_d_bits_source; // @[LazyModule.scala 309:16]
  assign auto_plic_in_d_bits_data = plic_auto_in_d_bits_data; // @[LazyModule.scala 309:16]
  assign plic_clock = auto_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign plic_reset = auto_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign plic_auto_int_in_0 = auto_plic_int_in_0; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_1 = auto_plic_int_in_1; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_2 = auto_plic_int_in_2; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_3 = auto_plic_int_in_3; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_4 = auto_plic_int_in_4; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_5 = auto_plic_int_in_5; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_6 = auto_plic_int_in_6; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_7 = auto_plic_int_in_7; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_8 = auto_plic_int_in_8; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_9 = auto_plic_int_in_9; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_10 = auto_plic_int_in_10; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_11 = auto_plic_int_in_11; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_12 = auto_plic_int_in_12; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_13 = auto_plic_int_in_13; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_14 = auto_plic_int_in_14; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_15 = auto_plic_int_in_15; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_16 = auto_plic_int_in_16; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_17 = auto_plic_int_in_17; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_18 = auto_plic_int_in_18; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_19 = auto_plic_int_in_19; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_20 = auto_plic_int_in_20; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_21 = auto_plic_int_in_21; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_22 = auto_plic_int_in_22; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_23 = auto_plic_int_in_23; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_24 = auto_plic_int_in_24; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_25 = auto_plic_int_in_25; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_26 = auto_plic_int_in_26; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_27 = auto_plic_int_in_27; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_28 = auto_plic_int_in_28; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_29 = auto_plic_int_in_29; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_30 = auto_plic_int_in_30; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_31 = auto_plic_int_in_31; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_32 = auto_plic_int_in_32; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_33 = auto_plic_int_in_33; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_34 = auto_plic_int_in_34; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_35 = auto_plic_int_in_35; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_36 = auto_plic_int_in_36; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_37 = auto_plic_int_in_37; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_38 = auto_plic_int_in_38; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_39 = auto_plic_int_in_39; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_40 = auto_plic_int_in_40; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_41 = auto_plic_int_in_41; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_42 = auto_plic_int_in_42; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_43 = auto_plic_int_in_43; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_44 = auto_plic_int_in_44; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_45 = auto_plic_int_in_45; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_46 = auto_plic_int_in_46; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_47 = auto_plic_int_in_47; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_48 = auto_plic_int_in_48; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_49 = auto_plic_int_in_49; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_50 = auto_plic_int_in_50; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_51 = auto_plic_int_in_51; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_52 = auto_plic_int_in_52; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_53 = auto_plic_int_in_53; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_54 = auto_plic_int_in_54; // @[LazyModule.scala 309:16]
  assign plic_auto_int_in_55 = auto_plic_int_in_55; // @[LazyModule.scala 309:16]
  assign plic_auto_in_a_valid = auto_plic_in_a_valid; // @[LazyModule.scala 309:16]
  assign plic_auto_in_a_bits_opcode = auto_plic_in_a_bits_opcode; // @[LazyModule.scala 309:16]
  assign plic_auto_in_a_bits_param = auto_plic_in_a_bits_param; // @[LazyModule.scala 309:16]
  assign plic_auto_in_a_bits_size = auto_plic_in_a_bits_size; // @[LazyModule.scala 309:16]
  assign plic_auto_in_a_bits_source = auto_plic_in_a_bits_source; // @[LazyModule.scala 309:16]
  assign plic_auto_in_a_bits_address = auto_plic_in_a_bits_address; // @[LazyModule.scala 309:16]
  assign plic_auto_in_a_bits_mask = auto_plic_in_a_bits_mask; // @[LazyModule.scala 309:16]
  assign plic_auto_in_a_bits_data = auto_plic_in_a_bits_data; // @[LazyModule.scala 309:16]
  assign plic_auto_in_a_bits_corrupt = auto_plic_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
  assign plic_auto_in_d_ready = auto_plic_in_d_ready; // @[LazyModule.scala 309:16]
endmodule
module TLMonitor_47(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [1:0]  io_in_a_bits_size,
  input  [6:0]  io_in_a_bits_source,
  input  [25:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_size,
  input  [6:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [95:0] _RAND_10;
  reg [383:0] _RAND_11;
  reg [383:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [95:0] _RAND_16;
  reg [383:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T_4 = io_in_a_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire [4:0] _is_aligned_mask_T_1 = 5'h3 << io_in_a_bits_size; // @[package.scala 234:77]
  wire [1:0] is_aligned_mask = ~_is_aligned_mask_T_1[1:0]; // @[package.scala 234:46]
  wire [25:0] _GEN_71 = {{24'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [25:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 2'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [25:0] _T_33 = io_in_a_bits_address ^ 26'h2000000; // @[Parameters.scala 137:31]
  wire [26:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
  wire [26:0] _T_36 = $signed(_T_34) & -27'sh10000; // @[Parameters.scala 137:52]
  wire  _T_37 = $signed(_T_36) == 27'sh0; // @[Parameters.scala 137:67]
  wire  _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_74 = _T_73 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_164 = io_in_a_bits_size <= 2'h2; // @[Parameters.scala 92:42]
  wire  _T_172 = _T_164 & _T_37; // @[Parameters.scala 670:56]
  wire  _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_218 = _source_ok_T_4 & _T_172; // @[Monitor.scala 115:71]
  wire  _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_273 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_274 = io_in_a_bits_mask & _T_273; // @[Monitor.scala 127:31]
  wire  _T_275 = _T_274 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_279 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_347 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_355 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_385 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_397 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_10 = io_in_d_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire  _T_401 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_405 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 312:27]
  wire  _T_421 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_449 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_478 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_495 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_513 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [1:0] size; // @[Monitor.scala 386:22]
  reg [6:0] source; // @[Monitor.scala 387:22]
  reg [25:0] address; // @[Monitor.scala 388:22]
  wire  _T_543 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_544 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_548 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_552 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_556 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_560 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] size_1; // @[Monitor.scala 537:22]
  reg [6:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_567 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_568 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_576 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_580 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [95:0] inflight; // @[Monitor.scala 611:27]
  reg [383:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [383:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [8:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [9:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [383:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [383:0] _GEN_73 = {{368'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[383:1]}; // @[Monitor.scala 634:152]
  wire [383:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [383:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
  wire [383:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[383:1]}; // @[Monitor.scala 638:144]
  wire  _T_594 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [127:0] _a_set_wo_ready_T = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_597 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
  wire [8:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [9:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [1026:0] _GEN_1 = {{1023'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [1026:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
  wire [1025:0] _GEN_2 = {{1023'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [1025:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [95:0] _T_599 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_601 = ~_T_599[0]; // @[Monitor.scala 658:17]
  wire [127:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 652:72 653:28]
  wire [1026:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 1027'h0; // @[Monitor.scala 652:72 656:28]
  wire [1025:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 1026'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_605 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_607 = ~_T_401; // @[Monitor.scala 671:74]
  wire  _T_608 = io_in_d_valid & d_first_1 & ~_T_401; // @[Monitor.scala 671:71]
  wire [127:0] _d_clr_wo_ready_T = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [1038:0] _GEN_3 = {{1023'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [1038:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [127:0] _GEN_22 = d_first_done & d_first_1 & _T_607 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 675:91 676:21]
  wire [1038:0] _GEN_23 = d_first_done & d_first_1 & _T_607 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_594 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [95:0] _T_618 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_620 = _T_618[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_625 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_626 = io_in_d_bits_opcode == _GEN_32 | _T_625; // @[Monitor.scala 685:77]
  wire  _T_630 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_637 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_638 = io_in_d_bits_opcode == _GEN_48 | _T_637; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_642 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_652 = _T_605 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_607; // @[Monitor.scala 694:116]
  wire  _T_654 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [95:0] a_set = _GEN_16[95:0];
  wire [95:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [95:0] d_clr = _GEN_22[95:0];
  wire [95:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [95:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [383:0] a_opcodes_set = _GEN_19[383:0];
  wire [383:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [383:0] d_opcodes_clr = _GEN_23[383:0];
  wire [383:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [383:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [383:0] a_sizes_set = _GEN_20[383:0];
  wire [383:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [383:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_663 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [95:0] inflight_1; // @[Monitor.scala 723:35]
  reg [383:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [383:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [383:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
  wire [383:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[383:1]}; // @[Monitor.scala 747:146]
  wire  _T_689 = io_in_d_valid & d_first_2 & _T_401; // @[Monitor.scala 779:71]
  wire [127:0] _GEN_67 = d_first_done & d_first_2 & _T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 783:90 784:21]
  wire [1038:0] _GEN_68 = d_first_done & d_first_2 & _T_401 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 783:90 785:21]
  wire [95:0] _T_697 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_707 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [95:0] d_clr_1 = _GEN_67[95:0];
  wire [95:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [95:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [383:0] d_opcodes_clr_1 = _GEN_68[383:0];
  wire [383:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [383:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_727 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 1'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= 1'h0;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 96'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 384'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 384'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 1'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= 1'h0;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 96'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 384'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= 1'h0;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (d_first_done) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_172 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_172) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_275 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_275) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_309 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_309) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_347 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_347) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_385 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_397 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_397) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at CLINT.scala:111:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CLINT.scala:111:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CLINT.scala:111:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CLINT.scala:111:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CLINT.scala:111:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at CLINT.scala:111:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CLINT.scala:111:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CLINT.scala:111:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CLINT.scala:111:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_478 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_478 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CLINT.scala:111:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_495 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_495 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CLINT.scala:111:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_513 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_513 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CLINT.scala:111:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_544 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_544) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_548 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_548) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_552 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_552) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_556 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_556) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_560 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_560) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_568 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_568) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CLINT.scala:111:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_576 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_576) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at CLINT.scala:111:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_580 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_580) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at CLINT.scala:111:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_601 & (_T_597 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_597 & ~reset & ~_T_601) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_620 & (_T_608 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & _T_2 & ~_T_620) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CLINT.scala:111:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_626 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_626) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CLINT.scala:111:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_630 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_630) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CLINT.scala:111:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_638 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_638) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CLINT.scala:111:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_642 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_642) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CLINT.scala:111:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_654 & (_T_652 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_652 & _T_2 & ~_T_654) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_663 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_663) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_697[0] & (_T_689 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_689 & _T_2 & ~_T_697[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CLINT.scala:111:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_707 & (_T_689 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_689 & _T_2 & ~_T_707) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CLINT.scala:111:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_727 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_727) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CLINT.scala:111:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[6:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[25:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[6:0];
  _RAND_10 = {3{`RANDOM}};
  inflight = _RAND_10[95:0];
  _RAND_11 = {12{`RANDOM}};
  inflight_opcodes = _RAND_11[383:0];
  _RAND_12 = {12{`RANDOM}};
  inflight_sizes = _RAND_12[383:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {3{`RANDOM}};
  inflight_1 = _RAND_16[95:0];
  _RAND_17 = {12{`RANDOM}};
  inflight_sizes_1 = _RAND_17[383:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module CLINT(
  input         clock,
  input         reset,
  output        auto_int_out_0,
  output        auto_int_out_1,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [1:0]  auto_in_a_bits_size,
  input  [6:0]  auto_in_a_bits_source,
  input  [25:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [1:0]  auto_in_d_bits_size,
  output [6:0]  auto_in_d_bits_source,
  output [31:0] auto_in_d_bits_data,
  input         io_rtcTick
);
`ifdef RANDOMIZE_REG_INIT
  reg [63:0] _RAND_0;
  reg [63:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [25:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  reg [63:0] time_; // @[CLINT.scala 69:23]
  wire [63:0] _time_T_1 = time_ + 64'h1; // @[CLINT.scala 70:38]
  reg [63:0] timecmp_0; // @[CLINT.scala 73:41]
  reg  ipi_0; // @[CLINT.scala 74:41]
  wire [7:0] oldBytes__0 = timecmp_0[7:0]; // @[RegField.scala 151:53]
  wire [7:0] oldBytes__1 = timecmp_0[15:8]; // @[RegField.scala 151:53]
  wire [7:0] oldBytes__2 = timecmp_0[23:16]; // @[RegField.scala 151:53]
  wire [7:0] oldBytes__3 = timecmp_0[31:24]; // @[RegField.scala 151:53]
  wire [7:0] oldBytes__4 = timecmp_0[39:32]; // @[RegField.scala 151:53]
  wire [7:0] oldBytes__5 = timecmp_0[47:40]; // @[RegField.scala 151:53]
  wire [7:0] oldBytes__6 = timecmp_0[55:48]; // @[RegField.scala 151:53]
  wire [7:0] oldBytes__7 = timecmp_0[63:56]; // @[RegField.scala 151:53]
  wire  in_bits_read = auto_in_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 72:36]
  wire [13:0] in_bits_index = auto_in_a_bits_address[15:2]; // @[RegisterRouter.scala 71:18 73:19]
  wire [2:0] out_iindex = {in_bits_index[13],in_bits_index[12],in_bits_index[0]}; // @[Cat.scala 31:58]
  wire [13:0] out_findex = in_bits_index & 14'hffe; // @[RegisterRouter.scala 83:24]
  wire  _out_T_6 = out_findex == 14'hffe; // @[RegisterRouter.scala 83:24]
  wire  _out_T_2 = out_findex == 14'h0; // @[RegisterRouter.scala 83:24]
  wire [7:0] _out_backSel_T = 8'h1 << out_iindex; // @[OneHot.scala 57:35]
  wire  out_backSel_2 = _out_backSel_T[2]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_14 = auto_in_a_valid & auto_in_d_ready & ~in_bits_read & out_backSel_2 & out_findex == 14'h0; // @[RegisterRouter.scala 83:24]
  wire [7:0] _out_backMask_T_11 = auto_in_a_bits_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_backMask_T_9 = auto_in_a_bits_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_backMask_T_7 = auto_in_a_bits_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_backMask_T_5 = auto_in_a_bits_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [31:0] out_backMask = {_out_backMask_T_11,_out_backMask_T_9,_out_backMask_T_7,_out_backMask_T_5}; // @[Cat.scala 31:58]
  wire  out_womask_14 = &out_backMask[7:0]; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_14 = out_woready_14 & out_womask_14; // @[RegisterRouter.scala 83:24]
  wire  out_womask_15 = &out_backMask[15:8]; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_15 = out_woready_14 & out_womask_15; // @[RegisterRouter.scala 83:24]
  wire  out_womask_16 = &out_backMask[23:16]; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_16 = out_woready_14 & out_womask_16; // @[RegisterRouter.scala 83:24]
  wire  out_womask_17 = &out_backMask[31:24]; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_17 = out_woready_14 & out_womask_17; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_3 = _out_backSel_T[3]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_2 = auto_in_a_valid & auto_in_d_ready & ~in_bits_read & out_backSel_3 & out_findex == 14'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_2 = out_woready_2 & out_womask_14; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_3 = out_woready_2 & out_womask_15; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_4 = out_woready_2 & out_womask_16; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_5 = out_woready_2 & out_womask_17; // @[RegisterRouter.scala 83:24]
  wire [7:0] newBytes__1 = out_f_woready_15 ? auto_in_a_bits_data[15:8] : oldBytes__1; // @[RegField.scala 158:{20,33}]
  wire [7:0] newBytes__0 = out_f_woready_14 ? auto_in_a_bits_data[7:0] : oldBytes__0; // @[RegField.scala 158:{20,33}]
  wire [7:0] newBytes__3 = out_f_woready_17 ? auto_in_a_bits_data[31:24] : oldBytes__3; // @[RegField.scala 158:{20,33}]
  wire [7:0] newBytes__2 = out_f_woready_16 ? auto_in_a_bits_data[23:16] : oldBytes__2; // @[RegField.scala 158:{20,33}]
  wire [7:0] newBytes__5 = out_f_woready_3 ? auto_in_a_bits_data[15:8] : oldBytes__5; // @[RegField.scala 158:{20,33}]
  wire [7:0] newBytes__4 = out_f_woready_2 ? auto_in_a_bits_data[7:0] : oldBytes__4; // @[RegField.scala 158:{20,33}]
  wire [7:0] newBytes__7 = out_f_woready_5 ? auto_in_a_bits_data[31:24] : oldBytes__7; // @[RegField.scala 158:{20,33}]
  wire [7:0] newBytes__6 = out_f_woready_4 ? auto_in_a_bits_data[23:16] : oldBytes__6; // @[RegField.scala 158:{20,33}]
  wire [63:0] _timecmp_0_T = {newBytes__7,newBytes__6,newBytes__5,newBytes__4,newBytes__3,newBytes__2,newBytes__1,
    newBytes__0}; // @[RegField.scala 154:52]
  wire [7:0] oldBytes_1_0 = time_[7:0]; // @[RegField.scala 151:53]
  wire [7:0] oldBytes_1_1 = time_[15:8]; // @[RegField.scala 151:53]
  wire [7:0] oldBytes_1_2 = time_[23:16]; // @[RegField.scala 151:53]
  wire [7:0] oldBytes_1_3 = time_[31:24]; // @[RegField.scala 151:53]
  wire [7:0] oldBytes_1_4 = time_[39:32]; // @[RegField.scala 151:53]
  wire [7:0] oldBytes_1_5 = time_[47:40]; // @[RegField.scala 151:53]
  wire [7:0] oldBytes_1_6 = time_[55:48]; // @[RegField.scala 151:53]
  wire [7:0] oldBytes_1_7 = time_[63:56]; // @[RegField.scala 151:53]
  wire  out_backSel_4 = _out_backSel_T[4]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_6 = auto_in_a_valid & auto_in_d_ready & ~in_bits_read & out_backSel_4 & out_findex == 14'hffe; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_6 = out_woready_6 & out_womask_14; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_7 = out_woready_6 & out_womask_15; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_8 = out_woready_6 & out_womask_16; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_9 = out_woready_6 & out_womask_17; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_5 = _out_backSel_T[5]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_10 = auto_in_a_valid & auto_in_d_ready & ~in_bits_read & out_backSel_5 & out_findex == 14'hffe; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_10 = out_woready_10 & out_womask_14; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_11 = out_woready_10 & out_womask_15; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_12 = out_woready_10 & out_womask_16; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_13 = out_woready_10 & out_womask_17; // @[RegisterRouter.scala 83:24]
  wire [7:0] newBytes_1_1 = out_f_woready_7 ? auto_in_a_bits_data[15:8] : oldBytes_1_1; // @[RegField.scala 158:{20,33}]
  wire [7:0] newBytes_1_0 = out_f_woready_6 ? auto_in_a_bits_data[7:0] : oldBytes_1_0; // @[RegField.scala 158:{20,33}]
  wire [7:0] newBytes_1_3 = out_f_woready_9 ? auto_in_a_bits_data[31:24] : oldBytes_1_3; // @[RegField.scala 158:{20,33}]
  wire [7:0] newBytes_1_2 = out_f_woready_8 ? auto_in_a_bits_data[23:16] : oldBytes_1_2; // @[RegField.scala 158:{20,33}]
  wire [7:0] newBytes_1_5 = out_f_woready_11 ? auto_in_a_bits_data[15:8] : oldBytes_1_5; // @[RegField.scala 158:{20,33}]
  wire [7:0] newBytes_1_4 = out_f_woready_10 ? auto_in_a_bits_data[7:0] : oldBytes_1_4; // @[RegField.scala 158:{20,33}]
  wire [7:0] newBytes_1_7 = out_f_woready_13 ? auto_in_a_bits_data[31:24] : oldBytes_1_7; // @[RegField.scala 158:{20,33}]
  wire [7:0] newBytes_1_6 = out_f_woready_12 ? auto_in_a_bits_data[23:16] : oldBytes_1_6; // @[RegField.scala 158:{20,33}]
  wire [63:0] _time_T_2 = {newBytes_1_7,newBytes_1_6,newBytes_1_5,newBytes_1_4,newBytes_1_3,newBytes_1_2,newBytes_1_1,
    newBytes_1_0}; // @[RegField.scala 154:52]
  wire  out_wimask = &out_backMask[0]; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_0 = _out_backSel_T[0]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_0 = auto_in_a_valid & auto_in_d_ready & ~in_bits_read & out_frontSel_0 & out_findex == 14'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala 83:24]
  wire [1:0] out_prepend = {1'h0,ipi_0}; // @[Cat.scala 31:58]
  wire [31:0] _out_T_28 = {{30'd0}, out_prepend}; // @[RegisterRouter.scala 83:24]
  wire [31:0] out_prepend_3 = {oldBytes__7,oldBytes__6,oldBytes__5,oldBytes__4}; // @[Cat.scala 31:58]
  wire [31:0] out_prepend_6 = {oldBytes_1_3,oldBytes_1_2,oldBytes_1_1,oldBytes_1_0}; // @[Cat.scala 31:58]
  wire [31:0] out_prepend_9 = {oldBytes_1_7,oldBytes_1_6,oldBytes_1_5,oldBytes_1_4}; // @[Cat.scala 31:58]
  wire [31:0] out_prepend_12 = {oldBytes__3,oldBytes__2,oldBytes__1,oldBytes__0}; // @[Cat.scala 31:58]
  wire  _GEN_54 = 3'h2 == out_iindex ? _out_T_2 : 3'h1 == out_iindex | _out_T_2; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_55 = 3'h3 == out_iindex ? _out_T_2 : _GEN_54; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_56 = 3'h4 == out_iindex ? _out_T_6 : _GEN_55; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_57 = 3'h5 == out_iindex ? _out_T_6 : _GEN_56; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_59 = 3'h7 == out_iindex | (3'h6 == out_iindex | _GEN_57); // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_61 = 3'h1 == out_iindex ? 32'h0 : _out_T_28; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_62 = 3'h2 == out_iindex ? out_prepend_12 : _GEN_61; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_63 = 3'h3 == out_iindex ? out_prepend_3 : _GEN_62; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_64 = 3'h4 == out_iindex ? out_prepend_6 : _GEN_63; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_65 = 3'h5 == out_iindex ? out_prepend_9 : _GEN_64; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_66 = 3'h6 == out_iindex ? 32'h0 : _GEN_65; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_67 = 3'h7 == out_iindex ? 32'h0 : _GEN_66; // @[MuxLiteral.scala 48:{10,10}]
  TLMonitor_47 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  assign auto_int_out_0 = ipi_0; // @[CLINT.scala 78:37]
  assign auto_int_out_1 = time_ >= timecmp_0; // @[CLINT.scala 79:43]
  assign auto_in_a_ready = auto_in_d_ready; // @[RegisterRouter.scala 83:24]
  assign auto_in_d_valid = auto_in_a_valid; // @[RegisterRouter.scala 83:24]
  assign auto_in_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign auto_in_d_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_in_d_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_in_d_bits_data = _GEN_59 ? _GEN_67 : 32'h0; // @[RegisterRouter.scala 83:24]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = auto_in_d_ready; // @[RegisterRouter.scala 83:24]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_in_a_valid; // @[RegisterRouter.scala 83:24]
  assign monitor_io_in_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign monitor_io_in_d_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  always @(posedge clock) begin
    if (reset) begin // @[CLINT.scala 69:23]
      time_ <= 64'h0; // @[CLINT.scala 69:23]
    end else if (out_f_woready_6 | out_f_woready_7 | out_f_woready_8 | out_f_woready_9 | out_f_woready_10 |
      out_f_woready_11 | out_f_woready_12 | out_f_woready_13) begin // @[RegField.scala 154:34]
      time_ <= _time_T_2; // @[RegField.scala 154:40]
    end else if (io_rtcTick) begin // @[CLINT.scala 70:23]
      time_ <= _time_T_1; // @[CLINT.scala 70:30]
    end
    if (out_f_woready_14 | out_f_woready_15 | out_f_woready_16 | out_f_woready_17 | out_f_woready_2 | out_f_woready_3 |
      out_f_woready_4 | out_f_woready_5) begin // @[RegField.scala 154:34]
      timecmp_0 <= _timecmp_0_T; // @[RegField.scala 154:40]
    end
    if (reset) begin // @[CLINT.scala 74:41]
      ipi_0 <= 1'h0; // @[CLINT.scala 74:41]
    end else if (out_f_wivalid) begin // @[RegField.scala 74:88]
      ipi_0 <= auto_in_a_bits_data[0]; // @[RegField.scala 74:92]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {2{`RANDOM}};
  time_ = _RAND_0[63:0];
  _RAND_1 = {2{`RANDOM}};
  timecmp_0 = _RAND_1[63:0];
  _RAND_2 = {1{`RANDOM}};
  ipi_0 = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLMonitor_48(
  input        clock,
  input        reset,
  input        io_in_a_ready,
  input        io_in_a_valid,
  input  [2:0] io_in_a_bits_opcode,
  input  [8:0] io_in_a_bits_address,
  input        io_in_d_ready,
  input        io_in_d_valid,
  input  [2:0] io_in_d_bits_opcode,
  input  [1:0] io_in_d_bits_param,
  input  [1:0] io_in_d_bits_size,
  input        io_in_d_bits_sink,
  input        io_in_d_bits_denied,
  input        io_in_d_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire [8:0] _is_aligned_T = io_in_a_bits_address & 9'h3; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala 20:24]
  wire [9:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
  wire  _T_15 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [9:0] _T_23 = $signed(_T_7) & 10'sh200; // @[Parameters.scala 137:52]
  wire  _T_24 = $signed(_T_23) == 10'sh0; // @[Parameters.scala 137:67]
  wire  _T_69 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_127 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_167 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_201 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire  _T_236 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_266 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_296 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_330 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _T_334 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_338 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 312:27]
  wire  _T_342 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
  wire  _T_346 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
  wire  _T_350 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
  wire  _T_354 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_365 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
  wire  _T_369 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
  wire  _T_382 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_402 = _T_350 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
  wire  _T_411 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_428 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_446 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [8:0] address; // @[Monitor.scala 388:22]
  wire  _T_476 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_477 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_493 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] param_1; // @[Monitor.scala 536:22]
  reg [1:0] size_1; // @[Monitor.scala 537:22]
  reg  sink; // @[Monitor.scala 539:22]
  reg  denied; // @[Monitor.scala 540:22]
  wire  _T_500 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_501 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_505 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
  wire  _T_509 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_517 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
  wire  _T_521 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
  reg  inflight; // @[Monitor.scala 611:27]
  reg [3:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [3:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_71 = {{12'd0}, inflight_opcodes}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_71 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [15:0] _GEN_73 = {{12'd0}, inflight_sizes}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_527 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire  _T_530 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [18:0] _a_opcodes_set_T_1 = {{15'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? 3'h5 : 3'h0; // @[Monitor.scala 652:72 655:28]
  wire [17:0] _a_sizes_set_T_1 = {{15'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire  _T_534 = ~inflight; // @[Monitor.scala 658:17]
  wire [1:0] _GEN_16 = a_first_done & a_first_1 ? 2'h1 : 2'h0; // @[Monitor.scala 652:72 653:28]
  wire [18:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 656:28]
  wire [17:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 18'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_538 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_540 = ~_T_334; // @[Monitor.scala 671:74]
  wire  _T_541 = io_in_d_valid & d_first_1 & ~_T_334; // @[Monitor.scala 671:71]
  wire [30:0] _d_opcodes_clr_T_5 = {{15'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [1:0] _GEN_22 = d_first_done & d_first_1 & _T_540 ? 2'h1 : 2'h0; // @[Monitor.scala 675:91 676:21]
  wire [30:0] _GEN_23 = d_first_done & d_first_1 & _T_540 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 677:21]
  wire  _T_553 = inflight | _T_527; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_558 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_559 = io_in_d_bits_opcode == _GEN_32 | _T_558; // @[Monitor.scala 685:77]
  wire  _T_563 = 2'h2 == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_570 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_571 = io_in_d_bits_opcode == _GEN_48 | _T_570; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_75 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_575 = _GEN_75 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_585 = _T_538 & a_first_1 & io_in_a_valid & _T_540; // @[Monitor.scala 694:116]
  wire  _T_587 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire  a_set = _GEN_16[0];
  wire  d_clr = _GEN_22[0];
  wire [3:0] a_opcodes_set = _GEN_19[3:0];
  wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [3:0] d_opcodes_clr = _GEN_23[3:0];
  wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [3:0] a_sizes_set = _GEN_20[3:0];
  wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_596 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [3:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [15:0] _GEN_78 = {{12'd0}, inflight_sizes_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_78 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_622 = io_in_d_valid & d_first_2 & _T_334; // @[Monitor.scala 779:71]
  wire [30:0] _GEN_68 = d_first_done & d_first_2 & _T_334 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 783:90 785:21]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_640 = _GEN_75 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [3:0] d_opcodes_clr_1 = _GEN_68[3:0];
  wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [3:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 1'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= 1'h0;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 1'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= (inflight | a_set) & ~d_clr; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 4'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 4'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 1'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= 1'h0;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 4'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= 1'h0;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at Debug.scala:628:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Debug.scala:628:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Debug.scala:628:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_69 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_69 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at Debug.scala:628:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_69 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_69 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Debug.scala:628:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_69 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_69 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Debug.scala:628:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_69 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_69 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Debug.scala:628:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_24 & (io_in_a_valid & _T_127 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_127 & ~reset & ~_T_24) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at Debug.scala:628:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_127 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_127 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at Debug.scala:628:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_24 & (io_in_a_valid & _T_167 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_167 & ~reset & ~_T_24) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at Debug.scala:628:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_167 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_167 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Debug.scala:628:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_201 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_201 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at Debug.scala:628:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_201 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_201 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Debug.scala:628:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at Debug.scala:628:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Debug.scala:628:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_266 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_266 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at Debug.scala:628:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_266 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_266 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at Debug.scala:628:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_296 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_296 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at Debug.scala:628:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_296 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_296 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at Debug.scala:628:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_330 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_330) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at Debug.scala:628:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_338 & (io_in_d_valid & _T_334 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_334 & _T_2 & ~_T_338) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Debug.scala:628:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_342 & (io_in_d_valid & _T_334 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_334 & _T_2 & ~_T_342) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Debug.scala:628:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_346 & (io_in_d_valid & _T_334 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_334 & _T_2 & ~_T_346) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at Debug.scala:628:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_350 & (io_in_d_valid & _T_334 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_334 & _T_2 & ~_T_350) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is denied (connected at Debug.scala:628:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_354 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_354 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Debug.scala:628:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_338 & (io_in_d_valid & _T_354 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_354 & _T_2 & ~_T_338) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at Debug.scala:628:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_365 & (io_in_d_valid & _T_354 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_354 & _T_2 & ~_T_365) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid cap param (connected at Debug.scala:628:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_369 & (io_in_d_valid & _T_354 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_354 & _T_2 & ~_T_369) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries toN param (connected at Debug.scala:628:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_346 & (io_in_d_valid & _T_354 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_354 & _T_2 & ~_T_346) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is corrupt (connected at Debug.scala:628:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_382 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_382 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Debug.scala:628:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_338 & (io_in_d_valid & _T_382 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_382 & _T_2 & ~_T_338) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Debug.scala:628:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_365 & (io_in_d_valid & _T_382 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_382 & _T_2 & ~_T_365) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Debug.scala:628:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_369 & (io_in_d_valid & _T_382 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_382 & _T_2 & ~_T_369) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries toN param (connected at Debug.scala:628:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_402 & (io_in_d_valid & _T_382 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_382 & _T_2 & ~_T_402) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at Debug.scala:628:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_342 & (io_in_d_valid & _T_411 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_411 & _T_2 & ~_T_342) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid param (connected at Debug.scala:628:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_346 & (io_in_d_valid & _T_411 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_411 & _T_2 & ~_T_346) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is corrupt (connected at Debug.scala:628:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_342 & (io_in_d_valid & _T_428 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_428 & _T_2 & ~_T_342) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Debug.scala:628:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_402 & (io_in_d_valid & _T_428 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_428 & _T_2 & ~_T_402) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at Debug.scala:628:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_342 & (io_in_d_valid & _T_446 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_446 & _T_2 & ~_T_342) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid param (connected at Debug.scala:628:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_346 & (io_in_d_valid & _T_446 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_446 & _T_2 & ~_T_346) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is corrupt (connected at Debug.scala:628:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_477 & (_T_476 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_476 & ~reset & ~_T_477) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Debug.scala:628:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_493 & (_T_476 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_476 & ~reset & ~_T_493) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at Debug.scala:628:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_501 & (_T_500 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_500 & _T_2 & ~_T_501) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Debug.scala:628:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_505 & (_T_500 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_500 & _T_2 & ~_T_505) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel param changed within multibeat operation (connected at Debug.scala:628:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_509 & (_T_500 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_500 & _T_2 & ~_T_509) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at Debug.scala:628:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_517 & (_T_500 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_500 & _T_2 & ~_T_517) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel sink changed with multibeat operation (connected at Debug.scala:628:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_521 & (_T_500 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_500 & _T_2 & ~_T_521) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel denied changed with multibeat operation (connected at Debug.scala:628:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_534 & (_T_530 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_530 & ~reset & ~_T_534) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at Debug.scala:628:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_553 & (_T_541 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_541 & _T_2 & ~_T_553) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Debug.scala:628:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_559 & (_T_541 & _T_527 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_541 & _T_527 & _T_2 & ~_T_559) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Debug.scala:628:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_563 & (_T_541 & _T_527 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_541 & _T_527 & _T_2 & ~_T_563) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Debug.scala:628:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_571 & (_T_541 & ~_T_527 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_541 & ~_T_527 & _T_2 & ~_T_571) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Debug.scala:628:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_575 & (_T_541 & ~_T_527 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_541 & ~_T_527 & _T_2 & ~_T_575) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Debug.scala:628:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_587 & (_T_585 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_585 & _T_2 & ~_T_587) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_596 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_596) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Debug.scala:628:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_622 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_622 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Debug.scala:628:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_640 & (_T_622 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_622 & _T_2 & ~_T_640) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Debug.scala:628:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  address = _RAND_2[8:0];
  _RAND_3 = {1{`RANDOM}};
  d_first_counter = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  opcode_1 = _RAND_4[2:0];
  _RAND_5 = {1{`RANDOM}};
  param_1 = _RAND_5[1:0];
  _RAND_6 = {1{`RANDOM}};
  size_1 = _RAND_6[1:0];
  _RAND_7 = {1{`RANDOM}};
  sink = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  denied = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  inflight = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  inflight_opcodes = _RAND_10[3:0];
  _RAND_11 = {1{`RANDOM}};
  inflight_sizes = _RAND_11[3:0];
  _RAND_12 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  watchdog = _RAND_14[31:0];
  _RAND_15 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_15[3:0];
  _RAND_16 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_16[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLXbar_9(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [8:0]  auto_in_a_bits_address,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output        auto_in_d_bits_denied,
  output [31:0] auto_in_d_bits_data,
  output        auto_in_d_bits_corrupt,
  input         auto_out_1_a_ready,
  output        auto_out_1_a_valid,
  output [2:0]  auto_out_1_a_bits_opcode,
  output [6:0]  auto_out_1_a_bits_address,
  output [31:0] auto_out_1_a_bits_data,
  output        auto_out_1_d_ready,
  input         auto_out_1_d_valid,
  input  [2:0]  auto_out_1_d_bits_opcode,
  input  [31:0] auto_out_1_d_bits_data,
  input         auto_out_0_a_ready,
  output        auto_out_0_a_valid,
  output [2:0]  auto_out_0_a_bits_opcode,
  output [8:0]  auto_out_0_a_bits_address,
  output [31:0] auto_out_0_a_bits_data,
  output        auto_out_0_d_ready,
  input         auto_out_0_d_valid,
  input  [2:0]  auto_out_0_d_bits_opcode,
  input  [1:0]  auto_out_0_d_bits_param,
  input  [1:0]  auto_out_0_d_bits_size,
  input         auto_out_0_d_bits_sink,
  input         auto_out_0_d_bits_denied,
  input  [31:0] auto_out_0_d_bits_data,
  input         auto_out_0_d_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [8:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
  wire [9:0] _requestAIO_T_1 = {1'b0,$signed(auto_in_a_bits_address)}; // @[Parameters.scala 137:49]
  wire [9:0] _requestAIO_T_3 = $signed(_requestAIO_T_1) & 10'sh1c0; // @[Parameters.scala 137:52]
  wire  _requestAIO_T_4 = $signed(_requestAIO_T_3) == 10'sh0; // @[Parameters.scala 137:67]
  wire [8:0] _requestAIO_T_5 = auto_in_a_bits_address ^ 9'h44; // @[Parameters.scala 137:31]
  wire [9:0] _requestAIO_T_6 = {1'b0,$signed(_requestAIO_T_5)}; // @[Parameters.scala 137:49]
  wire [9:0] _requestAIO_T_8 = $signed(_requestAIO_T_6) & 10'sh1f4; // @[Parameters.scala 137:52]
  wire  _requestAIO_T_9 = $signed(_requestAIO_T_8) == 10'sh0; // @[Parameters.scala 137:67]
  wire [8:0] _requestAIO_T_10 = auto_in_a_bits_address ^ 9'h58; // @[Parameters.scala 137:31]
  wire [9:0] _requestAIO_T_11 = {1'b0,$signed(_requestAIO_T_10)}; // @[Parameters.scala 137:49]
  wire [9:0] _requestAIO_T_13 = $signed(_requestAIO_T_11) & 10'sh1f8; // @[Parameters.scala 137:52]
  wire  _requestAIO_T_14 = $signed(_requestAIO_T_13) == 10'sh0; // @[Parameters.scala 137:67]
  wire [8:0] _requestAIO_T_15 = auto_in_a_bits_address ^ 9'h60; // @[Parameters.scala 137:31]
  wire [9:0] _requestAIO_T_16 = {1'b0,$signed(_requestAIO_T_15)}; // @[Parameters.scala 137:49]
  wire [9:0] _requestAIO_T_18 = $signed(_requestAIO_T_16) & 10'sh1e0; // @[Parameters.scala 137:52]
  wire  _requestAIO_T_19 = $signed(_requestAIO_T_18) == 10'sh0; // @[Parameters.scala 137:67]
  wire [8:0] _requestAIO_T_20 = auto_in_a_bits_address ^ 9'h80; // @[Parameters.scala 137:31]
  wire [9:0] _requestAIO_T_21 = {1'b0,$signed(_requestAIO_T_20)}; // @[Parameters.scala 137:49]
  wire [9:0] _requestAIO_T_23 = $signed(_requestAIO_T_21) & 10'sh180; // @[Parameters.scala 137:52]
  wire  _requestAIO_T_24 = $signed(_requestAIO_T_23) == 10'sh0; // @[Parameters.scala 137:67]
  wire [8:0] _requestAIO_T_25 = auto_in_a_bits_address ^ 9'h100; // @[Parameters.scala 137:31]
  wire [9:0] _requestAIO_T_26 = {1'b0,$signed(_requestAIO_T_25)}; // @[Parameters.scala 137:49]
  wire [9:0] _requestAIO_T_28 = $signed(_requestAIO_T_26) & 10'sh100; // @[Parameters.scala 137:52]
  wire  _requestAIO_T_29 = $signed(_requestAIO_T_28) == 10'sh0; // @[Parameters.scala 137:67]
  wire  requestAIO_0_0 = _requestAIO_T_4 | _requestAIO_T_9 | _requestAIO_T_14 | _requestAIO_T_19 | _requestAIO_T_24 |
    _requestAIO_T_29; // @[Xbar.scala 363:92]
  wire [8:0] _requestAIO_T_35 = auto_in_a_bits_address ^ 9'h40; // @[Parameters.scala 137:31]
  wire [9:0] _requestAIO_T_36 = {1'b0,$signed(_requestAIO_T_35)}; // @[Parameters.scala 137:49]
  wire [9:0] _requestAIO_T_38 = $signed(_requestAIO_T_36) & 10'sh1f4; // @[Parameters.scala 137:52]
  wire  _requestAIO_T_39 = $signed(_requestAIO_T_38) == 10'sh0; // @[Parameters.scala 137:67]
  wire [8:0] _requestAIO_T_40 = auto_in_a_bits_address ^ 9'h50; // @[Parameters.scala 137:31]
  wire [9:0] _requestAIO_T_41 = {1'b0,$signed(_requestAIO_T_40)}; // @[Parameters.scala 137:49]
  wire [9:0] _requestAIO_T_43 = $signed(_requestAIO_T_41) & 10'sh1f8; // @[Parameters.scala 137:52]
  wire  _requestAIO_T_44 = $signed(_requestAIO_T_43) == 10'sh0; // @[Parameters.scala 137:67]
  wire  requestAIO_0_1 = _requestAIO_T_39 | _requestAIO_T_44; // @[Xbar.scala 363:92]
  reg  beatsLeft; // @[Arbiter.scala 87:30]
  wire  idle = ~beatsLeft; // @[Arbiter.scala 88:28]
  wire  latch = idle & auto_in_d_ready; // @[Arbiter.scala 89:24]
  wire [1:0] readys_valid = {auto_out_1_d_valid,auto_out_0_d_valid}; // @[Cat.scala 31:58]
  wire  _readys_T_3 = ~reset; // @[Arbiter.scala 22:12]
  reg [1:0] readys_mask; // @[Arbiter.scala 23:23]
  wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala 24:30]
  wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala 24:28]
  wire [3:0] readys_filter = {_readys_filter_T_1,auto_out_1_d_valid,auto_out_0_d_valid}; // @[Cat.scala 31:58]
  wire [3:0] _GEN_1 = {{1'd0}, readys_filter[3:1]}; // @[package.scala 253:43]
  wire [3:0] _readys_unready_T_1 = readys_filter | _GEN_1; // @[package.scala 253:43]
  wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala 25:66]
  wire [3:0] _GEN_2 = {{1'd0}, _readys_unready_T_1[3:1]}; // @[Arbiter.scala 25:58]
  wire [3:0] readys_unready = _GEN_2 | _readys_unready_T_4; // @[Arbiter.scala 25:58]
  wire [1:0] _readys_readys_T_2 = readys_unready[3:2] & readys_unready[1:0]; // @[Arbiter.scala 26:39]
  wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala 26:18]
  wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala 28:29]
  wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala 244:48]
  wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_1[1:0]; // @[package.scala 244:43]
  wire  readys_0 = readys_readys[0]; // @[Arbiter.scala 95:86]
  wire  readys_1 = readys_readys[1]; // @[Arbiter.scala 95:86]
  wire  earlyWinner_0 = readys_0 & auto_out_0_d_valid; // @[Arbiter.scala 97:79]
  wire  earlyWinner_1 = readys_1 & auto_out_1_d_valid; // @[Arbiter.scala 97:79]
  wire  _prefixOR_T = earlyWinner_0 | earlyWinner_1; // @[Arbiter.scala 104:53]
  wire  _T_10 = auto_out_0_d_valid | auto_out_1_d_valid; // @[Arbiter.scala 107:36]
  wire  _T_11 = ~(auto_out_0_d_valid | auto_out_1_d_valid); // @[Arbiter.scala 107:15]
  reg  state_0; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_0 = idle ? earlyWinner_0 : state_0; // @[Arbiter.scala 117:30]
  reg  state_1; // @[Arbiter.scala 116:26]
  wire  muxStateEarly_1 = idle ? earlyWinner_1 : state_1; // @[Arbiter.scala 117:30]
  wire  _sink_ACancel_earlyValid_T_3 = state_0 & auto_out_0_d_valid | state_1 & auto_out_1_d_valid; // @[Mux.scala 27:73]
  wire  sink_ACancel_5_earlyValid = idle ? _T_10 : _sink_ACancel_earlyValid_T_3; // @[Arbiter.scala 125:29]
  wire  _beatsLeft_T_2 = auto_in_d_ready & sink_ACancel_5_earlyValid; // @[ReadyValidCancel.scala 49:33]
  wire  allowed_0 = idle ? readys_0 : state_0; // @[Arbiter.scala 121:24]
  wire  allowed_1 = idle ? readys_1 : state_1; // @[Arbiter.scala 121:24]
  wire [31:0] _T_27 = muxStateEarly_0 ? auto_out_0_d_bits_data : 32'h0; // @[Mux.scala 27:73]
  wire [31:0] _T_28 = muxStateEarly_1 ? auto_out_1_d_bits_data : 32'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_39 = muxStateEarly_0 ? auto_out_0_d_bits_size : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _T_40 = muxStateEarly_1 ? 2'h2 : 2'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_45 = muxStateEarly_0 ? auto_out_0_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  wire [2:0] _T_46 = muxStateEarly_1 ? auto_out_1_d_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  TLMonitor_48 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_param(monitor_io_in_d_bits_param),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
    .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
    .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
  );
  assign auto_in_a_ready = requestAIO_0_0 & auto_out_0_a_ready | requestAIO_0_1 & auto_out_1_a_ready; // @[Mux.scala 27:73]
  assign auto_in_d_valid = idle ? _T_10 : _sink_ACancel_earlyValid_T_3; // @[Arbiter.scala 125:29]
  assign auto_in_d_bits_denied = muxStateEarly_0 & auto_out_0_d_bits_denied; // @[Mux.scala 27:73]
  assign auto_in_d_bits_data = _T_27 | _T_28; // @[Mux.scala 27:73]
  assign auto_in_d_bits_corrupt = muxStateEarly_0 & auto_out_0_d_bits_corrupt; // @[Mux.scala 27:73]
  assign auto_out_1_a_valid = auto_in_a_valid & requestAIO_0_1; // @[Xbar.scala 428:50]
  assign auto_out_1_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_a_bits_address = auto_in_a_bits_address[6:0]; // @[Xbar.scala 132:50 BundleMap.scala 247:19]
  assign auto_out_1_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_d_ready = auto_in_d_ready & allowed_1; // @[Arbiter.scala 123:31]
  assign auto_out_0_a_valid = auto_in_a_valid & requestAIO_0_0; // @[Xbar.scala 428:50]
  assign auto_out_0_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_0_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_0_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_0_d_ready = auto_in_d_ready & allowed_0; // @[Arbiter.scala 123:31]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = requestAIO_0_0 & auto_out_0_a_ready | requestAIO_0_1 & auto_out_1_a_ready; // @[Mux.scala 27:73]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = idle ? _T_10 : _sink_ACancel_earlyValid_T_3; // @[Arbiter.scala 125:29]
  assign monitor_io_in_d_bits_opcode = _T_45 | _T_46; // @[Mux.scala 27:73]
  assign monitor_io_in_d_bits_param = muxStateEarly_0 ? auto_out_0_d_bits_param : 2'h0; // @[Mux.scala 27:73]
  assign monitor_io_in_d_bits_size = _T_39 | _T_40; // @[Mux.scala 27:73]
  assign monitor_io_in_d_bits_sink = muxStateEarly_0 & auto_out_0_d_bits_sink; // @[Mux.scala 27:73]
  assign monitor_io_in_d_bits_denied = muxStateEarly_0 & auto_out_0_d_bits_denied; // @[Mux.scala 27:73]
  assign monitor_io_in_d_bits_corrupt = muxStateEarly_0 & auto_out_0_d_bits_corrupt; // @[Mux.scala 27:73]
  always @(posedge clock) begin
    if (reset) begin // @[Arbiter.scala 87:30]
      beatsLeft <= 1'h0; // @[Arbiter.scala 87:30]
    end else if (latch) begin // @[Arbiter.scala 113:23]
      beatsLeft <= 1'h0;
    end else begin
      beatsLeft <= beatsLeft - _beatsLeft_T_2;
    end
    if (reset) begin // @[Arbiter.scala 23:23]
      readys_mask <= 2'h3; // @[Arbiter.scala 23:23]
    end else if (latch & |readys_valid) begin // @[Arbiter.scala 27:32]
      readys_mask <= _readys_mask_T_3; // @[Arbiter.scala 28:12]
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_0 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_0 <= earlyWinner_0;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_1 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle) begin // @[Arbiter.scala 117:30]
      state_1 <= earlyWinner_1;
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~earlyWinner_0 | ~earlyWinner_1) & _readys_T_3) begin
          $fatal; // @[Arbiter.scala 105:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_readys_T_3 & ~(~earlyWinner_0 | ~earlyWinner_1)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:105 assert((prefixOR zip earlyWinner) map { case (p,w) => !p || !w } reduce {_ && _})\n"
            ); // @[Arbiter.scala 105:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(auto_out_0_d_valid | auto_out_1_d_valid) | _prefixOR_T) & _readys_T_3) begin
          $fatal; // @[Arbiter.scala 107:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_readys_T_3 & ~(~(auto_out_0_d_valid | auto_out_1_d_valid) | _prefixOR_T)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:107 assert (!earlyValids.reduce(_||_) || earlyWinner.reduce(_||_))\n"
            ); // @[Arbiter.scala 107:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_11 | _T_10) & _readys_T_3) begin
          $fatal; // @[Arbiter.scala 108:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_readys_T_3 & ~(_T_11 | _T_10)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:108 assert (!validQuals .reduce(_||_) || validQuals .reduce(_||_))\n"
            ); // @[Arbiter.scala 108:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  beatsLeft = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  readys_mask = _RAND_1[1:0];
  _RAND_2 = {1{`RANDOM}};
  state_0 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  state_1 = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module DMIToTL(
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [8:0]  auto_out_a_bits_address,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input         auto_out_d_bits_denied,
  input  [31:0] auto_out_d_bits_data,
  input         auto_out_d_bits_corrupt,
  output        io_dmi_req_ready,
  input         io_dmi_req_valid,
  input  [6:0]  io_dmi_req_bits_addr,
  input  [31:0] io_dmi_req_bits_data,
  input  [1:0]  io_dmi_req_bits_op,
  input         io_dmi_resp_ready,
  output        io_dmi_resp_valid,
  output [31:0] io_dmi_resp_bits_data,
  output [1:0]  io_dmi_resp_bits_resp
);
  wire [8:0] addr = {io_dmi_req_bits_addr, 2'h0}; // @[DMI.scala 94:46]
  wire [8:0] _GEN_3 = io_dmi_req_bits_op == 2'h1 ? addr : 9'h48; // @[DMI.scala 109:{64,76} 110:76]
  wire [2:0] _GEN_7 = io_dmi_req_bits_op == 2'h1 ? 3'h4 : 3'h0; // @[DMI.scala 109:{64,76} 110:76]
  wire  _io_dmi_resp_bits_resp_T = auto_out_d_bits_corrupt | auto_out_d_bits_denied; // @[DMI.scala 118:53]
  assign auto_out_a_valid = io_dmi_req_valid; // @[DMI.scala 113:22 Nodes.scala 1207:84]
  assign auto_out_a_bits_opcode = io_dmi_req_bits_op == 2'h2 ? 3'h0 : _GEN_7; // @[DMI.scala 108:{64,76}]
  assign auto_out_a_bits_address = io_dmi_req_bits_op == 2'h2 ? addr : _GEN_3; // @[DMI.scala 108:{64,76}]
  assign auto_out_a_bits_data = io_dmi_req_bits_op == 2'h2 ? io_dmi_req_bits_data : 32'h0; // @[DMI.scala 108:{64,76}]
  assign auto_out_d_ready = io_dmi_resp_ready; // @[DMI.scala 117:28 Nodes.scala 1207:84]
  assign io_dmi_req_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign io_dmi_resp_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign io_dmi_resp_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign io_dmi_resp_bits_resp = {{1'd0}, _io_dmi_resp_bits_resp_T}; // @[DMI.scala 118:28]
endmodule
module TLMonitor_49(
  input        clock,
  input        reset,
  input        io_in_a_ready,
  input        io_in_a_valid,
  input  [2:0] io_in_a_bits_opcode,
  input  [6:0] io_in_a_bits_address,
  input        io_in_d_ready,
  input        io_in_d_valid,
  input  [2:0] io_in_d_bits_opcode
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire [6:0] _is_aligned_T = io_in_a_bits_address & 7'h3; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 7'h0; // @[Edges.scala 20:24]
  wire  _T_15 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [6:0] _T_20 = io_in_a_bits_address ^ 7'h40; // @[Parameters.scala 137:31]
  wire [7:0] _T_21 = {1'b0,$signed(_T_20)}; // @[Parameters.scala 137:49]
  wire [7:0] _T_23 = $signed(_T_21) & -8'shc; // @[Parameters.scala 137:52]
  wire  _T_24 = $signed(_T_23) == 8'sh0; // @[Parameters.scala 137:67]
  wire [6:0] _T_25 = io_in_a_bits_address ^ 7'h50; // @[Parameters.scala 137:31]
  wire [7:0] _T_26 = {1'b0,$signed(_T_25)}; // @[Parameters.scala 137:49]
  wire [7:0] _T_28 = $signed(_T_26) & -8'sh8; // @[Parameters.scala 137:52]
  wire  _T_29 = $signed(_T_28) == 8'sh0; // @[Parameters.scala 137:67]
  wire  _T_30 = _T_24 | _T_29; // @[Parameters.scala 671:42]
  wire  _T_81 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_151 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_197 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_237 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire  _T_278 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_314 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_350 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_390 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _T_394 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_414 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_442 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [6:0] address; // @[Monitor.scala 388:22]
  wire  _T_536 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_537 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_553 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  wire  _T_560 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_561 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  reg  inflight; // @[Monitor.scala 611:27]
  reg [3:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [3:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_71 = {{12'd0}, inflight_opcodes}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_71 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [15:0] _GEN_73 = {{12'd0}, inflight_sizes}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_587 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire  _T_590 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [18:0] _a_opcodes_set_T_1 = {{15'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? 3'h5 : 3'h0; // @[Monitor.scala 652:72 655:28]
  wire [17:0] _a_sizes_set_T_1 = {{15'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire  _T_594 = ~inflight; // @[Monitor.scala 658:17]
  wire [1:0] _GEN_16 = a_first_done & a_first_1 ? 2'h1 : 2'h0; // @[Monitor.scala 652:72 653:28]
  wire [18:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 656:28]
  wire [17:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 18'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_598 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_600 = ~_T_394; // @[Monitor.scala 671:74]
  wire  _T_601 = io_in_d_valid & d_first_1 & ~_T_394; // @[Monitor.scala 671:71]
  wire [30:0] _d_opcodes_clr_T_5 = {{15'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [1:0] _GEN_22 = d_first_done & d_first_1 & _T_600 ? 2'h1 : 2'h0; // @[Monitor.scala 675:91 676:21]
  wire [30:0] _GEN_23 = d_first_done & d_first_1 & _T_600 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 677:21]
  wire  _T_613 = inflight | _T_587; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_618 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_619 = io_in_d_bits_opcode == _GEN_32 | _T_618; // @[Monitor.scala 685:77]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_630 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_631 = io_in_d_bits_opcode == _GEN_48 | _T_630; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire  _T_635 = 4'h2 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_645 = _T_598 & a_first_1 & io_in_a_valid & _T_600; // @[Monitor.scala 694:116]
  wire  _T_647 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire  a_set = _GEN_16[0];
  wire  d_clr = _GEN_22[0];
  wire [3:0] a_opcodes_set = _GEN_19[3:0];
  wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [3:0] d_opcodes_clr = _GEN_23[3:0];
  wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [3:0] a_sizes_set = _GEN_20[3:0];
  wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_656 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [3:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [15:0] _GEN_77 = {{12'd0}, inflight_sizes_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_77 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_682 = io_in_d_valid & d_first_2 & _T_394; // @[Monitor.scala 779:71]
  wire [30:0] _GEN_68 = d_first_done & d_first_2 & _T_394 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 783:90 785:21]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_700 = 4'h2 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [3:0] d_opcodes_clr_1 = _GEN_68[3:0];
  wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [3:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 1'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= 1'h0;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 1'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= (inflight | a_set) & ~d_clr; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 4'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 4'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 1'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= 1'h0;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 4'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= 1'h0;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at Debug.scala:654:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Debug.scala:654:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Debug.scala:654:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_81 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_81 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at Debug.scala:654:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_81 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_81 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Debug.scala:654:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_81 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_81 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Debug.scala:654:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_81 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_81 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Debug.scala:654:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_30 & (io_in_a_valid & _T_151 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_151 & ~reset & ~_T_30) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at Debug.scala:654:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_151 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_151 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at Debug.scala:654:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_30 & (io_in_a_valid & _T_197 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_197 & ~reset & ~_T_30) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at Debug.scala:654:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_197 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_197 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Debug.scala:654:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_237 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_237 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at Debug.scala:654:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_237 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_237 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Debug.scala:654:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_278 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_278 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at Debug.scala:654:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_278 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_278 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Debug.scala:654:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_314 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_314 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at Debug.scala:654:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_314 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_314 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at Debug.scala:654:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_350 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_350 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at Debug.scala:654:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_350 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_350 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at Debug.scala:654:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_390 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_390) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at Debug.scala:654:19)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_414 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_414 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Debug.scala:654:19)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_442 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_442 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Debug.scala:654:19)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_537 & (_T_536 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_536 & ~reset & ~_T_537) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Debug.scala:654:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_553 & (_T_536 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_536 & ~reset & ~_T_553) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at Debug.scala:654:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_561 & (_T_560 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_560 & _T_2 & ~_T_561) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Debug.scala:654:19)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_594 & (_T_590 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & ~reset & ~_T_594) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at Debug.scala:654:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_613 & (_T_601 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_601 & _T_2 & ~_T_613) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Debug.scala:654:19)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_619 & (_T_601 & _T_587 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_601 & _T_587 & _T_2 & ~_T_619) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Debug.scala:654:19)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_631 & (_T_601 & ~_T_587 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_601 & ~_T_587 & _T_2 & ~_T_631) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Debug.scala:654:19)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_635 & (_T_601 & ~_T_587 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_601 & ~_T_587 & _T_2 & ~_T_635) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Debug.scala:654:19)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_647 & (_T_645 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_645 & _T_2 & ~_T_647) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_656 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_656) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Debug.scala:654:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_682 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_682 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Debug.scala:654:19)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_700 & (_T_682 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_682 & _T_2 & ~_T_700) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Debug.scala:654:19)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  address = _RAND_2[6:0];
  _RAND_3 = {1{`RANDOM}};
  d_first_counter = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  opcode_1 = _RAND_4[2:0];
  _RAND_5 = {1{`RANDOM}};
  inflight = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  inflight_opcodes = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  inflight_sizes = _RAND_7[3:0];
  _RAND_8 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  watchdog = _RAND_10[31:0];
  _RAND_11 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_11[3:0];
  _RAND_12 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_12[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLDebugModuleOuter(
  input         clock,
  input         reset,
  output        auto_dmi_in_a_ready,
  input         auto_dmi_in_a_valid,
  input  [2:0]  auto_dmi_in_a_bits_opcode,
  input  [6:0]  auto_dmi_in_a_bits_address,
  input  [31:0] auto_dmi_in_a_bits_data,
  input         auto_dmi_in_d_ready,
  output        auto_dmi_in_d_valid,
  output [2:0]  auto_dmi_in_d_bits_opcode,
  output [31:0] auto_dmi_in_d_bits_data,
  output        auto_int_out_0,
  output        io_ctrl_ndreset,
  output        io_ctrl_dmactive,
  input         io_ctrl_dmactiveAck,
  input         io_innerCtrl_ready,
  output        io_innerCtrl_valid,
  output        io_innerCtrl_bits_resumereq,
  output [9:0]  io_innerCtrl_bits_hartsel,
  output        io_innerCtrl_bits_ackhavereset,
  output        io_innerCtrl_bits_hrmask_0,
  input         io_hgDebugInt_0
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [6:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  reg  DMCONTROLReg_haltreq; // @[Debug.scala 336:31]
  reg  DMCONTROLReg_ndmreset; // @[Debug.scala 336:31]
  reg  DMCONTROLReg_dmactive; // @[Debug.scala 336:31]
  wire  _T_1 = ~DMCONTROLReg_dmactive; // @[Debug.scala 354:11]
  wire  in_bits_read = auto_dmi_in_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 72:36]
  wire [2:0] in_bits_index = auto_dmi_in_a_bits_address[4:2]; // @[RegisterRouter.scala 71:18 73:19]
  wire  out_iindex = in_bits_index[1]; // @[RegisterRouter.scala 83:24]
  wire [2:0] out_findex = in_bits_index & 3'h5; // @[RegisterRouter.scala 83:24]
  wire  _out_T = out_findex == 3'h0; // @[RegisterRouter.scala 83:24]
  wire [1:0] _out_backSel_T = 2'h1 << out_iindex; // @[OneHot.scala 57:35]
  wire  out_backSel_0 = _out_backSel_T[0]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_6 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_0 & out_findex == 3'h0; // @[RegisterRouter.scala 83:24]
  wire  DMCONTROLWrData_ndmreset = auto_dmi_in_a_bits_data[1]; // @[RegisterRouter.scala 83:24]
  wire  DMCONTROLWrData_haltreq = auto_dmi_in_a_bits_data[31]; // @[RegisterRouter.scala 83:24]
  wire  DMCONTROLWrData_dmactive = auto_dmi_in_a_bits_data[0]; // @[RegisterRouter.scala 83:24]
  reg  hrmaskReg_0; // @[Debug.scala 471:28]
  wire  DMCONTROLWrData_clrresethaltreq = auto_dmi_in_a_bits_data[2]; // @[RegisterRouter.scala 83:24]
  wire  _T_11 = io_innerCtrl_bits_hartsel == 10'h0; // @[Debug.scala 400:35]
  wire  DMCONTROLWrData_setresethaltreq = auto_dmi_in_a_bits_data[3]; // @[RegisterRouter.scala 83:24]
  wire  _GEN_23 = out_woready_6 & DMCONTROLWrData_setresethaltreq & _T_11 | hrmaskReg_0; // @[Debug.scala 479:102 473:15 480:30]
  wire  _GEN_24 = out_woready_6 & DMCONTROLWrData_clrresethaltreq & _T_11 ? 1'h0 : _GEN_23; // @[Debug.scala 477:102 478:30]
  wire  _T_18 = DMCONTROLReg_dmactive & io_ctrl_dmactiveAck; // @[Debug.scala 487:43]
  wire [4:0] out_prepend_7 = {1'h0,1'h0,1'h0,DMCONTROLReg_ndmreset,_T_18}; // @[Cat.scala 31:58]
  wire [15:0] _out_T_96 = {{11'd0}, out_prepend_7}; // @[RegisterRouter.scala 83:24]
  wire [17:0] out_prepend_9 = {1'h0,1'h0,_out_T_96}; // @[Cat.scala 31:58]
  wire [25:0] _out_T_114 = {{8'd0}, out_prepend_9}; // @[RegisterRouter.scala 83:24]
  wire  DMCONTROLWrData_ackhavereset = auto_dmi_in_a_bits_data[28]; // @[RegisterRouter.scala 83:24]
  wire  DMCONTROLWrData_resumereq = auto_dmi_in_a_bits_data[30]; // @[RegisterRouter.scala 83:24]
  wire [31:0] out_prepend_15 = {DMCONTROLReg_haltreq,1'h0,1'h0,1'h0,1'h0,1'h0,_out_T_114}; // @[Cat.scala 31:58]
  wire  _GEN_35 = out_iindex ? _out_T : _out_T; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_37 = out_iindex ? 32'h111380 : out_prepend_15; // @[MuxLiteral.scala 48:{10,10}]
  reg  debugIntRegs_0; // @[Debug.scala 552:31]
  reg  innerCtrlValidReg; // @[Debug.scala 583:36]
  reg  innerCtrlResumeReqReg; // @[Debug.scala 584:40]
  reg  innerCtrlAckHaveResetReg; // @[Debug.scala 585:43]
  wire  _innerCtrlValidReg_T = ~io_innerCtrl_ready; // @[Debug.scala 590:54]
  TLMonitor_49 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode)
  );
  assign auto_dmi_in_a_ready = auto_dmi_in_d_ready; // @[RegisterRouter.scala 83:24]
  assign auto_dmi_in_d_valid = auto_dmi_in_a_valid; // @[RegisterRouter.scala 83:24]
  assign auto_dmi_in_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign auto_dmi_in_d_bits_data = _GEN_35 ? _GEN_37 : 32'h0; // @[RegisterRouter.scala 83:24]
  assign auto_int_out_0 = debugIntRegs_0 | io_hgDebugInt_0; // @[Debug.scala 558:60]
  assign io_ctrl_ndreset = DMCONTROLReg_ndmreset; // @[Debug.scala 604:21]
  assign io_ctrl_dmactive = DMCONTROLReg_dmactive; // @[Debug.scala 605:22]
  assign io_innerCtrl_valid = out_woready_6 | innerCtrlValidReg; // @[Debug.scala 594:54]
  assign io_innerCtrl_bits_resumereq = out_woready_6 & DMCONTROLWrData_resumereq | innerCtrlResumeReqReg; // @[Debug.scala 596:83]
  assign io_innerCtrl_bits_hartsel = 10'h0; // @[Debug.scala 595:42]
  assign io_innerCtrl_bits_ackhavereset = out_woready_6 & DMCONTROLWrData_ackhavereset | innerCtrlAckHaveResetReg; // @[Debug.scala 597:89]
  assign io_innerCtrl_bits_hrmask_0 = _T_1 ? 1'h0 : _GEN_24; // @[Debug.scala 475:44 476:30]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = auto_dmi_in_d_ready; // @[RegisterRouter.scala 83:24]
  assign monitor_io_in_a_valid = auto_dmi_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_dmi_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_dmi_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_dmi_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_dmi_in_a_valid; // @[RegisterRouter.scala 83:24]
  assign monitor_io_in_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[Debug.scala 354:22]
      DMCONTROLReg_haltreq <= 1'h0; // @[Debug.scala 355:20]
    end else if (~DMCONTROLReg_dmactive) begin // @[Debug.scala 361:47]
      DMCONTROLReg_haltreq <= 1'h0; // @[Debug.scala 361:75]
    end else if (out_woready_6) begin // @[Debug.scala 353:18]
      DMCONTROLReg_haltreq <= DMCONTROLWrData_haltreq;
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[Debug.scala 354:22]
      DMCONTROLReg_ndmreset <= 1'h0; // @[Debug.scala 355:20]
    end else if (~DMCONTROLReg_dmactive) begin // @[Debug.scala 357:47]
      DMCONTROLReg_ndmreset <= 1'h0; // @[Debug.scala 357:75]
    end else if (out_woready_6) begin // @[Debug.scala 353:18]
      DMCONTROLReg_ndmreset <= DMCONTROLWrData_ndmreset;
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[Debug.scala 365:25]
      DMCONTROLReg_dmactive <= 1'h0; // @[Debug.scala 366:29]
    end else if (out_woready_6) begin // @[Debug.scala 354:22]
      DMCONTROLReg_dmactive <= DMCONTROLWrData_dmactive; // @[Debug.scala 355:20]
    end else if (~DMCONTROLReg_dmactive) begin // @[Debug.scala 353:18]
      DMCONTROLReg_dmactive <= 1'h0;
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[Debug.scala 475:44]
      hrmaskReg_0 <= 1'h0; // @[Debug.scala 476:30]
    end else if (_T_1) begin // @[Debug.scala 477:102]
      hrmaskReg_0 <= 1'h0; // @[Debug.scala 478:30]
    end else if (out_woready_6 & DMCONTROLWrData_clrresethaltreq & _T_11) begin
      hrmaskReg_0 <= 1'h0;
    end else begin
      hrmaskReg_0 <= _GEN_23;
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[Debug.scala 568:44]
      debugIntRegs_0 <= 1'h0; // @[Debug.scala 569:32]
    end else if (_T_1) begin // @[Debug.scala 572:96]
      debugIntRegs_0 <= 1'h0; // @[Debug.scala 573:34]
    end else if (out_woready_6) begin // @[Debug.scala 554:17]
      debugIntRegs_0 <= DMCONTROLWrData_haltreq;
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[Debug.scala 590:52]
      innerCtrlValidReg <= 1'h0;
    end else begin
      innerCtrlValidReg <= io_innerCtrl_valid & ~io_innerCtrl_ready;
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[Debug.scala 591:61]
      innerCtrlResumeReqReg <= 1'h0;
    end else begin
      innerCtrlResumeReqReg <= io_innerCtrl_bits_resumereq & _innerCtrlValidReg_T;
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[Debug.scala 592:64]
      innerCtrlAckHaveResetReg <= 1'h0;
    end else begin
      innerCtrlAckHaveResetReg <= io_innerCtrl_bits_ackhavereset & _innerCtrlValidReg_T;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  DMCONTROLReg_haltreq = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  DMCONTROLReg_ndmreset = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  DMCONTROLReg_dmactive = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  hrmaskReg_0 = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  debugIntRegs_0 = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  innerCtrlValidReg = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  innerCtrlResumeReqReg = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  innerCtrlAckHaveResetReg = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
  if (reset) begin
    DMCONTROLReg_haltreq = 1'h0;
  end
  if (reset) begin
    DMCONTROLReg_ndmreset = 1'h0;
  end
  if (reset) begin
    DMCONTROLReg_dmactive = 1'h0;
  end
  if (reset) begin
    hrmaskReg_0 = 1'h0;
  end
  if (reset) begin
    debugIntRegs_0 = 1'h0;
  end
  if (reset) begin
    innerCtrlValidReg = 1'h0;
  end
  if (reset) begin
    innerCtrlResumeReqReg = 1'h0;
  end
  if (reset) begin
    innerCtrlAckHaveResetReg = 1'h0;
  end
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module IntSyncCrossingSource_4(
  input   auto_in_0,
  output  auto_out_sync_0
);
  assign auto_out_sync_0 = auto_in_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module TLMonitor_50(
  input        clock,
  input        reset,
  input        io_in_a_ready,
  input        io_in_a_valid,
  input  [2:0] io_in_a_bits_opcode,
  input  [8:0] io_in_a_bits_address,
  input        io_in_d_ready,
  input        io_in_d_valid,
  input  [2:0] io_in_d_bits_opcode,
  input  [1:0] io_in_d_bits_param,
  input  [1:0] io_in_d_bits_size,
  input        io_in_d_bits_source,
  input        io_in_d_bits_sink,
  input        io_in_d_bits_denied,
  input        io_in_d_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire [8:0] _is_aligned_T = io_in_a_bits_address & 9'h3; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala 20:24]
  wire [9:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
  wire  _T_15 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [9:0] _T_23 = $signed(_T_7) & -10'sh40; // @[Parameters.scala 137:52]
  wire  _T_24 = $signed(_T_23) == 10'sh0; // @[Parameters.scala 137:67]
  wire [8:0] _T_25 = io_in_a_bits_address ^ 9'h44; // @[Parameters.scala 137:31]
  wire [9:0] _T_26 = {1'b0,$signed(_T_25)}; // @[Parameters.scala 137:49]
  wire [9:0] _T_28 = $signed(_T_26) & -10'shc; // @[Parameters.scala 137:52]
  wire  _T_29 = $signed(_T_28) == 10'sh0; // @[Parameters.scala 137:67]
  wire [8:0] _T_30 = io_in_a_bits_address ^ 9'h58; // @[Parameters.scala 137:31]
  wire [9:0] _T_31 = {1'b0,$signed(_T_30)}; // @[Parameters.scala 137:49]
  wire [9:0] _T_33 = $signed(_T_31) & -10'sh8; // @[Parameters.scala 137:52]
  wire  _T_34 = $signed(_T_33) == 10'sh0; // @[Parameters.scala 137:67]
  wire [8:0] _T_35 = io_in_a_bits_address ^ 9'h60; // @[Parameters.scala 137:31]
  wire [9:0] _T_36 = {1'b0,$signed(_T_35)}; // @[Parameters.scala 137:49]
  wire [9:0] _T_38 = $signed(_T_36) & -10'sh20; // @[Parameters.scala 137:52]
  wire  _T_39 = $signed(_T_38) == 10'sh0; // @[Parameters.scala 137:67]
  wire [8:0] _T_40 = io_in_a_bits_address ^ 9'h80; // @[Parameters.scala 137:31]
  wire [9:0] _T_41 = {1'b0,$signed(_T_40)}; // @[Parameters.scala 137:49]
  wire [9:0] _T_43 = $signed(_T_41) & -10'sh80; // @[Parameters.scala 137:52]
  wire  _T_44 = $signed(_T_43) == 10'sh0; // @[Parameters.scala 137:67]
  wire [8:0] _T_45 = io_in_a_bits_address ^ 9'h100; // @[Parameters.scala 137:31]
  wire [9:0] _T_46 = {1'b0,$signed(_T_45)}; // @[Parameters.scala 137:49]
  wire [9:0] _T_48 = $signed(_T_46) & -10'sh100; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 10'sh0; // @[Parameters.scala 137:67]
  wire  _T_54 = _T_24 | _T_29 | _T_34 | _T_39 | _T_44 | _T_49; // @[Parameters.scala 671:42]
  wire  _T_129 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_247 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_317 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_381 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire  _T_446 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_506 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_566 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_630 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_1 = ~io_in_d_bits_source; // @[Parameters.scala 46:9]
  wire  _T_634 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_638 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 312:27]
  wire  _T_642 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
  wire  _T_646 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
  wire  _T_650 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
  wire  _T_654 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_665 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
  wire  _T_669 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
  wire  _T_682 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_702 = _T_650 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
  wire  _T_711 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_728 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_746 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [8:0] address; // @[Monitor.scala 388:22]
  wire  _T_776 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_777 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_793 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] param_1; // @[Monitor.scala 536:22]
  reg [1:0] size_1; // @[Monitor.scala 537:22]
  reg  source_1; // @[Monitor.scala 538:22]
  reg  sink; // @[Monitor.scala 539:22]
  reg  denied; // @[Monitor.scala 540:22]
  wire  _T_800 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_801 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_805 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
  wire  _T_809 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_813 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  wire  _T_817 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
  wire  _T_821 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
  reg  inflight; // @[Monitor.scala 611:27]
  reg [3:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [3:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [2:0] _GEN_71 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [3:0] _a_opcode_lookup_T = {{1'd0}, _GEN_71}; // @[Monitor.scala 634:69]
  wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_72 = {{12'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_72 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [3:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _GEN_75 = {{12'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_75 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_827 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire  _T_830 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [18:0] _a_opcodes_set_T_1 = {{15'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? 3'h5 : 3'h0; // @[Monitor.scala 652:72 655:28]
  wire [17:0] _a_sizes_set_T_1 = {{15'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire  _T_834 = ~inflight; // @[Monitor.scala 658:17]
  wire [1:0] _GEN_16 = a_first_done & a_first_1 ? 2'h1 : 2'h0; // @[Monitor.scala 652:72 653:28]
  wire [18:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 656:28]
  wire [17:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 18'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_838 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_840 = ~_T_634; // @[Monitor.scala 671:74]
  wire  _T_841 = io_in_d_valid & d_first_1 & ~_T_634; // @[Monitor.scala 671:71]
  wire [1:0] _d_clr_wo_ready_T = 2'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [30:0] _GEN_1 = {{15'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [30:0] _d_opcodes_clr_T_5 = _GEN_1 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [1:0] _GEN_22 = d_first_done & d_first_1 & _T_840 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 675:91 676:21]
  wire [30:0] _GEN_23 = d_first_done & d_first_1 & _T_840 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 677:21]
  wire  same_cycle_resp = _T_827 & _source_ok_T_1; // @[Monitor.scala 681:88]
  wire  _T_853 = inflight >> io_in_d_bits_source | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_858 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_859 = io_in_d_bits_opcode == _GEN_32 | _T_858; // @[Monitor.scala 685:77]
  wire  _T_863 = 2'h2 == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_870 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_871 = io_in_d_bits_opcode == _GEN_48 | _T_870; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_79 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_875 = _GEN_79 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_885 = _T_838 & a_first_1 & io_in_a_valid & _source_ok_T_1 & _T_840; // @[Monitor.scala 694:116]
  wire  _T_887 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire  a_set = _GEN_16[0];
  wire  d_clr = _GEN_22[0];
  wire [3:0] a_opcodes_set = _GEN_19[3:0];
  wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [3:0] d_opcodes_clr = _GEN_23[3:0];
  wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [3:0] a_sizes_set = _GEN_20[3:0];
  wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_896 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [3:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [15:0] _GEN_84 = {{12'd0}, _c_size_lookup_T_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_84 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_922 = io_in_d_valid & d_first_2 & _T_634; // @[Monitor.scala 779:71]
  wire [30:0] _GEN_68 = d_first_done & d_first_2 & _T_634 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 783:90 785:21]
  wire  _T_930 = 1'h0 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_940 = _GEN_79 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [3:0] d_opcodes_clr_1 = _GEN_68[3:0];
  wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [3:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 1'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= 1'h0;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 1'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= (inflight | a_set) & ~d_clr; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 4'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 4'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 1'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= 1'h0;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 4'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= 1'h0;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at BusBypass.scala:32:12)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BusBypass.scala:32:12)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BusBypass.scala:32:12)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_129 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_129 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at BusBypass.scala:32:12)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_129 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_129 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BusBypass.scala:32:12)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_129 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_129 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BusBypass.scala:32:12)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_129 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_129 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BusBypass.scala:32:12)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_54 & (io_in_a_valid & _T_247 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_247 & ~reset & ~_T_54) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at BusBypass.scala:32:12)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_247 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_247 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at BusBypass.scala:32:12)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_54 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_54) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at BusBypass.scala:32:12)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at BusBypass.scala:32:12)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_381 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_381 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at BusBypass.scala:32:12)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_381 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_381 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BusBypass.scala:32:12)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_446 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_446 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at BusBypass.scala:32:12)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_446 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_446 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BusBypass.scala:32:12)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_506 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_506 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at BusBypass.scala:32:12)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_506 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_506 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at BusBypass.scala:32:12)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_566 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_566 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at BusBypass.scala:32:12)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_566 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at BusBypass.scala:32:12)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_630 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_630) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_1 & (io_in_d_valid & _T_634 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_634 & _T_2 & ~_source_ok_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_638 & (io_in_d_valid & _T_634 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_634 & _T_2 & ~_T_638) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_642 & (io_in_d_valid & _T_634 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_634 & _T_2 & ~_T_642) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_646 & (io_in_d_valid & _T_634 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_634 & _T_2 & ~_T_646) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_650 & (io_in_d_valid & _T_634 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_634 & _T_2 & ~_T_650) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is denied (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_1 & (io_in_d_valid & _T_654 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_654 & _T_2 & ~_source_ok_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_654 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_654 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_638 & (io_in_d_valid & _T_654 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_654 & _T_2 & ~_T_638) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_665 & (io_in_d_valid & _T_654 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_654 & _T_2 & ~_T_665) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid cap param (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_669 & (io_in_d_valid & _T_654 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_654 & _T_2 & ~_T_669) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries toN param (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_646 & (io_in_d_valid & _T_654 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_654 & _T_2 & ~_T_646) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is corrupt (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_1 & (io_in_d_valid & _T_682 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_682 & _T_2 & ~_source_ok_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_682 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_682 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_638 & (io_in_d_valid & _T_682 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_682 & _T_2 & ~_T_638) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_665 & (io_in_d_valid & _T_682 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_682 & _T_2 & ~_T_665) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_669 & (io_in_d_valid & _T_682 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_682 & _T_2 & ~_T_669) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries toN param (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_702 & (io_in_d_valid & _T_682 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_682 & _T_2 & ~_T_702) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_1 & (io_in_d_valid & _T_711 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_711 & _T_2 & ~_source_ok_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_642 & (io_in_d_valid & _T_711 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_711 & _T_2 & ~_T_642) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid param (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_646 & (io_in_d_valid & _T_711 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_711 & _T_2 & ~_T_646) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is corrupt (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_1 & (io_in_d_valid & _T_728 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_728 & _T_2 & ~_source_ok_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_642 & (io_in_d_valid & _T_728 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_728 & _T_2 & ~_T_642) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_702 & (io_in_d_valid & _T_728 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_728 & _T_2 & ~_T_702) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_1 & (io_in_d_valid & _T_746 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_746 & _T_2 & ~_source_ok_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_642 & (io_in_d_valid & _T_746 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_746 & _T_2 & ~_T_642) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid param (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_646 & (io_in_d_valid & _T_746 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_746 & _T_2 & ~_T_646) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is corrupt (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_777 & (_T_776 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_776 & ~reset & ~_T_777) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BusBypass.scala:32:12)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_793 & (_T_776 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_776 & ~reset & ~_T_793) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at BusBypass.scala:32:12)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_801 & (_T_800 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_800 & _T_2 & ~_T_801) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_805 & (_T_800 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_800 & _T_2 & ~_T_805) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel param changed within multibeat operation (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_809 & (_T_800 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_800 & _T_2 & ~_T_809) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_813 & (_T_800 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_800 & _T_2 & ~_T_813) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_817 & (_T_800 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_800 & _T_2 & ~_T_817) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel sink changed with multibeat operation (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_821 & (_T_800 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_800 & _T_2 & ~_T_821) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel denied changed with multibeat operation (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_834 & (_T_830 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_830 & ~reset & ~_T_834) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at BusBypass.scala:32:12)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_853 & (_T_841 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_841 & _T_2 & ~_T_853) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_859 & (_T_841 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_841 & same_cycle_resp & _T_2 & ~_T_859) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_863 & (_T_841 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_841 & same_cycle_resp & _T_2 & ~_T_863) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_871 & (_T_841 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_841 & ~same_cycle_resp & _T_2 & ~_T_871) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_875 & (_T_841 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_841 & ~same_cycle_resp & _T_2 & ~_T_875) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_887 & (_T_885 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_885 & _T_2 & ~_T_887) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_896 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_896) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at BusBypass.scala:32:12)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_930 & (_T_922 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_922 & _T_2 & ~_T_930) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_940 & (_T_922 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_922 & _T_2 & ~_T_940) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at BusBypass.scala:32:12)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  address = _RAND_2[8:0];
  _RAND_3 = {1{`RANDOM}};
  d_first_counter = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  opcode_1 = _RAND_4[2:0];
  _RAND_5 = {1{`RANDOM}};
  param_1 = _RAND_5[1:0];
  _RAND_6 = {1{`RANDOM}};
  size_1 = _RAND_6[1:0];
  _RAND_7 = {1{`RANDOM}};
  source_1 = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  sink = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  denied = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  inflight = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  inflight_opcodes = _RAND_11[3:0];
  _RAND_12 = {1{`RANDOM}};
  inflight_sizes = _RAND_12[3:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_16[3:0];
  _RAND_17 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_17[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLBusBypassBar(
  input          clock,
  input          reset,
  output         auto_in_a_ready,
  input          auto_in_a_valid,
  input  [2:0]   auto_in_a_bits_opcode,
  input  [8:0]   auto_in_a_bits_address,
  input  [31:0]  auto_in_a_bits_data,
  input          auto_in_d_ready,
  output         auto_in_d_valid,
  output [2:0]   auto_in_d_bits_opcode,
  output [1:0]   auto_in_d_bits_param,
  output [1:0]   auto_in_d_bits_size,
  output         auto_in_d_bits_sink,
  output         auto_in_d_bits_denied,
  output [31:0]  auto_in_d_bits_data,
  output         auto_in_d_bits_corrupt,
  input          auto_out_1_a_ready,
  output         auto_out_1_a_valid,
  output [2:0]   auto_out_1_a_bits_opcode,
  output [8:0]   auto_out_1_a_bits_address,
  output [31:0]  auto_out_1_a_bits_data,
  output         auto_out_1_d_ready,
  input          auto_out_1_d_valid,
  input  [2:0]   auto_out_1_d_bits_opcode,
  input  [1:0]   auto_out_1_d_bits_param,
  input  [1:0]   auto_out_1_d_bits_size,
  input          auto_out_1_d_bits_source,
  input          auto_out_1_d_bits_sink,
  input          auto_out_1_d_bits_denied,
  input  [31:0]  auto_out_1_d_bits_data,
  input          auto_out_1_d_bits_corrupt,
  input          auto_out_0_a_ready,
  output         auto_out_0_a_valid,
  output [2:0]   auto_out_0_a_bits_opcode,
  output [127:0] auto_out_0_a_bits_address,
  output         auto_out_0_d_ready,
  input          auto_out_0_d_valid,
  input  [2:0]   auto_out_0_d_bits_opcode,
  input  [1:0]   auto_out_0_d_bits_size,
  input          auto_out_0_d_bits_denied,
  input          auto_out_0_d_bits_corrupt,
  input          io_bypass
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [8:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
  reg  in_reset; // @[BusBypass.scala 77:27]
  reg  bypass_reg; // @[BusBypass.scala 78:25]
  wire  bypass = in_reset ? io_bypass : bypass_reg; // @[BusBypass.scala 79:21]
  reg [1:0] flight; // @[Edges.scala 294:25]
  reg  stall_counter; // @[Edges.scala 228:27]
  wire  stall_first = ~stall_counter; // @[Edges.scala 230:25]
  wire  stall = bypass != io_bypass & stall_first; // @[BusBypass.scala 84:40]
  wire  _bundleIn_0_a_ready_T = ~stall; // @[BusBypass.scala 88:21]
  wire  _bundleIn_0_a_ready_T_1 = bypass ? auto_out_0_a_ready : auto_out_1_a_ready; // @[BusBypass.scala 88:34]
  wire  in_a_ready = ~stall & _bundleIn_0_a_ready_T_1; // @[BusBypass.scala 88:28]
  wire  done = in_a_ready & auto_in_a_valid; // @[Decoupled.scala 50:35]
  reg  counter; // @[Edges.scala 228:27]
  wire  counter1 = counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~counter; // @[Edges.scala 230:25]
  wire  in_d_valid = bypass ? auto_out_0_d_valid : auto_out_1_d_valid; // @[BusBypass.scala 94:24]
  wire  done_3 = auto_in_d_ready & in_d_valid; // @[Decoupled.scala 50:35]
  wire [2:0] in_d_bits_opcode = bypass ? auto_out_0_d_bits_opcode : auto_out_1_d_bits_opcode; // @[BusBypass.scala 96:21]
  reg  counter_3; // @[Edges.scala 228:27]
  wire  counter1_3 = counter_3 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~counter_3; // @[Edges.scala 230:25]
  wire  d_request = in_d_bits_opcode[2] & ~in_d_bits_opcode[1]; // @[Edges.scala 70:40]
  wire  a_inc = done & a_first; // @[Edges.scala 309:28]
  wire  d_inc = done_3 & d_first & d_request; // @[Edges.scala 312:39]
  wire [1:0] inc = {a_inc,d_inc}; // @[Cat.scala 31:58]
  wire [1:0] dec = {1'h0,done_3}; // @[Cat.scala 31:58]
  wire [1:0] _next_flight_T_2 = inc[0] + inc[1]; // @[Bitwise.scala 48:55]
  wire [1:0] _next_flight_T_5 = flight + _next_flight_T_2; // @[Edges.scala 323:30]
  wire [1:0] _next_flight_T_8 = dec[0] + dec[1]; // @[Bitwise.scala 48:55]
  wire [1:0] next_flight = _next_flight_T_5 - _next_flight_T_8; // @[Edges.scala 323:46]
  wire  stall_counter1 = stall_counter - 1'h1; // @[Edges.scala 229:28]
  wire  _bundleOut_0_a_valid_T_1 = _bundleIn_0_a_ready_T & auto_in_a_valid; // @[BusBypass.scala 86:28]
  wire  _bundleOut_1_a_valid_T_2 = ~bypass; // @[BusBypass.scala 87:45]
  TLMonitor_50 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_param(monitor_io_in_d_bits_param),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source),
    .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
    .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
    .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
  );
  assign auto_in_a_ready = ~stall & _bundleIn_0_a_ready_T_1; // @[BusBypass.scala 88:28]
  assign auto_in_d_valid = bypass ? auto_out_0_d_valid : auto_out_1_d_valid; // @[BusBypass.scala 94:24]
  assign auto_in_d_bits_opcode = bypass ? auto_out_0_d_bits_opcode : auto_out_1_d_bits_opcode; // @[BusBypass.scala 96:21]
  assign auto_in_d_bits_param = bypass ? 2'h0 : auto_out_1_d_bits_param; // @[BusBypass.scala 96:21]
  assign auto_in_d_bits_size = bypass ? auto_out_0_d_bits_size : auto_out_1_d_bits_size; // @[BusBypass.scala 96:21]
  assign auto_in_d_bits_sink = bypass ? 1'h0 : auto_out_1_d_bits_sink; // @[BusBypass.scala 96:21]
  assign auto_in_d_bits_denied = bypass ? auto_out_0_d_bits_denied : auto_out_1_d_bits_denied; // @[BusBypass.scala 96:21]
  assign auto_in_d_bits_data = bypass ? 32'h0 : auto_out_1_d_bits_data; // @[BusBypass.scala 96:21]
  assign auto_in_d_bits_corrupt = bypass ? auto_out_0_d_bits_corrupt : auto_out_1_d_bits_corrupt; // @[BusBypass.scala 96:21]
  assign auto_out_1_a_valid = _bundleOut_0_a_valid_T_1 & ~bypass; // @[BusBypass.scala 87:42]
  assign auto_out_1_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1_d_ready = auto_in_d_ready & _bundleOut_1_a_valid_T_2; // @[BusBypass.scala 93:32]
  assign auto_out_0_a_valid = _bundleIn_0_a_ready_T & auto_in_a_valid & bypass; // @[BusBypass.scala 86:42]
  assign auto_out_0_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_0_a_bits_address = {{119'd0}, auto_in_a_bits_address}; // @[Nodes.scala 1207:84 BusBypass.scala 89:18]
  assign auto_out_0_d_ready = auto_in_d_ready & bypass; // @[BusBypass.scala 92:32]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = ~stall & _bundleIn_0_a_ready_T_1; // @[BusBypass.scala 88:28]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = bypass ? auto_out_0_d_valid : auto_out_1_d_valid; // @[BusBypass.scala 94:24]
  assign monitor_io_in_d_bits_opcode = bypass ? auto_out_0_d_bits_opcode : auto_out_1_d_bits_opcode; // @[BusBypass.scala 96:21]
  assign monitor_io_in_d_bits_param = bypass ? 2'h0 : auto_out_1_d_bits_param; // @[BusBypass.scala 96:21]
  assign monitor_io_in_d_bits_size = bypass ? auto_out_0_d_bits_size : auto_out_1_d_bits_size; // @[BusBypass.scala 96:21]
  assign monitor_io_in_d_bits_source = bypass ? 1'h0 : auto_out_1_d_bits_source; // @[BusBypass.scala 96:21]
  assign monitor_io_in_d_bits_sink = bypass ? 1'h0 : auto_out_1_d_bits_sink; // @[BusBypass.scala 96:21]
  assign monitor_io_in_d_bits_denied = bypass ? auto_out_0_d_bits_denied : auto_out_1_d_bits_denied; // @[BusBypass.scala 96:21]
  assign monitor_io_in_d_bits_corrupt = bypass ? auto_out_0_d_bits_corrupt : auto_out_1_d_bits_corrupt; // @[BusBypass.scala 96:21]
  always @(posedge clock) begin
    in_reset <= reset; // @[BusBypass.scala 77:{27,27,27}]
    if (in_reset | next_flight == 2'h0) begin // @[BusBypass.scala 83:50]
      bypass_reg <= io_bypass; // @[BusBypass.scala 83:63]
    end
    if (reset) begin // @[Edges.scala 294:25]
      flight <= 2'h0; // @[Edges.scala 294:25]
    end else begin
      flight <= next_flight; // @[Edges.scala 324:12]
    end
    if (reset) begin // @[Edges.scala 228:27]
      stall_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (done) begin // @[Edges.scala 234:17]
      if (stall_first) begin // @[Edges.scala 235:21]
        stall_counter <= 1'h0;
      end else begin
        stall_counter <= stall_counter1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (done) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        counter <= 1'h0;
      end else begin
        counter <= counter1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      counter_3 <= 1'h0; // @[Edges.scala 228:27]
    end else if (done_3) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        counter_3 <= 1'h0;
      end else begin
        counter_3 <= counter1_3;
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  in_reset = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  bypass_reg = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  flight = _RAND_2[1:0];
  _RAND_3 = {1{`RANDOM}};
  stall_counter = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  counter = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  counter_3 = _RAND_5[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLMonitor_51(
  input          clock,
  input          reset,
  input          io_in_a_ready,
  input          io_in_a_valid,
  input  [2:0]   io_in_a_bits_opcode,
  input  [127:0] io_in_a_bits_address,
  input          io_in_d_ready,
  input          io_in_d_valid,
  input  [2:0]   io_in_d_bits_opcode,
  input  [1:0]   io_in_d_bits_size,
  input          io_in_d_bits_denied,
  input          io_in_d_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [127:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire [127:0] _is_aligned_T = io_in_a_bits_address & 128'h3; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 128'h0; // @[Edges.scala 20:24]
  wire [128:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
  wire  _T_15 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [128:0] _T_26 = $signed(_T_7) & 129'sh100000000000000000000000000000000; // @[Parameters.scala 137:52]
  wire  _T_27 = $signed(_T_26) == 129'sh0; // @[Parameters.scala 137:67]
  wire  _T_72 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_133 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_173 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_207 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire  _T_242 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_272 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_302 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_339 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _T_343 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_347 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 312:27]
  wire  _T_355 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
  wire  _T_359 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
  wire  _T_363 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_391 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_411 = _T_359 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
  wire  _T_420 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_437 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_455 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [127:0] address; // @[Monitor.scala 388:22]
  wire  _T_485 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_486 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_502 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] size_1; // @[Monitor.scala 537:22]
  reg  denied; // @[Monitor.scala 540:22]
  wire  _T_509 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_510 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_518 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_530 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
  reg  inflight; // @[Monitor.scala 611:27]
  reg [3:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [3:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_71 = {{12'd0}, inflight_opcodes}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_71 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [15:0] _GEN_73 = {{12'd0}, inflight_sizes}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_536 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire  _T_539 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [18:0] _a_opcodes_set_T_1 = {{15'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? 3'h5 : 3'h0; // @[Monitor.scala 652:72 655:28]
  wire [17:0] _a_sizes_set_T_1 = {{15'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire  _T_543 = ~inflight; // @[Monitor.scala 658:17]
  wire [1:0] _GEN_16 = a_first_done & a_first_1 ? 2'h1 : 2'h0; // @[Monitor.scala 652:72 653:28]
  wire [18:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 656:28]
  wire [17:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 18'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_547 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_549 = ~_T_343; // @[Monitor.scala 671:74]
  wire  _T_550 = io_in_d_valid & d_first_1 & ~_T_343; // @[Monitor.scala 671:71]
  wire [30:0] _d_opcodes_clr_T_5 = {{15'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [1:0] _GEN_22 = d_first_done & d_first_1 & _T_549 ? 2'h1 : 2'h0; // @[Monitor.scala 675:91 676:21]
  wire [30:0] _GEN_23 = d_first_done & d_first_1 & _T_549 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 677:21]
  wire  _T_562 = inflight | _T_536; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_567 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_568 = io_in_d_bits_opcode == _GEN_32 | _T_567; // @[Monitor.scala 685:77]
  wire  _T_572 = 2'h2 == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_579 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_580 = io_in_d_bits_opcode == _GEN_48 | _T_579; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_75 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_584 = _GEN_75 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_594 = _T_547 & a_first_1 & io_in_a_valid & _T_549; // @[Monitor.scala 694:116]
  wire  _T_596 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire  a_set = _GEN_16[0];
  wire  d_clr = _GEN_22[0];
  wire [3:0] a_opcodes_set = _GEN_19[3:0];
  wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [3:0] d_opcodes_clr = _GEN_23[3:0];
  wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [3:0] a_sizes_set = _GEN_20[3:0];
  wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_605 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [3:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [15:0] _GEN_78 = {{12'd0}, inflight_sizes_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_78 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_631 = io_in_d_valid & d_first_2 & _T_343; // @[Monitor.scala 779:71]
  wire [30:0] _GEN_68 = d_first_done & d_first_2 & _T_343 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 783:90 785:21]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_649 = _GEN_75 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [3:0] d_opcodes_clr_1 = _GEN_68[3:0];
  wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [3:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 1'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= 1'h0;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 1'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= (inflight | a_set) & ~d_clr; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 4'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 4'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 1'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= 1'h0;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 4'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= 1'h0;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at BusBypass.scala:33:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BusBypass.scala:33:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BusBypass.scala:33:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_72 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_72 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at BusBypass.scala:33:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_72 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_72 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BusBypass.scala:33:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_72 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_72 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BusBypass.scala:33:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_72 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_72 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BusBypass.scala:33:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_27 & (io_in_a_valid & _T_133 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_133 & ~reset & ~_T_27) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at BusBypass.scala:33:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_133 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_133 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at BusBypass.scala:33:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_27 & (io_in_a_valid & _T_173 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_173 & ~reset & ~_T_27) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at BusBypass.scala:33:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_173 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_173 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at BusBypass.scala:33:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_207 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_207 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at BusBypass.scala:33:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_207 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_207 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BusBypass.scala:33:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_242 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_242 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at BusBypass.scala:33:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_242 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_242 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BusBypass.scala:33:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_272 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_272 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at BusBypass.scala:33:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_272 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_272 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at BusBypass.scala:33:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_302 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_302 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at BusBypass.scala:33:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_302 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_302 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at BusBypass.scala:33:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_339 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_339) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at BusBypass.scala:33:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_347 & (io_in_d_valid & _T_343 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_343 & _T_2 & ~_T_347) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BusBypass.scala:33:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_355 & (io_in_d_valid & _T_343 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_343 & _T_2 & ~_T_355) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at BusBypass.scala:33:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_359 & (io_in_d_valid & _T_343 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_343 & _T_2 & ~_T_359) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is denied (connected at BusBypass.scala:33:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_347 & (io_in_d_valid & _T_363 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_363 & _T_2 & ~_T_347) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at BusBypass.scala:33:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_355 & (io_in_d_valid & _T_363 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_363 & _T_2 & ~_T_355) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is corrupt (connected at BusBypass.scala:33:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_347 & (io_in_d_valid & _T_391 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_391 & _T_2 & ~_T_347) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at BusBypass.scala:33:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_411 & (io_in_d_valid & _T_391 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_391 & _T_2 & ~_T_411) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at BusBypass.scala:33:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_355 & (io_in_d_valid & _T_420 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_420 & _T_2 & ~_T_355) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is corrupt (connected at BusBypass.scala:33:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_411 & (io_in_d_valid & _T_437 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_437 & _T_2 & ~_T_411) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at BusBypass.scala:33:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_355 & (io_in_d_valid & _T_455 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_455 & _T_2 & ~_T_355) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is corrupt (connected at BusBypass.scala:33:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_486 & (_T_485 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_485 & ~reset & ~_T_486) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BusBypass.scala:33:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_502 & (_T_485 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_485 & ~reset & ~_T_502) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at BusBypass.scala:33:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_510 & (_T_509 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_509 & _T_2 & ~_T_510) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BusBypass.scala:33:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_518 & (_T_509 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_509 & _T_2 & ~_T_518) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at BusBypass.scala:33:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_530 & (_T_509 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_509 & _T_2 & ~_T_530) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel denied changed with multibeat operation (connected at BusBypass.scala:33:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_543 & (_T_539 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_539 & ~reset & ~_T_543) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at BusBypass.scala:33:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_562 & (_T_550 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_550 & _T_2 & ~_T_562) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusBypass.scala:33:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_568 & (_T_550 & _T_536 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_550 & _T_536 & _T_2 & ~_T_568) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at BusBypass.scala:33:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_572 & (_T_550 & _T_536 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_550 & _T_536 & _T_2 & ~_T_572) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at BusBypass.scala:33:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_580 & (_T_550 & ~_T_536 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_550 & ~_T_536 & _T_2 & ~_T_580) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at BusBypass.scala:33:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_584 & (_T_550 & ~_T_536 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_550 & ~_T_536 & _T_2 & ~_T_584) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at BusBypass.scala:33:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_596 & (_T_594 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_594 & _T_2 & ~_T_596) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_605 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_605) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at BusBypass.scala:33:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_631 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusBypass.scala:33:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_649 & (_T_631 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_631 & _T_2 & ~_T_649) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at BusBypass.scala:33:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {4{`RANDOM}};
  address = _RAND_2[127:0];
  _RAND_3 = {1{`RANDOM}};
  d_first_counter = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  opcode_1 = _RAND_4[2:0];
  _RAND_5 = {1{`RANDOM}};
  size_1 = _RAND_5[1:0];
  _RAND_6 = {1{`RANDOM}};
  denied = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  inflight = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  inflight_opcodes = _RAND_8[3:0];
  _RAND_9 = {1{`RANDOM}};
  inflight_sizes = _RAND_9[3:0];
  _RAND_10 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  watchdog = _RAND_12[31:0];
  _RAND_13 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_13[3:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_14[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLError_1(
  input          clock,
  input          reset,
  output         auto_in_a_ready,
  input          auto_in_a_valid,
  input  [2:0]   auto_in_a_bits_opcode,
  input  [127:0] auto_in_a_bits_address,
  input          auto_in_d_ready,
  output         auto_in_d_valid,
  output [2:0]   auto_in_d_bits_opcode,
  output [1:0]   auto_in_d_bits_size,
  output         auto_in_d_bits_denied,
  output         auto_in_d_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [127:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
  reg  idle; // @[Error.scala 44:23]
  reg  beatsLeft; // @[Arbiter.scala 87:30]
  wire  idle_1 = ~beatsLeft; // @[Arbiter.scala 88:28]
  wire  da_valid = auto_in_a_valid & idle; // @[Error.scala 51:35]
  wire [1:0] _readys_T = {da_valid,1'h0}; // @[Cat.scala 31:58]
  wire [2:0] _readys_T_1 = {_readys_T, 1'h0}; // @[package.scala 244:48]
  wire [1:0] _readys_T_3 = _readys_T | _readys_T_1[1:0]; // @[package.scala 244:43]
  wire [2:0] _readys_T_5 = {_readys_T_3, 1'h0}; // @[Arbiter.scala 16:78]
  wire [1:0] _readys_T_7 = ~_readys_T_5[1:0]; // @[Arbiter.scala 16:61]
  wire  readys_1 = _readys_T_7[1]; // @[Arbiter.scala 95:86]
  reg  state_1; // @[Arbiter.scala 116:26]
  wire  allowed_1 = idle_1 ? readys_1 : state_1; // @[Arbiter.scala 121:24]
  wire  out_1_ready = auto_in_d_ready & allowed_1; // @[Arbiter.scala 123:31]
  reg  counter; // @[Edges.scala 228:27]
  wire [2:0] _GEN_4 = 3'h2 == auto_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Error.scala 53:{21,21}]
  wire [2:0] _GEN_5 = 3'h3 == auto_in_a_bits_opcode ? 3'h1 : _GEN_4; // @[Error.scala 53:{21,21}]
  wire [2:0] _GEN_6 = 3'h4 == auto_in_a_bits_opcode ? 3'h1 : _GEN_5; // @[Error.scala 53:{21,21}]
  wire [2:0] _GEN_7 = 3'h5 == auto_in_a_bits_opcode ? 3'h2 : _GEN_6; // @[Error.scala 53:{21,21}]
  wire [2:0] _GEN_8 = 3'h6 == auto_in_a_bits_opcode ? 3'h4 : _GEN_7; // @[Error.scala 53:{21,21}]
  wire [2:0] da_bits_opcode = 3'h7 == auto_in_a_bits_opcode ? 3'h4 : _GEN_8; // @[Error.scala 53:{21,21}]
  wire  beats1_opdata = da_bits_opcode[0]; // @[Edges.scala 105:36]
  wire  done = out_1_ready & da_valid; // @[Decoupled.scala 50:35]
  wire  counter1 = counter - 1'h1; // @[Edges.scala 229:28]
  wire  da_first = ~counter; // @[Edges.scala 230:25]
  wire  _T_3 = ~reset; // @[Error.scala 49:12]
  wire  _GEN_12 = done & da_bits_opcode == 3'h4 ? 1'h0 : idle; // @[Error.scala 44:23 70:{52,59}]
  wire  latch = idle_1 & auto_in_d_ready; // @[Arbiter.scala 89:24]
  wire  earlyWinner_1 = readys_1 & da_valid; // @[Arbiter.scala 97:79]
  wire  _T_22 = ~da_valid; // @[Arbiter.scala 107:15]
  wire  muxStateEarly_1 = idle_1 ? earlyWinner_1 : state_1; // @[Arbiter.scala 117:30]
  wire  _sink_ACancel_earlyValid_T_2 = state_1 & da_valid; // @[Mux.scala 27:73]
  wire  sink_ACancel_earlyValid = idle_1 ? da_valid : _sink_ACancel_earlyValid_T_2; // @[Arbiter.scala 125:29]
  wire  _beatsLeft_T_2 = auto_in_d_ready & sink_ACancel_earlyValid; // @[ReadyValidCancel.scala 49:33]
  TLMonitor_51 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
    .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
  );
  assign auto_in_a_ready = out_1_ready & idle; // @[Error.scala 50:37]
  assign auto_in_d_valid = idle_1 ? da_valid : _sink_ACancel_earlyValid_T_2; // @[Arbiter.scala 125:29]
  assign auto_in_d_bits_opcode = muxStateEarly_1 ? da_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  assign auto_in_d_bits_size = muxStateEarly_1 ? 2'h2 : 2'h0; // @[Mux.scala 27:73]
  assign auto_in_d_bits_denied = idle_1 ? earlyWinner_1 : state_1; // @[Arbiter.scala 117:30]
  assign auto_in_d_bits_corrupt = muxStateEarly_1 & beats1_opdata; // @[Mux.scala 27:73]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = out_1_ready & idle; // @[Error.scala 50:37]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = idle_1 ? da_valid : _sink_ACancel_earlyValid_T_2; // @[Arbiter.scala 125:29]
  assign monitor_io_in_d_bits_opcode = muxStateEarly_1 ? da_bits_opcode : 3'h0; // @[Mux.scala 27:73]
  assign monitor_io_in_d_bits_size = muxStateEarly_1 ? 2'h2 : 2'h0; // @[Mux.scala 27:73]
  assign monitor_io_in_d_bits_denied = idle_1 ? earlyWinner_1 : state_1; // @[Arbiter.scala 117:30]
  assign monitor_io_in_d_bits_corrupt = muxStateEarly_1 & beats1_opdata; // @[Mux.scala 27:73]
  always @(posedge clock) begin
    idle <= reset | _GEN_12; // @[Error.scala 44:{23,23}]
    if (reset) begin // @[Arbiter.scala 87:30]
      beatsLeft <= 1'h0; // @[Arbiter.scala 87:30]
    end else if (latch) begin // @[Arbiter.scala 113:23]
      beatsLeft <= 1'h0;
    end else begin
      beatsLeft <= beatsLeft - _beatsLeft_T_2;
    end
    if (reset) begin // @[Arbiter.scala 116:26]
      state_1 <= 1'h0; // @[Arbiter.scala 116:26]
    end else if (idle_1) begin // @[Arbiter.scala 117:30]
      state_1 <= earlyWinner_1;
    end
    if (reset) begin // @[Edges.scala 228:27]
      counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (done) begin // @[Edges.scala 234:17]
      if (da_first) begin // @[Edges.scala 235:21]
        counter <= 1'h0;
      end else begin
        counter <= counter1;
      end
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(idle | da_first) & ~reset) begin
          $fatal; // @[Error.scala 49:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~(idle | da_first)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Error.scala:49 assert (idle || da_first) // we only send Grant, never GrantData => simplified flow control below\n"
            ); // @[Error.scala 49:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~da_valid | earlyWinner_1) & _T_3) begin
          $fatal; // @[Arbiter.scala 107:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3 & ~(~da_valid | earlyWinner_1)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:107 assert (!earlyValids.reduce(_||_) || earlyWinner.reduce(_||_))\n"
            ); // @[Arbiter.scala 107:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_22 | da_valid) & _T_3) begin
          $fatal; // @[Arbiter.scala 108:14]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_3 & ~(_T_22 | da_valid)) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at Arbiter.scala:108 assert (!validQuals .reduce(_||_) || validQuals .reduce(_||_))\n"
            ); // @[Arbiter.scala 108:14]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  idle = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  beatsLeft = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  state_1 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  counter = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLBusBypass(
  input         clock,
  input         reset,
  input         auto_node_out_out_a_ready,
  output        auto_node_out_out_a_valid,
  output [2:0]  auto_node_out_out_a_bits_opcode,
  output [8:0]  auto_node_out_out_a_bits_address,
  output [31:0] auto_node_out_out_a_bits_data,
  output        auto_node_out_out_d_ready,
  input         auto_node_out_out_d_valid,
  input  [2:0]  auto_node_out_out_d_bits_opcode,
  input  [1:0]  auto_node_out_out_d_bits_param,
  input  [1:0]  auto_node_out_out_d_bits_size,
  input         auto_node_out_out_d_bits_source,
  input         auto_node_out_out_d_bits_sink,
  input         auto_node_out_out_d_bits_denied,
  input  [31:0] auto_node_out_out_d_bits_data,
  input         auto_node_out_out_d_bits_corrupt,
  output        auto_node_in_in_a_ready,
  input         auto_node_in_in_a_valid,
  input  [2:0]  auto_node_in_in_a_bits_opcode,
  input  [8:0]  auto_node_in_in_a_bits_address,
  input  [31:0] auto_node_in_in_a_bits_data,
  input         auto_node_in_in_d_ready,
  output        auto_node_in_in_d_valid,
  output [2:0]  auto_node_in_in_d_bits_opcode,
  output [1:0]  auto_node_in_in_d_bits_param,
  output [1:0]  auto_node_in_in_d_bits_size,
  output        auto_node_in_in_d_bits_sink,
  output        auto_node_in_in_d_bits_denied,
  output [31:0] auto_node_in_in_d_bits_data,
  output        auto_node_in_in_d_bits_corrupt,
  input         io_bypass
);
  wire  bar_clock; // @[BusBypass.scala 17:33]
  wire  bar_reset; // @[BusBypass.scala 17:33]
  wire  bar_auto_in_a_ready; // @[BusBypass.scala 17:33]
  wire  bar_auto_in_a_valid; // @[BusBypass.scala 17:33]
  wire [2:0] bar_auto_in_a_bits_opcode; // @[BusBypass.scala 17:33]
  wire [8:0] bar_auto_in_a_bits_address; // @[BusBypass.scala 17:33]
  wire [31:0] bar_auto_in_a_bits_data; // @[BusBypass.scala 17:33]
  wire  bar_auto_in_d_ready; // @[BusBypass.scala 17:33]
  wire  bar_auto_in_d_valid; // @[BusBypass.scala 17:33]
  wire [2:0] bar_auto_in_d_bits_opcode; // @[BusBypass.scala 17:33]
  wire [1:0] bar_auto_in_d_bits_param; // @[BusBypass.scala 17:33]
  wire [1:0] bar_auto_in_d_bits_size; // @[BusBypass.scala 17:33]
  wire  bar_auto_in_d_bits_sink; // @[BusBypass.scala 17:33]
  wire  bar_auto_in_d_bits_denied; // @[BusBypass.scala 17:33]
  wire [31:0] bar_auto_in_d_bits_data; // @[BusBypass.scala 17:33]
  wire  bar_auto_in_d_bits_corrupt; // @[BusBypass.scala 17:33]
  wire  bar_auto_out_1_a_ready; // @[BusBypass.scala 17:33]
  wire  bar_auto_out_1_a_valid; // @[BusBypass.scala 17:33]
  wire [2:0] bar_auto_out_1_a_bits_opcode; // @[BusBypass.scala 17:33]
  wire [8:0] bar_auto_out_1_a_bits_address; // @[BusBypass.scala 17:33]
  wire [31:0] bar_auto_out_1_a_bits_data; // @[BusBypass.scala 17:33]
  wire  bar_auto_out_1_d_ready; // @[BusBypass.scala 17:33]
  wire  bar_auto_out_1_d_valid; // @[BusBypass.scala 17:33]
  wire [2:0] bar_auto_out_1_d_bits_opcode; // @[BusBypass.scala 17:33]
  wire [1:0] bar_auto_out_1_d_bits_param; // @[BusBypass.scala 17:33]
  wire [1:0] bar_auto_out_1_d_bits_size; // @[BusBypass.scala 17:33]
  wire  bar_auto_out_1_d_bits_source; // @[BusBypass.scala 17:33]
  wire  bar_auto_out_1_d_bits_sink; // @[BusBypass.scala 17:33]
  wire  bar_auto_out_1_d_bits_denied; // @[BusBypass.scala 17:33]
  wire [31:0] bar_auto_out_1_d_bits_data; // @[BusBypass.scala 17:33]
  wire  bar_auto_out_1_d_bits_corrupt; // @[BusBypass.scala 17:33]
  wire  bar_auto_out_0_a_ready; // @[BusBypass.scala 17:33]
  wire  bar_auto_out_0_a_valid; // @[BusBypass.scala 17:33]
  wire [2:0] bar_auto_out_0_a_bits_opcode; // @[BusBypass.scala 17:33]
  wire [127:0] bar_auto_out_0_a_bits_address; // @[BusBypass.scala 17:33]
  wire  bar_auto_out_0_d_ready; // @[BusBypass.scala 17:33]
  wire  bar_auto_out_0_d_valid; // @[BusBypass.scala 17:33]
  wire [2:0] bar_auto_out_0_d_bits_opcode; // @[BusBypass.scala 17:33]
  wire [1:0] bar_auto_out_0_d_bits_size; // @[BusBypass.scala 17:33]
  wire  bar_auto_out_0_d_bits_denied; // @[BusBypass.scala 17:33]
  wire  bar_auto_out_0_d_bits_corrupt; // @[BusBypass.scala 17:33]
  wire  bar_io_bypass; // @[BusBypass.scala 17:33]
  wire  error_clock; // @[BusBypass.scala 27:40]
  wire  error_reset; // @[BusBypass.scala 27:40]
  wire  error_auto_in_a_ready; // @[BusBypass.scala 27:40]
  wire  error_auto_in_a_valid; // @[BusBypass.scala 27:40]
  wire [2:0] error_auto_in_a_bits_opcode; // @[BusBypass.scala 27:40]
  wire [127:0] error_auto_in_a_bits_address; // @[BusBypass.scala 27:40]
  wire  error_auto_in_d_ready; // @[BusBypass.scala 27:40]
  wire  error_auto_in_d_valid; // @[BusBypass.scala 27:40]
  wire [2:0] error_auto_in_d_bits_opcode; // @[BusBypass.scala 27:40]
  wire [1:0] error_auto_in_d_bits_size; // @[BusBypass.scala 27:40]
  wire  error_auto_in_d_bits_denied; // @[BusBypass.scala 27:40]
  wire  error_auto_in_d_bits_corrupt; // @[BusBypass.scala 27:40]
  TLBusBypassBar bar ( // @[BusBypass.scala 17:33]
    .clock(bar_clock),
    .reset(bar_reset),
    .auto_in_a_ready(bar_auto_in_a_ready),
    .auto_in_a_valid(bar_auto_in_a_valid),
    .auto_in_a_bits_opcode(bar_auto_in_a_bits_opcode),
    .auto_in_a_bits_address(bar_auto_in_a_bits_address),
    .auto_in_a_bits_data(bar_auto_in_a_bits_data),
    .auto_in_d_ready(bar_auto_in_d_ready),
    .auto_in_d_valid(bar_auto_in_d_valid),
    .auto_in_d_bits_opcode(bar_auto_in_d_bits_opcode),
    .auto_in_d_bits_param(bar_auto_in_d_bits_param),
    .auto_in_d_bits_size(bar_auto_in_d_bits_size),
    .auto_in_d_bits_sink(bar_auto_in_d_bits_sink),
    .auto_in_d_bits_denied(bar_auto_in_d_bits_denied),
    .auto_in_d_bits_data(bar_auto_in_d_bits_data),
    .auto_in_d_bits_corrupt(bar_auto_in_d_bits_corrupt),
    .auto_out_1_a_ready(bar_auto_out_1_a_ready),
    .auto_out_1_a_valid(bar_auto_out_1_a_valid),
    .auto_out_1_a_bits_opcode(bar_auto_out_1_a_bits_opcode),
    .auto_out_1_a_bits_address(bar_auto_out_1_a_bits_address),
    .auto_out_1_a_bits_data(bar_auto_out_1_a_bits_data),
    .auto_out_1_d_ready(bar_auto_out_1_d_ready),
    .auto_out_1_d_valid(bar_auto_out_1_d_valid),
    .auto_out_1_d_bits_opcode(bar_auto_out_1_d_bits_opcode),
    .auto_out_1_d_bits_param(bar_auto_out_1_d_bits_param),
    .auto_out_1_d_bits_size(bar_auto_out_1_d_bits_size),
    .auto_out_1_d_bits_source(bar_auto_out_1_d_bits_source),
    .auto_out_1_d_bits_sink(bar_auto_out_1_d_bits_sink),
    .auto_out_1_d_bits_denied(bar_auto_out_1_d_bits_denied),
    .auto_out_1_d_bits_data(bar_auto_out_1_d_bits_data),
    .auto_out_1_d_bits_corrupt(bar_auto_out_1_d_bits_corrupt),
    .auto_out_0_a_ready(bar_auto_out_0_a_ready),
    .auto_out_0_a_valid(bar_auto_out_0_a_valid),
    .auto_out_0_a_bits_opcode(bar_auto_out_0_a_bits_opcode),
    .auto_out_0_a_bits_address(bar_auto_out_0_a_bits_address),
    .auto_out_0_d_ready(bar_auto_out_0_d_ready),
    .auto_out_0_d_valid(bar_auto_out_0_d_valid),
    .auto_out_0_d_bits_opcode(bar_auto_out_0_d_bits_opcode),
    .auto_out_0_d_bits_size(bar_auto_out_0_d_bits_size),
    .auto_out_0_d_bits_denied(bar_auto_out_0_d_bits_denied),
    .auto_out_0_d_bits_corrupt(bar_auto_out_0_d_bits_corrupt),
    .io_bypass(bar_io_bypass)
  );
  TLError_1 error ( // @[BusBypass.scala 27:40]
    .clock(error_clock),
    .reset(error_reset),
    .auto_in_a_ready(error_auto_in_a_ready),
    .auto_in_a_valid(error_auto_in_a_valid),
    .auto_in_a_bits_opcode(error_auto_in_a_bits_opcode),
    .auto_in_a_bits_address(error_auto_in_a_bits_address),
    .auto_in_d_ready(error_auto_in_d_ready),
    .auto_in_d_valid(error_auto_in_d_valid),
    .auto_in_d_bits_opcode(error_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(error_auto_in_d_bits_size),
    .auto_in_d_bits_denied(error_auto_in_d_bits_denied),
    .auto_in_d_bits_corrupt(error_auto_in_d_bits_corrupt)
  );
  assign auto_node_out_out_a_valid = bar_auto_out_1_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_node_out_out_a_bits_opcode = bar_auto_out_1_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_node_out_out_a_bits_address = bar_auto_out_1_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_node_out_out_a_bits_data = bar_auto_out_1_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_node_out_out_d_ready = bar_auto_out_1_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_node_in_in_a_ready = bar_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_node_in_in_d_valid = bar_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_node_in_in_d_bits_opcode = bar_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_node_in_in_d_bits_param = bar_auto_in_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_node_in_in_d_bits_size = bar_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_node_in_in_d_bits_sink = bar_auto_in_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_node_in_in_d_bits_denied = bar_auto_in_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_node_in_in_d_bits_data = bar_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_node_in_in_d_bits_corrupt = bar_auto_in_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign bar_clock = clock;
  assign bar_reset = reset;
  assign bar_auto_in_a_valid = auto_node_in_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bar_auto_in_a_bits_opcode = auto_node_in_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bar_auto_in_a_bits_address = auto_node_in_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bar_auto_in_a_bits_data = auto_node_in_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bar_auto_in_d_ready = auto_node_in_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bar_auto_out_1_a_ready = auto_node_out_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bar_auto_out_1_d_valid = auto_node_out_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bar_auto_out_1_d_bits_opcode = auto_node_out_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bar_auto_out_1_d_bits_param = auto_node_out_out_d_bits_param; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bar_auto_out_1_d_bits_size = auto_node_out_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bar_auto_out_1_d_bits_source = auto_node_out_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bar_auto_out_1_d_bits_sink = auto_node_out_out_d_bits_sink; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bar_auto_out_1_d_bits_denied = auto_node_out_out_d_bits_denied; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bar_auto_out_1_d_bits_data = auto_node_out_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bar_auto_out_1_d_bits_corrupt = auto_node_out_out_d_bits_corrupt; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bar_auto_out_0_a_ready = error_auto_in_a_ready; // @[LazyModule.scala 298:16]
  assign bar_auto_out_0_d_valid = error_auto_in_d_valid; // @[LazyModule.scala 298:16]
  assign bar_auto_out_0_d_bits_opcode = error_auto_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign bar_auto_out_0_d_bits_size = error_auto_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign bar_auto_out_0_d_bits_denied = error_auto_in_d_bits_denied; // @[LazyModule.scala 298:16]
  assign bar_auto_out_0_d_bits_corrupt = error_auto_in_d_bits_corrupt; // @[LazyModule.scala 298:16]
  assign bar_io_bypass = io_bypass; // @[BusBypass.scala 44:26]
  assign error_clock = clock;
  assign error_reset = reset;
  assign error_auto_in_a_valid = bar_auto_out_0_a_valid; // @[LazyModule.scala 298:16]
  assign error_auto_in_a_bits_opcode = bar_auto_out_0_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign error_auto_in_a_bits_address = bar_auto_out_0_a_bits_address; // @[LazyModule.scala 298:16]
  assign error_auto_in_d_ready = bar_auto_out_0_d_ready; // @[LazyModule.scala 298:16]
endmodule
module TLMonitor_52(
  input        clock,
  input        reset,
  input        io_in_a_ready,
  input        io_in_a_valid,
  input  [2:0] io_in_a_bits_opcode,
  input  [8:0] io_in_a_bits_address,
  input        io_in_d_ready,
  input        io_in_d_valid,
  input  [2:0] io_in_d_bits_opcode,
  input  [1:0] io_in_d_bits_param,
  input  [1:0] io_in_d_bits_size,
  input        io_in_d_bits_source,
  input        io_in_d_bits_sink,
  input        io_in_d_bits_denied,
  input        io_in_d_bits_corrupt
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire [8:0] _is_aligned_T = io_in_a_bits_address & 9'h3; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala 20:24]
  wire [9:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
  wire  _T_15 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [9:0] _T_23 = $signed(_T_7) & -10'sh40; // @[Parameters.scala 137:52]
  wire  _T_24 = $signed(_T_23) == 10'sh0; // @[Parameters.scala 137:67]
  wire [8:0] _T_25 = io_in_a_bits_address ^ 9'h44; // @[Parameters.scala 137:31]
  wire [9:0] _T_26 = {1'b0,$signed(_T_25)}; // @[Parameters.scala 137:49]
  wire [9:0] _T_28 = $signed(_T_26) & -10'shc; // @[Parameters.scala 137:52]
  wire  _T_29 = $signed(_T_28) == 10'sh0; // @[Parameters.scala 137:67]
  wire [8:0] _T_30 = io_in_a_bits_address ^ 9'h58; // @[Parameters.scala 137:31]
  wire [9:0] _T_31 = {1'b0,$signed(_T_30)}; // @[Parameters.scala 137:49]
  wire [9:0] _T_33 = $signed(_T_31) & -10'sh8; // @[Parameters.scala 137:52]
  wire  _T_34 = $signed(_T_33) == 10'sh0; // @[Parameters.scala 137:67]
  wire [8:0] _T_35 = io_in_a_bits_address ^ 9'h60; // @[Parameters.scala 137:31]
  wire [9:0] _T_36 = {1'b0,$signed(_T_35)}; // @[Parameters.scala 137:49]
  wire [9:0] _T_38 = $signed(_T_36) & -10'sh20; // @[Parameters.scala 137:52]
  wire  _T_39 = $signed(_T_38) == 10'sh0; // @[Parameters.scala 137:67]
  wire [8:0] _T_40 = io_in_a_bits_address ^ 9'h80; // @[Parameters.scala 137:31]
  wire [9:0] _T_41 = {1'b0,$signed(_T_40)}; // @[Parameters.scala 137:49]
  wire [9:0] _T_43 = $signed(_T_41) & -10'sh80; // @[Parameters.scala 137:52]
  wire  _T_44 = $signed(_T_43) == 10'sh0; // @[Parameters.scala 137:67]
  wire [8:0] _T_45 = io_in_a_bits_address ^ 9'h100; // @[Parameters.scala 137:31]
  wire [9:0] _T_46 = {1'b0,$signed(_T_45)}; // @[Parameters.scala 137:49]
  wire [9:0] _T_48 = $signed(_T_46) & -10'sh100; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 10'sh0; // @[Parameters.scala 137:67]
  wire  _T_54 = _T_24 | _T_29 | _T_34 | _T_39 | _T_44 | _T_49; // @[Parameters.scala 671:42]
  wire  _T_129 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_247 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_317 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_381 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire  _T_446 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_506 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_566 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_630 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_1 = ~io_in_d_bits_source; // @[Parameters.scala 46:9]
  wire  _T_634 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_638 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 312:27]
  wire  _T_642 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 313:28]
  wire  _T_646 = ~io_in_d_bits_corrupt; // @[Monitor.scala 314:15]
  wire  _T_650 = ~io_in_d_bits_denied; // @[Monitor.scala 315:15]
  wire  _T_654 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_665 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 102:26]
  wire  _T_669 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 323:28]
  wire  _T_682 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_702 = _T_650 | io_in_d_bits_corrupt; // @[Monitor.scala 334:30]
  wire  _T_711 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_728 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_746 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [8:0] address; // @[Monitor.scala 388:22]
  wire  _T_776 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_777 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_793 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] param_1; // @[Monitor.scala 536:22]
  reg [1:0] size_1; // @[Monitor.scala 537:22]
  reg  source_1; // @[Monitor.scala 538:22]
  reg  sink; // @[Monitor.scala 539:22]
  reg  denied; // @[Monitor.scala 540:22]
  wire  _T_800 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_801 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_805 = io_in_d_bits_param == param_1; // @[Monitor.scala 543:29]
  wire  _T_809 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_813 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  wire  _T_817 = io_in_d_bits_sink == sink; // @[Monitor.scala 546:29]
  wire  _T_821 = io_in_d_bits_denied == denied; // @[Monitor.scala 547:29]
  reg  inflight; // @[Monitor.scala 611:27]
  reg [3:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [3:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [2:0] _GEN_71 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [3:0] _a_opcode_lookup_T = {{1'd0}, _GEN_71}; // @[Monitor.scala 634:69]
  wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_72 = {{12'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_72 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [3:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _GEN_75 = {{12'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_75 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_827 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [1:0] _GEN_15 = io_in_a_valid & a_first_1 ? 2'h1 : 2'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_830 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [18:0] _a_opcodes_set_T_1 = {{15'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? 3'h5 : 3'h0; // @[Monitor.scala 652:72 655:28]
  wire [17:0] _a_sizes_set_T_1 = {{15'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire  _T_834 = ~inflight; // @[Monitor.scala 658:17]
  wire [1:0] _GEN_16 = a_first_done & a_first_1 ? 2'h1 : 2'h0; // @[Monitor.scala 652:72 653:28]
  wire [18:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 656:28]
  wire [17:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 18'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_838 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_840 = ~_T_634; // @[Monitor.scala 671:74]
  wire  _T_841 = io_in_d_valid & d_first_1 & ~_T_634; // @[Monitor.scala 671:71]
  wire [1:0] _d_clr_wo_ready_T = 2'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [1:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_634 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 671:90 672:22]
  wire [30:0] _GEN_1 = {{15'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [30:0] _d_opcodes_clr_T_5 = _GEN_1 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [1:0] _GEN_22 = d_first_done & d_first_1 & _T_840 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 675:91 676:21]
  wire [30:0] _GEN_23 = d_first_done & d_first_1 & _T_840 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 677:21]
  wire  same_cycle_resp = _T_827 & _source_ok_T_1; // @[Monitor.scala 681:88]
  wire  _T_853 = inflight >> io_in_d_bits_source | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_858 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_859 = io_in_d_bits_opcode == _GEN_32 | _T_858; // @[Monitor.scala 685:77]
  wire  _T_863 = 2'h2 == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_870 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_871 = io_in_d_bits_opcode == _GEN_48 | _T_870; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_79 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_875 = _GEN_79 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_885 = _T_838 & a_first_1 & io_in_a_valid & _source_ok_T_1 & _T_840; // @[Monitor.scala 694:116]
  wire  _T_887 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire  a_set_wo_ready = _GEN_15[0];
  wire  d_clr_wo_ready = _GEN_21[0];
  wire  _T_894 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire  a_set = _GEN_16[0];
  wire  d_clr = _GEN_22[0];
  wire [3:0] a_opcodes_set = _GEN_19[3:0];
  wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [3:0] d_opcodes_clr = _GEN_23[3:0];
  wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [3:0] a_sizes_set = _GEN_20[3:0];
  wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_903 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [3:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [15:0] _GEN_84 = {{12'd0}, _c_size_lookup_T_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_84 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_929 = io_in_d_valid & d_first_2 & _T_634; // @[Monitor.scala 779:71]
  wire [30:0] _GEN_68 = d_first_done & d_first_2 & _T_634 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 783:90 785:21]
  wire  _T_937 = 1'h0 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_947 = _GEN_79 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [3:0] d_opcodes_clr_1 = _GEN_68[3:0];
  wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [3:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 1'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= 1'h0;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      param_1 <= io_in_d_bits_param; // @[Monitor.scala 551:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      sink <= io_in_d_bits_sink; // @[Monitor.scala 554:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      denied <= io_in_d_bits_denied; // @[Monitor.scala 555:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 1'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= (inflight | a_set) & ~d_clr; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 4'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 4'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 1'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= 1'h0;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 4'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= 1'h0;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at Debug.scala:653:46)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Debug.scala:653:46)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_15 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Debug.scala:653:46)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_129 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_129 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at Debug.scala:653:46)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_129 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_129 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Debug.scala:653:46)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_129 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_129 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Debug.scala:653:46)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_129 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_129 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Debug.scala:653:46)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_54 & (io_in_a_valid & _T_247 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_247 & ~reset & ~_T_54) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at Debug.scala:653:46)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_247 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_247 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at Debug.scala:653:46)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_54 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_54) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at Debug.scala:653:46)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Debug.scala:653:46)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_381 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_381 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at Debug.scala:653:46)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_381 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_381 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Debug.scala:653:46)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_446 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_446 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at Debug.scala:653:46)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_446 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_446 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Debug.scala:653:46)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_506 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_506 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at Debug.scala:653:46)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_506 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_506 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at Debug.scala:653:46)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_566 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_566 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at Debug.scala:653:46)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_566 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_566 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at Debug.scala:653:46)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_630 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_630) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_1 & (io_in_d_valid & _T_634 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_634 & _T_2 & ~_source_ok_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_638 & (io_in_d_valid & _T_634 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_634 & _T_2 & ~_T_638) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_642 & (io_in_d_valid & _T_634 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_634 & _T_2 & ~_T_642) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_646 & (io_in_d_valid & _T_634 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_634 & _T_2 & ~_T_646) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_650 & (io_in_d_valid & _T_634 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_634 & _T_2 & ~_T_650) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck is denied (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_1 & (io_in_d_valid & _T_654 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_654 & _T_2 & ~_source_ok_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_654 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_654 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_638 & (io_in_d_valid & _T_654 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_654 & _T_2 & ~_T_638) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_665 & (io_in_d_valid & _T_654 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_654 & _T_2 & ~_T_665) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid cap param (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_669 & (io_in_d_valid & _T_654 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_654 & _T_2 & ~_T_669) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries toN param (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_646 & (io_in_d_valid & _T_654 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_654 & _T_2 & ~_T_646) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is corrupt (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_650 & (io_in_d_valid & _T_654 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_654 & _T_2 & ~_T_650) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant is denied (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_1 & (io_in_d_valid & _T_682 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_682 & _T_2 & ~_source_ok_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_682 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_682 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_638 & (io_in_d_valid & _T_682 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_682 & _T_2 & ~_T_638) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_665 & (io_in_d_valid & _T_682 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_682 & _T_2 & ~_T_665) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_669 & (io_in_d_valid & _T_682 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_682 & _T_2 & ~_T_669) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries toN param (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_702 & (io_in_d_valid & _T_682 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_682 & _T_2 & ~_T_702) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_650 & (io_in_d_valid & _T_682 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_682 & _T_2 & ~_T_650) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData is denied (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_1 & (io_in_d_valid & _T_711 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_711 & _T_2 & ~_source_ok_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_642 & (io_in_d_valid & _T_711 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_711 & _T_2 & ~_T_642) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid param (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_646 & (io_in_d_valid & _T_711 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_711 & _T_2 & ~_T_646) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is corrupt (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_650 & (io_in_d_valid & _T_711 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_711 & _T_2 & ~_T_650) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck is denied (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_1 & (io_in_d_valid & _T_728 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_728 & _T_2 & ~_source_ok_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_642 & (io_in_d_valid & _T_728 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_728 & _T_2 & ~_T_642) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_702 & (io_in_d_valid & _T_728 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_728 & _T_2 & ~_T_702) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_650 & (io_in_d_valid & _T_728 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_728 & _T_2 & ~_T_650) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData is denied (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_1 & (io_in_d_valid & _T_746 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_746 & _T_2 & ~_source_ok_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_642 & (io_in_d_valid & _T_746 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_746 & _T_2 & ~_T_642) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid param (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_646 & (io_in_d_valid & _T_746 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_746 & _T_2 & ~_T_646) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is corrupt (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_650 & (io_in_d_valid & _T_746 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_746 & _T_2 & ~_T_650) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck is denied (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_777 & (_T_776 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_776 & ~reset & ~_T_777) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Debug.scala:653:46)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_793 & (_T_776 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_776 & ~reset & ~_T_793) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at Debug.scala:653:46)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_801 & (_T_800 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_800 & _T_2 & ~_T_801) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_805 & (_T_800 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_800 & _T_2 & ~_T_805) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel param changed within multibeat operation (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_809 & (_T_800 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_800 & _T_2 & ~_T_809) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_813 & (_T_800 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_800 & _T_2 & ~_T_813) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_817 & (_T_800 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_800 & _T_2 & ~_T_817) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel sink changed with multibeat operation (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_821 & (_T_800 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_800 & _T_2 & ~_T_821) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel denied changed with multibeat operation (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_834 & (_T_830 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_830 & ~reset & ~_T_834) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at Debug.scala:653:46)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_853 & (_T_841 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_841 & _T_2 & ~_T_853) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_859 & (_T_841 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_841 & same_cycle_resp & _T_2 & ~_T_859) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_863 & (_T_841 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_841 & same_cycle_resp & _T_2 & ~_T_863) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_871 & (_T_841 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_841 & ~same_cycle_resp & _T_2 & ~_T_871) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_875 & (_T_841 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_841 & ~same_cycle_resp & _T_2 & ~_T_875) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_887 & (_T_885 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_885 & _T_2 & ~_T_887) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_894 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_894) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 3 (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_903 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_903) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Debug.scala:653:46)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_937 & (_T_929 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_929 & _T_2 & ~_T_937) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_947 & (_T_929 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_929 & _T_2 & ~_T_947) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Debug.scala:653:46)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  address = _RAND_2[8:0];
  _RAND_3 = {1{`RANDOM}};
  d_first_counter = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  opcode_1 = _RAND_4[2:0];
  _RAND_5 = {1{`RANDOM}};
  param_1 = _RAND_5[1:0];
  _RAND_6 = {1{`RANDOM}};
  size_1 = _RAND_6[1:0];
  _RAND_7 = {1{`RANDOM}};
  source_1 = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  sink = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  denied = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  inflight = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  inflight_opcodes = _RAND_11[3:0];
  _RAND_12 = {1{`RANDOM}};
  inflight_sizes = _RAND_12[3:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_16[3:0];
  _RAND_17 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_17[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module AsyncQueueSource_1(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [2:0]  io_enq_bits_opcode,
  input  [8:0]  io_enq_bits_address,
  input  [31:0] io_enq_bits_data,
  output [2:0]  io_async_mem_0_opcode,
  output [8:0]  io_async_mem_0_address,
  output [31:0] io_async_mem_0_data,
  input         io_async_ridx,
  output        io_async_widx,
  input         io_async_safe_ridx_valid,
  output        io_async_safe_widx_valid,
  output        io_async_safe_source_reset_n
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
`endif // RANDOMIZE_REG_INIT
  wire  ridx_ridx_gray_clock; // @[ShiftReg.scala 45:23]
  wire  ridx_ridx_gray_reset; // @[ShiftReg.scala 45:23]
  wire  ridx_ridx_gray_io_d; // @[ShiftReg.scala 45:23]
  wire  ridx_ridx_gray_io_q; // @[ShiftReg.scala 45:23]
  wire  source_valid_0_io_in; // @[AsyncQueue.scala 100:32]
  wire  source_valid_0_io_out; // @[AsyncQueue.scala 100:32]
  wire  source_valid_0_clock; // @[AsyncQueue.scala 100:32]
  wire  source_valid_0_reset; // @[AsyncQueue.scala 100:32]
  wire  source_valid_1_io_in; // @[AsyncQueue.scala 101:32]
  wire  source_valid_1_io_out; // @[AsyncQueue.scala 101:32]
  wire  source_valid_1_clock; // @[AsyncQueue.scala 101:32]
  wire  source_valid_1_reset; // @[AsyncQueue.scala 101:32]
  wire  sink_extend_io_in; // @[AsyncQueue.scala 103:30]
  wire  sink_extend_io_out; // @[AsyncQueue.scala 103:30]
  wire  sink_extend_clock; // @[AsyncQueue.scala 103:30]
  wire  sink_extend_reset; // @[AsyncQueue.scala 103:30]
  wire  sink_valid_io_in; // @[AsyncQueue.scala 104:30]
  wire  sink_valid_io_out; // @[AsyncQueue.scala 104:30]
  wire  sink_valid_clock; // @[AsyncQueue.scala 104:30]
  wire  sink_valid_reset; // @[AsyncQueue.scala 104:30]
  reg [2:0] mem_0_opcode; // @[AsyncQueue.scala 80:16]
  reg [8:0] mem_0_address; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_0_data; // @[AsyncQueue.scala 80:16]
  wire  _widx_T_1 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
  wire  sink_ready = sink_valid_io_out;
  wire  _widx_T_2 = ~sink_ready; // @[AsyncQueue.scala 81:79]
  reg  widx_widx_bin; // @[AsyncQueue.scala 52:25]
  wire  widx_incremented = _widx_T_2 ? 1'h0 : widx_widx_bin + _widx_T_1; // @[AsyncQueue.scala 53:23]
  wire  ridx = ridx_ridx_gray_io_q; // @[ShiftReg.scala 48:{24,24}]
  reg  ready_reg; // @[AsyncQueue.scala 88:56]
  reg  widx_gray; // @[AsyncQueue.scala 91:55]
  AsyncResetSynchronizerShiftReg_w1_d3_i0 ridx_ridx_gray ( // @[ShiftReg.scala 45:23]
    .clock(ridx_ridx_gray_clock),
    .reset(ridx_ridx_gray_reset),
    .io_d(ridx_ridx_gray_io_d),
    .io_q(ridx_ridx_gray_io_q)
  );
  AsyncValidSync source_valid_0 ( // @[AsyncQueue.scala 100:32]
    .io_in(source_valid_0_io_in),
    .io_out(source_valid_0_io_out),
    .clock(source_valid_0_clock),
    .reset(source_valid_0_reset)
  );
  AsyncValidSync source_valid_1 ( // @[AsyncQueue.scala 101:32]
    .io_in(source_valid_1_io_in),
    .io_out(source_valid_1_io_out),
    .clock(source_valid_1_clock),
    .reset(source_valid_1_reset)
  );
  AsyncValidSync sink_extend ( // @[AsyncQueue.scala 103:30]
    .io_in(sink_extend_io_in),
    .io_out(sink_extend_io_out),
    .clock(sink_extend_clock),
    .reset(sink_extend_reset)
  );
  AsyncValidSync sink_valid ( // @[AsyncQueue.scala 104:30]
    .io_in(sink_valid_io_in),
    .io_out(sink_valid_io_out),
    .clock(sink_valid_clock),
    .reset(sink_valid_reset)
  );
  assign io_enq_ready = ready_reg & sink_ready; // @[AsyncQueue.scala 89:29]
  assign io_async_mem_0_opcode = mem_0_opcode; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_0_address = mem_0_address; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_0_data = mem_0_data; // @[AsyncQueue.scala 96:31]
  assign io_async_widx = widx_gray; // @[AsyncQueue.scala 92:17]
  assign io_async_safe_widx_valid = source_valid_1_io_out; // @[AsyncQueue.scala 117:20]
  assign io_async_safe_source_reset_n = ~reset; // @[AsyncQueue.scala 121:27]
  assign ridx_ridx_gray_clock = clock;
  assign ridx_ridx_gray_reset = reset;
  assign ridx_ridx_gray_io_d = io_async_ridx; // @[ShiftReg.scala 47:16]
  assign source_valid_0_io_in = 1'h1; // @[AsyncQueue.scala 115:26]
  assign source_valid_0_clock = clock; // @[AsyncQueue.scala 110:26]
  assign source_valid_0_reset = reset; // @[AsyncQueue.scala 105:65]
  assign source_valid_1_io_in = source_valid_0_io_out; // @[AsyncQueue.scala 116:26]
  assign source_valid_1_clock = clock; // @[AsyncQueue.scala 111:26]
  assign source_valid_1_reset = reset; // @[AsyncQueue.scala 106:65]
  assign sink_extend_io_in = io_async_safe_ridx_valid; // @[AsyncQueue.scala 118:23]
  assign sink_extend_clock = clock; // @[AsyncQueue.scala 112:26]
  assign sink_extend_reset = reset; // @[AsyncQueue.scala 107:65]
  assign sink_valid_io_in = sink_extend_io_out; // @[AsyncQueue.scala 119:22]
  assign sink_valid_clock = clock; // @[AsyncQueue.scala 113:26]
  assign sink_valid_reset = reset; // @[AsyncQueue.scala 108:35]
  always @(posedge clock) begin
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      mem_0_opcode <= io_enq_bits_opcode; // @[AsyncQueue.scala 86:37]
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      mem_0_address <= io_enq_bits_address; // @[AsyncQueue.scala 86:37]
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      mem_0_data <= io_enq_bits_data; // @[AsyncQueue.scala 86:37]
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[AsyncQueue.scala 53:23]
      widx_widx_bin <= 1'h0;
    end else if (_widx_T_2) begin
      widx_widx_bin <= 1'h0;
    end else begin
      widx_widx_bin <= widx_widx_bin + _widx_T_1;
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[AsyncQueue.scala 83:26]
      ready_reg <= 1'h0;
    end else begin
      ready_reg <= sink_ready & widx_incremented != (ridx ^ 1'h1);
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[AsyncQueue.scala 53:23]
      widx_gray <= 1'h0;
    end else if (_widx_T_2) begin
      widx_gray <= 1'h0;
    end else begin
      widx_gray <= widx_widx_bin + _widx_T_1;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  mem_0_opcode = _RAND_0[2:0];
  _RAND_1 = {1{`RANDOM}};
  mem_0_address = _RAND_1[8:0];
  _RAND_2 = {1{`RANDOM}};
  mem_0_data = _RAND_2[31:0];
  _RAND_3 = {1{`RANDOM}};
  widx_widx_bin = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  ready_reg = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  widx_gray = _RAND_5[0:0];
`endif // RANDOMIZE_REG_INIT
  if (reset) begin
    widx_widx_bin = 1'h0;
  end
  if (reset) begin
    ready_reg = 1'h0;
  end
  if (reset) begin
    widx_gray = 1'h0;
  end
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ClockCrossingReg_w43(
  input         clock,
  input  [42:0] io_d,
  output [42:0] io_q,
  input         io_en
);
`ifdef RANDOMIZE_REG_INIT
  reg [63:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg [42:0] cdc_reg; // @[Reg.scala 16:16]
  assign io_q = cdc_reg; // @[SynchronizerReg.scala 202:8]
  always @(posedge clock) begin
    if (io_en) begin // @[Reg.scala 17:18]
      cdc_reg <= io_d; // @[Reg.scala 17:22]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {2{`RANDOM}};
  cdc_reg = _RAND_0[42:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module AsyncQueueSink_1(
  input         clock,
  input         reset,
  input         io_deq_ready,
  output        io_deq_valid,
  output [2:0]  io_deq_bits_opcode,
  output [1:0]  io_deq_bits_param,
  output [1:0]  io_deq_bits_size,
  output        io_deq_bits_source,
  output        io_deq_bits_sink,
  output        io_deq_bits_denied,
  output [31:0] io_deq_bits_data,
  output        io_deq_bits_corrupt,
  input  [2:0]  io_async_mem_0_opcode,
  input  [1:0]  io_async_mem_0_size,
  input         io_async_mem_0_source,
  input  [31:0] io_async_mem_0_data,
  output        io_async_ridx,
  input         io_async_widx,
  output        io_async_safe_ridx_valid,
  input         io_async_safe_widx_valid,
  output        io_async_safe_sink_reset_n
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
  wire  widx_widx_gray_clock; // @[ShiftReg.scala 45:23]
  wire  widx_widx_gray_reset; // @[ShiftReg.scala 45:23]
  wire  widx_widx_gray_io_d; // @[ShiftReg.scala 45:23]
  wire  widx_widx_gray_io_q; // @[ShiftReg.scala 45:23]
  wire  io_deq_bits_deq_bits_reg_clock; // @[SynchronizerReg.scala 207:25]
  wire [42:0] io_deq_bits_deq_bits_reg_io_d; // @[SynchronizerReg.scala 207:25]
  wire [42:0] io_deq_bits_deq_bits_reg_io_q; // @[SynchronizerReg.scala 207:25]
  wire  io_deq_bits_deq_bits_reg_io_en; // @[SynchronizerReg.scala 207:25]
  wire  sink_valid_0_io_in; // @[AsyncQueue.scala 168:33]
  wire  sink_valid_0_io_out; // @[AsyncQueue.scala 168:33]
  wire  sink_valid_0_clock; // @[AsyncQueue.scala 168:33]
  wire  sink_valid_0_reset; // @[AsyncQueue.scala 168:33]
  wire  sink_valid_1_io_in; // @[AsyncQueue.scala 169:33]
  wire  sink_valid_1_io_out; // @[AsyncQueue.scala 169:33]
  wire  sink_valid_1_clock; // @[AsyncQueue.scala 169:33]
  wire  sink_valid_1_reset; // @[AsyncQueue.scala 169:33]
  wire  source_extend_io_in; // @[AsyncQueue.scala 171:31]
  wire  source_extend_io_out; // @[AsyncQueue.scala 171:31]
  wire  source_extend_clock; // @[AsyncQueue.scala 171:31]
  wire  source_extend_reset; // @[AsyncQueue.scala 171:31]
  wire  source_valid_io_in; // @[AsyncQueue.scala 172:31]
  wire  source_valid_io_out; // @[AsyncQueue.scala 172:31]
  wire  source_valid_clock; // @[AsyncQueue.scala 172:31]
  wire  source_valid_reset; // @[AsyncQueue.scala 172:31]
  wire  _ridx_T_1 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
  wire  source_ready = source_valid_io_out;
  wire  _ridx_T_2 = ~source_ready; // @[AsyncQueue.scala 144:79]
  reg  ridx_ridx_bin; // @[AsyncQueue.scala 52:25]
  wire  ridx_incremented = _ridx_T_2 ? 1'h0 : ridx_ridx_bin + _ridx_T_1; // @[AsyncQueue.scala 53:23]
  wire  widx = widx_widx_gray_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire [34:0] io_deq_bits_deq_bits_reg_io_d_lo = {2'h0,io_async_mem_0_data,1'h0}; // @[SynchronizerReg.scala 209:24]
  wire [7:0] io_deq_bits_deq_bits_reg_io_d_hi = {io_async_mem_0_opcode,2'h0,io_async_mem_0_size,io_async_mem_0_source}; // @[SynchronizerReg.scala 209:24]
  wire [42:0] _io_deq_bits_WIRE_1 = io_deq_bits_deq_bits_reg_io_q;
  reg  valid_reg; // @[AsyncQueue.scala 161:56]
  reg  ridx_gray; // @[AsyncQueue.scala 164:55]
  AsyncResetSynchronizerShiftReg_w1_d3_i0 widx_widx_gray ( // @[ShiftReg.scala 45:23]
    .clock(widx_widx_gray_clock),
    .reset(widx_widx_gray_reset),
    .io_d(widx_widx_gray_io_d),
    .io_q(widx_widx_gray_io_q)
  );
  ClockCrossingReg_w43 io_deq_bits_deq_bits_reg ( // @[SynchronizerReg.scala 207:25]
    .clock(io_deq_bits_deq_bits_reg_clock),
    .io_d(io_deq_bits_deq_bits_reg_io_d),
    .io_q(io_deq_bits_deq_bits_reg_io_q),
    .io_en(io_deq_bits_deq_bits_reg_io_en)
  );
  AsyncValidSync sink_valid_0 ( // @[AsyncQueue.scala 168:33]
    .io_in(sink_valid_0_io_in),
    .io_out(sink_valid_0_io_out),
    .clock(sink_valid_0_clock),
    .reset(sink_valid_0_reset)
  );
  AsyncValidSync sink_valid_1 ( // @[AsyncQueue.scala 169:33]
    .io_in(sink_valid_1_io_in),
    .io_out(sink_valid_1_io_out),
    .clock(sink_valid_1_clock),
    .reset(sink_valid_1_reset)
  );
  AsyncValidSync source_extend ( // @[AsyncQueue.scala 171:31]
    .io_in(source_extend_io_in),
    .io_out(source_extend_io_out),
    .clock(source_extend_clock),
    .reset(source_extend_reset)
  );
  AsyncValidSync source_valid ( // @[AsyncQueue.scala 172:31]
    .io_in(source_valid_io_in),
    .io_out(source_valid_io_out),
    .clock(source_valid_clock),
    .reset(source_valid_reset)
  );
  assign io_deq_valid = valid_reg & source_ready; // @[AsyncQueue.scala 162:29]
  assign io_deq_bits_opcode = _io_deq_bits_WIRE_1[42:40]; // @[SynchronizerReg.scala 211:26]
  assign io_deq_bits_param = _io_deq_bits_WIRE_1[39:38]; // @[SynchronizerReg.scala 211:26]
  assign io_deq_bits_size = _io_deq_bits_WIRE_1[37:36]; // @[SynchronizerReg.scala 211:26]
  assign io_deq_bits_source = _io_deq_bits_WIRE_1[35]; // @[SynchronizerReg.scala 211:26]
  assign io_deq_bits_sink = _io_deq_bits_WIRE_1[34]; // @[SynchronizerReg.scala 211:26]
  assign io_deq_bits_denied = _io_deq_bits_WIRE_1[33]; // @[SynchronizerReg.scala 211:26]
  assign io_deq_bits_data = _io_deq_bits_WIRE_1[32:1]; // @[SynchronizerReg.scala 211:26]
  assign io_deq_bits_corrupt = _io_deq_bits_WIRE_1[0]; // @[SynchronizerReg.scala 211:26]
  assign io_async_ridx = ridx_gray; // @[AsyncQueue.scala 165:17]
  assign io_async_safe_ridx_valid = sink_valid_1_io_out; // @[AsyncQueue.scala 185:20]
  assign io_async_safe_sink_reset_n = ~reset; // @[AsyncQueue.scala 189:25]
  assign widx_widx_gray_clock = clock;
  assign widx_widx_gray_reset = reset;
  assign widx_widx_gray_io_d = io_async_widx; // @[ShiftReg.scala 47:16]
  assign io_deq_bits_deq_bits_reg_clock = clock;
  assign io_deq_bits_deq_bits_reg_io_d = {io_deq_bits_deq_bits_reg_io_d_hi,io_deq_bits_deq_bits_reg_io_d_lo}; // @[SynchronizerReg.scala 209:24]
  assign io_deq_bits_deq_bits_reg_io_en = source_ready & ridx_incremented != widx; // @[AsyncQueue.scala 146:28]
  assign sink_valid_0_io_in = 1'h1; // @[AsyncQueue.scala 183:24]
  assign sink_valid_0_clock = clock; // @[AsyncQueue.scala 178:25]
  assign sink_valid_0_reset = reset; // @[AsyncQueue.scala 173:66]
  assign sink_valid_1_io_in = sink_valid_0_io_out; // @[AsyncQueue.scala 184:24]
  assign sink_valid_1_clock = clock; // @[AsyncQueue.scala 179:25]
  assign sink_valid_1_reset = reset; // @[AsyncQueue.scala 174:66]
  assign source_extend_io_in = io_async_safe_widx_valid; // @[AsyncQueue.scala 186:25]
  assign source_extend_clock = clock; // @[AsyncQueue.scala 180:25]
  assign source_extend_reset = reset; // @[AsyncQueue.scala 175:66]
  assign source_valid_io_in = source_extend_io_out; // @[AsyncQueue.scala 187:24]
  assign source_valid_clock = clock; // @[AsyncQueue.scala 181:25]
  assign source_valid_reset = reset; // @[AsyncQueue.scala 176:34]
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[AsyncQueue.scala 53:23]
      ridx_ridx_bin <= 1'h0;
    end else if (_ridx_T_2) begin
      ridx_ridx_bin <= 1'h0;
    end else begin
      ridx_ridx_bin <= ridx_ridx_bin + _ridx_T_1;
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[AsyncQueue.scala 146:28]
      valid_reg <= 1'h0;
    end else begin
      valid_reg <= source_ready & ridx_incremented != widx;
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[AsyncQueue.scala 53:23]
      ridx_gray <= 1'h0;
    end else if (_ridx_T_2) begin
      ridx_gray <= 1'h0;
    end else begin
      ridx_gray <= ridx_ridx_bin + _ridx_T_1;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  ridx_ridx_bin = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  valid_reg = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  ridx_gray = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
  if (reset) begin
    ridx_ridx_bin = 1'h0;
  end
  if (reset) begin
    valid_reg = 1'h0;
  end
  if (reset) begin
    ridx_gray = 1'h0;
  end
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLAsyncCrossingSource_1(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [8:0]  auto_in_a_bits_address,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [1:0]  auto_in_d_bits_param,
  output [1:0]  auto_in_d_bits_size,
  output        auto_in_d_bits_source,
  output        auto_in_d_bits_sink,
  output        auto_in_d_bits_denied,
  output [31:0] auto_in_d_bits_data,
  output        auto_in_d_bits_corrupt,
  output [2:0]  auto_out_a_mem_0_opcode,
  output [8:0]  auto_out_a_mem_0_address,
  output [31:0] auto_out_a_mem_0_data,
  input         auto_out_a_ridx,
  output        auto_out_a_widx,
  input         auto_out_a_safe_ridx_valid,
  output        auto_out_a_safe_widx_valid,
  output        auto_out_a_safe_source_reset_n,
  input  [2:0]  auto_out_d_mem_0_opcode,
  input  [1:0]  auto_out_d_mem_0_size,
  input         auto_out_d_mem_0_source,
  input  [31:0] auto_out_d_mem_0_data,
  output        auto_out_d_ridx,
  input         auto_out_d_widx,
  output        auto_out_d_safe_ridx_valid,
  input         auto_out_d_safe_widx_valid,
  output        auto_out_d_safe_sink_reset_n
);
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [8:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_param; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_sink; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_denied; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_corrupt; // @[Nodes.scala 24:25]
  wire  bundleOut_0_a_source_clock; // @[AsyncQueue.scala 216:24]
  wire  bundleOut_0_a_source_reset; // @[AsyncQueue.scala 216:24]
  wire  bundleOut_0_a_source_io_enq_ready; // @[AsyncQueue.scala 216:24]
  wire  bundleOut_0_a_source_io_enq_valid; // @[AsyncQueue.scala 216:24]
  wire [2:0] bundleOut_0_a_source_io_enq_bits_opcode; // @[AsyncQueue.scala 216:24]
  wire [8:0] bundleOut_0_a_source_io_enq_bits_address; // @[AsyncQueue.scala 216:24]
  wire [31:0] bundleOut_0_a_source_io_enq_bits_data; // @[AsyncQueue.scala 216:24]
  wire [2:0] bundleOut_0_a_source_io_async_mem_0_opcode; // @[AsyncQueue.scala 216:24]
  wire [8:0] bundleOut_0_a_source_io_async_mem_0_address; // @[AsyncQueue.scala 216:24]
  wire [31:0] bundleOut_0_a_source_io_async_mem_0_data; // @[AsyncQueue.scala 216:24]
  wire  bundleOut_0_a_source_io_async_ridx; // @[AsyncQueue.scala 216:24]
  wire  bundleOut_0_a_source_io_async_widx; // @[AsyncQueue.scala 216:24]
  wire  bundleOut_0_a_source_io_async_safe_ridx_valid; // @[AsyncQueue.scala 216:24]
  wire  bundleOut_0_a_source_io_async_safe_widx_valid; // @[AsyncQueue.scala 216:24]
  wire  bundleOut_0_a_source_io_async_safe_source_reset_n; // @[AsyncQueue.scala 216:24]
  wire  bundleIn_0_d_sink_clock; // @[AsyncQueue.scala 207:22]
  wire  bundleIn_0_d_sink_reset; // @[AsyncQueue.scala 207:22]
  wire  bundleIn_0_d_sink_io_deq_ready; // @[AsyncQueue.scala 207:22]
  wire  bundleIn_0_d_sink_io_deq_valid; // @[AsyncQueue.scala 207:22]
  wire [2:0] bundleIn_0_d_sink_io_deq_bits_opcode; // @[AsyncQueue.scala 207:22]
  wire [1:0] bundleIn_0_d_sink_io_deq_bits_param; // @[AsyncQueue.scala 207:22]
  wire [1:0] bundleIn_0_d_sink_io_deq_bits_size; // @[AsyncQueue.scala 207:22]
  wire  bundleIn_0_d_sink_io_deq_bits_source; // @[AsyncQueue.scala 207:22]
  wire  bundleIn_0_d_sink_io_deq_bits_sink; // @[AsyncQueue.scala 207:22]
  wire  bundleIn_0_d_sink_io_deq_bits_denied; // @[AsyncQueue.scala 207:22]
  wire [31:0] bundleIn_0_d_sink_io_deq_bits_data; // @[AsyncQueue.scala 207:22]
  wire  bundleIn_0_d_sink_io_deq_bits_corrupt; // @[AsyncQueue.scala 207:22]
  wire [2:0] bundleIn_0_d_sink_io_async_mem_0_opcode; // @[AsyncQueue.scala 207:22]
  wire [1:0] bundleIn_0_d_sink_io_async_mem_0_size; // @[AsyncQueue.scala 207:22]
  wire  bundleIn_0_d_sink_io_async_mem_0_source; // @[AsyncQueue.scala 207:22]
  wire [31:0] bundleIn_0_d_sink_io_async_mem_0_data; // @[AsyncQueue.scala 207:22]
  wire  bundleIn_0_d_sink_io_async_ridx; // @[AsyncQueue.scala 207:22]
  wire  bundleIn_0_d_sink_io_async_widx; // @[AsyncQueue.scala 207:22]
  wire  bundleIn_0_d_sink_io_async_safe_ridx_valid; // @[AsyncQueue.scala 207:22]
  wire  bundleIn_0_d_sink_io_async_safe_widx_valid; // @[AsyncQueue.scala 207:22]
  wire  bundleIn_0_d_sink_io_async_safe_sink_reset_n; // @[AsyncQueue.scala 207:22]
  TLMonitor_52 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_param(monitor_io_in_d_bits_param),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source),
    .io_in_d_bits_sink(monitor_io_in_d_bits_sink),
    .io_in_d_bits_denied(monitor_io_in_d_bits_denied),
    .io_in_d_bits_corrupt(monitor_io_in_d_bits_corrupt)
  );
  AsyncQueueSource_1 bundleOut_0_a_source ( // @[AsyncQueue.scala 216:24]
    .clock(bundleOut_0_a_source_clock),
    .reset(bundleOut_0_a_source_reset),
    .io_enq_ready(bundleOut_0_a_source_io_enq_ready),
    .io_enq_valid(bundleOut_0_a_source_io_enq_valid),
    .io_enq_bits_opcode(bundleOut_0_a_source_io_enq_bits_opcode),
    .io_enq_bits_address(bundleOut_0_a_source_io_enq_bits_address),
    .io_enq_bits_data(bundleOut_0_a_source_io_enq_bits_data),
    .io_async_mem_0_opcode(bundleOut_0_a_source_io_async_mem_0_opcode),
    .io_async_mem_0_address(bundleOut_0_a_source_io_async_mem_0_address),
    .io_async_mem_0_data(bundleOut_0_a_source_io_async_mem_0_data),
    .io_async_ridx(bundleOut_0_a_source_io_async_ridx),
    .io_async_widx(bundleOut_0_a_source_io_async_widx),
    .io_async_safe_ridx_valid(bundleOut_0_a_source_io_async_safe_ridx_valid),
    .io_async_safe_widx_valid(bundleOut_0_a_source_io_async_safe_widx_valid),
    .io_async_safe_source_reset_n(bundleOut_0_a_source_io_async_safe_source_reset_n)
  );
  AsyncQueueSink_1 bundleIn_0_d_sink ( // @[AsyncQueue.scala 207:22]
    .clock(bundleIn_0_d_sink_clock),
    .reset(bundleIn_0_d_sink_reset),
    .io_deq_ready(bundleIn_0_d_sink_io_deq_ready),
    .io_deq_valid(bundleIn_0_d_sink_io_deq_valid),
    .io_deq_bits_opcode(bundleIn_0_d_sink_io_deq_bits_opcode),
    .io_deq_bits_param(bundleIn_0_d_sink_io_deq_bits_param),
    .io_deq_bits_size(bundleIn_0_d_sink_io_deq_bits_size),
    .io_deq_bits_source(bundleIn_0_d_sink_io_deq_bits_source),
    .io_deq_bits_sink(bundleIn_0_d_sink_io_deq_bits_sink),
    .io_deq_bits_denied(bundleIn_0_d_sink_io_deq_bits_denied),
    .io_deq_bits_data(bundleIn_0_d_sink_io_deq_bits_data),
    .io_deq_bits_corrupt(bundleIn_0_d_sink_io_deq_bits_corrupt),
    .io_async_mem_0_opcode(bundleIn_0_d_sink_io_async_mem_0_opcode),
    .io_async_mem_0_size(bundleIn_0_d_sink_io_async_mem_0_size),
    .io_async_mem_0_source(bundleIn_0_d_sink_io_async_mem_0_source),
    .io_async_mem_0_data(bundleIn_0_d_sink_io_async_mem_0_data),
    .io_async_ridx(bundleIn_0_d_sink_io_async_ridx),
    .io_async_widx(bundleIn_0_d_sink_io_async_widx),
    .io_async_safe_ridx_valid(bundleIn_0_d_sink_io_async_safe_ridx_valid),
    .io_async_safe_widx_valid(bundleIn_0_d_sink_io_async_safe_widx_valid),
    .io_async_safe_sink_reset_n(bundleIn_0_d_sink_io_async_safe_sink_reset_n)
  );
  assign auto_in_a_ready = bundleOut_0_a_source_io_enq_ready; // @[Nodes.scala 1210:84 AsyncQueue.scala 217:19]
  assign auto_in_d_valid = bundleIn_0_d_sink_io_deq_valid; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
  assign auto_in_d_bits_opcode = bundleIn_0_d_sink_io_deq_bits_opcode; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
  assign auto_in_d_bits_param = bundleIn_0_d_sink_io_deq_bits_param; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
  assign auto_in_d_bits_size = bundleIn_0_d_sink_io_deq_bits_size; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
  assign auto_in_d_bits_source = bundleIn_0_d_sink_io_deq_bits_source; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
  assign auto_in_d_bits_sink = bundleIn_0_d_sink_io_deq_bits_sink; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
  assign auto_in_d_bits_denied = bundleIn_0_d_sink_io_deq_bits_denied; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
  assign auto_in_d_bits_data = bundleIn_0_d_sink_io_deq_bits_data; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
  assign auto_in_d_bits_corrupt = bundleIn_0_d_sink_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
  assign auto_out_a_mem_0_opcode = bundleOut_0_a_source_io_async_mem_0_opcode; // @[Nodes.scala 1207:84 AsyncCrossing.scala 25:13]
  assign auto_out_a_mem_0_address = bundleOut_0_a_source_io_async_mem_0_address; // @[Nodes.scala 1207:84 AsyncCrossing.scala 25:13]
  assign auto_out_a_mem_0_data = bundleOut_0_a_source_io_async_mem_0_data; // @[Nodes.scala 1207:84 AsyncCrossing.scala 25:13]
  assign auto_out_a_widx = bundleOut_0_a_source_io_async_widx; // @[Nodes.scala 1207:84 AsyncCrossing.scala 25:13]
  assign auto_out_a_safe_widx_valid = bundleOut_0_a_source_io_async_safe_widx_valid; // @[Nodes.scala 1207:84 AsyncCrossing.scala 25:13]
  assign auto_out_a_safe_source_reset_n = bundleOut_0_a_source_io_async_safe_source_reset_n; // @[Nodes.scala 1207:84 AsyncCrossing.scala 25:13]
  assign auto_out_d_ridx = bundleIn_0_d_sink_io_async_ridx; // @[Nodes.scala 1207:84 AsyncQueue.scala 208:19]
  assign auto_out_d_safe_ridx_valid = bundleIn_0_d_sink_io_async_safe_ridx_valid; // @[Nodes.scala 1207:84 AsyncQueue.scala 208:19]
  assign auto_out_d_safe_sink_reset_n = bundleIn_0_d_sink_io_async_safe_sink_reset_n; // @[Nodes.scala 1207:84 AsyncQueue.scala 208:19]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = bundleOut_0_a_source_io_enq_ready; // @[Nodes.scala 1210:84 AsyncQueue.scala 217:19]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = bundleIn_0_d_sink_io_deq_valid; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
  assign monitor_io_in_d_bits_opcode = bundleIn_0_d_sink_io_deq_bits_opcode; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
  assign monitor_io_in_d_bits_param = bundleIn_0_d_sink_io_deq_bits_param; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
  assign monitor_io_in_d_bits_size = bundleIn_0_d_sink_io_deq_bits_size; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
  assign monitor_io_in_d_bits_source = bundleIn_0_d_sink_io_deq_bits_source; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
  assign monitor_io_in_d_bits_sink = bundleIn_0_d_sink_io_deq_bits_sink; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
  assign monitor_io_in_d_bits_denied = bundleIn_0_d_sink_io_deq_bits_denied; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
  assign monitor_io_in_d_bits_corrupt = bundleIn_0_d_sink_io_deq_bits_corrupt; // @[Nodes.scala 1210:84 AsyncCrossing.scala 26:12]
  assign bundleOut_0_a_source_clock = clock;
  assign bundleOut_0_a_source_reset = reset;
  assign bundleOut_0_a_source_io_enq_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_source_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_source_io_enq_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_source_io_enq_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_source_io_async_ridx = auto_out_a_ridx; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleOut_0_a_source_io_async_safe_ridx_valid = auto_out_a_safe_ridx_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_sink_clock = clock;
  assign bundleIn_0_d_sink_reset = reset;
  assign bundleIn_0_d_sink_io_deq_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleIn_0_d_sink_io_async_mem_0_opcode = auto_out_d_mem_0_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_sink_io_async_mem_0_size = auto_out_d_mem_0_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_sink_io_async_mem_0_source = auto_out_d_mem_0_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_sink_io_async_mem_0_data = auto_out_d_mem_0_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_sink_io_async_widx = auto_out_d_widx; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_sink_io_async_safe_widx_valid = auto_out_d_safe_widx_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
endmodule
module AsyncQueueSource_2(
  input   clock,
  input   reset,
  output  io_enq_ready,
  input   io_enq_valid,
  input   io_enq_bits_resumereq,
  input   io_enq_bits_ackhavereset,
  input   io_enq_bits_hrmask_0,
  output  io_async_mem_0_resumereq,
  output  io_async_mem_0_ackhavereset,
  output  io_async_mem_0_hrmask_0,
  input   io_async_ridx,
  output  io_async_widx,
  input   io_async_safe_ridx_valid,
  output  io_async_safe_widx_valid,
  output  io_async_safe_source_reset_n
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
`endif // RANDOMIZE_REG_INIT
  wire  ridx_ridx_gray_clock; // @[ShiftReg.scala 45:23]
  wire  ridx_ridx_gray_reset; // @[ShiftReg.scala 45:23]
  wire  ridx_ridx_gray_io_d; // @[ShiftReg.scala 45:23]
  wire  ridx_ridx_gray_io_q; // @[ShiftReg.scala 45:23]
  wire  source_valid_0_io_in; // @[AsyncQueue.scala 100:32]
  wire  source_valid_0_io_out; // @[AsyncQueue.scala 100:32]
  wire  source_valid_0_clock; // @[AsyncQueue.scala 100:32]
  wire  source_valid_0_reset; // @[AsyncQueue.scala 100:32]
  wire  source_valid_1_io_in; // @[AsyncQueue.scala 101:32]
  wire  source_valid_1_io_out; // @[AsyncQueue.scala 101:32]
  wire  source_valid_1_clock; // @[AsyncQueue.scala 101:32]
  wire  source_valid_1_reset; // @[AsyncQueue.scala 101:32]
  wire  sink_extend_io_in; // @[AsyncQueue.scala 103:30]
  wire  sink_extend_io_out; // @[AsyncQueue.scala 103:30]
  wire  sink_extend_clock; // @[AsyncQueue.scala 103:30]
  wire  sink_extend_reset; // @[AsyncQueue.scala 103:30]
  wire  sink_valid_io_in; // @[AsyncQueue.scala 104:30]
  wire  sink_valid_io_out; // @[AsyncQueue.scala 104:30]
  wire  sink_valid_clock; // @[AsyncQueue.scala 104:30]
  wire  sink_valid_reset; // @[AsyncQueue.scala 104:30]
  reg  mem_0_resumereq; // @[AsyncQueue.scala 80:16]
  reg  mem_0_ackhavereset; // @[AsyncQueue.scala 80:16]
  reg  mem_0_hrmask_0; // @[AsyncQueue.scala 80:16]
  wire  _widx_T_1 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
  wire  sink_ready = sink_valid_io_out;
  wire  _widx_T_2 = ~sink_ready; // @[AsyncQueue.scala 81:79]
  reg  widx_widx_bin; // @[AsyncQueue.scala 52:25]
  wire  widx_incremented = _widx_T_2 ? 1'h0 : widx_widx_bin + _widx_T_1; // @[AsyncQueue.scala 53:23]
  wire  ridx = ridx_ridx_gray_io_q; // @[ShiftReg.scala 48:{24,24}]
  reg  ready_reg; // @[AsyncQueue.scala 88:56]
  reg  widx_gray; // @[AsyncQueue.scala 91:55]
  AsyncResetSynchronizerShiftReg_w1_d3_i0 ridx_ridx_gray ( // @[ShiftReg.scala 45:23]
    .clock(ridx_ridx_gray_clock),
    .reset(ridx_ridx_gray_reset),
    .io_d(ridx_ridx_gray_io_d),
    .io_q(ridx_ridx_gray_io_q)
  );
  AsyncValidSync source_valid_0 ( // @[AsyncQueue.scala 100:32]
    .io_in(source_valid_0_io_in),
    .io_out(source_valid_0_io_out),
    .clock(source_valid_0_clock),
    .reset(source_valid_0_reset)
  );
  AsyncValidSync source_valid_1 ( // @[AsyncQueue.scala 101:32]
    .io_in(source_valid_1_io_in),
    .io_out(source_valid_1_io_out),
    .clock(source_valid_1_clock),
    .reset(source_valid_1_reset)
  );
  AsyncValidSync sink_extend ( // @[AsyncQueue.scala 103:30]
    .io_in(sink_extend_io_in),
    .io_out(sink_extend_io_out),
    .clock(sink_extend_clock),
    .reset(sink_extend_reset)
  );
  AsyncValidSync sink_valid ( // @[AsyncQueue.scala 104:30]
    .io_in(sink_valid_io_in),
    .io_out(sink_valid_io_out),
    .clock(sink_valid_clock),
    .reset(sink_valid_reset)
  );
  assign io_enq_ready = ready_reg & sink_ready; // @[AsyncQueue.scala 89:29]
  assign io_async_mem_0_resumereq = mem_0_resumereq; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_0_ackhavereset = mem_0_ackhavereset; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_0_hrmask_0 = mem_0_hrmask_0; // @[AsyncQueue.scala 96:31]
  assign io_async_widx = widx_gray; // @[AsyncQueue.scala 92:17]
  assign io_async_safe_widx_valid = source_valid_1_io_out; // @[AsyncQueue.scala 117:20]
  assign io_async_safe_source_reset_n = ~reset; // @[AsyncQueue.scala 121:27]
  assign ridx_ridx_gray_clock = clock;
  assign ridx_ridx_gray_reset = reset;
  assign ridx_ridx_gray_io_d = io_async_ridx; // @[ShiftReg.scala 47:16]
  assign source_valid_0_io_in = 1'h1; // @[AsyncQueue.scala 115:26]
  assign source_valid_0_clock = clock; // @[AsyncQueue.scala 110:26]
  assign source_valid_0_reset = reset; // @[AsyncQueue.scala 105:65]
  assign source_valid_1_io_in = source_valid_0_io_out; // @[AsyncQueue.scala 116:26]
  assign source_valid_1_clock = clock; // @[AsyncQueue.scala 111:26]
  assign source_valid_1_reset = reset; // @[AsyncQueue.scala 106:65]
  assign sink_extend_io_in = io_async_safe_ridx_valid; // @[AsyncQueue.scala 118:23]
  assign sink_extend_clock = clock; // @[AsyncQueue.scala 112:26]
  assign sink_extend_reset = reset; // @[AsyncQueue.scala 107:65]
  assign sink_valid_io_in = sink_extend_io_out; // @[AsyncQueue.scala 119:22]
  assign sink_valid_clock = clock; // @[AsyncQueue.scala 113:26]
  assign sink_valid_reset = reset; // @[AsyncQueue.scala 108:35]
  always @(posedge clock) begin
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      mem_0_resumereq <= io_enq_bits_resumereq; // @[AsyncQueue.scala 86:37]
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      mem_0_ackhavereset <= io_enq_bits_ackhavereset; // @[AsyncQueue.scala 86:37]
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      mem_0_hrmask_0 <= io_enq_bits_hrmask_0; // @[AsyncQueue.scala 86:37]
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[AsyncQueue.scala 53:23]
      widx_widx_bin <= 1'h0;
    end else if (_widx_T_2) begin
      widx_widx_bin <= 1'h0;
    end else begin
      widx_widx_bin <= widx_widx_bin + _widx_T_1;
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[AsyncQueue.scala 83:26]
      ready_reg <= 1'h0;
    end else begin
      ready_reg <= sink_ready & widx_incremented != (ridx ^ 1'h1);
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[AsyncQueue.scala 53:23]
      widx_gray <= 1'h0;
    end else if (_widx_T_2) begin
      widx_gray <= 1'h0;
    end else begin
      widx_gray <= widx_widx_bin + _widx_T_1;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  mem_0_resumereq = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  mem_0_ackhavereset = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  mem_0_hrmask_0 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  widx_widx_bin = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  ready_reg = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  widx_gray = _RAND_5[0:0];
`endif // RANDOMIZE_REG_INIT
  if (reset) begin
    widx_widx_bin = 1'h0;
  end
  if (reset) begin
    ready_reg = 1'h0;
  end
  if (reset) begin
    widx_gray = 1'h0;
  end
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLDebugModuleOuterAsync(
  output [2:0]  auto_asource_out_a_mem_0_opcode,
  output [8:0]  auto_asource_out_a_mem_0_address,
  output [31:0] auto_asource_out_a_mem_0_data,
  input         auto_asource_out_a_ridx,
  output        auto_asource_out_a_widx,
  input         auto_asource_out_a_safe_ridx_valid,
  output        auto_asource_out_a_safe_widx_valid,
  output        auto_asource_out_a_safe_source_reset_n,
  input  [2:0]  auto_asource_out_d_mem_0_opcode,
  input  [1:0]  auto_asource_out_d_mem_0_size,
  input         auto_asource_out_d_mem_0_source,
  input  [31:0] auto_asource_out_d_mem_0_data,
  output        auto_asource_out_d_ridx,
  input         auto_asource_out_d_widx,
  output        auto_asource_out_d_safe_ridx_valid,
  input         auto_asource_out_d_safe_widx_valid,
  output        auto_asource_out_d_safe_sink_reset_n,
  output        auto_intsource_out_sync_0,
  input         io_dmi_clock,
  input         io_dmi_reset,
  output        io_dmi_req_ready,
  input         io_dmi_req_valid,
  input  [6:0]  io_dmi_req_bits_addr,
  input  [31:0] io_dmi_req_bits_data,
  input  [1:0]  io_dmi_req_bits_op,
  input         io_dmi_resp_ready,
  output        io_dmi_resp_valid,
  output [31:0] io_dmi_resp_bits_data,
  output [1:0]  io_dmi_resp_bits_resp,
  output        io_ctrl_ndreset,
  output        io_ctrl_dmactive,
  output        io_innerCtrl_mem_0_resumereq,
  output        io_innerCtrl_mem_0_ackhavereset,
  output        io_innerCtrl_mem_0_hrmask_0,
  input         io_innerCtrl_ridx,
  output        io_innerCtrl_widx,
  input         io_innerCtrl_safe_ridx_valid,
  output        io_innerCtrl_safe_widx_valid,
  output        io_innerCtrl_safe_source_reset_n,
  input         io_hgDebugInt_0
);
  wire  dmiXbar_clock; // @[Debug.scala 624:28]
  wire  dmiXbar_reset; // @[Debug.scala 624:28]
  wire  dmiXbar_auto_in_a_ready; // @[Debug.scala 624:28]
  wire  dmiXbar_auto_in_a_valid; // @[Debug.scala 624:28]
  wire [2:0] dmiXbar_auto_in_a_bits_opcode; // @[Debug.scala 624:28]
  wire [8:0] dmiXbar_auto_in_a_bits_address; // @[Debug.scala 624:28]
  wire [31:0] dmiXbar_auto_in_a_bits_data; // @[Debug.scala 624:28]
  wire  dmiXbar_auto_in_d_ready; // @[Debug.scala 624:28]
  wire  dmiXbar_auto_in_d_valid; // @[Debug.scala 624:28]
  wire  dmiXbar_auto_in_d_bits_denied; // @[Debug.scala 624:28]
  wire [31:0] dmiXbar_auto_in_d_bits_data; // @[Debug.scala 624:28]
  wire  dmiXbar_auto_in_d_bits_corrupt; // @[Debug.scala 624:28]
  wire  dmiXbar_auto_out_1_a_ready; // @[Debug.scala 624:28]
  wire  dmiXbar_auto_out_1_a_valid; // @[Debug.scala 624:28]
  wire [2:0] dmiXbar_auto_out_1_a_bits_opcode; // @[Debug.scala 624:28]
  wire [6:0] dmiXbar_auto_out_1_a_bits_address; // @[Debug.scala 624:28]
  wire [31:0] dmiXbar_auto_out_1_a_bits_data; // @[Debug.scala 624:28]
  wire  dmiXbar_auto_out_1_d_ready; // @[Debug.scala 624:28]
  wire  dmiXbar_auto_out_1_d_valid; // @[Debug.scala 624:28]
  wire [2:0] dmiXbar_auto_out_1_d_bits_opcode; // @[Debug.scala 624:28]
  wire [31:0] dmiXbar_auto_out_1_d_bits_data; // @[Debug.scala 624:28]
  wire  dmiXbar_auto_out_0_a_ready; // @[Debug.scala 624:28]
  wire  dmiXbar_auto_out_0_a_valid; // @[Debug.scala 624:28]
  wire [2:0] dmiXbar_auto_out_0_a_bits_opcode; // @[Debug.scala 624:28]
  wire [8:0] dmiXbar_auto_out_0_a_bits_address; // @[Debug.scala 624:28]
  wire [31:0] dmiXbar_auto_out_0_a_bits_data; // @[Debug.scala 624:28]
  wire  dmiXbar_auto_out_0_d_ready; // @[Debug.scala 624:28]
  wire  dmiXbar_auto_out_0_d_valid; // @[Debug.scala 624:28]
  wire [2:0] dmiXbar_auto_out_0_d_bits_opcode; // @[Debug.scala 624:28]
  wire [1:0] dmiXbar_auto_out_0_d_bits_param; // @[Debug.scala 624:28]
  wire [1:0] dmiXbar_auto_out_0_d_bits_size; // @[Debug.scala 624:28]
  wire  dmiXbar_auto_out_0_d_bits_sink; // @[Debug.scala 624:28]
  wire  dmiXbar_auto_out_0_d_bits_denied; // @[Debug.scala 624:28]
  wire [31:0] dmiXbar_auto_out_0_d_bits_data; // @[Debug.scala 624:28]
  wire  dmiXbar_auto_out_0_d_bits_corrupt; // @[Debug.scala 624:28]
  wire  dmi2tl_auto_out_a_ready; // @[Debug.scala 627:28]
  wire  dmi2tl_auto_out_a_valid; // @[Debug.scala 627:28]
  wire [2:0] dmi2tl_auto_out_a_bits_opcode; // @[Debug.scala 627:28]
  wire [8:0] dmi2tl_auto_out_a_bits_address; // @[Debug.scala 627:28]
  wire [31:0] dmi2tl_auto_out_a_bits_data; // @[Debug.scala 627:28]
  wire  dmi2tl_auto_out_d_ready; // @[Debug.scala 627:28]
  wire  dmi2tl_auto_out_d_valid; // @[Debug.scala 627:28]
  wire  dmi2tl_auto_out_d_bits_denied; // @[Debug.scala 627:28]
  wire [31:0] dmi2tl_auto_out_d_bits_data; // @[Debug.scala 627:28]
  wire  dmi2tl_auto_out_d_bits_corrupt; // @[Debug.scala 627:28]
  wire  dmi2tl_io_dmi_req_ready; // @[Debug.scala 627:28]
  wire  dmi2tl_io_dmi_req_valid; // @[Debug.scala 627:28]
  wire [6:0] dmi2tl_io_dmi_req_bits_addr; // @[Debug.scala 627:28]
  wire [31:0] dmi2tl_io_dmi_req_bits_data; // @[Debug.scala 627:28]
  wire [1:0] dmi2tl_io_dmi_req_bits_op; // @[Debug.scala 627:28]
  wire  dmi2tl_io_dmi_resp_ready; // @[Debug.scala 627:28]
  wire  dmi2tl_io_dmi_resp_valid; // @[Debug.scala 627:28]
  wire [31:0] dmi2tl_io_dmi_resp_bits_data; // @[Debug.scala 627:28]
  wire [1:0] dmi2tl_io_dmi_resp_bits_resp; // @[Debug.scala 627:28]
  wire  dmOuter_clock; // @[Debug.scala 649:27]
  wire  dmOuter_reset; // @[Debug.scala 649:27]
  wire  dmOuter_auto_dmi_in_a_ready; // @[Debug.scala 649:27]
  wire  dmOuter_auto_dmi_in_a_valid; // @[Debug.scala 649:27]
  wire [2:0] dmOuter_auto_dmi_in_a_bits_opcode; // @[Debug.scala 649:27]
  wire [6:0] dmOuter_auto_dmi_in_a_bits_address; // @[Debug.scala 649:27]
  wire [31:0] dmOuter_auto_dmi_in_a_bits_data; // @[Debug.scala 649:27]
  wire  dmOuter_auto_dmi_in_d_ready; // @[Debug.scala 649:27]
  wire  dmOuter_auto_dmi_in_d_valid; // @[Debug.scala 649:27]
  wire [2:0] dmOuter_auto_dmi_in_d_bits_opcode; // @[Debug.scala 649:27]
  wire [31:0] dmOuter_auto_dmi_in_d_bits_data; // @[Debug.scala 649:27]
  wire  dmOuter_auto_int_out_0; // @[Debug.scala 649:27]
  wire  dmOuter_io_ctrl_ndreset; // @[Debug.scala 649:27]
  wire  dmOuter_io_ctrl_dmactive; // @[Debug.scala 649:27]
  wire  dmOuter_io_ctrl_dmactiveAck; // @[Debug.scala 649:27]
  wire  dmOuter_io_innerCtrl_ready; // @[Debug.scala 649:27]
  wire  dmOuter_io_innerCtrl_valid; // @[Debug.scala 649:27]
  wire  dmOuter_io_innerCtrl_bits_resumereq; // @[Debug.scala 649:27]
  wire [9:0] dmOuter_io_innerCtrl_bits_hartsel; // @[Debug.scala 649:27]
  wire  dmOuter_io_innerCtrl_bits_ackhavereset; // @[Debug.scala 649:27]
  wire  dmOuter_io_innerCtrl_bits_hrmask_0; // @[Debug.scala 649:27]
  wire  dmOuter_io_hgDebugInt_0; // @[Debug.scala 649:27]
  wire  intsource_auto_in_0; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_0; // @[Crossing.scala 26:31]
  wire  dmiBypass_clock; // @[Debug.scala 652:29]
  wire  dmiBypass_reset; // @[Debug.scala 652:29]
  wire  dmiBypass_auto_node_out_out_a_ready; // @[Debug.scala 652:29]
  wire  dmiBypass_auto_node_out_out_a_valid; // @[Debug.scala 652:29]
  wire [2:0] dmiBypass_auto_node_out_out_a_bits_opcode; // @[Debug.scala 652:29]
  wire [8:0] dmiBypass_auto_node_out_out_a_bits_address; // @[Debug.scala 652:29]
  wire [31:0] dmiBypass_auto_node_out_out_a_bits_data; // @[Debug.scala 652:29]
  wire  dmiBypass_auto_node_out_out_d_ready; // @[Debug.scala 652:29]
  wire  dmiBypass_auto_node_out_out_d_valid; // @[Debug.scala 652:29]
  wire [2:0] dmiBypass_auto_node_out_out_d_bits_opcode; // @[Debug.scala 652:29]
  wire [1:0] dmiBypass_auto_node_out_out_d_bits_param; // @[Debug.scala 652:29]
  wire [1:0] dmiBypass_auto_node_out_out_d_bits_size; // @[Debug.scala 652:29]
  wire  dmiBypass_auto_node_out_out_d_bits_source; // @[Debug.scala 652:29]
  wire  dmiBypass_auto_node_out_out_d_bits_sink; // @[Debug.scala 652:29]
  wire  dmiBypass_auto_node_out_out_d_bits_denied; // @[Debug.scala 652:29]
  wire [31:0] dmiBypass_auto_node_out_out_d_bits_data; // @[Debug.scala 652:29]
  wire  dmiBypass_auto_node_out_out_d_bits_corrupt; // @[Debug.scala 652:29]
  wire  dmiBypass_auto_node_in_in_a_ready; // @[Debug.scala 652:29]
  wire  dmiBypass_auto_node_in_in_a_valid; // @[Debug.scala 652:29]
  wire [2:0] dmiBypass_auto_node_in_in_a_bits_opcode; // @[Debug.scala 652:29]
  wire [8:0] dmiBypass_auto_node_in_in_a_bits_address; // @[Debug.scala 652:29]
  wire [31:0] dmiBypass_auto_node_in_in_a_bits_data; // @[Debug.scala 652:29]
  wire  dmiBypass_auto_node_in_in_d_ready; // @[Debug.scala 652:29]
  wire  dmiBypass_auto_node_in_in_d_valid; // @[Debug.scala 652:29]
  wire [2:0] dmiBypass_auto_node_in_in_d_bits_opcode; // @[Debug.scala 652:29]
  wire [1:0] dmiBypass_auto_node_in_in_d_bits_param; // @[Debug.scala 652:29]
  wire [1:0] dmiBypass_auto_node_in_in_d_bits_size; // @[Debug.scala 652:29]
  wire  dmiBypass_auto_node_in_in_d_bits_sink; // @[Debug.scala 652:29]
  wire  dmiBypass_auto_node_in_in_d_bits_denied; // @[Debug.scala 652:29]
  wire [31:0] dmiBypass_auto_node_in_in_d_bits_data; // @[Debug.scala 652:29]
  wire  dmiBypass_auto_node_in_in_d_bits_corrupt; // @[Debug.scala 652:29]
  wire  dmiBypass_io_bypass; // @[Debug.scala 652:29]
  wire  asource_clock; // @[AsyncCrossing.scala 87:29]
  wire  asource_reset; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_in_a_ready; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_in_a_valid; // @[AsyncCrossing.scala 87:29]
  wire [2:0] asource_auto_in_a_bits_opcode; // @[AsyncCrossing.scala 87:29]
  wire [8:0] asource_auto_in_a_bits_address; // @[AsyncCrossing.scala 87:29]
  wire [31:0] asource_auto_in_a_bits_data; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_in_d_ready; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_in_d_valid; // @[AsyncCrossing.scala 87:29]
  wire [2:0] asource_auto_in_d_bits_opcode; // @[AsyncCrossing.scala 87:29]
  wire [1:0] asource_auto_in_d_bits_param; // @[AsyncCrossing.scala 87:29]
  wire [1:0] asource_auto_in_d_bits_size; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_in_d_bits_source; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_in_d_bits_sink; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_in_d_bits_denied; // @[AsyncCrossing.scala 87:29]
  wire [31:0] asource_auto_in_d_bits_data; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_in_d_bits_corrupt; // @[AsyncCrossing.scala 87:29]
  wire [2:0] asource_auto_out_a_mem_0_opcode; // @[AsyncCrossing.scala 87:29]
  wire [8:0] asource_auto_out_a_mem_0_address; // @[AsyncCrossing.scala 87:29]
  wire [31:0] asource_auto_out_a_mem_0_data; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_out_a_ridx; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_out_a_widx; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_out_a_safe_ridx_valid; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_out_a_safe_widx_valid; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_out_a_safe_source_reset_n; // @[AsyncCrossing.scala 87:29]
  wire [2:0] asource_auto_out_d_mem_0_opcode; // @[AsyncCrossing.scala 87:29]
  wire [1:0] asource_auto_out_d_mem_0_size; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_out_d_mem_0_source; // @[AsyncCrossing.scala 87:29]
  wire [31:0] asource_auto_out_d_mem_0_data; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_out_d_ridx; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_out_d_widx; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_out_d_safe_ridx_valid; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_out_d_safe_widx_valid; // @[AsyncCrossing.scala 87:29]
  wire  asource_auto_out_d_safe_sink_reset_n; // @[AsyncCrossing.scala 87:29]
  wire  dmactiveAck_dmactiveAckSync_clock; // @[ShiftReg.scala 45:23]
  wire  dmactiveAck_dmactiveAckSync_reset; // @[ShiftReg.scala 45:23]
  wire  dmactiveAck_dmactiveAckSync_io_d; // @[ShiftReg.scala 45:23]
  wire  dmactiveAck_dmactiveAckSync_io_q; // @[ShiftReg.scala 45:23]
  wire  io_innerCtrl_source_clock; // @[AsyncQueue.scala 216:24]
  wire  io_innerCtrl_source_reset; // @[AsyncQueue.scala 216:24]
  wire  io_innerCtrl_source_io_enq_ready; // @[AsyncQueue.scala 216:24]
  wire  io_innerCtrl_source_io_enq_valid; // @[AsyncQueue.scala 216:24]
  wire  io_innerCtrl_source_io_enq_bits_resumereq; // @[AsyncQueue.scala 216:24]
  wire  io_innerCtrl_source_io_enq_bits_ackhavereset; // @[AsyncQueue.scala 216:24]
  wire  io_innerCtrl_source_io_enq_bits_hrmask_0; // @[AsyncQueue.scala 216:24]
  wire  io_innerCtrl_source_io_async_mem_0_resumereq; // @[AsyncQueue.scala 216:24]
  wire  io_innerCtrl_source_io_async_mem_0_ackhavereset; // @[AsyncQueue.scala 216:24]
  wire  io_innerCtrl_source_io_async_mem_0_hrmask_0; // @[AsyncQueue.scala 216:24]
  wire  io_innerCtrl_source_io_async_ridx; // @[AsyncQueue.scala 216:24]
  wire  io_innerCtrl_source_io_async_widx; // @[AsyncQueue.scala 216:24]
  wire  io_innerCtrl_source_io_async_safe_ridx_valid; // @[AsyncQueue.scala 216:24]
  wire  io_innerCtrl_source_io_async_safe_widx_valid; // @[AsyncQueue.scala 216:24]
  wire  io_innerCtrl_source_io_async_safe_source_reset_n; // @[AsyncQueue.scala 216:24]
  wire  dmactiveAck = dmactiveAck_dmactiveAckSync_io_q; // @[ShiftReg.scala 48:{24,24}]
  TLXbar_9 dmiXbar ( // @[Debug.scala 624:28]
    .clock(dmiXbar_clock),
    .reset(dmiXbar_reset),
    .auto_in_a_ready(dmiXbar_auto_in_a_ready),
    .auto_in_a_valid(dmiXbar_auto_in_a_valid),
    .auto_in_a_bits_opcode(dmiXbar_auto_in_a_bits_opcode),
    .auto_in_a_bits_address(dmiXbar_auto_in_a_bits_address),
    .auto_in_a_bits_data(dmiXbar_auto_in_a_bits_data),
    .auto_in_d_ready(dmiXbar_auto_in_d_ready),
    .auto_in_d_valid(dmiXbar_auto_in_d_valid),
    .auto_in_d_bits_denied(dmiXbar_auto_in_d_bits_denied),
    .auto_in_d_bits_data(dmiXbar_auto_in_d_bits_data),
    .auto_in_d_bits_corrupt(dmiXbar_auto_in_d_bits_corrupt),
    .auto_out_1_a_ready(dmiXbar_auto_out_1_a_ready),
    .auto_out_1_a_valid(dmiXbar_auto_out_1_a_valid),
    .auto_out_1_a_bits_opcode(dmiXbar_auto_out_1_a_bits_opcode),
    .auto_out_1_a_bits_address(dmiXbar_auto_out_1_a_bits_address),
    .auto_out_1_a_bits_data(dmiXbar_auto_out_1_a_bits_data),
    .auto_out_1_d_ready(dmiXbar_auto_out_1_d_ready),
    .auto_out_1_d_valid(dmiXbar_auto_out_1_d_valid),
    .auto_out_1_d_bits_opcode(dmiXbar_auto_out_1_d_bits_opcode),
    .auto_out_1_d_bits_data(dmiXbar_auto_out_1_d_bits_data),
    .auto_out_0_a_ready(dmiXbar_auto_out_0_a_ready),
    .auto_out_0_a_valid(dmiXbar_auto_out_0_a_valid),
    .auto_out_0_a_bits_opcode(dmiXbar_auto_out_0_a_bits_opcode),
    .auto_out_0_a_bits_address(dmiXbar_auto_out_0_a_bits_address),
    .auto_out_0_a_bits_data(dmiXbar_auto_out_0_a_bits_data),
    .auto_out_0_d_ready(dmiXbar_auto_out_0_d_ready),
    .auto_out_0_d_valid(dmiXbar_auto_out_0_d_valid),
    .auto_out_0_d_bits_opcode(dmiXbar_auto_out_0_d_bits_opcode),
    .auto_out_0_d_bits_param(dmiXbar_auto_out_0_d_bits_param),
    .auto_out_0_d_bits_size(dmiXbar_auto_out_0_d_bits_size),
    .auto_out_0_d_bits_sink(dmiXbar_auto_out_0_d_bits_sink),
    .auto_out_0_d_bits_denied(dmiXbar_auto_out_0_d_bits_denied),
    .auto_out_0_d_bits_data(dmiXbar_auto_out_0_d_bits_data),
    .auto_out_0_d_bits_corrupt(dmiXbar_auto_out_0_d_bits_corrupt)
  );
  DMIToTL dmi2tl ( // @[Debug.scala 627:28]
    .auto_out_a_ready(dmi2tl_auto_out_a_ready),
    .auto_out_a_valid(dmi2tl_auto_out_a_valid),
    .auto_out_a_bits_opcode(dmi2tl_auto_out_a_bits_opcode),
    .auto_out_a_bits_address(dmi2tl_auto_out_a_bits_address),
    .auto_out_a_bits_data(dmi2tl_auto_out_a_bits_data),
    .auto_out_d_ready(dmi2tl_auto_out_d_ready),
    .auto_out_d_valid(dmi2tl_auto_out_d_valid),
    .auto_out_d_bits_denied(dmi2tl_auto_out_d_bits_denied),
    .auto_out_d_bits_data(dmi2tl_auto_out_d_bits_data),
    .auto_out_d_bits_corrupt(dmi2tl_auto_out_d_bits_corrupt),
    .io_dmi_req_ready(dmi2tl_io_dmi_req_ready),
    .io_dmi_req_valid(dmi2tl_io_dmi_req_valid),
    .io_dmi_req_bits_addr(dmi2tl_io_dmi_req_bits_addr),
    .io_dmi_req_bits_data(dmi2tl_io_dmi_req_bits_data),
    .io_dmi_req_bits_op(dmi2tl_io_dmi_req_bits_op),
    .io_dmi_resp_ready(dmi2tl_io_dmi_resp_ready),
    .io_dmi_resp_valid(dmi2tl_io_dmi_resp_valid),
    .io_dmi_resp_bits_data(dmi2tl_io_dmi_resp_bits_data),
    .io_dmi_resp_bits_resp(dmi2tl_io_dmi_resp_bits_resp)
  );
  TLDebugModuleOuter dmOuter ( // @[Debug.scala 649:27]
    .clock(dmOuter_clock),
    .reset(dmOuter_reset),
    .auto_dmi_in_a_ready(dmOuter_auto_dmi_in_a_ready),
    .auto_dmi_in_a_valid(dmOuter_auto_dmi_in_a_valid),
    .auto_dmi_in_a_bits_opcode(dmOuter_auto_dmi_in_a_bits_opcode),
    .auto_dmi_in_a_bits_address(dmOuter_auto_dmi_in_a_bits_address),
    .auto_dmi_in_a_bits_data(dmOuter_auto_dmi_in_a_bits_data),
    .auto_dmi_in_d_ready(dmOuter_auto_dmi_in_d_ready),
    .auto_dmi_in_d_valid(dmOuter_auto_dmi_in_d_valid),
    .auto_dmi_in_d_bits_opcode(dmOuter_auto_dmi_in_d_bits_opcode),
    .auto_dmi_in_d_bits_data(dmOuter_auto_dmi_in_d_bits_data),
    .auto_int_out_0(dmOuter_auto_int_out_0),
    .io_ctrl_ndreset(dmOuter_io_ctrl_ndreset),
    .io_ctrl_dmactive(dmOuter_io_ctrl_dmactive),
    .io_ctrl_dmactiveAck(dmOuter_io_ctrl_dmactiveAck),
    .io_innerCtrl_ready(dmOuter_io_innerCtrl_ready),
    .io_innerCtrl_valid(dmOuter_io_innerCtrl_valid),
    .io_innerCtrl_bits_resumereq(dmOuter_io_innerCtrl_bits_resumereq),
    .io_innerCtrl_bits_hartsel(dmOuter_io_innerCtrl_bits_hartsel),
    .io_innerCtrl_bits_ackhavereset(dmOuter_io_innerCtrl_bits_ackhavereset),
    .io_innerCtrl_bits_hrmask_0(dmOuter_io_innerCtrl_bits_hrmask_0),
    .io_hgDebugInt_0(dmOuter_io_hgDebugInt_0)
  );
  IntSyncCrossingSource_4 intsource ( // @[Crossing.scala 26:31]
    .auto_in_0(intsource_auto_in_0),
    .auto_out_sync_0(intsource_auto_out_sync_0)
  );
  TLBusBypass dmiBypass ( // @[Debug.scala 652:29]
    .clock(dmiBypass_clock),
    .reset(dmiBypass_reset),
    .auto_node_out_out_a_ready(dmiBypass_auto_node_out_out_a_ready),
    .auto_node_out_out_a_valid(dmiBypass_auto_node_out_out_a_valid),
    .auto_node_out_out_a_bits_opcode(dmiBypass_auto_node_out_out_a_bits_opcode),
    .auto_node_out_out_a_bits_address(dmiBypass_auto_node_out_out_a_bits_address),
    .auto_node_out_out_a_bits_data(dmiBypass_auto_node_out_out_a_bits_data),
    .auto_node_out_out_d_ready(dmiBypass_auto_node_out_out_d_ready),
    .auto_node_out_out_d_valid(dmiBypass_auto_node_out_out_d_valid),
    .auto_node_out_out_d_bits_opcode(dmiBypass_auto_node_out_out_d_bits_opcode),
    .auto_node_out_out_d_bits_param(dmiBypass_auto_node_out_out_d_bits_param),
    .auto_node_out_out_d_bits_size(dmiBypass_auto_node_out_out_d_bits_size),
    .auto_node_out_out_d_bits_source(dmiBypass_auto_node_out_out_d_bits_source),
    .auto_node_out_out_d_bits_sink(dmiBypass_auto_node_out_out_d_bits_sink),
    .auto_node_out_out_d_bits_denied(dmiBypass_auto_node_out_out_d_bits_denied),
    .auto_node_out_out_d_bits_data(dmiBypass_auto_node_out_out_d_bits_data),
    .auto_node_out_out_d_bits_corrupt(dmiBypass_auto_node_out_out_d_bits_corrupt),
    .auto_node_in_in_a_ready(dmiBypass_auto_node_in_in_a_ready),
    .auto_node_in_in_a_valid(dmiBypass_auto_node_in_in_a_valid),
    .auto_node_in_in_a_bits_opcode(dmiBypass_auto_node_in_in_a_bits_opcode),
    .auto_node_in_in_a_bits_address(dmiBypass_auto_node_in_in_a_bits_address),
    .auto_node_in_in_a_bits_data(dmiBypass_auto_node_in_in_a_bits_data),
    .auto_node_in_in_d_ready(dmiBypass_auto_node_in_in_d_ready),
    .auto_node_in_in_d_valid(dmiBypass_auto_node_in_in_d_valid),
    .auto_node_in_in_d_bits_opcode(dmiBypass_auto_node_in_in_d_bits_opcode),
    .auto_node_in_in_d_bits_param(dmiBypass_auto_node_in_in_d_bits_param),
    .auto_node_in_in_d_bits_size(dmiBypass_auto_node_in_in_d_bits_size),
    .auto_node_in_in_d_bits_sink(dmiBypass_auto_node_in_in_d_bits_sink),
    .auto_node_in_in_d_bits_denied(dmiBypass_auto_node_in_in_d_bits_denied),
    .auto_node_in_in_d_bits_data(dmiBypass_auto_node_in_in_d_bits_data),
    .auto_node_in_in_d_bits_corrupt(dmiBypass_auto_node_in_in_d_bits_corrupt),
    .io_bypass(dmiBypass_io_bypass)
  );
  TLAsyncCrossingSource_1 asource ( // @[AsyncCrossing.scala 87:29]
    .clock(asource_clock),
    .reset(asource_reset),
    .auto_in_a_ready(asource_auto_in_a_ready),
    .auto_in_a_valid(asource_auto_in_a_valid),
    .auto_in_a_bits_opcode(asource_auto_in_a_bits_opcode),
    .auto_in_a_bits_address(asource_auto_in_a_bits_address),
    .auto_in_a_bits_data(asource_auto_in_a_bits_data),
    .auto_in_d_ready(asource_auto_in_d_ready),
    .auto_in_d_valid(asource_auto_in_d_valid),
    .auto_in_d_bits_opcode(asource_auto_in_d_bits_opcode),
    .auto_in_d_bits_param(asource_auto_in_d_bits_param),
    .auto_in_d_bits_size(asource_auto_in_d_bits_size),
    .auto_in_d_bits_source(asource_auto_in_d_bits_source),
    .auto_in_d_bits_sink(asource_auto_in_d_bits_sink),
    .auto_in_d_bits_denied(asource_auto_in_d_bits_denied),
    .auto_in_d_bits_data(asource_auto_in_d_bits_data),
    .auto_in_d_bits_corrupt(asource_auto_in_d_bits_corrupt),
    .auto_out_a_mem_0_opcode(asource_auto_out_a_mem_0_opcode),
    .auto_out_a_mem_0_address(asource_auto_out_a_mem_0_address),
    .auto_out_a_mem_0_data(asource_auto_out_a_mem_0_data),
    .auto_out_a_ridx(asource_auto_out_a_ridx),
    .auto_out_a_widx(asource_auto_out_a_widx),
    .auto_out_a_safe_ridx_valid(asource_auto_out_a_safe_ridx_valid),
    .auto_out_a_safe_widx_valid(asource_auto_out_a_safe_widx_valid),
    .auto_out_a_safe_source_reset_n(asource_auto_out_a_safe_source_reset_n),
    .auto_out_d_mem_0_opcode(asource_auto_out_d_mem_0_opcode),
    .auto_out_d_mem_0_size(asource_auto_out_d_mem_0_size),
    .auto_out_d_mem_0_source(asource_auto_out_d_mem_0_source),
    .auto_out_d_mem_0_data(asource_auto_out_d_mem_0_data),
    .auto_out_d_ridx(asource_auto_out_d_ridx),
    .auto_out_d_widx(asource_auto_out_d_widx),
    .auto_out_d_safe_ridx_valid(asource_auto_out_d_safe_ridx_valid),
    .auto_out_d_safe_widx_valid(asource_auto_out_d_safe_widx_valid),
    .auto_out_d_safe_sink_reset_n(asource_auto_out_d_safe_sink_reset_n)
  );
  AsyncResetSynchronizerShiftReg_w1_d3_i0 dmactiveAck_dmactiveAckSync ( // @[ShiftReg.scala 45:23]
    .clock(dmactiveAck_dmactiveAckSync_clock),
    .reset(dmactiveAck_dmactiveAckSync_reset),
    .io_d(dmactiveAck_dmactiveAckSync_io_d),
    .io_q(dmactiveAck_dmactiveAckSync_io_q)
  );
  AsyncQueueSource_2 io_innerCtrl_source ( // @[AsyncQueue.scala 216:24]
    .clock(io_innerCtrl_source_clock),
    .reset(io_innerCtrl_source_reset),
    .io_enq_ready(io_innerCtrl_source_io_enq_ready),
    .io_enq_valid(io_innerCtrl_source_io_enq_valid),
    .io_enq_bits_resumereq(io_innerCtrl_source_io_enq_bits_resumereq),
    .io_enq_bits_ackhavereset(io_innerCtrl_source_io_enq_bits_ackhavereset),
    .io_enq_bits_hrmask_0(io_innerCtrl_source_io_enq_bits_hrmask_0),
    .io_async_mem_0_resumereq(io_innerCtrl_source_io_async_mem_0_resumereq),
    .io_async_mem_0_ackhavereset(io_innerCtrl_source_io_async_mem_0_ackhavereset),
    .io_async_mem_0_hrmask_0(io_innerCtrl_source_io_async_mem_0_hrmask_0),
    .io_async_ridx(io_innerCtrl_source_io_async_ridx),
    .io_async_widx(io_innerCtrl_source_io_async_widx),
    .io_async_safe_ridx_valid(io_innerCtrl_source_io_async_safe_ridx_valid),
    .io_async_safe_widx_valid(io_innerCtrl_source_io_async_safe_widx_valid),
    .io_async_safe_source_reset_n(io_innerCtrl_source_io_async_safe_source_reset_n)
  );
  assign auto_asource_out_a_mem_0_opcode = asource_auto_out_a_mem_0_opcode; // @[LazyModule.scala 311:12]
  assign auto_asource_out_a_mem_0_address = asource_auto_out_a_mem_0_address; // @[LazyModule.scala 311:12]
  assign auto_asource_out_a_mem_0_data = asource_auto_out_a_mem_0_data; // @[LazyModule.scala 311:12]
  assign auto_asource_out_a_widx = asource_auto_out_a_widx; // @[LazyModule.scala 311:12]
  assign auto_asource_out_a_safe_widx_valid = asource_auto_out_a_safe_widx_valid; // @[LazyModule.scala 311:12]
  assign auto_asource_out_a_safe_source_reset_n = asource_auto_out_a_safe_source_reset_n; // @[LazyModule.scala 311:12]
  assign auto_asource_out_d_ridx = asource_auto_out_d_ridx; // @[LazyModule.scala 311:12]
  assign auto_asource_out_d_safe_ridx_valid = asource_auto_out_d_safe_ridx_valid; // @[LazyModule.scala 311:12]
  assign auto_asource_out_d_safe_sink_reset_n = asource_auto_out_d_safe_sink_reset_n; // @[LazyModule.scala 311:12]
  assign auto_intsource_out_sync_0 = intsource_auto_out_sync_0; // @[LazyModule.scala 311:12]
  assign io_dmi_req_ready = dmi2tl_io_dmi_req_ready; // @[Debug.scala 677:43]
  assign io_dmi_resp_valid = dmi2tl_io_dmi_resp_valid; // @[Debug.scala 677:43]
  assign io_dmi_resp_bits_data = dmi2tl_io_dmi_resp_bits_data; // @[Debug.scala 677:43]
  assign io_dmi_resp_bits_resp = dmi2tl_io_dmi_resp_bits_resp; // @[Debug.scala 677:43]
  assign io_ctrl_ndreset = dmOuter_io_ctrl_ndreset; // @[Debug.scala 682:15]
  assign io_ctrl_dmactive = dmOuter_io_ctrl_dmactive; // @[Debug.scala 682:15]
  assign io_innerCtrl_mem_0_resumereq = io_innerCtrl_source_io_async_mem_0_resumereq; // @[Debug.scala 684:20]
  assign io_innerCtrl_mem_0_ackhavereset = io_innerCtrl_source_io_async_mem_0_ackhavereset; // @[Debug.scala 684:20]
  assign io_innerCtrl_mem_0_hrmask_0 = io_innerCtrl_source_io_async_mem_0_hrmask_0; // @[Debug.scala 684:20]
  assign io_innerCtrl_widx = io_innerCtrl_source_io_async_widx; // @[Debug.scala 684:20]
  assign io_innerCtrl_safe_widx_valid = io_innerCtrl_source_io_async_safe_widx_valid; // @[Debug.scala 684:20]
  assign io_innerCtrl_safe_source_reset_n = io_innerCtrl_source_io_async_safe_source_reset_n; // @[Debug.scala 684:20]
  assign dmiXbar_clock = io_dmi_clock; // @[LazyModule.scala 350:31 Debug.scala 673:16]
  assign dmiXbar_reset = io_dmi_reset; // @[LazyModule.scala 352:31 Debug.scala 674:16]
  assign dmiXbar_auto_in_a_valid = dmi2tl_auto_out_a_valid; // @[LazyModule.scala 296:16]
  assign dmiXbar_auto_in_a_bits_opcode = dmi2tl_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign dmiXbar_auto_in_a_bits_address = dmi2tl_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign dmiXbar_auto_in_a_bits_data = dmi2tl_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign dmiXbar_auto_in_d_ready = dmi2tl_auto_out_d_ready; // @[LazyModule.scala 296:16]
  assign dmiXbar_auto_out_1_a_ready = dmOuter_auto_dmi_in_a_ready; // @[LazyModule.scala 298:16]
  assign dmiXbar_auto_out_1_d_valid = dmOuter_auto_dmi_in_d_valid; // @[LazyModule.scala 298:16]
  assign dmiXbar_auto_out_1_d_bits_opcode = dmOuter_auto_dmi_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign dmiXbar_auto_out_1_d_bits_data = dmOuter_auto_dmi_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign dmiXbar_auto_out_0_a_ready = dmiBypass_auto_node_in_in_a_ready; // @[LazyModule.scala 298:16]
  assign dmiXbar_auto_out_0_d_valid = dmiBypass_auto_node_in_in_d_valid; // @[LazyModule.scala 298:16]
  assign dmiXbar_auto_out_0_d_bits_opcode = dmiBypass_auto_node_in_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign dmiXbar_auto_out_0_d_bits_param = dmiBypass_auto_node_in_in_d_bits_param; // @[LazyModule.scala 298:16]
  assign dmiXbar_auto_out_0_d_bits_size = dmiBypass_auto_node_in_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign dmiXbar_auto_out_0_d_bits_sink = dmiBypass_auto_node_in_in_d_bits_sink; // @[LazyModule.scala 298:16]
  assign dmiXbar_auto_out_0_d_bits_denied = dmiBypass_auto_node_in_in_d_bits_denied; // @[LazyModule.scala 298:16]
  assign dmiXbar_auto_out_0_d_bits_data = dmiBypass_auto_node_in_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign dmiXbar_auto_out_0_d_bits_corrupt = dmiBypass_auto_node_in_in_d_bits_corrupt; // @[LazyModule.scala 298:16]
  assign dmi2tl_auto_out_a_ready = dmiXbar_auto_in_a_ready; // @[LazyModule.scala 296:16]
  assign dmi2tl_auto_out_d_valid = dmiXbar_auto_in_d_valid; // @[LazyModule.scala 296:16]
  assign dmi2tl_auto_out_d_bits_denied = dmiXbar_auto_in_d_bits_denied; // @[LazyModule.scala 296:16]
  assign dmi2tl_auto_out_d_bits_data = dmiXbar_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
  assign dmi2tl_auto_out_d_bits_corrupt = dmiXbar_auto_in_d_bits_corrupt; // @[LazyModule.scala 296:16]
  assign dmi2tl_io_dmi_req_valid = io_dmi_req_valid; // @[Debug.scala 677:43]
  assign dmi2tl_io_dmi_req_bits_addr = io_dmi_req_bits_addr; // @[Debug.scala 677:43]
  assign dmi2tl_io_dmi_req_bits_data = io_dmi_req_bits_data; // @[Debug.scala 677:43]
  assign dmi2tl_io_dmi_req_bits_op = io_dmi_req_bits_op; // @[Debug.scala 677:43]
  assign dmi2tl_io_dmi_resp_ready = io_dmi_resp_ready; // @[Debug.scala 677:43]
  assign dmOuter_clock = io_dmi_clock; // @[LazyModule.scala 350:31 Debug.scala 673:16]
  assign dmOuter_reset = io_dmi_reset; // @[LazyModule.scala 352:31 Debug.scala 674:16]
  assign dmOuter_auto_dmi_in_a_valid = dmiXbar_auto_out_1_a_valid; // @[LazyModule.scala 298:16]
  assign dmOuter_auto_dmi_in_a_bits_opcode = dmiXbar_auto_out_1_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign dmOuter_auto_dmi_in_a_bits_address = dmiXbar_auto_out_1_a_bits_address; // @[LazyModule.scala 298:16]
  assign dmOuter_auto_dmi_in_a_bits_data = dmiXbar_auto_out_1_a_bits_data; // @[LazyModule.scala 298:16]
  assign dmOuter_auto_dmi_in_d_ready = dmiXbar_auto_out_1_d_ready; // @[LazyModule.scala 298:16]
  assign dmOuter_io_ctrl_dmactiveAck = dmactiveAck_dmactiveAckSync_io_q; // @[ShiftReg.scala 48:{24,24}]
  assign dmOuter_io_innerCtrl_ready = io_innerCtrl_source_io_enq_ready; // @[AsyncQueue.scala 217:19]
  assign dmOuter_io_hgDebugInt_0 = io_hgDebugInt_0; // @[Debug.scala 685:36]
  assign intsource_auto_in_0 = dmOuter_auto_int_out_0; // @[LazyModule.scala 298:16]
  assign dmiBypass_clock = io_dmi_clock; // @[LazyModule.scala 350:31 Debug.scala 673:16]
  assign dmiBypass_reset = io_dmi_reset; // @[LazyModule.scala 352:31 Debug.scala 674:16]
  assign dmiBypass_auto_node_out_out_a_ready = asource_auto_in_a_ready; // @[LazyModule.scala 298:16]
  assign dmiBypass_auto_node_out_out_d_valid = asource_auto_in_d_valid; // @[LazyModule.scala 298:16]
  assign dmiBypass_auto_node_out_out_d_bits_opcode = asource_auto_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign dmiBypass_auto_node_out_out_d_bits_param = asource_auto_in_d_bits_param; // @[LazyModule.scala 298:16]
  assign dmiBypass_auto_node_out_out_d_bits_size = asource_auto_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign dmiBypass_auto_node_out_out_d_bits_source = asource_auto_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign dmiBypass_auto_node_out_out_d_bits_sink = asource_auto_in_d_bits_sink; // @[LazyModule.scala 298:16]
  assign dmiBypass_auto_node_out_out_d_bits_denied = asource_auto_in_d_bits_denied; // @[LazyModule.scala 298:16]
  assign dmiBypass_auto_node_out_out_d_bits_data = asource_auto_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign dmiBypass_auto_node_out_out_d_bits_corrupt = asource_auto_in_d_bits_corrupt; // @[LazyModule.scala 298:16]
  assign dmiBypass_auto_node_in_in_a_valid = dmiXbar_auto_out_0_a_valid; // @[LazyModule.scala 298:16]
  assign dmiBypass_auto_node_in_in_a_bits_opcode = dmiXbar_auto_out_0_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign dmiBypass_auto_node_in_in_a_bits_address = dmiXbar_auto_out_0_a_bits_address; // @[LazyModule.scala 298:16]
  assign dmiBypass_auto_node_in_in_a_bits_data = dmiXbar_auto_out_0_a_bits_data; // @[LazyModule.scala 298:16]
  assign dmiBypass_auto_node_in_in_d_ready = dmiXbar_auto_out_0_d_ready; // @[LazyModule.scala 298:16]
  assign dmiBypass_io_bypass = ~io_ctrl_dmactive | ~dmactiveAck; // @[Debug.scala 680:55]
  assign asource_clock = io_dmi_clock; // @[LazyModule.scala 350:31 Debug.scala 673:16]
  assign asource_reset = io_dmi_reset; // @[LazyModule.scala 352:31 Debug.scala 674:16]
  assign asource_auto_in_a_valid = dmiBypass_auto_node_out_out_a_valid; // @[LazyModule.scala 298:16]
  assign asource_auto_in_a_bits_opcode = dmiBypass_auto_node_out_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign asource_auto_in_a_bits_address = dmiBypass_auto_node_out_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign asource_auto_in_a_bits_data = dmiBypass_auto_node_out_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign asource_auto_in_d_ready = dmiBypass_auto_node_out_out_d_ready; // @[LazyModule.scala 298:16]
  assign asource_auto_out_a_ridx = auto_asource_out_a_ridx; // @[LazyModule.scala 311:12]
  assign asource_auto_out_a_safe_ridx_valid = auto_asource_out_a_safe_ridx_valid; // @[LazyModule.scala 311:12]
  assign asource_auto_out_d_mem_0_opcode = auto_asource_out_d_mem_0_opcode; // @[LazyModule.scala 311:12]
  assign asource_auto_out_d_mem_0_size = auto_asource_out_d_mem_0_size; // @[LazyModule.scala 311:12]
  assign asource_auto_out_d_mem_0_source = auto_asource_out_d_mem_0_source; // @[LazyModule.scala 311:12]
  assign asource_auto_out_d_mem_0_data = auto_asource_out_d_mem_0_data; // @[LazyModule.scala 311:12]
  assign asource_auto_out_d_widx = auto_asource_out_d_widx; // @[LazyModule.scala 311:12]
  assign asource_auto_out_d_safe_widx_valid = auto_asource_out_d_safe_widx_valid; // @[LazyModule.scala 311:12]
  assign dmactiveAck_dmactiveAckSync_clock = io_dmi_clock; // @[LazyModule.scala 350:31 Debug.scala 673:16]
  assign dmactiveAck_dmactiveAckSync_reset = io_dmi_reset; // @[LazyModule.scala 352:31 Debug.scala 674:16]
  assign dmactiveAck_dmactiveAckSync_io_d = 1'h0; // @[ShiftReg.scala 47:16]
  assign io_innerCtrl_source_clock = io_dmi_clock; // @[LazyModule.scala 350:31 Debug.scala 673:16]
  assign io_innerCtrl_source_reset = io_dmi_reset; // @[LazyModule.scala 352:31 Debug.scala 674:16]
  assign io_innerCtrl_source_io_enq_valid = dmOuter_io_innerCtrl_valid; // @[AsyncQueue.scala 217:19]
  assign io_innerCtrl_source_io_enq_bits_resumereq = dmOuter_io_innerCtrl_bits_resumereq; // @[AsyncQueue.scala 217:19]
  assign io_innerCtrl_source_io_enq_bits_ackhavereset = dmOuter_io_innerCtrl_bits_ackhavereset; // @[AsyncQueue.scala 217:19]
  assign io_innerCtrl_source_io_enq_bits_hrmask_0 = dmOuter_io_innerCtrl_bits_hrmask_0; // @[AsyncQueue.scala 217:19]
  assign io_innerCtrl_source_io_async_ridx = io_innerCtrl_ridx; // @[Debug.scala 684:20]
  assign io_innerCtrl_source_io_async_safe_ridx_valid = io_innerCtrl_safe_ridx_valid; // @[Debug.scala 684:20]
endmodule
module TLMonitor_53(
  input        clock,
  input        io_in_a_ready,
  input        io_in_a_valid,
  input  [2:0] io_in_a_bits_opcode,
  input  [2:0] io_in_a_bits_param,
  input  [1:0] io_in_a_bits_size,
  input        io_in_a_bits_source,
  input  [8:0] io_in_a_bits_address,
  input  [3:0] io_in_a_bits_mask,
  input        io_in_a_bits_corrupt,
  input        io_in_d_ready,
  input        io_in_d_valid,
  input  [2:0] io_in_d_bits_opcode,
  input  [1:0] io_in_d_bits_size,
  input        io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _source_ok_T = ~io_in_a_bits_source; // @[Parameters.scala 46:9]
  wire [4:0] _is_aligned_mask_T_1 = 5'h3 << io_in_a_bits_size; // @[package.scala 234:77]
  wire [1:0] is_aligned_mask = ~_is_aligned_mask_T_1[1:0]; // @[package.scala 234:46]
  wire [8:0] _GEN_71 = {{7'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [8:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 2'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_5 = ~_source_ok_T; // @[Monitor.scala 63:7]
  wire [9:0] _T_7 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
  wire  _T_15 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [9:0] _T_23 = $signed(_T_7) & -10'sh40; // @[Parameters.scala 137:52]
  wire  _T_24 = $signed(_T_23) == 10'sh0; // @[Parameters.scala 137:67]
  wire [8:0] _T_25 = io_in_a_bits_address ^ 9'h44; // @[Parameters.scala 137:31]
  wire [9:0] _T_26 = {1'b0,$signed(_T_25)}; // @[Parameters.scala 137:49]
  wire [9:0] _T_28 = $signed(_T_26) & -10'shc; // @[Parameters.scala 137:52]
  wire  _T_29 = $signed(_T_28) == 10'sh0; // @[Parameters.scala 137:67]
  wire [8:0] _T_30 = io_in_a_bits_address ^ 9'h58; // @[Parameters.scala 137:31]
  wire [9:0] _T_31 = {1'b0,$signed(_T_30)}; // @[Parameters.scala 137:49]
  wire [9:0] _T_33 = $signed(_T_31) & -10'sh8; // @[Parameters.scala 137:52]
  wire  _T_34 = $signed(_T_33) == 10'sh0; // @[Parameters.scala 137:67]
  wire [8:0] _T_35 = io_in_a_bits_address ^ 9'h60; // @[Parameters.scala 137:31]
  wire [9:0] _T_36 = {1'b0,$signed(_T_35)}; // @[Parameters.scala 137:49]
  wire [9:0] _T_38 = $signed(_T_36) & -10'sh20; // @[Parameters.scala 137:52]
  wire  _T_39 = $signed(_T_38) == 10'sh0; // @[Parameters.scala 137:67]
  wire [8:0] _T_40 = io_in_a_bits_address ^ 9'h80; // @[Parameters.scala 137:31]
  wire [9:0] _T_41 = {1'b0,$signed(_T_40)}; // @[Parameters.scala 137:49]
  wire [9:0] _T_43 = $signed(_T_41) & -10'sh80; // @[Parameters.scala 137:52]
  wire  _T_44 = $signed(_T_43) == 10'sh0; // @[Parameters.scala 137:67]
  wire [8:0] _T_45 = io_in_a_bits_address ^ 9'h100; // @[Parameters.scala 137:31]
  wire [9:0] _T_46 = {1'b0,$signed(_T_45)}; // @[Parameters.scala 137:49]
  wire [9:0] _T_48 = $signed(_T_46) & -10'sh100; // @[Parameters.scala 137:52]
  wire  _T_49 = $signed(_T_48) == 10'sh0; // @[Parameters.scala 137:67]
  wire  _T_54 = _T_24 | _T_29 | _T_34 | _T_39 | _T_44 | _T_49; // @[Parameters.scala 671:42]
  wire  _T_116 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_120 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_121 = _T_120 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_125 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_129 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_234 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_247 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_248 = 2'h2 == io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_250 = _T_248 & _source_ok_T; // @[Parameters.scala 1160:30]
  wire  _T_256 = io_in_a_bits_size <= 2'h2; // @[Parameters.scala 92:42]
  wire  _T_294 = _T_256 & _T_54; // @[Parameters.scala 670:56]
  wire  _T_305 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_309 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_317 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_363 = _T_250 & _T_294; // @[Monitor.scala 115:71]
  wire  _T_381 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_440 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_441 = io_in_a_bits_mask & _T_440; // @[Monitor.scala 127:31]
  wire  _T_442 = _T_441 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_446 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_498 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_506 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_558 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_566 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_618 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_630 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_1 = ~io_in_d_bits_source; // @[Parameters.scala 46:9]
  wire  _T_634 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_638 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 312:27]
  wire  _T_654 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_682 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_711 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_728 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_746 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [1:0] size; // @[Monitor.scala 386:22]
  reg  source; // @[Monitor.scala 387:22]
  reg [8:0] address; // @[Monitor.scala 388:22]
  wire  _T_776 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_777 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_781 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_785 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_789 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_793 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] size_1; // @[Monitor.scala 537:22]
  reg  source_1; // @[Monitor.scala 538:22]
  wire  _T_800 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_801 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_809 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_813 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg  inflight; // @[Monitor.scala 611:27]
  reg [3:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [3:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [2:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [3:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [15:0] _GEN_73 = {{12'd0}, _a_opcode_lookup_T_1}; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_6 = _GEN_73 & _a_opcode_lookup_T_5; // @[Monitor.scala 634:97]
  wire [15:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala 634:152]
  wire [3:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [15:0] _GEN_76 = {{12'd0}, _a_size_lookup_T_1}; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_6 = _GEN_76 & _a_opcode_lookup_T_5; // @[Monitor.scala 638:91]
  wire [15:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala 638:144]
  wire  _T_827 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [1:0] _a_set_wo_ready_T = 2'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_830 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
  wire [2:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [3:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [18:0] _GEN_0 = {{15'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [18:0] _a_opcodes_set_T_1 = _GEN_0 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
  wire [17:0] _GEN_1 = {{15'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [17:0] _a_sizes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire  _T_834 = ~(inflight >> io_in_a_bits_source); // @[Monitor.scala 658:17]
  wire [1:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 2'h0; // @[Monitor.scala 652:72 653:28]
  wire [18:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 19'h0; // @[Monitor.scala 652:72 656:28]
  wire [17:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 18'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_838 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_840 = ~_T_634; // @[Monitor.scala 671:74]
  wire  _T_841 = io_in_d_valid & d_first_1 & ~_T_634; // @[Monitor.scala 671:71]
  wire [1:0] _d_clr_wo_ready_T = 2'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [30:0] _GEN_2 = {{15'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [30:0] _d_opcodes_clr_T_5 = _GEN_2 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [1:0] _GEN_22 = d_first_done & d_first_1 & _T_840 ? _d_clr_wo_ready_T : 2'h0; // @[Monitor.scala 675:91 676:21]
  wire [30:0] _GEN_23 = d_first_done & d_first_1 & _T_840 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_827 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire  _T_853 = inflight >> io_in_d_bits_source | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_858 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_859 = io_in_d_bits_opcode == _GEN_32 | _T_858; // @[Monitor.scala 685:77]
  wire  _T_863 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_870 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_871 = io_in_d_bits_opcode == _GEN_48 | _T_870; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_875 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_885 = _T_838 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_840; // @[Monitor.scala 694:116]
  wire  _T_887 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire  a_set = _GEN_16[0];
  wire  d_clr = _GEN_22[0];
  wire [3:0] a_opcodes_set = _GEN_19[3:0];
  wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [3:0] d_opcodes_clr = _GEN_23[3:0];
  wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [3:0] a_sizes_set = _GEN_20[3:0];
  wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_896 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [3:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [15:0] _GEN_87 = {{12'd0}, _c_size_lookup_T_1}; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_6 = _GEN_87 & _a_opcode_lookup_T_5; // @[Monitor.scala 747:93]
  wire [15:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala 747:146]
  wire  _T_922 = io_in_d_valid & d_first_2 & _T_634; // @[Monitor.scala 779:71]
  wire [30:0] _GEN_68 = d_first_done & d_first_2 & _T_634 ? _d_opcodes_clr_T_5 : 31'h0; // @[Monitor.scala 783:90 785:21]
  wire  _T_930 = 1'h0 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_940 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [3:0] d_opcodes_clr_1 = _GEN_68[3:0];
  wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 1'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= 1'h0;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    inflight <= (inflight | a_set) & ~d_clr; // @[Monitor.scala 702:36]
    inflight_opcodes <= _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
    inflight_sizes <= _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
    if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 1'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= 1'h0;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    inflight_sizes_1 <= inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
    if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= 1'h0;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_15) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_15) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_5 & (io_in_a_valid & _T_15)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_15)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_15)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_116 & (io_in_a_valid & _T_15)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~_T_116) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_121 & (io_in_a_valid & _T_15)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~_T_121) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_125 & (io_in_a_valid & _T_15)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_15 & ~_T_125) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_129) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_129) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_129) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_129) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_5 & (io_in_a_valid & _T_129)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_129 & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_129)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_129 & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_129)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_129 & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_116 & (io_in_a_valid & _T_129)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_129 & ~_T_116) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_234 & (io_in_a_valid & _T_129)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_129 & ~_T_234) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_121 & (io_in_a_valid & _T_129)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_129 & ~_T_121) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_125 & (io_in_a_valid & _T_129)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_129 & ~_T_125) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_250 & (io_in_a_valid & _T_247)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_247 & ~_T_250) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_294 & (io_in_a_valid & _T_247)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_247 & ~_T_294) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_5 & (io_in_a_valid & _T_247)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_247 & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_247)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_247 & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_305 & (io_in_a_valid & _T_247)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_247 & ~_T_305) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_309 & (io_in_a_valid & _T_247)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_247 & ~_T_309) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_125 & (io_in_a_valid & _T_247)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_247 & ~_T_125) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_363 & (io_in_a_valid & _T_317)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~_T_363) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_5 & (io_in_a_valid & _T_317)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_317)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_305 & (io_in_a_valid & _T_317)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~_T_305) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_309 & (io_in_a_valid & _T_317)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~_T_309) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_381) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_381) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_5 & (io_in_a_valid & _T_381)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_381 & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_381)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_381 & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_305 & (io_in_a_valid & _T_381)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_381 & ~_T_305) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_442 & (io_in_a_valid & _T_381)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_381 & ~_T_442) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_446) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_446) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_5 & (io_in_a_valid & _T_446)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_446 & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_446)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_446 & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_498 & (io_in_a_valid & _T_446)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_446 & ~_T_498) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_309 & (io_in_a_valid & _T_446)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_446 & ~_T_309) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_506) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_506) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_5 & (io_in_a_valid & _T_506)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_506 & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_506)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_506 & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_558 & (io_in_a_valid & _T_506)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_506 & ~_T_558) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_309 & (io_in_a_valid & _T_506)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_506 & ~_T_309) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_566) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_566) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_5 & (io_in_a_valid & _T_566)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_566 & _T_5) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_566)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_566 & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_618 & (io_in_a_valid & _T_566)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_566 & ~_T_618) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_309 & (io_in_a_valid & _T_566)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_566 & ~_T_309) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_125 & (io_in_a_valid & _T_566)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_566 & ~_T_125) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_630 & io_in_d_valid) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & ~_T_630) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at Debug.scala:1746:19)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_1 & (io_in_d_valid & _T_634)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_634 & ~_source_ok_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Debug.scala:1746:19)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_638 & (io_in_d_valid & _T_634)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_634 & ~_T_638) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Debug.scala:1746:19)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_1 & (io_in_d_valid & _T_654)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_654 & ~_source_ok_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at Debug.scala:1746:19)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_654) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_654) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Debug.scala:1746:19)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_638 & (io_in_d_valid & _T_654)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_654 & ~_T_638) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at Debug.scala:1746:19)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_1 & (io_in_d_valid & _T_682)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_682 & ~_source_ok_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Debug.scala:1746:19)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_682) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_682) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Debug.scala:1746:19)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_638 & (io_in_d_valid & _T_682)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_682 & ~_T_638) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Debug.scala:1746:19)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_1 & (io_in_d_valid & _T_711)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_711 & ~_source_ok_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Debug.scala:1746:19)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_1 & (io_in_d_valid & _T_728)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_728 & ~_source_ok_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Debug.scala:1746:19)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_1 & (io_in_d_valid & _T_746)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_746 & ~_source_ok_T_1) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Debug.scala:1746:19)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_777 & _T_776) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_776 & ~_T_777) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_781 & _T_776) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_776 & ~_T_781) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_785 & _T_776) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_776 & ~_T_785) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_789 & _T_776) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_776 & ~_T_789) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_793 & _T_776) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_776 & ~_T_793) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_801 & _T_800) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_800 & ~_T_801) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Debug.scala:1746:19)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_809 & _T_800) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_800 & ~_T_809) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at Debug.scala:1746:19)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_813 & _T_800) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_800 & ~_T_813) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at Debug.scala:1746:19)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_834 & _T_830) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_830 & ~_T_834) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_853 & _T_841) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_841 & ~_T_853) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Debug.scala:1746:19)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_859 & (_T_841 & same_cycle_resp)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_841 & same_cycle_resp & ~_T_859) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Debug.scala:1746:19)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_863 & (_T_841 & same_cycle_resp)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_841 & same_cycle_resp & ~_T_863) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Debug.scala:1746:19)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_871 & (_T_841 & ~same_cycle_resp)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_841 & ~same_cycle_resp & ~_T_871) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Debug.scala:1746:19)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_875 & (_T_841 & ~same_cycle_resp)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_841 & ~same_cycle_resp & ~_T_875) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Debug.scala:1746:19)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_887 & _T_885) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_885 & ~_T_887) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_896) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~_T_896) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Debug.scala:1746:19)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_930 & _T_922) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_922 & ~_T_930) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Debug.scala:1746:19)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_940 & _T_922) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_922 & ~_T_940) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Debug.scala:1746:19)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[8:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  inflight = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  inflight_opcodes = _RAND_11[3:0];
  _RAND_12 = {1{`RANDOM}};
  inflight_sizes = _RAND_12[3:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  inflight_sizes_1 = _RAND_16[3:0];
  _RAND_17 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_17[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLMonitor_54(
  input         clock,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [1:0]  io_in_a_bits_size,
  input  [6:0]  io_in_a_bits_source,
  input  [11:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_size,
  input  [6:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [95:0] _RAND_10;
  reg [383:0] _RAND_11;
  reg [383:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [95:0] _RAND_16;
  reg [383:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _source_ok_T_4 = io_in_a_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire [4:0] _is_aligned_mask_T_1 = 5'h3 << io_in_a_bits_size; // @[package.scala 234:77]
  wire [1:0] is_aligned_mask = ~_is_aligned_mask_T_1[1:0]; // @[package.scala 234:46]
  wire [11:0] _GEN_71 = {{10'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [11:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 12'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 2'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
  wire [12:0] _T_12 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 137:49]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [12:0] _T_36 = $signed(_T_12) & 13'sh1000; // @[Parameters.scala 137:52]
  wire  _T_37 = $signed(_T_36) == 13'sh0; // @[Parameters.scala 137:67]
  wire  _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_74 = _T_73 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_164 = io_in_a_bits_size <= 2'h2; // @[Parameters.scala 92:42]
  wire  _T_172 = _T_164 & _T_37; // @[Parameters.scala 670:56]
  wire  _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_218 = _source_ok_T_4 & _T_172; // @[Monitor.scala 115:71]
  wire  _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_273 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_274 = io_in_a_bits_mask & _T_273; // @[Monitor.scala 127:31]
  wire  _T_275 = _T_274 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_279 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_347 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_355 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_385 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_397 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_10 = io_in_d_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire  _T_401 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_405 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 312:27]
  wire  _T_421 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_449 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_478 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_495 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_513 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [1:0] size; // @[Monitor.scala 386:22]
  reg [6:0] source; // @[Monitor.scala 387:22]
  reg [11:0] address; // @[Monitor.scala 388:22]
  wire  _T_543 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_544 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_548 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_552 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_556 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_560 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] size_1; // @[Monitor.scala 537:22]
  reg [6:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_567 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_568 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_576 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_580 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [95:0] inflight; // @[Monitor.scala 611:27]
  reg [383:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [383:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [8:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [9:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [383:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [383:0] _GEN_73 = {{368'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[383:1]}; // @[Monitor.scala 634:152]
  wire [383:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [383:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
  wire [383:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[383:1]}; // @[Monitor.scala 638:144]
  wire  _T_594 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [127:0] _a_set_wo_ready_T = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_597 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
  wire [8:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [9:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [1026:0] _GEN_0 = {{1023'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [1026:0] _a_opcodes_set_T_1 = _GEN_0 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
  wire [1025:0] _GEN_1 = {{1023'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [1025:0] _a_sizes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [95:0] _T_599 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_601 = ~_T_599[0]; // @[Monitor.scala 658:17]
  wire [127:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 652:72 653:28]
  wire [1026:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 1027'h0; // @[Monitor.scala 652:72 656:28]
  wire [1025:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 1026'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_605 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_607 = ~_T_401; // @[Monitor.scala 671:74]
  wire  _T_608 = io_in_d_valid & d_first_1 & ~_T_401; // @[Monitor.scala 671:71]
  wire [127:0] _d_clr_wo_ready_T = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [1038:0] _GEN_2 = {{1023'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [1038:0] _d_opcodes_clr_T_5 = _GEN_2 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [127:0] _GEN_22 = d_first_done & d_first_1 & _T_607 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 675:91 676:21]
  wire [1038:0] _GEN_23 = d_first_done & d_first_1 & _T_607 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_594 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [95:0] _T_618 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_620 = _T_618[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_625 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_626 = io_in_d_bits_opcode == _GEN_32 | _T_625; // @[Monitor.scala 685:77]
  wire  _T_630 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_637 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_638 = io_in_d_bits_opcode == _GEN_48 | _T_637; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_642 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_652 = _T_605 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_607; // @[Monitor.scala 694:116]
  wire  _T_654 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [95:0] a_set = _GEN_16[95:0];
  wire [95:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [95:0] d_clr = _GEN_22[95:0];
  wire [95:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [383:0] a_opcodes_set = _GEN_19[383:0];
  wire [383:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [383:0] d_opcodes_clr = _GEN_23[383:0];
  wire [383:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [383:0] a_sizes_set = _GEN_20[383:0];
  wire [383:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_663 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [95:0] inflight_1; // @[Monitor.scala 723:35]
  reg [383:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [383:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [383:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
  wire [383:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[383:1]}; // @[Monitor.scala 747:146]
  wire  _T_689 = io_in_d_valid & d_first_2 & _T_401; // @[Monitor.scala 779:71]
  wire [127:0] _GEN_67 = d_first_done & d_first_2 & _T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 783:90 784:21]
  wire [1038:0] _GEN_68 = d_first_done & d_first_2 & _T_401 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 783:90 785:21]
  wire [95:0] _T_697 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_707 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [95:0] d_clr_1 = _GEN_67[95:0];
  wire [95:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [383:0] d_opcodes_clr_1 = _GEN_68[383:0];
  wire [383:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_727 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 1'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= 1'h0;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    inflight <= _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
    inflight_opcodes <= _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
    inflight_sizes <= _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
    if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 1'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= 1'h0;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    inflight_1 <= inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
    inflight_sizes_1 <= inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
    if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= 1'h0;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (d_first_done) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_20)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_20)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_20)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_20)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_20)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_20)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_82)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_82)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_82)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_82)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_135 & (io_in_a_valid & _T_82)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~_T_135) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_82)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_82)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_172 & (io_in_a_valid & _T_148)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~_T_172) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_148)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_148)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_148)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_148)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_195)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_195)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_195)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_195)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_195)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_236)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_236)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_236)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_236)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_275 & (io_in_a_valid & _T_236)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~_T_275) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_279) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_279)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_279)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_309 & (io_in_a_valid & _T_279)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~_T_309) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_279)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_317) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_317)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_317)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_347 & (io_in_a_valid & _T_317)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~_T_347) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_317)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_355) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_355)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_355)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_385 & (io_in_a_valid & _T_355)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~_T_385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_355)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_355)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_397 & io_in_d_valid) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & ~_T_397) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at Periphery.scala:88:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_401)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Periphery.scala:88:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_401)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Periphery.scala:88:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_421)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at Periphery.scala:88:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_421) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Periphery.scala:88:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_421)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at Periphery.scala:88:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_449)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Periphery.scala:88:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_449) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Periphery.scala:88:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_449)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at Periphery.scala:88:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_478)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_478 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Periphery.scala:88:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_495)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_495 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Periphery.scala:88:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_513)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_513 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Periphery.scala:88:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_544 & _T_543) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~_T_544) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_548 & _T_543) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~_T_548) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_552 & _T_543) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~_T_552) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_556 & _T_543) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~_T_556) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_560 & _T_543) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~_T_560) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_568 & _T_567) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & ~_T_568) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Periphery.scala:88:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_576 & _T_567) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & ~_T_576) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at Periphery.scala:88:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_580 & _T_567) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & ~_T_580) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at Periphery.scala:88:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_601 & _T_597) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_597 & ~_T_601) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_620 & _T_608) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~_T_620) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Periphery.scala:88:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_626 & (_T_608 & same_cycle_resp)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & ~_T_626) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Periphery.scala:88:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_630 & (_T_608 & same_cycle_resp)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & ~_T_630) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Periphery.scala:88:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_638 & (_T_608 & ~same_cycle_resp)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & ~_T_638) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at Periphery.scala:88:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_642 & (_T_608 & ~same_cycle_resp)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & ~_T_642) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Periphery.scala:88:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_654 & _T_652) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_652 & ~_T_654) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_663) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~_T_663) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_697[0] & _T_689) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_689 & ~_T_697[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Periphery.scala:88:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_707 & _T_689) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_689 & ~_T_707) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at Periphery.scala:88:16)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_727) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~_T_727) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at Periphery.scala:88:16)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[6:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[11:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[6:0];
  _RAND_10 = {3{`RANDOM}};
  inflight = _RAND_10[95:0];
  _RAND_11 = {12{`RANDOM}};
  inflight_opcodes = _RAND_11[383:0];
  _RAND_12 = {12{`RANDOM}};
  inflight_sizes = _RAND_12[383:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {3{`RANDOM}};
  inflight_1 = _RAND_16[95:0];
  _RAND_17 = {12{`RANDOM}};
  inflight_sizes_1 = _RAND_17[383:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLDebugModuleInner(
  input         clock,
  output        auto_tl_in_a_ready,
  input         auto_tl_in_a_valid,
  input  [2:0]  auto_tl_in_a_bits_opcode,
  input  [2:0]  auto_tl_in_a_bits_param,
  input  [1:0]  auto_tl_in_a_bits_size,
  input  [6:0]  auto_tl_in_a_bits_source,
  input  [11:0] auto_tl_in_a_bits_address,
  input  [3:0]  auto_tl_in_a_bits_mask,
  input  [31:0] auto_tl_in_a_bits_data,
  input         auto_tl_in_a_bits_corrupt,
  input         auto_tl_in_d_ready,
  output        auto_tl_in_d_valid,
  output [2:0]  auto_tl_in_d_bits_opcode,
  output [1:0]  auto_tl_in_d_bits_size,
  output [6:0]  auto_tl_in_d_bits_source,
  output [31:0] auto_tl_in_d_bits_data,
  output        auto_dmi_in_a_ready,
  input         auto_dmi_in_a_valid,
  input  [2:0]  auto_dmi_in_a_bits_opcode,
  input  [2:0]  auto_dmi_in_a_bits_param,
  input  [1:0]  auto_dmi_in_a_bits_size,
  input         auto_dmi_in_a_bits_source,
  input  [8:0]  auto_dmi_in_a_bits_address,
  input  [3:0]  auto_dmi_in_a_bits_mask,
  input  [31:0] auto_dmi_in_a_bits_data,
  input         auto_dmi_in_a_bits_corrupt,
  input         auto_dmi_in_d_ready,
  output        auto_dmi_in_d_valid,
  output [2:0]  auto_dmi_in_d_bits_opcode,
  output [1:0]  auto_dmi_in_d_bits_size,
  output        auto_dmi_in_d_bits_source,
  output [31:0] auto_dmi_in_d_bits_data,
  input         io_dmactive,
  output        io_innerCtrl_ready,
  input         io_innerCtrl_valid,
  input         io_innerCtrl_bits_resumereq,
  input  [9:0]  io_innerCtrl_bits_hartsel,
  input         io_innerCtrl_bits_ackhavereset,
  input         io_innerCtrl_bits_hrmask_0,
  output        io_hgDebugInt_0
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [31:0] _RAND_33;
  reg [31:0] _RAND_34;
  reg [31:0] _RAND_35;
  reg [31:0] _RAND_36;
  reg [31:0] _RAND_37;
  reg [31:0] _RAND_38;
  reg [31:0] _RAND_39;
  reg [31:0] _RAND_40;
  reg [31:0] _RAND_41;
  reg [31:0] _RAND_42;
  reg [31:0] _RAND_43;
  reg [31:0] _RAND_44;
  reg [31:0] _RAND_45;
  reg [31:0] _RAND_46;
  reg [31:0] _RAND_47;
  reg [31:0] _RAND_48;
  reg [31:0] _RAND_49;
  reg [31:0] _RAND_50;
  reg [31:0] _RAND_51;
  reg [31:0] _RAND_52;
  reg [31:0] _RAND_53;
  reg [31:0] _RAND_54;
  reg [31:0] _RAND_55;
  reg [31:0] _RAND_56;
  reg [31:0] _RAND_57;
  reg [31:0] _RAND_58;
  reg [31:0] _RAND_59;
  reg [31:0] _RAND_60;
  reg [31:0] _RAND_61;
  reg [31:0] _RAND_62;
  reg [31:0] _RAND_63;
  reg [31:0] _RAND_64;
  reg [31:0] _RAND_65;
  reg [31:0] _RAND_66;
  reg [31:0] _RAND_67;
  reg [31:0] _RAND_68;
  reg [31:0] _RAND_69;
  reg [31:0] _RAND_70;
  reg [31:0] _RAND_71;
  reg [31:0] _RAND_72;
  reg [31:0] _RAND_73;
  reg [31:0] _RAND_74;
  reg [31:0] _RAND_75;
  reg [31:0] _RAND_76;
  reg [31:0] _RAND_77;
  reg [31:0] _RAND_78;
  reg [31:0] _RAND_79;
  reg [31:0] _RAND_80;
  reg [31:0] _RAND_81;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [8:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  monitor_1_clock; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_1_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_1_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [1:0] monitor_1_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_1_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [11:0] monitor_1_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_1_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_1_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_1_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_1_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  hartIsInResetSync_0_debug_hartReset_0_clock; // @[ShiftReg.scala 45:23]
  wire  hartIsInResetSync_0_debug_hartReset_0_reset; // @[ShiftReg.scala 45:23]
  wire  hartIsInResetSync_0_debug_hartReset_0_io_d; // @[ShiftReg.scala 45:23]
  wire  hartIsInResetSync_0_debug_hartReset_0_io_q; // @[ShiftReg.scala 45:23]
  reg  haltedBitRegs; // @[Debug.scala 778:31]
  reg  resumeReqRegs; // @[Debug.scala 779:31]
  reg  haveResetBitRegs; // @[Debug.scala 780:31]
  wire  hamaskWrSel_0 = io_innerCtrl_bits_hartsel == 10'h0; // @[Debug.scala 842:61]
  reg  hrmaskReg_0; // @[Debug.scala 854:29]
  wire  _T_1 = ~io_dmactive; // @[Debug.scala 861:11]
  wire  _T_4 = io_innerCtrl_ready & io_innerCtrl_valid; // @[Decoupled.scala 50:35]
  wire  _GEN_0 = 1'h0; // @[Debug.scala 868:34]
  reg  hrDebugIntReg_0; // @[Debug.scala 868:34]
  wire  _T_10 = ~haltedBitRegs; // @[package.scala 70:38]
  wire  _T_11 = hrDebugIntReg_0 & _T_10; // @[package.scala 65:72]
  wire  hartIsInResetSync_0 = hartIsInResetSync_0_debug_hartReset_0_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  _T_12 = hartIsInResetSync_0 | _T_11; // @[package.scala 66:75]
  wire  _T_13 = hrmaskReg_0 & _T_12; // @[package.scala 65:72]
  wire  resumereq = _T_4 & io_innerCtrl_bits_resumereq; // @[Debug.scala 890:41]
  wire  _resumeAcks_T_1 = ~hamaskWrSel_0; // @[Debug.scala 1235:41]
  wire  resumeAcks = resumereq ? ~resumeReqRegs & ~hamaskWrSel_0 : ~resumeReqRegs; // @[Debug.scala 1234:24 1235:20 1237:20]
  wire [31:0] haltedStatus_0 = {{31'd0}, haltedBitRegs}; // @[Debug.scala 1063:30]
  wire  haltedSummary = |haltedStatus_0; // @[Debug.scala 1073:48]
  wire [31:0] HALTSUM1RdData_haltsum1 = {{31'd0}, haltedSummary};
  reg [2:0] ABSTRACTCSReg_cmderr; // @[Debug.scala 1087:34]
  wire  in_bits_read = auto_dmi_in_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 72:36]
  wire [6:0] in_bits_index = auto_dmi_in_a_bits_address[8:2]; // @[Edges.scala 191:34]
  wire [4:0] out_iindex = {in_bits_index[5],in_bits_index[3],in_bits_index[2],in_bits_index[1],in_bits_index[0]}; // @[Cat.scala 31:58]
  wire [6:0] out_findex = in_bits_index & 7'h50; // @[RegisterRouter.scala 83:24]
  wire  _out_T_44 = out_findex == 7'h0; // @[RegisterRouter.scala 83:24]
  wire  _out_T_2 = out_findex == 7'h10; // @[RegisterRouter.scala 83:24]
  wire  _out_T_20 = out_findex == 7'h40; // @[RegisterRouter.scala 83:24]
  wire [31:0] _out_backSel_T = 32'h1 << out_iindex; // @[OneHot.scala 57:35]
  wire  out_backSel_6 = _out_backSel_T[6]; // @[RegisterRouter.scala 83:24]
  wire  out_woready__61 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_6 & out_findex == 7'h10
    ; // @[RegisterRouter.scala 83:24]
  wire [7:0] _out_backMask_T_11 = auto_dmi_in_a_bits_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_backMask_T_9 = auto_dmi_in_a_bits_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_backMask_T_7 = auto_dmi_in_a_bits_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_backMask_T_5 = auto_dmi_in_a_bits_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [31:0] out_backMask = {_out_backMask_T_11,_out_backMask_T_9,_out_backMask_T_7,_out_backMask_T_5}; // @[Cat.scala 31:58]
  wire  out_womask_61 = &out_backMask[10:8]; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_61 = out_woready__61 & out_womask_61; // @[RegisterRouter.scala 83:24]
  reg [1:0] ctrlStateReg; // @[Debug.scala 1616:27]
  wire  ABSTRACTCSWrEnLegal = ctrlStateReg == 2'h0; // @[Debug.scala 1626:44]
  wire  ABSTRACTCSWrEn = out_f_woready_61 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1095:51]
  wire [2:0] ABSTRACTCSWrData_cmderr = auto_dmi_in_a_bits_data[10:8]; // @[RegisterRouter.scala 83:24]
  wire [2:0] _ABSTRACTCSReg_cmderr_T = ~ABSTRACTCSWrData_cmderr; // @[Debug.scala 1115:58]
  wire [2:0] _ABSTRACTCSReg_cmderr_T_1 = ABSTRACTCSReg_cmderr & _ABSTRACTCSReg_cmderr_T; // @[Debug.scala 1115:56]
  wire [2:0] _GEN_37 = ABSTRACTCSWrEn ? _ABSTRACTCSReg_cmderr_T_1 : ABSTRACTCSReg_cmderr; // @[Debug.scala 1114:30 1115:32 1087:34]
  wire  _T_1383 = ctrlStateReg == 2'h1; // @[Debug.scala 1681:30]
  reg [7:0] COMMANDRdData_cmdtype; // @[Debug.scala 1172:25]
  wire  commandRegIsAccessRegister = COMMANDRdData_cmdtype == 8'h0; // @[Debug.scala 1641:58]
  reg [23:0] COMMANDRdData_control; // @[Debug.scala 1172:25]
  wire [31:0] _accessRegisterCommandReg_T = {COMMANDRdData_cmdtype,COMMANDRdData_control}; // @[Debug.scala 1417:62]
  wire  accessRegisterCommandReg_transfer = _accessRegisterCommandReg_T[17]; // @[Debug.scala 1417:73]
  wire  accessRegisterCommandReg_write = _accessRegisterCommandReg_T[16]; // @[Debug.scala 1417:73]
  wire [15:0] accessRegisterCommandReg_regno = _accessRegisterCommandReg_T[15:0]; // @[Debug.scala 1417:73]
  wire [2:0] accessRegisterCommandReg_size = _accessRegisterCommandReg_T[22:20]; // @[Debug.scala 1417:73]
  wire  accessRegIsLegalSize = accessRegisterCommandReg_size == 3'h2 | accessRegisterCommandReg_size == 3'h3; // @[Debug.scala 1649:72]
  wire  accessRegIsGPR = accessRegisterCommandReg_regno >= 16'h1000 & accessRegisterCommandReg_regno <= 16'h101f &
    accessRegIsLegalSize; // @[Debug.scala 1650:117]
  wire  _GEN_3614 = ~accessRegisterCommandReg_transfer | accessRegIsGPR ? 1'h0 : 1'h1; // @[Debug.scala 1660:73 1661:33]
  wire  commandRegIsUnsupported = commandRegIsAccessRegister ? _GEN_3614 : 1'h1; // @[Debug.scala 1657:39]
  wire  _GEN_3615 = (~accessRegisterCommandReg_transfer | accessRegIsGPR) & _T_10; // @[Debug.scala 1660:73 1662:33]
  wire  commandRegBadHaltResume = commandRegIsAccessRegister & _GEN_3615; // @[Debug.scala 1657:39]
  wire  _GEN_3631 = commandRegIsUnsupported ? 1'h0 : commandRegBadHaltResume; // @[Debug.scala 1688:38]
  wire  _GEN_3644 = ctrlStateReg == 2'h1 & _GEN_3631; // @[Debug.scala 1681:59]
  wire  errorHaltResume = ABSTRACTCSWrEnLegal ? 1'h0 : _GEN_3644; // @[Debug.scala 1673:47]
  wire [2:0] _GEN_38 = errorHaltResume ? 3'h4 : _GEN_37; // @[Debug.scala 1111:36 1112:30]
  wire  out_backSel_7 = _out_backSel_T[7]; // @[RegisterRouter.scala 83:24]
  wire  out_woready__86 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_7 & out_findex == 7'h10
    ; // @[RegisterRouter.scala 83:24]
  wire  out_womask_86 = &out_backMask; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_86 = out_woready__86 & out_womask_86; // @[RegisterRouter.scala 83:24]
  wire  COMMANDWrEn = out_f_woready_86 & ABSTRACTCSWrEnLegal; // @[Debug.scala 1180:40]
  wire [31:0] COMMANDWrDataVal = out_f_woready_86 ? auto_dmi_in_a_bits_data : 32'h0; // @[Debug.scala 265:{24,30}]
  wire [7:0] COMMANDWrData_cmdtype = COMMANDWrDataVal[31:24]; // @[Debug.scala 1175:65]
  wire  commandWrIsAccessRegister = COMMANDWrData_cmdtype == 8'h0; // @[Debug.scala 1640:60]
  wire  _wrAccessRegisterCommand_T_1 = ABSTRACTCSReg_cmderr == 3'h0; // @[Debug.scala 1666:103]
  wire  wrAccessRegisterCommand = COMMANDWrEn & commandWrIsAccessRegister & ABSTRACTCSReg_cmderr == 3'h0; // @[Debug.scala 1666:78]
  wire  out_backSel_4 = _out_backSel_T[4]; // @[RegisterRouter.scala 83:24]
  wire  out_woready__92 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_4 & out_findex == 7'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_womask_92 = &out_backMask[7:0]; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_92 = out_woready__92 & out_womask_92; // @[RegisterRouter.scala 83:24]
  wire  out_roready__92 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & in_bits_read & out_backSel_4 & out_findex == 7'h0; // @[RegisterRouter.scala 83:24]
  wire  out_romask_92 = |out_backMask[7:0]; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_92 = out_roready__92 & out_romask_92; // @[RegisterRouter.scala 83:24]
  wire  dmiAbstractDataAccessVec_0 = out_f_woready_92 | out_f_roready_92; // @[Debug.scala 1153:105]
  reg [11:0] ABSTRACTAUTOReg_autoexecdata; // @[Debug.scala 1131:36]
  wire  autoexecData_0 = dmiAbstractDataAccessVec_0 & ABSTRACTAUTOReg_autoexecdata[0]; // @[Debug.scala 1164:140]
  wire  out_backSel_16 = _out_backSel_T[16]; // @[RegisterRouter.scala 83:24]
  wire  out_woready__27 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_16 & out_findex == 7'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_27 = out_woready__27 & out_womask_92; // @[RegisterRouter.scala 83:24]
  wire  out_roready__27 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & in_bits_read & out_backSel_16 & out_findex == 7'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_27 = out_roready__27 & out_romask_92; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_0 = out_f_woready_27 | out_f_roready_27; // @[Debug.scala 1156:108]
  reg [15:0] ABSTRACTAUTOReg_autoexecprogbuf; // @[Debug.scala 1131:36]
  wire  autoexecProg_0 = dmiProgramBufferAccessVec_0 & ABSTRACTAUTOReg_autoexecprogbuf[0]; // @[Debug.scala 1165:144]
  wire  out_backSel_17 = _out_backSel_T[17]; // @[RegisterRouter.scala 83:24]
  wire  out_woready__19 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_17 & out_findex == 7'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_19 = out_woready__19 & out_womask_92; // @[RegisterRouter.scala 83:24]
  wire  out_roready__19 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & in_bits_read & out_backSel_17 & out_findex == 7'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_19 = out_roready__19 & out_romask_92; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_4 = out_f_woready_19 | out_f_roready_19; // @[Debug.scala 1156:108]
  wire  autoexecProg_1 = dmiProgramBufferAccessVec_4 & ABSTRACTAUTOReg_autoexecprogbuf[1]; // @[Debug.scala 1165:144]
  wire  out_backSel_18 = _out_backSel_T[18]; // @[RegisterRouter.scala 83:24]
  wire  out_woready__31 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_18 & out_findex == 7'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_31 = out_woready__31 & out_womask_92; // @[RegisterRouter.scala 83:24]
  wire  out_roready__31 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & in_bits_read & out_backSel_18 & out_findex == 7'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_31 = out_roready__31 & out_romask_92; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_8 = out_f_woready_31 | out_f_roready_31; // @[Debug.scala 1156:108]
  wire  autoexecProg_2 = dmiProgramBufferAccessVec_8 & ABSTRACTAUTOReg_autoexecprogbuf[2]; // @[Debug.scala 1165:144]
  wire  out_backSel_19 = _out_backSel_T[19]; // @[RegisterRouter.scala 83:24]
  wire  out_woready__74 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_19 & out_findex == 7'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_74 = out_woready__74 & out_womask_92; // @[RegisterRouter.scala 83:24]
  wire  out_roready__74 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & in_bits_read & out_backSel_19 & out_findex == 7'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_74 = out_roready__74 & out_romask_92; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_12 = out_f_woready_74 | out_f_roready_74; // @[Debug.scala 1156:108]
  wire  autoexecProg_3 = dmiProgramBufferAccessVec_12 & ABSTRACTAUTOReg_autoexecprogbuf[3]; // @[Debug.scala 1165:144]
  wire  out_backSel_20 = _out_backSel_T[20]; // @[RegisterRouter.scala 83:24]
  wire  out_woready__87 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_20 & out_findex == 7'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_87 = out_woready__87 & out_womask_92; // @[RegisterRouter.scala 83:24]
  wire  out_roready__87 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & in_bits_read & out_backSel_20 & out_findex == 7'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_87 = out_roready__87 & out_romask_92; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_16 = out_f_woready_87 | out_f_roready_87; // @[Debug.scala 1156:108]
  wire  autoexecProg_4 = dmiProgramBufferAccessVec_16 & ABSTRACTAUTOReg_autoexecprogbuf[4]; // @[Debug.scala 1165:144]
  wire  out_backSel_21 = _out_backSel_T[21]; // @[RegisterRouter.scala 83:24]
  wire  out_woready__7 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_21 & out_findex == 7'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_7 = out_woready__7 & out_womask_92; // @[RegisterRouter.scala 83:24]
  wire  out_roready__7 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & in_bits_read & out_backSel_21 & out_findex == 7'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_7 = out_roready__7 & out_romask_92; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_20 = out_f_woready_7 | out_f_roready_7; // @[Debug.scala 1156:108]
  wire  autoexecProg_5 = dmiProgramBufferAccessVec_20 & ABSTRACTAUTOReg_autoexecprogbuf[5]; // @[Debug.scala 1165:144]
  wire  out_backSel_22 = _out_backSel_T[22]; // @[RegisterRouter.scala 83:24]
  wire  out_woready__15 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_22 & out_findex == 7'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_15 = out_woready__15 & out_womask_92; // @[RegisterRouter.scala 83:24]
  wire  out_roready__15 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & in_bits_read & out_backSel_22 & out_findex == 7'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_15 = out_roready__15 & out_romask_92; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_24 = out_f_woready_15 | out_f_roready_15; // @[Debug.scala 1156:108]
  wire  autoexecProg_6 = dmiProgramBufferAccessVec_24 & ABSTRACTAUTOReg_autoexecprogbuf[6]; // @[Debug.scala 1165:144]
  wire  out_backSel_23 = _out_backSel_T[23]; // @[RegisterRouter.scala 83:24]
  wire  out_woready__70 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_23 & out_findex == 7'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_70 = out_woready__70 & out_womask_92; // @[RegisterRouter.scala 83:24]
  wire  out_roready__70 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & in_bits_read & out_backSel_23 & out_findex == 7'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_70 = out_roready__70 & out_romask_92; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_28 = out_f_woready_70 | out_f_roready_70; // @[Debug.scala 1156:108]
  wire  autoexecProg_7 = dmiProgramBufferAccessVec_28 & ABSTRACTAUTOReg_autoexecprogbuf[7]; // @[Debug.scala 1165:144]
  wire  out_backSel_24 = _out_backSel_T[24]; // @[RegisterRouter.scala 83:24]
  wire  out_woready__82 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_24 & out_findex == 7'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_82 = out_woready__82 & out_womask_92; // @[RegisterRouter.scala 83:24]
  wire  out_roready__82 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & in_bits_read & out_backSel_24 & out_findex == 7'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_82 = out_roready__82 & out_romask_92; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_32 = out_f_woready_82 | out_f_roready_82; // @[Debug.scala 1156:108]
  wire  autoexecProg_8 = dmiProgramBufferAccessVec_32 & ABSTRACTAUTOReg_autoexecprogbuf[8]; // @[Debug.scala 1165:144]
  wire  out_backSel_25 = _out_backSel_T[25]; // @[RegisterRouter.scala 83:24]
  wire  out_woready__23 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_25 & out_findex == 7'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_23 = out_woready__23 & out_womask_92; // @[RegisterRouter.scala 83:24]
  wire  out_roready__23 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & in_bits_read & out_backSel_25 & out_findex == 7'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_23 = out_roready__23 & out_romask_92; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_36 = out_f_woready_23 | out_f_roready_23; // @[Debug.scala 1156:108]
  wire  autoexecProg_9 = dmiProgramBufferAccessVec_36 & ABSTRACTAUTOReg_autoexecprogbuf[9]; // @[Debug.scala 1165:144]
  wire  out_backSel_26 = _out_backSel_T[26]; // @[RegisterRouter.scala 83:24]
  wire  out_woready__0 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_26 & out_findex == 7'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready = out_woready__0 & out_womask_92; // @[RegisterRouter.scala 83:24]
  wire  out_roready__0 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & in_bits_read & out_backSel_26 & out_findex == 7'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready = out_roready__0 & out_romask_92; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_40 = out_f_woready | out_f_roready; // @[Debug.scala 1156:108]
  wire  autoexecProg_10 = dmiProgramBufferAccessVec_40 & ABSTRACTAUTOReg_autoexecprogbuf[10]; // @[Debug.scala 1165:144]
  wire  out_backSel_27 = _out_backSel_T[27]; // @[RegisterRouter.scala 83:24]
  wire  out_woready__78 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_27 & out_findex == 7'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_78 = out_woready__78 & out_womask_92; // @[RegisterRouter.scala 83:24]
  wire  out_roready__78 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & in_bits_read & out_backSel_27 & out_findex == 7'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_78 = out_roready__78 & out_romask_92; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_44 = out_f_woready_78 | out_f_roready_78; // @[Debug.scala 1156:108]
  wire  autoexecProg_11 = dmiProgramBufferAccessVec_44 & ABSTRACTAUTOReg_autoexecprogbuf[11]; // @[Debug.scala 1165:144]
  wire  out_backSel_28 = _out_backSel_T[28]; // @[RegisterRouter.scala 83:24]
  wire  out_woready__66 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_28 & out_findex == 7'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_66 = out_woready__66 & out_womask_92; // @[RegisterRouter.scala 83:24]
  wire  out_roready__66 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & in_bits_read & out_backSel_28 & out_findex == 7'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_66 = out_roready__66 & out_romask_92; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_48 = out_f_woready_66 | out_f_roready_66; // @[Debug.scala 1156:108]
  wire  autoexecProg_12 = dmiProgramBufferAccessVec_48 & ABSTRACTAUTOReg_autoexecprogbuf[12]; // @[Debug.scala 1165:144]
  wire  out_backSel_29 = _out_backSel_T[29]; // @[RegisterRouter.scala 83:24]
  wire  out_woready__35 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_29 & out_findex == 7'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_35 = out_woready__35 & out_womask_92; // @[RegisterRouter.scala 83:24]
  wire  out_roready__35 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & in_bits_read & out_backSel_29 & out_findex == 7'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_35 = out_roready__35 & out_romask_92; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_52 = out_f_woready_35 | out_f_roready_35; // @[Debug.scala 1156:108]
  wire  autoexecProg_13 = dmiProgramBufferAccessVec_52 & ABSTRACTAUTOReg_autoexecprogbuf[13]; // @[Debug.scala 1165:144]
  wire  out_backSel_30 = _out_backSel_T[30]; // @[RegisterRouter.scala 83:24]
  wire  out_woready__11 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_30 & out_findex == 7'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_11 = out_woready__11 & out_womask_92; // @[RegisterRouter.scala 83:24]
  wire  out_roready__11 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & in_bits_read & out_backSel_30 & out_findex == 7'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_11 = out_roready__11 & out_romask_92; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_56 = out_f_woready_11 | out_f_roready_11; // @[Debug.scala 1156:108]
  wire  autoexecProg_14 = dmiProgramBufferAccessVec_56 & ABSTRACTAUTOReg_autoexecprogbuf[14]; // @[Debug.scala 1165:144]
  wire  out_backSel_31 = _out_backSel_T[31]; // @[RegisterRouter.scala 83:24]
  wire  out_woready__96 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_31 & out_findex == 7'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_96 = out_woready__96 & out_womask_92; // @[RegisterRouter.scala 83:24]
  wire  out_roready__96 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & in_bits_read & out_backSel_31 & out_findex == 7'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_96 = out_roready__96 & out_romask_92; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_60 = out_f_woready_96 | out_f_roready_96; // @[Debug.scala 1156:108]
  wire  autoexecProg_15 = dmiProgramBufferAccessVec_60 & ABSTRACTAUTOReg_autoexecprogbuf[15]; // @[Debug.scala 1165:144]
  wire  autoexec = autoexecData_0 | (autoexecProg_0 | autoexecProg_1 | autoexecProg_2 | autoexecProg_3 | autoexecProg_4
     | autoexecProg_5 | autoexecProg_6 | autoexecProg_7 | autoexecProg_8 | autoexecProg_9 | autoexecProg_10 |
    autoexecProg_11 | autoexecProg_12 | autoexecProg_13 | autoexecProg_14 | autoexecProg_15); // @[Debug.scala 1167:48]
  wire  regAccessRegisterCommand = autoexec & commandRegIsAccessRegister & _wrAccessRegisterCommand_T_1; // @[Debug.scala 1667:78]
  wire  commandWrIsUnsupported = COMMANDWrEn & ~commandWrIsAccessRegister; // @[Debug.scala 1643:46]
  wire  _T_1382 = autoexec & commandRegIsUnsupported; // @[Debug.scala 1678:28]
  wire  _GEN_3621 = commandWrIsUnsupported | _T_1382; // @[Debug.scala 1676:43 1677:26]
  wire  _GEN_3623 = wrAccessRegisterCommand | regAccessRegisterCommand ? 1'h0 : _GEN_3621; // @[Debug.scala 1674:66]
  wire  _GEN_3642 = ctrlStateReg == 2'h1 & commandRegIsUnsupported; // @[Debug.scala 1681:59]
  wire  errorUnsupported = ABSTRACTCSWrEnLegal ? _GEN_3623 : _GEN_3642; // @[Debug.scala 1673:47]
  wire  _T_1384 = ctrlStateReg == 2'h2; // @[Debug.scala 1702:30]
  wire  in_1_bits_read = auto_tl_in_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 72:36]
  wire [9:0] in_1_bits_index = auto_tl_in_a_bits_address[11:2]; // @[Edges.scala 191:34]
  wire [8:0] out_iindex_1 = {in_1_bits_index[8],in_1_bits_index[7],in_1_bits_index[6],in_1_bits_index[5],in_1_bits_index
    [4],in_1_bits_index[3],in_1_bits_index[2],in_1_bits_index[1],in_1_bits_index[0]}; // @[Cat.scala 31:58]
  wire [9:0] out_findex_1 = in_1_bits_index & 10'h200; // @[RegisterRouter.scala 83:24]
  wire  _out_T_1122 = out_findex_1 == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  _out_T_1642 = out_findex_1 == 10'h200; // @[RegisterRouter.scala 83:24]
  wire [511:0] _out_backSel_T_1 = 512'h1 << out_iindex_1; // @[OneHot.scala 57:35]
  wire  out_backSel_67 = _out_backSel_T_1[67]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_1_841 = auto_tl_in_a_valid & auto_tl_in_d_ready & ~in_1_bits_read & out_backSel_67 & out_findex_1
     == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [7:0] _out_backMask_T_23 = auto_tl_in_a_bits_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_backMask_T_21 = auto_tl_in_a_bits_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_backMask_T_19 = auto_tl_in_a_bits_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_backMask_T_17 = auto_tl_in_a_bits_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [31:0] out_backMask_1 = {_out_backMask_T_23,_out_backMask_T_21,_out_backMask_T_19,_out_backMask_T_17}; // @[Cat.scala 31:58]
  wire  out_womask_941 = &out_backMask_1[9:0]; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_941 = out_woready_1_841 & out_womask_941; // @[RegisterRouter.scala 83:24]
  wire  _GEN_3640 = ctrlStateReg == 2'h2 & out_f_woready_941; // @[Debug.scala 1702:51]
  wire  _GEN_3646 = ctrlStateReg == 2'h1 ? 1'h0 : _GEN_3640; // @[Debug.scala 1681:59]
  wire  errorException = ABSTRACTCSWrEnLegal ? 1'h0 : _GEN_3646; // @[Debug.scala 1673:47]
  wire  _errorBusy_T = ~ABSTRACTCSWrEnLegal; // @[Debug.scala 1632:45]
  wire  out_backSel_8 = _out_backSel_T[8]; // @[RegisterRouter.scala 83:24]
  wire  out_woready__4 = auto_dmi_in_a_valid & auto_dmi_in_d_ready & ~in_bits_read & out_backSel_8 & out_findex == 7'h10
    ; // @[RegisterRouter.scala 83:24]
  wire  out_womask_4 = &out_backMask[0]; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_4 = out_woready__4 & out_womask_4; // @[RegisterRouter.scala 83:24]
  wire  _errorBusy_T_3 = out_f_woready_4 & _errorBusy_T; // @[Debug.scala 1633:42]
  wire  _errorBusy_T_4 = out_f_woready_61 & ~ABSTRACTCSWrEnLegal | _errorBusy_T_3; // @[Debug.scala 1632:74]
  wire  out_womask_6 = &out_backMask[31:16]; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_6 = out_woready__4 & out_womask_6; // @[RegisterRouter.scala 83:24]
  wire  _errorBusy_T_6 = out_f_woready_6 & _errorBusy_T; // @[Debug.scala 1634:44]
  wire  _errorBusy_T_7 = _errorBusy_T_4 | _errorBusy_T_6; // @[Debug.scala 1633:74]
  wire  _errorBusy_T_9 = out_f_woready_86 & _errorBusy_T; // @[Debug.scala 1635:42]
  wire  _errorBusy_T_10 = _errorBusy_T_7 | _errorBusy_T_9; // @[Debug.scala 1634:74]
  wire  out_womask_93 = &out_backMask[15:8]; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_93 = out_woready__92 & out_womask_93; // @[RegisterRouter.scala 83:24]
  wire  out_romask_93 = |out_backMask[15:8]; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_93 = out_roready__92 & out_romask_93; // @[RegisterRouter.scala 83:24]
  wire  dmiAbstractDataAccessVec_1 = out_f_woready_93 | out_f_roready_93; // @[Debug.scala 1153:105]
  wire  out_womask_94 = &out_backMask[23:16]; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_94 = out_woready__92 & out_womask_94; // @[RegisterRouter.scala 83:24]
  wire  out_romask_94 = |out_backMask[23:16]; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_94 = out_roready__92 & out_romask_94; // @[RegisterRouter.scala 83:24]
  wire  dmiAbstractDataAccessVec_2 = out_f_woready_94 | out_f_roready_94; // @[Debug.scala 1153:105]
  wire  out_womask_95 = &out_backMask[31:24]; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_95 = out_woready__92 & out_womask_95; // @[RegisterRouter.scala 83:24]
  wire  out_romask_95 = |out_backMask[31:24]; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_95 = out_roready__92 & out_romask_95; // @[RegisterRouter.scala 83:24]
  wire  dmiAbstractDataAccessVec_3 = out_f_woready_95 | out_f_roready_95; // @[Debug.scala 1153:105]
  wire  dmiAbstractDataAccess = dmiAbstractDataAccessVec_0 | dmiAbstractDataAccessVec_1 | dmiAbstractDataAccessVec_2 |
    dmiAbstractDataAccessVec_3; // @[Debug.scala 1158:68]
  wire  _errorBusy_T_12 = dmiAbstractDataAccess & _errorBusy_T; // @[Debug.scala 1636:42]
  wire  _errorBusy_T_13 = _errorBusy_T_10 | _errorBusy_T_12; // @[Debug.scala 1635:74]
  wire  out_f_woready_28 = out_woready__27 & out_womask_93; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_28 = out_roready__27 & out_romask_93; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_1 = out_f_woready_28 | out_f_roready_28; // @[Debug.scala 1156:108]
  wire  out_f_woready_29 = out_woready__27 & out_womask_94; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_29 = out_roready__27 & out_romask_94; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_2 = out_f_woready_29 | out_f_roready_29; // @[Debug.scala 1156:108]
  wire  out_f_woready_30 = out_woready__27 & out_womask_95; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_30 = out_roready__27 & out_romask_95; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_3 = out_f_woready_30 | out_f_roready_30; // @[Debug.scala 1156:108]
  wire  out_f_woready_20 = out_woready__19 & out_womask_93; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_20 = out_roready__19 & out_romask_93; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_5 = out_f_woready_20 | out_f_roready_20; // @[Debug.scala 1156:108]
  wire  out_f_woready_21 = out_woready__19 & out_womask_94; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_21 = out_roready__19 & out_romask_94; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_6 = out_f_woready_21 | out_f_roready_21; // @[Debug.scala 1156:108]
  wire  out_f_woready_22 = out_woready__19 & out_womask_95; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_22 = out_roready__19 & out_romask_95; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_7 = out_f_woready_22 | out_f_roready_22; // @[Debug.scala 1156:108]
  wire  out_f_woready_32 = out_woready__31 & out_womask_93; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_32 = out_roready__31 & out_romask_93; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_9 = out_f_woready_32 | out_f_roready_32; // @[Debug.scala 1156:108]
  wire  out_f_woready_33 = out_woready__31 & out_womask_94; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_33 = out_roready__31 & out_romask_94; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_10 = out_f_woready_33 | out_f_roready_33; // @[Debug.scala 1156:108]
  wire  out_f_woready_34 = out_woready__31 & out_womask_95; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_34 = out_roready__31 & out_romask_95; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_11 = out_f_woready_34 | out_f_roready_34; // @[Debug.scala 1156:108]
  wire  out_f_woready_75 = out_woready__74 & out_womask_93; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_75 = out_roready__74 & out_romask_93; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_13 = out_f_woready_75 | out_f_roready_75; // @[Debug.scala 1156:108]
  wire  out_f_woready_76 = out_woready__74 & out_womask_94; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_76 = out_roready__74 & out_romask_94; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_14 = out_f_woready_76 | out_f_roready_76; // @[Debug.scala 1156:108]
  wire  out_f_woready_77 = out_woready__74 & out_womask_95; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_77 = out_roready__74 & out_romask_95; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_15 = out_f_woready_77 | out_f_roready_77; // @[Debug.scala 1156:108]
  wire  out_f_woready_88 = out_woready__87 & out_womask_93; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_88 = out_roready__87 & out_romask_93; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_17 = out_f_woready_88 | out_f_roready_88; // @[Debug.scala 1156:108]
  wire  out_f_woready_89 = out_woready__87 & out_womask_94; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_89 = out_roready__87 & out_romask_94; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_18 = out_f_woready_89 | out_f_roready_89; // @[Debug.scala 1156:108]
  wire  out_f_woready_90 = out_woready__87 & out_womask_95; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_90 = out_roready__87 & out_romask_95; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_19 = out_f_woready_90 | out_f_roready_90; // @[Debug.scala 1156:108]
  wire  out_f_woready_8 = out_woready__7 & out_womask_93; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_8 = out_roready__7 & out_romask_93; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_21 = out_f_woready_8 | out_f_roready_8; // @[Debug.scala 1156:108]
  wire  out_f_woready_9 = out_woready__7 & out_womask_94; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_9 = out_roready__7 & out_romask_94; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_22 = out_f_woready_9 | out_f_roready_9; // @[Debug.scala 1156:108]
  wire  out_f_woready_10 = out_woready__7 & out_womask_95; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_10 = out_roready__7 & out_romask_95; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_23 = out_f_woready_10 | out_f_roready_10; // @[Debug.scala 1156:108]
  wire  out_f_woready_16 = out_woready__15 & out_womask_93; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_16 = out_roready__15 & out_romask_93; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_25 = out_f_woready_16 | out_f_roready_16; // @[Debug.scala 1156:108]
  wire  out_f_woready_17 = out_woready__15 & out_womask_94; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_17 = out_roready__15 & out_romask_94; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_26 = out_f_woready_17 | out_f_roready_17; // @[Debug.scala 1156:108]
  wire  out_f_woready_18 = out_woready__15 & out_womask_95; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_18 = out_roready__15 & out_romask_95; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_27 = out_f_woready_18 | out_f_roready_18; // @[Debug.scala 1156:108]
  wire  out_f_woready_71 = out_woready__70 & out_womask_93; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_71 = out_roready__70 & out_romask_93; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_29 = out_f_woready_71 | out_f_roready_71; // @[Debug.scala 1156:108]
  wire  out_f_woready_72 = out_woready__70 & out_womask_94; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_72 = out_roready__70 & out_romask_94; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_30 = out_f_woready_72 | out_f_roready_72; // @[Debug.scala 1156:108]
  wire  _dmiProgramBufferAccess_T_29 = dmiProgramBufferAccessVec_0 | dmiProgramBufferAccessVec_1 |
    dmiProgramBufferAccessVec_2 | dmiProgramBufferAccessVec_3 | dmiProgramBufferAccessVec_4 |
    dmiProgramBufferAccessVec_5 | dmiProgramBufferAccessVec_6 | dmiProgramBufferAccessVec_7 |
    dmiProgramBufferAccessVec_8 | dmiProgramBufferAccessVec_9 | dmiProgramBufferAccessVec_10 |
    dmiProgramBufferAccessVec_11 | dmiProgramBufferAccessVec_12 | dmiProgramBufferAccessVec_13 |
    dmiProgramBufferAccessVec_14 | dmiProgramBufferAccessVec_15 | dmiProgramBufferAccessVec_16 |
    dmiProgramBufferAccessVec_17 | dmiProgramBufferAccessVec_18 | dmiProgramBufferAccessVec_19 |
    dmiProgramBufferAccessVec_20 | dmiProgramBufferAccessVec_21 | dmiProgramBufferAccessVec_22 |
    dmiProgramBufferAccessVec_23 | dmiProgramBufferAccessVec_24 | dmiProgramBufferAccessVec_25 |
    dmiProgramBufferAccessVec_26 | dmiProgramBufferAccessVec_27 | dmiProgramBufferAccessVec_28 |
    dmiProgramBufferAccessVec_29 | dmiProgramBufferAccessVec_30; // @[Debug.scala 1159:69]
  wire  out_f_woready_73 = out_woready__70 & out_womask_95; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_73 = out_roready__70 & out_romask_95; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_31 = out_f_woready_73 | out_f_roready_73; // @[Debug.scala 1156:108]
  wire  out_f_woready_83 = out_woready__82 & out_womask_93; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_83 = out_roready__82 & out_romask_93; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_33 = out_f_woready_83 | out_f_roready_83; // @[Debug.scala 1156:108]
  wire  out_f_woready_84 = out_woready__82 & out_womask_94; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_84 = out_roready__82 & out_romask_94; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_34 = out_f_woready_84 | out_f_roready_84; // @[Debug.scala 1156:108]
  wire  out_f_woready_85 = out_woready__82 & out_womask_95; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_85 = out_roready__82 & out_romask_95; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_35 = out_f_woready_85 | out_f_roready_85; // @[Debug.scala 1156:108]
  wire  out_f_woready_24 = out_woready__23 & out_womask_93; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_24 = out_roready__23 & out_romask_93; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_37 = out_f_woready_24 | out_f_roready_24; // @[Debug.scala 1156:108]
  wire  out_f_woready_25 = out_woready__23 & out_womask_94; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_25 = out_roready__23 & out_romask_94; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_38 = out_f_woready_25 | out_f_roready_25; // @[Debug.scala 1156:108]
  wire  out_f_woready_26 = out_woready__23 & out_womask_95; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_26 = out_roready__23 & out_romask_95; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_39 = out_f_woready_26 | out_f_roready_26; // @[Debug.scala 1156:108]
  wire  out_f_woready_1 = out_woready__0 & out_womask_93; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_1 = out_roready__0 & out_romask_93; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_41 = out_f_woready_1 | out_f_roready_1; // @[Debug.scala 1156:108]
  wire  out_f_woready_2 = out_woready__0 & out_womask_94; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_2 = out_roready__0 & out_romask_94; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_42 = out_f_woready_2 | out_f_roready_2; // @[Debug.scala 1156:108]
  wire  out_f_woready_3 = out_woready__0 & out_womask_95; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_3 = out_roready__0 & out_romask_95; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_43 = out_f_woready_3 | out_f_roready_3; // @[Debug.scala 1156:108]
  wire  out_f_woready_79 = out_woready__78 & out_womask_93; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_79 = out_roready__78 & out_romask_93; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_45 = out_f_woready_79 | out_f_roready_79; // @[Debug.scala 1156:108]
  wire  out_f_woready_80 = out_woready__78 & out_womask_94; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_80 = out_roready__78 & out_romask_94; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_46 = out_f_woready_80 | out_f_roready_80; // @[Debug.scala 1156:108]
  wire  out_f_woready_81 = out_woready__78 & out_womask_95; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_81 = out_roready__78 & out_romask_95; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_47 = out_f_woready_81 | out_f_roready_81; // @[Debug.scala 1156:108]
  wire  out_f_woready_67 = out_woready__66 & out_womask_93; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_67 = out_roready__66 & out_romask_93; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_49 = out_f_woready_67 | out_f_roready_67; // @[Debug.scala 1156:108]
  wire  out_f_woready_68 = out_woready__66 & out_womask_94; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_68 = out_roready__66 & out_romask_94; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_50 = out_f_woready_68 | out_f_roready_68; // @[Debug.scala 1156:108]
  wire  out_f_woready_69 = out_woready__66 & out_womask_95; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_69 = out_roready__66 & out_romask_95; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_51 = out_f_woready_69 | out_f_roready_69; // @[Debug.scala 1156:108]
  wire  out_f_woready_36 = out_woready__35 & out_womask_93; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_36 = out_roready__35 & out_romask_93; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_53 = out_f_woready_36 | out_f_roready_36; // @[Debug.scala 1156:108]
  wire  out_f_woready_37 = out_woready__35 & out_womask_94; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_37 = out_roready__35 & out_romask_94; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_54 = out_f_woready_37 | out_f_roready_37; // @[Debug.scala 1156:108]
  wire  out_f_woready_38 = out_woready__35 & out_womask_95; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_38 = out_roready__35 & out_romask_95; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_55 = out_f_woready_38 | out_f_roready_38; // @[Debug.scala 1156:108]
  wire  out_f_woready_12 = out_woready__11 & out_womask_93; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_12 = out_roready__11 & out_romask_93; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_57 = out_f_woready_12 | out_f_roready_12; // @[Debug.scala 1156:108]
  wire  out_f_woready_13 = out_woready__11 & out_womask_94; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_13 = out_roready__11 & out_romask_94; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_58 = out_f_woready_13 | out_f_roready_13; // @[Debug.scala 1156:108]
  wire  out_f_woready_14 = out_woready__11 & out_womask_95; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_14 = out_roready__11 & out_romask_95; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_59 = out_f_woready_14 | out_f_roready_14; // @[Debug.scala 1156:108]
  wire  _dmiProgramBufferAccess_T_59 = _dmiProgramBufferAccess_T_29 | dmiProgramBufferAccessVec_31 |
    dmiProgramBufferAccessVec_32 | dmiProgramBufferAccessVec_33 | dmiProgramBufferAccessVec_34 |
    dmiProgramBufferAccessVec_35 | dmiProgramBufferAccessVec_36 | dmiProgramBufferAccessVec_37 |
    dmiProgramBufferAccessVec_38 | dmiProgramBufferAccessVec_39 | dmiProgramBufferAccessVec_40 |
    dmiProgramBufferAccessVec_41 | dmiProgramBufferAccessVec_42 | dmiProgramBufferAccessVec_43 |
    dmiProgramBufferAccessVec_44 | dmiProgramBufferAccessVec_45 | dmiProgramBufferAccessVec_46 |
    dmiProgramBufferAccessVec_47 | dmiProgramBufferAccessVec_48 | dmiProgramBufferAccessVec_49 |
    dmiProgramBufferAccessVec_50 | dmiProgramBufferAccessVec_51 | dmiProgramBufferAccessVec_52 |
    dmiProgramBufferAccessVec_53 | dmiProgramBufferAccessVec_54 | dmiProgramBufferAccessVec_55 |
    dmiProgramBufferAccessVec_56 | dmiProgramBufferAccessVec_57 | dmiProgramBufferAccessVec_58 |
    dmiProgramBufferAccessVec_59 | dmiProgramBufferAccessVec_60; // @[Debug.scala 1159:69]
  wire  out_f_woready_97 = out_woready__96 & out_womask_93; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_97 = out_roready__96 & out_romask_93; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_61 = out_f_woready_97 | out_f_roready_97; // @[Debug.scala 1156:108]
  wire  out_f_woready_98 = out_woready__96 & out_womask_94; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_98 = out_roready__96 & out_romask_94; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_62 = out_f_woready_98 | out_f_roready_98; // @[Debug.scala 1156:108]
  wire  out_f_woready_99 = out_woready__96 & out_womask_95; // @[RegisterRouter.scala 83:24]
  wire  out_f_roready_99 = out_roready__96 & out_romask_95; // @[RegisterRouter.scala 83:24]
  wire  dmiProgramBufferAccessVec_63 = out_f_woready_99 | out_f_roready_99; // @[Debug.scala 1156:108]
  wire  dmiProgramBufferAccess = _dmiProgramBufferAccess_T_59 | dmiProgramBufferAccessVec_61 |
    dmiProgramBufferAccessVec_62 | dmiProgramBufferAccessVec_63; // @[Debug.scala 1159:69]
  wire  _errorBusy_T_15 = dmiProgramBufferAccess & _errorBusy_T; // @[Debug.scala 1637:42]
  wire  errorBusy = _errorBusy_T_13 | _errorBusy_T_15; // @[Debug.scala 1636:74]
  wire [15:0] ABSTRACTAUTOWrData_autoexecprogbuf = auto_dmi_in_a_bits_data[31:16]; // @[RegisterRouter.scala 83:24]
  wire [11:0] ABSTRACTAUTOWrData_autoexecdata = {{11'd0}, auto_dmi_in_a_bits_data[0]};
  wire [11:0] _ABSTRACTAUTOReg_autoexecdata_T = ABSTRACTAUTOWrData_autoexecdata & 12'h1; // @[Debug.scala 1148:73]
  wire [23:0] COMMANDWrData_control = COMMANDWrDataVal[23:0]; // @[Debug.scala 1175:65]
  reg [7:0] abstractDataMem_0; // @[Debug.scala 1195:36]
  reg [7:0] abstractDataMem_1; // @[Debug.scala 1195:36]
  reg [7:0] abstractDataMem_2; // @[Debug.scala 1195:36]
  reg [7:0] abstractDataMem_3; // @[Debug.scala 1195:36]
  reg [7:0] programBufferMem_0; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_1; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_2; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_3; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_4; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_5; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_6; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_7; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_8; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_9; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_10; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_11; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_12; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_13; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_14; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_15; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_16; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_17; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_18; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_19; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_20; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_21; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_22; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_23; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_24; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_25; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_26; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_27; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_28; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_29; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_30; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_31; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_32; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_33; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_34; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_35; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_36; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_37; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_38; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_39; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_40; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_41; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_42; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_43; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_44; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_45; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_46; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_47; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_48; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_49; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_50; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_51; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_52; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_53; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_54; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_55; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_56; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_57; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_58; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_59; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_60; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_61; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_62; // @[Debug.scala 1199:34]
  reg [7:0] programBufferMem_63; // @[Debug.scala 1199:34]
  wire  _resumeReqRegs_T = ~hartIsInResetSync_0; // @[Debug.scala 1212:42]
  wire  _resumeReqRegs_T_1 = resumeReqRegs & ~hartIsInResetSync_0; // @[Debug.scala 1212:40]
  wire [1:0] _GEN_3655 = {{1'd0}, haltedBitRegs}; // @[Debug.scala 1218:43]
  wire [1:0] _haltedBitRegs_T = _GEN_3655 | 2'h1; // @[Debug.scala 1218:43]
  wire [1:0] _GEN_3656 = {{1'd0}, _resumeReqRegs_T}; // @[Debug.scala 1218:64]
  wire [1:0] _haltedBitRegs_T_2 = _haltedBitRegs_T & _GEN_3656; // @[Debug.scala 1218:64]
  wire [1:0] _haltedBitRegs_T_4 = _GEN_3655 & 2'h2; // @[Debug.scala 1220:43]
  wire [1:0] _haltedBitRegs_T_6 = _haltedBitRegs_T_4 & _GEN_3656; // @[Debug.scala 1220:69]
  wire  _haltedBitRegs_T_8 = haltedBitRegs & _resumeReqRegs_T; // @[Debug.scala 1222:42]
  wire  out_backSel_66 = _out_backSel_T_1[66]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_1_708 = auto_tl_in_a_valid & auto_tl_in_d_ready & ~in_1_bits_read & out_backSel_66 & out_findex_1
     == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_808 = out_woready_1_708 & out_womask_941; // @[RegisterRouter.scala 83:24]
  wire [1:0] _GEN_61 = out_f_woready_808 ? _haltedBitRegs_T_6 : {{1'd0}, _haltedBitRegs_T_8}; // @[Debug.scala 1219:39 1220:25 1222:25]
  wire  out_backSel_64 = _out_backSel_T_1[64]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_1_547 = auto_tl_in_a_valid & auto_tl_in_d_ready & ~in_1_bits_read & out_backSel_64 & out_findex_1
     == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_647 = out_woready_1_547 & out_womask_941; // @[RegisterRouter.scala 83:24]
  wire [1:0] _GEN_62 = out_f_woready_647 ? _haltedBitRegs_T_2 : _GEN_61; // @[Debug.scala 1217:31 1218:25]
  wire [1:0] _GEN_3659 = {{1'd0}, resumeReqRegs}; // @[Debug.scala 1226:43]
  wire [1:0] _resumeReqRegs_T_3 = _GEN_3659 & 2'h2; // @[Debug.scala 1226:43]
  wire [1:0] _resumeReqRegs_T_5 = _resumeReqRegs_T_3 & _GEN_3656; // @[Debug.scala 1226:69]
  wire [1:0] _GEN_63 = out_f_woready_808 ? _resumeReqRegs_T_5 : {{1'd0}, _resumeReqRegs_T_1}; // @[Debug.scala 1212:23 1225:33 1226:25]
  wire  _resumeReqRegs_T_8 = (resumeReqRegs | hamaskWrSel_0) & _resumeReqRegs_T; // @[Debug.scala 1229:65]
  wire [1:0] _GEN_64 = resumereq ? {{1'd0}, _resumeReqRegs_T_8} : _GEN_63; // @[Debug.scala 1228:26 1229:25]
  wire [1:0] _GEN_65 = _T_1 ? 2'h0 : _GEN_62; // @[Debug.scala 1207:45 1208:23]
  wire [1:0] _GEN_66 = _T_1 ? 2'h0 : _GEN_64; // @[Debug.scala 1207:45 1209:23]
  wire [31:0] out_prepend_2 = {programBufferMem_43,programBufferMem_42,programBufferMem_41,programBufferMem_40}; // @[Cat.scala 31:58]
  wire [1:0] out_prepend_3 = {1'h0,ABSTRACTAUTOReg_autoexecdata[0]}; // @[Cat.scala 31:58]
  wire [15:0] _out_T_108 = {{14'd0}, out_prepend_3}; // @[RegisterRouter.scala 83:24]
  wire [31:0] out_prepend_4 = {ABSTRACTAUTOReg_autoexecprogbuf,_out_T_108}; // @[Cat.scala 31:58]
  wire [31:0] out_prepend_7 = {programBufferMem_23,programBufferMem_22,programBufferMem_21,programBufferMem_20}; // @[Cat.scala 31:58]
  wire [31:0] out_prepend_10 = {programBufferMem_59,programBufferMem_58,programBufferMem_57,programBufferMem_56}; // @[Cat.scala 31:58]
  wire [31:0] out_prepend_13 = {programBufferMem_27,programBufferMem_26,programBufferMem_25,programBufferMem_24}; // @[Cat.scala 31:58]
  wire [31:0] out_prepend_16 = {programBufferMem_7,programBufferMem_6,programBufferMem_5,programBufferMem_4}; // @[Cat.scala 31:58]
  wire [31:0] out_prepend_19 = {programBufferMem_39,programBufferMem_38,programBufferMem_37,programBufferMem_36}; // @[Cat.scala 31:58]
  wire [31:0] out_prepend_22 = {programBufferMem_3,programBufferMem_2,programBufferMem_1,programBufferMem_0}; // @[Cat.scala 31:58]
  wire [31:0] out_prepend_25 = {programBufferMem_11,programBufferMem_10,programBufferMem_9,programBufferMem_8}; // @[Cat.scala 31:58]
  wire [31:0] out_prepend_28 = {programBufferMem_55,programBufferMem_54,programBufferMem_53,programBufferMem_52}; // @[Cat.scala 31:58]
  wire [16:0] out_prepend_41 = {resumeAcks,1'h0,1'h0,1'h0,1'h0,_T_10,_T_10,haltedBitRegs,haltedBitRegs,8'ha2}; // @[Cat.scala 31:58]
  wire [20:0] out_prepend_45 = {1'h0,haveResetBitRegs,haveResetBitRegs,resumeAcks,out_prepend_41}; // @[Cat.scala 31:58]
  wire [21:0] _out_T_642 = {{1'd0}, out_prepend_45}; // @[RegisterRouter.scala 83:24]
  wire [22:0] out_prepend_46 = {1'h0,_out_T_642}; // @[Cat.scala 31:58]
  wire  abstractCommandBusy = ctrlStateReg != 2'h0; // @[Debug.scala 1624:42]
  wire [13:0] out_prepend_51 = {1'h0,abstractCommandBusy,1'h0,ABSTRACTCSReg_cmderr,8'h1}; // @[Cat.scala 31:58]
  wire [23:0] _out_T_707 = {{10'd0}, out_prepend_51}; // @[RegisterRouter.scala 83:24]
  wire [28:0] out_prepend_52 = {5'h10,_out_T_707}; // @[Cat.scala 31:58]
  wire [31:0] out_prepend_55 = {programBufferMem_51,programBufferMem_50,programBufferMem_49,programBufferMem_48}; // @[Cat.scala 31:58]
  wire [31:0] out_prepend_58 = {programBufferMem_31,programBufferMem_30,programBufferMem_29,programBufferMem_28}; // @[Cat.scala 31:58]
  wire [31:0] out_prepend_61 = {programBufferMem_15,programBufferMem_14,programBufferMem_13,programBufferMem_12}; // @[Cat.scala 31:58]
  wire [31:0] out_prepend_64 = {programBufferMem_47,programBufferMem_46,programBufferMem_45,programBufferMem_44}; // @[Cat.scala 31:58]
  wire [31:0] out_prepend_67 = {programBufferMem_35,programBufferMem_34,programBufferMem_33,programBufferMem_32}; // @[Cat.scala 31:58]
  wire [31:0] out_prepend_70 = {programBufferMem_19,programBufferMem_18,programBufferMem_17,programBufferMem_16}; // @[Cat.scala 31:58]
  wire [31:0] out_prepend_73 = {abstractDataMem_3,abstractDataMem_2,abstractDataMem_1,abstractDataMem_0}; // @[Cat.scala 31:58]
  wire [31:0] out_prepend_76 = {programBufferMem_63,programBufferMem_62,programBufferMem_61,programBufferMem_60}; // @[Cat.scala 31:58]
  wire  _GEN_266 = 5'h1 == out_iindex ? _out_T_2 : _out_T_20; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_268 = 5'h3 == out_iindex ? _out_T_2 : 5'h2 == out_iindex | _GEN_266; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_269 = 5'h4 == out_iindex ? _out_T_44 : _GEN_268; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_271 = 5'h6 == out_iindex ? _out_T_2 : 5'h5 == out_iindex | _GEN_269; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_272 = 5'h7 == out_iindex ? _out_T_2 : _GEN_271; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_273 = 5'h8 == out_iindex ? _out_T_2 : _GEN_272; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_281 = 5'h10 == out_iindex ? _out_T_44 : 5'hf == out_iindex | (5'he == out_iindex | (5'hd == out_iindex | (5'hc
     == out_iindex | (5'hb == out_iindex | (5'ha == out_iindex | (5'h9 == out_iindex | _GEN_273)))))); // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_282 = 5'h11 == out_iindex ? _out_T_44 : _GEN_281; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_283 = 5'h12 == out_iindex ? _out_T_44 : _GEN_282; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_284 = 5'h13 == out_iindex ? _out_T_44 : _GEN_283; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_285 = 5'h14 == out_iindex ? _out_T_44 : _GEN_284; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_286 = 5'h15 == out_iindex ? _out_T_44 : _GEN_285; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_287 = 5'h16 == out_iindex ? _out_T_44 : _GEN_286; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_288 = 5'h17 == out_iindex ? _out_T_44 : _GEN_287; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_289 = 5'h18 == out_iindex ? _out_T_44 : _GEN_288; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_290 = 5'h19 == out_iindex ? _out_T_44 : _GEN_289; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_291 = 5'h1a == out_iindex ? _out_T_44 : _GEN_290; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_292 = 5'h1b == out_iindex ? _out_T_44 : _GEN_291; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_293 = 5'h1c == out_iindex ? _out_T_44 : _GEN_292; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_294 = 5'h1d == out_iindex ? _out_T_44 : _GEN_293; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_295 = 5'h1e == out_iindex ? _out_T_44 : _GEN_294; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_296 = 5'h1f == out_iindex ? _out_T_44 : _GEN_295; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_1 = {{9'd0}, out_prepend_46}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_298 = 5'h1 == out_iindex ? _out_out_bits_data_WIRE_1_1 : haltedStatus_0; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_299 = 5'h2 == out_iindex ? 32'h0 : _GEN_298; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_300 = 5'h3 == out_iindex ? HALTSUM1RdData_haltsum1 : _GEN_299; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_301 = 5'h4 == out_iindex ? out_prepend_73 : _GEN_300; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_302 = 5'h5 == out_iindex ? 32'h0 : _GEN_301; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_6 = {{3'd0}, out_prepend_52}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_303 = 5'h6 == out_iindex ? _out_out_bits_data_WIRE_1_6 : _GEN_302; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_304 = 5'h7 == out_iindex ? _accessRegisterCommandReg_T : _GEN_303; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_305 = 5'h8 == out_iindex ? out_prepend_4 : _GEN_304; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_306 = 5'h9 == out_iindex ? 32'h0 : _GEN_305; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_307 = 5'ha == out_iindex ? 32'h0 : _GEN_306; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_308 = 5'hb == out_iindex ? 32'h0 : _GEN_307; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_309 = 5'hc == out_iindex ? 32'h0 : _GEN_308; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_310 = 5'hd == out_iindex ? 32'h0 : _GEN_309; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_311 = 5'he == out_iindex ? 32'h0 : _GEN_310; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_312 = 5'hf == out_iindex ? 32'h0 : _GEN_311; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_313 = 5'h10 == out_iindex ? out_prepend_22 : _GEN_312; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_314 = 5'h11 == out_iindex ? out_prepend_16 : _GEN_313; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_315 = 5'h12 == out_iindex ? out_prepend_25 : _GEN_314; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_316 = 5'h13 == out_iindex ? out_prepend_61 : _GEN_315; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_317 = 5'h14 == out_iindex ? out_prepend_70 : _GEN_316; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_318 = 5'h15 == out_iindex ? out_prepend_7 : _GEN_317; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_319 = 5'h16 == out_iindex ? out_prepend_13 : _GEN_318; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_320 = 5'h17 == out_iindex ? out_prepend_58 : _GEN_319; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_321 = 5'h18 == out_iindex ? out_prepend_67 : _GEN_320; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_322 = 5'h19 == out_iindex ? out_prepend_19 : _GEN_321; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_323 = 5'h1a == out_iindex ? out_prepend_2 : _GEN_322; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_324 = 5'h1b == out_iindex ? out_prepend_64 : _GEN_323; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_325 = 5'h1c == out_iindex ? out_prepend_55 : _GEN_324; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_326 = 5'h1d == out_iindex ? out_prepend_28 : _GEN_325; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_327 = 5'h1e == out_iindex ? out_prepend_10 : _GEN_326; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_328 = 5'h1f == out_iindex ? out_prepend_76 : _GEN_327; // @[MuxLiteral.scala 48:{10,10}]
  reg  goReg; // @[Debug.scala 1379:27]
  wire [9:0] hartGoingId = auto_tl_in_a_bits_data[9:0]; // @[RegisterRouter.scala 83:24]
  wire  _T_342 = ~(hartGoingId == 10'h0); // @[Debug.scala 1391:15]
  wire  out_backSel_65 = _out_backSel_T_1[65]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_1_370 = auto_tl_in_a_valid & auto_tl_in_d_ready & ~in_1_bits_read & out_backSel_65 & out_findex_1
     == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_470 = out_woready_1_370 & out_womask_941; // @[RegisterRouter.scala 83:24]
  wire  _GEN_397 = out_f_woready_470 ? 1'h0 : goReg; // @[Debug.scala 1390:33 1392:15 1379:27]
  wire  _GEN_3628 = commandRegBadHaltResume ? 1'h0 : 1'h1; // @[Debug.scala 1691:43]
  wire  _GEN_3632 = commandRegIsUnsupported ? 1'h0 : _GEN_3628; // @[Debug.scala 1688:38]
  wire  _GEN_3645 = ctrlStateReg == 2'h1 & _GEN_3632; // @[Debug.scala 1681:59]
  wire  goAbstract = ABSTRACTCSWrEnLegal ? 1'h0 : _GEN_3645; // @[Debug.scala 1673:47]
  wire  _GEN_398 = goAbstract | _GEN_397; // @[Debug.scala 1388:25 1389:15]
  wire  accessRegisterCommandReg_postexec = _accessRegisterCommandReg_T[18]; // @[Debug.scala 1417:73]
  reg [31:0] abstractGeneratedMem_0; // @[Debug.scala 1470:35]
  reg [31:0] abstractGeneratedMem_1; // @[Debug.scala 1470:35]
  wire [15:0] _abstractGeneratedMem_0_inst_rd_T = accessRegisterCommandReg_regno & 16'h1f; // @[Debug.scala 1477:54]
  wire [4:0] abstractGeneratedMem_0_inst_rd = _abstractGeneratedMem_0_inst_rd_T[4:0]; // @[Debug.scala 1473:22 1477:19]
  wire [31:0] _abstractGeneratedMem_0_T = {17'h7000,accessRegisterCommandReg_size,abstractGeneratedMem_0_inst_rd,7'h3}; // @[Debug.scala 1481:12]
  wire [31:0] _abstractGeneratedMem_0_T_1 = {7'h1c,abstractGeneratedMem_0_inst_rd,5'h0,accessRegisterCommandReg_size,5'h0
    ,7'h23}; // @[Debug.scala 1494:12]
  wire  out_wimask_100 = &out_backMask_1[7:0]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_101 = &out_backMask_1[15:8]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_102 = &out_backMask_1[23:16]; // @[RegisterRouter.scala 83:24]
  wire [23:0] out_prepend_78 = {6'h0,resumeReqRegs,goReg,6'h0,resumeReqRegs,goReg,6'h0,resumeReqRegs,goReg}; // @[Cat.scala 31:58]
  wire  out_wimask_103 = &out_backMask_1[31:24]; // @[RegisterRouter.scala 83:24]
  wire [31:0] out_prepend_79 = {6'h0,resumeReqRegs,goReg,out_prepend_78}; // @[Cat.scala 31:58]
  wire  out_frontSel_217 = _out_backSel_T_1[217]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_1_40 = auto_tl_in_a_valid & auto_tl_in_d_ready & ~in_1_bits_read & out_frontSel_217 & out_findex_1
     == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_140 = out_wivalid_1_40 & out_wimask_100; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_141 = out_wivalid_1_40 & out_wimask_101; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_142 = out_wivalid_1_40 & out_wimask_102; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_143 = out_wivalid_1_40 & out_wimask_103; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_216 = _out_backSel_T_1[216]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_1_176 = auto_tl_in_a_valid & auto_tl_in_d_ready & ~in_1_bits_read & out_frontSel_216 & out_findex_1
     == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_276 = out_wivalid_1_176 & out_wimask_100; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_277 = out_wivalid_1_176 & out_wimask_101; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_278 = out_wivalid_1_176 & out_wimask_102; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_279 = out_wivalid_1_176 & out_wimask_103; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_211 = _out_backSel_T_1[211]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_1_200 = auto_tl_in_a_valid & auto_tl_in_d_ready & ~in_1_bits_read & out_frontSel_211 & out_findex_1
     == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_300 = out_wivalid_1_200 & out_wimask_100; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_301 = out_wivalid_1_200 & out_wimask_101; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_302 = out_wivalid_1_200 & out_wimask_102; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_303 = out_wivalid_1_200 & out_wimask_103; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_221 = _out_backSel_T_1[221]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_1_232 = auto_tl_in_a_valid & auto_tl_in_d_ready & ~in_1_bits_read & out_frontSel_221 & out_findex_1
     == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_332 = out_wivalid_1_232 & out_wimask_100; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_333 = out_wivalid_1_232 & out_wimask_101; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_334 = out_wivalid_1_232 & out_wimask_102; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_335 = out_wivalid_1_232 & out_wimask_103; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_220 = _out_backSel_T_1[220]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_1_309 = auto_tl_in_a_valid & auto_tl_in_d_ready & ~in_1_bits_read & out_frontSel_220 & out_findex_1
     == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_409 = out_wivalid_1_309 & out_wimask_100; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_410 = out_wivalid_1_309 & out_wimask_101; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_411 = out_wivalid_1_309 & out_wimask_102; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_412 = out_wivalid_1_309 & out_wimask_103; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_224 = _out_backSel_T_1[224]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_1_403 = auto_tl_in_a_valid & auto_tl_in_d_ready & ~in_1_bits_read & out_frontSel_224 & out_findex_1
     == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_503 = out_wivalid_1_403 & out_wimask_100; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_504 = out_wivalid_1_403 & out_wimask_101; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_505 = out_wivalid_1_403 & out_wimask_102; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_506 = out_wivalid_1_403 & out_wimask_103; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_212 = _out_backSel_T_1[212]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_1_467 = auto_tl_in_a_valid & auto_tl_in_d_ready & ~in_1_bits_read & out_frontSel_212 & out_findex_1
     == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_567 = out_wivalid_1_467 & out_wimask_100; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_568 = out_wivalid_1_467 & out_wimask_101; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_569 = out_wivalid_1_467 & out_wimask_102; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_570 = out_wivalid_1_467 & out_wimask_103; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_219 = _out_backSel_T_1[219]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_1_624 = auto_tl_in_a_valid & auto_tl_in_d_ready & ~in_1_bits_read & out_frontSel_219 & out_findex_1
     == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_724 = out_wivalid_1_624 & out_wimask_100; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_725 = out_wivalid_1_624 & out_wimask_101; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_726 = out_wivalid_1_624 & out_wimask_102; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_727 = out_wivalid_1_624 & out_wimask_103; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_208 = _out_backSel_T_1[208]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_1_668 = auto_tl_in_a_valid & auto_tl_in_d_ready & ~in_1_bits_read & out_frontSel_208 & out_findex_1
     == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_768 = out_wivalid_1_668 & out_wimask_100; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_769 = out_wivalid_1_668 & out_wimask_101; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_770 = out_wivalid_1_668 & out_wimask_102; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_771 = out_wivalid_1_668 & out_wimask_103; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_213 = _out_backSel_T_1[213]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_1_696 = auto_tl_in_a_valid & auto_tl_in_d_ready & ~in_1_bits_read & out_frontSel_213 & out_findex_1
     == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_796 = out_wivalid_1_696 & out_wimask_100; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_797 = out_wivalid_1_696 & out_wimask_101; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_798 = out_wivalid_1_696 & out_wimask_102; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_799 = out_wivalid_1_696 & out_wimask_103; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_223 = _out_backSel_T_1[223]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_1_733 = auto_tl_in_a_valid & auto_tl_in_d_ready & ~in_1_bits_read & out_frontSel_223 & out_findex_1
     == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_833 = out_wivalid_1_733 & out_wimask_100; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_834 = out_wivalid_1_733 & out_wimask_101; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_835 = out_wivalid_1_733 & out_wimask_102; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_836 = out_wivalid_1_733 & out_wimask_103; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_209 = _out_backSel_T_1[209]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_1_785 = auto_tl_in_a_valid & auto_tl_in_d_ready & ~in_1_bits_read & out_frontSel_209 & out_findex_1
     == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_885 = out_wivalid_1_785 & out_wimask_100; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_886 = out_wivalid_1_785 & out_wimask_101; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_887 = out_wivalid_1_785 & out_wimask_102; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_888 = out_wivalid_1_785 & out_wimask_103; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_218 = _out_backSel_T_1[218]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_1_918 = auto_tl_in_a_valid & auto_tl_in_d_ready & ~in_1_bits_read & out_frontSel_218 & out_findex_1
     == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_1018 = out_wivalid_1_918 & out_wimask_100; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_1019 = out_wivalid_1_918 & out_wimask_101; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_1020 = out_wivalid_1_918 & out_wimask_102; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_1021 = out_wivalid_1_918 & out_wimask_103; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_214 = _out_backSel_T_1[214]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_1_991 = auto_tl_in_a_valid & auto_tl_in_d_ready & ~in_1_bits_read & out_frontSel_214 & out_findex_1
     == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_1091 = out_wivalid_1_991 & out_wimask_100; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_1092 = out_wivalid_1_991 & out_wimask_101; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_1093 = out_wivalid_1_991 & out_wimask_102; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_1094 = out_wivalid_1_991 & out_wimask_103; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_210 = _out_backSel_T_1[210]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_1_1043 = auto_tl_in_a_valid & auto_tl_in_d_ready & ~in_1_bits_read & out_frontSel_210 & out_findex_1
     == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_1143 = out_wivalid_1_1043 & out_wimask_100; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_1144 = out_wivalid_1_1043 & out_wimask_101; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_1145 = out_wivalid_1_1043 & out_wimask_102; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_1146 = out_wivalid_1_1043 & out_wimask_103; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_215 = _out_backSel_T_1[215]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_1_1159 = auto_tl_in_a_valid & auto_tl_in_d_ready & ~in_1_bits_read & out_frontSel_215 & out_findex_1
     == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_1259 = out_wivalid_1_1159 & out_wimask_100; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_1260 = out_wivalid_1_1159 & out_wimask_101; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_1261 = out_wivalid_1_1159 & out_wimask_102; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_1262 = out_wivalid_1_1159 & out_wimask_103; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_222 = _out_backSel_T_1[222]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_1_1167 = auto_tl_in_a_valid & auto_tl_in_d_ready & ~in_1_bits_read & out_frontSel_222 & out_findex_1
     == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_1267 = out_wivalid_1_1167 & out_wimask_100; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_1268 = out_wivalid_1_1167 & out_wimask_101; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_1269 = out_wivalid_1_1167 & out_wimask_102; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_1270 = out_wivalid_1_1167 & out_wimask_103; // @[RegisterRouter.scala 83:24]
  wire  _GEN_2523 = 9'h1 == out_iindex_1 ? _out_T_1642 : _out_T_1642; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2524 = 9'h2 == out_iindex_1 ? _out_T_1642 : _GEN_2523; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2525 = 9'h3 == out_iindex_1 ? _out_T_1642 : _GEN_2524; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2526 = 9'h4 == out_iindex_1 ? _out_T_1642 : _GEN_2525; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2527 = 9'h5 == out_iindex_1 ? _out_T_1642 : _GEN_2526; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2528 = 9'h6 == out_iindex_1 ? _out_T_1642 : _GEN_2527; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2529 = 9'h7 == out_iindex_1 ? _out_T_1642 : _GEN_2528; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2530 = 9'h8 == out_iindex_1 ? _out_T_1642 : _GEN_2529; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2531 = 9'h9 == out_iindex_1 ? _out_T_1642 : _GEN_2530; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2532 = 9'ha == out_iindex_1 ? _out_T_1642 : _GEN_2531; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2533 = 9'hb == out_iindex_1 ? _out_T_1642 : _GEN_2532; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2534 = 9'hc == out_iindex_1 ? _out_T_1642 : _GEN_2533; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2535 = 9'hd == out_iindex_1 ? _out_T_1642 : _GEN_2534; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2536 = 9'he == out_iindex_1 ? _out_T_1642 : _GEN_2535; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2537 = 9'hf == out_iindex_1 ? _out_T_1642 : _GEN_2536; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2538 = 9'h10 == out_iindex_1 ? _out_T_1642 : _GEN_2537; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2539 = 9'h11 == out_iindex_1 ? _out_T_1642 : _GEN_2538; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2540 = 9'h12 == out_iindex_1 ? _out_T_1642 : _GEN_2539; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2541 = 9'h13 == out_iindex_1 ? _out_T_1642 : _GEN_2540; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2542 = 9'h14 == out_iindex_1 ? _out_T_1642 : _GEN_2541; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2557 = 9'h23 == out_iindex_1 | (9'h22 == out_iindex_1 | (9'h21 == out_iindex_1 | (9'h20 == out_iindex_1 | (9'h1f
     == out_iindex_1 | (9'h1e == out_iindex_1 | (9'h1d == out_iindex_1 | (9'h1c == out_iindex_1 | (9'h1b == out_iindex_1
     | (9'h1a == out_iindex_1 | (9'h19 == out_iindex_1 | (9'h18 == out_iindex_1 | (9'h17 == out_iindex_1 | (9'h16 ==
    out_iindex_1 | (9'h15 == out_iindex_1 | _GEN_2542)))))))))))))); // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2572 = 9'h32 == out_iindex_1 | (9'h31 == out_iindex_1 | (9'h30 == out_iindex_1 | (9'h2f == out_iindex_1 | (9'h2e
     == out_iindex_1 | (9'h2d == out_iindex_1 | (9'h2c == out_iindex_1 | (9'h2b == out_iindex_1 | (9'h2a == out_iindex_1
     | (9'h29 == out_iindex_1 | (9'h28 == out_iindex_1 | (9'h27 == out_iindex_1 | (9'h26 == out_iindex_1 | (9'h25 ==
    out_iindex_1 | (9'h24 == out_iindex_1 | _GEN_2557)))))))))))))); // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2586 = 9'h40 == out_iindex_1 ? _out_T_1122 : 9'h3f == out_iindex_1 | (9'h3e == out_iindex_1 | (9'h3d ==
    out_iindex_1 | (9'h3c == out_iindex_1 | (9'h3b == out_iindex_1 | (9'h3a == out_iindex_1 | (9'h39 == out_iindex_1 | (9'h38
     == out_iindex_1 | (9'h37 == out_iindex_1 | (9'h36 == out_iindex_1 | (9'h35 == out_iindex_1 | (9'h34 == out_iindex_1
     | (9'h33 == out_iindex_1 | _GEN_2572)))))))))))); // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2587 = 9'h41 == out_iindex_1 ? _out_T_1122 : _GEN_2586; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2588 = 9'h42 == out_iindex_1 ? _out_T_1122 : _GEN_2587; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2589 = 9'h43 == out_iindex_1 ? _out_T_1122 : _GEN_2588; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2604 = 9'h52 == out_iindex_1 | (9'h51 == out_iindex_1 | (9'h50 == out_iindex_1 | (9'h4f == out_iindex_1 | (9'h4e
     == out_iindex_1 | (9'h4d == out_iindex_1 | (9'h4c == out_iindex_1 | (9'h4b == out_iindex_1 | (9'h4a == out_iindex_1
     | (9'h49 == out_iindex_1 | (9'h48 == out_iindex_1 | (9'h47 == out_iindex_1 | (9'h46 == out_iindex_1 | (9'h45 ==
    out_iindex_1 | (9'h44 == out_iindex_1 | _GEN_2589)))))))))))))); // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2619 = 9'h61 == out_iindex_1 | (9'h60 == out_iindex_1 | (9'h5f == out_iindex_1 | (9'h5e == out_iindex_1 | (9'h5d
     == out_iindex_1 | (9'h5c == out_iindex_1 | (9'h5b == out_iindex_1 | (9'h5a == out_iindex_1 | (9'h59 == out_iindex_1
     | (9'h58 == out_iindex_1 | (9'h57 == out_iindex_1 | (9'h56 == out_iindex_1 | (9'h55 == out_iindex_1 | (9'h54 ==
    out_iindex_1 | (9'h53 == out_iindex_1 | _GEN_2604)))))))))))))); // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2634 = 9'h70 == out_iindex_1 | (9'h6f == out_iindex_1 | (9'h6e == out_iindex_1 | (9'h6d == out_iindex_1 | (9'h6c
     == out_iindex_1 | (9'h6b == out_iindex_1 | (9'h6a == out_iindex_1 | (9'h69 == out_iindex_1 | (9'h68 == out_iindex_1
     | (9'h67 == out_iindex_1 | (9'h66 == out_iindex_1 | (9'h65 == out_iindex_1 | (9'h64 == out_iindex_1 | (9'h63 ==
    out_iindex_1 | (9'h62 == out_iindex_1 | _GEN_2619)))))))))))))); // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2649 = 9'h7f == out_iindex_1 | (9'h7e == out_iindex_1 | (9'h7d == out_iindex_1 | (9'h7c == out_iindex_1 | (9'h7b
     == out_iindex_1 | (9'h7a == out_iindex_1 | (9'h79 == out_iindex_1 | (9'h78 == out_iindex_1 | (9'h77 == out_iindex_1
     | (9'h76 == out_iindex_1 | (9'h75 == out_iindex_1 | (9'h74 == out_iindex_1 | (9'h73 == out_iindex_1 | (9'h72 ==
    out_iindex_1 | (9'h71 == out_iindex_1 | _GEN_2634)))))))))))))); // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2664 = 9'h8e == out_iindex_1 | (9'h8d == out_iindex_1 | (9'h8c == out_iindex_1 | (9'h8b == out_iindex_1 | (9'h8a
     == out_iindex_1 | (9'h89 == out_iindex_1 | (9'h88 == out_iindex_1 | (9'h87 == out_iindex_1 | (9'h86 == out_iindex_1
     | (9'h85 == out_iindex_1 | (9'h84 == out_iindex_1 | (9'h83 == out_iindex_1 | (9'h82 == out_iindex_1 | (9'h81 ==
    out_iindex_1 | (9'h80 == out_iindex_1 | _GEN_2649)))))))))))))); // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2679 = 9'h9d == out_iindex_1 | (9'h9c == out_iindex_1 | (9'h9b == out_iindex_1 | (9'h9a == out_iindex_1 | (9'h99
     == out_iindex_1 | (9'h98 == out_iindex_1 | (9'h97 == out_iindex_1 | (9'h96 == out_iindex_1 | (9'h95 == out_iindex_1
     | (9'h94 == out_iindex_1 | (9'h93 == out_iindex_1 | (9'h92 == out_iindex_1 | (9'h91 == out_iindex_1 | (9'h90 ==
    out_iindex_1 | (9'h8f == out_iindex_1 | _GEN_2664)))))))))))))); // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2694 = 9'hac == out_iindex_1 | (9'hab == out_iindex_1 | (9'haa == out_iindex_1 | (9'ha9 == out_iindex_1 | (9'ha8
     == out_iindex_1 | (9'ha7 == out_iindex_1 | (9'ha6 == out_iindex_1 | (9'ha5 == out_iindex_1 | (9'ha4 == out_iindex_1
     | (9'ha3 == out_iindex_1 | (9'ha2 == out_iindex_1 | (9'ha1 == out_iindex_1 | (9'ha0 == out_iindex_1 | (9'h9f ==
    out_iindex_1 | (9'h9e == out_iindex_1 | _GEN_2679)))))))))))))); // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2709 = 9'hbb == out_iindex_1 | (9'hba == out_iindex_1 | (9'hb9 == out_iindex_1 | (9'hb8 == out_iindex_1 | (9'hb7
     == out_iindex_1 | (9'hb6 == out_iindex_1 | (9'hb5 == out_iindex_1 | (9'hb4 == out_iindex_1 | (9'hb3 == out_iindex_1
     | (9'hb2 == out_iindex_1 | (9'hb1 == out_iindex_1 | (9'hb0 == out_iindex_1 | (9'haf == out_iindex_1 | (9'hae ==
    out_iindex_1 | (9'had == out_iindex_1 | _GEN_2694)))))))))))))); // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2714 = 9'hc0 == out_iindex_1 ? _out_T_1122 : 9'hbf == out_iindex_1 | (9'hbe == out_iindex_1 | (9'hbd ==
    out_iindex_1 | (9'hbc == out_iindex_1 | _GEN_2709))); // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2728 = 9'hce == out_iindex_1 ? _out_T_1122 : 9'hcd == out_iindex_1 | (9'hcc == out_iindex_1 | (9'hcb ==
    out_iindex_1 | (9'hca == out_iindex_1 | (9'hc9 == out_iindex_1 | (9'hc8 == out_iindex_1 | (9'hc7 == out_iindex_1 | (9'hc6
     == out_iindex_1 | (9'hc5 == out_iindex_1 | (9'hc4 == out_iindex_1 | (9'hc3 == out_iindex_1 | (9'hc2 == out_iindex_1
     | (9'hc1 == out_iindex_1 | _GEN_2714)))))))))))); // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2729 = 9'hcf == out_iindex_1 ? _out_T_1122 : _GEN_2728; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2730 = 9'hd0 == out_iindex_1 ? _out_T_1122 : _GEN_2729; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2731 = 9'hd1 == out_iindex_1 ? _out_T_1122 : _GEN_2730; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2732 = 9'hd2 == out_iindex_1 ? _out_T_1122 : _GEN_2731; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2733 = 9'hd3 == out_iindex_1 ? _out_T_1122 : _GEN_2732; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2734 = 9'hd4 == out_iindex_1 ? _out_T_1122 : _GEN_2733; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2735 = 9'hd5 == out_iindex_1 ? _out_T_1122 : _GEN_2734; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2736 = 9'hd6 == out_iindex_1 ? _out_T_1122 : _GEN_2735; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2737 = 9'hd7 == out_iindex_1 ? _out_T_1122 : _GEN_2736; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2738 = 9'hd8 == out_iindex_1 ? _out_T_1122 : _GEN_2737; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2739 = 9'hd9 == out_iindex_1 ? _out_T_1122 : _GEN_2738; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2740 = 9'hda == out_iindex_1 ? _out_T_1122 : _GEN_2739; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2741 = 9'hdb == out_iindex_1 ? _out_T_1122 : _GEN_2740; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2742 = 9'hdc == out_iindex_1 ? _out_T_1122 : _GEN_2741; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2743 = 9'hdd == out_iindex_1 ? _out_T_1122 : _GEN_2742; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2744 = 9'hde == out_iindex_1 ? _out_T_1122 : _GEN_2743; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2745 = 9'hdf == out_iindex_1 ? _out_T_1122 : _GEN_2744; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2746 = 9'he0 == out_iindex_1 ? _out_T_1122 : _GEN_2745; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2761 = 9'hef == out_iindex_1 | (9'hee == out_iindex_1 | (9'hed == out_iindex_1 | (9'hec == out_iindex_1 | (9'heb
     == out_iindex_1 | (9'hea == out_iindex_1 | (9'he9 == out_iindex_1 | (9'he8 == out_iindex_1 | (9'he7 == out_iindex_1
     | (9'he6 == out_iindex_1 | (9'he5 == out_iindex_1 | (9'he4 == out_iindex_1 | (9'he3 == out_iindex_1 | (9'he2 ==
    out_iindex_1 | (9'he1 == out_iindex_1 | _GEN_2746)))))))))))))); // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2776 = 9'hfe == out_iindex_1 | (9'hfd == out_iindex_1 | (9'hfc == out_iindex_1 | (9'hfb == out_iindex_1 | (9'hfa
     == out_iindex_1 | (9'hf9 == out_iindex_1 | (9'hf8 == out_iindex_1 | (9'hf7 == out_iindex_1 | (9'hf6 == out_iindex_1
     | (9'hf5 == out_iindex_1 | (9'hf4 == out_iindex_1 | (9'hf3 == out_iindex_1 | (9'hf2 == out_iindex_1 | (9'hf1 ==
    out_iindex_1 | (9'hf0 == out_iindex_1 | _GEN_2761)))))))))))))); // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2778 = 9'h100 == out_iindex_1 ? _out_T_1122 : 9'hff == out_iindex_1 | _GEN_2776; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2779 = 9'h101 == out_iindex_1 ? _out_T_1122 : _GEN_2778; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2780 = 9'h102 == out_iindex_1 ? _out_T_1122 : _GEN_2779; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2781 = 9'h103 == out_iindex_1 ? _out_T_1122 : _GEN_2780; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2782 = 9'h104 == out_iindex_1 ? _out_T_1122 : _GEN_2781; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2783 = 9'h105 == out_iindex_1 ? _out_T_1122 : _GEN_2782; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2784 = 9'h106 == out_iindex_1 ? _out_T_1122 : _GEN_2783; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2785 = 9'h107 == out_iindex_1 ? _out_T_1122 : _GEN_2784; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2786 = 9'h108 == out_iindex_1 ? _out_T_1122 : _GEN_2785; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2787 = 9'h109 == out_iindex_1 ? _out_T_1122 : _GEN_2786; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2788 = 9'h10a == out_iindex_1 ? _out_T_1122 : _GEN_2787; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2789 = 9'h10b == out_iindex_1 ? _out_T_1122 : _GEN_2788; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2790 = 9'h10c == out_iindex_1 ? _out_T_1122 : _GEN_2789; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2791 = 9'h10d == out_iindex_1 ? _out_T_1122 : _GEN_2790; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2792 = 9'h10e == out_iindex_1 ? _out_T_1122 : _GEN_2791; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2793 = 9'h10f == out_iindex_1 ? _out_T_1122 : _GEN_2792; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2794 = 9'h110 == out_iindex_1 ? _out_T_1122 : _GEN_2793; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2795 = 9'h111 == out_iindex_1 ? _out_T_1122 : _GEN_2794; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2796 = 9'h112 == out_iindex_1 ? _out_T_1122 : _GEN_2795; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2797 = 9'h113 == out_iindex_1 ? _out_T_1122 : _GEN_2796; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2798 = 9'h114 == out_iindex_1 ? _out_T_1122 : _GEN_2797; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2799 = 9'h115 == out_iindex_1 ? _out_T_1122 : _GEN_2798; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2800 = 9'h116 == out_iindex_1 ? _out_T_1122 : _GEN_2799; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2801 = 9'h117 == out_iindex_1 ? _out_T_1122 : _GEN_2800; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2802 = 9'h118 == out_iindex_1 ? _out_T_1122 : _GEN_2801; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2803 = 9'h119 == out_iindex_1 ? _out_T_1122 : _GEN_2802; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2804 = 9'h11a == out_iindex_1 ? _out_T_1122 : _GEN_2803; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2805 = 9'h11b == out_iindex_1 ? _out_T_1122 : _GEN_2804; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2806 = 9'h11c == out_iindex_1 ? _out_T_1122 : _GEN_2805; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2807 = 9'h11d == out_iindex_1 ? _out_T_1122 : _GEN_2806; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2808 = 9'h11e == out_iindex_1 ? _out_T_1122 : _GEN_2807; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2809 = 9'h11f == out_iindex_1 ? _out_T_1122 : _GEN_2808; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2810 = 9'h120 == out_iindex_1 ? _out_T_1122 : _GEN_2809; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2811 = 9'h121 == out_iindex_1 ? _out_T_1122 : _GEN_2810; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2812 = 9'h122 == out_iindex_1 ? _out_T_1122 : _GEN_2811; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2813 = 9'h123 == out_iindex_1 ? _out_T_1122 : _GEN_2812; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2814 = 9'h124 == out_iindex_1 ? _out_T_1122 : _GEN_2813; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2815 = 9'h125 == out_iindex_1 ? _out_T_1122 : _GEN_2814; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2816 = 9'h126 == out_iindex_1 ? _out_T_1122 : _GEN_2815; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2817 = 9'h127 == out_iindex_1 ? _out_T_1122 : _GEN_2816; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2818 = 9'h128 == out_iindex_1 ? _out_T_1122 : _GEN_2817; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2819 = 9'h129 == out_iindex_1 ? _out_T_1122 : _GEN_2818; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2820 = 9'h12a == out_iindex_1 ? _out_T_1122 : _GEN_2819; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2821 = 9'h12b == out_iindex_1 ? _out_T_1122 : _GEN_2820; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2822 = 9'h12c == out_iindex_1 ? _out_T_1122 : _GEN_2821; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2823 = 9'h12d == out_iindex_1 ? _out_T_1122 : _GEN_2822; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2824 = 9'h12e == out_iindex_1 ? _out_T_1122 : _GEN_2823; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2825 = 9'h12f == out_iindex_1 ? _out_T_1122 : _GEN_2824; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2826 = 9'h130 == out_iindex_1 ? _out_T_1122 : _GEN_2825; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2827 = 9'h131 == out_iindex_1 ? _out_T_1122 : _GEN_2826; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2828 = 9'h132 == out_iindex_1 ? _out_T_1122 : _GEN_2827; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2829 = 9'h133 == out_iindex_1 ? _out_T_1122 : _GEN_2828; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2830 = 9'h134 == out_iindex_1 ? _out_T_1122 : _GEN_2829; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2831 = 9'h135 == out_iindex_1 ? _out_T_1122 : _GEN_2830; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2832 = 9'h136 == out_iindex_1 ? _out_T_1122 : _GEN_2831; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2833 = 9'h137 == out_iindex_1 ? _out_T_1122 : _GEN_2832; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2834 = 9'h138 == out_iindex_1 ? _out_T_1122 : _GEN_2833; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2835 = 9'h139 == out_iindex_1 ? _out_T_1122 : _GEN_2834; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2836 = 9'h13a == out_iindex_1 ? _out_T_1122 : _GEN_2835; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2837 = 9'h13b == out_iindex_1 ? _out_T_1122 : _GEN_2836; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2838 = 9'h13c == out_iindex_1 ? _out_T_1122 : _GEN_2837; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2839 = 9'h13d == out_iindex_1 ? _out_T_1122 : _GEN_2838; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2840 = 9'h13e == out_iindex_1 ? _out_T_1122 : _GEN_2839; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2841 = 9'h13f == out_iindex_1 ? _out_T_1122 : _GEN_2840; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2842 = 9'h140 == out_iindex_1 ? _out_T_1122 : _GEN_2841; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2843 = 9'h141 == out_iindex_1 ? _out_T_1122 : _GEN_2842; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2844 = 9'h142 == out_iindex_1 ? _out_T_1122 : _GEN_2843; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2845 = 9'h143 == out_iindex_1 ? _out_T_1122 : _GEN_2844; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2846 = 9'h144 == out_iindex_1 ? _out_T_1122 : _GEN_2845; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2847 = 9'h145 == out_iindex_1 ? _out_T_1122 : _GEN_2846; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2848 = 9'h146 == out_iindex_1 ? _out_T_1122 : _GEN_2847; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2849 = 9'h147 == out_iindex_1 ? _out_T_1122 : _GEN_2848; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2850 = 9'h148 == out_iindex_1 ? _out_T_1122 : _GEN_2849; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2851 = 9'h149 == out_iindex_1 ? _out_T_1122 : _GEN_2850; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2852 = 9'h14a == out_iindex_1 ? _out_T_1122 : _GEN_2851; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2853 = 9'h14b == out_iindex_1 ? _out_T_1122 : _GEN_2852; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2854 = 9'h14c == out_iindex_1 ? _out_T_1122 : _GEN_2853; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2855 = 9'h14d == out_iindex_1 ? _out_T_1122 : _GEN_2854; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2856 = 9'h14e == out_iindex_1 ? _out_T_1122 : _GEN_2855; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2857 = 9'h14f == out_iindex_1 ? _out_T_1122 : _GEN_2856; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2858 = 9'h150 == out_iindex_1 ? _out_T_1122 : _GEN_2857; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2859 = 9'h151 == out_iindex_1 ? _out_T_1122 : _GEN_2858; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2860 = 9'h152 == out_iindex_1 ? _out_T_1122 : _GEN_2859; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2861 = 9'h153 == out_iindex_1 ? _out_T_1122 : _GEN_2860; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2862 = 9'h154 == out_iindex_1 ? _out_T_1122 : _GEN_2861; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2863 = 9'h155 == out_iindex_1 ? _out_T_1122 : _GEN_2862; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2864 = 9'h156 == out_iindex_1 ? _out_T_1122 : _GEN_2863; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2865 = 9'h157 == out_iindex_1 ? _out_T_1122 : _GEN_2864; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2866 = 9'h158 == out_iindex_1 ? _out_T_1122 : _GEN_2865; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2867 = 9'h159 == out_iindex_1 ? _out_T_1122 : _GEN_2866; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2868 = 9'h15a == out_iindex_1 ? _out_T_1122 : _GEN_2867; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2869 = 9'h15b == out_iindex_1 ? _out_T_1122 : _GEN_2868; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2870 = 9'h15c == out_iindex_1 ? _out_T_1122 : _GEN_2869; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2871 = 9'h15d == out_iindex_1 ? _out_T_1122 : _GEN_2870; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2872 = 9'h15e == out_iindex_1 ? _out_T_1122 : _GEN_2871; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2873 = 9'h15f == out_iindex_1 ? _out_T_1122 : _GEN_2872; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2874 = 9'h160 == out_iindex_1 ? _out_T_1122 : _GEN_2873; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2875 = 9'h161 == out_iindex_1 ? _out_T_1122 : _GEN_2874; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2876 = 9'h162 == out_iindex_1 ? _out_T_1122 : _GEN_2875; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2877 = 9'h163 == out_iindex_1 ? _out_T_1122 : _GEN_2876; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2878 = 9'h164 == out_iindex_1 ? _out_T_1122 : _GEN_2877; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2879 = 9'h165 == out_iindex_1 ? _out_T_1122 : _GEN_2878; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2880 = 9'h166 == out_iindex_1 ? _out_T_1122 : _GEN_2879; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2881 = 9'h167 == out_iindex_1 ? _out_T_1122 : _GEN_2880; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2882 = 9'h168 == out_iindex_1 ? _out_T_1122 : _GEN_2881; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2883 = 9'h169 == out_iindex_1 ? _out_T_1122 : _GEN_2882; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2884 = 9'h16a == out_iindex_1 ? _out_T_1122 : _GEN_2883; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2885 = 9'h16b == out_iindex_1 ? _out_T_1122 : _GEN_2884; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2886 = 9'h16c == out_iindex_1 ? _out_T_1122 : _GEN_2885; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2887 = 9'h16d == out_iindex_1 ? _out_T_1122 : _GEN_2886; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2888 = 9'h16e == out_iindex_1 ? _out_T_1122 : _GEN_2887; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2889 = 9'h16f == out_iindex_1 ? _out_T_1122 : _GEN_2888; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2890 = 9'h170 == out_iindex_1 ? _out_T_1122 : _GEN_2889; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2891 = 9'h171 == out_iindex_1 ? _out_T_1122 : _GEN_2890; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2892 = 9'h172 == out_iindex_1 ? _out_T_1122 : _GEN_2891; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2893 = 9'h173 == out_iindex_1 ? _out_T_1122 : _GEN_2892; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2894 = 9'h174 == out_iindex_1 ? _out_T_1122 : _GEN_2893; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2895 = 9'h175 == out_iindex_1 ? _out_T_1122 : _GEN_2894; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2896 = 9'h176 == out_iindex_1 ? _out_T_1122 : _GEN_2895; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2897 = 9'h177 == out_iindex_1 ? _out_T_1122 : _GEN_2896; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2898 = 9'h178 == out_iindex_1 ? _out_T_1122 : _GEN_2897; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2899 = 9'h179 == out_iindex_1 ? _out_T_1122 : _GEN_2898; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2900 = 9'h17a == out_iindex_1 ? _out_T_1122 : _GEN_2899; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2901 = 9'h17b == out_iindex_1 ? _out_T_1122 : _GEN_2900; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2902 = 9'h17c == out_iindex_1 ? _out_T_1122 : _GEN_2901; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2903 = 9'h17d == out_iindex_1 ? _out_T_1122 : _GEN_2902; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2904 = 9'h17e == out_iindex_1 ? _out_T_1122 : _GEN_2903; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2905 = 9'h17f == out_iindex_1 ? _out_T_1122 : _GEN_2904; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2906 = 9'h180 == out_iindex_1 ? _out_T_1122 : _GEN_2905; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2907 = 9'h181 == out_iindex_1 ? _out_T_1122 : _GEN_2906; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2908 = 9'h182 == out_iindex_1 ? _out_T_1122 : _GEN_2907; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2909 = 9'h183 == out_iindex_1 ? _out_T_1122 : _GEN_2908; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2910 = 9'h184 == out_iindex_1 ? _out_T_1122 : _GEN_2909; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2911 = 9'h185 == out_iindex_1 ? _out_T_1122 : _GEN_2910; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2912 = 9'h186 == out_iindex_1 ? _out_T_1122 : _GEN_2911; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2913 = 9'h187 == out_iindex_1 ? _out_T_1122 : _GEN_2912; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2914 = 9'h188 == out_iindex_1 ? _out_T_1122 : _GEN_2913; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2915 = 9'h189 == out_iindex_1 ? _out_T_1122 : _GEN_2914; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2916 = 9'h18a == out_iindex_1 ? _out_T_1122 : _GEN_2915; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2917 = 9'h18b == out_iindex_1 ? _out_T_1122 : _GEN_2916; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2918 = 9'h18c == out_iindex_1 ? _out_T_1122 : _GEN_2917; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2919 = 9'h18d == out_iindex_1 ? _out_T_1122 : _GEN_2918; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2920 = 9'h18e == out_iindex_1 ? _out_T_1122 : _GEN_2919; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2921 = 9'h18f == out_iindex_1 ? _out_T_1122 : _GEN_2920; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2922 = 9'h190 == out_iindex_1 ? _out_T_1122 : _GEN_2921; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2923 = 9'h191 == out_iindex_1 ? _out_T_1122 : _GEN_2922; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2924 = 9'h192 == out_iindex_1 ? _out_T_1122 : _GEN_2923; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2925 = 9'h193 == out_iindex_1 ? _out_T_1122 : _GEN_2924; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2926 = 9'h194 == out_iindex_1 ? _out_T_1122 : _GEN_2925; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2927 = 9'h195 == out_iindex_1 ? _out_T_1122 : _GEN_2926; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2928 = 9'h196 == out_iindex_1 ? _out_T_1122 : _GEN_2927; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2929 = 9'h197 == out_iindex_1 ? _out_T_1122 : _GEN_2928; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2930 = 9'h198 == out_iindex_1 ? _out_T_1122 : _GEN_2929; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2931 = 9'h199 == out_iindex_1 ? _out_T_1122 : _GEN_2930; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2932 = 9'h19a == out_iindex_1 ? _out_T_1122 : _GEN_2931; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2933 = 9'h19b == out_iindex_1 ? _out_T_1122 : _GEN_2932; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2934 = 9'h19c == out_iindex_1 ? _out_T_1122 : _GEN_2933; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2935 = 9'h19d == out_iindex_1 ? _out_T_1122 : _GEN_2934; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2936 = 9'h19e == out_iindex_1 ? _out_T_1122 : _GEN_2935; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2937 = 9'h19f == out_iindex_1 ? _out_T_1122 : _GEN_2936; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2938 = 9'h1a0 == out_iindex_1 ? _out_T_1122 : _GEN_2937; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2939 = 9'h1a1 == out_iindex_1 ? _out_T_1122 : _GEN_2938; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2940 = 9'h1a2 == out_iindex_1 ? _out_T_1122 : _GEN_2939; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2941 = 9'h1a3 == out_iindex_1 ? _out_T_1122 : _GEN_2940; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2942 = 9'h1a4 == out_iindex_1 ? _out_T_1122 : _GEN_2941; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2943 = 9'h1a5 == out_iindex_1 ? _out_T_1122 : _GEN_2942; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2944 = 9'h1a6 == out_iindex_1 ? _out_T_1122 : _GEN_2943; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2945 = 9'h1a7 == out_iindex_1 ? _out_T_1122 : _GEN_2944; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2946 = 9'h1a8 == out_iindex_1 ? _out_T_1122 : _GEN_2945; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2947 = 9'h1a9 == out_iindex_1 ? _out_T_1122 : _GEN_2946; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2948 = 9'h1aa == out_iindex_1 ? _out_T_1122 : _GEN_2947; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2949 = 9'h1ab == out_iindex_1 ? _out_T_1122 : _GEN_2948; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2950 = 9'h1ac == out_iindex_1 ? _out_T_1122 : _GEN_2949; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2951 = 9'h1ad == out_iindex_1 ? _out_T_1122 : _GEN_2950; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2952 = 9'h1ae == out_iindex_1 ? _out_T_1122 : _GEN_2951; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2953 = 9'h1af == out_iindex_1 ? _out_T_1122 : _GEN_2952; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2954 = 9'h1b0 == out_iindex_1 ? _out_T_1122 : _GEN_2953; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2955 = 9'h1b1 == out_iindex_1 ? _out_T_1122 : _GEN_2954; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2956 = 9'h1b2 == out_iindex_1 ? _out_T_1122 : _GEN_2955; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2957 = 9'h1b3 == out_iindex_1 ? _out_T_1122 : _GEN_2956; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2958 = 9'h1b4 == out_iindex_1 ? _out_T_1122 : _GEN_2957; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2959 = 9'h1b5 == out_iindex_1 ? _out_T_1122 : _GEN_2958; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2960 = 9'h1b6 == out_iindex_1 ? _out_T_1122 : _GEN_2959; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2961 = 9'h1b7 == out_iindex_1 ? _out_T_1122 : _GEN_2960; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2962 = 9'h1b8 == out_iindex_1 ? _out_T_1122 : _GEN_2961; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2963 = 9'h1b9 == out_iindex_1 ? _out_T_1122 : _GEN_2962; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2964 = 9'h1ba == out_iindex_1 ? _out_T_1122 : _GEN_2963; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2965 = 9'h1bb == out_iindex_1 ? _out_T_1122 : _GEN_2964; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2966 = 9'h1bc == out_iindex_1 ? _out_T_1122 : _GEN_2965; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2967 = 9'h1bd == out_iindex_1 ? _out_T_1122 : _GEN_2966; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2968 = 9'h1be == out_iindex_1 ? _out_T_1122 : _GEN_2967; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2969 = 9'h1bf == out_iindex_1 ? _out_T_1122 : _GEN_2968; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2970 = 9'h1c0 == out_iindex_1 ? _out_T_1122 : _GEN_2969; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2971 = 9'h1c1 == out_iindex_1 ? _out_T_1122 : _GEN_2970; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2972 = 9'h1c2 == out_iindex_1 ? _out_T_1122 : _GEN_2971; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2973 = 9'h1c3 == out_iindex_1 ? _out_T_1122 : _GEN_2972; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2974 = 9'h1c4 == out_iindex_1 ? _out_T_1122 : _GEN_2973; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2975 = 9'h1c5 == out_iindex_1 ? _out_T_1122 : _GEN_2974; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2976 = 9'h1c6 == out_iindex_1 ? _out_T_1122 : _GEN_2975; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2977 = 9'h1c7 == out_iindex_1 ? _out_T_1122 : _GEN_2976; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2978 = 9'h1c8 == out_iindex_1 ? _out_T_1122 : _GEN_2977; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2979 = 9'h1c9 == out_iindex_1 ? _out_T_1122 : _GEN_2978; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2980 = 9'h1ca == out_iindex_1 ? _out_T_1122 : _GEN_2979; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2981 = 9'h1cb == out_iindex_1 ? _out_T_1122 : _GEN_2980; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2982 = 9'h1cc == out_iindex_1 ? _out_T_1122 : _GEN_2981; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2983 = 9'h1cd == out_iindex_1 ? _out_T_1122 : _GEN_2982; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2984 = 9'h1ce == out_iindex_1 ? _out_T_1122 : _GEN_2983; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2985 = 9'h1cf == out_iindex_1 ? _out_T_1122 : _GEN_2984; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2986 = 9'h1d0 == out_iindex_1 ? _out_T_1122 : _GEN_2985; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2987 = 9'h1d1 == out_iindex_1 ? _out_T_1122 : _GEN_2986; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2988 = 9'h1d2 == out_iindex_1 ? _out_T_1122 : _GEN_2987; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2989 = 9'h1d3 == out_iindex_1 ? _out_T_1122 : _GEN_2988; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2990 = 9'h1d4 == out_iindex_1 ? _out_T_1122 : _GEN_2989; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2991 = 9'h1d5 == out_iindex_1 ? _out_T_1122 : _GEN_2990; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2992 = 9'h1d6 == out_iindex_1 ? _out_T_1122 : _GEN_2991; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2993 = 9'h1d7 == out_iindex_1 ? _out_T_1122 : _GEN_2992; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2994 = 9'h1d8 == out_iindex_1 ? _out_T_1122 : _GEN_2993; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2995 = 9'h1d9 == out_iindex_1 ? _out_T_1122 : _GEN_2994; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2996 = 9'h1da == out_iindex_1 ? _out_T_1122 : _GEN_2995; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2997 = 9'h1db == out_iindex_1 ? _out_T_1122 : _GEN_2996; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2998 = 9'h1dc == out_iindex_1 ? _out_T_1122 : _GEN_2997; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_2999 = 9'h1dd == out_iindex_1 ? _out_T_1122 : _GEN_2998; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_3000 = 9'h1de == out_iindex_1 ? _out_T_1122 : _GEN_2999; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_3001 = 9'h1df == out_iindex_1 ? _out_T_1122 : _GEN_3000; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_3002 = 9'h1e0 == out_iindex_1 ? _out_T_1122 : _GEN_3001; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_3003 = 9'h1e1 == out_iindex_1 ? _out_T_1122 : _GEN_3002; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_3004 = 9'h1e2 == out_iindex_1 ? _out_T_1122 : _GEN_3003; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_3005 = 9'h1e3 == out_iindex_1 ? _out_T_1122 : _GEN_3004; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_3006 = 9'h1e4 == out_iindex_1 ? _out_T_1122 : _GEN_3005; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_3007 = 9'h1e5 == out_iindex_1 ? _out_T_1122 : _GEN_3006; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_3008 = 9'h1e6 == out_iindex_1 ? _out_T_1122 : _GEN_3007; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_3009 = 9'h1e7 == out_iindex_1 ? _out_T_1122 : _GEN_3008; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_3010 = 9'h1e8 == out_iindex_1 ? _out_T_1122 : _GEN_3009; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_3011 = 9'h1e9 == out_iindex_1 ? _out_T_1122 : _GEN_3010; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_3012 = 9'h1ea == out_iindex_1 ? _out_T_1122 : _GEN_3011; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_3013 = 9'h1eb == out_iindex_1 ? _out_T_1122 : _GEN_3012; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_3014 = 9'h1ec == out_iindex_1 ? _out_T_1122 : _GEN_3013; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_3015 = 9'h1ed == out_iindex_1 ? _out_T_1122 : _GEN_3014; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_3016 = 9'h1ee == out_iindex_1 ? _out_T_1122 : _GEN_3015; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_3017 = 9'h1ef == out_iindex_1 ? _out_T_1122 : _GEN_3016; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_3018 = 9'h1f0 == out_iindex_1 ? _out_T_1122 : _GEN_3017; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_3019 = 9'h1f1 == out_iindex_1 ? _out_T_1122 : _GEN_3018; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_3020 = 9'h1f2 == out_iindex_1 ? _out_T_1122 : _GEN_3019; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_3021 = 9'h1f3 == out_iindex_1 ? _out_T_1122 : _GEN_3020; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_3022 = 9'h1f4 == out_iindex_1 ? _out_T_1122 : _GEN_3021; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_3023 = 9'h1f5 == out_iindex_1 ? _out_T_1122 : _GEN_3022; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_3024 = 9'h1f6 == out_iindex_1 ? _out_T_1122 : _GEN_3023; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_3025 = 9'h1f7 == out_iindex_1 ? _out_T_1122 : _GEN_3024; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_3026 = 9'h1f8 == out_iindex_1 ? _out_T_1122 : _GEN_3025; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_3027 = 9'h1f9 == out_iindex_1 ? _out_T_1122 : _GEN_3026; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_3028 = 9'h1fa == out_iindex_1 ? _out_T_1122 : _GEN_3027; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_3029 = 9'h1fb == out_iindex_1 ? _out_T_1122 : _GEN_3028; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_3030 = 9'h1fc == out_iindex_1 ? _out_T_1122 : _GEN_3029; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_3031 = 9'h1fd == out_iindex_1 ? _out_T_1122 : _GEN_3030; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_3032 = 9'h1fe == out_iindex_1 ? _out_T_1122 : _GEN_3031; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_3033 = 9'h1ff == out_iindex_1 ? _out_T_1122 : _GEN_3032; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3035 = 9'h1 == out_iindex_1 ? 32'h380006f : 32'hc0006f; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3036 = 9'h2 == out_iindex_1 ? 32'h440006f : _GEN_3035; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3037 = 9'h3 == out_iindex_1 ? 32'hff0000f : _GEN_3036; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3038 = 9'h4 == out_iindex_1 ? 32'h7b241073 : _GEN_3037; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3039 = 9'h5 == out_iindex_1 ? 32'hf1402473 : _GEN_3038; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3040 = 9'h6 == out_iindex_1 ? 32'h10802023 : _GEN_3039; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3041 = 9'h7 == out_iindex_1 ? 32'h40044403 : _GEN_3040; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3042 = 9'h8 == out_iindex_1 ? 32'h347413 : _GEN_3041; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3043 = 9'h9 == out_iindex_1 ? 32'hfe0408e3 : _GEN_3042; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3044 = 9'ha == out_iindex_1 ? 32'h147413 : _GEN_3043; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3045 = 9'hb == out_iindex_1 ? 32'h40863 : _GEN_3044; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3046 = 9'hc == out_iindex_1 ? 32'h7b202473 : _GEN_3045; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3047 = 9'hd == out_iindex_1 ? 32'h10002223 : _GEN_3046; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3048 = 9'he == out_iindex_1 ? 32'h30000067 : _GEN_3047; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3049 = 9'hf == out_iindex_1 ? 32'hf1402473 : _GEN_3048; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3050 = 9'h10 == out_iindex_1 ? 32'h10802423 : _GEN_3049; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3051 = 9'h11 == out_iindex_1 ? 32'h7b202473 : _GEN_3050; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3052 = 9'h12 == out_iindex_1 ? 32'h7b200073 : _GEN_3051; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3053 = 9'h13 == out_iindex_1 ? 32'h10002623 : _GEN_3052; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3054 = 9'h14 == out_iindex_1 ? 32'h100073 : _GEN_3053; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3055 = 9'h15 == out_iindex_1 ? 32'h0 : _GEN_3054; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3056 = 9'h16 == out_iindex_1 ? 32'h0 : _GEN_3055; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3057 = 9'h17 == out_iindex_1 ? 32'h0 : _GEN_3056; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3058 = 9'h18 == out_iindex_1 ? 32'h0 : _GEN_3057; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3059 = 9'h19 == out_iindex_1 ? 32'h0 : _GEN_3058; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3060 = 9'h1a == out_iindex_1 ? 32'h0 : _GEN_3059; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3061 = 9'h1b == out_iindex_1 ? 32'h0 : _GEN_3060; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3062 = 9'h1c == out_iindex_1 ? 32'h0 : _GEN_3061; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3063 = 9'h1d == out_iindex_1 ? 32'h0 : _GEN_3062; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3064 = 9'h1e == out_iindex_1 ? 32'h0 : _GEN_3063; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3065 = 9'h1f == out_iindex_1 ? 32'h0 : _GEN_3064; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3066 = 9'h20 == out_iindex_1 ? 32'h0 : _GEN_3065; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3067 = 9'h21 == out_iindex_1 ? 32'h0 : _GEN_3066; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3068 = 9'h22 == out_iindex_1 ? 32'h0 : _GEN_3067; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3069 = 9'h23 == out_iindex_1 ? 32'h0 : _GEN_3068; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3070 = 9'h24 == out_iindex_1 ? 32'h0 : _GEN_3069; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3071 = 9'h25 == out_iindex_1 ? 32'h0 : _GEN_3070; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3072 = 9'h26 == out_iindex_1 ? 32'h0 : _GEN_3071; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3073 = 9'h27 == out_iindex_1 ? 32'h0 : _GEN_3072; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3074 = 9'h28 == out_iindex_1 ? 32'h0 : _GEN_3073; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3075 = 9'h29 == out_iindex_1 ? 32'h0 : _GEN_3074; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3076 = 9'h2a == out_iindex_1 ? 32'h0 : _GEN_3075; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3077 = 9'h2b == out_iindex_1 ? 32'h0 : _GEN_3076; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3078 = 9'h2c == out_iindex_1 ? 32'h0 : _GEN_3077; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3079 = 9'h2d == out_iindex_1 ? 32'h0 : _GEN_3078; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3080 = 9'h2e == out_iindex_1 ? 32'h0 : _GEN_3079; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3081 = 9'h2f == out_iindex_1 ? 32'h0 : _GEN_3080; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3082 = 9'h30 == out_iindex_1 ? 32'h0 : _GEN_3081; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3083 = 9'h31 == out_iindex_1 ? 32'h0 : _GEN_3082; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3084 = 9'h32 == out_iindex_1 ? 32'h0 : _GEN_3083; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3085 = 9'h33 == out_iindex_1 ? 32'h0 : _GEN_3084; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3086 = 9'h34 == out_iindex_1 ? 32'h0 : _GEN_3085; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3087 = 9'h35 == out_iindex_1 ? 32'h0 : _GEN_3086; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3088 = 9'h36 == out_iindex_1 ? 32'h0 : _GEN_3087; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3089 = 9'h37 == out_iindex_1 ? 32'h0 : _GEN_3088; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3090 = 9'h38 == out_iindex_1 ? 32'h0 : _GEN_3089; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3091 = 9'h39 == out_iindex_1 ? 32'h0 : _GEN_3090; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3092 = 9'h3a == out_iindex_1 ? 32'h0 : _GEN_3091; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3093 = 9'h3b == out_iindex_1 ? 32'h0 : _GEN_3092; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3094 = 9'h3c == out_iindex_1 ? 32'h0 : _GEN_3093; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3095 = 9'h3d == out_iindex_1 ? 32'h0 : _GEN_3094; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3096 = 9'h3e == out_iindex_1 ? 32'h0 : _GEN_3095; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3097 = 9'h3f == out_iindex_1 ? 32'h0 : _GEN_3096; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3098 = 9'h40 == out_iindex_1 ? 32'h0 : _GEN_3097; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3099 = 9'h41 == out_iindex_1 ? 32'h0 : _GEN_3098; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3100 = 9'h42 == out_iindex_1 ? 32'h0 : _GEN_3099; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3101 = 9'h43 == out_iindex_1 ? 32'h0 : _GEN_3100; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3102 = 9'h44 == out_iindex_1 ? 32'h0 : _GEN_3101; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3103 = 9'h45 == out_iindex_1 ? 32'h0 : _GEN_3102; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3104 = 9'h46 == out_iindex_1 ? 32'h0 : _GEN_3103; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3105 = 9'h47 == out_iindex_1 ? 32'h0 : _GEN_3104; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3106 = 9'h48 == out_iindex_1 ? 32'h0 : _GEN_3105; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3107 = 9'h49 == out_iindex_1 ? 32'h0 : _GEN_3106; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3108 = 9'h4a == out_iindex_1 ? 32'h0 : _GEN_3107; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3109 = 9'h4b == out_iindex_1 ? 32'h0 : _GEN_3108; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3110 = 9'h4c == out_iindex_1 ? 32'h0 : _GEN_3109; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3111 = 9'h4d == out_iindex_1 ? 32'h0 : _GEN_3110; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3112 = 9'h4e == out_iindex_1 ? 32'h0 : _GEN_3111; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3113 = 9'h4f == out_iindex_1 ? 32'h0 : _GEN_3112; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3114 = 9'h50 == out_iindex_1 ? 32'h0 : _GEN_3113; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3115 = 9'h51 == out_iindex_1 ? 32'h0 : _GEN_3114; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3116 = 9'h52 == out_iindex_1 ? 32'h0 : _GEN_3115; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3117 = 9'h53 == out_iindex_1 ? 32'h0 : _GEN_3116; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3118 = 9'h54 == out_iindex_1 ? 32'h0 : _GEN_3117; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3119 = 9'h55 == out_iindex_1 ? 32'h0 : _GEN_3118; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3120 = 9'h56 == out_iindex_1 ? 32'h0 : _GEN_3119; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3121 = 9'h57 == out_iindex_1 ? 32'h0 : _GEN_3120; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3122 = 9'h58 == out_iindex_1 ? 32'h0 : _GEN_3121; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3123 = 9'h59 == out_iindex_1 ? 32'h0 : _GEN_3122; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3124 = 9'h5a == out_iindex_1 ? 32'h0 : _GEN_3123; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3125 = 9'h5b == out_iindex_1 ? 32'h0 : _GEN_3124; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3126 = 9'h5c == out_iindex_1 ? 32'h0 : _GEN_3125; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3127 = 9'h5d == out_iindex_1 ? 32'h0 : _GEN_3126; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3128 = 9'h5e == out_iindex_1 ? 32'h0 : _GEN_3127; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3129 = 9'h5f == out_iindex_1 ? 32'h0 : _GEN_3128; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3130 = 9'h60 == out_iindex_1 ? 32'h0 : _GEN_3129; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3131 = 9'h61 == out_iindex_1 ? 32'h0 : _GEN_3130; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3132 = 9'h62 == out_iindex_1 ? 32'h0 : _GEN_3131; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3133 = 9'h63 == out_iindex_1 ? 32'h0 : _GEN_3132; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3134 = 9'h64 == out_iindex_1 ? 32'h0 : _GEN_3133; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3135 = 9'h65 == out_iindex_1 ? 32'h0 : _GEN_3134; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3136 = 9'h66 == out_iindex_1 ? 32'h0 : _GEN_3135; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3137 = 9'h67 == out_iindex_1 ? 32'h0 : _GEN_3136; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3138 = 9'h68 == out_iindex_1 ? 32'h0 : _GEN_3137; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3139 = 9'h69 == out_iindex_1 ? 32'h0 : _GEN_3138; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3140 = 9'h6a == out_iindex_1 ? 32'h0 : _GEN_3139; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3141 = 9'h6b == out_iindex_1 ? 32'h0 : _GEN_3140; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3142 = 9'h6c == out_iindex_1 ? 32'h0 : _GEN_3141; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3143 = 9'h6d == out_iindex_1 ? 32'h0 : _GEN_3142; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3144 = 9'h6e == out_iindex_1 ? 32'h0 : _GEN_3143; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3145 = 9'h6f == out_iindex_1 ? 32'h0 : _GEN_3144; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3146 = 9'h70 == out_iindex_1 ? 32'h0 : _GEN_3145; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3147 = 9'h71 == out_iindex_1 ? 32'h0 : _GEN_3146; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3148 = 9'h72 == out_iindex_1 ? 32'h0 : _GEN_3147; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3149 = 9'h73 == out_iindex_1 ? 32'h0 : _GEN_3148; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3150 = 9'h74 == out_iindex_1 ? 32'h0 : _GEN_3149; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3151 = 9'h75 == out_iindex_1 ? 32'h0 : _GEN_3150; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3152 = 9'h76 == out_iindex_1 ? 32'h0 : _GEN_3151; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3153 = 9'h77 == out_iindex_1 ? 32'h0 : _GEN_3152; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3154 = 9'h78 == out_iindex_1 ? 32'h0 : _GEN_3153; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3155 = 9'h79 == out_iindex_1 ? 32'h0 : _GEN_3154; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3156 = 9'h7a == out_iindex_1 ? 32'h0 : _GEN_3155; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3157 = 9'h7b == out_iindex_1 ? 32'h0 : _GEN_3156; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3158 = 9'h7c == out_iindex_1 ? 32'h0 : _GEN_3157; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3159 = 9'h7d == out_iindex_1 ? 32'h0 : _GEN_3158; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3160 = 9'h7e == out_iindex_1 ? 32'h0 : _GEN_3159; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3161 = 9'h7f == out_iindex_1 ? 32'h0 : _GEN_3160; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3162 = 9'h80 == out_iindex_1 ? 32'h0 : _GEN_3161; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3163 = 9'h81 == out_iindex_1 ? 32'h0 : _GEN_3162; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3164 = 9'h82 == out_iindex_1 ? 32'h0 : _GEN_3163; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3165 = 9'h83 == out_iindex_1 ? 32'h0 : _GEN_3164; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3166 = 9'h84 == out_iindex_1 ? 32'h0 : _GEN_3165; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3167 = 9'h85 == out_iindex_1 ? 32'h0 : _GEN_3166; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3168 = 9'h86 == out_iindex_1 ? 32'h0 : _GEN_3167; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3169 = 9'h87 == out_iindex_1 ? 32'h0 : _GEN_3168; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3170 = 9'h88 == out_iindex_1 ? 32'h0 : _GEN_3169; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3171 = 9'h89 == out_iindex_1 ? 32'h0 : _GEN_3170; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3172 = 9'h8a == out_iindex_1 ? 32'h0 : _GEN_3171; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3173 = 9'h8b == out_iindex_1 ? 32'h0 : _GEN_3172; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3174 = 9'h8c == out_iindex_1 ? 32'h0 : _GEN_3173; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3175 = 9'h8d == out_iindex_1 ? 32'h0 : _GEN_3174; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3176 = 9'h8e == out_iindex_1 ? 32'h0 : _GEN_3175; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3177 = 9'h8f == out_iindex_1 ? 32'h0 : _GEN_3176; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3178 = 9'h90 == out_iindex_1 ? 32'h0 : _GEN_3177; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3179 = 9'h91 == out_iindex_1 ? 32'h0 : _GEN_3178; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3180 = 9'h92 == out_iindex_1 ? 32'h0 : _GEN_3179; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3181 = 9'h93 == out_iindex_1 ? 32'h0 : _GEN_3180; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3182 = 9'h94 == out_iindex_1 ? 32'h0 : _GEN_3181; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3183 = 9'h95 == out_iindex_1 ? 32'h0 : _GEN_3182; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3184 = 9'h96 == out_iindex_1 ? 32'h0 : _GEN_3183; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3185 = 9'h97 == out_iindex_1 ? 32'h0 : _GEN_3184; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3186 = 9'h98 == out_iindex_1 ? 32'h0 : _GEN_3185; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3187 = 9'h99 == out_iindex_1 ? 32'h0 : _GEN_3186; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3188 = 9'h9a == out_iindex_1 ? 32'h0 : _GEN_3187; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3189 = 9'h9b == out_iindex_1 ? 32'h0 : _GEN_3188; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3190 = 9'h9c == out_iindex_1 ? 32'h0 : _GEN_3189; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3191 = 9'h9d == out_iindex_1 ? 32'h0 : _GEN_3190; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3192 = 9'h9e == out_iindex_1 ? 32'h0 : _GEN_3191; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3193 = 9'h9f == out_iindex_1 ? 32'h0 : _GEN_3192; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3194 = 9'ha0 == out_iindex_1 ? 32'h0 : _GEN_3193; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3195 = 9'ha1 == out_iindex_1 ? 32'h0 : _GEN_3194; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3196 = 9'ha2 == out_iindex_1 ? 32'h0 : _GEN_3195; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3197 = 9'ha3 == out_iindex_1 ? 32'h0 : _GEN_3196; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3198 = 9'ha4 == out_iindex_1 ? 32'h0 : _GEN_3197; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3199 = 9'ha5 == out_iindex_1 ? 32'h0 : _GEN_3198; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3200 = 9'ha6 == out_iindex_1 ? 32'h0 : _GEN_3199; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3201 = 9'ha7 == out_iindex_1 ? 32'h0 : _GEN_3200; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3202 = 9'ha8 == out_iindex_1 ? 32'h0 : _GEN_3201; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3203 = 9'ha9 == out_iindex_1 ? 32'h0 : _GEN_3202; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3204 = 9'haa == out_iindex_1 ? 32'h0 : _GEN_3203; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3205 = 9'hab == out_iindex_1 ? 32'h0 : _GEN_3204; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3206 = 9'hac == out_iindex_1 ? 32'h0 : _GEN_3205; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3207 = 9'had == out_iindex_1 ? 32'h0 : _GEN_3206; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3208 = 9'hae == out_iindex_1 ? 32'h0 : _GEN_3207; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3209 = 9'haf == out_iindex_1 ? 32'h0 : _GEN_3208; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3210 = 9'hb0 == out_iindex_1 ? 32'h0 : _GEN_3209; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3211 = 9'hb1 == out_iindex_1 ? 32'h0 : _GEN_3210; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3212 = 9'hb2 == out_iindex_1 ? 32'h0 : _GEN_3211; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3213 = 9'hb3 == out_iindex_1 ? 32'h0 : _GEN_3212; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3214 = 9'hb4 == out_iindex_1 ? 32'h0 : _GEN_3213; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3215 = 9'hb5 == out_iindex_1 ? 32'h0 : _GEN_3214; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3216 = 9'hb6 == out_iindex_1 ? 32'h0 : _GEN_3215; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3217 = 9'hb7 == out_iindex_1 ? 32'h0 : _GEN_3216; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3218 = 9'hb8 == out_iindex_1 ? 32'h0 : _GEN_3217; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3219 = 9'hb9 == out_iindex_1 ? 32'h0 : _GEN_3218; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3220 = 9'hba == out_iindex_1 ? 32'h0 : _GEN_3219; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3221 = 9'hbb == out_iindex_1 ? 32'h0 : _GEN_3220; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3222 = 9'hbc == out_iindex_1 ? 32'h0 : _GEN_3221; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3223 = 9'hbd == out_iindex_1 ? 32'h0 : _GEN_3222; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3224 = 9'hbe == out_iindex_1 ? 32'h0 : _GEN_3223; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3225 = 9'hbf == out_iindex_1 ? 32'h0 : _GEN_3224; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3226 = 9'hc0 == out_iindex_1 ? 32'h380006f : _GEN_3225; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3227 = 9'hc1 == out_iindex_1 ? 32'h0 : _GEN_3226; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3228 = 9'hc2 == out_iindex_1 ? 32'h0 : _GEN_3227; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3229 = 9'hc3 == out_iindex_1 ? 32'h0 : _GEN_3228; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3230 = 9'hc4 == out_iindex_1 ? 32'h0 : _GEN_3229; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3231 = 9'hc5 == out_iindex_1 ? 32'h0 : _GEN_3230; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3232 = 9'hc6 == out_iindex_1 ? 32'h0 : _GEN_3231; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3233 = 9'hc7 == out_iindex_1 ? 32'h0 : _GEN_3232; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3234 = 9'hc8 == out_iindex_1 ? 32'h0 : _GEN_3233; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3235 = 9'hc9 == out_iindex_1 ? 32'h0 : _GEN_3234; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3236 = 9'hca == out_iindex_1 ? 32'h0 : _GEN_3235; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3237 = 9'hcb == out_iindex_1 ? 32'h0 : _GEN_3236; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3238 = 9'hcc == out_iindex_1 ? 32'h0 : _GEN_3237; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3239 = 9'hcd == out_iindex_1 ? 32'h0 : _GEN_3238; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3240 = 9'hce == out_iindex_1 ? abstractGeneratedMem_0 : _GEN_3239; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3241 = 9'hcf == out_iindex_1 ? abstractGeneratedMem_1 : _GEN_3240; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3242 = 9'hd0 == out_iindex_1 ? out_prepend_22 : _GEN_3241; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3243 = 9'hd1 == out_iindex_1 ? out_prepend_16 : _GEN_3242; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3244 = 9'hd2 == out_iindex_1 ? out_prepend_25 : _GEN_3243; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3245 = 9'hd3 == out_iindex_1 ? out_prepend_61 : _GEN_3244; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3246 = 9'hd4 == out_iindex_1 ? out_prepend_70 : _GEN_3245; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3247 = 9'hd5 == out_iindex_1 ? out_prepend_7 : _GEN_3246; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3248 = 9'hd6 == out_iindex_1 ? out_prepend_13 : _GEN_3247; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3249 = 9'hd7 == out_iindex_1 ? out_prepend_58 : _GEN_3248; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3250 = 9'hd8 == out_iindex_1 ? out_prepend_67 : _GEN_3249; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3251 = 9'hd9 == out_iindex_1 ? out_prepend_19 : _GEN_3250; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3252 = 9'hda == out_iindex_1 ? out_prepend_2 : _GEN_3251; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3253 = 9'hdb == out_iindex_1 ? out_prepend_64 : _GEN_3252; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3254 = 9'hdc == out_iindex_1 ? out_prepend_55 : _GEN_3253; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3255 = 9'hdd == out_iindex_1 ? out_prepend_28 : _GEN_3254; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3256 = 9'hde == out_iindex_1 ? out_prepend_10 : _GEN_3255; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3257 = 9'hdf == out_iindex_1 ? out_prepend_76 : _GEN_3256; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3258 = 9'he0 == out_iindex_1 ? out_prepend_73 : _GEN_3257; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3259 = 9'he1 == out_iindex_1 ? 32'h0 : _GEN_3258; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3260 = 9'he2 == out_iindex_1 ? 32'h0 : _GEN_3259; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3261 = 9'he3 == out_iindex_1 ? 32'h0 : _GEN_3260; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3262 = 9'he4 == out_iindex_1 ? 32'h0 : _GEN_3261; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3263 = 9'he5 == out_iindex_1 ? 32'h0 : _GEN_3262; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3264 = 9'he6 == out_iindex_1 ? 32'h0 : _GEN_3263; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3265 = 9'he7 == out_iindex_1 ? 32'h0 : _GEN_3264; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3266 = 9'he8 == out_iindex_1 ? 32'h0 : _GEN_3265; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3267 = 9'he9 == out_iindex_1 ? 32'h0 : _GEN_3266; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3268 = 9'hea == out_iindex_1 ? 32'h0 : _GEN_3267; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3269 = 9'heb == out_iindex_1 ? 32'h0 : _GEN_3268; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3270 = 9'hec == out_iindex_1 ? 32'h0 : _GEN_3269; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3271 = 9'hed == out_iindex_1 ? 32'h0 : _GEN_3270; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3272 = 9'hee == out_iindex_1 ? 32'h0 : _GEN_3271; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3273 = 9'hef == out_iindex_1 ? 32'h0 : _GEN_3272; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3274 = 9'hf0 == out_iindex_1 ? 32'h0 : _GEN_3273; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3275 = 9'hf1 == out_iindex_1 ? 32'h0 : _GEN_3274; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3276 = 9'hf2 == out_iindex_1 ? 32'h0 : _GEN_3275; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3277 = 9'hf3 == out_iindex_1 ? 32'h0 : _GEN_3276; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3278 = 9'hf4 == out_iindex_1 ? 32'h0 : _GEN_3277; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3279 = 9'hf5 == out_iindex_1 ? 32'h0 : _GEN_3278; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3280 = 9'hf6 == out_iindex_1 ? 32'h0 : _GEN_3279; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3281 = 9'hf7 == out_iindex_1 ? 32'h0 : _GEN_3280; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3282 = 9'hf8 == out_iindex_1 ? 32'h0 : _GEN_3281; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3283 = 9'hf9 == out_iindex_1 ? 32'h0 : _GEN_3282; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3284 = 9'hfa == out_iindex_1 ? 32'h0 : _GEN_3283; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3285 = 9'hfb == out_iindex_1 ? 32'h0 : _GEN_3284; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3286 = 9'hfc == out_iindex_1 ? 32'h0 : _GEN_3285; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3287 = 9'hfd == out_iindex_1 ? 32'h0 : _GEN_3286; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3288 = 9'hfe == out_iindex_1 ? 32'h0 : _GEN_3287; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3289 = 9'hff == out_iindex_1 ? 32'h0 : _GEN_3288; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3290 = 9'h100 == out_iindex_1 ? out_prepend_79 : _GEN_3289; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3291 = 9'h101 == out_iindex_1 ? out_prepend_79 : _GEN_3290; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3292 = 9'h102 == out_iindex_1 ? out_prepend_79 : _GEN_3291; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3293 = 9'h103 == out_iindex_1 ? out_prepend_79 : _GEN_3292; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3294 = 9'h104 == out_iindex_1 ? out_prepend_79 : _GEN_3293; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3295 = 9'h105 == out_iindex_1 ? out_prepend_79 : _GEN_3294; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3296 = 9'h106 == out_iindex_1 ? out_prepend_79 : _GEN_3295; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3297 = 9'h107 == out_iindex_1 ? out_prepend_79 : _GEN_3296; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3298 = 9'h108 == out_iindex_1 ? out_prepend_79 : _GEN_3297; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3299 = 9'h109 == out_iindex_1 ? out_prepend_79 : _GEN_3298; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3300 = 9'h10a == out_iindex_1 ? out_prepend_79 : _GEN_3299; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3301 = 9'h10b == out_iindex_1 ? out_prepend_79 : _GEN_3300; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3302 = 9'h10c == out_iindex_1 ? out_prepend_79 : _GEN_3301; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3303 = 9'h10d == out_iindex_1 ? out_prepend_79 : _GEN_3302; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3304 = 9'h10e == out_iindex_1 ? out_prepend_79 : _GEN_3303; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3305 = 9'h10f == out_iindex_1 ? out_prepend_79 : _GEN_3304; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3306 = 9'h110 == out_iindex_1 ? out_prepend_79 : _GEN_3305; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3307 = 9'h111 == out_iindex_1 ? out_prepend_79 : _GEN_3306; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3308 = 9'h112 == out_iindex_1 ? out_prepend_79 : _GEN_3307; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3309 = 9'h113 == out_iindex_1 ? out_prepend_79 : _GEN_3308; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3310 = 9'h114 == out_iindex_1 ? out_prepend_79 : _GEN_3309; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3311 = 9'h115 == out_iindex_1 ? out_prepend_79 : _GEN_3310; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3312 = 9'h116 == out_iindex_1 ? out_prepend_79 : _GEN_3311; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3313 = 9'h117 == out_iindex_1 ? out_prepend_79 : _GEN_3312; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3314 = 9'h118 == out_iindex_1 ? out_prepend_79 : _GEN_3313; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3315 = 9'h119 == out_iindex_1 ? out_prepend_79 : _GEN_3314; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3316 = 9'h11a == out_iindex_1 ? out_prepend_79 : _GEN_3315; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3317 = 9'h11b == out_iindex_1 ? out_prepend_79 : _GEN_3316; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3318 = 9'h11c == out_iindex_1 ? out_prepend_79 : _GEN_3317; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3319 = 9'h11d == out_iindex_1 ? out_prepend_79 : _GEN_3318; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3320 = 9'h11e == out_iindex_1 ? out_prepend_79 : _GEN_3319; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3321 = 9'h11f == out_iindex_1 ? out_prepend_79 : _GEN_3320; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3322 = 9'h120 == out_iindex_1 ? out_prepend_79 : _GEN_3321; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3323 = 9'h121 == out_iindex_1 ? out_prepend_79 : _GEN_3322; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3324 = 9'h122 == out_iindex_1 ? out_prepend_79 : _GEN_3323; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3325 = 9'h123 == out_iindex_1 ? out_prepend_79 : _GEN_3324; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3326 = 9'h124 == out_iindex_1 ? out_prepend_79 : _GEN_3325; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3327 = 9'h125 == out_iindex_1 ? out_prepend_79 : _GEN_3326; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3328 = 9'h126 == out_iindex_1 ? out_prepend_79 : _GEN_3327; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3329 = 9'h127 == out_iindex_1 ? out_prepend_79 : _GEN_3328; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3330 = 9'h128 == out_iindex_1 ? out_prepend_79 : _GEN_3329; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3331 = 9'h129 == out_iindex_1 ? out_prepend_79 : _GEN_3330; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3332 = 9'h12a == out_iindex_1 ? out_prepend_79 : _GEN_3331; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3333 = 9'h12b == out_iindex_1 ? out_prepend_79 : _GEN_3332; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3334 = 9'h12c == out_iindex_1 ? out_prepend_79 : _GEN_3333; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3335 = 9'h12d == out_iindex_1 ? out_prepend_79 : _GEN_3334; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3336 = 9'h12e == out_iindex_1 ? out_prepend_79 : _GEN_3335; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3337 = 9'h12f == out_iindex_1 ? out_prepend_79 : _GEN_3336; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3338 = 9'h130 == out_iindex_1 ? out_prepend_79 : _GEN_3337; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3339 = 9'h131 == out_iindex_1 ? out_prepend_79 : _GEN_3338; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3340 = 9'h132 == out_iindex_1 ? out_prepend_79 : _GEN_3339; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3341 = 9'h133 == out_iindex_1 ? out_prepend_79 : _GEN_3340; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3342 = 9'h134 == out_iindex_1 ? out_prepend_79 : _GEN_3341; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3343 = 9'h135 == out_iindex_1 ? out_prepend_79 : _GEN_3342; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3344 = 9'h136 == out_iindex_1 ? out_prepend_79 : _GEN_3343; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3345 = 9'h137 == out_iindex_1 ? out_prepend_79 : _GEN_3344; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3346 = 9'h138 == out_iindex_1 ? out_prepend_79 : _GEN_3345; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3347 = 9'h139 == out_iindex_1 ? out_prepend_79 : _GEN_3346; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3348 = 9'h13a == out_iindex_1 ? out_prepend_79 : _GEN_3347; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3349 = 9'h13b == out_iindex_1 ? out_prepend_79 : _GEN_3348; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3350 = 9'h13c == out_iindex_1 ? out_prepend_79 : _GEN_3349; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3351 = 9'h13d == out_iindex_1 ? out_prepend_79 : _GEN_3350; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3352 = 9'h13e == out_iindex_1 ? out_prepend_79 : _GEN_3351; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3353 = 9'h13f == out_iindex_1 ? out_prepend_79 : _GEN_3352; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3354 = 9'h140 == out_iindex_1 ? out_prepend_79 : _GEN_3353; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3355 = 9'h141 == out_iindex_1 ? out_prepend_79 : _GEN_3354; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3356 = 9'h142 == out_iindex_1 ? out_prepend_79 : _GEN_3355; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3357 = 9'h143 == out_iindex_1 ? out_prepend_79 : _GEN_3356; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3358 = 9'h144 == out_iindex_1 ? out_prepend_79 : _GEN_3357; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3359 = 9'h145 == out_iindex_1 ? out_prepend_79 : _GEN_3358; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3360 = 9'h146 == out_iindex_1 ? out_prepend_79 : _GEN_3359; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3361 = 9'h147 == out_iindex_1 ? out_prepend_79 : _GEN_3360; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3362 = 9'h148 == out_iindex_1 ? out_prepend_79 : _GEN_3361; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3363 = 9'h149 == out_iindex_1 ? out_prepend_79 : _GEN_3362; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3364 = 9'h14a == out_iindex_1 ? out_prepend_79 : _GEN_3363; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3365 = 9'h14b == out_iindex_1 ? out_prepend_79 : _GEN_3364; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3366 = 9'h14c == out_iindex_1 ? out_prepend_79 : _GEN_3365; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3367 = 9'h14d == out_iindex_1 ? out_prepend_79 : _GEN_3366; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3368 = 9'h14e == out_iindex_1 ? out_prepend_79 : _GEN_3367; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3369 = 9'h14f == out_iindex_1 ? out_prepend_79 : _GEN_3368; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3370 = 9'h150 == out_iindex_1 ? out_prepend_79 : _GEN_3369; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3371 = 9'h151 == out_iindex_1 ? out_prepend_79 : _GEN_3370; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3372 = 9'h152 == out_iindex_1 ? out_prepend_79 : _GEN_3371; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3373 = 9'h153 == out_iindex_1 ? out_prepend_79 : _GEN_3372; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3374 = 9'h154 == out_iindex_1 ? out_prepend_79 : _GEN_3373; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3375 = 9'h155 == out_iindex_1 ? out_prepend_79 : _GEN_3374; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3376 = 9'h156 == out_iindex_1 ? out_prepend_79 : _GEN_3375; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3377 = 9'h157 == out_iindex_1 ? out_prepend_79 : _GEN_3376; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3378 = 9'h158 == out_iindex_1 ? out_prepend_79 : _GEN_3377; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3379 = 9'h159 == out_iindex_1 ? out_prepend_79 : _GEN_3378; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3380 = 9'h15a == out_iindex_1 ? out_prepend_79 : _GEN_3379; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3381 = 9'h15b == out_iindex_1 ? out_prepend_79 : _GEN_3380; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3382 = 9'h15c == out_iindex_1 ? out_prepend_79 : _GEN_3381; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3383 = 9'h15d == out_iindex_1 ? out_prepend_79 : _GEN_3382; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3384 = 9'h15e == out_iindex_1 ? out_prepend_79 : _GEN_3383; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3385 = 9'h15f == out_iindex_1 ? out_prepend_79 : _GEN_3384; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3386 = 9'h160 == out_iindex_1 ? out_prepend_79 : _GEN_3385; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3387 = 9'h161 == out_iindex_1 ? out_prepend_79 : _GEN_3386; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3388 = 9'h162 == out_iindex_1 ? out_prepend_79 : _GEN_3387; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3389 = 9'h163 == out_iindex_1 ? out_prepend_79 : _GEN_3388; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3390 = 9'h164 == out_iindex_1 ? out_prepend_79 : _GEN_3389; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3391 = 9'h165 == out_iindex_1 ? out_prepend_79 : _GEN_3390; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3392 = 9'h166 == out_iindex_1 ? out_prepend_79 : _GEN_3391; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3393 = 9'h167 == out_iindex_1 ? out_prepend_79 : _GEN_3392; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3394 = 9'h168 == out_iindex_1 ? out_prepend_79 : _GEN_3393; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3395 = 9'h169 == out_iindex_1 ? out_prepend_79 : _GEN_3394; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3396 = 9'h16a == out_iindex_1 ? out_prepend_79 : _GEN_3395; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3397 = 9'h16b == out_iindex_1 ? out_prepend_79 : _GEN_3396; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3398 = 9'h16c == out_iindex_1 ? out_prepend_79 : _GEN_3397; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3399 = 9'h16d == out_iindex_1 ? out_prepend_79 : _GEN_3398; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3400 = 9'h16e == out_iindex_1 ? out_prepend_79 : _GEN_3399; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3401 = 9'h16f == out_iindex_1 ? out_prepend_79 : _GEN_3400; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3402 = 9'h170 == out_iindex_1 ? out_prepend_79 : _GEN_3401; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3403 = 9'h171 == out_iindex_1 ? out_prepend_79 : _GEN_3402; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3404 = 9'h172 == out_iindex_1 ? out_prepend_79 : _GEN_3403; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3405 = 9'h173 == out_iindex_1 ? out_prepend_79 : _GEN_3404; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3406 = 9'h174 == out_iindex_1 ? out_prepend_79 : _GEN_3405; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3407 = 9'h175 == out_iindex_1 ? out_prepend_79 : _GEN_3406; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3408 = 9'h176 == out_iindex_1 ? out_prepend_79 : _GEN_3407; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3409 = 9'h177 == out_iindex_1 ? out_prepend_79 : _GEN_3408; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3410 = 9'h178 == out_iindex_1 ? out_prepend_79 : _GEN_3409; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3411 = 9'h179 == out_iindex_1 ? out_prepend_79 : _GEN_3410; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3412 = 9'h17a == out_iindex_1 ? out_prepend_79 : _GEN_3411; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3413 = 9'h17b == out_iindex_1 ? out_prepend_79 : _GEN_3412; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3414 = 9'h17c == out_iindex_1 ? out_prepend_79 : _GEN_3413; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3415 = 9'h17d == out_iindex_1 ? out_prepend_79 : _GEN_3414; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3416 = 9'h17e == out_iindex_1 ? out_prepend_79 : _GEN_3415; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3417 = 9'h17f == out_iindex_1 ? out_prepend_79 : _GEN_3416; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3418 = 9'h180 == out_iindex_1 ? out_prepend_79 : _GEN_3417; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3419 = 9'h181 == out_iindex_1 ? out_prepend_79 : _GEN_3418; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3420 = 9'h182 == out_iindex_1 ? out_prepend_79 : _GEN_3419; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3421 = 9'h183 == out_iindex_1 ? out_prepend_79 : _GEN_3420; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3422 = 9'h184 == out_iindex_1 ? out_prepend_79 : _GEN_3421; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3423 = 9'h185 == out_iindex_1 ? out_prepend_79 : _GEN_3422; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3424 = 9'h186 == out_iindex_1 ? out_prepend_79 : _GEN_3423; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3425 = 9'h187 == out_iindex_1 ? out_prepend_79 : _GEN_3424; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3426 = 9'h188 == out_iindex_1 ? out_prepend_79 : _GEN_3425; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3427 = 9'h189 == out_iindex_1 ? out_prepend_79 : _GEN_3426; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3428 = 9'h18a == out_iindex_1 ? out_prepend_79 : _GEN_3427; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3429 = 9'h18b == out_iindex_1 ? out_prepend_79 : _GEN_3428; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3430 = 9'h18c == out_iindex_1 ? out_prepend_79 : _GEN_3429; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3431 = 9'h18d == out_iindex_1 ? out_prepend_79 : _GEN_3430; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3432 = 9'h18e == out_iindex_1 ? out_prepend_79 : _GEN_3431; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3433 = 9'h18f == out_iindex_1 ? out_prepend_79 : _GEN_3432; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3434 = 9'h190 == out_iindex_1 ? out_prepend_79 : _GEN_3433; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3435 = 9'h191 == out_iindex_1 ? out_prepend_79 : _GEN_3434; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3436 = 9'h192 == out_iindex_1 ? out_prepend_79 : _GEN_3435; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3437 = 9'h193 == out_iindex_1 ? out_prepend_79 : _GEN_3436; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3438 = 9'h194 == out_iindex_1 ? out_prepend_79 : _GEN_3437; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3439 = 9'h195 == out_iindex_1 ? out_prepend_79 : _GEN_3438; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3440 = 9'h196 == out_iindex_1 ? out_prepend_79 : _GEN_3439; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3441 = 9'h197 == out_iindex_1 ? out_prepend_79 : _GEN_3440; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3442 = 9'h198 == out_iindex_1 ? out_prepend_79 : _GEN_3441; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3443 = 9'h199 == out_iindex_1 ? out_prepend_79 : _GEN_3442; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3444 = 9'h19a == out_iindex_1 ? out_prepend_79 : _GEN_3443; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3445 = 9'h19b == out_iindex_1 ? out_prepend_79 : _GEN_3444; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3446 = 9'h19c == out_iindex_1 ? out_prepend_79 : _GEN_3445; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3447 = 9'h19d == out_iindex_1 ? out_prepend_79 : _GEN_3446; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3448 = 9'h19e == out_iindex_1 ? out_prepend_79 : _GEN_3447; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3449 = 9'h19f == out_iindex_1 ? out_prepend_79 : _GEN_3448; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3450 = 9'h1a0 == out_iindex_1 ? out_prepend_79 : _GEN_3449; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3451 = 9'h1a1 == out_iindex_1 ? out_prepend_79 : _GEN_3450; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3452 = 9'h1a2 == out_iindex_1 ? out_prepend_79 : _GEN_3451; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3453 = 9'h1a3 == out_iindex_1 ? out_prepend_79 : _GEN_3452; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3454 = 9'h1a4 == out_iindex_1 ? out_prepend_79 : _GEN_3453; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3455 = 9'h1a5 == out_iindex_1 ? out_prepend_79 : _GEN_3454; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3456 = 9'h1a6 == out_iindex_1 ? out_prepend_79 : _GEN_3455; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3457 = 9'h1a7 == out_iindex_1 ? out_prepend_79 : _GEN_3456; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3458 = 9'h1a8 == out_iindex_1 ? out_prepend_79 : _GEN_3457; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3459 = 9'h1a9 == out_iindex_1 ? out_prepend_79 : _GEN_3458; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3460 = 9'h1aa == out_iindex_1 ? out_prepend_79 : _GEN_3459; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3461 = 9'h1ab == out_iindex_1 ? out_prepend_79 : _GEN_3460; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3462 = 9'h1ac == out_iindex_1 ? out_prepend_79 : _GEN_3461; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3463 = 9'h1ad == out_iindex_1 ? out_prepend_79 : _GEN_3462; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3464 = 9'h1ae == out_iindex_1 ? out_prepend_79 : _GEN_3463; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3465 = 9'h1af == out_iindex_1 ? out_prepend_79 : _GEN_3464; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3466 = 9'h1b0 == out_iindex_1 ? out_prepend_79 : _GEN_3465; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3467 = 9'h1b1 == out_iindex_1 ? out_prepend_79 : _GEN_3466; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3468 = 9'h1b2 == out_iindex_1 ? out_prepend_79 : _GEN_3467; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3469 = 9'h1b3 == out_iindex_1 ? out_prepend_79 : _GEN_3468; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3470 = 9'h1b4 == out_iindex_1 ? out_prepend_79 : _GEN_3469; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3471 = 9'h1b5 == out_iindex_1 ? out_prepend_79 : _GEN_3470; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3472 = 9'h1b6 == out_iindex_1 ? out_prepend_79 : _GEN_3471; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3473 = 9'h1b7 == out_iindex_1 ? out_prepend_79 : _GEN_3472; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3474 = 9'h1b8 == out_iindex_1 ? out_prepend_79 : _GEN_3473; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3475 = 9'h1b9 == out_iindex_1 ? out_prepend_79 : _GEN_3474; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3476 = 9'h1ba == out_iindex_1 ? out_prepend_79 : _GEN_3475; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3477 = 9'h1bb == out_iindex_1 ? out_prepend_79 : _GEN_3476; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3478 = 9'h1bc == out_iindex_1 ? out_prepend_79 : _GEN_3477; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3479 = 9'h1bd == out_iindex_1 ? out_prepend_79 : _GEN_3478; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3480 = 9'h1be == out_iindex_1 ? out_prepend_79 : _GEN_3479; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3481 = 9'h1bf == out_iindex_1 ? out_prepend_79 : _GEN_3480; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3482 = 9'h1c0 == out_iindex_1 ? out_prepend_79 : _GEN_3481; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3483 = 9'h1c1 == out_iindex_1 ? out_prepend_79 : _GEN_3482; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3484 = 9'h1c2 == out_iindex_1 ? out_prepend_79 : _GEN_3483; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3485 = 9'h1c3 == out_iindex_1 ? out_prepend_79 : _GEN_3484; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3486 = 9'h1c4 == out_iindex_1 ? out_prepend_79 : _GEN_3485; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3487 = 9'h1c5 == out_iindex_1 ? out_prepend_79 : _GEN_3486; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3488 = 9'h1c6 == out_iindex_1 ? out_prepend_79 : _GEN_3487; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3489 = 9'h1c7 == out_iindex_1 ? out_prepend_79 : _GEN_3488; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3490 = 9'h1c8 == out_iindex_1 ? out_prepend_79 : _GEN_3489; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3491 = 9'h1c9 == out_iindex_1 ? out_prepend_79 : _GEN_3490; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3492 = 9'h1ca == out_iindex_1 ? out_prepend_79 : _GEN_3491; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3493 = 9'h1cb == out_iindex_1 ? out_prepend_79 : _GEN_3492; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3494 = 9'h1cc == out_iindex_1 ? out_prepend_79 : _GEN_3493; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3495 = 9'h1cd == out_iindex_1 ? out_prepend_79 : _GEN_3494; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3496 = 9'h1ce == out_iindex_1 ? out_prepend_79 : _GEN_3495; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3497 = 9'h1cf == out_iindex_1 ? out_prepend_79 : _GEN_3496; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3498 = 9'h1d0 == out_iindex_1 ? out_prepend_79 : _GEN_3497; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3499 = 9'h1d1 == out_iindex_1 ? out_prepend_79 : _GEN_3498; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3500 = 9'h1d2 == out_iindex_1 ? out_prepend_79 : _GEN_3499; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3501 = 9'h1d3 == out_iindex_1 ? out_prepend_79 : _GEN_3500; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3502 = 9'h1d4 == out_iindex_1 ? out_prepend_79 : _GEN_3501; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3503 = 9'h1d5 == out_iindex_1 ? out_prepend_79 : _GEN_3502; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3504 = 9'h1d6 == out_iindex_1 ? out_prepend_79 : _GEN_3503; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3505 = 9'h1d7 == out_iindex_1 ? out_prepend_79 : _GEN_3504; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3506 = 9'h1d8 == out_iindex_1 ? out_prepend_79 : _GEN_3505; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3507 = 9'h1d9 == out_iindex_1 ? out_prepend_79 : _GEN_3506; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3508 = 9'h1da == out_iindex_1 ? out_prepend_79 : _GEN_3507; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3509 = 9'h1db == out_iindex_1 ? out_prepend_79 : _GEN_3508; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3510 = 9'h1dc == out_iindex_1 ? out_prepend_79 : _GEN_3509; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3511 = 9'h1dd == out_iindex_1 ? out_prepend_79 : _GEN_3510; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3512 = 9'h1de == out_iindex_1 ? out_prepend_79 : _GEN_3511; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3513 = 9'h1df == out_iindex_1 ? out_prepend_79 : _GEN_3512; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3514 = 9'h1e0 == out_iindex_1 ? out_prepend_79 : _GEN_3513; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3515 = 9'h1e1 == out_iindex_1 ? out_prepend_79 : _GEN_3514; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3516 = 9'h1e2 == out_iindex_1 ? out_prepend_79 : _GEN_3515; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3517 = 9'h1e3 == out_iindex_1 ? out_prepend_79 : _GEN_3516; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3518 = 9'h1e4 == out_iindex_1 ? out_prepend_79 : _GEN_3517; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3519 = 9'h1e5 == out_iindex_1 ? out_prepend_79 : _GEN_3518; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3520 = 9'h1e6 == out_iindex_1 ? out_prepend_79 : _GEN_3519; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3521 = 9'h1e7 == out_iindex_1 ? out_prepend_79 : _GEN_3520; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3522 = 9'h1e8 == out_iindex_1 ? out_prepend_79 : _GEN_3521; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3523 = 9'h1e9 == out_iindex_1 ? out_prepend_79 : _GEN_3522; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3524 = 9'h1ea == out_iindex_1 ? out_prepend_79 : _GEN_3523; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3525 = 9'h1eb == out_iindex_1 ? out_prepend_79 : _GEN_3524; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3526 = 9'h1ec == out_iindex_1 ? out_prepend_79 : _GEN_3525; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3527 = 9'h1ed == out_iindex_1 ? out_prepend_79 : _GEN_3526; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3528 = 9'h1ee == out_iindex_1 ? out_prepend_79 : _GEN_3527; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3529 = 9'h1ef == out_iindex_1 ? out_prepend_79 : _GEN_3528; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3530 = 9'h1f0 == out_iindex_1 ? out_prepend_79 : _GEN_3529; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3531 = 9'h1f1 == out_iindex_1 ? out_prepend_79 : _GEN_3530; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3532 = 9'h1f2 == out_iindex_1 ? out_prepend_79 : _GEN_3531; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3533 = 9'h1f3 == out_iindex_1 ? out_prepend_79 : _GEN_3532; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3534 = 9'h1f4 == out_iindex_1 ? out_prepend_79 : _GEN_3533; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3535 = 9'h1f5 == out_iindex_1 ? out_prepend_79 : _GEN_3534; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3536 = 9'h1f6 == out_iindex_1 ? out_prepend_79 : _GEN_3535; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3537 = 9'h1f7 == out_iindex_1 ? out_prepend_79 : _GEN_3536; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3538 = 9'h1f8 == out_iindex_1 ? out_prepend_79 : _GEN_3537; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3539 = 9'h1f9 == out_iindex_1 ? out_prepend_79 : _GEN_3538; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3540 = 9'h1fa == out_iindex_1 ? out_prepend_79 : _GEN_3539; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3541 = 9'h1fb == out_iindex_1 ? out_prepend_79 : _GEN_3540; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3542 = 9'h1fc == out_iindex_1 ? out_prepend_79 : _GEN_3541; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3543 = 9'h1fd == out_iindex_1 ? out_prepend_79 : _GEN_3542; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3544 = 9'h1fe == out_iindex_1 ? out_prepend_79 : _GEN_3543; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_3545 = 9'h1ff == out_iindex_1 ? out_prepend_79 : _GEN_3544; // @[MuxLiteral.scala 48:{10,10}]
  wire [1:0] _GEN_3627 = commandRegBadHaltResume ? 2'h0 : 2'h2; // @[Debug.scala 1691:43 1693:22]
  wire [1:0] _GEN_3633 = ~goReg & out_f_woready_647 ? 2'h0 : ctrlStateReg; // @[Debug.scala 1707:116 1708:22]
  wire [1:0] _GEN_3634 = out_f_woready_941 ? 2'h0 : _GEN_3633; // @[Debug.scala 1710:31 1712:24]
  wire  _T_1393 = ctrlStateReg == 2'h3; // @[Debug.scala 1715:30]
  wire  _GEN_3892 = _errorBusy_T & ~_T_1383; // @[Debug.scala 1711:15]
  TLMonitor_53 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  TLMonitor_54 monitor_1 ( // @[Nodes.scala 24:25]
    .clock(monitor_1_clock),
    .io_in_a_ready(monitor_1_io_in_a_ready),
    .io_in_a_valid(monitor_1_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_1_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_1_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_1_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_1_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_1_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_1_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_1_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_1_io_in_d_ready),
    .io_in_d_valid(monitor_1_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_1_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_1_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_1_io_in_d_bits_source)
  );
  AsyncResetSynchronizerShiftReg_w1_d3_i0 hartIsInResetSync_0_debug_hartReset_0 ( // @[ShiftReg.scala 45:23]
    .clock(hartIsInResetSync_0_debug_hartReset_0_clock),
    .reset(hartIsInResetSync_0_debug_hartReset_0_reset),
    .io_d(hartIsInResetSync_0_debug_hartReset_0_io_d),
    .io_q(hartIsInResetSync_0_debug_hartReset_0_io_q)
  );
  assign auto_tl_in_a_ready = auto_tl_in_d_ready; // @[RegisterRouter.scala 83:24]
  assign auto_tl_in_d_valid = auto_tl_in_a_valid; // @[RegisterRouter.scala 83:24]
  assign auto_tl_in_d_bits_opcode = {{2'd0}, in_1_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign auto_tl_in_d_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_tl_in_d_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_tl_in_d_bits_data = _GEN_3033 ? _GEN_3545 : 32'h0; // @[RegisterRouter.scala 83:24]
  assign auto_dmi_in_a_ready = auto_dmi_in_d_ready; // @[RegisterRouter.scala 83:24]
  assign auto_dmi_in_d_valid = auto_dmi_in_a_valid; // @[RegisterRouter.scala 83:24]
  assign auto_dmi_in_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign auto_dmi_in_d_bits_size = auto_dmi_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_dmi_in_d_bits_source = auto_dmi_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_dmi_in_d_bits_data = _GEN_296 ? _GEN_328 : 32'h0; // @[RegisterRouter.scala 83:24]
  assign io_innerCtrl_ready = 1'h1; // @[Debug.scala 836:24]
  assign io_hgDebugInt_0 = hrDebugIntReg_0; // @[package.scala 66:75]
  assign monitor_clock = clock;
  assign monitor_io_in_a_ready = auto_dmi_in_d_ready; // @[RegisterRouter.scala 83:24]
  assign monitor_io_in_a_valid = auto_dmi_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_dmi_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_dmi_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_dmi_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_dmi_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_dmi_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_dmi_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_dmi_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_dmi_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_dmi_in_a_valid; // @[RegisterRouter.scala 83:24]
  assign monitor_io_in_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign monitor_io_in_d_bits_size = auto_dmi_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_bits_source = auto_dmi_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_clock = clock;
  assign monitor_1_io_in_a_ready = auto_tl_in_d_ready; // @[RegisterRouter.scala 83:24]
  assign monitor_1_io_in_a_valid = auto_tl_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_a_bits_opcode = auto_tl_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_a_bits_param = auto_tl_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_a_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_a_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_a_bits_address = auto_tl_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_a_bits_mask = auto_tl_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_a_bits_corrupt = auto_tl_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_d_ready = auto_tl_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_d_valid = auto_tl_in_a_valid; // @[RegisterRouter.scala 83:24]
  assign monitor_1_io_in_d_bits_opcode = {{2'd0}, in_1_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign monitor_1_io_in_d_bits_size = auto_tl_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_1_io_in_d_bits_source = auto_tl_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign hartIsInResetSync_0_debug_hartReset_0_clock = clock;
  assign hartIsInResetSync_0_debug_hartReset_0_reset = 1'h0;
  assign hartIsInResetSync_0_debug_hartReset_0_io_d = 1'h0; // @[ShiftReg.scala 47:16]
  always @(posedge clock) begin
    haltedBitRegs <= _GEN_65[0];
    resumeReqRegs <= _GEN_66[0];
    if (_T_1) begin // @[Debug.scala 919:44]
      haveResetBitRegs <= 1'h0; // @[Debug.scala 920:24]
    end else if (_T_4 & io_innerCtrl_bits_ackhavereset) begin // @[Debug.scala 922:68]
      haveResetBitRegs <= haveResetBitRegs & _resumeAcks_T_1 | hartIsInResetSync_0; // @[Debug.scala 923:26]
    end else begin
      haveResetBitRegs <= haveResetBitRegs | hartIsInResetSync_0; // @[Debug.scala 925:26]
    end
    if (~io_dmactive) begin // @[Debug.scala 861:45]
      hrmaskReg_0 <= 1'h0; // @[Debug.scala 862:17]
    end else if (_T_4) begin // @[Debug.scala 863:37]
      hrmaskReg_0 <= io_innerCtrl_bits_hrmask_0; // @[Debug.scala 864:17]
    end
    if (_T_1) begin // @[Debug.scala 1102:45]
      ABSTRACTCSReg_cmderr <= 3'h0; // @[Debug.scala 1103:21]
    end else if (errorBusy) begin // @[Debug.scala 1105:23]
      ABSTRACTCSReg_cmderr <= 3'h1; // @[Debug.scala 1106:30]
    end else if (errorException) begin // @[Debug.scala 1107:35]
      ABSTRACTCSReg_cmderr <= 3'h3; // @[Debug.scala 1108:30]
    end else if (errorUnsupported) begin // @[Debug.scala 1109:37]
      ABSTRACTCSReg_cmderr <= 3'h2; // @[Debug.scala 1110:30]
    end else begin
      ABSTRACTCSReg_cmderr <= _GEN_38;
    end
    if (_T_1) begin // @[Debug.scala 1724:45]
      ctrlStateReg <= 2'h0; // @[Debug.scala 1725:20]
    end else if (ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1673:47]
      if (wrAccessRegisterCommand | regAccessRegisterCommand) begin // @[Debug.scala 1674:66]
        ctrlStateReg <= 2'h1; // @[Debug.scala 1675:22]
      end
    end else if (ctrlStateReg == 2'h1) begin // @[Debug.scala 1681:59]
      if (commandRegIsUnsupported) begin // @[Debug.scala 1688:38]
        ctrlStateReg <= 2'h0; // @[Debug.scala 1690:22]
      end else begin
        ctrlStateReg <= _GEN_3627;
      end
    end else if (ctrlStateReg == 2'h2) begin // @[Debug.scala 1702:51]
      ctrlStateReg <= _GEN_3634;
    end
    if (_T_1) begin // @[Debug.scala 1183:45]
      COMMANDRdData_cmdtype <= 8'h0; // @[Debug.scala 1184:18]
    end else if (COMMANDWrEn) begin // @[Debug.scala 1186:26]
      COMMANDRdData_cmdtype <= COMMANDWrData_cmdtype; // @[Debug.scala 1187:20]
    end
    if (_T_1) begin // @[Debug.scala 1183:45]
      COMMANDRdData_control <= 24'h0; // @[Debug.scala 1184:18]
    end else if (COMMANDWrEn) begin // @[Debug.scala 1186:26]
      COMMANDRdData_control <= COMMANDWrData_control; // @[Debug.scala 1187:20]
    end
    if (_T_1) begin // @[Debug.scala 1141:45]
      ABSTRACTAUTOReg_autoexecdata <= 12'h0; // @[Debug.scala 1142:23]
    end else if (out_f_woready_4 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1147:61]
      ABSTRACTAUTOReg_autoexecdata <= _ABSTRACTAUTOReg_autoexecdata_T; // @[Debug.scala 1148:38]
    end
    if (_T_1) begin // @[Debug.scala 1141:45]
      ABSTRACTAUTOReg_autoexecprogbuf <= 16'h0; // @[Debug.scala 1142:23]
    end else if (out_f_woready_6 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1144:64]
      ABSTRACTAUTOReg_autoexecprogbuf <= ABSTRACTAUTOWrData_autoexecprogbuf; // @[Debug.scala 1145:41]
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      abstractDataMem_0 <= 8'h0; // @[Debug.scala 1597:40]
    end else if (out_f_wivalid_503) begin // @[RegField.scala 74:88]
      abstractDataMem_0 <= auto_tl_in_a_bits_data[7:0]; // @[RegField.scala 74:92]
    end else if (out_f_woready_92 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1348:91]
      if (out_f_woready_92) begin // @[Debug.scala 265:24]
        abstractDataMem_0 <= auto_dmi_in_a_bits_data[7:0]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      abstractDataMem_1 <= 8'h0; // @[Debug.scala 1597:40]
    end else if (out_f_wivalid_504) begin // @[RegField.scala 74:88]
      abstractDataMem_1 <= auto_tl_in_a_bits_data[15:8]; // @[RegField.scala 74:92]
    end else if (out_f_woready_93 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1348:91]
      if (out_f_woready_93) begin // @[Debug.scala 265:24]
        abstractDataMem_1 <= auto_dmi_in_a_bits_data[15:8]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      abstractDataMem_2 <= 8'h0; // @[Debug.scala 1597:40]
    end else if (out_f_wivalid_505) begin // @[RegField.scala 74:88]
      abstractDataMem_2 <= auto_tl_in_a_bits_data[23:16]; // @[RegField.scala 74:92]
    end else if (out_f_woready_94 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1348:91]
      if (out_f_woready_94) begin // @[Debug.scala 265:24]
        abstractDataMem_2 <= auto_dmi_in_a_bits_data[23:16]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      abstractDataMem_3 <= 8'h0; // @[Debug.scala 1597:40]
    end else if (out_f_wivalid_506) begin // @[RegField.scala 74:88]
      abstractDataMem_3 <= auto_tl_in_a_bits_data[31:24]; // @[RegField.scala 74:92]
    end else if (out_f_woready_95 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1348:91]
      if (out_f_woready_95) begin // @[Debug.scala 265:24]
        abstractDataMem_3 <= auto_dmi_in_a_bits_data[31:24]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_0 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_768) begin // @[RegField.scala 74:88]
      programBufferMem_0 <= auto_tl_in_a_bits_data[7:0]; // @[RegField.scala 74:92]
    end else if (out_f_woready_27 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_27) begin // @[Debug.scala 265:24]
        programBufferMem_0 <= auto_dmi_in_a_bits_data[7:0]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_1 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_769) begin // @[RegField.scala 74:88]
      programBufferMem_1 <= auto_tl_in_a_bits_data[15:8]; // @[RegField.scala 74:92]
    end else if (out_f_woready_28 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_28) begin // @[Debug.scala 265:24]
        programBufferMem_1 <= auto_dmi_in_a_bits_data[15:8]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_2 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_770) begin // @[RegField.scala 74:88]
      programBufferMem_2 <= auto_tl_in_a_bits_data[23:16]; // @[RegField.scala 74:92]
    end else if (out_f_woready_29 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_29) begin // @[Debug.scala 265:24]
        programBufferMem_2 <= auto_dmi_in_a_bits_data[23:16]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_3 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_771) begin // @[RegField.scala 74:88]
      programBufferMem_3 <= auto_tl_in_a_bits_data[31:24]; // @[RegField.scala 74:92]
    end else if (out_f_woready_30 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_30) begin // @[Debug.scala 265:24]
        programBufferMem_3 <= auto_dmi_in_a_bits_data[31:24]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_4 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_885) begin // @[RegField.scala 74:88]
      programBufferMem_4 <= auto_tl_in_a_bits_data[7:0]; // @[RegField.scala 74:92]
    end else if (out_f_woready_19 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_19) begin // @[Debug.scala 265:24]
        programBufferMem_4 <= auto_dmi_in_a_bits_data[7:0]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_5 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_886) begin // @[RegField.scala 74:88]
      programBufferMem_5 <= auto_tl_in_a_bits_data[15:8]; // @[RegField.scala 74:92]
    end else if (out_f_woready_20 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_20) begin // @[Debug.scala 265:24]
        programBufferMem_5 <= auto_dmi_in_a_bits_data[15:8]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_6 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_887) begin // @[RegField.scala 74:88]
      programBufferMem_6 <= auto_tl_in_a_bits_data[23:16]; // @[RegField.scala 74:92]
    end else if (out_f_woready_21 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_21) begin // @[Debug.scala 265:24]
        programBufferMem_6 <= auto_dmi_in_a_bits_data[23:16]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_7 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_888) begin // @[RegField.scala 74:88]
      programBufferMem_7 <= auto_tl_in_a_bits_data[31:24]; // @[RegField.scala 74:92]
    end else if (out_f_woready_22 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_22) begin // @[Debug.scala 265:24]
        programBufferMem_7 <= auto_dmi_in_a_bits_data[31:24]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_8 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_1143) begin // @[RegField.scala 74:88]
      programBufferMem_8 <= auto_tl_in_a_bits_data[7:0]; // @[RegField.scala 74:92]
    end else if (out_f_woready_31 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_31) begin // @[Debug.scala 265:24]
        programBufferMem_8 <= auto_dmi_in_a_bits_data[7:0]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_9 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_1144) begin // @[RegField.scala 74:88]
      programBufferMem_9 <= auto_tl_in_a_bits_data[15:8]; // @[RegField.scala 74:92]
    end else if (out_f_woready_32 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_32) begin // @[Debug.scala 265:24]
        programBufferMem_9 <= auto_dmi_in_a_bits_data[15:8]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_10 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_1145) begin // @[RegField.scala 74:88]
      programBufferMem_10 <= auto_tl_in_a_bits_data[23:16]; // @[RegField.scala 74:92]
    end else if (out_f_woready_33 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_33) begin // @[Debug.scala 265:24]
        programBufferMem_10 <= auto_dmi_in_a_bits_data[23:16]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_11 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_1146) begin // @[RegField.scala 74:88]
      programBufferMem_11 <= auto_tl_in_a_bits_data[31:24]; // @[RegField.scala 74:92]
    end else if (out_f_woready_34 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_34) begin // @[Debug.scala 265:24]
        programBufferMem_11 <= auto_dmi_in_a_bits_data[31:24]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_12 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_300) begin // @[RegField.scala 74:88]
      programBufferMem_12 <= auto_tl_in_a_bits_data[7:0]; // @[RegField.scala 74:92]
    end else if (out_f_woready_74 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_74) begin // @[Debug.scala 265:24]
        programBufferMem_12 <= auto_dmi_in_a_bits_data[7:0]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_13 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_301) begin // @[RegField.scala 74:88]
      programBufferMem_13 <= auto_tl_in_a_bits_data[15:8]; // @[RegField.scala 74:92]
    end else if (out_f_woready_75 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_75) begin // @[Debug.scala 265:24]
        programBufferMem_13 <= auto_dmi_in_a_bits_data[15:8]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_14 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_302) begin // @[RegField.scala 74:88]
      programBufferMem_14 <= auto_tl_in_a_bits_data[23:16]; // @[RegField.scala 74:92]
    end else if (out_f_woready_76 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_76) begin // @[Debug.scala 265:24]
        programBufferMem_14 <= auto_dmi_in_a_bits_data[23:16]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_15 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_303) begin // @[RegField.scala 74:88]
      programBufferMem_15 <= auto_tl_in_a_bits_data[31:24]; // @[RegField.scala 74:92]
    end else if (out_f_woready_77 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_77) begin // @[Debug.scala 265:24]
        programBufferMem_15 <= auto_dmi_in_a_bits_data[31:24]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_16 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_567) begin // @[RegField.scala 74:88]
      programBufferMem_16 <= auto_tl_in_a_bits_data[7:0]; // @[RegField.scala 74:92]
    end else if (out_f_woready_87 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_87) begin // @[Debug.scala 265:24]
        programBufferMem_16 <= auto_dmi_in_a_bits_data[7:0]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_17 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_568) begin // @[RegField.scala 74:88]
      programBufferMem_17 <= auto_tl_in_a_bits_data[15:8]; // @[RegField.scala 74:92]
    end else if (out_f_woready_88 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_88) begin // @[Debug.scala 265:24]
        programBufferMem_17 <= auto_dmi_in_a_bits_data[15:8]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_18 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_569) begin // @[RegField.scala 74:88]
      programBufferMem_18 <= auto_tl_in_a_bits_data[23:16]; // @[RegField.scala 74:92]
    end else if (out_f_woready_89 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_89) begin // @[Debug.scala 265:24]
        programBufferMem_18 <= auto_dmi_in_a_bits_data[23:16]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_19 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_570) begin // @[RegField.scala 74:88]
      programBufferMem_19 <= auto_tl_in_a_bits_data[31:24]; // @[RegField.scala 74:92]
    end else if (out_f_woready_90 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_90) begin // @[Debug.scala 265:24]
        programBufferMem_19 <= auto_dmi_in_a_bits_data[31:24]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_20 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_796) begin // @[RegField.scala 74:88]
      programBufferMem_20 <= auto_tl_in_a_bits_data[7:0]; // @[RegField.scala 74:92]
    end else if (out_f_woready_7 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_7) begin // @[Debug.scala 265:24]
        programBufferMem_20 <= auto_dmi_in_a_bits_data[7:0]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_21 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_797) begin // @[RegField.scala 74:88]
      programBufferMem_21 <= auto_tl_in_a_bits_data[15:8]; // @[RegField.scala 74:92]
    end else if (out_f_woready_8 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_8) begin // @[Debug.scala 265:24]
        programBufferMem_21 <= auto_dmi_in_a_bits_data[15:8]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_22 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_798) begin // @[RegField.scala 74:88]
      programBufferMem_22 <= auto_tl_in_a_bits_data[23:16]; // @[RegField.scala 74:92]
    end else if (out_f_woready_9 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_9) begin // @[Debug.scala 265:24]
        programBufferMem_22 <= auto_dmi_in_a_bits_data[23:16]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_23 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_799) begin // @[RegField.scala 74:88]
      programBufferMem_23 <= auto_tl_in_a_bits_data[31:24]; // @[RegField.scala 74:92]
    end else if (out_f_woready_10 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_10) begin // @[Debug.scala 265:24]
        programBufferMem_23 <= auto_dmi_in_a_bits_data[31:24]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_24 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_1091) begin // @[RegField.scala 74:88]
      programBufferMem_24 <= auto_tl_in_a_bits_data[7:0]; // @[RegField.scala 74:92]
    end else if (out_f_woready_15 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_15) begin // @[Debug.scala 265:24]
        programBufferMem_24 <= auto_dmi_in_a_bits_data[7:0]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_25 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_1092) begin // @[RegField.scala 74:88]
      programBufferMem_25 <= auto_tl_in_a_bits_data[15:8]; // @[RegField.scala 74:92]
    end else if (out_f_woready_16 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_16) begin // @[Debug.scala 265:24]
        programBufferMem_25 <= auto_dmi_in_a_bits_data[15:8]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_26 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_1093) begin // @[RegField.scala 74:88]
      programBufferMem_26 <= auto_tl_in_a_bits_data[23:16]; // @[RegField.scala 74:92]
    end else if (out_f_woready_17 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_17) begin // @[Debug.scala 265:24]
        programBufferMem_26 <= auto_dmi_in_a_bits_data[23:16]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_27 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_1094) begin // @[RegField.scala 74:88]
      programBufferMem_27 <= auto_tl_in_a_bits_data[31:24]; // @[RegField.scala 74:92]
    end else if (out_f_woready_18 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_18) begin // @[Debug.scala 265:24]
        programBufferMem_27 <= auto_dmi_in_a_bits_data[31:24]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_28 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_1259) begin // @[RegField.scala 74:88]
      programBufferMem_28 <= auto_tl_in_a_bits_data[7:0]; // @[RegField.scala 74:92]
    end else if (out_f_woready_70 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_70) begin // @[Debug.scala 265:24]
        programBufferMem_28 <= auto_dmi_in_a_bits_data[7:0]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_29 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_1260) begin // @[RegField.scala 74:88]
      programBufferMem_29 <= auto_tl_in_a_bits_data[15:8]; // @[RegField.scala 74:92]
    end else if (out_f_woready_71 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_71) begin // @[Debug.scala 265:24]
        programBufferMem_29 <= auto_dmi_in_a_bits_data[15:8]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_30 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_1261) begin // @[RegField.scala 74:88]
      programBufferMem_30 <= auto_tl_in_a_bits_data[23:16]; // @[RegField.scala 74:92]
    end else if (out_f_woready_72 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_72) begin // @[Debug.scala 265:24]
        programBufferMem_30 <= auto_dmi_in_a_bits_data[23:16]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_31 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_1262) begin // @[RegField.scala 74:88]
      programBufferMem_31 <= auto_tl_in_a_bits_data[31:24]; // @[RegField.scala 74:92]
    end else if (out_f_woready_73 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_73) begin // @[Debug.scala 265:24]
        programBufferMem_31 <= auto_dmi_in_a_bits_data[31:24]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_32 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_276) begin // @[RegField.scala 74:88]
      programBufferMem_32 <= auto_tl_in_a_bits_data[7:0]; // @[RegField.scala 74:92]
    end else if (out_f_woready_82 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_82) begin // @[Debug.scala 265:24]
        programBufferMem_32 <= auto_dmi_in_a_bits_data[7:0]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_33 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_277) begin // @[RegField.scala 74:88]
      programBufferMem_33 <= auto_tl_in_a_bits_data[15:8]; // @[RegField.scala 74:92]
    end else if (out_f_woready_83 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_83) begin // @[Debug.scala 265:24]
        programBufferMem_33 <= auto_dmi_in_a_bits_data[15:8]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_34 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_278) begin // @[RegField.scala 74:88]
      programBufferMem_34 <= auto_tl_in_a_bits_data[23:16]; // @[RegField.scala 74:92]
    end else if (out_f_woready_84 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_84) begin // @[Debug.scala 265:24]
        programBufferMem_34 <= auto_dmi_in_a_bits_data[23:16]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_35 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_279) begin // @[RegField.scala 74:88]
      programBufferMem_35 <= auto_tl_in_a_bits_data[31:24]; // @[RegField.scala 74:92]
    end else if (out_f_woready_85 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_85) begin // @[Debug.scala 265:24]
        programBufferMem_35 <= auto_dmi_in_a_bits_data[31:24]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_36 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_140) begin // @[RegField.scala 74:88]
      programBufferMem_36 <= auto_tl_in_a_bits_data[7:0]; // @[RegField.scala 74:92]
    end else if (out_f_woready_23 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_23) begin // @[Debug.scala 265:24]
        programBufferMem_36 <= auto_dmi_in_a_bits_data[7:0]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_37 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_141) begin // @[RegField.scala 74:88]
      programBufferMem_37 <= auto_tl_in_a_bits_data[15:8]; // @[RegField.scala 74:92]
    end else if (out_f_woready_24 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_24) begin // @[Debug.scala 265:24]
        programBufferMem_37 <= auto_dmi_in_a_bits_data[15:8]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_38 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_142) begin // @[RegField.scala 74:88]
      programBufferMem_38 <= auto_tl_in_a_bits_data[23:16]; // @[RegField.scala 74:92]
    end else if (out_f_woready_25 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_25) begin // @[Debug.scala 265:24]
        programBufferMem_38 <= auto_dmi_in_a_bits_data[23:16]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_39 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_143) begin // @[RegField.scala 74:88]
      programBufferMem_39 <= auto_tl_in_a_bits_data[31:24]; // @[RegField.scala 74:92]
    end else if (out_f_woready_26 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_26) begin // @[Debug.scala 265:24]
        programBufferMem_39 <= auto_dmi_in_a_bits_data[31:24]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_40 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_1018) begin // @[RegField.scala 74:88]
      programBufferMem_40 <= auto_tl_in_a_bits_data[7:0]; // @[RegField.scala 74:92]
    end else if (out_f_woready & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready) begin // @[Debug.scala 265:24]
        programBufferMem_40 <= auto_dmi_in_a_bits_data[7:0]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_41 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_1019) begin // @[RegField.scala 74:88]
      programBufferMem_41 <= auto_tl_in_a_bits_data[15:8]; // @[RegField.scala 74:92]
    end else if (out_f_woready_1 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_1) begin // @[Debug.scala 265:24]
        programBufferMem_41 <= auto_dmi_in_a_bits_data[15:8]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_42 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_1020) begin // @[RegField.scala 74:88]
      programBufferMem_42 <= auto_tl_in_a_bits_data[23:16]; // @[RegField.scala 74:92]
    end else if (out_f_woready_2 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_2) begin // @[Debug.scala 265:24]
        programBufferMem_42 <= auto_dmi_in_a_bits_data[23:16]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_43 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_1021) begin // @[RegField.scala 74:88]
      programBufferMem_43 <= auto_tl_in_a_bits_data[31:24]; // @[RegField.scala 74:92]
    end else if (out_f_woready_3 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_3) begin // @[Debug.scala 265:24]
        programBufferMem_43 <= auto_dmi_in_a_bits_data[31:24]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_44 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_724) begin // @[RegField.scala 74:88]
      programBufferMem_44 <= auto_tl_in_a_bits_data[7:0]; // @[RegField.scala 74:92]
    end else if (out_f_woready_78 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_78) begin // @[Debug.scala 265:24]
        programBufferMem_44 <= auto_dmi_in_a_bits_data[7:0]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_45 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_725) begin // @[RegField.scala 74:88]
      programBufferMem_45 <= auto_tl_in_a_bits_data[15:8]; // @[RegField.scala 74:92]
    end else if (out_f_woready_79 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_79) begin // @[Debug.scala 265:24]
        programBufferMem_45 <= auto_dmi_in_a_bits_data[15:8]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_46 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_726) begin // @[RegField.scala 74:88]
      programBufferMem_46 <= auto_tl_in_a_bits_data[23:16]; // @[RegField.scala 74:92]
    end else if (out_f_woready_80 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_80) begin // @[Debug.scala 265:24]
        programBufferMem_46 <= auto_dmi_in_a_bits_data[23:16]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_47 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_727) begin // @[RegField.scala 74:88]
      programBufferMem_47 <= auto_tl_in_a_bits_data[31:24]; // @[RegField.scala 74:92]
    end else if (out_f_woready_81 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_81) begin // @[Debug.scala 265:24]
        programBufferMem_47 <= auto_dmi_in_a_bits_data[31:24]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_48 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_409) begin // @[RegField.scala 74:88]
      programBufferMem_48 <= auto_tl_in_a_bits_data[7:0]; // @[RegField.scala 74:92]
    end else if (out_f_woready_66 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_66) begin // @[Debug.scala 265:24]
        programBufferMem_48 <= auto_dmi_in_a_bits_data[7:0]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_49 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_410) begin // @[RegField.scala 74:88]
      programBufferMem_49 <= auto_tl_in_a_bits_data[15:8]; // @[RegField.scala 74:92]
    end else if (out_f_woready_67 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_67) begin // @[Debug.scala 265:24]
        programBufferMem_49 <= auto_dmi_in_a_bits_data[15:8]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_50 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_411) begin // @[RegField.scala 74:88]
      programBufferMem_50 <= auto_tl_in_a_bits_data[23:16]; // @[RegField.scala 74:92]
    end else if (out_f_woready_68 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_68) begin // @[Debug.scala 265:24]
        programBufferMem_50 <= auto_dmi_in_a_bits_data[23:16]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_51 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_412) begin // @[RegField.scala 74:88]
      programBufferMem_51 <= auto_tl_in_a_bits_data[31:24]; // @[RegField.scala 74:92]
    end else if (out_f_woready_69 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_69) begin // @[Debug.scala 265:24]
        programBufferMem_51 <= auto_dmi_in_a_bits_data[31:24]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_52 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_332) begin // @[RegField.scala 74:88]
      programBufferMem_52 <= auto_tl_in_a_bits_data[7:0]; // @[RegField.scala 74:92]
    end else if (out_f_woready_35 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_35) begin // @[Debug.scala 265:24]
        programBufferMem_52 <= auto_dmi_in_a_bits_data[7:0]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_53 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_333) begin // @[RegField.scala 74:88]
      programBufferMem_53 <= auto_tl_in_a_bits_data[15:8]; // @[RegField.scala 74:92]
    end else if (out_f_woready_36 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_36) begin // @[Debug.scala 265:24]
        programBufferMem_53 <= auto_dmi_in_a_bits_data[15:8]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_54 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_334) begin // @[RegField.scala 74:88]
      programBufferMem_54 <= auto_tl_in_a_bits_data[23:16]; // @[RegField.scala 74:92]
    end else if (out_f_woready_37 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_37) begin // @[Debug.scala 265:24]
        programBufferMem_54 <= auto_dmi_in_a_bits_data[23:16]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_55 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_335) begin // @[RegField.scala 74:88]
      programBufferMem_55 <= auto_tl_in_a_bits_data[31:24]; // @[RegField.scala 74:92]
    end else if (out_f_woready_38 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_38) begin // @[Debug.scala 265:24]
        programBufferMem_55 <= auto_dmi_in_a_bits_data[31:24]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_56 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_1267) begin // @[RegField.scala 74:88]
      programBufferMem_56 <= auto_tl_in_a_bits_data[7:0]; // @[RegField.scala 74:92]
    end else if (out_f_woready_11 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_11) begin // @[Debug.scala 265:24]
        programBufferMem_56 <= auto_dmi_in_a_bits_data[7:0]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_57 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_1268) begin // @[RegField.scala 74:88]
      programBufferMem_57 <= auto_tl_in_a_bits_data[15:8]; // @[RegField.scala 74:92]
    end else if (out_f_woready_12 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_12) begin // @[Debug.scala 265:24]
        programBufferMem_57 <= auto_dmi_in_a_bits_data[15:8]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_58 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_1269) begin // @[RegField.scala 74:88]
      programBufferMem_58 <= auto_tl_in_a_bits_data[23:16]; // @[RegField.scala 74:92]
    end else if (out_f_woready_13 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_13) begin // @[Debug.scala 265:24]
        programBufferMem_58 <= auto_dmi_in_a_bits_data[23:16]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_59 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_1270) begin // @[RegField.scala 74:88]
      programBufferMem_59 <= auto_tl_in_a_bits_data[31:24]; // @[RegField.scala 74:92]
    end else if (out_f_woready_14 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_14) begin // @[Debug.scala 265:24]
        programBufferMem_59 <= auto_dmi_in_a_bits_data[31:24]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_60 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_833) begin // @[RegField.scala 74:88]
      programBufferMem_60 <= auto_tl_in_a_bits_data[7:0]; // @[RegField.scala 74:92]
    end else if (out_f_woready_96 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_96) begin // @[Debug.scala 265:24]
        programBufferMem_60 <= auto_dmi_in_a_bits_data[7:0]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_61 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_834) begin // @[RegField.scala 74:88]
      programBufferMem_61 <= auto_tl_in_a_bits_data[15:8]; // @[RegField.scala 74:92]
    end else if (out_f_woready_97 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_97) begin // @[Debug.scala 265:24]
        programBufferMem_61 <= auto_dmi_in_a_bits_data[15:8]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_62 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_835) begin // @[RegField.scala 74:88]
      programBufferMem_62 <= auto_tl_in_a_bits_data[23:16]; // @[RegField.scala 74:92]
    end else if (out_f_woready_98 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_98) begin // @[Debug.scala 265:24]
        programBufferMem_62 <= auto_dmi_in_a_bits_data[23:16]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1596:24]
      programBufferMem_63 <= 8'h0; // @[Debug.scala 1598:40]
    end else if (out_f_wivalid_836) begin // @[RegField.scala 74:88]
      programBufferMem_63 <= auto_tl_in_a_bits_data[31:24]; // @[RegField.scala 74:92]
    end else if (out_f_woready_99 & ABSTRACTCSWrEnLegal) begin // @[Debug.scala 1370:93]
      if (out_f_woready_99) begin // @[Debug.scala 265:24]
        programBufferMem_63 <= auto_dmi_in_a_bits_data[31:24]; // @[Debug.scala 265:30]
      end
    end
    if (_T_1) begin // @[Debug.scala 1385:24]
      goReg <= 1'h0; // @[Debug.scala 1386:13]
    end else begin
      goReg <= _GEN_398;
    end
    if (goAbstract) begin // @[Debug.scala 1520:23]
      if (accessRegisterCommandReg_transfer) begin // @[Debug.scala 1524:39]
        if (accessRegisterCommandReg_write) begin // @[Debug.scala 1525:14]
          abstractGeneratedMem_0 <= _abstractGeneratedMem_0_T;
        end else begin
          abstractGeneratedMem_0 <= _abstractGeneratedMem_0_T_1;
        end
      end else begin
        abstractGeneratedMem_0 <= 32'h13;
      end
    end
    if (goAbstract) begin // @[Debug.scala 1520:23]
      if (accessRegisterCommandReg_postexec) begin // @[Debug.scala 1528:39]
        abstractGeneratedMem_1 <= 32'h13;
      end else begin
        abstractGeneratedMem_1 <= 32'h100073;
      end
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(hartGoingId == 10'h0) & (~_T_1 & ~goAbstract & out_f_woready_470)) begin
          $fatal; // @[Debug.scala 1391:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~_T_1 & ~goAbstract & out_f_woready_470 & ~(hartGoingId == 10'h0)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Unexpected 'GOING' hart.\n    at Debug.scala:1391 assert(hartGoingId === 0.U, \"Unexpected 'GOING' hart.\")//Chisel3 #540 %%x, expected %%x\", hartGoingId, 0.U)\n"
            ); // @[Debug.scala 1391:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_342 & (_errorBusy_T & ~_T_1383 & _T_1384 & out_f_woready_941)) begin
          $fatal; // @[Debug.scala 1711:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_errorBusy_T & ~_T_1383 & _T_1384 & out_f_woready_941 & _T_342) begin
          $fwrite(32'h80000002,
            "Assertion failed: Unexpected 'EXCEPTION' hart\n    at Debug.scala:1711 assert(hartExceptionId === 0.U, \"Unexpected 'EXCEPTION' hart\")//Chisel3 #540, %%x, expected %%x\", hartExceptionId, 0.U)\n"
            ); // @[Debug.scala 1711:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_GEN_3892 & ~_T_1384 & _T_1393) begin
          $fatal; // @[Debug.scala 1716:13]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_GEN_3892 & ~_T_1384 & _T_1393) begin
          $fwrite(32'h80000002,
            "Assertion failed: Should not be in custom state unless we need it.\n    at Debug.scala:1716 assert(needCustom.B, \"Should not be in custom state unless we need it.\")\n"
            ); // @[Debug.scala 1716:13]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_T_1 | ~out_f_woready_941 | _T_1384)) begin
          $fatal; // @[Debug.scala 1729:12]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~(_T_1 | ~out_f_woready_941 | _T_1384)) begin
          $fwrite(32'h80000002,
            "Assertion failed: Unexpected EXCEPTION write: should only get it in Debug Module EXEC state\n    at Debug.scala:1729 assert ((!io.dmactive || !hartExceptionWrEn || ctrlStateReg === CtrlState(Exec)),\n"
            ); // @[Debug.scala 1729:12]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge clock or posedge _GEN_0) begin
    if (_GEN_0) begin // @[Debug.scala 869:47]
      hrDebugIntReg_0 <= 1'h0; // @[Debug.scala 870:23]
    end else if (_T_1) begin // @[Debug.scala 872:23]
      hrDebugIntReg_0 <= 1'h0;
    end else begin
      hrDebugIntReg_0 <= _T_13;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  haltedBitRegs = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  resumeReqRegs = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  haveResetBitRegs = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  hrmaskReg_0 = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  hrDebugIntReg_0 = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  ABSTRACTCSReg_cmderr = _RAND_5[2:0];
  _RAND_6 = {1{`RANDOM}};
  ctrlStateReg = _RAND_6[1:0];
  _RAND_7 = {1{`RANDOM}};
  COMMANDRdData_cmdtype = _RAND_7[7:0];
  _RAND_8 = {1{`RANDOM}};
  COMMANDRdData_control = _RAND_8[23:0];
  _RAND_9 = {1{`RANDOM}};
  ABSTRACTAUTOReg_autoexecdata = _RAND_9[11:0];
  _RAND_10 = {1{`RANDOM}};
  ABSTRACTAUTOReg_autoexecprogbuf = _RAND_10[15:0];
  _RAND_11 = {1{`RANDOM}};
  abstractDataMem_0 = _RAND_11[7:0];
  _RAND_12 = {1{`RANDOM}};
  abstractDataMem_1 = _RAND_12[7:0];
  _RAND_13 = {1{`RANDOM}};
  abstractDataMem_2 = _RAND_13[7:0];
  _RAND_14 = {1{`RANDOM}};
  abstractDataMem_3 = _RAND_14[7:0];
  _RAND_15 = {1{`RANDOM}};
  programBufferMem_0 = _RAND_15[7:0];
  _RAND_16 = {1{`RANDOM}};
  programBufferMem_1 = _RAND_16[7:0];
  _RAND_17 = {1{`RANDOM}};
  programBufferMem_2 = _RAND_17[7:0];
  _RAND_18 = {1{`RANDOM}};
  programBufferMem_3 = _RAND_18[7:0];
  _RAND_19 = {1{`RANDOM}};
  programBufferMem_4 = _RAND_19[7:0];
  _RAND_20 = {1{`RANDOM}};
  programBufferMem_5 = _RAND_20[7:0];
  _RAND_21 = {1{`RANDOM}};
  programBufferMem_6 = _RAND_21[7:0];
  _RAND_22 = {1{`RANDOM}};
  programBufferMem_7 = _RAND_22[7:0];
  _RAND_23 = {1{`RANDOM}};
  programBufferMem_8 = _RAND_23[7:0];
  _RAND_24 = {1{`RANDOM}};
  programBufferMem_9 = _RAND_24[7:0];
  _RAND_25 = {1{`RANDOM}};
  programBufferMem_10 = _RAND_25[7:0];
  _RAND_26 = {1{`RANDOM}};
  programBufferMem_11 = _RAND_26[7:0];
  _RAND_27 = {1{`RANDOM}};
  programBufferMem_12 = _RAND_27[7:0];
  _RAND_28 = {1{`RANDOM}};
  programBufferMem_13 = _RAND_28[7:0];
  _RAND_29 = {1{`RANDOM}};
  programBufferMem_14 = _RAND_29[7:0];
  _RAND_30 = {1{`RANDOM}};
  programBufferMem_15 = _RAND_30[7:0];
  _RAND_31 = {1{`RANDOM}};
  programBufferMem_16 = _RAND_31[7:0];
  _RAND_32 = {1{`RANDOM}};
  programBufferMem_17 = _RAND_32[7:0];
  _RAND_33 = {1{`RANDOM}};
  programBufferMem_18 = _RAND_33[7:0];
  _RAND_34 = {1{`RANDOM}};
  programBufferMem_19 = _RAND_34[7:0];
  _RAND_35 = {1{`RANDOM}};
  programBufferMem_20 = _RAND_35[7:0];
  _RAND_36 = {1{`RANDOM}};
  programBufferMem_21 = _RAND_36[7:0];
  _RAND_37 = {1{`RANDOM}};
  programBufferMem_22 = _RAND_37[7:0];
  _RAND_38 = {1{`RANDOM}};
  programBufferMem_23 = _RAND_38[7:0];
  _RAND_39 = {1{`RANDOM}};
  programBufferMem_24 = _RAND_39[7:0];
  _RAND_40 = {1{`RANDOM}};
  programBufferMem_25 = _RAND_40[7:0];
  _RAND_41 = {1{`RANDOM}};
  programBufferMem_26 = _RAND_41[7:0];
  _RAND_42 = {1{`RANDOM}};
  programBufferMem_27 = _RAND_42[7:0];
  _RAND_43 = {1{`RANDOM}};
  programBufferMem_28 = _RAND_43[7:0];
  _RAND_44 = {1{`RANDOM}};
  programBufferMem_29 = _RAND_44[7:0];
  _RAND_45 = {1{`RANDOM}};
  programBufferMem_30 = _RAND_45[7:0];
  _RAND_46 = {1{`RANDOM}};
  programBufferMem_31 = _RAND_46[7:0];
  _RAND_47 = {1{`RANDOM}};
  programBufferMem_32 = _RAND_47[7:0];
  _RAND_48 = {1{`RANDOM}};
  programBufferMem_33 = _RAND_48[7:0];
  _RAND_49 = {1{`RANDOM}};
  programBufferMem_34 = _RAND_49[7:0];
  _RAND_50 = {1{`RANDOM}};
  programBufferMem_35 = _RAND_50[7:0];
  _RAND_51 = {1{`RANDOM}};
  programBufferMem_36 = _RAND_51[7:0];
  _RAND_52 = {1{`RANDOM}};
  programBufferMem_37 = _RAND_52[7:0];
  _RAND_53 = {1{`RANDOM}};
  programBufferMem_38 = _RAND_53[7:0];
  _RAND_54 = {1{`RANDOM}};
  programBufferMem_39 = _RAND_54[7:0];
  _RAND_55 = {1{`RANDOM}};
  programBufferMem_40 = _RAND_55[7:0];
  _RAND_56 = {1{`RANDOM}};
  programBufferMem_41 = _RAND_56[7:0];
  _RAND_57 = {1{`RANDOM}};
  programBufferMem_42 = _RAND_57[7:0];
  _RAND_58 = {1{`RANDOM}};
  programBufferMem_43 = _RAND_58[7:0];
  _RAND_59 = {1{`RANDOM}};
  programBufferMem_44 = _RAND_59[7:0];
  _RAND_60 = {1{`RANDOM}};
  programBufferMem_45 = _RAND_60[7:0];
  _RAND_61 = {1{`RANDOM}};
  programBufferMem_46 = _RAND_61[7:0];
  _RAND_62 = {1{`RANDOM}};
  programBufferMem_47 = _RAND_62[7:0];
  _RAND_63 = {1{`RANDOM}};
  programBufferMem_48 = _RAND_63[7:0];
  _RAND_64 = {1{`RANDOM}};
  programBufferMem_49 = _RAND_64[7:0];
  _RAND_65 = {1{`RANDOM}};
  programBufferMem_50 = _RAND_65[7:0];
  _RAND_66 = {1{`RANDOM}};
  programBufferMem_51 = _RAND_66[7:0];
  _RAND_67 = {1{`RANDOM}};
  programBufferMem_52 = _RAND_67[7:0];
  _RAND_68 = {1{`RANDOM}};
  programBufferMem_53 = _RAND_68[7:0];
  _RAND_69 = {1{`RANDOM}};
  programBufferMem_54 = _RAND_69[7:0];
  _RAND_70 = {1{`RANDOM}};
  programBufferMem_55 = _RAND_70[7:0];
  _RAND_71 = {1{`RANDOM}};
  programBufferMem_56 = _RAND_71[7:0];
  _RAND_72 = {1{`RANDOM}};
  programBufferMem_57 = _RAND_72[7:0];
  _RAND_73 = {1{`RANDOM}};
  programBufferMem_58 = _RAND_73[7:0];
  _RAND_74 = {1{`RANDOM}};
  programBufferMem_59 = _RAND_74[7:0];
  _RAND_75 = {1{`RANDOM}};
  programBufferMem_60 = _RAND_75[7:0];
  _RAND_76 = {1{`RANDOM}};
  programBufferMem_61 = _RAND_76[7:0];
  _RAND_77 = {1{`RANDOM}};
  programBufferMem_62 = _RAND_77[7:0];
  _RAND_78 = {1{`RANDOM}};
  programBufferMem_63 = _RAND_78[7:0];
  _RAND_79 = {1{`RANDOM}};
  goReg = _RAND_79[0:0];
  _RAND_80 = {1{`RANDOM}};
  abstractGeneratedMem_0 = _RAND_80[31:0];
  _RAND_81 = {1{`RANDOM}};
  abstractGeneratedMem_1 = _RAND_81[31:0];
`endif // RANDOMIZE_REG_INIT
  if (_GEN_0) begin
    hrDebugIntReg_0 = 1'h0;
  end
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ClockCrossingReg_w55(
  input         clock,
  input  [54:0] io_d,
  output [54:0] io_q,
  input         io_en
);
`ifdef RANDOMIZE_REG_INIT
  reg [63:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg [54:0] cdc_reg; // @[Reg.scala 16:16]
  assign io_q = cdc_reg; // @[SynchronizerReg.scala 202:8]
  always @(posedge clock) begin
    if (io_en) begin // @[Reg.scala 17:18]
      cdc_reg <= io_d; // @[Reg.scala 17:22]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {2{`RANDOM}};
  cdc_reg = _RAND_0[54:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module AsyncQueueSink_2(
  input         clock,
  input         io_deq_ready,
  output        io_deq_valid,
  output [2:0]  io_deq_bits_opcode,
  output [2:0]  io_deq_bits_param,
  output [1:0]  io_deq_bits_size,
  output        io_deq_bits_source,
  output [8:0]  io_deq_bits_address,
  output [3:0]  io_deq_bits_mask,
  output [31:0] io_deq_bits_data,
  output        io_deq_bits_corrupt,
  input  [2:0]  io_async_mem_0_opcode,
  input  [8:0]  io_async_mem_0_address,
  input  [31:0] io_async_mem_0_data,
  output        io_async_ridx,
  input         io_async_widx,
  output        io_async_safe_ridx_valid,
  input         io_async_safe_widx_valid,
  input         io_async_safe_source_reset_n
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
  wire  widx_widx_gray_clock; // @[ShiftReg.scala 45:23]
  wire  widx_widx_gray_reset; // @[ShiftReg.scala 45:23]
  wire  widx_widx_gray_io_d; // @[ShiftReg.scala 45:23]
  wire  widx_widx_gray_io_q; // @[ShiftReg.scala 45:23]
  wire  io_deq_bits_deq_bits_reg_clock; // @[SynchronizerReg.scala 207:25]
  wire [54:0] io_deq_bits_deq_bits_reg_io_d; // @[SynchronizerReg.scala 207:25]
  wire [54:0] io_deq_bits_deq_bits_reg_io_q; // @[SynchronizerReg.scala 207:25]
  wire  io_deq_bits_deq_bits_reg_io_en; // @[SynchronizerReg.scala 207:25]
  wire  sink_valid_0_io_in; // @[AsyncQueue.scala 168:33]
  wire  sink_valid_0_io_out; // @[AsyncQueue.scala 168:33]
  wire  sink_valid_0_clock; // @[AsyncQueue.scala 168:33]
  wire  sink_valid_0_reset; // @[AsyncQueue.scala 168:33]
  wire  sink_valid_1_io_in; // @[AsyncQueue.scala 169:33]
  wire  sink_valid_1_io_out; // @[AsyncQueue.scala 169:33]
  wire  sink_valid_1_clock; // @[AsyncQueue.scala 169:33]
  wire  sink_valid_1_reset; // @[AsyncQueue.scala 169:33]
  wire  source_extend_io_in; // @[AsyncQueue.scala 171:31]
  wire  source_extend_io_out; // @[AsyncQueue.scala 171:31]
  wire  source_extend_clock; // @[AsyncQueue.scala 171:31]
  wire  source_extend_reset; // @[AsyncQueue.scala 171:31]
  wire  source_valid_io_in; // @[AsyncQueue.scala 172:31]
  wire  source_valid_io_out; // @[AsyncQueue.scala 172:31]
  wire  source_valid_clock; // @[AsyncQueue.scala 172:31]
  wire  source_valid_reset; // @[AsyncQueue.scala 172:31]
  wire  _ridx_T_1 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
  wire  source_ready = source_valid_io_out;
  wire  _ridx_T_2 = ~source_ready; // @[AsyncQueue.scala 144:79]
  wire  _GEN_0 = 1'h0; // @[AsyncQueue.scala 52:25]
  reg  ridx_ridx_bin; // @[AsyncQueue.scala 52:25]
  wire  ridx_incremented = _ridx_T_2 ? 1'h0 : ridx_ridx_bin + _ridx_T_1; // @[AsyncQueue.scala 53:23]
  wire  widx = widx_widx_gray_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire [45:0] io_deq_bits_deq_bits_reg_io_d_lo = {io_async_mem_0_address,4'hf,io_async_mem_0_data,1'h0}; // @[SynchronizerReg.scala 209:24]
  wire [8:0] io_deq_bits_deq_bits_reg_io_d_hi = {io_async_mem_0_opcode,3'h0,3'h4}; // @[SynchronizerReg.scala 209:24]
  wire [54:0] _io_deq_bits_WIRE_1 = io_deq_bits_deq_bits_reg_io_q;
  wire  _GEN_1 = 1'h0; // @[AsyncQueue.scala 161:56]
  reg  valid_reg; // @[AsyncQueue.scala 161:56]
  wire  _GEN_2 = 1'h0; // @[AsyncQueue.scala 164:55]
  reg  ridx_gray; // @[AsyncQueue.scala 164:55]
  AsyncResetSynchronizerShiftReg_w1_d3_i0 widx_widx_gray ( // @[ShiftReg.scala 45:23]
    .clock(widx_widx_gray_clock),
    .reset(widx_widx_gray_reset),
    .io_d(widx_widx_gray_io_d),
    .io_q(widx_widx_gray_io_q)
  );
  ClockCrossingReg_w55 io_deq_bits_deq_bits_reg ( // @[SynchronizerReg.scala 207:25]
    .clock(io_deq_bits_deq_bits_reg_clock),
    .io_d(io_deq_bits_deq_bits_reg_io_d),
    .io_q(io_deq_bits_deq_bits_reg_io_q),
    .io_en(io_deq_bits_deq_bits_reg_io_en)
  );
  AsyncValidSync sink_valid_0 ( // @[AsyncQueue.scala 168:33]
    .io_in(sink_valid_0_io_in),
    .io_out(sink_valid_0_io_out),
    .clock(sink_valid_0_clock),
    .reset(sink_valid_0_reset)
  );
  AsyncValidSync sink_valid_1 ( // @[AsyncQueue.scala 169:33]
    .io_in(sink_valid_1_io_in),
    .io_out(sink_valid_1_io_out),
    .clock(sink_valid_1_clock),
    .reset(sink_valid_1_reset)
  );
  AsyncValidSync source_extend ( // @[AsyncQueue.scala 171:31]
    .io_in(source_extend_io_in),
    .io_out(source_extend_io_out),
    .clock(source_extend_clock),
    .reset(source_extend_reset)
  );
  AsyncValidSync source_valid ( // @[AsyncQueue.scala 172:31]
    .io_in(source_valid_io_in),
    .io_out(source_valid_io_out),
    .clock(source_valid_clock),
    .reset(source_valid_reset)
  );
  assign io_deq_valid = valid_reg & source_ready; // @[AsyncQueue.scala 162:29]
  assign io_deq_bits_opcode = _io_deq_bits_WIRE_1[54:52]; // @[SynchronizerReg.scala 211:26]
  assign io_deq_bits_param = _io_deq_bits_WIRE_1[51:49]; // @[SynchronizerReg.scala 211:26]
  assign io_deq_bits_size = _io_deq_bits_WIRE_1[48:47]; // @[SynchronizerReg.scala 211:26]
  assign io_deq_bits_source = _io_deq_bits_WIRE_1[46]; // @[SynchronizerReg.scala 211:26]
  assign io_deq_bits_address = _io_deq_bits_WIRE_1[45:37]; // @[SynchronizerReg.scala 211:26]
  assign io_deq_bits_mask = _io_deq_bits_WIRE_1[36:33]; // @[SynchronizerReg.scala 211:26]
  assign io_deq_bits_data = _io_deq_bits_WIRE_1[32:1]; // @[SynchronizerReg.scala 211:26]
  assign io_deq_bits_corrupt = _io_deq_bits_WIRE_1[0]; // @[SynchronizerReg.scala 211:26]
  assign io_async_ridx = ridx_gray; // @[AsyncQueue.scala 165:17]
  assign io_async_safe_ridx_valid = sink_valid_1_io_out; // @[AsyncQueue.scala 185:20]
  assign widx_widx_gray_clock = clock;
  assign widx_widx_gray_reset = 1'h0;
  assign widx_widx_gray_io_d = io_async_widx; // @[ShiftReg.scala 47:16]
  assign io_deq_bits_deq_bits_reg_clock = clock;
  assign io_deq_bits_deq_bits_reg_io_d = {io_deq_bits_deq_bits_reg_io_d_hi,io_deq_bits_deq_bits_reg_io_d_lo}; // @[SynchronizerReg.scala 209:24]
  assign io_deq_bits_deq_bits_reg_io_en = source_ready & ridx_incremented != widx; // @[AsyncQueue.scala 146:28]
  assign sink_valid_0_io_in = 1'h1; // @[AsyncQueue.scala 183:24]
  assign sink_valid_0_clock = clock; // @[AsyncQueue.scala 178:25]
  assign sink_valid_0_reset = ~io_async_safe_source_reset_n; // @[AsyncQueue.scala 173:66]
  assign sink_valid_1_io_in = sink_valid_0_io_out; // @[AsyncQueue.scala 184:24]
  assign sink_valid_1_clock = clock; // @[AsyncQueue.scala 179:25]
  assign sink_valid_1_reset = ~io_async_safe_source_reset_n; // @[AsyncQueue.scala 174:66]
  assign source_extend_io_in = io_async_safe_widx_valid; // @[AsyncQueue.scala 186:25]
  assign source_extend_clock = clock; // @[AsyncQueue.scala 180:25]
  assign source_extend_reset = ~io_async_safe_source_reset_n; // @[AsyncQueue.scala 175:66]
  assign source_valid_io_in = source_extend_io_out; // @[AsyncQueue.scala 187:24]
  assign source_valid_clock = clock; // @[AsyncQueue.scala 181:25]
  assign source_valid_reset = 1'h0; // @[AsyncQueue.scala 176:34]
  always @(posedge clock or posedge _GEN_0) begin
    if (_GEN_0) begin // @[AsyncQueue.scala 53:23]
      ridx_ridx_bin <= 1'h0;
    end else if (_ridx_T_2) begin
      ridx_ridx_bin <= 1'h0;
    end else begin
      ridx_ridx_bin <= ridx_ridx_bin + _ridx_T_1;
    end
  end
  always @(posedge clock or posedge _GEN_1) begin
    if (_GEN_1) begin // @[AsyncQueue.scala 146:28]
      valid_reg <= 1'h0;
    end else begin
      valid_reg <= source_ready & ridx_incremented != widx;
    end
  end
  always @(posedge clock or posedge _GEN_2) begin
    if (_GEN_2) begin // @[AsyncQueue.scala 53:23]
      ridx_gray <= 1'h0;
    end else if (_ridx_T_2) begin
      ridx_gray <= 1'h0;
    end else begin
      ridx_gray <= ridx_ridx_bin + _ridx_T_1;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  ridx_ridx_bin = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  valid_reg = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  ridx_gray = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
  if (_GEN_0) begin
    ridx_ridx_bin = 1'h0;
  end
  if (_GEN_1) begin
    valid_reg = 1'h0;
  end
  if (_GEN_2) begin
    ridx_gray = 1'h0;
  end
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module AsyncQueueSource_3(
  input         clock,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [2:0]  io_enq_bits_opcode,
  input  [1:0]  io_enq_bits_size,
  input         io_enq_bits_source,
  input  [31:0] io_enq_bits_data,
  output [2:0]  io_async_mem_0_opcode,
  output [1:0]  io_async_mem_0_size,
  output        io_async_mem_0_source,
  output [31:0] io_async_mem_0_data,
  input         io_async_ridx,
  output        io_async_widx,
  input         io_async_safe_ridx_valid,
  output        io_async_safe_widx_valid,
  input         io_async_safe_sink_reset_n
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
`endif // RANDOMIZE_REG_INIT
  wire  ridx_ridx_gray_clock; // @[ShiftReg.scala 45:23]
  wire  ridx_ridx_gray_reset; // @[ShiftReg.scala 45:23]
  wire  ridx_ridx_gray_io_d; // @[ShiftReg.scala 45:23]
  wire  ridx_ridx_gray_io_q; // @[ShiftReg.scala 45:23]
  wire  source_valid_0_io_in; // @[AsyncQueue.scala 100:32]
  wire  source_valid_0_io_out; // @[AsyncQueue.scala 100:32]
  wire  source_valid_0_clock; // @[AsyncQueue.scala 100:32]
  wire  source_valid_0_reset; // @[AsyncQueue.scala 100:32]
  wire  source_valid_1_io_in; // @[AsyncQueue.scala 101:32]
  wire  source_valid_1_io_out; // @[AsyncQueue.scala 101:32]
  wire  source_valid_1_clock; // @[AsyncQueue.scala 101:32]
  wire  source_valid_1_reset; // @[AsyncQueue.scala 101:32]
  wire  sink_extend_io_in; // @[AsyncQueue.scala 103:30]
  wire  sink_extend_io_out; // @[AsyncQueue.scala 103:30]
  wire  sink_extend_clock; // @[AsyncQueue.scala 103:30]
  wire  sink_extend_reset; // @[AsyncQueue.scala 103:30]
  wire  sink_valid_io_in; // @[AsyncQueue.scala 104:30]
  wire  sink_valid_io_out; // @[AsyncQueue.scala 104:30]
  wire  sink_valid_clock; // @[AsyncQueue.scala 104:30]
  wire  sink_valid_reset; // @[AsyncQueue.scala 104:30]
  reg [2:0] mem_0_opcode; // @[AsyncQueue.scala 80:16]
  reg [1:0] mem_0_size; // @[AsyncQueue.scala 80:16]
  reg  mem_0_source; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_0_data; // @[AsyncQueue.scala 80:16]
  wire  _widx_T_1 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
  wire  sink_ready = sink_valid_io_out;
  wire  _widx_T_2 = ~sink_ready; // @[AsyncQueue.scala 81:79]
  wire  _GEN_0 = 1'h0; // @[AsyncQueue.scala 52:25]
  reg  widx_widx_bin; // @[AsyncQueue.scala 52:25]
  wire  widx_incremented = _widx_T_2 ? 1'h0 : widx_widx_bin + _widx_T_1; // @[AsyncQueue.scala 53:23]
  wire  ridx = ridx_ridx_gray_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  _GEN_1 = 1'h0; // @[AsyncQueue.scala 88:56]
  reg  ready_reg; // @[AsyncQueue.scala 88:56]
  wire  _GEN_2 = 1'h0; // @[AsyncQueue.scala 91:55]
  reg  widx_gray; // @[AsyncQueue.scala 91:55]
  AsyncResetSynchronizerShiftReg_w1_d3_i0 ridx_ridx_gray ( // @[ShiftReg.scala 45:23]
    .clock(ridx_ridx_gray_clock),
    .reset(ridx_ridx_gray_reset),
    .io_d(ridx_ridx_gray_io_d),
    .io_q(ridx_ridx_gray_io_q)
  );
  AsyncValidSync source_valid_0 ( // @[AsyncQueue.scala 100:32]
    .io_in(source_valid_0_io_in),
    .io_out(source_valid_0_io_out),
    .clock(source_valid_0_clock),
    .reset(source_valid_0_reset)
  );
  AsyncValidSync source_valid_1 ( // @[AsyncQueue.scala 101:32]
    .io_in(source_valid_1_io_in),
    .io_out(source_valid_1_io_out),
    .clock(source_valid_1_clock),
    .reset(source_valid_1_reset)
  );
  AsyncValidSync sink_extend ( // @[AsyncQueue.scala 103:30]
    .io_in(sink_extend_io_in),
    .io_out(sink_extend_io_out),
    .clock(sink_extend_clock),
    .reset(sink_extend_reset)
  );
  AsyncValidSync sink_valid ( // @[AsyncQueue.scala 104:30]
    .io_in(sink_valid_io_in),
    .io_out(sink_valid_io_out),
    .clock(sink_valid_clock),
    .reset(sink_valid_reset)
  );
  assign io_enq_ready = ready_reg & sink_ready; // @[AsyncQueue.scala 89:29]
  assign io_async_mem_0_opcode = mem_0_opcode; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_0_size = mem_0_size; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_0_source = mem_0_source; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_0_data = mem_0_data; // @[AsyncQueue.scala 96:31]
  assign io_async_widx = widx_gray; // @[AsyncQueue.scala 92:17]
  assign io_async_safe_widx_valid = source_valid_1_io_out; // @[AsyncQueue.scala 117:20]
  assign ridx_ridx_gray_clock = clock;
  assign ridx_ridx_gray_reset = 1'h0;
  assign ridx_ridx_gray_io_d = io_async_ridx; // @[ShiftReg.scala 47:16]
  assign source_valid_0_io_in = 1'h1; // @[AsyncQueue.scala 115:26]
  assign source_valid_0_clock = clock; // @[AsyncQueue.scala 110:26]
  assign source_valid_0_reset = ~io_async_safe_sink_reset_n; // @[AsyncQueue.scala 105:65]
  assign source_valid_1_io_in = source_valid_0_io_out; // @[AsyncQueue.scala 116:26]
  assign source_valid_1_clock = clock; // @[AsyncQueue.scala 111:26]
  assign source_valid_1_reset = ~io_async_safe_sink_reset_n; // @[AsyncQueue.scala 106:65]
  assign sink_extend_io_in = io_async_safe_ridx_valid; // @[AsyncQueue.scala 118:23]
  assign sink_extend_clock = clock; // @[AsyncQueue.scala 112:26]
  assign sink_extend_reset = ~io_async_safe_sink_reset_n; // @[AsyncQueue.scala 107:65]
  assign sink_valid_io_in = sink_extend_io_out; // @[AsyncQueue.scala 119:22]
  assign sink_valid_clock = clock; // @[AsyncQueue.scala 113:26]
  assign sink_valid_reset = 1'h0; // @[AsyncQueue.scala 108:35]
  always @(posedge clock) begin
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      mem_0_opcode <= io_enq_bits_opcode; // @[AsyncQueue.scala 86:37]
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      mem_0_size <= io_enq_bits_size; // @[AsyncQueue.scala 86:37]
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      mem_0_source <= io_enq_bits_source; // @[AsyncQueue.scala 86:37]
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      mem_0_data <= io_enq_bits_data; // @[AsyncQueue.scala 86:37]
    end
  end
  always @(posedge clock or posedge _GEN_0) begin
    if (_GEN_0) begin // @[AsyncQueue.scala 53:23]
      widx_widx_bin <= 1'h0;
    end else if (_widx_T_2) begin
      widx_widx_bin <= 1'h0;
    end else begin
      widx_widx_bin <= widx_widx_bin + _widx_T_1;
    end
  end
  always @(posedge clock or posedge _GEN_1) begin
    if (_GEN_1) begin // @[AsyncQueue.scala 83:26]
      ready_reg <= 1'h0;
    end else begin
      ready_reg <= sink_ready & widx_incremented != (ridx ^ 1'h1);
    end
  end
  always @(posedge clock or posedge _GEN_2) begin
    if (_GEN_2) begin // @[AsyncQueue.scala 53:23]
      widx_gray <= 1'h0;
    end else if (_widx_T_2) begin
      widx_gray <= 1'h0;
    end else begin
      widx_gray <= widx_widx_bin + _widx_T_1;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  mem_0_opcode = _RAND_0[2:0];
  _RAND_1 = {1{`RANDOM}};
  mem_0_size = _RAND_1[1:0];
  _RAND_2 = {1{`RANDOM}};
  mem_0_source = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  mem_0_data = _RAND_3[31:0];
  _RAND_4 = {1{`RANDOM}};
  widx_widx_bin = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  ready_reg = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  widx_gray = _RAND_6[0:0];
`endif // RANDOMIZE_REG_INIT
  if (_GEN_0) begin
    widx_widx_bin = 1'h0;
  end
  if (_GEN_1) begin
    ready_reg = 1'h0;
  end
  if (_GEN_2) begin
    widx_gray = 1'h0;
  end
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLAsyncCrossingSink(
  input         clock,
  input  [2:0]  auto_in_a_mem_0_opcode,
  input  [8:0]  auto_in_a_mem_0_address,
  input  [31:0] auto_in_a_mem_0_data,
  output        auto_in_a_ridx,
  input         auto_in_a_widx,
  output        auto_in_a_safe_ridx_valid,
  input         auto_in_a_safe_widx_valid,
  input         auto_in_a_safe_source_reset_n,
  output [2:0]  auto_in_d_mem_0_opcode,
  output [1:0]  auto_in_d_mem_0_size,
  output        auto_in_d_mem_0_source,
  output [31:0] auto_in_d_mem_0_data,
  input         auto_in_d_ridx,
  output        auto_in_d_widx,
  input         auto_in_d_safe_ridx_valid,
  output        auto_in_d_safe_widx_valid,
  input         auto_in_d_safe_sink_reset_n,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [1:0]  auto_out_a_bits_size,
  output        auto_out_a_bits_source,
  output [8:0]  auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_size,
  input         auto_out_d_bits_source,
  input  [31:0] auto_out_d_bits_data
);
  wire  bundleOut_0_a_sink_clock; // @[AsyncQueue.scala 207:22]
  wire  bundleOut_0_a_sink_io_deq_ready; // @[AsyncQueue.scala 207:22]
  wire  bundleOut_0_a_sink_io_deq_valid; // @[AsyncQueue.scala 207:22]
  wire [2:0] bundleOut_0_a_sink_io_deq_bits_opcode; // @[AsyncQueue.scala 207:22]
  wire [2:0] bundleOut_0_a_sink_io_deq_bits_param; // @[AsyncQueue.scala 207:22]
  wire [1:0] bundleOut_0_a_sink_io_deq_bits_size; // @[AsyncQueue.scala 207:22]
  wire  bundleOut_0_a_sink_io_deq_bits_source; // @[AsyncQueue.scala 207:22]
  wire [8:0] bundleOut_0_a_sink_io_deq_bits_address; // @[AsyncQueue.scala 207:22]
  wire [3:0] bundleOut_0_a_sink_io_deq_bits_mask; // @[AsyncQueue.scala 207:22]
  wire [31:0] bundleOut_0_a_sink_io_deq_bits_data; // @[AsyncQueue.scala 207:22]
  wire  bundleOut_0_a_sink_io_deq_bits_corrupt; // @[AsyncQueue.scala 207:22]
  wire [2:0] bundleOut_0_a_sink_io_async_mem_0_opcode; // @[AsyncQueue.scala 207:22]
  wire [8:0] bundleOut_0_a_sink_io_async_mem_0_address; // @[AsyncQueue.scala 207:22]
  wire [31:0] bundleOut_0_a_sink_io_async_mem_0_data; // @[AsyncQueue.scala 207:22]
  wire  bundleOut_0_a_sink_io_async_ridx; // @[AsyncQueue.scala 207:22]
  wire  bundleOut_0_a_sink_io_async_widx; // @[AsyncQueue.scala 207:22]
  wire  bundleOut_0_a_sink_io_async_safe_ridx_valid; // @[AsyncQueue.scala 207:22]
  wire  bundleOut_0_a_sink_io_async_safe_widx_valid; // @[AsyncQueue.scala 207:22]
  wire  bundleOut_0_a_sink_io_async_safe_source_reset_n; // @[AsyncQueue.scala 207:22]
  wire  bundleIn_0_d_source_clock; // @[AsyncQueue.scala 216:24]
  wire  bundleIn_0_d_source_io_enq_ready; // @[AsyncQueue.scala 216:24]
  wire  bundleIn_0_d_source_io_enq_valid; // @[AsyncQueue.scala 216:24]
  wire [2:0] bundleIn_0_d_source_io_enq_bits_opcode; // @[AsyncQueue.scala 216:24]
  wire [1:0] bundleIn_0_d_source_io_enq_bits_size; // @[AsyncQueue.scala 216:24]
  wire  bundleIn_0_d_source_io_enq_bits_source; // @[AsyncQueue.scala 216:24]
  wire [31:0] bundleIn_0_d_source_io_enq_bits_data; // @[AsyncQueue.scala 216:24]
  wire [2:0] bundleIn_0_d_source_io_async_mem_0_opcode; // @[AsyncQueue.scala 216:24]
  wire [1:0] bundleIn_0_d_source_io_async_mem_0_size; // @[AsyncQueue.scala 216:24]
  wire  bundleIn_0_d_source_io_async_mem_0_source; // @[AsyncQueue.scala 216:24]
  wire [31:0] bundleIn_0_d_source_io_async_mem_0_data; // @[AsyncQueue.scala 216:24]
  wire  bundleIn_0_d_source_io_async_ridx; // @[AsyncQueue.scala 216:24]
  wire  bundleIn_0_d_source_io_async_widx; // @[AsyncQueue.scala 216:24]
  wire  bundleIn_0_d_source_io_async_safe_ridx_valid; // @[AsyncQueue.scala 216:24]
  wire  bundleIn_0_d_source_io_async_safe_widx_valid; // @[AsyncQueue.scala 216:24]
  wire  bundleIn_0_d_source_io_async_safe_sink_reset_n; // @[AsyncQueue.scala 216:24]
  AsyncQueueSink_2 bundleOut_0_a_sink ( // @[AsyncQueue.scala 207:22]
    .clock(bundleOut_0_a_sink_clock),
    .io_deq_ready(bundleOut_0_a_sink_io_deq_ready),
    .io_deq_valid(bundleOut_0_a_sink_io_deq_valid),
    .io_deq_bits_opcode(bundleOut_0_a_sink_io_deq_bits_opcode),
    .io_deq_bits_param(bundleOut_0_a_sink_io_deq_bits_param),
    .io_deq_bits_size(bundleOut_0_a_sink_io_deq_bits_size),
    .io_deq_bits_source(bundleOut_0_a_sink_io_deq_bits_source),
    .io_deq_bits_address(bundleOut_0_a_sink_io_deq_bits_address),
    .io_deq_bits_mask(bundleOut_0_a_sink_io_deq_bits_mask),
    .io_deq_bits_data(bundleOut_0_a_sink_io_deq_bits_data),
    .io_deq_bits_corrupt(bundleOut_0_a_sink_io_deq_bits_corrupt),
    .io_async_mem_0_opcode(bundleOut_0_a_sink_io_async_mem_0_opcode),
    .io_async_mem_0_address(bundleOut_0_a_sink_io_async_mem_0_address),
    .io_async_mem_0_data(bundleOut_0_a_sink_io_async_mem_0_data),
    .io_async_ridx(bundleOut_0_a_sink_io_async_ridx),
    .io_async_widx(bundleOut_0_a_sink_io_async_widx),
    .io_async_safe_ridx_valid(bundleOut_0_a_sink_io_async_safe_ridx_valid),
    .io_async_safe_widx_valid(bundleOut_0_a_sink_io_async_safe_widx_valid),
    .io_async_safe_source_reset_n(bundleOut_0_a_sink_io_async_safe_source_reset_n)
  );
  AsyncQueueSource_3 bundleIn_0_d_source ( // @[AsyncQueue.scala 216:24]
    .clock(bundleIn_0_d_source_clock),
    .io_enq_ready(bundleIn_0_d_source_io_enq_ready),
    .io_enq_valid(bundleIn_0_d_source_io_enq_valid),
    .io_enq_bits_opcode(bundleIn_0_d_source_io_enq_bits_opcode),
    .io_enq_bits_size(bundleIn_0_d_source_io_enq_bits_size),
    .io_enq_bits_source(bundleIn_0_d_source_io_enq_bits_source),
    .io_enq_bits_data(bundleIn_0_d_source_io_enq_bits_data),
    .io_async_mem_0_opcode(bundleIn_0_d_source_io_async_mem_0_opcode),
    .io_async_mem_0_size(bundleIn_0_d_source_io_async_mem_0_size),
    .io_async_mem_0_source(bundleIn_0_d_source_io_async_mem_0_source),
    .io_async_mem_0_data(bundleIn_0_d_source_io_async_mem_0_data),
    .io_async_ridx(bundleIn_0_d_source_io_async_ridx),
    .io_async_widx(bundleIn_0_d_source_io_async_widx),
    .io_async_safe_ridx_valid(bundleIn_0_d_source_io_async_safe_ridx_valid),
    .io_async_safe_widx_valid(bundleIn_0_d_source_io_async_safe_widx_valid),
    .io_async_safe_sink_reset_n(bundleIn_0_d_source_io_async_safe_sink_reset_n)
  );
  assign auto_in_a_ridx = bundleOut_0_a_sink_io_async_ridx; // @[Nodes.scala 1210:84 AsyncQueue.scala 208:19]
  assign auto_in_a_safe_ridx_valid = bundleOut_0_a_sink_io_async_safe_ridx_valid; // @[Nodes.scala 1210:84 AsyncQueue.scala 208:19]
  assign auto_in_d_mem_0_opcode = bundleIn_0_d_source_io_async_mem_0_opcode; // @[Nodes.scala 1210:84 AsyncCrossing.scala 58:12]
  assign auto_in_d_mem_0_size = bundleIn_0_d_source_io_async_mem_0_size; // @[Nodes.scala 1210:84 AsyncCrossing.scala 58:12]
  assign auto_in_d_mem_0_source = bundleIn_0_d_source_io_async_mem_0_source; // @[Nodes.scala 1210:84 AsyncCrossing.scala 58:12]
  assign auto_in_d_mem_0_data = bundleIn_0_d_source_io_async_mem_0_data; // @[Nodes.scala 1210:84 AsyncCrossing.scala 58:12]
  assign auto_in_d_widx = bundleIn_0_d_source_io_async_widx; // @[Nodes.scala 1210:84 AsyncCrossing.scala 58:12]
  assign auto_in_d_safe_widx_valid = bundleIn_0_d_source_io_async_safe_widx_valid; // @[Nodes.scala 1210:84 AsyncCrossing.scala 58:12]
  assign auto_out_a_valid = bundleOut_0_a_sink_io_deq_valid; // @[Nodes.scala 1207:84 AsyncCrossing.scala 57:13]
  assign auto_out_a_bits_opcode = bundleOut_0_a_sink_io_deq_bits_opcode; // @[Nodes.scala 1207:84 AsyncCrossing.scala 57:13]
  assign auto_out_a_bits_param = bundleOut_0_a_sink_io_deq_bits_param; // @[Nodes.scala 1207:84 AsyncCrossing.scala 57:13]
  assign auto_out_a_bits_size = bundleOut_0_a_sink_io_deq_bits_size; // @[Nodes.scala 1207:84 AsyncCrossing.scala 57:13]
  assign auto_out_a_bits_source = bundleOut_0_a_sink_io_deq_bits_source; // @[Nodes.scala 1207:84 AsyncCrossing.scala 57:13]
  assign auto_out_a_bits_address = bundleOut_0_a_sink_io_deq_bits_address; // @[Nodes.scala 1207:84 AsyncCrossing.scala 57:13]
  assign auto_out_a_bits_mask = bundleOut_0_a_sink_io_deq_bits_mask; // @[Nodes.scala 1207:84 AsyncCrossing.scala 57:13]
  assign auto_out_a_bits_data = bundleOut_0_a_sink_io_deq_bits_data; // @[Nodes.scala 1207:84 AsyncCrossing.scala 57:13]
  assign auto_out_a_bits_corrupt = bundleOut_0_a_sink_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 AsyncCrossing.scala 57:13]
  assign auto_out_d_ready = bundleIn_0_d_source_io_enq_ready; // @[Nodes.scala 1207:84 AsyncQueue.scala 217:19]
  assign bundleOut_0_a_sink_clock = clock;
  assign bundleOut_0_a_sink_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleOut_0_a_sink_io_async_mem_0_opcode = auto_in_a_mem_0_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_sink_io_async_mem_0_address = auto_in_a_mem_0_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_sink_io_async_mem_0_data = auto_in_a_mem_0_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_sink_io_async_widx = auto_in_a_widx; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_sink_io_async_safe_widx_valid = auto_in_a_safe_widx_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_sink_io_async_safe_source_reset_n = auto_in_a_safe_source_reset_n; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleIn_0_d_source_clock = clock;
  assign bundleIn_0_d_source_io_enq_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_source_io_enq_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_source_io_enq_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_source_io_enq_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_source_io_enq_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_source_io_async_ridx = auto_in_d_ridx; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleIn_0_d_source_io_async_safe_ridx_valid = auto_in_d_safe_ridx_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleIn_0_d_source_io_async_safe_sink_reset_n = auto_in_d_safe_sink_reset_n; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module ClockCrossingReg_w15(
  input         clock,
  input  [14:0] io_d,
  output [14:0] io_q,
  input         io_en
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg [14:0] cdc_reg; // @[Reg.scala 16:16]
  assign io_q = cdc_reg; // @[SynchronizerReg.scala 202:8]
  always @(posedge clock) begin
    if (io_en) begin // @[Reg.scala 17:18]
      cdc_reg <= io_d; // @[Reg.scala 17:22]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  cdc_reg = _RAND_0[14:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module AsyncQueueSink_3(
  input        clock,
  output       io_deq_valid,
  output       io_deq_bits_resumereq,
  output [9:0] io_deq_bits_hartsel,
  output       io_deq_bits_ackhavereset,
  output       io_deq_bits_hrmask_0,
  input        io_async_mem_0_resumereq,
  input        io_async_mem_0_ackhavereset,
  input        io_async_mem_0_hrmask_0,
  output       io_async_ridx,
  input        io_async_widx,
  output       io_async_safe_ridx_valid,
  input        io_async_safe_widx_valid,
  input        io_async_safe_source_reset_n
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
  wire  widx_widx_gray_clock; // @[ShiftReg.scala 45:23]
  wire  widx_widx_gray_reset; // @[ShiftReg.scala 45:23]
  wire  widx_widx_gray_io_d; // @[ShiftReg.scala 45:23]
  wire  widx_widx_gray_io_q; // @[ShiftReg.scala 45:23]
  wire  io_deq_bits_deq_bits_reg_clock; // @[SynchronizerReg.scala 207:25]
  wire [14:0] io_deq_bits_deq_bits_reg_io_d; // @[SynchronizerReg.scala 207:25]
  wire [14:0] io_deq_bits_deq_bits_reg_io_q; // @[SynchronizerReg.scala 207:25]
  wire  io_deq_bits_deq_bits_reg_io_en; // @[SynchronizerReg.scala 207:25]
  wire  sink_valid_0_io_in; // @[AsyncQueue.scala 168:33]
  wire  sink_valid_0_io_out; // @[AsyncQueue.scala 168:33]
  wire  sink_valid_0_clock; // @[AsyncQueue.scala 168:33]
  wire  sink_valid_0_reset; // @[AsyncQueue.scala 168:33]
  wire  sink_valid_1_io_in; // @[AsyncQueue.scala 169:33]
  wire  sink_valid_1_io_out; // @[AsyncQueue.scala 169:33]
  wire  sink_valid_1_clock; // @[AsyncQueue.scala 169:33]
  wire  sink_valid_1_reset; // @[AsyncQueue.scala 169:33]
  wire  source_extend_io_in; // @[AsyncQueue.scala 171:31]
  wire  source_extend_io_out; // @[AsyncQueue.scala 171:31]
  wire  source_extend_clock; // @[AsyncQueue.scala 171:31]
  wire  source_extend_reset; // @[AsyncQueue.scala 171:31]
  wire  source_valid_io_in; // @[AsyncQueue.scala 172:31]
  wire  source_valid_io_out; // @[AsyncQueue.scala 172:31]
  wire  source_valid_clock; // @[AsyncQueue.scala 172:31]
  wire  source_valid_reset; // @[AsyncQueue.scala 172:31]
  wire  source_ready = source_valid_io_out;
  wire  _ridx_T_2 = ~source_ready; // @[AsyncQueue.scala 144:79]
  wire  _GEN_0 = 1'h0; // @[AsyncQueue.scala 52:25]
  reg  ridx_ridx_bin; // @[AsyncQueue.scala 52:25]
  wire  ridx_incremented = _ridx_T_2 ? 1'h0 : ridx_ridx_bin + io_deq_valid; // @[AsyncQueue.scala 53:23]
  wire  widx = widx_widx_gray_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire [2:0] io_deq_bits_deq_bits_reg_io_d_lo = {2'h0,io_async_mem_0_hrmask_0}; // @[SynchronizerReg.scala 209:24]
  wire [11:0] io_deq_bits_deq_bits_reg_io_d_hi = {io_async_mem_0_resumereq,10'h0,io_async_mem_0_ackhavereset}; // @[SynchronizerReg.scala 209:24]
  wire [14:0] _io_deq_bits_WIRE_1 = io_deq_bits_deq_bits_reg_io_q;
  wire  _GEN_1 = 1'h0; // @[AsyncQueue.scala 161:56]
  reg  valid_reg; // @[AsyncQueue.scala 161:56]
  wire  _GEN_2 = 1'h0; // @[AsyncQueue.scala 164:55]
  reg  ridx_gray; // @[AsyncQueue.scala 164:55]
  AsyncResetSynchronizerShiftReg_w1_d3_i0 widx_widx_gray ( // @[ShiftReg.scala 45:23]
    .clock(widx_widx_gray_clock),
    .reset(widx_widx_gray_reset),
    .io_d(widx_widx_gray_io_d),
    .io_q(widx_widx_gray_io_q)
  );
  ClockCrossingReg_w15 io_deq_bits_deq_bits_reg ( // @[SynchronizerReg.scala 207:25]
    .clock(io_deq_bits_deq_bits_reg_clock),
    .io_d(io_deq_bits_deq_bits_reg_io_d),
    .io_q(io_deq_bits_deq_bits_reg_io_q),
    .io_en(io_deq_bits_deq_bits_reg_io_en)
  );
  AsyncValidSync sink_valid_0 ( // @[AsyncQueue.scala 168:33]
    .io_in(sink_valid_0_io_in),
    .io_out(sink_valid_0_io_out),
    .clock(sink_valid_0_clock),
    .reset(sink_valid_0_reset)
  );
  AsyncValidSync sink_valid_1 ( // @[AsyncQueue.scala 169:33]
    .io_in(sink_valid_1_io_in),
    .io_out(sink_valid_1_io_out),
    .clock(sink_valid_1_clock),
    .reset(sink_valid_1_reset)
  );
  AsyncValidSync source_extend ( // @[AsyncQueue.scala 171:31]
    .io_in(source_extend_io_in),
    .io_out(source_extend_io_out),
    .clock(source_extend_clock),
    .reset(source_extend_reset)
  );
  AsyncValidSync source_valid ( // @[AsyncQueue.scala 172:31]
    .io_in(source_valid_io_in),
    .io_out(source_valid_io_out),
    .clock(source_valid_clock),
    .reset(source_valid_reset)
  );
  assign io_deq_valid = valid_reg & source_ready; // @[AsyncQueue.scala 162:29]
  assign io_deq_bits_resumereq = _io_deq_bits_WIRE_1[14]; // @[SynchronizerReg.scala 211:26]
  assign io_deq_bits_hartsel = _io_deq_bits_WIRE_1[13:4]; // @[SynchronizerReg.scala 211:26]
  assign io_deq_bits_ackhavereset = _io_deq_bits_WIRE_1[3]; // @[SynchronizerReg.scala 211:26]
  assign io_deq_bits_hrmask_0 = _io_deq_bits_WIRE_1[0]; // @[SynchronizerReg.scala 211:26]
  assign io_async_ridx = ridx_gray; // @[AsyncQueue.scala 165:17]
  assign io_async_safe_ridx_valid = sink_valid_1_io_out; // @[AsyncQueue.scala 185:20]
  assign widx_widx_gray_clock = clock;
  assign widx_widx_gray_reset = 1'h0;
  assign widx_widx_gray_io_d = io_async_widx; // @[ShiftReg.scala 47:16]
  assign io_deq_bits_deq_bits_reg_clock = clock;
  assign io_deq_bits_deq_bits_reg_io_d = {io_deq_bits_deq_bits_reg_io_d_hi,io_deq_bits_deq_bits_reg_io_d_lo}; // @[SynchronizerReg.scala 209:24]
  assign io_deq_bits_deq_bits_reg_io_en = source_ready & ridx_incremented != widx; // @[AsyncQueue.scala 146:28]
  assign sink_valid_0_io_in = 1'h1; // @[AsyncQueue.scala 183:24]
  assign sink_valid_0_clock = clock; // @[AsyncQueue.scala 178:25]
  assign sink_valid_0_reset = ~io_async_safe_source_reset_n; // @[AsyncQueue.scala 173:66]
  assign sink_valid_1_io_in = sink_valid_0_io_out; // @[AsyncQueue.scala 184:24]
  assign sink_valid_1_clock = clock; // @[AsyncQueue.scala 179:25]
  assign sink_valid_1_reset = ~io_async_safe_source_reset_n; // @[AsyncQueue.scala 174:66]
  assign source_extend_io_in = io_async_safe_widx_valid; // @[AsyncQueue.scala 186:25]
  assign source_extend_clock = clock; // @[AsyncQueue.scala 180:25]
  assign source_extend_reset = ~io_async_safe_source_reset_n; // @[AsyncQueue.scala 175:66]
  assign source_valid_io_in = source_extend_io_out; // @[AsyncQueue.scala 187:24]
  assign source_valid_clock = clock; // @[AsyncQueue.scala 181:25]
  assign source_valid_reset = 1'h0; // @[AsyncQueue.scala 176:34]
  always @(posedge clock or posedge _GEN_0) begin
    if (_GEN_0) begin // @[AsyncQueue.scala 53:23]
      ridx_ridx_bin <= 1'h0;
    end else if (_ridx_T_2) begin
      ridx_ridx_bin <= 1'h0;
    end else begin
      ridx_ridx_bin <= ridx_ridx_bin + io_deq_valid;
    end
  end
  always @(posedge clock or posedge _GEN_1) begin
    if (_GEN_1) begin // @[AsyncQueue.scala 146:28]
      valid_reg <= 1'h0;
    end else begin
      valid_reg <= source_ready & ridx_incremented != widx;
    end
  end
  always @(posedge clock or posedge _GEN_2) begin
    if (_GEN_2) begin // @[AsyncQueue.scala 53:23]
      ridx_gray <= 1'h0;
    end else if (_ridx_T_2) begin
      ridx_gray <= 1'h0;
    end else begin
      ridx_gray <= ridx_ridx_bin + io_deq_valid;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  ridx_ridx_bin = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  valid_reg = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  ridx_gray = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
  if (_GEN_0) begin
    ridx_ridx_bin = 1'h0;
  end
  if (_GEN_1) begin
    valid_reg = 1'h0;
  end
  if (_GEN_2) begin
    ridx_gray = 1'h0;
  end
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLDebugModuleInnerAsync(
  input  [2:0]  auto_dmiXing_in_a_mem_0_opcode,
  input  [8:0]  auto_dmiXing_in_a_mem_0_address,
  input  [31:0] auto_dmiXing_in_a_mem_0_data,
  output        auto_dmiXing_in_a_ridx,
  input         auto_dmiXing_in_a_widx,
  output        auto_dmiXing_in_a_safe_ridx_valid,
  input         auto_dmiXing_in_a_safe_widx_valid,
  input         auto_dmiXing_in_a_safe_source_reset_n,
  output [2:0]  auto_dmiXing_in_d_mem_0_opcode,
  output [1:0]  auto_dmiXing_in_d_mem_0_size,
  output        auto_dmiXing_in_d_mem_0_source,
  output [31:0] auto_dmiXing_in_d_mem_0_data,
  input         auto_dmiXing_in_d_ridx,
  output        auto_dmiXing_in_d_widx,
  input         auto_dmiXing_in_d_safe_ridx_valid,
  output        auto_dmiXing_in_d_safe_widx_valid,
  input         auto_dmiXing_in_d_safe_sink_reset_n,
  output        auto_dmInner_tl_in_a_ready,
  input         auto_dmInner_tl_in_a_valid,
  input  [2:0]  auto_dmInner_tl_in_a_bits_opcode,
  input  [2:0]  auto_dmInner_tl_in_a_bits_param,
  input  [1:0]  auto_dmInner_tl_in_a_bits_size,
  input  [6:0]  auto_dmInner_tl_in_a_bits_source,
  input  [11:0] auto_dmInner_tl_in_a_bits_address,
  input  [3:0]  auto_dmInner_tl_in_a_bits_mask,
  input  [31:0] auto_dmInner_tl_in_a_bits_data,
  input         auto_dmInner_tl_in_a_bits_corrupt,
  input         auto_dmInner_tl_in_d_ready,
  output        auto_dmInner_tl_in_d_valid,
  output [2:0]  auto_dmInner_tl_in_d_bits_opcode,
  output [1:0]  auto_dmInner_tl_in_d_bits_size,
  output [6:0]  auto_dmInner_tl_in_d_bits_source,
  output [31:0] auto_dmInner_tl_in_d_bits_data,
  input         io_debug_clock,
  input         io_dmactive,
  input         io_innerCtrl_mem_0_resumereq,
  input         io_innerCtrl_mem_0_ackhavereset,
  input         io_innerCtrl_mem_0_hrmask_0,
  output        io_innerCtrl_ridx,
  input         io_innerCtrl_widx,
  output        io_innerCtrl_safe_ridx_valid,
  input         io_innerCtrl_safe_widx_valid,
  input         io_innerCtrl_safe_source_reset_n,
  output        io_hgDebugInt_0
);
  wire  dmInner_clock; // @[Debug.scala 1741:27]
  wire  dmInner_auto_tl_in_a_ready; // @[Debug.scala 1741:27]
  wire  dmInner_auto_tl_in_a_valid; // @[Debug.scala 1741:27]
  wire [2:0] dmInner_auto_tl_in_a_bits_opcode; // @[Debug.scala 1741:27]
  wire [2:0] dmInner_auto_tl_in_a_bits_param; // @[Debug.scala 1741:27]
  wire [1:0] dmInner_auto_tl_in_a_bits_size; // @[Debug.scala 1741:27]
  wire [6:0] dmInner_auto_tl_in_a_bits_source; // @[Debug.scala 1741:27]
  wire [11:0] dmInner_auto_tl_in_a_bits_address; // @[Debug.scala 1741:27]
  wire [3:0] dmInner_auto_tl_in_a_bits_mask; // @[Debug.scala 1741:27]
  wire [31:0] dmInner_auto_tl_in_a_bits_data; // @[Debug.scala 1741:27]
  wire  dmInner_auto_tl_in_a_bits_corrupt; // @[Debug.scala 1741:27]
  wire  dmInner_auto_tl_in_d_ready; // @[Debug.scala 1741:27]
  wire  dmInner_auto_tl_in_d_valid; // @[Debug.scala 1741:27]
  wire [2:0] dmInner_auto_tl_in_d_bits_opcode; // @[Debug.scala 1741:27]
  wire [1:0] dmInner_auto_tl_in_d_bits_size; // @[Debug.scala 1741:27]
  wire [6:0] dmInner_auto_tl_in_d_bits_source; // @[Debug.scala 1741:27]
  wire [31:0] dmInner_auto_tl_in_d_bits_data; // @[Debug.scala 1741:27]
  wire  dmInner_auto_dmi_in_a_ready; // @[Debug.scala 1741:27]
  wire  dmInner_auto_dmi_in_a_valid; // @[Debug.scala 1741:27]
  wire [2:0] dmInner_auto_dmi_in_a_bits_opcode; // @[Debug.scala 1741:27]
  wire [2:0] dmInner_auto_dmi_in_a_bits_param; // @[Debug.scala 1741:27]
  wire [1:0] dmInner_auto_dmi_in_a_bits_size; // @[Debug.scala 1741:27]
  wire  dmInner_auto_dmi_in_a_bits_source; // @[Debug.scala 1741:27]
  wire [8:0] dmInner_auto_dmi_in_a_bits_address; // @[Debug.scala 1741:27]
  wire [3:0] dmInner_auto_dmi_in_a_bits_mask; // @[Debug.scala 1741:27]
  wire [31:0] dmInner_auto_dmi_in_a_bits_data; // @[Debug.scala 1741:27]
  wire  dmInner_auto_dmi_in_a_bits_corrupt; // @[Debug.scala 1741:27]
  wire  dmInner_auto_dmi_in_d_ready; // @[Debug.scala 1741:27]
  wire  dmInner_auto_dmi_in_d_valid; // @[Debug.scala 1741:27]
  wire [2:0] dmInner_auto_dmi_in_d_bits_opcode; // @[Debug.scala 1741:27]
  wire [1:0] dmInner_auto_dmi_in_d_bits_size; // @[Debug.scala 1741:27]
  wire  dmInner_auto_dmi_in_d_bits_source; // @[Debug.scala 1741:27]
  wire [31:0] dmInner_auto_dmi_in_d_bits_data; // @[Debug.scala 1741:27]
  wire  dmInner_io_dmactive; // @[Debug.scala 1741:27]
  wire  dmInner_io_innerCtrl_ready; // @[Debug.scala 1741:27]
  wire  dmInner_io_innerCtrl_valid; // @[Debug.scala 1741:27]
  wire  dmInner_io_innerCtrl_bits_resumereq; // @[Debug.scala 1741:27]
  wire [9:0] dmInner_io_innerCtrl_bits_hartsel; // @[Debug.scala 1741:27]
  wire  dmInner_io_innerCtrl_bits_ackhavereset; // @[Debug.scala 1741:27]
  wire  dmInner_io_innerCtrl_bits_hrmask_0; // @[Debug.scala 1741:27]
  wire  dmInner_io_hgDebugInt_0; // @[Debug.scala 1741:27]
  wire  dmiXing_clock; // @[Debug.scala 1742:27]
  wire [2:0] dmiXing_auto_in_a_mem_0_opcode; // @[Debug.scala 1742:27]
  wire [8:0] dmiXing_auto_in_a_mem_0_address; // @[Debug.scala 1742:27]
  wire [31:0] dmiXing_auto_in_a_mem_0_data; // @[Debug.scala 1742:27]
  wire  dmiXing_auto_in_a_ridx; // @[Debug.scala 1742:27]
  wire  dmiXing_auto_in_a_widx; // @[Debug.scala 1742:27]
  wire  dmiXing_auto_in_a_safe_ridx_valid; // @[Debug.scala 1742:27]
  wire  dmiXing_auto_in_a_safe_widx_valid; // @[Debug.scala 1742:27]
  wire  dmiXing_auto_in_a_safe_source_reset_n; // @[Debug.scala 1742:27]
  wire [2:0] dmiXing_auto_in_d_mem_0_opcode; // @[Debug.scala 1742:27]
  wire [1:0] dmiXing_auto_in_d_mem_0_size; // @[Debug.scala 1742:27]
  wire  dmiXing_auto_in_d_mem_0_source; // @[Debug.scala 1742:27]
  wire [31:0] dmiXing_auto_in_d_mem_0_data; // @[Debug.scala 1742:27]
  wire  dmiXing_auto_in_d_ridx; // @[Debug.scala 1742:27]
  wire  dmiXing_auto_in_d_widx; // @[Debug.scala 1742:27]
  wire  dmiXing_auto_in_d_safe_ridx_valid; // @[Debug.scala 1742:27]
  wire  dmiXing_auto_in_d_safe_widx_valid; // @[Debug.scala 1742:27]
  wire  dmiXing_auto_in_d_safe_sink_reset_n; // @[Debug.scala 1742:27]
  wire  dmiXing_auto_out_a_ready; // @[Debug.scala 1742:27]
  wire  dmiXing_auto_out_a_valid; // @[Debug.scala 1742:27]
  wire [2:0] dmiXing_auto_out_a_bits_opcode; // @[Debug.scala 1742:27]
  wire [2:0] dmiXing_auto_out_a_bits_param; // @[Debug.scala 1742:27]
  wire [1:0] dmiXing_auto_out_a_bits_size; // @[Debug.scala 1742:27]
  wire  dmiXing_auto_out_a_bits_source; // @[Debug.scala 1742:27]
  wire [8:0] dmiXing_auto_out_a_bits_address; // @[Debug.scala 1742:27]
  wire [3:0] dmiXing_auto_out_a_bits_mask; // @[Debug.scala 1742:27]
  wire [31:0] dmiXing_auto_out_a_bits_data; // @[Debug.scala 1742:27]
  wire  dmiXing_auto_out_a_bits_corrupt; // @[Debug.scala 1742:27]
  wire  dmiXing_auto_out_d_ready; // @[Debug.scala 1742:27]
  wire  dmiXing_auto_out_d_valid; // @[Debug.scala 1742:27]
  wire [2:0] dmiXing_auto_out_d_bits_opcode; // @[Debug.scala 1742:27]
  wire [1:0] dmiXing_auto_out_d_bits_size; // @[Debug.scala 1742:27]
  wire  dmiXing_auto_out_d_bits_source; // @[Debug.scala 1742:27]
  wire [31:0] dmiXing_auto_out_d_bits_data; // @[Debug.scala 1742:27]
  wire  dmactive_synced_dmactive_synced_dmactiveSync_clock; // @[ShiftReg.scala 45:23]
  wire  dmactive_synced_dmactive_synced_dmactiveSync_reset; // @[ShiftReg.scala 45:23]
  wire  dmactive_synced_dmactive_synced_dmactiveSync_io_d; // @[ShiftReg.scala 45:23]
  wire  dmactive_synced_dmactive_synced_dmactiveSync_io_q; // @[ShiftReg.scala 45:23]
  wire  dmactive_synced_dmInner_io_innerCtrl_sink_clock; // @[AsyncQueue.scala 207:22]
  wire  dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_valid; // @[AsyncQueue.scala 207:22]
  wire  dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_resumereq; // @[AsyncQueue.scala 207:22]
  wire [9:0] dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hartsel; // @[AsyncQueue.scala 207:22]
  wire  dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_ackhavereset; // @[AsyncQueue.scala 207:22]
  wire  dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_0; // @[AsyncQueue.scala 207:22]
  wire  dmactive_synced_dmInner_io_innerCtrl_sink_io_async_mem_0_resumereq; // @[AsyncQueue.scala 207:22]
  wire  dmactive_synced_dmInner_io_innerCtrl_sink_io_async_mem_0_ackhavereset; // @[AsyncQueue.scala 207:22]
  wire  dmactive_synced_dmInner_io_innerCtrl_sink_io_async_mem_0_hrmask_0; // @[AsyncQueue.scala 207:22]
  wire  dmactive_synced_dmInner_io_innerCtrl_sink_io_async_ridx; // @[AsyncQueue.scala 207:22]
  wire  dmactive_synced_dmInner_io_innerCtrl_sink_io_async_widx; // @[AsyncQueue.scala 207:22]
  wire  dmactive_synced_dmInner_io_innerCtrl_sink_io_async_safe_ridx_valid; // @[AsyncQueue.scala 207:22]
  wire  dmactive_synced_dmInner_io_innerCtrl_sink_io_async_safe_widx_valid; // @[AsyncQueue.scala 207:22]
  wire  dmactive_synced_dmInner_io_innerCtrl_sink_io_async_safe_source_reset_n; // @[AsyncQueue.scala 207:22]
  TLDebugModuleInner dmInner ( // @[Debug.scala 1741:27]
    .clock(dmInner_clock),
    .auto_tl_in_a_ready(dmInner_auto_tl_in_a_ready),
    .auto_tl_in_a_valid(dmInner_auto_tl_in_a_valid),
    .auto_tl_in_a_bits_opcode(dmInner_auto_tl_in_a_bits_opcode),
    .auto_tl_in_a_bits_param(dmInner_auto_tl_in_a_bits_param),
    .auto_tl_in_a_bits_size(dmInner_auto_tl_in_a_bits_size),
    .auto_tl_in_a_bits_source(dmInner_auto_tl_in_a_bits_source),
    .auto_tl_in_a_bits_address(dmInner_auto_tl_in_a_bits_address),
    .auto_tl_in_a_bits_mask(dmInner_auto_tl_in_a_bits_mask),
    .auto_tl_in_a_bits_data(dmInner_auto_tl_in_a_bits_data),
    .auto_tl_in_a_bits_corrupt(dmInner_auto_tl_in_a_bits_corrupt),
    .auto_tl_in_d_ready(dmInner_auto_tl_in_d_ready),
    .auto_tl_in_d_valid(dmInner_auto_tl_in_d_valid),
    .auto_tl_in_d_bits_opcode(dmInner_auto_tl_in_d_bits_opcode),
    .auto_tl_in_d_bits_size(dmInner_auto_tl_in_d_bits_size),
    .auto_tl_in_d_bits_source(dmInner_auto_tl_in_d_bits_source),
    .auto_tl_in_d_bits_data(dmInner_auto_tl_in_d_bits_data),
    .auto_dmi_in_a_ready(dmInner_auto_dmi_in_a_ready),
    .auto_dmi_in_a_valid(dmInner_auto_dmi_in_a_valid),
    .auto_dmi_in_a_bits_opcode(dmInner_auto_dmi_in_a_bits_opcode),
    .auto_dmi_in_a_bits_param(dmInner_auto_dmi_in_a_bits_param),
    .auto_dmi_in_a_bits_size(dmInner_auto_dmi_in_a_bits_size),
    .auto_dmi_in_a_bits_source(dmInner_auto_dmi_in_a_bits_source),
    .auto_dmi_in_a_bits_address(dmInner_auto_dmi_in_a_bits_address),
    .auto_dmi_in_a_bits_mask(dmInner_auto_dmi_in_a_bits_mask),
    .auto_dmi_in_a_bits_data(dmInner_auto_dmi_in_a_bits_data),
    .auto_dmi_in_a_bits_corrupt(dmInner_auto_dmi_in_a_bits_corrupt),
    .auto_dmi_in_d_ready(dmInner_auto_dmi_in_d_ready),
    .auto_dmi_in_d_valid(dmInner_auto_dmi_in_d_valid),
    .auto_dmi_in_d_bits_opcode(dmInner_auto_dmi_in_d_bits_opcode),
    .auto_dmi_in_d_bits_size(dmInner_auto_dmi_in_d_bits_size),
    .auto_dmi_in_d_bits_source(dmInner_auto_dmi_in_d_bits_source),
    .auto_dmi_in_d_bits_data(dmInner_auto_dmi_in_d_bits_data),
    .io_dmactive(dmInner_io_dmactive),
    .io_innerCtrl_ready(dmInner_io_innerCtrl_ready),
    .io_innerCtrl_valid(dmInner_io_innerCtrl_valid),
    .io_innerCtrl_bits_resumereq(dmInner_io_innerCtrl_bits_resumereq),
    .io_innerCtrl_bits_hartsel(dmInner_io_innerCtrl_bits_hartsel),
    .io_innerCtrl_bits_ackhavereset(dmInner_io_innerCtrl_bits_ackhavereset),
    .io_innerCtrl_bits_hrmask_0(dmInner_io_innerCtrl_bits_hrmask_0),
    .io_hgDebugInt_0(dmInner_io_hgDebugInt_0)
  );
  TLAsyncCrossingSink dmiXing ( // @[Debug.scala 1742:27]
    .clock(dmiXing_clock),
    .auto_in_a_mem_0_opcode(dmiXing_auto_in_a_mem_0_opcode),
    .auto_in_a_mem_0_address(dmiXing_auto_in_a_mem_0_address),
    .auto_in_a_mem_0_data(dmiXing_auto_in_a_mem_0_data),
    .auto_in_a_ridx(dmiXing_auto_in_a_ridx),
    .auto_in_a_widx(dmiXing_auto_in_a_widx),
    .auto_in_a_safe_ridx_valid(dmiXing_auto_in_a_safe_ridx_valid),
    .auto_in_a_safe_widx_valid(dmiXing_auto_in_a_safe_widx_valid),
    .auto_in_a_safe_source_reset_n(dmiXing_auto_in_a_safe_source_reset_n),
    .auto_in_d_mem_0_opcode(dmiXing_auto_in_d_mem_0_opcode),
    .auto_in_d_mem_0_size(dmiXing_auto_in_d_mem_0_size),
    .auto_in_d_mem_0_source(dmiXing_auto_in_d_mem_0_source),
    .auto_in_d_mem_0_data(dmiXing_auto_in_d_mem_0_data),
    .auto_in_d_ridx(dmiXing_auto_in_d_ridx),
    .auto_in_d_widx(dmiXing_auto_in_d_widx),
    .auto_in_d_safe_ridx_valid(dmiXing_auto_in_d_safe_ridx_valid),
    .auto_in_d_safe_widx_valid(dmiXing_auto_in_d_safe_widx_valid),
    .auto_in_d_safe_sink_reset_n(dmiXing_auto_in_d_safe_sink_reset_n),
    .auto_out_a_ready(dmiXing_auto_out_a_ready),
    .auto_out_a_valid(dmiXing_auto_out_a_valid),
    .auto_out_a_bits_opcode(dmiXing_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(dmiXing_auto_out_a_bits_param),
    .auto_out_a_bits_size(dmiXing_auto_out_a_bits_size),
    .auto_out_a_bits_source(dmiXing_auto_out_a_bits_source),
    .auto_out_a_bits_address(dmiXing_auto_out_a_bits_address),
    .auto_out_a_bits_mask(dmiXing_auto_out_a_bits_mask),
    .auto_out_a_bits_data(dmiXing_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(dmiXing_auto_out_a_bits_corrupt),
    .auto_out_d_ready(dmiXing_auto_out_d_ready),
    .auto_out_d_valid(dmiXing_auto_out_d_valid),
    .auto_out_d_bits_opcode(dmiXing_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(dmiXing_auto_out_d_bits_size),
    .auto_out_d_bits_source(dmiXing_auto_out_d_bits_source),
    .auto_out_d_bits_data(dmiXing_auto_out_d_bits_data)
  );
  AsyncResetSynchronizerShiftReg_w1_d3_i0 dmactive_synced_dmactive_synced_dmactiveSync ( // @[ShiftReg.scala 45:23]
    .clock(dmactive_synced_dmactive_synced_dmactiveSync_clock),
    .reset(dmactive_synced_dmactive_synced_dmactiveSync_reset),
    .io_d(dmactive_synced_dmactive_synced_dmactiveSync_io_d),
    .io_q(dmactive_synced_dmactive_synced_dmactiveSync_io_q)
  );
  AsyncQueueSink_3 dmactive_synced_dmInner_io_innerCtrl_sink ( // @[AsyncQueue.scala 207:22]
    .clock(dmactive_synced_dmInner_io_innerCtrl_sink_clock),
    .io_deq_valid(dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_valid),
    .io_deq_bits_resumereq(dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_resumereq),
    .io_deq_bits_hartsel(dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hartsel),
    .io_deq_bits_ackhavereset(dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_ackhavereset),
    .io_deq_bits_hrmask_0(dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_0),
    .io_async_mem_0_resumereq(dmactive_synced_dmInner_io_innerCtrl_sink_io_async_mem_0_resumereq),
    .io_async_mem_0_ackhavereset(dmactive_synced_dmInner_io_innerCtrl_sink_io_async_mem_0_ackhavereset),
    .io_async_mem_0_hrmask_0(dmactive_synced_dmInner_io_innerCtrl_sink_io_async_mem_0_hrmask_0),
    .io_async_ridx(dmactive_synced_dmInner_io_innerCtrl_sink_io_async_ridx),
    .io_async_widx(dmactive_synced_dmInner_io_innerCtrl_sink_io_async_widx),
    .io_async_safe_ridx_valid(dmactive_synced_dmInner_io_innerCtrl_sink_io_async_safe_ridx_valid),
    .io_async_safe_widx_valid(dmactive_synced_dmInner_io_innerCtrl_sink_io_async_safe_widx_valid),
    .io_async_safe_source_reset_n(dmactive_synced_dmInner_io_innerCtrl_sink_io_async_safe_source_reset_n)
  );
  assign auto_dmiXing_in_a_ridx = dmiXing_auto_in_a_ridx; // @[LazyModule.scala 309:16]
  assign auto_dmiXing_in_a_safe_ridx_valid = dmiXing_auto_in_a_safe_ridx_valid; // @[LazyModule.scala 309:16]
  assign auto_dmiXing_in_d_mem_0_opcode = dmiXing_auto_in_d_mem_0_opcode; // @[LazyModule.scala 309:16]
  assign auto_dmiXing_in_d_mem_0_size = dmiXing_auto_in_d_mem_0_size; // @[LazyModule.scala 309:16]
  assign auto_dmiXing_in_d_mem_0_source = dmiXing_auto_in_d_mem_0_source; // @[LazyModule.scala 309:16]
  assign auto_dmiXing_in_d_mem_0_data = dmiXing_auto_in_d_mem_0_data; // @[LazyModule.scala 309:16]
  assign auto_dmiXing_in_d_widx = dmiXing_auto_in_d_widx; // @[LazyModule.scala 309:16]
  assign auto_dmiXing_in_d_safe_widx_valid = dmiXing_auto_in_d_safe_widx_valid; // @[LazyModule.scala 309:16]
  assign auto_dmInner_tl_in_a_ready = dmInner_auto_tl_in_a_ready; // @[LazyModule.scala 309:16]
  assign auto_dmInner_tl_in_d_valid = dmInner_auto_tl_in_d_valid; // @[LazyModule.scala 309:16]
  assign auto_dmInner_tl_in_d_bits_opcode = dmInner_auto_tl_in_d_bits_opcode; // @[LazyModule.scala 309:16]
  assign auto_dmInner_tl_in_d_bits_size = dmInner_auto_tl_in_d_bits_size; // @[LazyModule.scala 309:16]
  assign auto_dmInner_tl_in_d_bits_source = dmInner_auto_tl_in_d_bits_source; // @[LazyModule.scala 309:16]
  assign auto_dmInner_tl_in_d_bits_data = dmInner_auto_tl_in_d_bits_data; // @[LazyModule.scala 309:16]
  assign io_innerCtrl_ridx = dmactive_synced_dmInner_io_innerCtrl_sink_io_async_ridx; // @[AsyncQueue.scala 208:19]
  assign io_innerCtrl_safe_ridx_valid = dmactive_synced_dmInner_io_innerCtrl_sink_io_async_safe_ridx_valid; // @[AsyncQueue.scala 208:19]
  assign io_hgDebugInt_0 = dmInner_io_hgDebugInt_0; // @[Debug.scala 1789:21]
  assign dmInner_clock = io_debug_clock; // @[Debug.scala 1782:28]
  assign dmInner_auto_tl_in_a_valid = auto_dmInner_tl_in_a_valid; // @[LazyModule.scala 309:16]
  assign dmInner_auto_tl_in_a_bits_opcode = auto_dmInner_tl_in_a_bits_opcode; // @[LazyModule.scala 309:16]
  assign dmInner_auto_tl_in_a_bits_param = auto_dmInner_tl_in_a_bits_param; // @[LazyModule.scala 309:16]
  assign dmInner_auto_tl_in_a_bits_size = auto_dmInner_tl_in_a_bits_size; // @[LazyModule.scala 309:16]
  assign dmInner_auto_tl_in_a_bits_source = auto_dmInner_tl_in_a_bits_source; // @[LazyModule.scala 309:16]
  assign dmInner_auto_tl_in_a_bits_address = auto_dmInner_tl_in_a_bits_address; // @[LazyModule.scala 309:16]
  assign dmInner_auto_tl_in_a_bits_mask = auto_dmInner_tl_in_a_bits_mask; // @[LazyModule.scala 309:16]
  assign dmInner_auto_tl_in_a_bits_data = auto_dmInner_tl_in_a_bits_data; // @[LazyModule.scala 309:16]
  assign dmInner_auto_tl_in_a_bits_corrupt = auto_dmInner_tl_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
  assign dmInner_auto_tl_in_d_ready = auto_dmInner_tl_in_d_ready; // @[LazyModule.scala 309:16]
  assign dmInner_auto_dmi_in_a_valid = dmiXing_auto_out_a_valid; // @[LazyModule.scala 296:16]
  assign dmInner_auto_dmi_in_a_bits_opcode = dmiXing_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign dmInner_auto_dmi_in_a_bits_param = dmiXing_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
  assign dmInner_auto_dmi_in_a_bits_size = dmiXing_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign dmInner_auto_dmi_in_a_bits_source = dmiXing_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign dmInner_auto_dmi_in_a_bits_address = dmiXing_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign dmInner_auto_dmi_in_a_bits_mask = dmiXing_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign dmInner_auto_dmi_in_a_bits_data = dmiXing_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign dmInner_auto_dmi_in_a_bits_corrupt = dmiXing_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
  assign dmInner_auto_dmi_in_d_ready = dmiXing_auto_out_d_ready; // @[LazyModule.scala 296:16]
  assign dmInner_io_dmactive = dmactive_synced_dmactive_synced_dmactiveSync_io_q; // @[ShiftReg.scala 48:{24,24}]
  assign dmInner_io_innerCtrl_valid = dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_valid; // @[Debug.scala 1787:35]
  assign dmInner_io_innerCtrl_bits_resumereq = dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_resumereq; // @[Debug.scala 1787:35]
  assign dmInner_io_innerCtrl_bits_hartsel = dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hartsel; // @[Debug.scala 1787:35]
  assign dmInner_io_innerCtrl_bits_ackhavereset = dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_ackhavereset; // @[Debug.scala 1787:35]
  assign dmInner_io_innerCtrl_bits_hrmask_0 = dmactive_synced_dmInner_io_innerCtrl_sink_io_deq_bits_hrmask_0; // @[Debug.scala 1787:35]
  assign dmiXing_clock = io_debug_clock; // @[Debug.scala 1777:16 LazyModule.scala 350:31]
  assign dmiXing_auto_in_a_mem_0_opcode = auto_dmiXing_in_a_mem_0_opcode; // @[LazyModule.scala 309:16]
  assign dmiXing_auto_in_a_mem_0_address = auto_dmiXing_in_a_mem_0_address; // @[LazyModule.scala 309:16]
  assign dmiXing_auto_in_a_mem_0_data = auto_dmiXing_in_a_mem_0_data; // @[LazyModule.scala 309:16]
  assign dmiXing_auto_in_a_widx = auto_dmiXing_in_a_widx; // @[LazyModule.scala 309:16]
  assign dmiXing_auto_in_a_safe_widx_valid = auto_dmiXing_in_a_safe_widx_valid; // @[LazyModule.scala 309:16]
  assign dmiXing_auto_in_a_safe_source_reset_n = auto_dmiXing_in_a_safe_source_reset_n; // @[LazyModule.scala 309:16]
  assign dmiXing_auto_in_d_ridx = auto_dmiXing_in_d_ridx; // @[LazyModule.scala 309:16]
  assign dmiXing_auto_in_d_safe_ridx_valid = auto_dmiXing_in_d_safe_ridx_valid; // @[LazyModule.scala 309:16]
  assign dmiXing_auto_in_d_safe_sink_reset_n = auto_dmiXing_in_d_safe_sink_reset_n; // @[LazyModule.scala 309:16]
  assign dmiXing_auto_out_a_ready = dmInner_auto_dmi_in_a_ready; // @[LazyModule.scala 296:16]
  assign dmiXing_auto_out_d_valid = dmInner_auto_dmi_in_d_valid; // @[LazyModule.scala 296:16]
  assign dmiXing_auto_out_d_bits_opcode = dmInner_auto_dmi_in_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign dmiXing_auto_out_d_bits_size = dmInner_auto_dmi_in_d_bits_size; // @[LazyModule.scala 296:16]
  assign dmiXing_auto_out_d_bits_source = dmInner_auto_dmi_in_d_bits_source; // @[LazyModule.scala 296:16]
  assign dmiXing_auto_out_d_bits_data = dmInner_auto_dmi_in_d_bits_data; // @[LazyModule.scala 296:16]
  assign dmactive_synced_dmactive_synced_dmactiveSync_clock = io_debug_clock; // @[Debug.scala 1777:16 LazyModule.scala 350:31]
  assign dmactive_synced_dmactive_synced_dmactiveSync_reset = 1'h0; // @[Debug.scala 1778:16 LazyModule.scala 352:31]
  assign dmactive_synced_dmactive_synced_dmactiveSync_io_d = io_dmactive; // @[ShiftReg.scala 47:16]
  assign dmactive_synced_dmInner_io_innerCtrl_sink_clock = io_debug_clock; // @[Debug.scala 1777:16 LazyModule.scala 350:31]
  assign dmactive_synced_dmInner_io_innerCtrl_sink_io_async_mem_0_resumereq = io_innerCtrl_mem_0_resumereq; // @[AsyncQueue.scala 208:19]
  assign dmactive_synced_dmInner_io_innerCtrl_sink_io_async_mem_0_ackhavereset = io_innerCtrl_mem_0_ackhavereset; // @[AsyncQueue.scala 208:19]
  assign dmactive_synced_dmInner_io_innerCtrl_sink_io_async_mem_0_hrmask_0 = io_innerCtrl_mem_0_hrmask_0; // @[AsyncQueue.scala 208:19]
  assign dmactive_synced_dmInner_io_innerCtrl_sink_io_async_widx = io_innerCtrl_widx; // @[AsyncQueue.scala 208:19]
  assign dmactive_synced_dmInner_io_innerCtrl_sink_io_async_safe_widx_valid = io_innerCtrl_safe_widx_valid; // @[AsyncQueue.scala 208:19]
  assign dmactive_synced_dmInner_io_innerCtrl_sink_io_async_safe_source_reset_n = io_innerCtrl_safe_source_reset_n; // @[AsyncQueue.scala 208:19]
endmodule
module TLDebugModule(
  output        auto_dmInner_dmInner_tl_in_a_ready,
  input         auto_dmInner_dmInner_tl_in_a_valid,
  input  [2:0]  auto_dmInner_dmInner_tl_in_a_bits_opcode,
  input  [2:0]  auto_dmInner_dmInner_tl_in_a_bits_param,
  input  [1:0]  auto_dmInner_dmInner_tl_in_a_bits_size,
  input  [6:0]  auto_dmInner_dmInner_tl_in_a_bits_source,
  input  [11:0] auto_dmInner_dmInner_tl_in_a_bits_address,
  input  [3:0]  auto_dmInner_dmInner_tl_in_a_bits_mask,
  input  [31:0] auto_dmInner_dmInner_tl_in_a_bits_data,
  input         auto_dmInner_dmInner_tl_in_a_bits_corrupt,
  input         auto_dmInner_dmInner_tl_in_d_ready,
  output        auto_dmInner_dmInner_tl_in_d_valid,
  output [2:0]  auto_dmInner_dmInner_tl_in_d_bits_opcode,
  output [1:0]  auto_dmInner_dmInner_tl_in_d_bits_size,
  output [6:0]  auto_dmInner_dmInner_tl_in_d_bits_source,
  output [31:0] auto_dmInner_dmInner_tl_in_d_bits_data,
  output        auto_dmOuter_intsource_out_sync_0,
  input         io_debug_clock,
  output        io_ctrl_ndreset,
  output        io_dmi_dmi_req_ready,
  input         io_dmi_dmi_req_valid,
  input  [6:0]  io_dmi_dmi_req_bits_addr,
  input  [31:0] io_dmi_dmi_req_bits_data,
  input  [1:0]  io_dmi_dmi_req_bits_op,
  input         io_dmi_dmi_resp_ready,
  output        io_dmi_dmi_resp_valid,
  output [31:0] io_dmi_dmi_resp_bits_data,
  output [1:0]  io_dmi_dmi_resp_bits_resp,
  input         io_dmi_dmiClock,
  input         io_dmi_dmiReset
);
  wire [2:0] dmOuter_auto_asource_out_a_mem_0_opcode; // @[Debug.scala 1819:53]
  wire [8:0] dmOuter_auto_asource_out_a_mem_0_address; // @[Debug.scala 1819:53]
  wire [31:0] dmOuter_auto_asource_out_a_mem_0_data; // @[Debug.scala 1819:53]
  wire  dmOuter_auto_asource_out_a_ridx; // @[Debug.scala 1819:53]
  wire  dmOuter_auto_asource_out_a_widx; // @[Debug.scala 1819:53]
  wire  dmOuter_auto_asource_out_a_safe_ridx_valid; // @[Debug.scala 1819:53]
  wire  dmOuter_auto_asource_out_a_safe_widx_valid; // @[Debug.scala 1819:53]
  wire  dmOuter_auto_asource_out_a_safe_source_reset_n; // @[Debug.scala 1819:53]
  wire [2:0] dmOuter_auto_asource_out_d_mem_0_opcode; // @[Debug.scala 1819:53]
  wire [1:0] dmOuter_auto_asource_out_d_mem_0_size; // @[Debug.scala 1819:53]
  wire  dmOuter_auto_asource_out_d_mem_0_source; // @[Debug.scala 1819:53]
  wire [31:0] dmOuter_auto_asource_out_d_mem_0_data; // @[Debug.scala 1819:53]
  wire  dmOuter_auto_asource_out_d_ridx; // @[Debug.scala 1819:53]
  wire  dmOuter_auto_asource_out_d_widx; // @[Debug.scala 1819:53]
  wire  dmOuter_auto_asource_out_d_safe_ridx_valid; // @[Debug.scala 1819:53]
  wire  dmOuter_auto_asource_out_d_safe_widx_valid; // @[Debug.scala 1819:53]
  wire  dmOuter_auto_asource_out_d_safe_sink_reset_n; // @[Debug.scala 1819:53]
  wire  dmOuter_auto_intsource_out_sync_0; // @[Debug.scala 1819:53]
  wire  dmOuter_io_dmi_clock; // @[Debug.scala 1819:53]
  wire  dmOuter_io_dmi_reset; // @[Debug.scala 1819:53]
  wire  dmOuter_io_dmi_req_ready; // @[Debug.scala 1819:53]
  wire  dmOuter_io_dmi_req_valid; // @[Debug.scala 1819:53]
  wire [6:0] dmOuter_io_dmi_req_bits_addr; // @[Debug.scala 1819:53]
  wire [31:0] dmOuter_io_dmi_req_bits_data; // @[Debug.scala 1819:53]
  wire [1:0] dmOuter_io_dmi_req_bits_op; // @[Debug.scala 1819:53]
  wire  dmOuter_io_dmi_resp_ready; // @[Debug.scala 1819:53]
  wire  dmOuter_io_dmi_resp_valid; // @[Debug.scala 1819:53]
  wire [31:0] dmOuter_io_dmi_resp_bits_data; // @[Debug.scala 1819:53]
  wire [1:0] dmOuter_io_dmi_resp_bits_resp; // @[Debug.scala 1819:53]
  wire  dmOuter_io_ctrl_ndreset; // @[Debug.scala 1819:53]
  wire  dmOuter_io_ctrl_dmactive; // @[Debug.scala 1819:53]
  wire  dmOuter_io_innerCtrl_mem_0_resumereq; // @[Debug.scala 1819:53]
  wire  dmOuter_io_innerCtrl_mem_0_ackhavereset; // @[Debug.scala 1819:53]
  wire  dmOuter_io_innerCtrl_mem_0_hrmask_0; // @[Debug.scala 1819:53]
  wire  dmOuter_io_innerCtrl_ridx; // @[Debug.scala 1819:53]
  wire  dmOuter_io_innerCtrl_widx; // @[Debug.scala 1819:53]
  wire  dmOuter_io_innerCtrl_safe_ridx_valid; // @[Debug.scala 1819:53]
  wire  dmOuter_io_innerCtrl_safe_widx_valid; // @[Debug.scala 1819:53]
  wire  dmOuter_io_innerCtrl_safe_source_reset_n; // @[Debug.scala 1819:53]
  wire  dmOuter_io_hgDebugInt_0; // @[Debug.scala 1819:53]
  wire [2:0] dmInner_auto_dmiXing_in_a_mem_0_opcode; // @[Debug.scala 1820:53]
  wire [8:0] dmInner_auto_dmiXing_in_a_mem_0_address; // @[Debug.scala 1820:53]
  wire [31:0] dmInner_auto_dmiXing_in_a_mem_0_data; // @[Debug.scala 1820:53]
  wire  dmInner_auto_dmiXing_in_a_ridx; // @[Debug.scala 1820:53]
  wire  dmInner_auto_dmiXing_in_a_widx; // @[Debug.scala 1820:53]
  wire  dmInner_auto_dmiXing_in_a_safe_ridx_valid; // @[Debug.scala 1820:53]
  wire  dmInner_auto_dmiXing_in_a_safe_widx_valid; // @[Debug.scala 1820:53]
  wire  dmInner_auto_dmiXing_in_a_safe_source_reset_n; // @[Debug.scala 1820:53]
  wire [2:0] dmInner_auto_dmiXing_in_d_mem_0_opcode; // @[Debug.scala 1820:53]
  wire [1:0] dmInner_auto_dmiXing_in_d_mem_0_size; // @[Debug.scala 1820:53]
  wire  dmInner_auto_dmiXing_in_d_mem_0_source; // @[Debug.scala 1820:53]
  wire [31:0] dmInner_auto_dmiXing_in_d_mem_0_data; // @[Debug.scala 1820:53]
  wire  dmInner_auto_dmiXing_in_d_ridx; // @[Debug.scala 1820:53]
  wire  dmInner_auto_dmiXing_in_d_widx; // @[Debug.scala 1820:53]
  wire  dmInner_auto_dmiXing_in_d_safe_ridx_valid; // @[Debug.scala 1820:53]
  wire  dmInner_auto_dmiXing_in_d_safe_widx_valid; // @[Debug.scala 1820:53]
  wire  dmInner_auto_dmiXing_in_d_safe_sink_reset_n; // @[Debug.scala 1820:53]
  wire  dmInner_auto_dmInner_tl_in_a_ready; // @[Debug.scala 1820:53]
  wire  dmInner_auto_dmInner_tl_in_a_valid; // @[Debug.scala 1820:53]
  wire [2:0] dmInner_auto_dmInner_tl_in_a_bits_opcode; // @[Debug.scala 1820:53]
  wire [2:0] dmInner_auto_dmInner_tl_in_a_bits_param; // @[Debug.scala 1820:53]
  wire [1:0] dmInner_auto_dmInner_tl_in_a_bits_size; // @[Debug.scala 1820:53]
  wire [6:0] dmInner_auto_dmInner_tl_in_a_bits_source; // @[Debug.scala 1820:53]
  wire [11:0] dmInner_auto_dmInner_tl_in_a_bits_address; // @[Debug.scala 1820:53]
  wire [3:0] dmInner_auto_dmInner_tl_in_a_bits_mask; // @[Debug.scala 1820:53]
  wire [31:0] dmInner_auto_dmInner_tl_in_a_bits_data; // @[Debug.scala 1820:53]
  wire  dmInner_auto_dmInner_tl_in_a_bits_corrupt; // @[Debug.scala 1820:53]
  wire  dmInner_auto_dmInner_tl_in_d_ready; // @[Debug.scala 1820:53]
  wire  dmInner_auto_dmInner_tl_in_d_valid; // @[Debug.scala 1820:53]
  wire [2:0] dmInner_auto_dmInner_tl_in_d_bits_opcode; // @[Debug.scala 1820:53]
  wire [1:0] dmInner_auto_dmInner_tl_in_d_bits_size; // @[Debug.scala 1820:53]
  wire [6:0] dmInner_auto_dmInner_tl_in_d_bits_source; // @[Debug.scala 1820:53]
  wire [31:0] dmInner_auto_dmInner_tl_in_d_bits_data; // @[Debug.scala 1820:53]
  wire  dmInner_io_debug_clock; // @[Debug.scala 1820:53]
  wire  dmInner_io_dmactive; // @[Debug.scala 1820:53]
  wire  dmInner_io_innerCtrl_mem_0_resumereq; // @[Debug.scala 1820:53]
  wire  dmInner_io_innerCtrl_mem_0_ackhavereset; // @[Debug.scala 1820:53]
  wire  dmInner_io_innerCtrl_mem_0_hrmask_0; // @[Debug.scala 1820:53]
  wire  dmInner_io_innerCtrl_ridx; // @[Debug.scala 1820:53]
  wire  dmInner_io_innerCtrl_widx; // @[Debug.scala 1820:53]
  wire  dmInner_io_innerCtrl_safe_ridx_valid; // @[Debug.scala 1820:53]
  wire  dmInner_io_innerCtrl_safe_widx_valid; // @[Debug.scala 1820:53]
  wire  dmInner_io_innerCtrl_safe_source_reset_n; // @[Debug.scala 1820:53]
  wire  dmInner_io_hgDebugInt_0; // @[Debug.scala 1820:53]
  TLDebugModuleOuterAsync dmOuter ( // @[Debug.scala 1819:53]
    .auto_asource_out_a_mem_0_opcode(dmOuter_auto_asource_out_a_mem_0_opcode),
    .auto_asource_out_a_mem_0_address(dmOuter_auto_asource_out_a_mem_0_address),
    .auto_asource_out_a_mem_0_data(dmOuter_auto_asource_out_a_mem_0_data),
    .auto_asource_out_a_ridx(dmOuter_auto_asource_out_a_ridx),
    .auto_asource_out_a_widx(dmOuter_auto_asource_out_a_widx),
    .auto_asource_out_a_safe_ridx_valid(dmOuter_auto_asource_out_a_safe_ridx_valid),
    .auto_asource_out_a_safe_widx_valid(dmOuter_auto_asource_out_a_safe_widx_valid),
    .auto_asource_out_a_safe_source_reset_n(dmOuter_auto_asource_out_a_safe_source_reset_n),
    .auto_asource_out_d_mem_0_opcode(dmOuter_auto_asource_out_d_mem_0_opcode),
    .auto_asource_out_d_mem_0_size(dmOuter_auto_asource_out_d_mem_0_size),
    .auto_asource_out_d_mem_0_source(dmOuter_auto_asource_out_d_mem_0_source),
    .auto_asource_out_d_mem_0_data(dmOuter_auto_asource_out_d_mem_0_data),
    .auto_asource_out_d_ridx(dmOuter_auto_asource_out_d_ridx),
    .auto_asource_out_d_widx(dmOuter_auto_asource_out_d_widx),
    .auto_asource_out_d_safe_ridx_valid(dmOuter_auto_asource_out_d_safe_ridx_valid),
    .auto_asource_out_d_safe_widx_valid(dmOuter_auto_asource_out_d_safe_widx_valid),
    .auto_asource_out_d_safe_sink_reset_n(dmOuter_auto_asource_out_d_safe_sink_reset_n),
    .auto_intsource_out_sync_0(dmOuter_auto_intsource_out_sync_0),
    .io_dmi_clock(dmOuter_io_dmi_clock),
    .io_dmi_reset(dmOuter_io_dmi_reset),
    .io_dmi_req_ready(dmOuter_io_dmi_req_ready),
    .io_dmi_req_valid(dmOuter_io_dmi_req_valid),
    .io_dmi_req_bits_addr(dmOuter_io_dmi_req_bits_addr),
    .io_dmi_req_bits_data(dmOuter_io_dmi_req_bits_data),
    .io_dmi_req_bits_op(dmOuter_io_dmi_req_bits_op),
    .io_dmi_resp_ready(dmOuter_io_dmi_resp_ready),
    .io_dmi_resp_valid(dmOuter_io_dmi_resp_valid),
    .io_dmi_resp_bits_data(dmOuter_io_dmi_resp_bits_data),
    .io_dmi_resp_bits_resp(dmOuter_io_dmi_resp_bits_resp),
    .io_ctrl_ndreset(dmOuter_io_ctrl_ndreset),
    .io_ctrl_dmactive(dmOuter_io_ctrl_dmactive),
    .io_innerCtrl_mem_0_resumereq(dmOuter_io_innerCtrl_mem_0_resumereq),
    .io_innerCtrl_mem_0_ackhavereset(dmOuter_io_innerCtrl_mem_0_ackhavereset),
    .io_innerCtrl_mem_0_hrmask_0(dmOuter_io_innerCtrl_mem_0_hrmask_0),
    .io_innerCtrl_ridx(dmOuter_io_innerCtrl_ridx),
    .io_innerCtrl_widx(dmOuter_io_innerCtrl_widx),
    .io_innerCtrl_safe_ridx_valid(dmOuter_io_innerCtrl_safe_ridx_valid),
    .io_innerCtrl_safe_widx_valid(dmOuter_io_innerCtrl_safe_widx_valid),
    .io_innerCtrl_safe_source_reset_n(dmOuter_io_innerCtrl_safe_source_reset_n),
    .io_hgDebugInt_0(dmOuter_io_hgDebugInt_0)
  );
  TLDebugModuleInnerAsync dmInner ( // @[Debug.scala 1820:53]
    .auto_dmiXing_in_a_mem_0_opcode(dmInner_auto_dmiXing_in_a_mem_0_opcode),
    .auto_dmiXing_in_a_mem_0_address(dmInner_auto_dmiXing_in_a_mem_0_address),
    .auto_dmiXing_in_a_mem_0_data(dmInner_auto_dmiXing_in_a_mem_0_data),
    .auto_dmiXing_in_a_ridx(dmInner_auto_dmiXing_in_a_ridx),
    .auto_dmiXing_in_a_widx(dmInner_auto_dmiXing_in_a_widx),
    .auto_dmiXing_in_a_safe_ridx_valid(dmInner_auto_dmiXing_in_a_safe_ridx_valid),
    .auto_dmiXing_in_a_safe_widx_valid(dmInner_auto_dmiXing_in_a_safe_widx_valid),
    .auto_dmiXing_in_a_safe_source_reset_n(dmInner_auto_dmiXing_in_a_safe_source_reset_n),
    .auto_dmiXing_in_d_mem_0_opcode(dmInner_auto_dmiXing_in_d_mem_0_opcode),
    .auto_dmiXing_in_d_mem_0_size(dmInner_auto_dmiXing_in_d_mem_0_size),
    .auto_dmiXing_in_d_mem_0_source(dmInner_auto_dmiXing_in_d_mem_0_source),
    .auto_dmiXing_in_d_mem_0_data(dmInner_auto_dmiXing_in_d_mem_0_data),
    .auto_dmiXing_in_d_ridx(dmInner_auto_dmiXing_in_d_ridx),
    .auto_dmiXing_in_d_widx(dmInner_auto_dmiXing_in_d_widx),
    .auto_dmiXing_in_d_safe_ridx_valid(dmInner_auto_dmiXing_in_d_safe_ridx_valid),
    .auto_dmiXing_in_d_safe_widx_valid(dmInner_auto_dmiXing_in_d_safe_widx_valid),
    .auto_dmiXing_in_d_safe_sink_reset_n(dmInner_auto_dmiXing_in_d_safe_sink_reset_n),
    .auto_dmInner_tl_in_a_ready(dmInner_auto_dmInner_tl_in_a_ready),
    .auto_dmInner_tl_in_a_valid(dmInner_auto_dmInner_tl_in_a_valid),
    .auto_dmInner_tl_in_a_bits_opcode(dmInner_auto_dmInner_tl_in_a_bits_opcode),
    .auto_dmInner_tl_in_a_bits_param(dmInner_auto_dmInner_tl_in_a_bits_param),
    .auto_dmInner_tl_in_a_bits_size(dmInner_auto_dmInner_tl_in_a_bits_size),
    .auto_dmInner_tl_in_a_bits_source(dmInner_auto_dmInner_tl_in_a_bits_source),
    .auto_dmInner_tl_in_a_bits_address(dmInner_auto_dmInner_tl_in_a_bits_address),
    .auto_dmInner_tl_in_a_bits_mask(dmInner_auto_dmInner_tl_in_a_bits_mask),
    .auto_dmInner_tl_in_a_bits_data(dmInner_auto_dmInner_tl_in_a_bits_data),
    .auto_dmInner_tl_in_a_bits_corrupt(dmInner_auto_dmInner_tl_in_a_bits_corrupt),
    .auto_dmInner_tl_in_d_ready(dmInner_auto_dmInner_tl_in_d_ready),
    .auto_dmInner_tl_in_d_valid(dmInner_auto_dmInner_tl_in_d_valid),
    .auto_dmInner_tl_in_d_bits_opcode(dmInner_auto_dmInner_tl_in_d_bits_opcode),
    .auto_dmInner_tl_in_d_bits_size(dmInner_auto_dmInner_tl_in_d_bits_size),
    .auto_dmInner_tl_in_d_bits_source(dmInner_auto_dmInner_tl_in_d_bits_source),
    .auto_dmInner_tl_in_d_bits_data(dmInner_auto_dmInner_tl_in_d_bits_data),
    .io_debug_clock(dmInner_io_debug_clock),
    .io_dmactive(dmInner_io_dmactive),
    .io_innerCtrl_mem_0_resumereq(dmInner_io_innerCtrl_mem_0_resumereq),
    .io_innerCtrl_mem_0_ackhavereset(dmInner_io_innerCtrl_mem_0_ackhavereset),
    .io_innerCtrl_mem_0_hrmask_0(dmInner_io_innerCtrl_mem_0_hrmask_0),
    .io_innerCtrl_ridx(dmInner_io_innerCtrl_ridx),
    .io_innerCtrl_widx(dmInner_io_innerCtrl_widx),
    .io_innerCtrl_safe_ridx_valid(dmInner_io_innerCtrl_safe_ridx_valid),
    .io_innerCtrl_safe_widx_valid(dmInner_io_innerCtrl_safe_widx_valid),
    .io_innerCtrl_safe_source_reset_n(dmInner_io_innerCtrl_safe_source_reset_n),
    .io_hgDebugInt_0(dmInner_io_hgDebugInt_0)
  );
  assign auto_dmInner_dmInner_tl_in_a_ready = dmInner_auto_dmInner_tl_in_a_ready; // @[LazyModule.scala 309:16]
  assign auto_dmInner_dmInner_tl_in_d_valid = dmInner_auto_dmInner_tl_in_d_valid; // @[LazyModule.scala 309:16]
  assign auto_dmInner_dmInner_tl_in_d_bits_opcode = dmInner_auto_dmInner_tl_in_d_bits_opcode; // @[LazyModule.scala 309:16]
  assign auto_dmInner_dmInner_tl_in_d_bits_size = dmInner_auto_dmInner_tl_in_d_bits_size; // @[LazyModule.scala 309:16]
  assign auto_dmInner_dmInner_tl_in_d_bits_source = dmInner_auto_dmInner_tl_in_d_bits_source; // @[LazyModule.scala 309:16]
  assign auto_dmInner_dmInner_tl_in_d_bits_data = dmInner_auto_dmInner_tl_in_d_bits_data; // @[LazyModule.scala 309:16]
  assign auto_dmOuter_intsource_out_sync_0 = dmOuter_auto_intsource_out_sync_0; // @[LazyModule.scala 311:12]
  assign io_ctrl_ndreset = dmOuter_io_ctrl_ndreset; // @[Debug.scala 1879:13]
  assign io_dmi_dmi_req_ready = dmOuter_io_dmi_req_ready; // @[Debug.scala 1857:18]
  assign io_dmi_dmi_resp_valid = dmOuter_io_dmi_resp_valid; // @[Debug.scala 1857:18]
  assign io_dmi_dmi_resp_bits_data = dmOuter_io_dmi_resp_bits_data; // @[Debug.scala 1857:18]
  assign io_dmi_dmi_resp_bits_resp = dmOuter_io_dmi_resp_bits_resp; // @[Debug.scala 1857:18]
  assign dmOuter_auto_asource_out_a_ridx = dmInner_auto_dmiXing_in_a_ridx; // @[LazyModule.scala 298:16]
  assign dmOuter_auto_asource_out_a_safe_ridx_valid = dmInner_auto_dmiXing_in_a_safe_ridx_valid; // @[LazyModule.scala 298:16]
  assign dmOuter_auto_asource_out_d_mem_0_opcode = dmInner_auto_dmiXing_in_d_mem_0_opcode; // @[LazyModule.scala 298:16]
  assign dmOuter_auto_asource_out_d_mem_0_size = dmInner_auto_dmiXing_in_d_mem_0_size; // @[LazyModule.scala 298:16]
  assign dmOuter_auto_asource_out_d_mem_0_source = dmInner_auto_dmiXing_in_d_mem_0_source; // @[LazyModule.scala 298:16]
  assign dmOuter_auto_asource_out_d_mem_0_data = dmInner_auto_dmiXing_in_d_mem_0_data; // @[LazyModule.scala 298:16]
  assign dmOuter_auto_asource_out_d_widx = dmInner_auto_dmiXing_in_d_widx; // @[LazyModule.scala 298:16]
  assign dmOuter_auto_asource_out_d_safe_widx_valid = dmInner_auto_dmiXing_in_d_safe_widx_valid; // @[LazyModule.scala 298:16]
  assign dmOuter_io_dmi_clock = io_dmi_dmiClock; // @[Debug.scala 1859:35]
  assign dmOuter_io_dmi_reset = io_dmi_dmiReset; // @[Debug.scala 1858:35]
  assign dmOuter_io_dmi_req_valid = io_dmi_dmi_req_valid; // @[Debug.scala 1857:18]
  assign dmOuter_io_dmi_req_bits_addr = io_dmi_dmi_req_bits_addr; // @[Debug.scala 1857:18]
  assign dmOuter_io_dmi_req_bits_data = io_dmi_dmi_req_bits_data; // @[Debug.scala 1857:18]
  assign dmOuter_io_dmi_req_bits_op = io_dmi_dmi_req_bits_op; // @[Debug.scala 1857:18]
  assign dmOuter_io_dmi_resp_ready = io_dmi_dmi_resp_ready; // @[Debug.scala 1857:18]
  assign dmOuter_io_innerCtrl_ridx = dmInner_io_innerCtrl_ridx; // @[Debug.scala 1874:36]
  assign dmOuter_io_innerCtrl_safe_ridx_valid = dmInner_io_innerCtrl_safe_ridx_valid; // @[Debug.scala 1874:36]
  assign dmOuter_io_hgDebugInt_0 = dmInner_io_hgDebugInt_0; // @[Debug.scala 1877:36]
  assign dmInner_auto_dmiXing_in_a_mem_0_opcode = dmOuter_auto_asource_out_a_mem_0_opcode; // @[LazyModule.scala 298:16]
  assign dmInner_auto_dmiXing_in_a_mem_0_address = dmOuter_auto_asource_out_a_mem_0_address; // @[LazyModule.scala 298:16]
  assign dmInner_auto_dmiXing_in_a_mem_0_data = dmOuter_auto_asource_out_a_mem_0_data; // @[LazyModule.scala 298:16]
  assign dmInner_auto_dmiXing_in_a_widx = dmOuter_auto_asource_out_a_widx; // @[LazyModule.scala 298:16]
  assign dmInner_auto_dmiXing_in_a_safe_widx_valid = dmOuter_auto_asource_out_a_safe_widx_valid; // @[LazyModule.scala 298:16]
  assign dmInner_auto_dmiXing_in_a_safe_source_reset_n = dmOuter_auto_asource_out_a_safe_source_reset_n; // @[LazyModule.scala 298:16]
  assign dmInner_auto_dmiXing_in_d_ridx = dmOuter_auto_asource_out_d_ridx; // @[LazyModule.scala 298:16]
  assign dmInner_auto_dmiXing_in_d_safe_ridx_valid = dmOuter_auto_asource_out_d_safe_ridx_valid; // @[LazyModule.scala 298:16]
  assign dmInner_auto_dmiXing_in_d_safe_sink_reset_n = dmOuter_auto_asource_out_d_safe_sink_reset_n; // @[LazyModule.scala 298:16]
  assign dmInner_auto_dmInner_tl_in_a_valid = auto_dmInner_dmInner_tl_in_a_valid; // @[LazyModule.scala 309:16]
  assign dmInner_auto_dmInner_tl_in_a_bits_opcode = auto_dmInner_dmInner_tl_in_a_bits_opcode; // @[LazyModule.scala 309:16]
  assign dmInner_auto_dmInner_tl_in_a_bits_param = auto_dmInner_dmInner_tl_in_a_bits_param; // @[LazyModule.scala 309:16]
  assign dmInner_auto_dmInner_tl_in_a_bits_size = auto_dmInner_dmInner_tl_in_a_bits_size; // @[LazyModule.scala 309:16]
  assign dmInner_auto_dmInner_tl_in_a_bits_source = auto_dmInner_dmInner_tl_in_a_bits_source; // @[LazyModule.scala 309:16]
  assign dmInner_auto_dmInner_tl_in_a_bits_address = auto_dmInner_dmInner_tl_in_a_bits_address; // @[LazyModule.scala 309:16]
  assign dmInner_auto_dmInner_tl_in_a_bits_mask = auto_dmInner_dmInner_tl_in_a_bits_mask; // @[LazyModule.scala 309:16]
  assign dmInner_auto_dmInner_tl_in_a_bits_data = auto_dmInner_dmInner_tl_in_a_bits_data; // @[LazyModule.scala 309:16]
  assign dmInner_auto_dmInner_tl_in_a_bits_corrupt = auto_dmInner_dmInner_tl_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
  assign dmInner_auto_dmInner_tl_in_d_ready = auto_dmInner_dmInner_tl_in_d_ready; // @[LazyModule.scala 309:16]
  assign dmInner_io_debug_clock = io_debug_clock; // @[Debug.scala 1870:35]
  assign dmInner_io_dmactive = dmOuter_io_ctrl_dmactive; // @[Debug.scala 1875:36]
  assign dmInner_io_innerCtrl_mem_0_resumereq = dmOuter_io_innerCtrl_mem_0_resumereq; // @[Debug.scala 1874:36]
  assign dmInner_io_innerCtrl_mem_0_ackhavereset = dmOuter_io_innerCtrl_mem_0_ackhavereset; // @[Debug.scala 1874:36]
  assign dmInner_io_innerCtrl_mem_0_hrmask_0 = dmOuter_io_innerCtrl_mem_0_hrmask_0; // @[Debug.scala 1874:36]
  assign dmInner_io_innerCtrl_widx = dmOuter_io_innerCtrl_widx; // @[Debug.scala 1874:36]
  assign dmInner_io_innerCtrl_safe_widx_valid = dmOuter_io_innerCtrl_safe_widx_valid; // @[Debug.scala 1874:36]
  assign dmInner_io_innerCtrl_safe_source_reset_n = dmOuter_io_innerCtrl_safe_source_reset_n; // @[Debug.scala 1874:36]
endmodule
module BundleBridgeNexus_15(
  output  auto_out
);
  wire  outputs_0 = 1'h0; // @[HasTiles.scala 162:32]
  assign auto_out = outputs_0; // @[Nodes.scala 1207:84 BundleBridge.scala 151:67]
endmodule
module AsyncResetRegVec_w2_i0(
  input        clock,
  input        reset,
  input  [1:0] io_d,
  output [1:0] io_q
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg [1:0] reg_; // @[AsyncResetReg.scala 64:50]
  assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[AsyncResetReg.scala 65:16]
      reg_ <= 2'h0; // @[AsyncResetReg.scala 66:9]
    end else begin
      reg_ <= io_d; // @[AsyncResetReg.scala 64:50]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  reg_ = _RAND_0[1:0];
`endif // RANDOMIZE_REG_INIT
  if (reset) begin
    reg_ = 2'h0;
  end
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module IntSyncCrossingSource_5(
  input   clock,
  input   reset,
  input   auto_in_0,
  input   auto_in_1,
  output  auto_out_sync_0,
  output  auto_out_sync_1
);
  wire  reg__clock; // @[AsyncResetReg.scala 89:21]
  wire  reg__reset; // @[AsyncResetReg.scala 89:21]
  wire [1:0] reg__io_d; // @[AsyncResetReg.scala 89:21]
  wire [1:0] reg__io_q; // @[AsyncResetReg.scala 89:21]
  AsyncResetRegVec_w2_i0 reg_ ( // @[AsyncResetReg.scala 89:21]
    .clock(reg__clock),
    .reset(reg__reset),
    .io_d(reg__io_d),
    .io_q(reg__io_q)
  );
  assign auto_out_sync_0 = reg__io_q[0]; // @[Crossing.scala 41:52]
  assign auto_out_sync_1 = reg__io_q[1]; // @[Crossing.scala 41:52]
  assign reg__clock = clock;
  assign reg__reset = reset;
  assign reg__io_d = {auto_in_1,auto_in_0}; // @[Cat.scala 31:58]
endmodule
module TLMonitor_55(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [1:0]  io_in_a_bits_size,
  input  [6:0]  io_in_a_bits_source,
  input  [28:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_size,
  input  [6:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [95:0] _RAND_10;
  reg [383:0] _RAND_11;
  reg [383:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [95:0] _RAND_16;
  reg [383:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T_4 = io_in_a_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire [4:0] _is_aligned_mask_T_1 = 5'h3 << io_in_a_bits_size; // @[package.scala 234:77]
  wire [1:0] is_aligned_mask = ~_is_aligned_mask_T_1[1:0]; // @[package.scala 234:46]
  wire [28:0] _GEN_71 = {{27'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 2'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [28:0] _T_33 = io_in_a_bits_address ^ 29'h10000000; // @[Parameters.scala 137:31]
  wire [29:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
  wire [29:0] _T_36 = $signed(_T_34) & -30'sh1000; // @[Parameters.scala 137:52]
  wire  _T_37 = $signed(_T_36) == 30'sh0; // @[Parameters.scala 137:67]
  wire  _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_74 = _T_73 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_164 = io_in_a_bits_size <= 2'h2; // @[Parameters.scala 92:42]
  wire  _T_172 = _T_164 & _T_37; // @[Parameters.scala 670:56]
  wire  _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_218 = _source_ok_T_4 & _T_172; // @[Monitor.scala 115:71]
  wire  _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_273 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_274 = io_in_a_bits_mask & _T_273; // @[Monitor.scala 127:31]
  wire  _T_275 = _T_274 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_279 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_347 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_355 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_385 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_397 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_10 = io_in_d_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire  _T_401 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_405 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 312:27]
  wire  _T_421 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_449 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_478 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_495 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_513 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [1:0] size; // @[Monitor.scala 386:22]
  reg [6:0] source; // @[Monitor.scala 387:22]
  reg [28:0] address; // @[Monitor.scala 388:22]
  wire  _T_543 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_544 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_548 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_552 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_556 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_560 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] size_1; // @[Monitor.scala 537:22]
  reg [6:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_567 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_568 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_576 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_580 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [95:0] inflight; // @[Monitor.scala 611:27]
  reg [383:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [383:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [8:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [9:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [383:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [383:0] _GEN_73 = {{368'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[383:1]}; // @[Monitor.scala 634:152]
  wire [383:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [383:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
  wire [383:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[383:1]}; // @[Monitor.scala 638:144]
  wire  _T_594 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [127:0] _a_set_wo_ready_T = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire [127:0] _GEN_15 = io_in_a_valid & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 648:71 649:22]
  wire  _T_597 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
  wire [8:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [9:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [1026:0] _GEN_1 = {{1023'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [1026:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
  wire [1025:0] _GEN_2 = {{1023'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [1025:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [95:0] _T_599 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_601 = ~_T_599[0]; // @[Monitor.scala 658:17]
  wire [127:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 652:72 653:28]
  wire [1026:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 1027'h0; // @[Monitor.scala 652:72 656:28]
  wire [1025:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 1026'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_605 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_607 = ~_T_401; // @[Monitor.scala 671:74]
  wire  _T_608 = io_in_d_valid & d_first_1 & ~_T_401; // @[Monitor.scala 671:71]
  wire [127:0] _d_clr_wo_ready_T = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [127:0] _GEN_21 = io_in_d_valid & d_first_1 & ~_T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 671:90 672:22]
  wire [1038:0] _GEN_3 = {{1023'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [1038:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [127:0] _GEN_22 = d_first_done & d_first_1 & _T_607 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 675:91 676:21]
  wire [1038:0] _GEN_23 = d_first_done & d_first_1 & _T_607 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_594 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [95:0] _T_618 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_620 = _T_618[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_625 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_626 = io_in_d_bits_opcode == _GEN_32 | _T_625; // @[Monitor.scala 685:77]
  wire  _T_630 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_637 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_638 = io_in_d_bits_opcode == _GEN_48 | _T_637; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_642 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_652 = _T_605 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_607; // @[Monitor.scala 694:116]
  wire  _T_654 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [95:0] a_set_wo_ready = _GEN_15[95:0];
  wire [95:0] d_clr_wo_ready = _GEN_21[95:0];
  wire  _T_661 = a_set_wo_ready != d_clr_wo_ready | ~(|a_set_wo_ready); // @[Monitor.scala 699:48]
  wire [95:0] a_set = _GEN_16[95:0];
  wire [95:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [95:0] d_clr = _GEN_22[95:0];
  wire [95:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [95:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [383:0] a_opcodes_set = _GEN_19[383:0];
  wire [383:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [383:0] d_opcodes_clr = _GEN_23[383:0];
  wire [383:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [383:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [383:0] a_sizes_set = _GEN_20[383:0];
  wire [383:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [383:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_670 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [95:0] inflight_1; // @[Monitor.scala 723:35]
  reg [383:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [383:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [383:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
  wire [383:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[383:1]}; // @[Monitor.scala 747:146]
  wire  _T_696 = io_in_d_valid & d_first_2 & _T_401; // @[Monitor.scala 779:71]
  wire [127:0] _GEN_67 = d_first_done & d_first_2 & _T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 783:90 784:21]
  wire [1038:0] _GEN_68 = d_first_done & d_first_2 & _T_401 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 783:90 785:21]
  wire [95:0] _T_704 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_714 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [95:0] d_clr_1 = _GEN_67[95:0];
  wire [95:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [95:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [383:0] d_opcodes_clr_1 = _GEN_68[383:0];
  wire [383:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [383:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_739 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 1'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= 1'h0;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 96'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 384'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 384'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 1'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= 1'h0;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 96'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 384'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= 1'h0;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (d_first_done) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_172 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_172) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_275 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_275) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_309 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_309) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_347 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_347) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_385 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_397 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_397) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_478 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_478 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_495 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_495 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_513 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_513 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_544 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_544) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_548 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_548) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_552 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_552) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_556 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_556) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_560 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_560) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_568 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_568) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_576 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_576) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_580 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_580) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_601 & (_T_597 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_597 & ~reset & ~_T_601) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_620 & (_T_608 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & _T_2 & ~_T_620) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_626 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_626) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_630 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_630) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_638 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_638) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_642 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_642) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_654 & (_T_652 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_652 & _T_2 & ~_T_654) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_661 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_2 & ~_T_661) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_670 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_670) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_704[0] & (_T_696 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_696 & _T_2 & ~_T_704[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_714 & (_T_696 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_696 & _T_2 & ~_T_714) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_739 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_739) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at MockAONWrapper.scala:48:23)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[6:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[28:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[6:0];
  _RAND_10 = {3{`RANDOM}};
  inflight = _RAND_10[95:0];
  _RAND_11 = {12{`RANDOM}};
  inflight_opcodes = _RAND_11[383:0];
  _RAND_12 = {12{`RANDOM}};
  inflight_sizes = _RAND_12[383:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {3{`RANDOM}};
  inflight_1 = _RAND_16[95:0];
  _RAND_17 = {12{`RANDOM}};
  inflight_sizes_1 = _RAND_17[383:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module RTC(
  input         clock,
  input         reset,
  input         scale_io_regs_cfg_write__countAlways,
  input  [3:0]  scale_io_regs_cfg_write__scale,
  output        scale_io_regs_cfg_read_ip_0,
  output        scale_io_regs_cfg_read_countAlways,
  output [3:0]  scale_io_regs_cfg_read_scale,
  input         scale_io_regs_cfg_write_countAlways,
  input         scale_io_regs_cfg_write_scale,
  input         scale_io_regs_countLo_write_valid,
  input  [31:0] scale_io_regs_countLo_write_bits,
  output [31:0] scale_io_regs_countLo_read,
  input         scale_io_regs_countHi_write_valid,
  input  [31:0] scale_io_regs_countHi_write_bits,
  output [31:0] scale_io_regs_countHi_read,
  output [31:0] scale_io_regs_s_read,
  input         scale_io_regs_cmp_0_write_valid,
  input  [31:0] scale_io_regs_cmp_0_write_bits,
  output [31:0] scale_io_regs_cmp_0_read,
  output        scale_io_ip_0
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [63:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
  wire  countAlways_reg_clock; // @[AsyncResetReg.scala 89:21]
  wire  countAlways_reg_reset; // @[AsyncResetReg.scala 89:21]
  wire  countAlways_reg_io_d; // @[AsyncResetReg.scala 89:21]
  wire  countAlways_reg_io_q; // @[AsyncResetReg.scala 89:21]
  wire  countAlways_reg_io_en; // @[AsyncResetReg.scala 89:21]
  reg [3:0] scale; // @[Reg.scala 16:16]
  reg [31:0] cmp_0; // @[Reg.scala 16:16]
  wire  countAlways = countAlways_reg_io_q; // @[RTC.scala 22:123]
  reg [5:0] small_; // @[Counters.scala 45:37]
  wire [5:0] _GEN_10 = {{5'd0}, countAlways}; // @[Counters.scala 46:33]
  wire [6:0] nextSmall = small_ + _GEN_10; // @[Counters.scala 46:33]
  reg [41:0] large_; // @[Counters.scala 50:27]
  wire [41:0] _large_r_T_1 = large_ + 42'h1; // @[Counters.scala 51:55]
  wire [41:0] _GEN_3 = nextSmall[6] ? _large_r_T_1 : large_; // @[Counters.scala 50:27 51:{46,50}]
  wire [47:0] value = {large_,small_}; // @[Cat.scala 31:58]
  wire [47:0] _s_T = value >> scale; // @[Timer.scala 209:28]
  wire [31:0] s = _s_T[31:0]; // @[Timer.scala 209:37]
  wire [47:0] _T_3 = {value[47:32],scale_io_regs_countLo_write_bits}; // @[Cat.scala 31:58]
  wire [47:0] _GEN_6 = scale_io_regs_countLo_write_valid ? _T_3 : {{41'd0}, nextSmall}; // @[Timer.scala 214:50 Counters.scala 65:11]
  wire [41:0] _GEN_7 = scale_io_regs_countLo_write_valid ? _T_3[47:6] : _GEN_3; // @[Timer.scala 214:50 Counters.scala 66:23]
  wire [63:0] _T_6 = {scale_io_regs_countHi_write_bits,value[31:0]}; // @[Cat.scala 31:58]
  wire [63:0] _GEN_8 = scale_io_regs_countHi_write_valid ? _T_6 : {{16'd0}, _GEN_6}; // @[Timer.scala 215:77 Counters.scala 65:11]
  wire [57:0] _GEN_9 = scale_io_regs_countHi_write_valid ? _T_6[63:6] : {{16'd0}, _GEN_7}; // @[Timer.scala 215:77 Counters.scala 66:23]
  reg  ip_0; // @[RTC.scala 20:43]
  AsyncResetRegVec_w1_i0 countAlways_reg ( // @[AsyncResetReg.scala 89:21]
    .clock(countAlways_reg_clock),
    .reset(countAlways_reg_reset),
    .io_d(countAlways_reg_io_d),
    .io_q(countAlways_reg_io_q),
    .io_en(countAlways_reg_io_en)
  );
  assign scale_io_regs_cfg_read_ip_0 = ip_0; // @[Timer.scala 218:23]
  assign scale_io_regs_cfg_read_countAlways = countAlways_reg_io_q; // @[RTC.scala 22:123]
  assign scale_io_regs_cfg_read_scale = scale; // @[Timer.scala 227:26]
  assign scale_io_regs_countLo_read = value[31:0]; // @[Timer.scala 229:24]
  assign scale_io_regs_countHi_read = {{16'd0}, value[47:32]}; // @[Timer.scala 230:24]
  assign scale_io_regs_s_read = _s_T[31:0]; // @[Timer.scala 209:37]
  assign scale_io_regs_cmp_0_read = cmp_0; // @[Timer.scala 232:53]
  assign scale_io_ip_0 = ip_0; // @[Timer.scala 235:9]
  assign countAlways_reg_clock = clock;
  assign countAlways_reg_reset = reset;
  assign countAlways_reg_io_d = scale_io_regs_cfg_write__countAlways; // @[AsyncResetReg.scala 91:14]
  assign countAlways_reg_io_en = scale_io_regs_cfg_write_countAlways; // @[RTC.scala 22:111]
  always @(posedge clock) begin
    if (scale_io_regs_cfg_write_scale) begin // @[Reg.scala 17:18]
      scale <= scale_io_regs_cfg_write__scale; // @[Reg.scala 17:22]
    end
    if (scale_io_regs_cmp_0_write_valid) begin // @[Reg.scala 17:18]
      cmp_0 <= scale_io_regs_cmp_0_write_bits; // @[Reg.scala 17:22]
    end
    if (reset) begin // @[Counters.scala 45:37]
      small_ <= 6'h0; // @[Counters.scala 45:37]
    end else begin
      small_ <= _GEN_8[5:0];
    end
    if (reset) begin // @[Counters.scala 50:27]
      large_ <= 42'h0; // @[Counters.scala 50:27]
    end else begin
      large_ <= _GEN_9[41:0];
    end
    ip_0 <= s >= cmp_0; // @[Timer.scala 211:90]
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  scale = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  cmp_0 = _RAND_1[31:0];
  _RAND_2 = {1{`RANDOM}};
  small_ = _RAND_2[5:0];
  _RAND_3 = {2{`RANDOM}};
  large_ = _RAND_3[41:0];
  _RAND_4 = {1{`RANDOM}};
  ip_0 = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module PMUCore(
  input         clock,
  input         reset,
  input         io_wakeup_rtc,
  output        io_control_valid,
  output        io_control_bits_hfclkrst,
  output        io_control_bits_corerst,
  output        io_control_bits_reserved1,
  output        io_control_bits_vddpaden,
  output        io_control_bits_reserved0,
  input  [1:0]  io_resetCause,
  input         io_regs_ie_write_valid,
  input  [3:0]  io_regs_ie_write_bits,
  output [3:0]  io_regs_ie_read,
  input         io_regs_cause_write_valid,
  output [31:0] io_regs_cause_read,
  input         io_regs_sleep_write_valid,
  input         io_regs_key_write_valid,
  input  [31:0] io_regs_key_write_bits,
  output [31:0] io_regs_key_read,
  input         io_regs_wakeupProgram_0_write_valid,
  input  [31:0] io_regs_wakeupProgram_0_write_bits,
  output [31:0] io_regs_wakeupProgram_0_read,
  input         io_regs_wakeupProgram_1_write_valid,
  input  [31:0] io_regs_wakeupProgram_1_write_bits,
  output [31:0] io_regs_wakeupProgram_1_read,
  input         io_regs_wakeupProgram_2_write_valid,
  input  [31:0] io_regs_wakeupProgram_2_write_bits,
  output [31:0] io_regs_wakeupProgram_2_read,
  input         io_regs_wakeupProgram_3_write_valid,
  input  [31:0] io_regs_wakeupProgram_3_write_bits,
  output [31:0] io_regs_wakeupProgram_3_read,
  input         io_regs_wakeupProgram_4_write_valid,
  input  [31:0] io_regs_wakeupProgram_4_write_bits,
  output [31:0] io_regs_wakeupProgram_4_read,
  input         io_regs_wakeupProgram_5_write_valid,
  input  [31:0] io_regs_wakeupProgram_5_write_bits,
  output [31:0] io_regs_wakeupProgram_5_read,
  input         io_regs_wakeupProgram_6_write_valid,
  input  [31:0] io_regs_wakeupProgram_6_write_bits,
  output [31:0] io_regs_wakeupProgram_6_read,
  input         io_regs_wakeupProgram_7_write_valid,
  input  [31:0] io_regs_wakeupProgram_7_write_bits,
  output [31:0] io_regs_wakeupProgram_7_read,
  input         io_regs_sleepProgram_0_write_valid,
  input  [31:0] io_regs_sleepProgram_0_write_bits,
  output [31:0] io_regs_sleepProgram_0_read,
  input         io_regs_sleepProgram_1_write_valid,
  input  [31:0] io_regs_sleepProgram_1_write_bits,
  output [31:0] io_regs_sleepProgram_1_read,
  input         io_regs_sleepProgram_2_write_valid,
  input  [31:0] io_regs_sleepProgram_2_write_bits,
  output [31:0] io_regs_sleepProgram_2_read,
  input         io_regs_sleepProgram_3_write_valid,
  input  [31:0] io_regs_sleepProgram_3_write_bits,
  output [31:0] io_regs_sleepProgram_3_read,
  input         io_regs_sleepProgram_4_write_valid,
  input  [31:0] io_regs_sleepProgram_4_write_bits,
  output [31:0] io_regs_sleepProgram_4_read,
  input         io_regs_sleepProgram_5_write_valid,
  input  [31:0] io_regs_sleepProgram_5_write_bits,
  output [31:0] io_regs_sleepProgram_5_read,
  input         io_regs_sleepProgram_6_write_valid,
  input  [31:0] io_regs_sleepProgram_6_write_bits,
  output [31:0] io_regs_sleepProgram_6_read,
  input         io_regs_sleepProgram_7_write_valid,
  input  [31:0] io_regs_sleepProgram_7_write_bits,
  output [31:0] io_regs_sleepProgram_7_read
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
`endif // RANDOMIZE_REG_INIT
  reg  run; // @[PMU.scala 69:16]
  reg  awake; // @[PMU.scala 70:18]
  wire  _unlocked_writeAny_T_6 = io_regs_sleepProgram_0_write_valid | io_regs_sleepProgram_1_write_valid |
    io_regs_sleepProgram_2_write_valid | io_regs_sleepProgram_3_write_valid | io_regs_sleepProgram_4_write_valid |
    io_regs_sleepProgram_5_write_valid | io_regs_sleepProgram_6_write_valid | io_regs_sleepProgram_7_write_valid; // @[WatchdogTimer.scala 17:74]
  wire  _unlocked_writeAny_T_13 = io_regs_wakeupProgram_0_write_valid | io_regs_wakeupProgram_1_write_valid |
    io_regs_wakeupProgram_2_write_valid | io_regs_wakeupProgram_3_write_valid | io_regs_wakeupProgram_4_write_valid |
    io_regs_wakeupProgram_5_write_valid | io_regs_wakeupProgram_6_write_valid | io_regs_wakeupProgram_7_write_valid; // @[WatchdogTimer.scala 17:74]
  wire  unlocked_writeAny = _unlocked_writeAny_T_6 | _unlocked_writeAny_T_13 | io_regs_sleep_write_valid |
    io_regs_cause_write_valid | io_regs_ie_write_valid; // @[WatchdogTimer.scala 19:16]
  wire  _unlocked_T_2 = io_regs_key_write_bits == 32'h51f15e & ~unlocked_writeAny; // @[PMU.scala 73:60]
  wire  _unlocked_T_3 = io_regs_key_write_valid | unlocked_writeAny; // @[PMU.scala 73:111]
  reg  unlocked; // @[Reg.scala 28:20]
  wire  _wantSleep_T = io_regs_sleep_write_valid & unlocked; // @[PMU.scala 75:80]
  reg  wantSleep; // @[Reg.scala 28:20]
  wire  _GEN_1 = _wantSleep_T | wantSleep; // @[Reg.scala 29:18 28:20 29:22]
  reg [2:0] pc; // @[PMU.scala 76:15]
  reg [1:0] wakeupCause; // @[PMU.scala 77:24]
  wire  _ie_T = io_regs_ie_write_valid & unlocked; // @[PMU.scala 78:68]
  reg [3:0] ie_r; // @[Reg.scala 16:16]
  wire [3:0] ie = ie_r | 4'h1; // @[PMU.scala 78:81]
  reg [8:0] wakeupProgram_0; // @[PMU.scala 81:51]
  reg [8:0] wakeupProgram_1; // @[PMU.scala 81:51]
  reg [8:0] wakeupProgram_2; // @[PMU.scala 81:51]
  reg [8:0] wakeupProgram_3; // @[PMU.scala 81:51]
  reg [8:0] wakeupProgram_4; // @[PMU.scala 81:51]
  reg [8:0] wakeupProgram_5; // @[PMU.scala 81:51]
  reg [8:0] wakeupProgram_6; // @[PMU.scala 81:51]
  reg [8:0] wakeupProgram_7; // @[PMU.scala 81:51]
  reg [8:0] sleepProgram_0; // @[PMU.scala 82:49]
  reg [8:0] sleepProgram_1; // @[PMU.scala 82:49]
  reg [8:0] sleepProgram_2; // @[PMU.scala 82:49]
  reg [8:0] sleepProgram_3; // @[PMU.scala 82:49]
  reg [8:0] sleepProgram_4; // @[PMU.scala 82:49]
  reg [8:0] sleepProgram_5; // @[PMU.scala 82:49]
  reg [8:0] sleepProgram_6; // @[PMU.scala 82:49]
  reg [8:0] sleepProgram_7; // @[PMU.scala 82:49]
  wire [8:0] _insnBits_T_1 = pc == 3'h1 ? wakeupProgram_1 : wakeupProgram_0; // @[package.scala 32:76]
  wire [8:0] _insnBits_T_3 = pc == 3'h2 ? wakeupProgram_2 : _insnBits_T_1; // @[package.scala 32:76]
  wire [8:0] _insnBits_T_5 = pc == 3'h3 ? wakeupProgram_3 : _insnBits_T_3; // @[package.scala 32:76]
  wire [8:0] _insnBits_T_7 = pc == 3'h4 ? wakeupProgram_4 : _insnBits_T_5; // @[package.scala 32:76]
  wire [8:0] _insnBits_T_9 = pc == 3'h5 ? wakeupProgram_5 : _insnBits_T_7; // @[package.scala 32:76]
  wire [8:0] _insnBits_T_11 = pc == 3'h6 ? wakeupProgram_6 : _insnBits_T_9; // @[package.scala 32:76]
  wire [8:0] _insnBits_T_13 = pc == 3'h7 ? wakeupProgram_7 : _insnBits_T_11; // @[package.scala 32:76]
  wire [8:0] _insnBits_T_15 = pc == 3'h1 ? sleepProgram_1 : sleepProgram_0; // @[package.scala 32:76]
  wire [8:0] _insnBits_T_17 = pc == 3'h2 ? sleepProgram_2 : _insnBits_T_15; // @[package.scala 32:76]
  wire [8:0] _insnBits_T_19 = pc == 3'h3 ? sleepProgram_3 : _insnBits_T_17; // @[package.scala 32:76]
  wire [8:0] _insnBits_T_21 = pc == 3'h4 ? sleepProgram_4 : _insnBits_T_19; // @[package.scala 32:76]
  wire [8:0] _insnBits_T_23 = pc == 3'h5 ? sleepProgram_5 : _insnBits_T_21; // @[package.scala 32:76]
  wire [8:0] _insnBits_T_25 = pc == 3'h6 ? sleepProgram_6 : _insnBits_T_23; // @[package.scala 32:76]
  wire [8:0] _insnBits_T_27 = pc == 3'h7 ? sleepProgram_7 : _insnBits_T_25; // @[package.scala 32:76]
  wire [8:0] insnBits = awake ? _insnBits_T_13 : _insnBits_T_27; // @[PMU.scala 83:21]
  wire [3:0] insn_dt = insnBits[3:0]; // @[PMU.scala 84:43]
  reg [15:0] count; // @[PMU.scala 86:18]
  wire [15:0] _tick_T_1 = count + 16'h1; // @[PMU.scala 87:30]
  wire [15:0] _tick_T_2 = count ^ _tick_T_1; // @[PMU.scala 87:21]
  wire [15:0] _tick_T_3 = _tick_T_2 >> insn_dt; // @[PMU.scala 87:35]
  wire  tick = _tick_T_3[0]; // @[PMU.scala 87:35]
  wire [3:0] npc = pc + 3'h1; // @[PMU.scala 88:16]
  wire  last = npc >= 4'h8; // @[PMU.scala 89:18]
  wire  _io_control_valid_T = ~last; // @[PMU.scala 90:30]
  wire  _GEN_4 = tick ? _io_control_valid_T : run; // @[PMU.scala 95:17 99:11 69:16]
  wire [3:0] _GEN_5 = tick ? npc : {{1'd0}, pc}; // @[PMU.scala 100:10 76:15 95:17]
  wire [3:0] _maskedWakeupCauses_T = {2'h1,io_wakeup_rtc,1'h0}; // @[PMU.scala 103:45]
  wire [3:0] maskedWakeupCauses = ie & _maskedWakeupCauses_T; // @[PMU.scala 103:33]
  wire [1:0] _wakeupCause_T_4 = maskedWakeupCauses[2] ? 2'h2 : 2'h3; // @[Mux.scala 47:70]
  wire [1:0] _wakeupCause_T_5 = maskedWakeupCauses[1] ? 2'h1 : _wakeupCause_T_4; // @[Mux.scala 47:70]
  wire  _GEN_6 = ~awake & |maskedWakeupCauses | run; // @[PMU.scala 104:45 105:11 69:16]
  wire  _GEN_7 = ~awake & |maskedWakeupCauses | awake; // @[PMU.scala 104:45 106:13 70:18]
  wire  _GEN_9 = awake & wantSleep | _GEN_6; // @[PMU.scala 109:31 110:11]
  wire  _GEN_10 = awake & wantSleep ? 1'h0 : _GEN_7; // @[PMU.scala 109:31 111:13]
  wire  _GEN_13 = run ? _GEN_4 : _GEN_9; // @[PMU.scala 93:14]
  wire [3:0] _GEN_14 = run ? _GEN_5 : {{1'd0}, pc}; // @[PMU.scala 93:14 76:15]
  wire  _GEN_15 = run ? awake : _GEN_10; // @[PMU.scala 93:14 70:18]
  wire [9:0] _io_regs_cause_read_T = {io_resetCause, 8'h0}; // @[PMU.scala 116:54]
  wire [9:0] _GEN_34 = {{8'd0}, wakeupCause}; // @[PMU.scala 116:37]
  wire [9:0] _io_regs_cause_read_T_1 = _GEN_34 | _io_regs_cause_read_T; // @[PMU.scala 116:37]
  wire [31:0] _GEN_18 = io_regs_wakeupProgram_0_write_valid & unlocked ? io_regs_wakeupProgram_0_write_bits : {{23'd0},
    wakeupProgram_0}; // @[PMU.scala 123:{41,47} 81:51]
  wire [31:0] _GEN_19 = io_regs_wakeupProgram_1_write_valid & unlocked ? io_regs_wakeupProgram_1_write_bits : {{23'd0},
    wakeupProgram_1}; // @[PMU.scala 123:{41,47} 81:51]
  wire [31:0] _GEN_20 = io_regs_wakeupProgram_2_write_valid & unlocked ? io_regs_wakeupProgram_2_write_bits : {{23'd0},
    wakeupProgram_2}; // @[PMU.scala 123:{41,47} 81:51]
  wire [31:0] _GEN_21 = io_regs_wakeupProgram_3_write_valid & unlocked ? io_regs_wakeupProgram_3_write_bits : {{23'd0},
    wakeupProgram_3}; // @[PMU.scala 123:{41,47} 81:51]
  wire [31:0] _GEN_22 = io_regs_wakeupProgram_4_write_valid & unlocked ? io_regs_wakeupProgram_4_write_bits : {{23'd0},
    wakeupProgram_4}; // @[PMU.scala 123:{41,47} 81:51]
  wire [31:0] _GEN_23 = io_regs_wakeupProgram_5_write_valid & unlocked ? io_regs_wakeupProgram_5_write_bits : {{23'd0},
    wakeupProgram_5}; // @[PMU.scala 123:{41,47} 81:51]
  wire [31:0] _GEN_24 = io_regs_wakeupProgram_6_write_valid & unlocked ? io_regs_wakeupProgram_6_write_bits : {{23'd0},
    wakeupProgram_6}; // @[PMU.scala 123:{41,47} 81:51]
  wire [31:0] _GEN_25 = io_regs_wakeupProgram_7_write_valid & unlocked ? io_regs_wakeupProgram_7_write_bits : {{23'd0},
    wakeupProgram_7}; // @[PMU.scala 123:{41,47} 81:51]
  wire [31:0] _GEN_26 = io_regs_sleepProgram_0_write_valid & unlocked ? io_regs_sleepProgram_0_write_bits : {{23'd0},
    sleepProgram_0}; // @[PMU.scala 123:{41,47} 82:49]
  wire [31:0] _GEN_27 = io_regs_sleepProgram_1_write_valid & unlocked ? io_regs_sleepProgram_1_write_bits : {{23'd0},
    sleepProgram_1}; // @[PMU.scala 123:{41,47} 82:49]
  wire [31:0] _GEN_28 = io_regs_sleepProgram_2_write_valid & unlocked ? io_regs_sleepProgram_2_write_bits : {{23'd0},
    sleepProgram_2}; // @[PMU.scala 123:{41,47} 82:49]
  wire [31:0] _GEN_29 = io_regs_sleepProgram_3_write_valid & unlocked ? io_regs_sleepProgram_3_write_bits : {{23'd0},
    sleepProgram_3}; // @[PMU.scala 123:{41,47} 82:49]
  wire [31:0] _GEN_30 = io_regs_sleepProgram_4_write_valid & unlocked ? io_regs_sleepProgram_4_write_bits : {{23'd0},
    sleepProgram_4}; // @[PMU.scala 123:{41,47} 82:49]
  wire [31:0] _GEN_31 = io_regs_sleepProgram_5_write_valid & unlocked ? io_regs_sleepProgram_5_write_bits : {{23'd0},
    sleepProgram_5}; // @[PMU.scala 123:{41,47} 82:49]
  wire [31:0] _GEN_32 = io_regs_sleepProgram_6_write_valid & unlocked ? io_regs_sleepProgram_6_write_bits : {{23'd0},
    sleepProgram_6}; // @[PMU.scala 123:{41,47} 82:49]
  wire [31:0] _GEN_33 = io_regs_sleepProgram_7_write_valid & unlocked ? io_regs_sleepProgram_7_write_bits : {{23'd0},
    sleepProgram_7}; // @[PMU.scala 123:{41,47} 82:49]
  assign io_control_valid = run & ~last & tick; // @[PMU.scala 90:36]
  assign io_control_bits_hfclkrst = insnBits[8]; // @[PMU.scala 84:43]
  assign io_control_bits_corerst = insnBits[7]; // @[PMU.scala 84:43]
  assign io_control_bits_reserved1 = insnBits[6]; // @[PMU.scala 84:43]
  assign io_control_bits_vddpaden = insnBits[5]; // @[PMU.scala 84:43]
  assign io_control_bits_reserved0 = insnBits[4]; // @[PMU.scala 84:43]
  assign io_regs_ie_read = ie_r | 4'h1; // @[PMU.scala 78:81]
  assign io_regs_cause_read = {{22'd0}, _io_regs_cause_read_T_1}; // @[PMU.scala 116:22]
  assign io_regs_key_read = {{31'd0}, unlocked}; // @[PMU.scala 118:20]
  assign io_regs_wakeupProgram_0_read = {{23'd0}, wakeupProgram_0}; // @[PMU.scala 122:15]
  assign io_regs_wakeupProgram_1_read = {{23'd0}, wakeupProgram_1}; // @[PMU.scala 122:15]
  assign io_regs_wakeupProgram_2_read = {{23'd0}, wakeupProgram_2}; // @[PMU.scala 122:15]
  assign io_regs_wakeupProgram_3_read = {{23'd0}, wakeupProgram_3}; // @[PMU.scala 122:15]
  assign io_regs_wakeupProgram_4_read = {{23'd0}, wakeupProgram_4}; // @[PMU.scala 122:15]
  assign io_regs_wakeupProgram_5_read = {{23'd0}, wakeupProgram_5}; // @[PMU.scala 122:15]
  assign io_regs_wakeupProgram_6_read = {{23'd0}, wakeupProgram_6}; // @[PMU.scala 122:15]
  assign io_regs_wakeupProgram_7_read = {{23'd0}, wakeupProgram_7}; // @[PMU.scala 122:15]
  assign io_regs_sleepProgram_0_read = {{23'd0}, sleepProgram_0}; // @[PMU.scala 122:15]
  assign io_regs_sleepProgram_1_read = {{23'd0}, sleepProgram_1}; // @[PMU.scala 122:15]
  assign io_regs_sleepProgram_2_read = {{23'd0}, sleepProgram_2}; // @[PMU.scala 122:15]
  assign io_regs_sleepProgram_3_read = {{23'd0}, sleepProgram_3}; // @[PMU.scala 122:15]
  assign io_regs_sleepProgram_4_read = {{23'd0}, sleepProgram_4}; // @[PMU.scala 122:15]
  assign io_regs_sleepProgram_5_read = {{23'd0}, sleepProgram_5}; // @[PMU.scala 122:15]
  assign io_regs_sleepProgram_6_read = {{23'd0}, sleepProgram_6}; // @[PMU.scala 122:15]
  assign io_regs_sleepProgram_7_read = {{23'd0}, sleepProgram_7}; // @[PMU.scala 122:15]
  always @(posedge clock) begin
    run <= reset | _GEN_13; // @[PMU.scala 69:{16,16}]
    awake <= reset | _GEN_15; // @[PMU.scala 70:{18,18}]
    if (reset) begin // @[Reg.scala 28:20]
      unlocked <= 1'h0; // @[Reg.scala 28:20]
    end else if (_unlocked_T_3) begin // @[Reg.scala 29:18]
      unlocked <= _unlocked_T_2; // @[Reg.scala 29:22]
    end
    if (reset) begin // @[Reg.scala 28:20]
      wantSleep <= 1'h0; // @[Reg.scala 28:20]
    end else if (run) begin // @[PMU.scala 93:14]
      wantSleep <= _GEN_1;
    end else if (awake & wantSleep) begin // @[PMU.scala 109:31]
      wantSleep <= 1'h0; // @[PMU.scala 112:17]
    end else begin
      wantSleep <= _GEN_1;
    end
    if (reset) begin // @[PMU.scala 76:15]
      pc <= 3'h0; // @[PMU.scala 76:15]
    end else begin
      pc <= _GEN_14[2:0];
    end
    if (reset) begin // @[PMU.scala 77:24]
      wakeupCause <= 2'h0; // @[PMU.scala 77:24]
    end else if (!(run)) begin // @[PMU.scala 93:14]
      if (~awake & |maskedWakeupCauses) begin // @[PMU.scala 104:45]
        if (maskedWakeupCauses[0]) begin // @[Mux.scala 47:70]
          wakeupCause <= 2'h0;
        end else begin
          wakeupCause <= _wakeupCause_T_5;
        end
      end
    end
    if (_ie_T) begin // @[Reg.scala 17:18]
      ie_r <= io_regs_ie_write_bits; // @[Reg.scala 17:22]
    end
    if (reset) begin // @[PMU.scala 81:51]
      wakeupProgram_0 <= 9'h1f0; // @[PMU.scala 81:51]
    end else begin
      wakeupProgram_0 <= _GEN_18[8:0];
    end
    if (reset) begin // @[PMU.scala 81:51]
      wakeupProgram_1 <= 9'hf8; // @[PMU.scala 81:51]
    end else begin
      wakeupProgram_1 <= _GEN_19[8:0];
    end
    if (reset) begin // @[PMU.scala 81:51]
      wakeupProgram_2 <= 9'h30; // @[PMU.scala 81:51]
    end else begin
      wakeupProgram_2 <= _GEN_20[8:0];
    end
    if (reset) begin // @[PMU.scala 81:51]
      wakeupProgram_3 <= 9'h30; // @[PMU.scala 81:51]
    end else begin
      wakeupProgram_3 <= _GEN_21[8:0];
    end
    if (reset) begin // @[PMU.scala 81:51]
      wakeupProgram_4 <= 9'h30; // @[PMU.scala 81:51]
    end else begin
      wakeupProgram_4 <= _GEN_22[8:0];
    end
    if (reset) begin // @[PMU.scala 81:51]
      wakeupProgram_5 <= 9'h30; // @[PMU.scala 81:51]
    end else begin
      wakeupProgram_5 <= _GEN_23[8:0];
    end
    if (reset) begin // @[PMU.scala 81:51]
      wakeupProgram_6 <= 9'h30; // @[PMU.scala 81:51]
    end else begin
      wakeupProgram_6 <= _GEN_24[8:0];
    end
    if (reset) begin // @[PMU.scala 81:51]
      wakeupProgram_7 <= 9'h30; // @[PMU.scala 81:51]
    end else begin
      wakeupProgram_7 <= _GEN_25[8:0];
    end
    if (reset) begin // @[PMU.scala 82:49]
      sleepProgram_0 <= 9'hf0; // @[PMU.scala 82:49]
    end else begin
      sleepProgram_0 <= _GEN_26[8:0];
    end
    if (reset) begin // @[PMU.scala 82:49]
      sleepProgram_1 <= 9'h1f0; // @[PMU.scala 82:49]
    end else begin
      sleepProgram_1 <= _GEN_27[8:0];
    end
    if (reset) begin // @[PMU.scala 82:49]
      sleepProgram_2 <= 9'h1d0; // @[PMU.scala 82:49]
    end else begin
      sleepProgram_2 <= _GEN_28[8:0];
    end
    if (reset) begin // @[PMU.scala 82:49]
      sleepProgram_3 <= 9'h1c0; // @[PMU.scala 82:49]
    end else begin
      sleepProgram_3 <= _GEN_29[8:0];
    end
    if (reset) begin // @[PMU.scala 82:49]
      sleepProgram_4 <= 9'h1c0; // @[PMU.scala 82:49]
    end else begin
      sleepProgram_4 <= _GEN_30[8:0];
    end
    if (reset) begin // @[PMU.scala 82:49]
      sleepProgram_5 <= 9'h1c0; // @[PMU.scala 82:49]
    end else begin
      sleepProgram_5 <= _GEN_31[8:0];
    end
    if (reset) begin // @[PMU.scala 82:49]
      sleepProgram_6 <= 9'h1c0; // @[PMU.scala 82:49]
    end else begin
      sleepProgram_6 <= _GEN_32[8:0];
    end
    if (reset) begin // @[PMU.scala 82:49]
      sleepProgram_7 <= 9'h1c0; // @[PMU.scala 82:49]
    end else begin
      sleepProgram_7 <= _GEN_33[8:0];
    end
    if (reset) begin // @[PMU.scala 86:18]
      count <= 16'h0; // @[PMU.scala 86:18]
    end else if (run) begin // @[PMU.scala 93:14]
      if (tick) begin // @[PMU.scala 95:17]
        count <= 16'h0; // @[PMU.scala 96:13]
      end else begin
        count <= _tick_T_1; // @[PMU.scala 94:11]
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  run = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  awake = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  unlocked = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  wantSleep = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  pc = _RAND_4[2:0];
  _RAND_5 = {1{`RANDOM}};
  wakeupCause = _RAND_5[1:0];
  _RAND_6 = {1{`RANDOM}};
  ie_r = _RAND_6[3:0];
  _RAND_7 = {1{`RANDOM}};
  wakeupProgram_0 = _RAND_7[8:0];
  _RAND_8 = {1{`RANDOM}};
  wakeupProgram_1 = _RAND_8[8:0];
  _RAND_9 = {1{`RANDOM}};
  wakeupProgram_2 = _RAND_9[8:0];
  _RAND_10 = {1{`RANDOM}};
  wakeupProgram_3 = _RAND_10[8:0];
  _RAND_11 = {1{`RANDOM}};
  wakeupProgram_4 = _RAND_11[8:0];
  _RAND_12 = {1{`RANDOM}};
  wakeupProgram_5 = _RAND_12[8:0];
  _RAND_13 = {1{`RANDOM}};
  wakeupProgram_6 = _RAND_13[8:0];
  _RAND_14 = {1{`RANDOM}};
  wakeupProgram_7 = _RAND_14[8:0];
  _RAND_15 = {1{`RANDOM}};
  sleepProgram_0 = _RAND_15[8:0];
  _RAND_16 = {1{`RANDOM}};
  sleepProgram_1 = _RAND_16[8:0];
  _RAND_17 = {1{`RANDOM}};
  sleepProgram_2 = _RAND_17[8:0];
  _RAND_18 = {1{`RANDOM}};
  sleepProgram_3 = _RAND_18[8:0];
  _RAND_19 = {1{`RANDOM}};
  sleepProgram_4 = _RAND_19[8:0];
  _RAND_20 = {1{`RANDOM}};
  sleepProgram_5 = _RAND_20[8:0];
  _RAND_21 = {1{`RANDOM}};
  sleepProgram_6 = _RAND_21[8:0];
  _RAND_22 = {1{`RANDOM}};
  sleepProgram_7 = _RAND_22[8:0];
  _RAND_23 = {1{`RANDOM}};
  count = _RAND_23[15:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module AsyncResetRegVec_w5_i0(
  input        clock,
  input        reset,
  input  [4:0] io_d,
  output [4:0] io_q,
  input        io_en
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg [4:0] reg_; // @[AsyncResetReg.scala 64:50]
  assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[AsyncResetReg.scala 65:16]
      reg_ <= 5'h0; // @[AsyncResetReg.scala 66:9]
    end else if (io_en) begin // @[AsyncResetReg.scala 64:50]
      reg_ <= io_d;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  reg_ = _RAND_0[4:0];
`endif // RANDOMIZE_REG_INIT
  if (reset) begin
    reg_ = 5'h0;
  end
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module PMU(
  input         clock,
  input         reset,
  input         io_wakeup_rtc,
  output        io_control_corerst,
  input         io_regs_ie_write_valid,
  input  [3:0]  io_regs_ie_write_bits,
  output [3:0]  io_regs_ie_read,
  input         io_regs_cause_write_valid,
  output [31:0] io_regs_cause_read,
  input         io_regs_sleep_write_valid,
  input         io_regs_key_write_valid,
  input  [31:0] io_regs_key_write_bits,
  output [31:0] io_regs_key_read,
  input         io_regs_wakeupProgram_0_write_valid,
  input  [31:0] io_regs_wakeupProgram_0_write_bits,
  output [31:0] io_regs_wakeupProgram_0_read,
  input         io_regs_wakeupProgram_1_write_valid,
  input  [31:0] io_regs_wakeupProgram_1_write_bits,
  output [31:0] io_regs_wakeupProgram_1_read,
  input         io_regs_wakeupProgram_2_write_valid,
  input  [31:0] io_regs_wakeupProgram_2_write_bits,
  output [31:0] io_regs_wakeupProgram_2_read,
  input         io_regs_wakeupProgram_3_write_valid,
  input  [31:0] io_regs_wakeupProgram_3_write_bits,
  output [31:0] io_regs_wakeupProgram_3_read,
  input         io_regs_wakeupProgram_4_write_valid,
  input  [31:0] io_regs_wakeupProgram_4_write_bits,
  output [31:0] io_regs_wakeupProgram_4_read,
  input         io_regs_wakeupProgram_5_write_valid,
  input  [31:0] io_regs_wakeupProgram_5_write_bits,
  output [31:0] io_regs_wakeupProgram_5_read,
  input         io_regs_wakeupProgram_6_write_valid,
  input  [31:0] io_regs_wakeupProgram_6_write_bits,
  output [31:0] io_regs_wakeupProgram_6_read,
  input         io_regs_wakeupProgram_7_write_valid,
  input  [31:0] io_regs_wakeupProgram_7_write_bits,
  output [31:0] io_regs_wakeupProgram_7_read,
  input         io_regs_sleepProgram_0_write_valid,
  input  [31:0] io_regs_sleepProgram_0_write_bits,
  output [31:0] io_regs_sleepProgram_0_read,
  input         io_regs_sleepProgram_1_write_valid,
  input  [31:0] io_regs_sleepProgram_1_write_bits,
  output [31:0] io_regs_sleepProgram_1_read,
  input         io_regs_sleepProgram_2_write_valid,
  input  [31:0] io_regs_sleepProgram_2_write_bits,
  output [31:0] io_regs_sleepProgram_2_read,
  input         io_regs_sleepProgram_3_write_valid,
  input  [31:0] io_regs_sleepProgram_3_write_bits,
  output [31:0] io_regs_sleepProgram_3_read,
  input         io_regs_sleepProgram_4_write_valid,
  input  [31:0] io_regs_sleepProgram_4_write_bits,
  output [31:0] io_regs_sleepProgram_4_read,
  input         io_regs_sleepProgram_5_write_valid,
  input  [31:0] io_regs_sleepProgram_5_write_bits,
  output [31:0] io_regs_sleepProgram_5_read,
  input         io_regs_sleepProgram_6_write_valid,
  input  [31:0] io_regs_sleepProgram_6_write_bits,
  output [31:0] io_regs_sleepProgram_6_read,
  input         io_regs_sleepProgram_7_write_valid,
  input  [31:0] io_regs_sleepProgram_7_write_bits,
  output [31:0] io_regs_sleepProgram_7_read,
  input         io_resetCauses_wdogrst,
  input         io_resetCauses_erst
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
  wire  core_clock; // @[PMU.scala 136:20]
  wire  core_reset; // @[PMU.scala 136:20]
  wire  core_io_wakeup_rtc; // @[PMU.scala 136:20]
  wire  core_io_control_valid; // @[PMU.scala 136:20]
  wire  core_io_control_bits_hfclkrst; // @[PMU.scala 136:20]
  wire  core_io_control_bits_corerst; // @[PMU.scala 136:20]
  wire  core_io_control_bits_reserved1; // @[PMU.scala 136:20]
  wire  core_io_control_bits_vddpaden; // @[PMU.scala 136:20]
  wire  core_io_control_bits_reserved0; // @[PMU.scala 136:20]
  wire [1:0] core_io_resetCause; // @[PMU.scala 136:20]
  wire  core_io_regs_ie_write_valid; // @[PMU.scala 136:20]
  wire [3:0] core_io_regs_ie_write_bits; // @[PMU.scala 136:20]
  wire [3:0] core_io_regs_ie_read; // @[PMU.scala 136:20]
  wire  core_io_regs_cause_write_valid; // @[PMU.scala 136:20]
  wire [31:0] core_io_regs_cause_read; // @[PMU.scala 136:20]
  wire  core_io_regs_sleep_write_valid; // @[PMU.scala 136:20]
  wire  core_io_regs_key_write_valid; // @[PMU.scala 136:20]
  wire [31:0] core_io_regs_key_write_bits; // @[PMU.scala 136:20]
  wire [31:0] core_io_regs_key_read; // @[PMU.scala 136:20]
  wire  core_io_regs_wakeupProgram_0_write_valid; // @[PMU.scala 136:20]
  wire [31:0] core_io_regs_wakeupProgram_0_write_bits; // @[PMU.scala 136:20]
  wire [31:0] core_io_regs_wakeupProgram_0_read; // @[PMU.scala 136:20]
  wire  core_io_regs_wakeupProgram_1_write_valid; // @[PMU.scala 136:20]
  wire [31:0] core_io_regs_wakeupProgram_1_write_bits; // @[PMU.scala 136:20]
  wire [31:0] core_io_regs_wakeupProgram_1_read; // @[PMU.scala 136:20]
  wire  core_io_regs_wakeupProgram_2_write_valid; // @[PMU.scala 136:20]
  wire [31:0] core_io_regs_wakeupProgram_2_write_bits; // @[PMU.scala 136:20]
  wire [31:0] core_io_regs_wakeupProgram_2_read; // @[PMU.scala 136:20]
  wire  core_io_regs_wakeupProgram_3_write_valid; // @[PMU.scala 136:20]
  wire [31:0] core_io_regs_wakeupProgram_3_write_bits; // @[PMU.scala 136:20]
  wire [31:0] core_io_regs_wakeupProgram_3_read; // @[PMU.scala 136:20]
  wire  core_io_regs_wakeupProgram_4_write_valid; // @[PMU.scala 136:20]
  wire [31:0] core_io_regs_wakeupProgram_4_write_bits; // @[PMU.scala 136:20]
  wire [31:0] core_io_regs_wakeupProgram_4_read; // @[PMU.scala 136:20]
  wire  core_io_regs_wakeupProgram_5_write_valid; // @[PMU.scala 136:20]
  wire [31:0] core_io_regs_wakeupProgram_5_write_bits; // @[PMU.scala 136:20]
  wire [31:0] core_io_regs_wakeupProgram_5_read; // @[PMU.scala 136:20]
  wire  core_io_regs_wakeupProgram_6_write_valid; // @[PMU.scala 136:20]
  wire [31:0] core_io_regs_wakeupProgram_6_write_bits; // @[PMU.scala 136:20]
  wire [31:0] core_io_regs_wakeupProgram_6_read; // @[PMU.scala 136:20]
  wire  core_io_regs_wakeupProgram_7_write_valid; // @[PMU.scala 136:20]
  wire [31:0] core_io_regs_wakeupProgram_7_write_bits; // @[PMU.scala 136:20]
  wire [31:0] core_io_regs_wakeupProgram_7_read; // @[PMU.scala 136:20]
  wire  core_io_regs_sleepProgram_0_write_valid; // @[PMU.scala 136:20]
  wire [31:0] core_io_regs_sleepProgram_0_write_bits; // @[PMU.scala 136:20]
  wire [31:0] core_io_regs_sleepProgram_0_read; // @[PMU.scala 136:20]
  wire  core_io_regs_sleepProgram_1_write_valid; // @[PMU.scala 136:20]
  wire [31:0] core_io_regs_sleepProgram_1_write_bits; // @[PMU.scala 136:20]
  wire [31:0] core_io_regs_sleepProgram_1_read; // @[PMU.scala 136:20]
  wire  core_io_regs_sleepProgram_2_write_valid; // @[PMU.scala 136:20]
  wire [31:0] core_io_regs_sleepProgram_2_write_bits; // @[PMU.scala 136:20]
  wire [31:0] core_io_regs_sleepProgram_2_read; // @[PMU.scala 136:20]
  wire  core_io_regs_sleepProgram_3_write_valid; // @[PMU.scala 136:20]
  wire [31:0] core_io_regs_sleepProgram_3_write_bits; // @[PMU.scala 136:20]
  wire [31:0] core_io_regs_sleepProgram_3_read; // @[PMU.scala 136:20]
  wire  core_io_regs_sleepProgram_4_write_valid; // @[PMU.scala 136:20]
  wire [31:0] core_io_regs_sleepProgram_4_write_bits; // @[PMU.scala 136:20]
  wire [31:0] core_io_regs_sleepProgram_4_read; // @[PMU.scala 136:20]
  wire  core_io_regs_sleepProgram_5_write_valid; // @[PMU.scala 136:20]
  wire [31:0] core_io_regs_sleepProgram_5_write_bits; // @[PMU.scala 136:20]
  wire [31:0] core_io_regs_sleepProgram_5_read; // @[PMU.scala 136:20]
  wire  core_io_regs_sleepProgram_6_write_valid; // @[PMU.scala 136:20]
  wire [31:0] core_io_regs_sleepProgram_6_write_bits; // @[PMU.scala 136:20]
  wire [31:0] core_io_regs_sleepProgram_6_read; // @[PMU.scala 136:20]
  wire  core_io_regs_sleepProgram_7_write_valid; // @[PMU.scala 136:20]
  wire [31:0] core_io_regs_sleepProgram_7_write_bits; // @[PMU.scala 136:20]
  wire [31:0] core_io_regs_sleepProgram_7_read; // @[PMU.scala 136:20]
  wire  latch_reg_clock; // @[AsyncResetReg.scala 89:21]
  wire  latch_reg_reset; // @[AsyncResetReg.scala 89:21]
  wire [4:0] latch_reg_io_d; // @[AsyncResetReg.scala 89:21]
  wire [4:0] latch_reg_io_q; // @[AsyncResetReg.scala 89:21]
  wire  latch_reg_io_en; // @[AsyncResetReg.scala 89:21]
  wire  core_io_resetCause_latches_latch_set; // @[PMU.scala 148:25]
  wire  core_io_resetCause_latches_latch_reset; // @[PMU.scala 148:25]
  wire  core_io_resetCause_latches_latch_q; // @[PMU.scala 148:25]
  wire  core_io_resetCause_latches_latch_1_set; // @[PMU.scala 148:25]
  wire  core_io_resetCause_latches_latch_1_reset; // @[PMU.scala 148:25]
  wire  core_io_resetCause_latches_latch_1_q; // @[PMU.scala 148:25]
  wire  core_io_resetCause_latches_latch_2_set; // @[PMU.scala 148:25]
  wire  core_io_resetCause_latches_latch_2_reset; // @[PMU.scala 148:25]
  wire  core_io_resetCause_latches_latch_2_q; // @[PMU.scala 148:25]
  reg  coreReset_x4; // @[PMU.scala 135:33]
  reg  coreReset; // @[PMU.scala 135:22]
  wire [4:0] _latch_T = {core_io_control_bits_hfclkrst,core_io_control_bits_corerst,core_io_control_bits_reserved1,
    core_io_control_bits_vddpaden,core_io_control_bits_reserved0}; // @[PMU.scala 142:52]
  wire [4:0] latch = ~latch_reg_io_q; // @[PMU.scala 142:15]
  wire [2:0] core_io_resetCause_cause = {io_resetCauses_wdogrst,io_resetCauses_erst,1'h0}; // @[PMU.scala 146:32]
  wire [2:0] _core_io_resetCause_T = {core_io_resetCause_latches_latch_2_q,core_io_resetCause_latches_latch_1_q,
    core_io_resetCause_latches_latch_q}; // @[Cat.scala 31:58]
  wire  core_io_resetCause_hi_1 = _core_io_resetCause_T[2]; // @[OneHot.scala 30:18]
  wire [1:0] core_io_resetCause_lo = _core_io_resetCause_T[1:0]; // @[OneHot.scala 31:18]
  wire  _core_io_resetCause_T_1 = |core_io_resetCause_hi_1; // @[OneHot.scala 32:14]
  wire [1:0] _GEN_0 = {{1'd0}, core_io_resetCause_hi_1}; // @[OneHot.scala 32:28]
  wire [1:0] _core_io_resetCause_T_2 = _GEN_0 | core_io_resetCause_lo; // @[OneHot.scala 32:28]
  PMUCore core ( // @[PMU.scala 136:20]
    .clock(core_clock),
    .reset(core_reset),
    .io_wakeup_rtc(core_io_wakeup_rtc),
    .io_control_valid(core_io_control_valid),
    .io_control_bits_hfclkrst(core_io_control_bits_hfclkrst),
    .io_control_bits_corerst(core_io_control_bits_corerst),
    .io_control_bits_reserved1(core_io_control_bits_reserved1),
    .io_control_bits_vddpaden(core_io_control_bits_vddpaden),
    .io_control_bits_reserved0(core_io_control_bits_reserved0),
    .io_resetCause(core_io_resetCause),
    .io_regs_ie_write_valid(core_io_regs_ie_write_valid),
    .io_regs_ie_write_bits(core_io_regs_ie_write_bits),
    .io_regs_ie_read(core_io_regs_ie_read),
    .io_regs_cause_write_valid(core_io_regs_cause_write_valid),
    .io_regs_cause_read(core_io_regs_cause_read),
    .io_regs_sleep_write_valid(core_io_regs_sleep_write_valid),
    .io_regs_key_write_valid(core_io_regs_key_write_valid),
    .io_regs_key_write_bits(core_io_regs_key_write_bits),
    .io_regs_key_read(core_io_regs_key_read),
    .io_regs_wakeupProgram_0_write_valid(core_io_regs_wakeupProgram_0_write_valid),
    .io_regs_wakeupProgram_0_write_bits(core_io_regs_wakeupProgram_0_write_bits),
    .io_regs_wakeupProgram_0_read(core_io_regs_wakeupProgram_0_read),
    .io_regs_wakeupProgram_1_write_valid(core_io_regs_wakeupProgram_1_write_valid),
    .io_regs_wakeupProgram_1_write_bits(core_io_regs_wakeupProgram_1_write_bits),
    .io_regs_wakeupProgram_1_read(core_io_regs_wakeupProgram_1_read),
    .io_regs_wakeupProgram_2_write_valid(core_io_regs_wakeupProgram_2_write_valid),
    .io_regs_wakeupProgram_2_write_bits(core_io_regs_wakeupProgram_2_write_bits),
    .io_regs_wakeupProgram_2_read(core_io_regs_wakeupProgram_2_read),
    .io_regs_wakeupProgram_3_write_valid(core_io_regs_wakeupProgram_3_write_valid),
    .io_regs_wakeupProgram_3_write_bits(core_io_regs_wakeupProgram_3_write_bits),
    .io_regs_wakeupProgram_3_read(core_io_regs_wakeupProgram_3_read),
    .io_regs_wakeupProgram_4_write_valid(core_io_regs_wakeupProgram_4_write_valid),
    .io_regs_wakeupProgram_4_write_bits(core_io_regs_wakeupProgram_4_write_bits),
    .io_regs_wakeupProgram_4_read(core_io_regs_wakeupProgram_4_read),
    .io_regs_wakeupProgram_5_write_valid(core_io_regs_wakeupProgram_5_write_valid),
    .io_regs_wakeupProgram_5_write_bits(core_io_regs_wakeupProgram_5_write_bits),
    .io_regs_wakeupProgram_5_read(core_io_regs_wakeupProgram_5_read),
    .io_regs_wakeupProgram_6_write_valid(core_io_regs_wakeupProgram_6_write_valid),
    .io_regs_wakeupProgram_6_write_bits(core_io_regs_wakeupProgram_6_write_bits),
    .io_regs_wakeupProgram_6_read(core_io_regs_wakeupProgram_6_read),
    .io_regs_wakeupProgram_7_write_valid(core_io_regs_wakeupProgram_7_write_valid),
    .io_regs_wakeupProgram_7_write_bits(core_io_regs_wakeupProgram_7_write_bits),
    .io_regs_wakeupProgram_7_read(core_io_regs_wakeupProgram_7_read),
    .io_regs_sleepProgram_0_write_valid(core_io_regs_sleepProgram_0_write_valid),
    .io_regs_sleepProgram_0_write_bits(core_io_regs_sleepProgram_0_write_bits),
    .io_regs_sleepProgram_0_read(core_io_regs_sleepProgram_0_read),
    .io_regs_sleepProgram_1_write_valid(core_io_regs_sleepProgram_1_write_valid),
    .io_regs_sleepProgram_1_write_bits(core_io_regs_sleepProgram_1_write_bits),
    .io_regs_sleepProgram_1_read(core_io_regs_sleepProgram_1_read),
    .io_regs_sleepProgram_2_write_valid(core_io_regs_sleepProgram_2_write_valid),
    .io_regs_sleepProgram_2_write_bits(core_io_regs_sleepProgram_2_write_bits),
    .io_regs_sleepProgram_2_read(core_io_regs_sleepProgram_2_read),
    .io_regs_sleepProgram_3_write_valid(core_io_regs_sleepProgram_3_write_valid),
    .io_regs_sleepProgram_3_write_bits(core_io_regs_sleepProgram_3_write_bits),
    .io_regs_sleepProgram_3_read(core_io_regs_sleepProgram_3_read),
    .io_regs_sleepProgram_4_write_valid(core_io_regs_sleepProgram_4_write_valid),
    .io_regs_sleepProgram_4_write_bits(core_io_regs_sleepProgram_4_write_bits),
    .io_regs_sleepProgram_4_read(core_io_regs_sleepProgram_4_read),
    .io_regs_sleepProgram_5_write_valid(core_io_regs_sleepProgram_5_write_valid),
    .io_regs_sleepProgram_5_write_bits(core_io_regs_sleepProgram_5_write_bits),
    .io_regs_sleepProgram_5_read(core_io_regs_sleepProgram_5_read),
    .io_regs_sleepProgram_6_write_valid(core_io_regs_sleepProgram_6_write_valid),
    .io_regs_sleepProgram_6_write_bits(core_io_regs_sleepProgram_6_write_bits),
    .io_regs_sleepProgram_6_read(core_io_regs_sleepProgram_6_read),
    .io_regs_sleepProgram_7_write_valid(core_io_regs_sleepProgram_7_write_valid),
    .io_regs_sleepProgram_7_write_bits(core_io_regs_sleepProgram_7_write_bits),
    .io_regs_sleepProgram_7_read(core_io_regs_sleepProgram_7_read)
  );
  AsyncResetRegVec_w5_i0 latch_reg ( // @[AsyncResetReg.scala 89:21]
    .clock(latch_reg_clock),
    .reset(latch_reg_reset),
    .io_d(latch_reg_io_d),
    .io_q(latch_reg_io_q),
    .io_en(latch_reg_io_en)
  );
  SRLatch core_io_resetCause_latches_latch ( // @[PMU.scala 148:25]
    .set(core_io_resetCause_latches_latch_set),
    .reset(core_io_resetCause_latches_latch_reset),
    .q(core_io_resetCause_latches_latch_q)
  );
  SRLatch core_io_resetCause_latches_latch_1 ( // @[PMU.scala 148:25]
    .set(core_io_resetCause_latches_latch_1_set),
    .reset(core_io_resetCause_latches_latch_1_reset),
    .q(core_io_resetCause_latches_latch_1_q)
  );
  SRLatch core_io_resetCause_latches_latch_2 ( // @[PMU.scala 148:25]
    .set(core_io_resetCause_latches_latch_2_set),
    .reset(core_io_resetCause_latches_latch_2_reset),
    .q(core_io_resetCause_latches_latch_2_q)
  );
  assign io_control_corerst = latch[3]; // @[PMU.scala 143:36]
  assign io_regs_ie_read = core_io_regs_ie_read; // @[PMU.scala 138:6]
  assign io_regs_cause_read = core_io_regs_cause_read; // @[PMU.scala 138:6]
  assign io_regs_key_read = core_io_regs_key_read; // @[PMU.scala 138:6]
  assign io_regs_wakeupProgram_0_read = core_io_regs_wakeupProgram_0_read; // @[PMU.scala 138:6]
  assign io_regs_wakeupProgram_1_read = core_io_regs_wakeupProgram_1_read; // @[PMU.scala 138:6]
  assign io_regs_wakeupProgram_2_read = core_io_regs_wakeupProgram_2_read; // @[PMU.scala 138:6]
  assign io_regs_wakeupProgram_3_read = core_io_regs_wakeupProgram_3_read; // @[PMU.scala 138:6]
  assign io_regs_wakeupProgram_4_read = core_io_regs_wakeupProgram_4_read; // @[PMU.scala 138:6]
  assign io_regs_wakeupProgram_5_read = core_io_regs_wakeupProgram_5_read; // @[PMU.scala 138:6]
  assign io_regs_wakeupProgram_6_read = core_io_regs_wakeupProgram_6_read; // @[PMU.scala 138:6]
  assign io_regs_wakeupProgram_7_read = core_io_regs_wakeupProgram_7_read; // @[PMU.scala 138:6]
  assign io_regs_sleepProgram_0_read = core_io_regs_sleepProgram_0_read; // @[PMU.scala 138:6]
  assign io_regs_sleepProgram_1_read = core_io_regs_sleepProgram_1_read; // @[PMU.scala 138:6]
  assign io_regs_sleepProgram_2_read = core_io_regs_sleepProgram_2_read; // @[PMU.scala 138:6]
  assign io_regs_sleepProgram_3_read = core_io_regs_sleepProgram_3_read; // @[PMU.scala 138:6]
  assign io_regs_sleepProgram_4_read = core_io_regs_sleepProgram_4_read; // @[PMU.scala 138:6]
  assign io_regs_sleepProgram_5_read = core_io_regs_sleepProgram_5_read; // @[PMU.scala 138:6]
  assign io_regs_sleepProgram_6_read = core_io_regs_sleepProgram_6_read; // @[PMU.scala 138:6]
  assign io_regs_sleepProgram_7_read = core_io_regs_sleepProgram_7_read; // @[PMU.scala 138:6]
  assign core_clock = clock;
  assign core_reset = coreReset; // @[compatibility.scala 290:56]
  assign core_io_wakeup_rtc = io_wakeup_rtc; // @[PMU.scala 138:6]
  assign core_io_resetCause = {_core_io_resetCause_T_1,_core_io_resetCause_T_2[1]}; // @[Cat.scala 31:58]
  assign core_io_regs_ie_write_valid = io_regs_ie_write_valid; // @[PMU.scala 138:6]
  assign core_io_regs_ie_write_bits = io_regs_ie_write_bits; // @[PMU.scala 138:6]
  assign core_io_regs_cause_write_valid = io_regs_cause_write_valid; // @[PMU.scala 138:6]
  assign core_io_regs_sleep_write_valid = io_regs_sleep_write_valid; // @[PMU.scala 138:6]
  assign core_io_regs_key_write_valid = io_regs_key_write_valid; // @[PMU.scala 138:6]
  assign core_io_regs_key_write_bits = io_regs_key_write_bits; // @[PMU.scala 138:6]
  assign core_io_regs_wakeupProgram_0_write_valid = io_regs_wakeupProgram_0_write_valid; // @[PMU.scala 138:6]
  assign core_io_regs_wakeupProgram_0_write_bits = io_regs_wakeupProgram_0_write_bits; // @[PMU.scala 138:6]
  assign core_io_regs_wakeupProgram_1_write_valid = io_regs_wakeupProgram_1_write_valid; // @[PMU.scala 138:6]
  assign core_io_regs_wakeupProgram_1_write_bits = io_regs_wakeupProgram_1_write_bits; // @[PMU.scala 138:6]
  assign core_io_regs_wakeupProgram_2_write_valid = io_regs_wakeupProgram_2_write_valid; // @[PMU.scala 138:6]
  assign core_io_regs_wakeupProgram_2_write_bits = io_regs_wakeupProgram_2_write_bits; // @[PMU.scala 138:6]
  assign core_io_regs_wakeupProgram_3_write_valid = io_regs_wakeupProgram_3_write_valid; // @[PMU.scala 138:6]
  assign core_io_regs_wakeupProgram_3_write_bits = io_regs_wakeupProgram_3_write_bits; // @[PMU.scala 138:6]
  assign core_io_regs_wakeupProgram_4_write_valid = io_regs_wakeupProgram_4_write_valid; // @[PMU.scala 138:6]
  assign core_io_regs_wakeupProgram_4_write_bits = io_regs_wakeupProgram_4_write_bits; // @[PMU.scala 138:6]
  assign core_io_regs_wakeupProgram_5_write_valid = io_regs_wakeupProgram_5_write_valid; // @[PMU.scala 138:6]
  assign core_io_regs_wakeupProgram_5_write_bits = io_regs_wakeupProgram_5_write_bits; // @[PMU.scala 138:6]
  assign core_io_regs_wakeupProgram_6_write_valid = io_regs_wakeupProgram_6_write_valid; // @[PMU.scala 138:6]
  assign core_io_regs_wakeupProgram_6_write_bits = io_regs_wakeupProgram_6_write_bits; // @[PMU.scala 138:6]
  assign core_io_regs_wakeupProgram_7_write_valid = io_regs_wakeupProgram_7_write_valid; // @[PMU.scala 138:6]
  assign core_io_regs_wakeupProgram_7_write_bits = io_regs_wakeupProgram_7_write_bits; // @[PMU.scala 138:6]
  assign core_io_regs_sleepProgram_0_write_valid = io_regs_sleepProgram_0_write_valid; // @[PMU.scala 138:6]
  assign core_io_regs_sleepProgram_0_write_bits = io_regs_sleepProgram_0_write_bits; // @[PMU.scala 138:6]
  assign core_io_regs_sleepProgram_1_write_valid = io_regs_sleepProgram_1_write_valid; // @[PMU.scala 138:6]
  assign core_io_regs_sleepProgram_1_write_bits = io_regs_sleepProgram_1_write_bits; // @[PMU.scala 138:6]
  assign core_io_regs_sleepProgram_2_write_valid = io_regs_sleepProgram_2_write_valid; // @[PMU.scala 138:6]
  assign core_io_regs_sleepProgram_2_write_bits = io_regs_sleepProgram_2_write_bits; // @[PMU.scala 138:6]
  assign core_io_regs_sleepProgram_3_write_valid = io_regs_sleepProgram_3_write_valid; // @[PMU.scala 138:6]
  assign core_io_regs_sleepProgram_3_write_bits = io_regs_sleepProgram_3_write_bits; // @[PMU.scala 138:6]
  assign core_io_regs_sleepProgram_4_write_valid = io_regs_sleepProgram_4_write_valid; // @[PMU.scala 138:6]
  assign core_io_regs_sleepProgram_4_write_bits = io_regs_sleepProgram_4_write_bits; // @[PMU.scala 138:6]
  assign core_io_regs_sleepProgram_5_write_valid = io_regs_sleepProgram_5_write_valid; // @[PMU.scala 138:6]
  assign core_io_regs_sleepProgram_5_write_bits = io_regs_sleepProgram_5_write_bits; // @[PMU.scala 138:6]
  assign core_io_regs_sleepProgram_6_write_valid = io_regs_sleepProgram_6_write_valid; // @[PMU.scala 138:6]
  assign core_io_regs_sleepProgram_6_write_bits = io_regs_sleepProgram_6_write_bits; // @[PMU.scala 138:6]
  assign core_io_regs_sleepProgram_7_write_valid = io_regs_sleepProgram_7_write_valid; // @[PMU.scala 138:6]
  assign core_io_regs_sleepProgram_7_write_bits = io_regs_sleepProgram_7_write_bits; // @[PMU.scala 138:6]
  assign latch_reg_clock = clock;
  assign latch_reg_reset = reset;
  assign latch_reg_io_d = ~_latch_T; // @[PMU.scala 142:30]
  assign latch_reg_io_en = core_io_control_valid; // @[AsyncResetReg.scala 92:15]
  assign core_io_resetCause_latches_latch_set = core_io_resetCause_cause[0]; // @[PMU.scala 149:28]
  assign core_io_resetCause_latches_latch_reset = core_io_resetCause_cause[1] | core_io_resetCause_cause[2]; // @[PMU.scala 150:87]
  assign core_io_resetCause_latches_latch_1_set = core_io_resetCause_cause[1]; // @[PMU.scala 149:28]
  assign core_io_resetCause_latches_latch_1_reset = core_io_resetCause_cause[0] | core_io_resetCause_cause[2]; // @[PMU.scala 150:87]
  assign core_io_resetCause_latches_latch_2_set = core_io_resetCause_cause[2]; // @[PMU.scala 149:28]
  assign core_io_resetCause_latches_latch_2_reset = core_io_resetCause_cause[0] | core_io_resetCause_cause[1]; // @[PMU.scala 150:87]
  always @(posedge clock) begin
    coreReset_x4 <= reset; // @[PMU.scala 135:33]
    coreReset <= coreReset_x4; // @[PMU.scala 135:22]
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  coreReset_x4 = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  coreReset = _RAND_1[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module WatchdogTimer(
  input         clock,
  input         reset,
  input         scale_io_regs_cfg_write__ip_0,
  input         scale_io_regs_cfg_write__running,
  input         scale_io_regs_cfg_write__countAlways,
  input         scale_io_regs_cfg_write__zerocmp,
  input         scale_io_regs_cfg_write__sticky,
  input  [3:0]  scale_io_regs_cfg_write__scale,
  output        scale_io_regs_cfg_read_ip_0,
  output        scale_io_regs_cfg_read_running,
  output        scale_io_regs_cfg_read_countAlways,
  output        scale_io_regs_cfg_read_zerocmp,
  output        scale_io_regs_cfg_read_sticky,
  output [3:0]  scale_io_regs_cfg_read_scale,
  input         scale_io_regs_cfg_write_ip_0,
  input         scale_io_regs_cfg_write_gang_0,
  input         scale_io_regs_cfg_write_extra_0,
  input         scale_io_regs_cfg_write_center_0,
  input         scale_io_regs_cfg_write_running,
  input         scale_io_regs_cfg_write_countAlways,
  input         scale_io_regs_cfg_write_deglitch,
  input         scale_io_regs_cfg_write_zerocmp,
  input         scale_io_regs_cfg_write_sticky,
  input         scale_io_regs_cfg_write_scale,
  input         scale_io_regs_countLo_write_valid,
  input  [30:0] scale_io_regs_countLo_write_bits,
  output [30:0] scale_io_regs_countLo_read,
  input         scale_io_regs_countHi_write_valid,
  input         scale_io_regs_s_write_valid,
  output [15:0] scale_io_regs_s_read,
  input         scale_io_regs_cmp_0_write_valid,
  input  [15:0] scale_io_regs_cmp_0_write_bits,
  output [15:0] scale_io_regs_cmp_0_read,
  input         scale_io_regs_feed_write_valid,
  input  [31:0] scale_io_regs_feed_write_bits,
  input         scale_io_regs_key_write_valid,
  input  [31:0] scale_io_regs_key_write_bits,
  output [31:0] scale_io_regs_key_read,
  output        scale_io_ip_0,
  input         scale_io_corerst,
  output        scale_io_rst
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
`endif // RANDOMIZE_REG_INIT
  wire  scale_unlocked_reg_clock; // @[AsyncResetReg.scala 89:21]
  wire  scale_unlocked_reg_reset; // @[AsyncResetReg.scala 89:21]
  wire  scale_unlocked_reg_io_d; // @[AsyncResetReg.scala 89:21]
  wire  scale_unlocked_reg_io_q; // @[AsyncResetReg.scala 89:21]
  wire  scale_unlocked_reg_io_en; // @[AsyncResetReg.scala 89:21]
  wire  countEn_countAlways_reg_clock; // @[AsyncResetReg.scala 89:21]
  wire  countEn_countAlways_reg_reset; // @[AsyncResetReg.scala 89:21]
  wire  countEn_countAlways_reg_io_d; // @[AsyncResetReg.scala 89:21]
  wire  countEn_countAlways_reg_io_q; // @[AsyncResetReg.scala 89:21]
  wire  countEn_countAlways_reg_io_en; // @[AsyncResetReg.scala 89:21]
  wire  countEn_countAwake_reg_clock; // @[AsyncResetReg.scala 89:21]
  wire  countEn_countAwake_reg_reset; // @[AsyncResetReg.scala 89:21]
  wire  countEn_countAwake_reg_io_d; // @[AsyncResetReg.scala 89:21]
  wire  countEn_countAwake_reg_io_q; // @[AsyncResetReg.scala 89:21]
  wire  countEn_countAwake_reg_io_en; // @[AsyncResetReg.scala 89:21]
  wire  io_regs_cfg_read_sticky_rsten_reg_clock; // @[AsyncResetReg.scala 89:21]
  wire  io_regs_cfg_read_sticky_rsten_reg_reset; // @[AsyncResetReg.scala 89:21]
  wire  io_regs_cfg_read_sticky_rsten_reg_io_d; // @[AsyncResetReg.scala 89:21]
  wire  io_regs_cfg_read_sticky_rsten_reg_io_q; // @[AsyncResetReg.scala 89:21]
  wire  io_regs_cfg_read_sticky_rsten_reg_io_en; // @[AsyncResetReg.scala 89:21]
  wire  io_rst_reg_clock; // @[AsyncResetReg.scala 89:21]
  wire  io_rst_reg_reset; // @[AsyncResetReg.scala 89:21]
  wire  io_rst_reg_io_d; // @[AsyncResetReg.scala 89:21]
  wire  io_rst_reg_io_q; // @[AsyncResetReg.scala 89:21]
  wire  io_rst_reg_io_en; // @[AsyncResetReg.scala 89:21]
  wire  _scale_unlocked_writeAny_T_20 = scale_io_regs_cfg_write_ip_0 | scale_io_regs_cfg_write_gang_0 |
    scale_io_regs_cfg_write_extra_0 | scale_io_regs_cfg_write_center_0 | scale_io_regs_cfg_write_running |
    scale_io_regs_cfg_write_countAlways | scale_io_regs_cfg_write_deglitch | scale_io_regs_cfg_write_zerocmp |
    scale_io_regs_cfg_write_sticky | scale_io_regs_cfg_write_scale; // @[Timer.scala 139:13]
  wire  scale_unlocked_writeAny = scale_io_regs_feed_write_valid | scale_io_regs_cmp_0_write_valid |
    scale_io_regs_s_write_valid | scale_io_regs_countHi_write_valid | scale_io_regs_countLo_write_valid |
    _scale_unlocked_writeAny_T_20; // @[WatchdogTimer.scala 19:16]
  wire  unlocked = scale_unlocked_reg_io_q; // @[WatchdogTimer.scala 40:114]
  wire  _scale_T = scale_io_regs_cfg_write_scale & unlocked; // @[Timer.scala 202:84]
  reg [3:0] scale; // @[Reg.scala 16:16]
  wire  _cmp_T = scale_io_regs_cmp_0_write_valid & unlocked; // @[Timer.scala 204:82]
  reg [15:0] cmp_0; // @[Reg.scala 16:16]
  reg  countEn_corerstSynchronized_x4; // @[WatchdogTimer.scala 33:45]
  reg  countEn_corerstSynchronized; // @[WatchdogTimer.scala 33:34]
  wire  countAlways = countEn_countAlways_reg_io_q; // @[WatchdogTimer.scala 30:123]
  wire  countAwake = countEn_countAwake_reg_io_q; // @[WatchdogTimer.scala 31:123]
  wire  countEn = countAlways | countAwake & ~countEn_corerstSynchronized; // @[WatchdogTimer.scala 34:17]
  reg [4:0] small_; // @[Counters.scala 45:37]
  wire [4:0] _GEN_10 = {{4'd0}, countEn}; // @[Counters.scala 46:33]
  wire [5:0] nextSmall = small_ + _GEN_10; // @[Counters.scala 46:33]
  reg [25:0] large_; // @[Counters.scala 50:27]
  wire [25:0] _large_r_T_1 = large_ + 26'h1; // @[Counters.scala 51:55]
  wire [25:0] _GEN_3 = nextSmall[5] ? _large_r_T_1 : large_; // @[Counters.scala 50:27 51:{46,50}]
  wire [30:0] value = {large_,small_}; // @[Cat.scala 31:58]
  wire [30:0] _s_T = value >> scale; // @[Timer.scala 209:28]
  wire [15:0] s = _s_T[15:0]; // @[Timer.scala 209:37]
  wire  elapsed_0 = s >= cmp_0; // @[Timer.scala 211:90]
  wire  feed = unlocked & scale_io_regs_feed_write_valid & scale_io_regs_feed_write_bits == 32'hd09f00d; // @[WatchdogTimer.scala 44:42]
  wire  _countReset_zerocmp_T = scale_io_regs_cfg_write_zerocmp & unlocked; // @[Timer.scala 203:95]
  reg  zerocmp; // @[Reg.scala 16:16]
  wire  countReset = feed | zerocmp & elapsed_0; // @[Timer.scala 212:35]
  wire [5:0] _GEN_5 = countReset ? 6'h0 : nextSmall; // @[Timer.scala 213:21 Counters.scala 65:11]
  wire [25:0] _GEN_6 = countReset ? 26'h0 : _GEN_3; // @[Timer.scala 213:21 Counters.scala 66:23]
  wire [31:0] _T_3 = {1'h0,scale_io_regs_countLo_write_bits}; // @[Cat.scala 31:58]
  wire [31:0] _GEN_7 = scale_io_regs_countLo_write_valid & unlocked ? _T_3 : {{26'd0}, _GEN_5}; // @[Timer.scala 214:50 Counters.scala 65:11]
  wire [26:0] _GEN_8 = scale_io_regs_countLo_write_valid & unlocked ? _T_3[31:5] : {{1'd0}, _GEN_6}; // @[Timer.scala 214:50 Counters.scala 66:23]
  wire  _ip_T = scale_io_regs_cfg_write__ip_0 | elapsed_0; // @[WatchdogTimer.scala 37:69]
  wire  _ip_T_2 = scale_io_regs_cfg_write_ip_0 & unlocked | elapsed_0; // @[WatchdogTimer.scala 37:124]
  reg  ip_0; // @[Reg.scala 16:16]
  wire  rsten = io_regs_cfg_read_sticky_rsten_reg_io_q; // @[WatchdogTimer.scala 36:116]
  AsyncResetRegVec_w1_i0 scale_unlocked_reg ( // @[AsyncResetReg.scala 89:21]
    .clock(scale_unlocked_reg_clock),
    .reset(scale_unlocked_reg_reset),
    .io_d(scale_unlocked_reg_io_d),
    .io_q(scale_unlocked_reg_io_q),
    .io_en(scale_unlocked_reg_io_en)
  );
  AsyncResetRegVec_w1_i0 countEn_countAlways_reg ( // @[AsyncResetReg.scala 89:21]
    .clock(countEn_countAlways_reg_clock),
    .reset(countEn_countAlways_reg_reset),
    .io_d(countEn_countAlways_reg_io_d),
    .io_q(countEn_countAlways_reg_io_q),
    .io_en(countEn_countAlways_reg_io_en)
  );
  AsyncResetRegVec_w1_i0 countEn_countAwake_reg ( // @[AsyncResetReg.scala 89:21]
    .clock(countEn_countAwake_reg_clock),
    .reset(countEn_countAwake_reg_reset),
    .io_d(countEn_countAwake_reg_io_d),
    .io_q(countEn_countAwake_reg_io_q),
    .io_en(countEn_countAwake_reg_io_en)
  );
  AsyncResetRegVec_w1_i0 io_regs_cfg_read_sticky_rsten_reg ( // @[AsyncResetReg.scala 89:21]
    .clock(io_regs_cfg_read_sticky_rsten_reg_clock),
    .reset(io_regs_cfg_read_sticky_rsten_reg_reset),
    .io_d(io_regs_cfg_read_sticky_rsten_reg_io_d),
    .io_q(io_regs_cfg_read_sticky_rsten_reg_io_q),
    .io_en(io_regs_cfg_read_sticky_rsten_reg_io_en)
  );
  AsyncResetRegVec_w1_i0 io_rst_reg ( // @[AsyncResetReg.scala 89:21]
    .clock(io_rst_reg_clock),
    .reset(io_rst_reg_reset),
    .io_d(io_rst_reg_io_d),
    .io_q(io_rst_reg_io_q),
    .io_en(io_rst_reg_io_en)
  );
  assign scale_io_regs_cfg_read_ip_0 = ip_0; // @[Timer.scala 218:23]
  assign scale_io_regs_cfg_read_running = countEn_countAwake_reg_io_q; // @[WatchdogTimer.scala 31:123]
  assign scale_io_regs_cfg_read_countAlways = countEn_countAlways_reg_io_q; // @[WatchdogTimer.scala 30:123]
  assign scale_io_regs_cfg_read_zerocmp = zerocmp; // @[Timer.scala 225:28]
  assign scale_io_regs_cfg_read_sticky = io_regs_cfg_read_sticky_rsten_reg_io_q; // @[WatchdogTimer.scala 36:116]
  assign scale_io_regs_cfg_read_scale = scale; // @[Timer.scala 227:26]
  assign scale_io_regs_countLo_read = {large_,small_}; // @[Cat.scala 31:58]
  assign scale_io_regs_s_read = _s_T[15:0]; // @[Timer.scala 209:37]
  assign scale_io_regs_cmp_0_read = cmp_0; // @[Timer.scala 232:53]
  assign scale_io_regs_key_read = {{31'd0}, unlocked}; // @[Timer.scala 234:20]
  assign scale_io_ip_0 = ip_0; // @[Timer.scala 235:9]
  assign scale_io_rst = io_rst_reg_io_q; // @[WatchdogTimer.scala 66:10]
  assign scale_unlocked_reg_clock = clock;
  assign scale_unlocked_reg_reset = reset;
  assign scale_unlocked_reg_io_d = scale_io_regs_key_write_bits == 32'h51f15e & ~scale_unlocked_writeAny; // @[WatchdogTimer.scala 40:64]
  assign scale_unlocked_reg_io_en = scale_io_regs_key_write_valid | scale_unlocked_writeAny; // @[WatchdogTimer.scala 40:102]
  assign countEn_countAlways_reg_clock = clock;
  assign countEn_countAlways_reg_reset = reset;
  assign countEn_countAlways_reg_io_d = scale_io_regs_cfg_write__countAlways; // @[AsyncResetReg.scala 91:14]
  assign countEn_countAlways_reg_io_en = scale_io_regs_cfg_write_countAlways & unlocked; // @[WatchdogTimer.scala 30:111]
  assign countEn_countAwake_reg_clock = clock;
  assign countEn_countAwake_reg_reset = reset;
  assign countEn_countAwake_reg_io_d = scale_io_regs_cfg_write__running; // @[AsyncResetReg.scala 91:14]
  assign countEn_countAwake_reg_io_en = scale_io_regs_cfg_write_running & unlocked; // @[WatchdogTimer.scala 31:111]
  assign io_regs_cfg_read_sticky_rsten_reg_clock = clock;
  assign io_regs_cfg_read_sticky_rsten_reg_reset = reset;
  assign io_regs_cfg_read_sticky_rsten_reg_io_d = scale_io_regs_cfg_write__sticky; // @[AsyncResetReg.scala 91:14]
  assign io_regs_cfg_read_sticky_rsten_reg_io_en = scale_io_regs_cfg_write_sticky & unlocked; // @[WatchdogTimer.scala 36:104]
  assign io_rst_reg_clock = clock;
  assign io_rst_reg_reset = reset;
  assign io_rst_reg_io_d = 1'h1; // @[AsyncResetReg.scala 91:14]
  assign io_rst_reg_io_en = rsten & elapsed_0; // @[WatchdogTimer.scala 66:45]
  always @(posedge clock) begin
    if (_scale_T) begin // @[Reg.scala 17:18]
      scale <= scale_io_regs_cfg_write__scale; // @[Reg.scala 17:22]
    end
    if (_cmp_T) begin // @[Reg.scala 17:18]
      cmp_0 <= scale_io_regs_cmp_0_write_bits; // @[Reg.scala 17:22]
    end
    countEn_corerstSynchronized_x4 <= scale_io_corerst; // @[WatchdogTimer.scala 33:45]
    countEn_corerstSynchronized <= countEn_corerstSynchronized_x4; // @[WatchdogTimer.scala 33:34]
    if (reset) begin // @[Counters.scala 45:37]
      small_ <= 5'h0; // @[Counters.scala 45:37]
    end else begin
      small_ <= _GEN_7[4:0];
    end
    if (reset) begin // @[Counters.scala 50:27]
      large_ <= 26'h0; // @[Counters.scala 50:27]
    end else begin
      large_ <= _GEN_8[25:0];
    end
    if (_countReset_zerocmp_T) begin // @[Reg.scala 17:18]
      zerocmp <= scale_io_regs_cfg_write__zerocmp; // @[Reg.scala 17:22]
    end
    if (_ip_T_2) begin // @[Reg.scala 17:18]
      ip_0 <= _ip_T; // @[Reg.scala 17:22]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  scale = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  cmp_0 = _RAND_1[15:0];
  _RAND_2 = {1{`RANDOM}};
  countEn_corerstSynchronized_x4 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  countEn_corerstSynchronized = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  small_ = _RAND_4[4:0];
  _RAND_5 = {1{`RANDOM}};
  large_ = _RAND_5[25:0];
  _RAND_6 = {1{`RANDOM}};
  zerocmp = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  ip_0 = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Queue_23(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input         io_enq_bits_read,
  input  [9:0]  io_enq_bits_index,
  input  [31:0] io_enq_bits_data,
  input  [3:0]  io_enq_bits_mask,
  input  [6:0]  io_enq_bits_extra_tlrr_extra_source,
  input  [1:0]  io_enq_bits_extra_tlrr_extra_size,
  input         io_deq_ready,
  output        io_deq_valid,
  output        io_deq_bits_read,
  output [9:0]  io_deq_bits_index,
  output [31:0] io_deq_bits_data,
  output [3:0]  io_deq_bits_mask,
  output [6:0]  io_deq_bits_extra_tlrr_extra_source,
  output [1:0]  io_deq_bits_extra_tlrr_extra_size
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_6;
`endif // RANDOMIZE_REG_INIT
  reg  ram_read [0:0]; // @[Decoupled.scala 259:95]
  wire  ram_read_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_read_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_read_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_read_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_read_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_read_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_read_MPORT_en; // @[Decoupled.scala 259:95]
  reg [9:0] ram_index [0:0]; // @[Decoupled.scala 259:95]
  wire  ram_index_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_index_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [9:0] ram_index_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [9:0] ram_index_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_index_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_index_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_index_MPORT_en; // @[Decoupled.scala 259:95]
  reg [31:0] ram_data [0:0]; // @[Decoupled.scala 259:95]
  wire  ram_data_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_data_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [31:0] ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [31:0] ram_data_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_data_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_data_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_data_MPORT_en; // @[Decoupled.scala 259:95]
  reg [3:0] ram_mask [0:0]; // @[Decoupled.scala 259:95]
  wire  ram_mask_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_mask_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [3:0] ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [3:0] ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_mask_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_mask_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_mask_MPORT_en; // @[Decoupled.scala 259:95]
  reg [6:0] ram_extra_tlrr_extra_source [0:0]; // @[Decoupled.scala 259:95]
  wire  ram_extra_tlrr_extra_source_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_extra_tlrr_extra_source_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [6:0] ram_extra_tlrr_extra_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [6:0] ram_extra_tlrr_extra_source_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_extra_tlrr_extra_source_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_extra_tlrr_extra_source_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_extra_tlrr_extra_source_MPORT_en; // @[Decoupled.scala 259:95]
  reg [1:0] ram_extra_tlrr_extra_size [0:0]; // @[Decoupled.scala 259:95]
  wire  ram_extra_tlrr_extra_size_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire  ram_extra_tlrr_extra_size_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [1:0] ram_extra_tlrr_extra_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [1:0] ram_extra_tlrr_extra_size_MPORT_data; // @[Decoupled.scala 259:95]
  wire  ram_extra_tlrr_extra_size_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_extra_tlrr_extra_size_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_extra_tlrr_extra_size_MPORT_en; // @[Decoupled.scala 259:95]
  reg  maybe_full; // @[Decoupled.scala 262:27]
  wire  empty = ~maybe_full; // @[Decoupled.scala 264:28]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
  wire  do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
  assign ram_read_io_deq_bits_MPORT_en = 1'h1;
  assign ram_read_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_read_io_deq_bits_MPORT_data = ram_read[ram_read_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_read_MPORT_data = io_enq_bits_read;
  assign ram_read_MPORT_addr = 1'h0;
  assign ram_read_MPORT_mask = 1'h1;
  assign ram_read_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_index_io_deq_bits_MPORT_en = 1'h1;
  assign ram_index_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_index_io_deq_bits_MPORT_data = ram_index[ram_index_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_index_MPORT_data = io_enq_bits_index;
  assign ram_index_MPORT_addr = 1'h0;
  assign ram_index_MPORT_mask = 1'h1;
  assign ram_index_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_data_io_deq_bits_MPORT_en = 1'h1;
  assign ram_data_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_data_io_deq_bits_MPORT_data = ram_data[ram_data_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_data_MPORT_data = io_enq_bits_data;
  assign ram_data_MPORT_addr = 1'h0;
  assign ram_data_MPORT_mask = 1'h1;
  assign ram_data_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_mask_io_deq_bits_MPORT_en = 1'h1;
  assign ram_mask_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_mask_io_deq_bits_MPORT_data = ram_mask[ram_mask_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_mask_MPORT_data = io_enq_bits_mask;
  assign ram_mask_MPORT_addr = 1'h0;
  assign ram_mask_MPORT_mask = 1'h1;
  assign ram_mask_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_extra_tlrr_extra_source_io_deq_bits_MPORT_en = 1'h1;
  assign ram_extra_tlrr_extra_source_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_extra_tlrr_extra_source_io_deq_bits_MPORT_data =
    ram_extra_tlrr_extra_source[ram_extra_tlrr_extra_source_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_extra_tlrr_extra_source_MPORT_data = io_enq_bits_extra_tlrr_extra_source;
  assign ram_extra_tlrr_extra_source_MPORT_addr = 1'h0;
  assign ram_extra_tlrr_extra_source_MPORT_mask = 1'h1;
  assign ram_extra_tlrr_extra_source_MPORT_en = io_enq_ready & io_enq_valid;
  assign ram_extra_tlrr_extra_size_io_deq_bits_MPORT_en = 1'h1;
  assign ram_extra_tlrr_extra_size_io_deq_bits_MPORT_addr = 1'h0;
  assign ram_extra_tlrr_extra_size_io_deq_bits_MPORT_data =
    ram_extra_tlrr_extra_size[ram_extra_tlrr_extra_size_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_extra_tlrr_extra_size_MPORT_data = io_enq_bits_extra_tlrr_extra_size;
  assign ram_extra_tlrr_extra_size_MPORT_addr = 1'h0;
  assign ram_extra_tlrr_extra_size_MPORT_mask = 1'h1;
  assign ram_extra_tlrr_extra_size_MPORT_en = io_enq_ready & io_enq_valid;
  assign io_enq_ready = ~maybe_full; // @[Decoupled.scala 289:19]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 288:19]
  assign io_deq_bits_read = ram_read_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_index = ram_index_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_data = ram_data_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_mask = ram_mask_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_extra_tlrr_extra_source = ram_extra_tlrr_extra_source_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_deq_bits_extra_tlrr_extra_size = ram_extra_tlrr_extra_size_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  always @(posedge clock) begin
    if (ram_read_MPORT_en & ram_read_MPORT_mask) begin
      ram_read[ram_read_MPORT_addr] <= ram_read_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_index_MPORT_en & ram_index_MPORT_mask) begin
      ram_index[ram_index_MPORT_addr] <= ram_index_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_data_MPORT_en & ram_data_MPORT_mask) begin
      ram_data[ram_data_MPORT_addr] <= ram_data_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_mask_MPORT_en & ram_mask_MPORT_mask) begin
      ram_mask[ram_mask_MPORT_addr] <= ram_mask_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_extra_tlrr_extra_source_MPORT_en & ram_extra_tlrr_extra_source_MPORT_mask) begin
      ram_extra_tlrr_extra_source[ram_extra_tlrr_extra_source_MPORT_addr] <= ram_extra_tlrr_extra_source_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (ram_extra_tlrr_extra_size_MPORT_en & ram_extra_tlrr_extra_size_MPORT_mask) begin
      ram_extra_tlrr_extra_size[ram_extra_tlrr_extra_size_MPORT_addr] <= ram_extra_tlrr_extra_size_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (reset) begin // @[Decoupled.scala 262:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 262:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 279:27]
      maybe_full <= do_enq; // @[Decoupled.scala 280:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_read[initvar] = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_index[initvar] = _RAND_1[9:0];
  _RAND_2 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_data[initvar] = _RAND_2[31:0];
  _RAND_3 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_mask[initvar] = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_extra_tlrr_extra_source[initvar] = _RAND_4[6:0];
  _RAND_5 = {1{`RANDOM}};
  for (initvar = 0; initvar < 1; initvar = initvar+1)
    ram_extra_tlrr_extra_size[initvar] = _RAND_5[1:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_6 = {1{`RANDOM}};
  maybe_full = _RAND_6[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLMockAON(
  input         clock,
  input         reset,
  output        auto_int_out_0,
  output        auto_int_out_1,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [1:0]  auto_in_a_bits_size,
  input  [6:0]  auto_in_a_bits_source,
  input  [28:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [1:0]  auto_in_d_bits_size,
  output [6:0]  auto_in_d_bits_source,
  output [31:0] auto_in_d_bits_data,
  output        io_moff_corerst,
  output        io_wdog_rst,
  output        io_lfclk,
  input         io_lfextclk,
  input         io_resetCauses_wdogrst,
  input         io_resetCauses_erst
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
`endif // RANDOMIZE_REG_INIT
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  rtc_clock; // @[MockAON.scala 62:19]
  wire  rtc_reset; // @[MockAON.scala 62:19]
  wire  rtc_scale_io_regs_cfg_write__countAlways; // @[MockAON.scala 62:19]
  wire [3:0] rtc_scale_io_regs_cfg_write__scale; // @[MockAON.scala 62:19]
  wire  rtc_scale_io_regs_cfg_read_ip_0; // @[MockAON.scala 62:19]
  wire  rtc_scale_io_regs_cfg_read_countAlways; // @[MockAON.scala 62:19]
  wire [3:0] rtc_scale_io_regs_cfg_read_scale; // @[MockAON.scala 62:19]
  wire  rtc_scale_io_regs_cfg_write_countAlways; // @[MockAON.scala 62:19]
  wire  rtc_scale_io_regs_cfg_write_scale; // @[MockAON.scala 62:19]
  wire  rtc_scale_io_regs_countLo_write_valid; // @[MockAON.scala 62:19]
  wire [31:0] rtc_scale_io_regs_countLo_write_bits; // @[MockAON.scala 62:19]
  wire [31:0] rtc_scale_io_regs_countLo_read; // @[MockAON.scala 62:19]
  wire  rtc_scale_io_regs_countHi_write_valid; // @[MockAON.scala 62:19]
  wire [31:0] rtc_scale_io_regs_countHi_write_bits; // @[MockAON.scala 62:19]
  wire [31:0] rtc_scale_io_regs_countHi_read; // @[MockAON.scala 62:19]
  wire [31:0] rtc_scale_io_regs_s_read; // @[MockAON.scala 62:19]
  wire  rtc_scale_io_regs_cmp_0_write_valid; // @[MockAON.scala 62:19]
  wire [31:0] rtc_scale_io_regs_cmp_0_write_bits; // @[MockAON.scala 62:19]
  wire [31:0] rtc_scale_io_regs_cmp_0_read; // @[MockAON.scala 62:19]
  wire  rtc_scale_io_ip_0; // @[MockAON.scala 62:19]
  wire  pmu_clock; // @[MockAON.scala 64:19]
  wire  pmu_reset; // @[MockAON.scala 64:19]
  wire  pmu_io_wakeup_rtc; // @[MockAON.scala 64:19]
  wire  pmu_io_control_corerst; // @[MockAON.scala 64:19]
  wire  pmu_io_regs_ie_write_valid; // @[MockAON.scala 64:19]
  wire [3:0] pmu_io_regs_ie_write_bits; // @[MockAON.scala 64:19]
  wire [3:0] pmu_io_regs_ie_read; // @[MockAON.scala 64:19]
  wire  pmu_io_regs_cause_write_valid; // @[MockAON.scala 64:19]
  wire [31:0] pmu_io_regs_cause_read; // @[MockAON.scala 64:19]
  wire  pmu_io_regs_sleep_write_valid; // @[MockAON.scala 64:19]
  wire  pmu_io_regs_key_write_valid; // @[MockAON.scala 64:19]
  wire [31:0] pmu_io_regs_key_write_bits; // @[MockAON.scala 64:19]
  wire [31:0] pmu_io_regs_key_read; // @[MockAON.scala 64:19]
  wire  pmu_io_regs_wakeupProgram_0_write_valid; // @[MockAON.scala 64:19]
  wire [31:0] pmu_io_regs_wakeupProgram_0_write_bits; // @[MockAON.scala 64:19]
  wire [31:0] pmu_io_regs_wakeupProgram_0_read; // @[MockAON.scala 64:19]
  wire  pmu_io_regs_wakeupProgram_1_write_valid; // @[MockAON.scala 64:19]
  wire [31:0] pmu_io_regs_wakeupProgram_1_write_bits; // @[MockAON.scala 64:19]
  wire [31:0] pmu_io_regs_wakeupProgram_1_read; // @[MockAON.scala 64:19]
  wire  pmu_io_regs_wakeupProgram_2_write_valid; // @[MockAON.scala 64:19]
  wire [31:0] pmu_io_regs_wakeupProgram_2_write_bits; // @[MockAON.scala 64:19]
  wire [31:0] pmu_io_regs_wakeupProgram_2_read; // @[MockAON.scala 64:19]
  wire  pmu_io_regs_wakeupProgram_3_write_valid; // @[MockAON.scala 64:19]
  wire [31:0] pmu_io_regs_wakeupProgram_3_write_bits; // @[MockAON.scala 64:19]
  wire [31:0] pmu_io_regs_wakeupProgram_3_read; // @[MockAON.scala 64:19]
  wire  pmu_io_regs_wakeupProgram_4_write_valid; // @[MockAON.scala 64:19]
  wire [31:0] pmu_io_regs_wakeupProgram_4_write_bits; // @[MockAON.scala 64:19]
  wire [31:0] pmu_io_regs_wakeupProgram_4_read; // @[MockAON.scala 64:19]
  wire  pmu_io_regs_wakeupProgram_5_write_valid; // @[MockAON.scala 64:19]
  wire [31:0] pmu_io_regs_wakeupProgram_5_write_bits; // @[MockAON.scala 64:19]
  wire [31:0] pmu_io_regs_wakeupProgram_5_read; // @[MockAON.scala 64:19]
  wire  pmu_io_regs_wakeupProgram_6_write_valid; // @[MockAON.scala 64:19]
  wire [31:0] pmu_io_regs_wakeupProgram_6_write_bits; // @[MockAON.scala 64:19]
  wire [31:0] pmu_io_regs_wakeupProgram_6_read; // @[MockAON.scala 64:19]
  wire  pmu_io_regs_wakeupProgram_7_write_valid; // @[MockAON.scala 64:19]
  wire [31:0] pmu_io_regs_wakeupProgram_7_write_bits; // @[MockAON.scala 64:19]
  wire [31:0] pmu_io_regs_wakeupProgram_7_read; // @[MockAON.scala 64:19]
  wire  pmu_io_regs_sleepProgram_0_write_valid; // @[MockAON.scala 64:19]
  wire [31:0] pmu_io_regs_sleepProgram_0_write_bits; // @[MockAON.scala 64:19]
  wire [31:0] pmu_io_regs_sleepProgram_0_read; // @[MockAON.scala 64:19]
  wire  pmu_io_regs_sleepProgram_1_write_valid; // @[MockAON.scala 64:19]
  wire [31:0] pmu_io_regs_sleepProgram_1_write_bits; // @[MockAON.scala 64:19]
  wire [31:0] pmu_io_regs_sleepProgram_1_read; // @[MockAON.scala 64:19]
  wire  pmu_io_regs_sleepProgram_2_write_valid; // @[MockAON.scala 64:19]
  wire [31:0] pmu_io_regs_sleepProgram_2_write_bits; // @[MockAON.scala 64:19]
  wire [31:0] pmu_io_regs_sleepProgram_2_read; // @[MockAON.scala 64:19]
  wire  pmu_io_regs_sleepProgram_3_write_valid; // @[MockAON.scala 64:19]
  wire [31:0] pmu_io_regs_sleepProgram_3_write_bits; // @[MockAON.scala 64:19]
  wire [31:0] pmu_io_regs_sleepProgram_3_read; // @[MockAON.scala 64:19]
  wire  pmu_io_regs_sleepProgram_4_write_valid; // @[MockAON.scala 64:19]
  wire [31:0] pmu_io_regs_sleepProgram_4_write_bits; // @[MockAON.scala 64:19]
  wire [31:0] pmu_io_regs_sleepProgram_4_read; // @[MockAON.scala 64:19]
  wire  pmu_io_regs_sleepProgram_5_write_valid; // @[MockAON.scala 64:19]
  wire [31:0] pmu_io_regs_sleepProgram_5_write_bits; // @[MockAON.scala 64:19]
  wire [31:0] pmu_io_regs_sleepProgram_5_read; // @[MockAON.scala 64:19]
  wire  pmu_io_regs_sleepProgram_6_write_valid; // @[MockAON.scala 64:19]
  wire [31:0] pmu_io_regs_sleepProgram_6_write_bits; // @[MockAON.scala 64:19]
  wire [31:0] pmu_io_regs_sleepProgram_6_read; // @[MockAON.scala 64:19]
  wire  pmu_io_regs_sleepProgram_7_write_valid; // @[MockAON.scala 64:19]
  wire [31:0] pmu_io_regs_sleepProgram_7_write_bits; // @[MockAON.scala 64:19]
  wire [31:0] pmu_io_regs_sleepProgram_7_read; // @[MockAON.scala 64:19]
  wire  pmu_io_resetCauses_wdogrst; // @[MockAON.scala 64:19]
  wire  pmu_io_resetCauses_erst; // @[MockAON.scala 64:19]
  wire  wdog_clock; // @[MockAON.scala 79:20]
  wire  wdog_reset; // @[MockAON.scala 79:20]
  wire  wdog_scale_io_regs_cfg_write__ip_0; // @[MockAON.scala 79:20]
  wire  wdog_scale_io_regs_cfg_write__running; // @[MockAON.scala 79:20]
  wire  wdog_scale_io_regs_cfg_write__countAlways; // @[MockAON.scala 79:20]
  wire  wdog_scale_io_regs_cfg_write__zerocmp; // @[MockAON.scala 79:20]
  wire  wdog_scale_io_regs_cfg_write__sticky; // @[MockAON.scala 79:20]
  wire [3:0] wdog_scale_io_regs_cfg_write__scale; // @[MockAON.scala 79:20]
  wire  wdog_scale_io_regs_cfg_read_ip_0; // @[MockAON.scala 79:20]
  wire  wdog_scale_io_regs_cfg_read_running; // @[MockAON.scala 79:20]
  wire  wdog_scale_io_regs_cfg_read_countAlways; // @[MockAON.scala 79:20]
  wire  wdog_scale_io_regs_cfg_read_zerocmp; // @[MockAON.scala 79:20]
  wire  wdog_scale_io_regs_cfg_read_sticky; // @[MockAON.scala 79:20]
  wire [3:0] wdog_scale_io_regs_cfg_read_scale; // @[MockAON.scala 79:20]
  wire  wdog_scale_io_regs_cfg_write_ip_0; // @[MockAON.scala 79:20]
  wire  wdog_scale_io_regs_cfg_write_gang_0; // @[MockAON.scala 79:20]
  wire  wdog_scale_io_regs_cfg_write_extra_0; // @[MockAON.scala 79:20]
  wire  wdog_scale_io_regs_cfg_write_center_0; // @[MockAON.scala 79:20]
  wire  wdog_scale_io_regs_cfg_write_running; // @[MockAON.scala 79:20]
  wire  wdog_scale_io_regs_cfg_write_countAlways; // @[MockAON.scala 79:20]
  wire  wdog_scale_io_regs_cfg_write_deglitch; // @[MockAON.scala 79:20]
  wire  wdog_scale_io_regs_cfg_write_zerocmp; // @[MockAON.scala 79:20]
  wire  wdog_scale_io_regs_cfg_write_sticky; // @[MockAON.scala 79:20]
  wire  wdog_scale_io_regs_cfg_write_scale; // @[MockAON.scala 79:20]
  wire  wdog_scale_io_regs_countLo_write_valid; // @[MockAON.scala 79:20]
  wire [30:0] wdog_scale_io_regs_countLo_write_bits; // @[MockAON.scala 79:20]
  wire [30:0] wdog_scale_io_regs_countLo_read; // @[MockAON.scala 79:20]
  wire  wdog_scale_io_regs_countHi_write_valid; // @[MockAON.scala 79:20]
  wire  wdog_scale_io_regs_s_write_valid; // @[MockAON.scala 79:20]
  wire [15:0] wdog_scale_io_regs_s_read; // @[MockAON.scala 79:20]
  wire  wdog_scale_io_regs_cmp_0_write_valid; // @[MockAON.scala 79:20]
  wire [15:0] wdog_scale_io_regs_cmp_0_write_bits; // @[MockAON.scala 79:20]
  wire [15:0] wdog_scale_io_regs_cmp_0_read; // @[MockAON.scala 79:20]
  wire  wdog_scale_io_regs_feed_write_valid; // @[MockAON.scala 79:20]
  wire [31:0] wdog_scale_io_regs_feed_write_bits; // @[MockAON.scala 79:20]
  wire  wdog_scale_io_regs_key_write_valid; // @[MockAON.scala 79:20]
  wire [31:0] wdog_scale_io_regs_key_write_bits; // @[MockAON.scala 79:20]
  wire [31:0] wdog_scale_io_regs_key_read; // @[MockAON.scala 79:20]
  wire  wdog_scale_io_ip_0; // @[MockAON.scala 79:20]
  wire  wdog_scale_io_corerst; // @[MockAON.scala 79:20]
  wire  wdog_scale_io_rst; // @[MockAON.scala 79:20]
  wire  out_back_clock; // @[Decoupled.scala 361:21]
  wire  out_back_reset; // @[Decoupled.scala 361:21]
  wire  out_back_io_enq_ready; // @[Decoupled.scala 361:21]
  wire  out_back_io_enq_valid; // @[Decoupled.scala 361:21]
  wire  out_back_io_enq_bits_read; // @[Decoupled.scala 361:21]
  wire [9:0] out_back_io_enq_bits_index; // @[Decoupled.scala 361:21]
  wire [31:0] out_back_io_enq_bits_data; // @[Decoupled.scala 361:21]
  wire [3:0] out_back_io_enq_bits_mask; // @[Decoupled.scala 361:21]
  wire [6:0] out_back_io_enq_bits_extra_tlrr_extra_source; // @[Decoupled.scala 361:21]
  wire [1:0] out_back_io_enq_bits_extra_tlrr_extra_size; // @[Decoupled.scala 361:21]
  wire  out_back_io_deq_ready; // @[Decoupled.scala 361:21]
  wire  out_back_io_deq_valid; // @[Decoupled.scala 361:21]
  wire  out_back_io_deq_bits_read; // @[Decoupled.scala 361:21]
  wire [9:0] out_back_io_deq_bits_index; // @[Decoupled.scala 361:21]
  wire [31:0] out_back_io_deq_bits_data; // @[Decoupled.scala 361:21]
  wire [3:0] out_back_io_deq_bits_mask; // @[Decoupled.scala 361:21]
  wire [6:0] out_back_io_deq_bits_extra_tlrr_extra_source; // @[Decoupled.scala 361:21]
  wire [1:0] out_back_io_deq_bits_extra_tlrr_extra_size; // @[Decoupled.scala 361:21]
  reg [31:0] backupRegs_0; // @[MockAON.scala 87:47]
  reg [31:0] backupRegs_1; // @[MockAON.scala 87:47]
  reg [31:0] backupRegs_2; // @[MockAON.scala 87:47]
  reg [31:0] backupRegs_3; // @[MockAON.scala 87:47]
  reg [31:0] backupRegs_4; // @[MockAON.scala 87:47]
  reg [31:0] backupRegs_5; // @[MockAON.scala 87:47]
  reg [31:0] backupRegs_6; // @[MockAON.scala 87:47]
  reg [31:0] backupRegs_7; // @[MockAON.scala 87:47]
  reg [31:0] backupRegs_8; // @[MockAON.scala 87:47]
  reg [31:0] backupRegs_9; // @[MockAON.scala 87:47]
  reg [31:0] backupRegs_10; // @[MockAON.scala 87:47]
  reg [31:0] backupRegs_11; // @[MockAON.scala 87:47]
  reg [31:0] backupRegs_12; // @[MockAON.scala 87:47]
  reg [31:0] backupRegs_13; // @[MockAON.scala 87:47]
  reg [31:0] backupRegs_14; // @[MockAON.scala 87:47]
  reg [31:0] backupRegs_15; // @[MockAON.scala 87:47]
  wire [9:0] out_bindex = out_back_io_deq_bits_index & 10'h380; // @[RegisterRouter.scala 83:24]
  wire  _out_T_1 = out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [7:0] _out_backMask_T_5 = out_back_io_deq_bits_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_backMask_T_7 = out_back_io_deq_bits_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_backMask_T_9 = out_back_io_deq_bits_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_backMask_T_11 = out_back_io_deq_bits_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [31:0] out_backMask = {_out_backMask_T_11,_out_backMask_T_9,_out_backMask_T_7,_out_backMask_T_5}; // @[Cat.scala 31:58]
  wire  out_womask = &out_backMask; // @[RegisterRouter.scala 83:24]
  wire [6:0] out_oindex = {out_back_io_deq_bits_index[6],out_back_io_deq_bits_index[5],out_back_io_deq_bits_index[4],
    out_back_io_deq_bits_index[3],out_back_io_deq_bits_index[2],out_back_io_deq_bits_index[1],out_back_io_deq_bits_index
    [0]}; // @[Cat.scala 31:58]
  wire [127:0] _out_backSel_T = 128'h1 << out_oindex; // @[OneHot.scala 57:35]
  wire  out_backSel_69 = _out_backSel_T[69]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_0 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_69 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [31:0] _out_T_100 = out_back_io_deq_bits_data; // @[RegisterRouter.scala 83:24]
  wire [31:0] _out_T_105 = pmu_io_regs_wakeupProgram_5_read; // @[RegisterRouter.scala 83:24]
  wire  out_womask_1 = &out_backMask[3:0]; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_0 = _out_backSel_T[0]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_1 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_0 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [3:0] _out_T_116 = wdog_scale_io_regs_cfg_read_scale; // @[RegisterRouter.scala 83:24]
  wire [4:0] out_prepend = {1'h0,_out_T_116}; // @[Cat.scala 31:58]
  wire [7:0] _out_T_125 = {{3'd0}, out_prepend}; // @[RegisterRouter.scala 83:24]
  wire  out_womask_3 = &out_backMask[8]; // @[RegisterRouter.scala 83:24]
  wire  out_womask_4 = &out_backMask[9]; // @[RegisterRouter.scala 83:24]
  wire  out_womask_5 = &out_backMask[10]; // @[RegisterRouter.scala 83:24]
  wire  out_womask_7 = &out_backMask[12]; // @[RegisterRouter.scala 83:24]
  wire  out_womask_8 = &out_backMask[13]; // @[RegisterRouter.scala 83:24]
  wire [14:0] out_prepend_7 = {1'h0,wdog_scale_io_regs_cfg_read_running,wdog_scale_io_regs_cfg_read_countAlways,1'h0,1'h0
    ,wdog_scale_io_regs_cfg_read_zerocmp,wdog_scale_io_regs_cfg_read_sticky,_out_T_125}; // @[Cat.scala 31:58]
  wire [15:0] _out_T_196 = {{1'd0}, out_prepend_7}; // @[RegisterRouter.scala 83:24]
  wire  out_womask_10 = &out_backMask[16]; // @[RegisterRouter.scala 83:24]
  wire [17:0] out_prepend_9 = {1'h0,1'h0,_out_T_196}; // @[Cat.scala 31:58]
  wire [19:0] _out_T_214 = {{2'd0}, out_prepend_9}; // @[RegisterRouter.scala 83:24]
  wire  out_womask_12 = &out_backMask[20]; // @[RegisterRouter.scala 83:24]
  wire [21:0] out_prepend_11 = {1'h0,1'h0,_out_T_214}; // @[Cat.scala 31:58]
  wire [23:0] _out_T_232 = {{2'd0}, out_prepend_11}; // @[RegisterRouter.scala 83:24]
  wire  out_womask_14 = &out_backMask[24]; // @[RegisterRouter.scala 83:24]
  wire [25:0] out_prepend_13 = {1'h0,1'h0,_out_T_232}; // @[Cat.scala 31:58]
  wire [27:0] _out_T_250 = {{2'd0}, out_prepend_13}; // @[RegisterRouter.scala 83:24]
  wire  out_womask_16 = &out_backMask[28]; // @[RegisterRouter.scala 83:24]
  wire [29:0] out_prepend_15 = {1'h0,wdog_scale_io_regs_cfg_read_ip_0,_out_T_250}; // @[Cat.scala 31:58]
  wire [31:0] _out_T_270 = {{2'd0}, out_prepend_15}; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_42 = _out_backSel_T[42]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_18 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_42 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_18 = out_woready_18 & out_womask; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_24 = _out_backSel_T[24]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_19 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_24 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [31:0] _out_T_288 = rtc_scale_io_regs_cmp_0_read; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_37 = _out_backSel_T[37]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_20 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_37 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_20 = out_woready_20 & out_womask; // @[RegisterRouter.scala 83:24]
  wire [31:0] _out_T_304 = rtc_scale_io_regs_s_read; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_46 = _out_backSel_T[46]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_22 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_46 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_22 = out_woready_22 & out_womask; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_78 = _out_backSel_T[78]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_23 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_78 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [31:0] _out_T_318 = pmu_io_regs_sleepProgram_6_read; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_74 = _out_backSel_T[74]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_24 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_74 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [31:0] _out_T_325 = pmu_io_regs_sleepProgram_2_read; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_6 = _out_backSel_T[6]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_25 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_6 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_38 = _out_backSel_T[38]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_26 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_38 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_26 = out_woready_26 & out_womask; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_70 = _out_backSel_T[70]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_27 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_70 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [31:0] _out_T_350 = pmu_io_regs_wakeupProgram_6_read; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_33 = _out_backSel_T[33]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_28 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_33 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_28 = out_woready_28 & out_womask; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_65 = _out_backSel_T[65]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_29 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_65 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [31:0] _out_T_364 = pmu_io_regs_wakeupProgram_1_read; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_77 = _out_backSel_T[77]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_30 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_77 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [31:0] _out_T_371 = pmu_io_regs_sleepProgram_5_read; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_41 = _out_backSel_T[41]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_31 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_41 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_31 = out_woready_31 & out_womask; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_73 = _out_backSel_T[73]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_32 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_73 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [31:0] _out_T_385 = pmu_io_regs_sleepProgram_1_read; // @[RegisterRouter.scala 83:24]
  wire  out_womask_33 = &out_backMask[30:0]; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_2 = _out_backSel_T[2]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_33 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_2 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [30:0] _out_T_396 = wdog_scale_io_regs_countLo_read; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_32 = _out_backSel_T[32]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_34 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_32 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_34 = out_woready_34 & out_womask; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_34 = _out_backSel_T[34]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_35 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_34 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_35 = out_woready_35 & out_womask; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_45 = _out_backSel_T[45]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_36 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_45 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_36 = out_woready_36 & out_womask; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_64 = _out_backSel_T[64]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_37 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_64 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [31:0] _out_T_424 = pmu_io_regs_wakeupProgram_0_read; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_44 = _out_backSel_T[44]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_39 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_44 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_39 = out_woready_39 & out_womask; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_71 = _out_backSel_T[71]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_40 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_71 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [31:0] _out_T_447 = pmu_io_regs_wakeupProgram_7_read; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_81 = _out_backSel_T[81]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_41 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_81 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [31:0] _out_T_454 = pmu_io_regs_cause_read; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_76 = _out_backSel_T[76]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_42 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_76 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [31:0] _out_T_461 = pmu_io_regs_sleepProgram_4_read; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_7 = _out_backSel_T[7]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_43 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_7 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [31:0] _out_T_472 = wdog_scale_io_regs_key_read; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_39 = _out_backSel_T[39]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_44 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_39 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_44 = out_woready_44 & out_womask; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_66 = _out_backSel_T[66]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_45 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_66 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [31:0] _out_T_486 = pmu_io_regs_wakeupProgram_2_read; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_3 = _out_backSel_T[3]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_46 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_3 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_80 = _out_backSel_T[80]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_47 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_80 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [3:0] _out_T_502 = pmu_io_regs_ie_read; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_35 = _out_backSel_T[35]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_48 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_35 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_48 = out_woready_48 & out_womask; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_18 = _out_backSel_T[18]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_49 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_18 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [31:0] _out_T_520 = rtc_scale_io_regs_countLo_read; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_67 = _out_backSel_T[67]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_50 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_67 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [31:0] _out_T_527 = pmu_io_regs_wakeupProgram_3_read; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_16 = _out_backSel_T[16]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_51 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_16 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [3:0] _out_T_538 = rtc_scale_io_regs_cfg_read_scale; // @[RegisterRouter.scala 83:24]
  wire [4:0] out_prepend_16 = {1'h0,_out_T_538}; // @[Cat.scala 31:58]
  wire [7:0] _out_T_547 = {{3'd0}, out_prepend_16}; // @[RegisterRouter.scala 83:24]
  wire [14:0] out_prepend_23 = {1'h0,1'h0,rtc_scale_io_regs_cfg_read_countAlways,1'h0,1'h0,1'h0,1'h0,_out_T_547}; // @[Cat.scala 31:58]
  wire [15:0] _out_T_612 = {{1'd0}, out_prepend_23}; // @[RegisterRouter.scala 83:24]
  wire [17:0] out_prepend_25 = {1'h0,1'h0,_out_T_612}; // @[Cat.scala 31:58]
  wire [19:0] _out_T_630 = {{2'd0}, out_prepend_25}; // @[RegisterRouter.scala 83:24]
  wire [21:0] out_prepend_27 = {1'h0,1'h0,_out_T_630}; // @[Cat.scala 31:58]
  wire [23:0] _out_T_648 = {{2'd0}, out_prepend_27}; // @[RegisterRouter.scala 83:24]
  wire [25:0] out_prepend_29 = {1'h0,1'h0,_out_T_648}; // @[Cat.scala 31:58]
  wire [27:0] _out_T_666 = {{2'd0}, out_prepend_29}; // @[RegisterRouter.scala 83:24]
  wire [29:0] out_prepend_31 = {1'h0,rtc_scale_io_regs_cfg_read_ip_0,_out_T_666}; // @[Cat.scala 31:58]
  wire [31:0] _out_T_686 = {{2'd0}, out_prepend_31}; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_72 = _out_backSel_T[72]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_68 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_72 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [31:0] _out_T_693 = pmu_io_regs_sleepProgram_0_read; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_43 = _out_backSel_T[43]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_69 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_43 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_69 = out_woready_69 & out_womask; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_40 = _out_backSel_T[40]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_70 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_40 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_70 = out_woready_70 & out_womask; // @[RegisterRouter.scala 83:24]
  wire  out_womask_72 = &out_backMask[15:0]; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_8 = _out_backSel_T[8]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_72 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_8 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_T_727 = wdog_scale_io_regs_cmp_0_read; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_75 = _out_backSel_T[75]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_73 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_75 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [31:0] _out_T_734 = pmu_io_regs_sleepProgram_3_read; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_82 = _out_backSel_T[82]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_74 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_82 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_36 = _out_backSel_T[36]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_75 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_36 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_75 = out_woready_75 & out_womask; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_19 = _out_backSel_T[19]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_76 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_19 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [31:0] _out_T_759 = rtc_scale_io_regs_countHi_read; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_4 = _out_backSel_T[4]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_77 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_4 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_T_768 = wdog_scale_io_regs_s_read; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_79 = _out_backSel_T[79]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_78 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_79 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [31:0] _out_T_775 = pmu_io_regs_sleepProgram_7_read; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_47 = _out_backSel_T[47]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_79 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_47 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_79 = out_woready_79 & out_womask; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_68 = _out_backSel_T[68]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_80 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_68 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [31:0] _out_T_789 = pmu_io_regs_wakeupProgram_4_read; // @[RegisterRouter.scala 83:24]
  wire  out_backSel_83 = _out_backSel_T[83]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_81 = out_back_io_deq_valid & auto_in_d_ready & ~out_back_io_deq_bits_read & out_backSel_83 &
    out_bindex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [31:0] _out_T_796 = pmu_io_regs_key_read; // @[RegisterRouter.scala 83:24]
  wire  _GEN_528 = 7'h53 == out_oindex ? _out_T_1 : 1'h1; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_529 = 7'h52 == out_oindex ? _out_T_1 : _GEN_528; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_530 = 7'h51 == out_oindex ? _out_T_1 : _GEN_529; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_531 = 7'h50 == out_oindex ? _out_T_1 : _GEN_530; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_532 = 7'h4f == out_oindex ? _out_T_1 : _GEN_531; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_533 = 7'h4e == out_oindex ? _out_T_1 : _GEN_532; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_534 = 7'h4d == out_oindex ? _out_T_1 : _GEN_533; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_535 = 7'h4c == out_oindex ? _out_T_1 : _GEN_534; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_536 = 7'h4b == out_oindex ? _out_T_1 : _GEN_535; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_537 = 7'h4a == out_oindex ? _out_T_1 : _GEN_536; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_538 = 7'h49 == out_oindex ? _out_T_1 : _GEN_537; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_539 = 7'h48 == out_oindex ? _out_T_1 : _GEN_538; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_540 = 7'h47 == out_oindex ? _out_T_1 : _GEN_539; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_541 = 7'h46 == out_oindex ? _out_T_1 : _GEN_540; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_542 = 7'h45 == out_oindex ? _out_T_1 : _GEN_541; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_543 = 7'h44 == out_oindex ? _out_T_1 : _GEN_542; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_544 = 7'h43 == out_oindex ? _out_T_1 : _GEN_543; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_545 = 7'h42 == out_oindex ? _out_T_1 : _GEN_544; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_546 = 7'h41 == out_oindex ? _out_T_1 : _GEN_545; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_547 = 7'h40 == out_oindex ? _out_T_1 : _GEN_546; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_548 = 7'h2f == out_oindex ? _out_T_1 : _GEN_547; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_549 = 7'h2e == out_oindex ? _out_T_1 : _GEN_548; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_550 = 7'h2d == out_oindex ? _out_T_1 : _GEN_549; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_551 = 7'h2c == out_oindex ? _out_T_1 : _GEN_550; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_552 = 7'h2b == out_oindex ? _out_T_1 : _GEN_551; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_553 = 7'h2a == out_oindex ? _out_T_1 : _GEN_552; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_554 = 7'h29 == out_oindex ? _out_T_1 : _GEN_553; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_555 = 7'h28 == out_oindex ? _out_T_1 : _GEN_554; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_556 = 7'h27 == out_oindex ? _out_T_1 : _GEN_555; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_557 = 7'h26 == out_oindex ? _out_T_1 : _GEN_556; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_558 = 7'h25 == out_oindex ? _out_T_1 : _GEN_557; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_559 = 7'h24 == out_oindex ? _out_T_1 : _GEN_558; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_560 = 7'h23 == out_oindex ? _out_T_1 : _GEN_559; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_561 = 7'h22 == out_oindex ? _out_T_1 : _GEN_560; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_562 = 7'h21 == out_oindex ? _out_T_1 : _GEN_561; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_563 = 7'h20 == out_oindex ? _out_T_1 : _GEN_562; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_564 = 7'h18 == out_oindex ? _out_T_1 : _GEN_563; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_565 = 7'h17 == out_oindex ? _out_T_1 : _GEN_564; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_566 = 7'h16 == out_oindex ? _out_T_1 : _GEN_565; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_567 = 7'h14 == out_oindex ? _out_T_1 : _GEN_566; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_568 = 7'h13 == out_oindex ? _out_T_1 : _GEN_567; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_569 = 7'h12 == out_oindex ? _out_T_1 : _GEN_568; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_570 = 7'h10 == out_oindex ? _out_T_1 : _GEN_569; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_571 = 7'h8 == out_oindex ? _out_T_1 : _GEN_570; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_572 = 7'h7 == out_oindex ? _out_T_1 : _GEN_571; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_573 = 7'h6 == out_oindex ? _out_T_1 : _GEN_572; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_574 = 7'h4 == out_oindex ? _out_T_1 : _GEN_573; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_575 = 7'h3 == out_oindex ? _out_T_1 : _GEN_574; // @[MuxLiteral.scala 53:{26,32}]
  wire  _GEN_576 = 7'h2 == out_oindex ? _out_T_1 : _GEN_575; // @[MuxLiteral.scala 53:{26,32}]
  wire  out_out_bits_data_out = 7'h0 == out_oindex ? _out_T_1 : _GEN_576; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_578 = 7'h53 == out_oindex ? _out_T_796 : 32'h0; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_579 = 7'h52 == out_oindex ? 32'h0 : _GEN_578; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_580 = 7'h51 == out_oindex ? _out_T_454 : _GEN_579; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_581 = 7'h50 == out_oindex ? {{28'd0}, _out_T_502} : _GEN_580; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_582 = 7'h4f == out_oindex ? _out_T_775 : _GEN_581; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_583 = 7'h4e == out_oindex ? _out_T_318 : _GEN_582; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_584 = 7'h4d == out_oindex ? _out_T_371 : _GEN_583; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_585 = 7'h4c == out_oindex ? _out_T_461 : _GEN_584; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_586 = 7'h4b == out_oindex ? _out_T_734 : _GEN_585; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_587 = 7'h4a == out_oindex ? _out_T_325 : _GEN_586; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_588 = 7'h49 == out_oindex ? _out_T_385 : _GEN_587; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_589 = 7'h48 == out_oindex ? _out_T_693 : _GEN_588; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_590 = 7'h47 == out_oindex ? _out_T_447 : _GEN_589; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_591 = 7'h46 == out_oindex ? _out_T_350 : _GEN_590; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_592 = 7'h45 == out_oindex ? _out_T_105 : _GEN_591; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_593 = 7'h44 == out_oindex ? _out_T_789 : _GEN_592; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_594 = 7'h43 == out_oindex ? _out_T_527 : _GEN_593; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_595 = 7'h42 == out_oindex ? _out_T_486 : _GEN_594; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_596 = 7'h41 == out_oindex ? _out_T_364 : _GEN_595; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_597 = 7'h40 == out_oindex ? _out_T_424 : _GEN_596; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_598 = 7'h2f == out_oindex ? backupRegs_15 : _GEN_597; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_599 = 7'h2e == out_oindex ? backupRegs_14 : _GEN_598; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_600 = 7'h2d == out_oindex ? backupRegs_13 : _GEN_599; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_601 = 7'h2c == out_oindex ? backupRegs_12 : _GEN_600; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_602 = 7'h2b == out_oindex ? backupRegs_11 : _GEN_601; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_603 = 7'h2a == out_oindex ? backupRegs_10 : _GEN_602; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_604 = 7'h29 == out_oindex ? backupRegs_9 : _GEN_603; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_605 = 7'h28 == out_oindex ? backupRegs_8 : _GEN_604; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_606 = 7'h27 == out_oindex ? backupRegs_7 : _GEN_605; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_607 = 7'h26 == out_oindex ? backupRegs_6 : _GEN_606; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_608 = 7'h25 == out_oindex ? backupRegs_5 : _GEN_607; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_609 = 7'h24 == out_oindex ? backupRegs_4 : _GEN_608; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_610 = 7'h23 == out_oindex ? backupRegs_3 : _GEN_609; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_611 = 7'h22 == out_oindex ? backupRegs_2 : _GEN_610; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_612 = 7'h21 == out_oindex ? backupRegs_1 : _GEN_611; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_613 = 7'h20 == out_oindex ? backupRegs_0 : _GEN_612; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_614 = 7'h18 == out_oindex ? _out_T_288 : _GEN_613; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_615 = 7'h17 == out_oindex ? 32'h1 : _GEN_614; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_616 = 7'h16 == out_oindex ? 32'h0 : _GEN_615; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_617 = 7'h14 == out_oindex ? _out_T_304 : _GEN_616; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_618 = 7'h13 == out_oindex ? _out_T_759 : _GEN_617; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_619 = 7'h12 == out_oindex ? _out_T_520 : _GEN_618; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_620 = 7'h10 == out_oindex ? _out_T_686 : _GEN_619; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_621 = 7'h8 == out_oindex ? {{16'd0}, _out_T_727} : _GEN_620; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_622 = 7'h7 == out_oindex ? _out_T_472 : _GEN_621; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_623 = 7'h6 == out_oindex ? 32'h0 : _GEN_622; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_624 = 7'h4 == out_oindex ? {{16'd0}, _out_T_768} : _GEN_623; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_625 = 7'h3 == out_oindex ? 32'h0 : _GEN_624; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] _GEN_626 = 7'h2 == out_oindex ? {{1'd0}, _out_T_396} : _GEN_625; // @[MuxLiteral.scala 53:{26,32}]
  wire [31:0] out_out_bits_data_out_1 = 7'h0 == out_oindex ? _out_T_270 : _GEN_626; // @[MuxLiteral.scala 53:{26,32}]
  wire  out_bits_read = out_back_io_deq_bits_read; // @[RegisterRouter.scala 83:{24,24}]
  TLMonitor_55 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  RTC rtc ( // @[MockAON.scala 62:19]
    .clock(rtc_clock),
    .reset(rtc_reset),
    .scale_io_regs_cfg_write__countAlways(rtc_scale_io_regs_cfg_write__countAlways),
    .scale_io_regs_cfg_write__scale(rtc_scale_io_regs_cfg_write__scale),
    .scale_io_regs_cfg_read_ip_0(rtc_scale_io_regs_cfg_read_ip_0),
    .scale_io_regs_cfg_read_countAlways(rtc_scale_io_regs_cfg_read_countAlways),
    .scale_io_regs_cfg_read_scale(rtc_scale_io_regs_cfg_read_scale),
    .scale_io_regs_cfg_write_countAlways(rtc_scale_io_regs_cfg_write_countAlways),
    .scale_io_regs_cfg_write_scale(rtc_scale_io_regs_cfg_write_scale),
    .scale_io_regs_countLo_write_valid(rtc_scale_io_regs_countLo_write_valid),
    .scale_io_regs_countLo_write_bits(rtc_scale_io_regs_countLo_write_bits),
    .scale_io_regs_countLo_read(rtc_scale_io_regs_countLo_read),
    .scale_io_regs_countHi_write_valid(rtc_scale_io_regs_countHi_write_valid),
    .scale_io_regs_countHi_write_bits(rtc_scale_io_regs_countHi_write_bits),
    .scale_io_regs_countHi_read(rtc_scale_io_regs_countHi_read),
    .scale_io_regs_s_read(rtc_scale_io_regs_s_read),
    .scale_io_regs_cmp_0_write_valid(rtc_scale_io_regs_cmp_0_write_valid),
    .scale_io_regs_cmp_0_write_bits(rtc_scale_io_regs_cmp_0_write_bits),
    .scale_io_regs_cmp_0_read(rtc_scale_io_regs_cmp_0_read),
    .scale_io_ip_0(rtc_scale_io_ip_0)
  );
  PMU pmu ( // @[MockAON.scala 64:19]
    .clock(pmu_clock),
    .reset(pmu_reset),
    .io_wakeup_rtc(pmu_io_wakeup_rtc),
    .io_control_corerst(pmu_io_control_corerst),
    .io_regs_ie_write_valid(pmu_io_regs_ie_write_valid),
    .io_regs_ie_write_bits(pmu_io_regs_ie_write_bits),
    .io_regs_ie_read(pmu_io_regs_ie_read),
    .io_regs_cause_write_valid(pmu_io_regs_cause_write_valid),
    .io_regs_cause_read(pmu_io_regs_cause_read),
    .io_regs_sleep_write_valid(pmu_io_regs_sleep_write_valid),
    .io_regs_key_write_valid(pmu_io_regs_key_write_valid),
    .io_regs_key_write_bits(pmu_io_regs_key_write_bits),
    .io_regs_key_read(pmu_io_regs_key_read),
    .io_regs_wakeupProgram_0_write_valid(pmu_io_regs_wakeupProgram_0_write_valid),
    .io_regs_wakeupProgram_0_write_bits(pmu_io_regs_wakeupProgram_0_write_bits),
    .io_regs_wakeupProgram_0_read(pmu_io_regs_wakeupProgram_0_read),
    .io_regs_wakeupProgram_1_write_valid(pmu_io_regs_wakeupProgram_1_write_valid),
    .io_regs_wakeupProgram_1_write_bits(pmu_io_regs_wakeupProgram_1_write_bits),
    .io_regs_wakeupProgram_1_read(pmu_io_regs_wakeupProgram_1_read),
    .io_regs_wakeupProgram_2_write_valid(pmu_io_regs_wakeupProgram_2_write_valid),
    .io_regs_wakeupProgram_2_write_bits(pmu_io_regs_wakeupProgram_2_write_bits),
    .io_regs_wakeupProgram_2_read(pmu_io_regs_wakeupProgram_2_read),
    .io_regs_wakeupProgram_3_write_valid(pmu_io_regs_wakeupProgram_3_write_valid),
    .io_regs_wakeupProgram_3_write_bits(pmu_io_regs_wakeupProgram_3_write_bits),
    .io_regs_wakeupProgram_3_read(pmu_io_regs_wakeupProgram_3_read),
    .io_regs_wakeupProgram_4_write_valid(pmu_io_regs_wakeupProgram_4_write_valid),
    .io_regs_wakeupProgram_4_write_bits(pmu_io_regs_wakeupProgram_4_write_bits),
    .io_regs_wakeupProgram_4_read(pmu_io_regs_wakeupProgram_4_read),
    .io_regs_wakeupProgram_5_write_valid(pmu_io_regs_wakeupProgram_5_write_valid),
    .io_regs_wakeupProgram_5_write_bits(pmu_io_regs_wakeupProgram_5_write_bits),
    .io_regs_wakeupProgram_5_read(pmu_io_regs_wakeupProgram_5_read),
    .io_regs_wakeupProgram_6_write_valid(pmu_io_regs_wakeupProgram_6_write_valid),
    .io_regs_wakeupProgram_6_write_bits(pmu_io_regs_wakeupProgram_6_write_bits),
    .io_regs_wakeupProgram_6_read(pmu_io_regs_wakeupProgram_6_read),
    .io_regs_wakeupProgram_7_write_valid(pmu_io_regs_wakeupProgram_7_write_valid),
    .io_regs_wakeupProgram_7_write_bits(pmu_io_regs_wakeupProgram_7_write_bits),
    .io_regs_wakeupProgram_7_read(pmu_io_regs_wakeupProgram_7_read),
    .io_regs_sleepProgram_0_write_valid(pmu_io_regs_sleepProgram_0_write_valid),
    .io_regs_sleepProgram_0_write_bits(pmu_io_regs_sleepProgram_0_write_bits),
    .io_regs_sleepProgram_0_read(pmu_io_regs_sleepProgram_0_read),
    .io_regs_sleepProgram_1_write_valid(pmu_io_regs_sleepProgram_1_write_valid),
    .io_regs_sleepProgram_1_write_bits(pmu_io_regs_sleepProgram_1_write_bits),
    .io_regs_sleepProgram_1_read(pmu_io_regs_sleepProgram_1_read),
    .io_regs_sleepProgram_2_write_valid(pmu_io_regs_sleepProgram_2_write_valid),
    .io_regs_sleepProgram_2_write_bits(pmu_io_regs_sleepProgram_2_write_bits),
    .io_regs_sleepProgram_2_read(pmu_io_regs_sleepProgram_2_read),
    .io_regs_sleepProgram_3_write_valid(pmu_io_regs_sleepProgram_3_write_valid),
    .io_regs_sleepProgram_3_write_bits(pmu_io_regs_sleepProgram_3_write_bits),
    .io_regs_sleepProgram_3_read(pmu_io_regs_sleepProgram_3_read),
    .io_regs_sleepProgram_4_write_valid(pmu_io_regs_sleepProgram_4_write_valid),
    .io_regs_sleepProgram_4_write_bits(pmu_io_regs_sleepProgram_4_write_bits),
    .io_regs_sleepProgram_4_read(pmu_io_regs_sleepProgram_4_read),
    .io_regs_sleepProgram_5_write_valid(pmu_io_regs_sleepProgram_5_write_valid),
    .io_regs_sleepProgram_5_write_bits(pmu_io_regs_sleepProgram_5_write_bits),
    .io_regs_sleepProgram_5_read(pmu_io_regs_sleepProgram_5_read),
    .io_regs_sleepProgram_6_write_valid(pmu_io_regs_sleepProgram_6_write_valid),
    .io_regs_sleepProgram_6_write_bits(pmu_io_regs_sleepProgram_6_write_bits),
    .io_regs_sleepProgram_6_read(pmu_io_regs_sleepProgram_6_read),
    .io_regs_sleepProgram_7_write_valid(pmu_io_regs_sleepProgram_7_write_valid),
    .io_regs_sleepProgram_7_write_bits(pmu_io_regs_sleepProgram_7_write_bits),
    .io_regs_sleepProgram_7_read(pmu_io_regs_sleepProgram_7_read),
    .io_resetCauses_wdogrst(pmu_io_resetCauses_wdogrst),
    .io_resetCauses_erst(pmu_io_resetCauses_erst)
  );
  WatchdogTimer wdog ( // @[MockAON.scala 79:20]
    .clock(wdog_clock),
    .reset(wdog_reset),
    .scale_io_regs_cfg_write__ip_0(wdog_scale_io_regs_cfg_write__ip_0),
    .scale_io_regs_cfg_write__running(wdog_scale_io_regs_cfg_write__running),
    .scale_io_regs_cfg_write__countAlways(wdog_scale_io_regs_cfg_write__countAlways),
    .scale_io_regs_cfg_write__zerocmp(wdog_scale_io_regs_cfg_write__zerocmp),
    .scale_io_regs_cfg_write__sticky(wdog_scale_io_regs_cfg_write__sticky),
    .scale_io_regs_cfg_write__scale(wdog_scale_io_regs_cfg_write__scale),
    .scale_io_regs_cfg_read_ip_0(wdog_scale_io_regs_cfg_read_ip_0),
    .scale_io_regs_cfg_read_running(wdog_scale_io_regs_cfg_read_running),
    .scale_io_regs_cfg_read_countAlways(wdog_scale_io_regs_cfg_read_countAlways),
    .scale_io_regs_cfg_read_zerocmp(wdog_scale_io_regs_cfg_read_zerocmp),
    .scale_io_regs_cfg_read_sticky(wdog_scale_io_regs_cfg_read_sticky),
    .scale_io_regs_cfg_read_scale(wdog_scale_io_regs_cfg_read_scale),
    .scale_io_regs_cfg_write_ip_0(wdog_scale_io_regs_cfg_write_ip_0),
    .scale_io_regs_cfg_write_gang_0(wdog_scale_io_regs_cfg_write_gang_0),
    .scale_io_regs_cfg_write_extra_0(wdog_scale_io_regs_cfg_write_extra_0),
    .scale_io_regs_cfg_write_center_0(wdog_scale_io_regs_cfg_write_center_0),
    .scale_io_regs_cfg_write_running(wdog_scale_io_regs_cfg_write_running),
    .scale_io_regs_cfg_write_countAlways(wdog_scale_io_regs_cfg_write_countAlways),
    .scale_io_regs_cfg_write_deglitch(wdog_scale_io_regs_cfg_write_deglitch),
    .scale_io_regs_cfg_write_zerocmp(wdog_scale_io_regs_cfg_write_zerocmp),
    .scale_io_regs_cfg_write_sticky(wdog_scale_io_regs_cfg_write_sticky),
    .scale_io_regs_cfg_write_scale(wdog_scale_io_regs_cfg_write_scale),
    .scale_io_regs_countLo_write_valid(wdog_scale_io_regs_countLo_write_valid),
    .scale_io_regs_countLo_write_bits(wdog_scale_io_regs_countLo_write_bits),
    .scale_io_regs_countLo_read(wdog_scale_io_regs_countLo_read),
    .scale_io_regs_countHi_write_valid(wdog_scale_io_regs_countHi_write_valid),
    .scale_io_regs_s_write_valid(wdog_scale_io_regs_s_write_valid),
    .scale_io_regs_s_read(wdog_scale_io_regs_s_read),
    .scale_io_regs_cmp_0_write_valid(wdog_scale_io_regs_cmp_0_write_valid),
    .scale_io_regs_cmp_0_write_bits(wdog_scale_io_regs_cmp_0_write_bits),
    .scale_io_regs_cmp_0_read(wdog_scale_io_regs_cmp_0_read),
    .scale_io_regs_feed_write_valid(wdog_scale_io_regs_feed_write_valid),
    .scale_io_regs_feed_write_bits(wdog_scale_io_regs_feed_write_bits),
    .scale_io_regs_key_write_valid(wdog_scale_io_regs_key_write_valid),
    .scale_io_regs_key_write_bits(wdog_scale_io_regs_key_write_bits),
    .scale_io_regs_key_read(wdog_scale_io_regs_key_read),
    .scale_io_ip_0(wdog_scale_io_ip_0),
    .scale_io_corerst(wdog_scale_io_corerst),
    .scale_io_rst(wdog_scale_io_rst)
  );
  Queue_23 out_back ( // @[Decoupled.scala 361:21]
    .clock(out_back_clock),
    .reset(out_back_reset),
    .io_enq_ready(out_back_io_enq_ready),
    .io_enq_valid(out_back_io_enq_valid),
    .io_enq_bits_read(out_back_io_enq_bits_read),
    .io_enq_bits_index(out_back_io_enq_bits_index),
    .io_enq_bits_data(out_back_io_enq_bits_data),
    .io_enq_bits_mask(out_back_io_enq_bits_mask),
    .io_enq_bits_extra_tlrr_extra_source(out_back_io_enq_bits_extra_tlrr_extra_source),
    .io_enq_bits_extra_tlrr_extra_size(out_back_io_enq_bits_extra_tlrr_extra_size),
    .io_deq_ready(out_back_io_deq_ready),
    .io_deq_valid(out_back_io_deq_valid),
    .io_deq_bits_read(out_back_io_deq_bits_read),
    .io_deq_bits_index(out_back_io_deq_bits_index),
    .io_deq_bits_data(out_back_io_deq_bits_data),
    .io_deq_bits_mask(out_back_io_deq_bits_mask),
    .io_deq_bits_extra_tlrr_extra_source(out_back_io_deq_bits_extra_tlrr_extra_source),
    .io_deq_bits_extra_tlrr_extra_size(out_back_io_deq_bits_extra_tlrr_extra_size)
  );
  assign auto_int_out_0 = wdog_scale_io_ip_0; // @[Nodes.scala 1207:84 MockAON.scala 82:17]
  assign auto_int_out_1 = rtc_scale_io_ip_0; // @[Nodes.scala 1207:84 MockAON.scala 77:17]
  assign auto_in_a_ready = out_back_io_enq_ready; // @[Decoupled.scala 365:17 RegisterRouter.scala 83:24]
  assign auto_in_d_valid = out_back_io_deq_valid; // @[RegisterRouter.scala 83:24]
  assign auto_in_d_bits_opcode = {{2'd0}, out_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign auto_in_d_bits_size = out_back_io_deq_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala 83:{24,24}]
  assign auto_in_d_bits_source = out_back_io_deq_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala 83:{24,24}]
  assign auto_in_d_bits_data = out_out_bits_data_out ? out_out_bits_data_out_1 : 32'h0; // @[RegisterRouter.scala 83:24]
  assign io_moff_corerst = pmu_io_control_corerst; // @[MockAON.scala 65:11]
  assign io_wdog_rst = wdog_scale_io_rst; // @[MockAON.scala 80:15]
  assign io_lfclk = io_lfextclk; // @[MockAON.scala 85:12]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = out_back_io_enq_ready; // @[Decoupled.scala 365:17 RegisterRouter.scala 83:24]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = out_back_io_deq_valid; // @[RegisterRouter.scala 83:24]
  assign monitor_io_in_d_bits_opcode = {{2'd0}, out_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign monitor_io_in_d_bits_size = out_back_io_deq_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala 83:{24,24}]
  assign monitor_io_in_d_bits_source = out_back_io_deq_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala 83:{24,24}]
  assign rtc_clock = clock;
  assign rtc_reset = reset;
  assign rtc_scale_io_regs_cfg_write__countAlways = out_back_io_deq_bits_data[12]; // @[RegisterRouter.scala 83:24]
  assign rtc_scale_io_regs_cfg_write__scale = out_back_io_deq_bits_data[3:0]; // @[RegisterRouter.scala 83:24]
  assign rtc_scale_io_regs_cfg_write_countAlways = out_woready_51 & out_womask_7; // @[RegisterRouter.scala 83:24]
  assign rtc_scale_io_regs_cfg_write_scale = out_woready_51 & out_womask_1; // @[RegisterRouter.scala 83:24]
  assign rtc_scale_io_regs_countLo_write_valid = out_woready_49 & out_womask; // @[RegisterRouter.scala 83:24]
  assign rtc_scale_io_regs_countLo_write_bits = out_back_io_deq_bits_data; // @[RegisterRouter.scala 83:24]
  assign rtc_scale_io_regs_countHi_write_valid = out_woready_76 & out_womask; // @[RegisterRouter.scala 83:24]
  assign rtc_scale_io_regs_countHi_write_bits = out_back_io_deq_bits_data; // @[RegisterRouter.scala 83:24]
  assign rtc_scale_io_regs_cmp_0_write_valid = out_woready_19 & out_womask; // @[RegisterRouter.scala 83:24]
  assign rtc_scale_io_regs_cmp_0_write_bits = out_back_io_deq_bits_data; // @[RegisterRouter.scala 83:24]
  assign pmu_clock = clock;
  assign pmu_reset = reset;
  assign pmu_io_wakeup_rtc = rtc_scale_io_ip_0; // @[MockAON.scala 69:21]
  assign pmu_io_regs_ie_write_valid = out_woready_47 & out_womask_1; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_ie_write_bits = out_back_io_deq_bits_data[3:0]; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_cause_write_valid = out_woready_41 & out_womask; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_sleep_write_valid = out_woready_74 & out_womask; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_key_write_valid = out_woready_81 & out_womask; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_key_write_bits = out_back_io_deq_bits_data; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_wakeupProgram_0_write_valid = out_woready_37 & out_womask; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_wakeupProgram_0_write_bits = out_back_io_deq_bits_data; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_wakeupProgram_1_write_valid = out_woready_29 & out_womask; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_wakeupProgram_1_write_bits = out_back_io_deq_bits_data; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_wakeupProgram_2_write_valid = out_woready_45 & out_womask; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_wakeupProgram_2_write_bits = out_back_io_deq_bits_data; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_wakeupProgram_3_write_valid = out_woready_50 & out_womask; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_wakeupProgram_3_write_bits = out_back_io_deq_bits_data; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_wakeupProgram_4_write_valid = out_woready_80 & out_womask; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_wakeupProgram_4_write_bits = out_back_io_deq_bits_data; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_wakeupProgram_5_write_valid = out_woready_0 & out_womask; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_wakeupProgram_5_write_bits = out_back_io_deq_bits_data; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_wakeupProgram_6_write_valid = out_woready_27 & out_womask; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_wakeupProgram_6_write_bits = out_back_io_deq_bits_data; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_wakeupProgram_7_write_valid = out_woready_40 & out_womask; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_wakeupProgram_7_write_bits = out_back_io_deq_bits_data; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_sleepProgram_0_write_valid = out_woready_68 & out_womask; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_sleepProgram_0_write_bits = out_back_io_deq_bits_data; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_sleepProgram_1_write_valid = out_woready_32 & out_womask; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_sleepProgram_1_write_bits = out_back_io_deq_bits_data; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_sleepProgram_2_write_valid = out_woready_24 & out_womask; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_sleepProgram_2_write_bits = out_back_io_deq_bits_data; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_sleepProgram_3_write_valid = out_woready_73 & out_womask; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_sleepProgram_3_write_bits = out_back_io_deq_bits_data; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_sleepProgram_4_write_valid = out_woready_42 & out_womask; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_sleepProgram_4_write_bits = out_back_io_deq_bits_data; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_sleepProgram_5_write_valid = out_woready_30 & out_womask; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_sleepProgram_5_write_bits = out_back_io_deq_bits_data; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_sleepProgram_6_write_valid = out_woready_23 & out_womask; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_sleepProgram_6_write_bits = out_back_io_deq_bits_data; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_sleepProgram_7_write_valid = out_woready_78 & out_womask; // @[RegisterRouter.scala 83:24]
  assign pmu_io_regs_sleepProgram_7_write_bits = out_back_io_deq_bits_data; // @[RegisterRouter.scala 83:24]
  assign pmu_io_resetCauses_wdogrst = io_resetCauses_wdogrst; // @[MockAON.scala 70:22]
  assign pmu_io_resetCauses_erst = io_resetCauses_erst; // @[MockAON.scala 70:22]
  assign wdog_clock = clock;
  assign wdog_reset = reset;
  assign wdog_scale_io_regs_cfg_write__ip_0 = out_back_io_deq_bits_data[28]; // @[RegisterRouter.scala 83:24]
  assign wdog_scale_io_regs_cfg_write__running = out_back_io_deq_bits_data[13]; // @[RegisterRouter.scala 83:24]
  assign wdog_scale_io_regs_cfg_write__countAlways = out_back_io_deq_bits_data[12]; // @[RegisterRouter.scala 83:24]
  assign wdog_scale_io_regs_cfg_write__zerocmp = out_back_io_deq_bits_data[9]; // @[RegisterRouter.scala 83:24]
  assign wdog_scale_io_regs_cfg_write__sticky = out_back_io_deq_bits_data[8]; // @[RegisterRouter.scala 83:24]
  assign wdog_scale_io_regs_cfg_write__scale = out_back_io_deq_bits_data[3:0]; // @[RegisterRouter.scala 83:24]
  assign wdog_scale_io_regs_cfg_write_ip_0 = out_woready_1 & out_womask_16; // @[RegisterRouter.scala 83:24]
  assign wdog_scale_io_regs_cfg_write_gang_0 = out_woready_1 & out_womask_14; // @[RegisterRouter.scala 83:24]
  assign wdog_scale_io_regs_cfg_write_extra_0 = out_woready_1 & out_womask_12; // @[RegisterRouter.scala 83:24]
  assign wdog_scale_io_regs_cfg_write_center_0 = out_woready_1 & out_womask_10; // @[RegisterRouter.scala 83:24]
  assign wdog_scale_io_regs_cfg_write_running = out_woready_1 & out_womask_8; // @[RegisterRouter.scala 83:24]
  assign wdog_scale_io_regs_cfg_write_countAlways = out_woready_1 & out_womask_7; // @[RegisterRouter.scala 83:24]
  assign wdog_scale_io_regs_cfg_write_deglitch = out_woready_1 & out_womask_5; // @[RegisterRouter.scala 83:24]
  assign wdog_scale_io_regs_cfg_write_zerocmp = out_woready_1 & out_womask_4; // @[RegisterRouter.scala 83:24]
  assign wdog_scale_io_regs_cfg_write_sticky = out_woready_1 & out_womask_3; // @[RegisterRouter.scala 83:24]
  assign wdog_scale_io_regs_cfg_write_scale = out_woready_1 & out_womask_1; // @[RegisterRouter.scala 83:24]
  assign wdog_scale_io_regs_countLo_write_valid = out_woready_33 & out_womask_33; // @[RegisterRouter.scala 83:24]
  assign wdog_scale_io_regs_countLo_write_bits = out_back_io_deq_bits_data[30:0]; // @[RegisterRouter.scala 83:24]
  assign wdog_scale_io_regs_countHi_write_valid = out_woready_46 & out_womask; // @[RegisterRouter.scala 83:24]
  assign wdog_scale_io_regs_s_write_valid = out_woready_77 & out_womask_72; // @[RegisterRouter.scala 83:24]
  assign wdog_scale_io_regs_cmp_0_write_valid = out_woready_72 & out_womask_72; // @[RegisterRouter.scala 83:24]
  assign wdog_scale_io_regs_cmp_0_write_bits = out_back_io_deq_bits_data[15:0]; // @[RegisterRouter.scala 83:24]
  assign wdog_scale_io_regs_feed_write_valid = out_woready_25 & out_womask; // @[RegisterRouter.scala 83:24]
  assign wdog_scale_io_regs_feed_write_bits = out_back_io_deq_bits_data; // @[RegisterRouter.scala 83:24]
  assign wdog_scale_io_regs_key_write_valid = out_woready_43 & out_womask; // @[RegisterRouter.scala 83:24]
  assign wdog_scale_io_regs_key_write_bits = out_back_io_deq_bits_data; // @[RegisterRouter.scala 83:24]
  assign wdog_scale_io_corerst = pmu_io_control_corerst; // @[MockAON.scala 81:19]
  assign out_back_clock = clock;
  assign out_back_reset = reset;
  assign out_back_io_enq_valid = auto_in_a_valid; // @[RegisterRouter.scala 83:24]
  assign out_back_io_enq_bits_read = auto_in_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 72:36]
  assign out_back_io_enq_bits_index = auto_in_a_bits_address[11:2]; // @[RegisterRouter.scala 71:18 73:19]
  assign out_back_io_enq_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign out_back_io_enq_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign out_back_io_enq_bits_extra_tlrr_extra_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign out_back_io_enq_bits_extra_tlrr_extra_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign out_back_io_deq_ready = auto_in_d_ready; // @[RegisterRouter.scala 83:24]
  always @(posedge clock) begin
    if (out_f_woready_34) begin // @[RegField.scala 74:88]
      backupRegs_0 <= _out_T_100; // @[RegField.scala 74:92]
    end
    if (out_f_woready_28) begin // @[RegField.scala 74:88]
      backupRegs_1 <= _out_T_100; // @[RegField.scala 74:92]
    end
    if (out_f_woready_35) begin // @[RegField.scala 74:88]
      backupRegs_2 <= _out_T_100; // @[RegField.scala 74:92]
    end
    if (out_f_woready_48) begin // @[RegField.scala 74:88]
      backupRegs_3 <= _out_T_100; // @[RegField.scala 74:92]
    end
    if (out_f_woready_75) begin // @[RegField.scala 74:88]
      backupRegs_4 <= _out_T_100; // @[RegField.scala 74:92]
    end
    if (out_f_woready_20) begin // @[RegField.scala 74:88]
      backupRegs_5 <= _out_T_100; // @[RegField.scala 74:92]
    end
    if (out_f_woready_26) begin // @[RegField.scala 74:88]
      backupRegs_6 <= _out_T_100; // @[RegField.scala 74:92]
    end
    if (out_f_woready_44) begin // @[RegField.scala 74:88]
      backupRegs_7 <= _out_T_100; // @[RegField.scala 74:92]
    end
    if (out_f_woready_70) begin // @[RegField.scala 74:88]
      backupRegs_8 <= _out_T_100; // @[RegField.scala 74:92]
    end
    if (out_f_woready_31) begin // @[RegField.scala 74:88]
      backupRegs_9 <= _out_T_100; // @[RegField.scala 74:92]
    end
    if (out_f_woready_18) begin // @[RegField.scala 74:88]
      backupRegs_10 <= _out_T_100; // @[RegField.scala 74:92]
    end
    if (out_f_woready_69) begin // @[RegField.scala 74:88]
      backupRegs_11 <= _out_T_100; // @[RegField.scala 74:92]
    end
    if (out_f_woready_39) begin // @[RegField.scala 74:88]
      backupRegs_12 <= _out_T_100; // @[RegField.scala 74:92]
    end
    if (out_f_woready_36) begin // @[RegField.scala 74:88]
      backupRegs_13 <= _out_T_100; // @[RegField.scala 74:92]
    end
    if (out_f_woready_22) begin // @[RegField.scala 74:88]
      backupRegs_14 <= _out_T_100; // @[RegField.scala 74:92]
    end
    if (out_f_woready_79) begin // @[RegField.scala 74:88]
      backupRegs_15 <= _out_T_100; // @[RegField.scala 74:92]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  backupRegs_0 = _RAND_0[31:0];
  _RAND_1 = {1{`RANDOM}};
  backupRegs_1 = _RAND_1[31:0];
  _RAND_2 = {1{`RANDOM}};
  backupRegs_2 = _RAND_2[31:0];
  _RAND_3 = {1{`RANDOM}};
  backupRegs_3 = _RAND_3[31:0];
  _RAND_4 = {1{`RANDOM}};
  backupRegs_4 = _RAND_4[31:0];
  _RAND_5 = {1{`RANDOM}};
  backupRegs_5 = _RAND_5[31:0];
  _RAND_6 = {1{`RANDOM}};
  backupRegs_6 = _RAND_6[31:0];
  _RAND_7 = {1{`RANDOM}};
  backupRegs_7 = _RAND_7[31:0];
  _RAND_8 = {1{`RANDOM}};
  backupRegs_8 = _RAND_8[31:0];
  _RAND_9 = {1{`RANDOM}};
  backupRegs_9 = _RAND_9[31:0];
  _RAND_10 = {1{`RANDOM}};
  backupRegs_10 = _RAND_10[31:0];
  _RAND_11 = {1{`RANDOM}};
  backupRegs_11 = _RAND_11[31:0];
  _RAND_12 = {1{`RANDOM}};
  backupRegs_12 = _RAND_12[31:0];
  _RAND_13 = {1{`RANDOM}};
  backupRegs_13 = _RAND_13[31:0];
  _RAND_14 = {1{`RANDOM}};
  backupRegs_14 = _RAND_14[31:0];
  _RAND_15 = {1{`RANDOM}};
  backupRegs_15 = _RAND_15[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module IsoZero(
  input   io_in,
  input   io_iso,
  output  io_out
);
  assign io_out = io_in & ~io_iso; // @[MockAONWrapper.scala 158:19]
endmodule
module TLIsolation(
  input  [2:0]  auto_in_a_mem_0_opcode,
  input  [2:0]  auto_in_a_mem_0_param,
  input  [1:0]  auto_in_a_mem_0_size,
  input  [6:0]  auto_in_a_mem_0_source,
  input  [28:0] auto_in_a_mem_0_address,
  input  [3:0]  auto_in_a_mem_0_mask,
  input  [31:0] auto_in_a_mem_0_data,
  input         auto_in_a_mem_0_corrupt,
  output        auto_in_a_ridx,
  input         auto_in_a_widx,
  output        auto_in_a_safe_ridx_valid,
  input         auto_in_a_safe_widx_valid,
  input         auto_in_a_safe_source_reset_n,
  output        auto_in_a_safe_sink_reset_n,
  output [2:0]  auto_in_d_mem_0_opcode,
  output [1:0]  auto_in_d_mem_0_param,
  output [1:0]  auto_in_d_mem_0_size,
  output [6:0]  auto_in_d_mem_0_source,
  output        auto_in_d_mem_0_sink,
  output        auto_in_d_mem_0_denied,
  output [31:0] auto_in_d_mem_0_data,
  output        auto_in_d_mem_0_corrupt,
  input         auto_in_d_ridx,
  output        auto_in_d_widx,
  input         auto_in_d_safe_ridx_valid,
  output        auto_in_d_safe_widx_valid,
  output        auto_in_d_safe_source_reset_n,
  input         auto_in_d_safe_sink_reset_n,
  output [2:0]  auto_out_a_mem_0_opcode,
  output [2:0]  auto_out_a_mem_0_param,
  output [1:0]  auto_out_a_mem_0_size,
  output [6:0]  auto_out_a_mem_0_source,
  output [28:0] auto_out_a_mem_0_address,
  output [3:0]  auto_out_a_mem_0_mask,
  output [31:0] auto_out_a_mem_0_data,
  output        auto_out_a_mem_0_corrupt,
  input         auto_out_a_ridx,
  output        auto_out_a_widx,
  input         auto_out_a_safe_ridx_valid,
  output        auto_out_a_safe_widx_valid,
  output        auto_out_a_safe_source_reset_n,
  input         auto_out_a_safe_sink_reset_n,
  input  [2:0]  auto_out_d_mem_0_opcode,
  input  [1:0]  auto_out_d_mem_0_size,
  input  [6:0]  auto_out_d_mem_0_source,
  input  [31:0] auto_out_d_mem_0_data,
  output        auto_out_d_ridx,
  input         auto_out_d_widx,
  output        auto_out_d_safe_ridx_valid,
  input         auto_out_d_safe_widx_valid,
  input         auto_out_d_safe_source_reset_n,
  output        auto_out_d_safe_sink_reset_n,
  input         io_iso_out
);
  wire  iso_0_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_0_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_0_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_1_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_1_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_1_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_2_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_2_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_2_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_3_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_3_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_3_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_4_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_4_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_4_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_5_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_5_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_5_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_6_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_6_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_6_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_7_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_7_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_7_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_8_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_8_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_8_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_9_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_9_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_9_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_10_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_10_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_10_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_11_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_11_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_11_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_12_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_12_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_12_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_13_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_13_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_13_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_14_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_14_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_14_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_15_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_15_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_15_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_16_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_16_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_16_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_17_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_17_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_17_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_18_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_18_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_18_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_19_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_19_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_19_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_20_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_20_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_20_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_21_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_21_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_21_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_22_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_22_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_22_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_23_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_23_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_23_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_24_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_24_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_24_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_25_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_25_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_25_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_26_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_26_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_26_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_27_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_27_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_27_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_28_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_28_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_28_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_29_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_29_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_29_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_30_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_30_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_30_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_31_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_31_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_31_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_32_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_32_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_32_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_33_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_33_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_33_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_34_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_34_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_34_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_35_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_35_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_35_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_36_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_36_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_36_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_37_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_37_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_37_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_38_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_38_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_38_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_39_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_39_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_39_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_40_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_40_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_40_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_41_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_41_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_41_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_42_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_42_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_42_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_43_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_43_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_43_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_44_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_44_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_44_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_45_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_45_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_45_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_46_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_46_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_46_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_47_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_47_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_47_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_48_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_48_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_48_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_49_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_49_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_49_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_50_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_50_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_50_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_51_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_51_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_51_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_52_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_52_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_52_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_53_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_53_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_53_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_54_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_54_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_54_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_55_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_55_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_55_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_56_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_56_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_56_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_57_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_57_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_57_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_58_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_58_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_58_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_59_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_59_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_59_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_60_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_60_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_60_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_61_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_61_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_61_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_62_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_62_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_62_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_63_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_63_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_63_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_64_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_64_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_64_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_65_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_65_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_65_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_66_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_66_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_66_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_67_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_67_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_67_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_68_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_68_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_68_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_69_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_69_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_69_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_70_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_70_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_70_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_71_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_71_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_71_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_72_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_72_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_72_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_73_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_73_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_73_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_74_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_74_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_74_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_75_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_75_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_75_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_76_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_76_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_76_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_77_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_77_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_77_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_78_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_78_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_78_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_79_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_79_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_79_io_out; // @[MockAONWrapper.scala 166:18]
  wire  iso_80_io_in; // @[MockAONWrapper.scala 166:18]
  wire  iso_80_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  iso_80_io_out; // @[MockAONWrapper.scala 166:18]
  wire  bundleOut_0_a_widx_iso_0_io_in; // @[MockAONWrapper.scala 166:18]
  wire  bundleOut_0_a_widx_iso_0_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  bundleOut_0_a_widx_iso_0_io_out; // @[MockAONWrapper.scala 166:18]
  wire  bundleOut_0_a_safe_widx_valid_iso_0_io_in; // @[MockAONWrapper.scala 166:18]
  wire  bundleOut_0_a_safe_widx_valid_iso_0_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  bundleOut_0_a_safe_widx_valid_iso_0_io_out; // @[MockAONWrapper.scala 166:18]
  wire  bundleOut_0_a_safe_source_reset_n_iso_0_io_in; // @[MockAONWrapper.scala 166:18]
  wire  bundleOut_0_a_safe_source_reset_n_iso_0_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  bundleOut_0_a_safe_source_reset_n_iso_0_io_out; // @[MockAONWrapper.scala 166:18]
  wire  bundleOut_0_d_ridx_iso_0_io_in; // @[MockAONWrapper.scala 166:18]
  wire  bundleOut_0_d_ridx_iso_0_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  bundleOut_0_d_ridx_iso_0_io_out; // @[MockAONWrapper.scala 166:18]
  wire  bundleOut_0_d_safe_ridx_valid_iso_0_io_in; // @[MockAONWrapper.scala 166:18]
  wire  bundleOut_0_d_safe_ridx_valid_iso_0_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  bundleOut_0_d_safe_ridx_valid_iso_0_io_out; // @[MockAONWrapper.scala 166:18]
  wire  bundleOut_0_d_safe_sink_reset_n_iso_0_io_in; // @[MockAONWrapper.scala 166:18]
  wire  bundleOut_0_d_safe_sink_reset_n_iso_0_io_iso; // @[MockAONWrapper.scala 166:18]
  wire  bundleOut_0_d_safe_sink_reset_n_iso_0_io_out; // @[MockAONWrapper.scala 166:18]
  wire [80:0] _T = {auto_in_a_mem_0_opcode,auto_in_a_mem_0_param,auto_in_a_mem_0_size,auto_in_a_mem_0_source,
    auto_in_a_mem_0_address,auto_in_a_mem_0_mask,auto_in_a_mem_0_data,auto_in_a_mem_0_corrupt}; // @[Isolation.scala 21:66]
  wire [9:0] lo_lo_lo = {iso_9_io_out,iso_8_io_out,iso_7_io_out,iso_6_io_out,iso_5_io_out,iso_4_io_out,iso_3_io_out,
    iso_2_io_out,iso_1_io_out,iso_0_io_out}; // @[Cat.scala 31:58]
  wire [9:0] lo_lo_hi = {iso_19_io_out,iso_18_io_out,iso_17_io_out,iso_16_io_out,iso_15_io_out,iso_14_io_out,
    iso_13_io_out,iso_12_io_out,iso_11_io_out,iso_10_io_out}; // @[Cat.scala 31:58]
  wire [9:0] lo_hi_lo = {iso_29_io_out,iso_28_io_out,iso_27_io_out,iso_26_io_out,iso_25_io_out,iso_24_io_out,
    iso_23_io_out,iso_22_io_out,iso_21_io_out,iso_20_io_out}; // @[Cat.scala 31:58]
  wire [9:0] lo_hi_hi = {iso_39_io_out,iso_38_io_out,iso_37_io_out,iso_36_io_out,iso_35_io_out,iso_34_io_out,
    iso_33_io_out,iso_32_io_out,iso_31_io_out,iso_30_io_out}; // @[Cat.scala 31:58]
  wire [9:0] hi_lo_lo = {iso_49_io_out,iso_48_io_out,iso_47_io_out,iso_46_io_out,iso_45_io_out,iso_44_io_out,
    iso_43_io_out,iso_42_io_out,iso_41_io_out,iso_40_io_out}; // @[Cat.scala 31:58]
  wire [9:0] hi_lo_hi = {iso_59_io_out,iso_58_io_out,iso_57_io_out,iso_56_io_out,iso_55_io_out,iso_54_io_out,
    iso_53_io_out,iso_52_io_out,iso_51_io_out,iso_50_io_out}; // @[Cat.scala 31:58]
  wire [9:0] hi_hi_lo = {iso_69_io_out,iso_68_io_out,iso_67_io_out,iso_66_io_out,iso_65_io_out,iso_64_io_out,
    iso_63_io_out,iso_62_io_out,iso_61_io_out,iso_60_io_out}; // @[Cat.scala 31:58]
  wire [4:0] hi_hi_hi_lo = {iso_74_io_out,iso_73_io_out,iso_72_io_out,iso_71_io_out,iso_70_io_out}; // @[Cat.scala 31:58]
  wire [40:0] hi_1 = {iso_80_io_out,iso_79_io_out,iso_78_io_out,iso_77_io_out,iso_76_io_out,iso_75_io_out,hi_hi_hi_lo,
    hi_hi_lo,hi_lo_hi,hi_lo_lo}; // @[Cat.scala 31:58]
  wire [80:0] _T_1 = {hi_1,lo_hi_hi,lo_hi_lo,lo_lo_hi,lo_lo_lo}; // @[Cat.scala 31:58]
  wire [48:0] _T_10 = {auto_out_d_mem_0_opcode,2'h0,auto_out_d_mem_0_size,auto_out_d_mem_0_source,2'h0,
    auto_out_d_mem_0_data,1'h0}; // @[Isolation.scala 22:66]
  IsoZero iso_0 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_0_io_in),
    .io_iso(iso_0_io_iso),
    .io_out(iso_0_io_out)
  );
  IsoZero iso_1 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_1_io_in),
    .io_iso(iso_1_io_iso),
    .io_out(iso_1_io_out)
  );
  IsoZero iso_2 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_2_io_in),
    .io_iso(iso_2_io_iso),
    .io_out(iso_2_io_out)
  );
  IsoZero iso_3 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_3_io_in),
    .io_iso(iso_3_io_iso),
    .io_out(iso_3_io_out)
  );
  IsoZero iso_4 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_4_io_in),
    .io_iso(iso_4_io_iso),
    .io_out(iso_4_io_out)
  );
  IsoZero iso_5 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_5_io_in),
    .io_iso(iso_5_io_iso),
    .io_out(iso_5_io_out)
  );
  IsoZero iso_6 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_6_io_in),
    .io_iso(iso_6_io_iso),
    .io_out(iso_6_io_out)
  );
  IsoZero iso_7 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_7_io_in),
    .io_iso(iso_7_io_iso),
    .io_out(iso_7_io_out)
  );
  IsoZero iso_8 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_8_io_in),
    .io_iso(iso_8_io_iso),
    .io_out(iso_8_io_out)
  );
  IsoZero iso_9 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_9_io_in),
    .io_iso(iso_9_io_iso),
    .io_out(iso_9_io_out)
  );
  IsoZero iso_10 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_10_io_in),
    .io_iso(iso_10_io_iso),
    .io_out(iso_10_io_out)
  );
  IsoZero iso_11 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_11_io_in),
    .io_iso(iso_11_io_iso),
    .io_out(iso_11_io_out)
  );
  IsoZero iso_12 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_12_io_in),
    .io_iso(iso_12_io_iso),
    .io_out(iso_12_io_out)
  );
  IsoZero iso_13 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_13_io_in),
    .io_iso(iso_13_io_iso),
    .io_out(iso_13_io_out)
  );
  IsoZero iso_14 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_14_io_in),
    .io_iso(iso_14_io_iso),
    .io_out(iso_14_io_out)
  );
  IsoZero iso_15 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_15_io_in),
    .io_iso(iso_15_io_iso),
    .io_out(iso_15_io_out)
  );
  IsoZero iso_16 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_16_io_in),
    .io_iso(iso_16_io_iso),
    .io_out(iso_16_io_out)
  );
  IsoZero iso_17 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_17_io_in),
    .io_iso(iso_17_io_iso),
    .io_out(iso_17_io_out)
  );
  IsoZero iso_18 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_18_io_in),
    .io_iso(iso_18_io_iso),
    .io_out(iso_18_io_out)
  );
  IsoZero iso_19 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_19_io_in),
    .io_iso(iso_19_io_iso),
    .io_out(iso_19_io_out)
  );
  IsoZero iso_20 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_20_io_in),
    .io_iso(iso_20_io_iso),
    .io_out(iso_20_io_out)
  );
  IsoZero iso_21 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_21_io_in),
    .io_iso(iso_21_io_iso),
    .io_out(iso_21_io_out)
  );
  IsoZero iso_22 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_22_io_in),
    .io_iso(iso_22_io_iso),
    .io_out(iso_22_io_out)
  );
  IsoZero iso_23 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_23_io_in),
    .io_iso(iso_23_io_iso),
    .io_out(iso_23_io_out)
  );
  IsoZero iso_24 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_24_io_in),
    .io_iso(iso_24_io_iso),
    .io_out(iso_24_io_out)
  );
  IsoZero iso_25 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_25_io_in),
    .io_iso(iso_25_io_iso),
    .io_out(iso_25_io_out)
  );
  IsoZero iso_26 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_26_io_in),
    .io_iso(iso_26_io_iso),
    .io_out(iso_26_io_out)
  );
  IsoZero iso_27 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_27_io_in),
    .io_iso(iso_27_io_iso),
    .io_out(iso_27_io_out)
  );
  IsoZero iso_28 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_28_io_in),
    .io_iso(iso_28_io_iso),
    .io_out(iso_28_io_out)
  );
  IsoZero iso_29 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_29_io_in),
    .io_iso(iso_29_io_iso),
    .io_out(iso_29_io_out)
  );
  IsoZero iso_30 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_30_io_in),
    .io_iso(iso_30_io_iso),
    .io_out(iso_30_io_out)
  );
  IsoZero iso_31 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_31_io_in),
    .io_iso(iso_31_io_iso),
    .io_out(iso_31_io_out)
  );
  IsoZero iso_32 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_32_io_in),
    .io_iso(iso_32_io_iso),
    .io_out(iso_32_io_out)
  );
  IsoZero iso_33 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_33_io_in),
    .io_iso(iso_33_io_iso),
    .io_out(iso_33_io_out)
  );
  IsoZero iso_34 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_34_io_in),
    .io_iso(iso_34_io_iso),
    .io_out(iso_34_io_out)
  );
  IsoZero iso_35 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_35_io_in),
    .io_iso(iso_35_io_iso),
    .io_out(iso_35_io_out)
  );
  IsoZero iso_36 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_36_io_in),
    .io_iso(iso_36_io_iso),
    .io_out(iso_36_io_out)
  );
  IsoZero iso_37 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_37_io_in),
    .io_iso(iso_37_io_iso),
    .io_out(iso_37_io_out)
  );
  IsoZero iso_38 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_38_io_in),
    .io_iso(iso_38_io_iso),
    .io_out(iso_38_io_out)
  );
  IsoZero iso_39 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_39_io_in),
    .io_iso(iso_39_io_iso),
    .io_out(iso_39_io_out)
  );
  IsoZero iso_40 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_40_io_in),
    .io_iso(iso_40_io_iso),
    .io_out(iso_40_io_out)
  );
  IsoZero iso_41 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_41_io_in),
    .io_iso(iso_41_io_iso),
    .io_out(iso_41_io_out)
  );
  IsoZero iso_42 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_42_io_in),
    .io_iso(iso_42_io_iso),
    .io_out(iso_42_io_out)
  );
  IsoZero iso_43 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_43_io_in),
    .io_iso(iso_43_io_iso),
    .io_out(iso_43_io_out)
  );
  IsoZero iso_44 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_44_io_in),
    .io_iso(iso_44_io_iso),
    .io_out(iso_44_io_out)
  );
  IsoZero iso_45 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_45_io_in),
    .io_iso(iso_45_io_iso),
    .io_out(iso_45_io_out)
  );
  IsoZero iso_46 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_46_io_in),
    .io_iso(iso_46_io_iso),
    .io_out(iso_46_io_out)
  );
  IsoZero iso_47 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_47_io_in),
    .io_iso(iso_47_io_iso),
    .io_out(iso_47_io_out)
  );
  IsoZero iso_48 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_48_io_in),
    .io_iso(iso_48_io_iso),
    .io_out(iso_48_io_out)
  );
  IsoZero iso_49 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_49_io_in),
    .io_iso(iso_49_io_iso),
    .io_out(iso_49_io_out)
  );
  IsoZero iso_50 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_50_io_in),
    .io_iso(iso_50_io_iso),
    .io_out(iso_50_io_out)
  );
  IsoZero iso_51 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_51_io_in),
    .io_iso(iso_51_io_iso),
    .io_out(iso_51_io_out)
  );
  IsoZero iso_52 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_52_io_in),
    .io_iso(iso_52_io_iso),
    .io_out(iso_52_io_out)
  );
  IsoZero iso_53 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_53_io_in),
    .io_iso(iso_53_io_iso),
    .io_out(iso_53_io_out)
  );
  IsoZero iso_54 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_54_io_in),
    .io_iso(iso_54_io_iso),
    .io_out(iso_54_io_out)
  );
  IsoZero iso_55 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_55_io_in),
    .io_iso(iso_55_io_iso),
    .io_out(iso_55_io_out)
  );
  IsoZero iso_56 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_56_io_in),
    .io_iso(iso_56_io_iso),
    .io_out(iso_56_io_out)
  );
  IsoZero iso_57 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_57_io_in),
    .io_iso(iso_57_io_iso),
    .io_out(iso_57_io_out)
  );
  IsoZero iso_58 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_58_io_in),
    .io_iso(iso_58_io_iso),
    .io_out(iso_58_io_out)
  );
  IsoZero iso_59 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_59_io_in),
    .io_iso(iso_59_io_iso),
    .io_out(iso_59_io_out)
  );
  IsoZero iso_60 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_60_io_in),
    .io_iso(iso_60_io_iso),
    .io_out(iso_60_io_out)
  );
  IsoZero iso_61 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_61_io_in),
    .io_iso(iso_61_io_iso),
    .io_out(iso_61_io_out)
  );
  IsoZero iso_62 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_62_io_in),
    .io_iso(iso_62_io_iso),
    .io_out(iso_62_io_out)
  );
  IsoZero iso_63 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_63_io_in),
    .io_iso(iso_63_io_iso),
    .io_out(iso_63_io_out)
  );
  IsoZero iso_64 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_64_io_in),
    .io_iso(iso_64_io_iso),
    .io_out(iso_64_io_out)
  );
  IsoZero iso_65 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_65_io_in),
    .io_iso(iso_65_io_iso),
    .io_out(iso_65_io_out)
  );
  IsoZero iso_66 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_66_io_in),
    .io_iso(iso_66_io_iso),
    .io_out(iso_66_io_out)
  );
  IsoZero iso_67 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_67_io_in),
    .io_iso(iso_67_io_iso),
    .io_out(iso_67_io_out)
  );
  IsoZero iso_68 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_68_io_in),
    .io_iso(iso_68_io_iso),
    .io_out(iso_68_io_out)
  );
  IsoZero iso_69 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_69_io_in),
    .io_iso(iso_69_io_iso),
    .io_out(iso_69_io_out)
  );
  IsoZero iso_70 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_70_io_in),
    .io_iso(iso_70_io_iso),
    .io_out(iso_70_io_out)
  );
  IsoZero iso_71 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_71_io_in),
    .io_iso(iso_71_io_iso),
    .io_out(iso_71_io_out)
  );
  IsoZero iso_72 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_72_io_in),
    .io_iso(iso_72_io_iso),
    .io_out(iso_72_io_out)
  );
  IsoZero iso_73 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_73_io_in),
    .io_iso(iso_73_io_iso),
    .io_out(iso_73_io_out)
  );
  IsoZero iso_74 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_74_io_in),
    .io_iso(iso_74_io_iso),
    .io_out(iso_74_io_out)
  );
  IsoZero iso_75 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_75_io_in),
    .io_iso(iso_75_io_iso),
    .io_out(iso_75_io_out)
  );
  IsoZero iso_76 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_76_io_in),
    .io_iso(iso_76_io_iso),
    .io_out(iso_76_io_out)
  );
  IsoZero iso_77 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_77_io_in),
    .io_iso(iso_77_io_iso),
    .io_out(iso_77_io_out)
  );
  IsoZero iso_78 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_78_io_in),
    .io_iso(iso_78_io_iso),
    .io_out(iso_78_io_out)
  );
  IsoZero iso_79 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_79_io_in),
    .io_iso(iso_79_io_iso),
    .io_out(iso_79_io_out)
  );
  IsoZero iso_80 ( // @[MockAONWrapper.scala 166:18]
    .io_in(iso_80_io_in),
    .io_iso(iso_80_io_iso),
    .io_out(iso_80_io_out)
  );
  IsoZero bundleOut_0_a_widx_iso_0 ( // @[MockAONWrapper.scala 166:18]
    .io_in(bundleOut_0_a_widx_iso_0_io_in),
    .io_iso(bundleOut_0_a_widx_iso_0_io_iso),
    .io_out(bundleOut_0_a_widx_iso_0_io_out)
  );
  IsoZero bundleOut_0_a_safe_widx_valid_iso_0 ( // @[MockAONWrapper.scala 166:18]
    .io_in(bundleOut_0_a_safe_widx_valid_iso_0_io_in),
    .io_iso(bundleOut_0_a_safe_widx_valid_iso_0_io_iso),
    .io_out(bundleOut_0_a_safe_widx_valid_iso_0_io_out)
  );
  IsoZero bundleOut_0_a_safe_source_reset_n_iso_0 ( // @[MockAONWrapper.scala 166:18]
    .io_in(bundleOut_0_a_safe_source_reset_n_iso_0_io_in),
    .io_iso(bundleOut_0_a_safe_source_reset_n_iso_0_io_iso),
    .io_out(bundleOut_0_a_safe_source_reset_n_iso_0_io_out)
  );
  IsoZero bundleOut_0_d_ridx_iso_0 ( // @[MockAONWrapper.scala 166:18]
    .io_in(bundleOut_0_d_ridx_iso_0_io_in),
    .io_iso(bundleOut_0_d_ridx_iso_0_io_iso),
    .io_out(bundleOut_0_d_ridx_iso_0_io_out)
  );
  IsoZero bundleOut_0_d_safe_ridx_valid_iso_0 ( // @[MockAONWrapper.scala 166:18]
    .io_in(bundleOut_0_d_safe_ridx_valid_iso_0_io_in),
    .io_iso(bundleOut_0_d_safe_ridx_valid_iso_0_io_iso),
    .io_out(bundleOut_0_d_safe_ridx_valid_iso_0_io_out)
  );
  IsoZero bundleOut_0_d_safe_sink_reset_n_iso_0 ( // @[MockAONWrapper.scala 166:18]
    .io_in(bundleOut_0_d_safe_sink_reset_n_iso_0_io_in),
    .io_iso(bundleOut_0_d_safe_sink_reset_n_iso_0_io_iso),
    .io_out(bundleOut_0_d_safe_sink_reset_n_iso_0_io_out)
  );
  assign auto_in_a_ridx = auto_out_a_ridx; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_a_safe_ridx_valid = auto_out_a_safe_ridx_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_a_safe_sink_reset_n = auto_out_a_safe_sink_reset_n; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_mem_0_opcode = _T_10[48:46]; // @[Isolation.scala 22:46]
  assign auto_in_d_mem_0_param = _T_10[45:44]; // @[Isolation.scala 22:46]
  assign auto_in_d_mem_0_size = _T_10[43:42]; // @[Isolation.scala 22:46]
  assign auto_in_d_mem_0_source = _T_10[41:35]; // @[Isolation.scala 22:46]
  assign auto_in_d_mem_0_sink = _T_10[34]; // @[Isolation.scala 22:46]
  assign auto_in_d_mem_0_denied = _T_10[33]; // @[Isolation.scala 22:46]
  assign auto_in_d_mem_0_data = _T_10[32:1]; // @[Isolation.scala 22:46]
  assign auto_in_d_mem_0_corrupt = _T_10[0]; // @[Isolation.scala 22:46]
  assign auto_in_d_widx = auto_out_d_widx; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_safe_widx_valid = auto_out_d_safe_widx_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_safe_source_reset_n = auto_out_d_safe_source_reset_n; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_mem_0_opcode = _T_1[80:78]; // @[Isolation.scala 21:46]
  assign auto_out_a_mem_0_param = _T_1[77:75]; // @[Isolation.scala 21:46]
  assign auto_out_a_mem_0_size = _T_1[74:73]; // @[Isolation.scala 21:46]
  assign auto_out_a_mem_0_source = _T_1[72:66]; // @[Isolation.scala 21:46]
  assign auto_out_a_mem_0_address = _T_1[65:37]; // @[Isolation.scala 21:46]
  assign auto_out_a_mem_0_mask = _T_1[36:33]; // @[Isolation.scala 21:46]
  assign auto_out_a_mem_0_data = _T_1[32:1]; // @[Isolation.scala 21:46]
  assign auto_out_a_mem_0_corrupt = _T_1[0]; // @[Isolation.scala 21:46]
  assign auto_out_a_widx = bundleOut_0_a_widx_iso_0_io_out; // @[Isolation.scala 21:{46,46}]
  assign auto_out_a_safe_widx_valid = bundleOut_0_a_safe_widx_valid_iso_0_io_out; // @[Isolation.scala 21:{46,46}]
  assign auto_out_a_safe_source_reset_n = bundleOut_0_a_safe_source_reset_n_iso_0_io_out; // @[Isolation.scala 21:{46,46}]
  assign auto_out_d_ridx = bundleOut_0_d_ridx_iso_0_io_out; // @[Isolation.scala 21:{46,46}]
  assign auto_out_d_safe_ridx_valid = bundleOut_0_d_safe_ridx_valid_iso_0_io_out; // @[Isolation.scala 21:{46,46}]
  assign auto_out_d_safe_sink_reset_n = bundleOut_0_d_safe_sink_reset_n_iso_0_io_out; // @[Isolation.scala 21:{46,46}]
  assign iso_0_io_in = _T[0]; // @[MockAONWrapper.scala 169:20]
  assign iso_0_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_1_io_in = _T[1]; // @[MockAONWrapper.scala 169:20]
  assign iso_1_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_2_io_in = _T[2]; // @[MockAONWrapper.scala 169:20]
  assign iso_2_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_3_io_in = _T[3]; // @[MockAONWrapper.scala 169:20]
  assign iso_3_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_4_io_in = _T[4]; // @[MockAONWrapper.scala 169:20]
  assign iso_4_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_5_io_in = _T[5]; // @[MockAONWrapper.scala 169:20]
  assign iso_5_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_6_io_in = _T[6]; // @[MockAONWrapper.scala 169:20]
  assign iso_6_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_7_io_in = _T[7]; // @[MockAONWrapper.scala 169:20]
  assign iso_7_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_8_io_in = _T[8]; // @[MockAONWrapper.scala 169:20]
  assign iso_8_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_9_io_in = _T[9]; // @[MockAONWrapper.scala 169:20]
  assign iso_9_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_10_io_in = _T[10]; // @[MockAONWrapper.scala 169:20]
  assign iso_10_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_11_io_in = _T[11]; // @[MockAONWrapper.scala 169:20]
  assign iso_11_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_12_io_in = _T[12]; // @[MockAONWrapper.scala 169:20]
  assign iso_12_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_13_io_in = _T[13]; // @[MockAONWrapper.scala 169:20]
  assign iso_13_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_14_io_in = _T[14]; // @[MockAONWrapper.scala 169:20]
  assign iso_14_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_15_io_in = _T[15]; // @[MockAONWrapper.scala 169:20]
  assign iso_15_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_16_io_in = _T[16]; // @[MockAONWrapper.scala 169:20]
  assign iso_16_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_17_io_in = _T[17]; // @[MockAONWrapper.scala 169:20]
  assign iso_17_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_18_io_in = _T[18]; // @[MockAONWrapper.scala 169:20]
  assign iso_18_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_19_io_in = _T[19]; // @[MockAONWrapper.scala 169:20]
  assign iso_19_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_20_io_in = _T[20]; // @[MockAONWrapper.scala 169:20]
  assign iso_20_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_21_io_in = _T[21]; // @[MockAONWrapper.scala 169:20]
  assign iso_21_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_22_io_in = _T[22]; // @[MockAONWrapper.scala 169:20]
  assign iso_22_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_23_io_in = _T[23]; // @[MockAONWrapper.scala 169:20]
  assign iso_23_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_24_io_in = _T[24]; // @[MockAONWrapper.scala 169:20]
  assign iso_24_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_25_io_in = _T[25]; // @[MockAONWrapper.scala 169:20]
  assign iso_25_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_26_io_in = _T[26]; // @[MockAONWrapper.scala 169:20]
  assign iso_26_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_27_io_in = _T[27]; // @[MockAONWrapper.scala 169:20]
  assign iso_27_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_28_io_in = _T[28]; // @[MockAONWrapper.scala 169:20]
  assign iso_28_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_29_io_in = _T[29]; // @[MockAONWrapper.scala 169:20]
  assign iso_29_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_30_io_in = _T[30]; // @[MockAONWrapper.scala 169:20]
  assign iso_30_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_31_io_in = _T[31]; // @[MockAONWrapper.scala 169:20]
  assign iso_31_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_32_io_in = _T[32]; // @[MockAONWrapper.scala 169:20]
  assign iso_32_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_33_io_in = _T[33]; // @[MockAONWrapper.scala 169:20]
  assign iso_33_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_34_io_in = _T[34]; // @[MockAONWrapper.scala 169:20]
  assign iso_34_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_35_io_in = _T[35]; // @[MockAONWrapper.scala 169:20]
  assign iso_35_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_36_io_in = _T[36]; // @[MockAONWrapper.scala 169:20]
  assign iso_36_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_37_io_in = _T[37]; // @[MockAONWrapper.scala 169:20]
  assign iso_37_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_38_io_in = _T[38]; // @[MockAONWrapper.scala 169:20]
  assign iso_38_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_39_io_in = _T[39]; // @[MockAONWrapper.scala 169:20]
  assign iso_39_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_40_io_in = _T[40]; // @[MockAONWrapper.scala 169:20]
  assign iso_40_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_41_io_in = _T[41]; // @[MockAONWrapper.scala 169:20]
  assign iso_41_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_42_io_in = _T[42]; // @[MockAONWrapper.scala 169:20]
  assign iso_42_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_43_io_in = _T[43]; // @[MockAONWrapper.scala 169:20]
  assign iso_43_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_44_io_in = _T[44]; // @[MockAONWrapper.scala 169:20]
  assign iso_44_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_45_io_in = _T[45]; // @[MockAONWrapper.scala 169:20]
  assign iso_45_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_46_io_in = _T[46]; // @[MockAONWrapper.scala 169:20]
  assign iso_46_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_47_io_in = _T[47]; // @[MockAONWrapper.scala 169:20]
  assign iso_47_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_48_io_in = _T[48]; // @[MockAONWrapper.scala 169:20]
  assign iso_48_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_49_io_in = _T[49]; // @[MockAONWrapper.scala 169:20]
  assign iso_49_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_50_io_in = _T[50]; // @[MockAONWrapper.scala 169:20]
  assign iso_50_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_51_io_in = _T[51]; // @[MockAONWrapper.scala 169:20]
  assign iso_51_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_52_io_in = _T[52]; // @[MockAONWrapper.scala 169:20]
  assign iso_52_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_53_io_in = _T[53]; // @[MockAONWrapper.scala 169:20]
  assign iso_53_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_54_io_in = _T[54]; // @[MockAONWrapper.scala 169:20]
  assign iso_54_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_55_io_in = _T[55]; // @[MockAONWrapper.scala 169:20]
  assign iso_55_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_56_io_in = _T[56]; // @[MockAONWrapper.scala 169:20]
  assign iso_56_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_57_io_in = _T[57]; // @[MockAONWrapper.scala 169:20]
  assign iso_57_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_58_io_in = _T[58]; // @[MockAONWrapper.scala 169:20]
  assign iso_58_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_59_io_in = _T[59]; // @[MockAONWrapper.scala 169:20]
  assign iso_59_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_60_io_in = _T[60]; // @[MockAONWrapper.scala 169:20]
  assign iso_60_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_61_io_in = _T[61]; // @[MockAONWrapper.scala 169:20]
  assign iso_61_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_62_io_in = _T[62]; // @[MockAONWrapper.scala 169:20]
  assign iso_62_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_63_io_in = _T[63]; // @[MockAONWrapper.scala 169:20]
  assign iso_63_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_64_io_in = _T[64]; // @[MockAONWrapper.scala 169:20]
  assign iso_64_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_65_io_in = _T[65]; // @[MockAONWrapper.scala 169:20]
  assign iso_65_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_66_io_in = _T[66]; // @[MockAONWrapper.scala 169:20]
  assign iso_66_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_67_io_in = _T[67]; // @[MockAONWrapper.scala 169:20]
  assign iso_67_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_68_io_in = _T[68]; // @[MockAONWrapper.scala 169:20]
  assign iso_68_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_69_io_in = _T[69]; // @[MockAONWrapper.scala 169:20]
  assign iso_69_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_70_io_in = _T[70]; // @[MockAONWrapper.scala 169:20]
  assign iso_70_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_71_io_in = _T[71]; // @[MockAONWrapper.scala 169:20]
  assign iso_71_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_72_io_in = _T[72]; // @[MockAONWrapper.scala 169:20]
  assign iso_72_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_73_io_in = _T[73]; // @[MockAONWrapper.scala 169:20]
  assign iso_73_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_74_io_in = _T[74]; // @[MockAONWrapper.scala 169:20]
  assign iso_74_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_75_io_in = _T[75]; // @[MockAONWrapper.scala 169:20]
  assign iso_75_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_76_io_in = _T[76]; // @[MockAONWrapper.scala 169:20]
  assign iso_76_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_77_io_in = _T[77]; // @[MockAONWrapper.scala 169:20]
  assign iso_77_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_78_io_in = _T[78]; // @[MockAONWrapper.scala 169:20]
  assign iso_78_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_79_io_in = _T[79]; // @[MockAONWrapper.scala 169:20]
  assign iso_79_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign iso_80_io_in = _T[80]; // @[MockAONWrapper.scala 169:20]
  assign iso_80_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign bundleOut_0_a_widx_iso_0_io_in = auto_in_a_widx; // @[MockAONWrapper.scala 169:20]
  assign bundleOut_0_a_widx_iso_0_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign bundleOut_0_a_safe_widx_valid_iso_0_io_in = auto_in_a_safe_widx_valid; // @[MockAONWrapper.scala 169:20]
  assign bundleOut_0_a_safe_widx_valid_iso_0_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign bundleOut_0_a_safe_source_reset_n_iso_0_io_in = auto_in_a_safe_source_reset_n; // @[MockAONWrapper.scala 169:20]
  assign bundleOut_0_a_safe_source_reset_n_iso_0_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign bundleOut_0_d_ridx_iso_0_io_in = auto_in_d_ridx; // @[MockAONWrapper.scala 169:20]
  assign bundleOut_0_d_ridx_iso_0_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign bundleOut_0_d_safe_ridx_valid_iso_0_io_in = auto_in_d_safe_ridx_valid; // @[MockAONWrapper.scala 169:20]
  assign bundleOut_0_d_safe_ridx_valid_iso_0_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
  assign bundleOut_0_d_safe_sink_reset_n_iso_0_io_in = auto_in_d_safe_sink_reset_n; // @[MockAONWrapper.scala 169:20]
  assign bundleOut_0_d_safe_sink_reset_n_iso_0_io_iso = io_iso_out; // @[MockAONWrapper.scala 170:16]
endmodule
module ClockCrossingReg_w81(
  input         clock,
  input  [80:0] io_d,
  output [80:0] io_q,
  input         io_en
);
`ifdef RANDOMIZE_REG_INIT
  reg [95:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg [80:0] cdc_reg; // @[Reg.scala 16:16]
  assign io_q = cdc_reg; // @[SynchronizerReg.scala 202:8]
  always @(posedge clock) begin
    if (io_en) begin // @[Reg.scala 17:18]
      cdc_reg <= io_d; // @[Reg.scala 17:22]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {3{`RANDOM}};
  cdc_reg = _RAND_0[80:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module AsyncQueueSink_4(
  input         clock,
  input         reset,
  input         io_deq_ready,
  output        io_deq_valid,
  output [2:0]  io_deq_bits_opcode,
  output [2:0]  io_deq_bits_param,
  output [1:0]  io_deq_bits_size,
  output [6:0]  io_deq_bits_source,
  output [28:0] io_deq_bits_address,
  output [3:0]  io_deq_bits_mask,
  output [31:0] io_deq_bits_data,
  output        io_deq_bits_corrupt,
  input  [2:0]  io_async_mem_0_opcode,
  input  [2:0]  io_async_mem_0_param,
  input  [1:0]  io_async_mem_0_size,
  input  [6:0]  io_async_mem_0_source,
  input  [28:0] io_async_mem_0_address,
  input  [3:0]  io_async_mem_0_mask,
  input  [31:0] io_async_mem_0_data,
  input         io_async_mem_0_corrupt,
  output        io_async_ridx,
  input         io_async_widx,
  output        io_async_safe_ridx_valid,
  input         io_async_safe_widx_valid,
  input         io_async_safe_source_reset_n,
  output        io_async_safe_sink_reset_n
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
  wire  widx_widx_gray_clock; // @[ShiftReg.scala 45:23]
  wire  widx_widx_gray_reset; // @[ShiftReg.scala 45:23]
  wire  widx_widx_gray_io_d; // @[ShiftReg.scala 45:23]
  wire  widx_widx_gray_io_q; // @[ShiftReg.scala 45:23]
  wire  io_deq_bits_deq_bits_reg_clock; // @[SynchronizerReg.scala 207:25]
  wire [80:0] io_deq_bits_deq_bits_reg_io_d; // @[SynchronizerReg.scala 207:25]
  wire [80:0] io_deq_bits_deq_bits_reg_io_q; // @[SynchronizerReg.scala 207:25]
  wire  io_deq_bits_deq_bits_reg_io_en; // @[SynchronizerReg.scala 207:25]
  wire  sink_valid_0_io_in; // @[AsyncQueue.scala 168:33]
  wire  sink_valid_0_io_out; // @[AsyncQueue.scala 168:33]
  wire  sink_valid_0_clock; // @[AsyncQueue.scala 168:33]
  wire  sink_valid_0_reset; // @[AsyncQueue.scala 168:33]
  wire  sink_valid_1_io_in; // @[AsyncQueue.scala 169:33]
  wire  sink_valid_1_io_out; // @[AsyncQueue.scala 169:33]
  wire  sink_valid_1_clock; // @[AsyncQueue.scala 169:33]
  wire  sink_valid_1_reset; // @[AsyncQueue.scala 169:33]
  wire  source_extend_io_in; // @[AsyncQueue.scala 171:31]
  wire  source_extend_io_out; // @[AsyncQueue.scala 171:31]
  wire  source_extend_clock; // @[AsyncQueue.scala 171:31]
  wire  source_extend_reset; // @[AsyncQueue.scala 171:31]
  wire  source_valid_io_in; // @[AsyncQueue.scala 172:31]
  wire  source_valid_io_out; // @[AsyncQueue.scala 172:31]
  wire  source_valid_clock; // @[AsyncQueue.scala 172:31]
  wire  source_valid_reset; // @[AsyncQueue.scala 172:31]
  wire  _ridx_T_1 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
  wire  source_ready = source_valid_io_out;
  wire  _ridx_T_2 = ~source_ready; // @[AsyncQueue.scala 144:79]
  reg  ridx_ridx_bin; // @[AsyncQueue.scala 52:25]
  wire  ridx_incremented = _ridx_T_2 ? 1'h0 : ridx_ridx_bin + _ridx_T_1; // @[AsyncQueue.scala 53:23]
  wire  widx = widx_widx_gray_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire [65:0] io_deq_bits_deq_bits_reg_io_d_lo = {io_async_mem_0_address,io_async_mem_0_mask,io_async_mem_0_data,
    io_async_mem_0_corrupt}; // @[SynchronizerReg.scala 209:24]
  wire [14:0] io_deq_bits_deq_bits_reg_io_d_hi = {io_async_mem_0_opcode,io_async_mem_0_param,io_async_mem_0_size,
    io_async_mem_0_source}; // @[SynchronizerReg.scala 209:24]
  wire [80:0] _io_deq_bits_WIRE_1 = io_deq_bits_deq_bits_reg_io_q;
  reg  valid_reg; // @[AsyncQueue.scala 161:56]
  reg  ridx_gray; // @[AsyncQueue.scala 164:55]
  AsyncResetSynchronizerShiftReg_w1_d3_i0 widx_widx_gray ( // @[ShiftReg.scala 45:23]
    .clock(widx_widx_gray_clock),
    .reset(widx_widx_gray_reset),
    .io_d(widx_widx_gray_io_d),
    .io_q(widx_widx_gray_io_q)
  );
  ClockCrossingReg_w81 io_deq_bits_deq_bits_reg ( // @[SynchronizerReg.scala 207:25]
    .clock(io_deq_bits_deq_bits_reg_clock),
    .io_d(io_deq_bits_deq_bits_reg_io_d),
    .io_q(io_deq_bits_deq_bits_reg_io_q),
    .io_en(io_deq_bits_deq_bits_reg_io_en)
  );
  AsyncValidSync sink_valid_0 ( // @[AsyncQueue.scala 168:33]
    .io_in(sink_valid_0_io_in),
    .io_out(sink_valid_0_io_out),
    .clock(sink_valid_0_clock),
    .reset(sink_valid_0_reset)
  );
  AsyncValidSync sink_valid_1 ( // @[AsyncQueue.scala 169:33]
    .io_in(sink_valid_1_io_in),
    .io_out(sink_valid_1_io_out),
    .clock(sink_valid_1_clock),
    .reset(sink_valid_1_reset)
  );
  AsyncValidSync source_extend ( // @[AsyncQueue.scala 171:31]
    .io_in(source_extend_io_in),
    .io_out(source_extend_io_out),
    .clock(source_extend_clock),
    .reset(source_extend_reset)
  );
  AsyncValidSync source_valid ( // @[AsyncQueue.scala 172:31]
    .io_in(source_valid_io_in),
    .io_out(source_valid_io_out),
    .clock(source_valid_clock),
    .reset(source_valid_reset)
  );
  assign io_deq_valid = valid_reg & source_ready; // @[AsyncQueue.scala 162:29]
  assign io_deq_bits_opcode = _io_deq_bits_WIRE_1[80:78]; // @[SynchronizerReg.scala 211:26]
  assign io_deq_bits_param = _io_deq_bits_WIRE_1[77:75]; // @[SynchronizerReg.scala 211:26]
  assign io_deq_bits_size = _io_deq_bits_WIRE_1[74:73]; // @[SynchronizerReg.scala 211:26]
  assign io_deq_bits_source = _io_deq_bits_WIRE_1[72:66]; // @[SynchronizerReg.scala 211:26]
  assign io_deq_bits_address = _io_deq_bits_WIRE_1[65:37]; // @[SynchronizerReg.scala 211:26]
  assign io_deq_bits_mask = _io_deq_bits_WIRE_1[36:33]; // @[SynchronizerReg.scala 211:26]
  assign io_deq_bits_data = _io_deq_bits_WIRE_1[32:1]; // @[SynchronizerReg.scala 211:26]
  assign io_deq_bits_corrupt = _io_deq_bits_WIRE_1[0]; // @[SynchronizerReg.scala 211:26]
  assign io_async_ridx = ridx_gray; // @[AsyncQueue.scala 165:17]
  assign io_async_safe_ridx_valid = sink_valid_1_io_out; // @[AsyncQueue.scala 185:20]
  assign io_async_safe_sink_reset_n = ~reset; // @[AsyncQueue.scala 189:25]
  assign widx_widx_gray_clock = clock;
  assign widx_widx_gray_reset = reset;
  assign widx_widx_gray_io_d = io_async_widx; // @[ShiftReg.scala 47:16]
  assign io_deq_bits_deq_bits_reg_clock = clock;
  assign io_deq_bits_deq_bits_reg_io_d = {io_deq_bits_deq_bits_reg_io_d_hi,io_deq_bits_deq_bits_reg_io_d_lo}; // @[SynchronizerReg.scala 209:24]
  assign io_deq_bits_deq_bits_reg_io_en = source_ready & ridx_incremented != widx; // @[AsyncQueue.scala 146:28]
  assign sink_valid_0_io_in = 1'h1; // @[AsyncQueue.scala 183:24]
  assign sink_valid_0_clock = clock; // @[AsyncQueue.scala 178:25]
  assign sink_valid_0_reset = reset | ~io_async_safe_source_reset_n; // @[AsyncQueue.scala 173:66]
  assign sink_valid_1_io_in = sink_valid_0_io_out; // @[AsyncQueue.scala 184:24]
  assign sink_valid_1_clock = clock; // @[AsyncQueue.scala 179:25]
  assign sink_valid_1_reset = reset | ~io_async_safe_source_reset_n; // @[AsyncQueue.scala 174:66]
  assign source_extend_io_in = io_async_safe_widx_valid; // @[AsyncQueue.scala 186:25]
  assign source_extend_clock = clock; // @[AsyncQueue.scala 180:25]
  assign source_extend_reset = reset | ~io_async_safe_source_reset_n; // @[AsyncQueue.scala 175:66]
  assign source_valid_io_in = source_extend_io_out; // @[AsyncQueue.scala 187:24]
  assign source_valid_clock = clock; // @[AsyncQueue.scala 181:25]
  assign source_valid_reset = reset; // @[AsyncQueue.scala 176:34]
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[AsyncQueue.scala 53:23]
      ridx_ridx_bin <= 1'h0;
    end else if (_ridx_T_2) begin
      ridx_ridx_bin <= 1'h0;
    end else begin
      ridx_ridx_bin <= ridx_ridx_bin + _ridx_T_1;
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[AsyncQueue.scala 146:28]
      valid_reg <= 1'h0;
    end else begin
      valid_reg <= source_ready & ridx_incremented != widx;
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[AsyncQueue.scala 53:23]
      ridx_gray <= 1'h0;
    end else if (_ridx_T_2) begin
      ridx_gray <= 1'h0;
    end else begin
      ridx_gray <= ridx_ridx_bin + _ridx_T_1;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  ridx_ridx_bin = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  valid_reg = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  ridx_gray = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
  if (reset) begin
    ridx_ridx_bin = 1'h0;
  end
  if (reset) begin
    valid_reg = 1'h0;
  end
  if (reset) begin
    ridx_gray = 1'h0;
  end
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module AsyncQueueSource_4(
  input         clock,
  input         reset,
  output        io_enq_ready,
  input         io_enq_valid,
  input  [2:0]  io_enq_bits_opcode,
  input  [1:0]  io_enq_bits_size,
  input  [6:0]  io_enq_bits_source,
  input  [31:0] io_enq_bits_data,
  output [2:0]  io_async_mem_0_opcode,
  output [1:0]  io_async_mem_0_size,
  output [6:0]  io_async_mem_0_source,
  output [31:0] io_async_mem_0_data,
  input         io_async_ridx,
  output        io_async_widx,
  input         io_async_safe_ridx_valid,
  output        io_async_safe_widx_valid,
  output        io_async_safe_source_reset_n,
  input         io_async_safe_sink_reset_n
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
`endif // RANDOMIZE_REG_INIT
  wire  ridx_ridx_gray_clock; // @[ShiftReg.scala 45:23]
  wire  ridx_ridx_gray_reset; // @[ShiftReg.scala 45:23]
  wire  ridx_ridx_gray_io_d; // @[ShiftReg.scala 45:23]
  wire  ridx_ridx_gray_io_q; // @[ShiftReg.scala 45:23]
  wire  source_valid_0_io_in; // @[AsyncQueue.scala 100:32]
  wire  source_valid_0_io_out; // @[AsyncQueue.scala 100:32]
  wire  source_valid_0_clock; // @[AsyncQueue.scala 100:32]
  wire  source_valid_0_reset; // @[AsyncQueue.scala 100:32]
  wire  source_valid_1_io_in; // @[AsyncQueue.scala 101:32]
  wire  source_valid_1_io_out; // @[AsyncQueue.scala 101:32]
  wire  source_valid_1_clock; // @[AsyncQueue.scala 101:32]
  wire  source_valid_1_reset; // @[AsyncQueue.scala 101:32]
  wire  sink_extend_io_in; // @[AsyncQueue.scala 103:30]
  wire  sink_extend_io_out; // @[AsyncQueue.scala 103:30]
  wire  sink_extend_clock; // @[AsyncQueue.scala 103:30]
  wire  sink_extend_reset; // @[AsyncQueue.scala 103:30]
  wire  sink_valid_io_in; // @[AsyncQueue.scala 104:30]
  wire  sink_valid_io_out; // @[AsyncQueue.scala 104:30]
  wire  sink_valid_clock; // @[AsyncQueue.scala 104:30]
  wire  sink_valid_reset; // @[AsyncQueue.scala 104:30]
  reg [2:0] mem_0_opcode; // @[AsyncQueue.scala 80:16]
  reg [1:0] mem_0_size; // @[AsyncQueue.scala 80:16]
  reg [6:0] mem_0_source; // @[AsyncQueue.scala 80:16]
  reg [31:0] mem_0_data; // @[AsyncQueue.scala 80:16]
  wire  _widx_T_1 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
  wire  sink_ready = sink_valid_io_out;
  wire  _widx_T_2 = ~sink_ready; // @[AsyncQueue.scala 81:79]
  reg  widx_widx_bin; // @[AsyncQueue.scala 52:25]
  wire  widx_incremented = _widx_T_2 ? 1'h0 : widx_widx_bin + _widx_T_1; // @[AsyncQueue.scala 53:23]
  wire  ridx = ridx_ridx_gray_io_q; // @[ShiftReg.scala 48:{24,24}]
  reg  ready_reg; // @[AsyncQueue.scala 88:56]
  reg  widx_gray; // @[AsyncQueue.scala 91:55]
  AsyncResetSynchronizerShiftReg_w1_d3_i0 ridx_ridx_gray ( // @[ShiftReg.scala 45:23]
    .clock(ridx_ridx_gray_clock),
    .reset(ridx_ridx_gray_reset),
    .io_d(ridx_ridx_gray_io_d),
    .io_q(ridx_ridx_gray_io_q)
  );
  AsyncValidSync source_valid_0 ( // @[AsyncQueue.scala 100:32]
    .io_in(source_valid_0_io_in),
    .io_out(source_valid_0_io_out),
    .clock(source_valid_0_clock),
    .reset(source_valid_0_reset)
  );
  AsyncValidSync source_valid_1 ( // @[AsyncQueue.scala 101:32]
    .io_in(source_valid_1_io_in),
    .io_out(source_valid_1_io_out),
    .clock(source_valid_1_clock),
    .reset(source_valid_1_reset)
  );
  AsyncValidSync sink_extend ( // @[AsyncQueue.scala 103:30]
    .io_in(sink_extend_io_in),
    .io_out(sink_extend_io_out),
    .clock(sink_extend_clock),
    .reset(sink_extend_reset)
  );
  AsyncValidSync sink_valid ( // @[AsyncQueue.scala 104:30]
    .io_in(sink_valid_io_in),
    .io_out(sink_valid_io_out),
    .clock(sink_valid_clock),
    .reset(sink_valid_reset)
  );
  assign io_enq_ready = ready_reg & sink_ready; // @[AsyncQueue.scala 89:29]
  assign io_async_mem_0_opcode = mem_0_opcode; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_0_size = mem_0_size; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_0_source = mem_0_source; // @[AsyncQueue.scala 96:31]
  assign io_async_mem_0_data = mem_0_data; // @[AsyncQueue.scala 96:31]
  assign io_async_widx = widx_gray; // @[AsyncQueue.scala 92:17]
  assign io_async_safe_widx_valid = source_valid_1_io_out; // @[AsyncQueue.scala 117:20]
  assign io_async_safe_source_reset_n = ~reset; // @[AsyncQueue.scala 121:27]
  assign ridx_ridx_gray_clock = clock;
  assign ridx_ridx_gray_reset = reset;
  assign ridx_ridx_gray_io_d = io_async_ridx; // @[ShiftReg.scala 47:16]
  assign source_valid_0_io_in = 1'h1; // @[AsyncQueue.scala 115:26]
  assign source_valid_0_clock = clock; // @[AsyncQueue.scala 110:26]
  assign source_valid_0_reset = reset | ~io_async_safe_sink_reset_n; // @[AsyncQueue.scala 105:65]
  assign source_valid_1_io_in = source_valid_0_io_out; // @[AsyncQueue.scala 116:26]
  assign source_valid_1_clock = clock; // @[AsyncQueue.scala 111:26]
  assign source_valid_1_reset = reset | ~io_async_safe_sink_reset_n; // @[AsyncQueue.scala 106:65]
  assign sink_extend_io_in = io_async_safe_ridx_valid; // @[AsyncQueue.scala 118:23]
  assign sink_extend_clock = clock; // @[AsyncQueue.scala 112:26]
  assign sink_extend_reset = reset | ~io_async_safe_sink_reset_n; // @[AsyncQueue.scala 107:65]
  assign sink_valid_io_in = sink_extend_io_out; // @[AsyncQueue.scala 119:22]
  assign sink_valid_clock = clock; // @[AsyncQueue.scala 113:26]
  assign sink_valid_reset = reset; // @[AsyncQueue.scala 108:35]
  always @(posedge clock) begin
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      mem_0_opcode <= io_enq_bits_opcode; // @[AsyncQueue.scala 86:37]
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      mem_0_size <= io_enq_bits_size; // @[AsyncQueue.scala 86:37]
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      mem_0_source <= io_enq_bits_source; // @[AsyncQueue.scala 86:37]
    end
    if (_widx_T_1) begin // @[AsyncQueue.scala 86:24]
      mem_0_data <= io_enq_bits_data; // @[AsyncQueue.scala 86:37]
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[AsyncQueue.scala 53:23]
      widx_widx_bin <= 1'h0;
    end else if (_widx_T_2) begin
      widx_widx_bin <= 1'h0;
    end else begin
      widx_widx_bin <= widx_widx_bin + _widx_T_1;
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[AsyncQueue.scala 83:26]
      ready_reg <= 1'h0;
    end else begin
      ready_reg <= sink_ready & widx_incremented != (ridx ^ 1'h1);
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[AsyncQueue.scala 53:23]
      widx_gray <= 1'h0;
    end else if (_widx_T_2) begin
      widx_gray <= 1'h0;
    end else begin
      widx_gray <= widx_widx_bin + _widx_T_1;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  mem_0_opcode = _RAND_0[2:0];
  _RAND_1 = {1{`RANDOM}};
  mem_0_size = _RAND_1[1:0];
  _RAND_2 = {1{`RANDOM}};
  mem_0_source = _RAND_2[6:0];
  _RAND_3 = {1{`RANDOM}};
  mem_0_data = _RAND_3[31:0];
  _RAND_4 = {1{`RANDOM}};
  widx_widx_bin = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  ready_reg = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  widx_gray = _RAND_6[0:0];
`endif // RANDOMIZE_REG_INIT
  if (reset) begin
    widx_widx_bin = 1'h0;
  end
  if (reset) begin
    ready_reg = 1'h0;
  end
  if (reset) begin
    widx_gray = 1'h0;
  end
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLAsyncCrossingSink_1(
  input         clock,
  input         reset,
  input  [2:0]  auto_in_a_mem_0_opcode,
  input  [2:0]  auto_in_a_mem_0_param,
  input  [1:0]  auto_in_a_mem_0_size,
  input  [6:0]  auto_in_a_mem_0_source,
  input  [28:0] auto_in_a_mem_0_address,
  input  [3:0]  auto_in_a_mem_0_mask,
  input  [31:0] auto_in_a_mem_0_data,
  input         auto_in_a_mem_0_corrupt,
  output        auto_in_a_ridx,
  input         auto_in_a_widx,
  output        auto_in_a_safe_ridx_valid,
  input         auto_in_a_safe_widx_valid,
  input         auto_in_a_safe_source_reset_n,
  output        auto_in_a_safe_sink_reset_n,
  output [2:0]  auto_in_d_mem_0_opcode,
  output [1:0]  auto_in_d_mem_0_size,
  output [6:0]  auto_in_d_mem_0_source,
  output [31:0] auto_in_d_mem_0_data,
  input         auto_in_d_ridx,
  output        auto_in_d_widx,
  input         auto_in_d_safe_ridx_valid,
  output        auto_in_d_safe_widx_valid,
  output        auto_in_d_safe_source_reset_n,
  input         auto_in_d_safe_sink_reset_n,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [1:0]  auto_out_a_bits_size,
  output [6:0]  auto_out_a_bits_source,
  output [28:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_size,
  input  [6:0]  auto_out_d_bits_source,
  input  [31:0] auto_out_d_bits_data
);
  wire  bundleOut_0_a_sink_clock; // @[AsyncQueue.scala 207:22]
  wire  bundleOut_0_a_sink_reset; // @[AsyncQueue.scala 207:22]
  wire  bundleOut_0_a_sink_io_deq_ready; // @[AsyncQueue.scala 207:22]
  wire  bundleOut_0_a_sink_io_deq_valid; // @[AsyncQueue.scala 207:22]
  wire [2:0] bundleOut_0_a_sink_io_deq_bits_opcode; // @[AsyncQueue.scala 207:22]
  wire [2:0] bundleOut_0_a_sink_io_deq_bits_param; // @[AsyncQueue.scala 207:22]
  wire [1:0] bundleOut_0_a_sink_io_deq_bits_size; // @[AsyncQueue.scala 207:22]
  wire [6:0] bundleOut_0_a_sink_io_deq_bits_source; // @[AsyncQueue.scala 207:22]
  wire [28:0] bundleOut_0_a_sink_io_deq_bits_address; // @[AsyncQueue.scala 207:22]
  wire [3:0] bundleOut_0_a_sink_io_deq_bits_mask; // @[AsyncQueue.scala 207:22]
  wire [31:0] bundleOut_0_a_sink_io_deq_bits_data; // @[AsyncQueue.scala 207:22]
  wire  bundleOut_0_a_sink_io_deq_bits_corrupt; // @[AsyncQueue.scala 207:22]
  wire [2:0] bundleOut_0_a_sink_io_async_mem_0_opcode; // @[AsyncQueue.scala 207:22]
  wire [2:0] bundleOut_0_a_sink_io_async_mem_0_param; // @[AsyncQueue.scala 207:22]
  wire [1:0] bundleOut_0_a_sink_io_async_mem_0_size; // @[AsyncQueue.scala 207:22]
  wire [6:0] bundleOut_0_a_sink_io_async_mem_0_source; // @[AsyncQueue.scala 207:22]
  wire [28:0] bundleOut_0_a_sink_io_async_mem_0_address; // @[AsyncQueue.scala 207:22]
  wire [3:0] bundleOut_0_a_sink_io_async_mem_0_mask; // @[AsyncQueue.scala 207:22]
  wire [31:0] bundleOut_0_a_sink_io_async_mem_0_data; // @[AsyncQueue.scala 207:22]
  wire  bundleOut_0_a_sink_io_async_mem_0_corrupt; // @[AsyncQueue.scala 207:22]
  wire  bundleOut_0_a_sink_io_async_ridx; // @[AsyncQueue.scala 207:22]
  wire  bundleOut_0_a_sink_io_async_widx; // @[AsyncQueue.scala 207:22]
  wire  bundleOut_0_a_sink_io_async_safe_ridx_valid; // @[AsyncQueue.scala 207:22]
  wire  bundleOut_0_a_sink_io_async_safe_widx_valid; // @[AsyncQueue.scala 207:22]
  wire  bundleOut_0_a_sink_io_async_safe_source_reset_n; // @[AsyncQueue.scala 207:22]
  wire  bundleOut_0_a_sink_io_async_safe_sink_reset_n; // @[AsyncQueue.scala 207:22]
  wire  bundleIn_0_d_source_clock; // @[AsyncQueue.scala 216:24]
  wire  bundleIn_0_d_source_reset; // @[AsyncQueue.scala 216:24]
  wire  bundleIn_0_d_source_io_enq_ready; // @[AsyncQueue.scala 216:24]
  wire  bundleIn_0_d_source_io_enq_valid; // @[AsyncQueue.scala 216:24]
  wire [2:0] bundleIn_0_d_source_io_enq_bits_opcode; // @[AsyncQueue.scala 216:24]
  wire [1:0] bundleIn_0_d_source_io_enq_bits_size; // @[AsyncQueue.scala 216:24]
  wire [6:0] bundleIn_0_d_source_io_enq_bits_source; // @[AsyncQueue.scala 216:24]
  wire [31:0] bundleIn_0_d_source_io_enq_bits_data; // @[AsyncQueue.scala 216:24]
  wire [2:0] bundleIn_0_d_source_io_async_mem_0_opcode; // @[AsyncQueue.scala 216:24]
  wire [1:0] bundleIn_0_d_source_io_async_mem_0_size; // @[AsyncQueue.scala 216:24]
  wire [6:0] bundleIn_0_d_source_io_async_mem_0_source; // @[AsyncQueue.scala 216:24]
  wire [31:0] bundleIn_0_d_source_io_async_mem_0_data; // @[AsyncQueue.scala 216:24]
  wire  bundleIn_0_d_source_io_async_ridx; // @[AsyncQueue.scala 216:24]
  wire  bundleIn_0_d_source_io_async_widx; // @[AsyncQueue.scala 216:24]
  wire  bundleIn_0_d_source_io_async_safe_ridx_valid; // @[AsyncQueue.scala 216:24]
  wire  bundleIn_0_d_source_io_async_safe_widx_valid; // @[AsyncQueue.scala 216:24]
  wire  bundleIn_0_d_source_io_async_safe_source_reset_n; // @[AsyncQueue.scala 216:24]
  wire  bundleIn_0_d_source_io_async_safe_sink_reset_n; // @[AsyncQueue.scala 216:24]
  AsyncQueueSink_4 bundleOut_0_a_sink ( // @[AsyncQueue.scala 207:22]
    .clock(bundleOut_0_a_sink_clock),
    .reset(bundleOut_0_a_sink_reset),
    .io_deq_ready(bundleOut_0_a_sink_io_deq_ready),
    .io_deq_valid(bundleOut_0_a_sink_io_deq_valid),
    .io_deq_bits_opcode(bundleOut_0_a_sink_io_deq_bits_opcode),
    .io_deq_bits_param(bundleOut_0_a_sink_io_deq_bits_param),
    .io_deq_bits_size(bundleOut_0_a_sink_io_deq_bits_size),
    .io_deq_bits_source(bundleOut_0_a_sink_io_deq_bits_source),
    .io_deq_bits_address(bundleOut_0_a_sink_io_deq_bits_address),
    .io_deq_bits_mask(bundleOut_0_a_sink_io_deq_bits_mask),
    .io_deq_bits_data(bundleOut_0_a_sink_io_deq_bits_data),
    .io_deq_bits_corrupt(bundleOut_0_a_sink_io_deq_bits_corrupt),
    .io_async_mem_0_opcode(bundleOut_0_a_sink_io_async_mem_0_opcode),
    .io_async_mem_0_param(bundleOut_0_a_sink_io_async_mem_0_param),
    .io_async_mem_0_size(bundleOut_0_a_sink_io_async_mem_0_size),
    .io_async_mem_0_source(bundleOut_0_a_sink_io_async_mem_0_source),
    .io_async_mem_0_address(bundleOut_0_a_sink_io_async_mem_0_address),
    .io_async_mem_0_mask(bundleOut_0_a_sink_io_async_mem_0_mask),
    .io_async_mem_0_data(bundleOut_0_a_sink_io_async_mem_0_data),
    .io_async_mem_0_corrupt(bundleOut_0_a_sink_io_async_mem_0_corrupt),
    .io_async_ridx(bundleOut_0_a_sink_io_async_ridx),
    .io_async_widx(bundleOut_0_a_sink_io_async_widx),
    .io_async_safe_ridx_valid(bundleOut_0_a_sink_io_async_safe_ridx_valid),
    .io_async_safe_widx_valid(bundleOut_0_a_sink_io_async_safe_widx_valid),
    .io_async_safe_source_reset_n(bundleOut_0_a_sink_io_async_safe_source_reset_n),
    .io_async_safe_sink_reset_n(bundleOut_0_a_sink_io_async_safe_sink_reset_n)
  );
  AsyncQueueSource_4 bundleIn_0_d_source ( // @[AsyncQueue.scala 216:24]
    .clock(bundleIn_0_d_source_clock),
    .reset(bundleIn_0_d_source_reset),
    .io_enq_ready(bundleIn_0_d_source_io_enq_ready),
    .io_enq_valid(bundleIn_0_d_source_io_enq_valid),
    .io_enq_bits_opcode(bundleIn_0_d_source_io_enq_bits_opcode),
    .io_enq_bits_size(bundleIn_0_d_source_io_enq_bits_size),
    .io_enq_bits_source(bundleIn_0_d_source_io_enq_bits_source),
    .io_enq_bits_data(bundleIn_0_d_source_io_enq_bits_data),
    .io_async_mem_0_opcode(bundleIn_0_d_source_io_async_mem_0_opcode),
    .io_async_mem_0_size(bundleIn_0_d_source_io_async_mem_0_size),
    .io_async_mem_0_source(bundleIn_0_d_source_io_async_mem_0_source),
    .io_async_mem_0_data(bundleIn_0_d_source_io_async_mem_0_data),
    .io_async_ridx(bundleIn_0_d_source_io_async_ridx),
    .io_async_widx(bundleIn_0_d_source_io_async_widx),
    .io_async_safe_ridx_valid(bundleIn_0_d_source_io_async_safe_ridx_valid),
    .io_async_safe_widx_valid(bundleIn_0_d_source_io_async_safe_widx_valid),
    .io_async_safe_source_reset_n(bundleIn_0_d_source_io_async_safe_source_reset_n),
    .io_async_safe_sink_reset_n(bundleIn_0_d_source_io_async_safe_sink_reset_n)
  );
  assign auto_in_a_ridx = bundleOut_0_a_sink_io_async_ridx; // @[Nodes.scala 1210:84 AsyncQueue.scala 208:19]
  assign auto_in_a_safe_ridx_valid = bundleOut_0_a_sink_io_async_safe_ridx_valid; // @[Nodes.scala 1210:84 AsyncQueue.scala 208:19]
  assign auto_in_a_safe_sink_reset_n = bundleOut_0_a_sink_io_async_safe_sink_reset_n; // @[Nodes.scala 1210:84 AsyncQueue.scala 208:19]
  assign auto_in_d_mem_0_opcode = bundleIn_0_d_source_io_async_mem_0_opcode; // @[Nodes.scala 1210:84 AsyncCrossing.scala 58:12]
  assign auto_in_d_mem_0_size = bundleIn_0_d_source_io_async_mem_0_size; // @[Nodes.scala 1210:84 AsyncCrossing.scala 58:12]
  assign auto_in_d_mem_0_source = bundleIn_0_d_source_io_async_mem_0_source; // @[Nodes.scala 1210:84 AsyncCrossing.scala 58:12]
  assign auto_in_d_mem_0_data = bundleIn_0_d_source_io_async_mem_0_data; // @[Nodes.scala 1210:84 AsyncCrossing.scala 58:12]
  assign auto_in_d_widx = bundleIn_0_d_source_io_async_widx; // @[Nodes.scala 1210:84 AsyncCrossing.scala 58:12]
  assign auto_in_d_safe_widx_valid = bundleIn_0_d_source_io_async_safe_widx_valid; // @[Nodes.scala 1210:84 AsyncCrossing.scala 58:12]
  assign auto_in_d_safe_source_reset_n = bundleIn_0_d_source_io_async_safe_source_reset_n; // @[Nodes.scala 1210:84 AsyncCrossing.scala 58:12]
  assign auto_out_a_valid = bundleOut_0_a_sink_io_deq_valid; // @[Nodes.scala 1207:84 AsyncCrossing.scala 57:13]
  assign auto_out_a_bits_opcode = bundleOut_0_a_sink_io_deq_bits_opcode; // @[Nodes.scala 1207:84 AsyncCrossing.scala 57:13]
  assign auto_out_a_bits_param = bundleOut_0_a_sink_io_deq_bits_param; // @[Nodes.scala 1207:84 AsyncCrossing.scala 57:13]
  assign auto_out_a_bits_size = bundleOut_0_a_sink_io_deq_bits_size; // @[Nodes.scala 1207:84 AsyncCrossing.scala 57:13]
  assign auto_out_a_bits_source = bundleOut_0_a_sink_io_deq_bits_source; // @[Nodes.scala 1207:84 AsyncCrossing.scala 57:13]
  assign auto_out_a_bits_address = bundleOut_0_a_sink_io_deq_bits_address; // @[Nodes.scala 1207:84 AsyncCrossing.scala 57:13]
  assign auto_out_a_bits_mask = bundleOut_0_a_sink_io_deq_bits_mask; // @[Nodes.scala 1207:84 AsyncCrossing.scala 57:13]
  assign auto_out_a_bits_data = bundleOut_0_a_sink_io_deq_bits_data; // @[Nodes.scala 1207:84 AsyncCrossing.scala 57:13]
  assign auto_out_a_bits_corrupt = bundleOut_0_a_sink_io_deq_bits_corrupt; // @[Nodes.scala 1207:84 AsyncCrossing.scala 57:13]
  assign auto_out_d_ready = bundleIn_0_d_source_io_enq_ready; // @[Nodes.scala 1207:84 AsyncQueue.scala 217:19]
  assign bundleOut_0_a_sink_clock = clock;
  assign bundleOut_0_a_sink_reset = reset;
  assign bundleOut_0_a_sink_io_deq_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleOut_0_a_sink_io_async_mem_0_opcode = auto_in_a_mem_0_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_sink_io_async_mem_0_param = auto_in_a_mem_0_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_sink_io_async_mem_0_size = auto_in_a_mem_0_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_sink_io_async_mem_0_source = auto_in_a_mem_0_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_sink_io_async_mem_0_address = auto_in_a_mem_0_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_sink_io_async_mem_0_mask = auto_in_a_mem_0_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_sink_io_async_mem_0_data = auto_in_a_mem_0_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_sink_io_async_mem_0_corrupt = auto_in_a_mem_0_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_sink_io_async_widx = auto_in_a_widx; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_sink_io_async_safe_widx_valid = auto_in_a_safe_widx_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleOut_0_a_sink_io_async_safe_source_reset_n = auto_in_a_safe_source_reset_n; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleIn_0_d_source_clock = clock;
  assign bundleIn_0_d_source_reset = reset;
  assign bundleIn_0_d_source_io_enq_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_source_io_enq_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_source_io_enq_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_source_io_enq_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_source_io_enq_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign bundleIn_0_d_source_io_async_ridx = auto_in_d_ridx; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleIn_0_d_source_io_async_safe_ridx_valid = auto_in_d_safe_ridx_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bundleIn_0_d_source_io_async_safe_sink_reset_n = auto_in_d_safe_sink_reset_n; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module IntSyncCrossingSource_8(
  input   auto_in_0,
  input   auto_in_1,
  output  auto_out_sync_0,
  output  auto_out_sync_1
);
  assign auto_out_sync_0 = auto_in_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_sync_1 = auto_in_1; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module ResetCatchAndSync_d3(
  input   clock,
  input   reset,
  output  io_sync_reset
);
  wire  io_sync_reset_chain_clock; // @[ShiftReg.scala 45:23]
  wire  io_sync_reset_chain_reset; // @[ShiftReg.scala 45:23]
  wire  io_sync_reset_chain_io_d; // @[ShiftReg.scala 45:23]
  wire  io_sync_reset_chain_io_q; // @[ShiftReg.scala 45:23]
  wire  _io_sync_reset_WIRE = io_sync_reset_chain_io_q; // @[ShiftReg.scala 48:{24,24}]
  AsyncResetSynchronizerShiftReg_w1_d3_i0 io_sync_reset_chain ( // @[ShiftReg.scala 45:23]
    .clock(io_sync_reset_chain_clock),
    .reset(io_sync_reset_chain_reset),
    .io_d(io_sync_reset_chain_io_d),
    .io_q(io_sync_reset_chain_io_q)
  );
  assign io_sync_reset = ~_io_sync_reset_WIRE; // @[ResetCatchAndSync.scala 29:7]
  assign io_sync_reset_chain_clock = clock;
  assign io_sync_reset_chain_reset = reset; // @[ResetCatchAndSync.scala 26:27]
  assign io_sync_reset_chain_io_d = 1'h1; // @[ShiftReg.scala 47:16]
endmodule
module ResetCatchAndSync_d3_1(
  input   clock,
  input   reset,
  output  io_sync_reset
);
  wire  io_sync_reset_chain_clock; // @[ShiftReg.scala 45:23]
  wire  io_sync_reset_chain_reset; // @[ShiftReg.scala 45:23]
  wire  io_sync_reset_chain_io_d; // @[ShiftReg.scala 45:23]
  wire  io_sync_reset_chain_io_q; // @[ShiftReg.scala 45:23]
  wire  _io_sync_reset_WIRE = io_sync_reset_chain_io_q; // @[ShiftReg.scala 48:{24,24}]
  AsyncResetSynchronizerShiftReg_w1_d3_i0 io_sync_reset_chain ( // @[ShiftReg.scala 45:23]
    .clock(io_sync_reset_chain_clock),
    .reset(io_sync_reset_chain_reset),
    .io_d(io_sync_reset_chain_io_d),
    .io_q(io_sync_reset_chain_io_q)
  );
  assign io_sync_reset = ~_io_sync_reset_WIRE; // @[ResetCatchAndSync.scala 29:7]
  assign io_sync_reset_chain_clock = clock;
  assign io_sync_reset_chain_reset = reset; // @[ResetCatchAndSync.scala 26:27]
  assign io_sync_reset_chain_io_d = 1'h1; // @[ShiftReg.scala 47:16]
endmodule
module MockAONWrapper(
  output        auto_intsource_out_sync_0,
  output        auto_intsource_out_sync_1,
  input  [2:0]  auto_isolation_in_a_mem_0_opcode,
  input  [2:0]  auto_isolation_in_a_mem_0_param,
  input  [1:0]  auto_isolation_in_a_mem_0_size,
  input  [6:0]  auto_isolation_in_a_mem_0_source,
  input  [28:0] auto_isolation_in_a_mem_0_address,
  input  [3:0]  auto_isolation_in_a_mem_0_mask,
  input  [31:0] auto_isolation_in_a_mem_0_data,
  input         auto_isolation_in_a_mem_0_corrupt,
  output        auto_isolation_in_a_ridx,
  input         auto_isolation_in_a_widx,
  output        auto_isolation_in_a_safe_ridx_valid,
  input         auto_isolation_in_a_safe_widx_valid,
  input         auto_isolation_in_a_safe_source_reset_n,
  output        auto_isolation_in_a_safe_sink_reset_n,
  output [2:0]  auto_isolation_in_d_mem_0_opcode,
  output [1:0]  auto_isolation_in_d_mem_0_param,
  output [1:0]  auto_isolation_in_d_mem_0_size,
  output [6:0]  auto_isolation_in_d_mem_0_source,
  output        auto_isolation_in_d_mem_0_sink,
  output        auto_isolation_in_d_mem_0_denied,
  output [31:0] auto_isolation_in_d_mem_0_data,
  output        auto_isolation_in_d_mem_0_corrupt,
  input         auto_isolation_in_d_ridx,
  output        auto_isolation_in_d_widx,
  input         auto_isolation_in_d_safe_ridx_valid,
  output        auto_isolation_in_d_safe_widx_valid,
  output        auto_isolation_in_d_safe_source_reset_n,
  input         auto_isolation_in_d_safe_sink_reset_n,
  input         io_pins_erst_n_i_ival,
  input         io_pins_lfextclk_i_ival,
  output        io_rsts_corerst,
  output        io_rtc,
  input         io_ndreset
);
  wire  aon_clock; // @[MockAONWrapper.scala 35:23]
  wire  aon_reset; // @[MockAONWrapper.scala 35:23]
  wire  aon_auto_int_out_0; // @[MockAONWrapper.scala 35:23]
  wire  aon_auto_int_out_1; // @[MockAONWrapper.scala 35:23]
  wire  aon_auto_in_a_ready; // @[MockAONWrapper.scala 35:23]
  wire  aon_auto_in_a_valid; // @[MockAONWrapper.scala 35:23]
  wire [2:0] aon_auto_in_a_bits_opcode; // @[MockAONWrapper.scala 35:23]
  wire [2:0] aon_auto_in_a_bits_param; // @[MockAONWrapper.scala 35:23]
  wire [1:0] aon_auto_in_a_bits_size; // @[MockAONWrapper.scala 35:23]
  wire [6:0] aon_auto_in_a_bits_source; // @[MockAONWrapper.scala 35:23]
  wire [28:0] aon_auto_in_a_bits_address; // @[MockAONWrapper.scala 35:23]
  wire [3:0] aon_auto_in_a_bits_mask; // @[MockAONWrapper.scala 35:23]
  wire [31:0] aon_auto_in_a_bits_data; // @[MockAONWrapper.scala 35:23]
  wire  aon_auto_in_a_bits_corrupt; // @[MockAONWrapper.scala 35:23]
  wire  aon_auto_in_d_ready; // @[MockAONWrapper.scala 35:23]
  wire  aon_auto_in_d_valid; // @[MockAONWrapper.scala 35:23]
  wire [2:0] aon_auto_in_d_bits_opcode; // @[MockAONWrapper.scala 35:23]
  wire [1:0] aon_auto_in_d_bits_size; // @[MockAONWrapper.scala 35:23]
  wire [6:0] aon_auto_in_d_bits_source; // @[MockAONWrapper.scala 35:23]
  wire [31:0] aon_auto_in_d_bits_data; // @[MockAONWrapper.scala 35:23]
  wire  aon_io_moff_corerst; // @[MockAONWrapper.scala 35:23]
  wire  aon_io_wdog_rst; // @[MockAONWrapper.scala 35:23]
  wire  aon_io_lfclk; // @[MockAONWrapper.scala 35:23]
  wire  aon_io_lfextclk; // @[MockAONWrapper.scala 35:23]
  wire  aon_io_resetCauses_wdogrst; // @[MockAONWrapper.scala 35:23]
  wire  aon_io_resetCauses_erst; // @[MockAONWrapper.scala 35:23]
  wire [2:0] isolation_auto_in_a_mem_0_opcode; // @[MockAONWrapper.scala 45:29]
  wire [2:0] isolation_auto_in_a_mem_0_param; // @[MockAONWrapper.scala 45:29]
  wire [1:0] isolation_auto_in_a_mem_0_size; // @[MockAONWrapper.scala 45:29]
  wire [6:0] isolation_auto_in_a_mem_0_source; // @[MockAONWrapper.scala 45:29]
  wire [28:0] isolation_auto_in_a_mem_0_address; // @[MockAONWrapper.scala 45:29]
  wire [3:0] isolation_auto_in_a_mem_0_mask; // @[MockAONWrapper.scala 45:29]
  wire [31:0] isolation_auto_in_a_mem_0_data; // @[MockAONWrapper.scala 45:29]
  wire  isolation_auto_in_a_mem_0_corrupt; // @[MockAONWrapper.scala 45:29]
  wire  isolation_auto_in_a_ridx; // @[MockAONWrapper.scala 45:29]
  wire  isolation_auto_in_a_widx; // @[MockAONWrapper.scala 45:29]
  wire  isolation_auto_in_a_safe_ridx_valid; // @[MockAONWrapper.scala 45:29]
  wire  isolation_auto_in_a_safe_widx_valid; // @[MockAONWrapper.scala 45:29]
  wire  isolation_auto_in_a_safe_source_reset_n; // @[MockAONWrapper.scala 45:29]
  wire  isolation_auto_in_a_safe_sink_reset_n; // @[MockAONWrapper.scala 45:29]
  wire [2:0] isolation_auto_in_d_mem_0_opcode; // @[MockAONWrapper.scala 45:29]
  wire [1:0] isolation_auto_in_d_mem_0_param; // @[MockAONWrapper.scala 45:29]
  wire [1:0] isolation_auto_in_d_mem_0_size; // @[MockAONWrapper.scala 45:29]
  wire [6:0] isolation_auto_in_d_mem_0_source; // @[MockAONWrapper.scala 45:29]
  wire  isolation_auto_in_d_mem_0_sink; // @[MockAONWrapper.scala 45:29]
  wire  isolation_auto_in_d_mem_0_denied; // @[MockAONWrapper.scala 45:29]
  wire [31:0] isolation_auto_in_d_mem_0_data; // @[MockAONWrapper.scala 45:29]
  wire  isolation_auto_in_d_mem_0_corrupt; // @[MockAONWrapper.scala 45:29]
  wire  isolation_auto_in_d_ridx; // @[MockAONWrapper.scala 45:29]
  wire  isolation_auto_in_d_widx; // @[MockAONWrapper.scala 45:29]
  wire  isolation_auto_in_d_safe_ridx_valid; // @[MockAONWrapper.scala 45:29]
  wire  isolation_auto_in_d_safe_widx_valid; // @[MockAONWrapper.scala 45:29]
  wire  isolation_auto_in_d_safe_source_reset_n; // @[MockAONWrapper.scala 45:29]
  wire  isolation_auto_in_d_safe_sink_reset_n; // @[MockAONWrapper.scala 45:29]
  wire [2:0] isolation_auto_out_a_mem_0_opcode; // @[MockAONWrapper.scala 45:29]
  wire [2:0] isolation_auto_out_a_mem_0_param; // @[MockAONWrapper.scala 45:29]
  wire [1:0] isolation_auto_out_a_mem_0_size; // @[MockAONWrapper.scala 45:29]
  wire [6:0] isolation_auto_out_a_mem_0_source; // @[MockAONWrapper.scala 45:29]
  wire [28:0] isolation_auto_out_a_mem_0_address; // @[MockAONWrapper.scala 45:29]
  wire [3:0] isolation_auto_out_a_mem_0_mask; // @[MockAONWrapper.scala 45:29]
  wire [31:0] isolation_auto_out_a_mem_0_data; // @[MockAONWrapper.scala 45:29]
  wire  isolation_auto_out_a_mem_0_corrupt; // @[MockAONWrapper.scala 45:29]
  wire  isolation_auto_out_a_ridx; // @[MockAONWrapper.scala 45:29]
  wire  isolation_auto_out_a_widx; // @[MockAONWrapper.scala 45:29]
  wire  isolation_auto_out_a_safe_ridx_valid; // @[MockAONWrapper.scala 45:29]
  wire  isolation_auto_out_a_safe_widx_valid; // @[MockAONWrapper.scala 45:29]
  wire  isolation_auto_out_a_safe_source_reset_n; // @[MockAONWrapper.scala 45:29]
  wire  isolation_auto_out_a_safe_sink_reset_n; // @[MockAONWrapper.scala 45:29]
  wire [2:0] isolation_auto_out_d_mem_0_opcode; // @[MockAONWrapper.scala 45:29]
  wire [1:0] isolation_auto_out_d_mem_0_size; // @[MockAONWrapper.scala 45:29]
  wire [6:0] isolation_auto_out_d_mem_0_source; // @[MockAONWrapper.scala 45:29]
  wire [31:0] isolation_auto_out_d_mem_0_data; // @[MockAONWrapper.scala 45:29]
  wire  isolation_auto_out_d_ridx; // @[MockAONWrapper.scala 45:29]
  wire  isolation_auto_out_d_widx; // @[MockAONWrapper.scala 45:29]
  wire  isolation_auto_out_d_safe_ridx_valid; // @[MockAONWrapper.scala 45:29]
  wire  isolation_auto_out_d_safe_widx_valid; // @[MockAONWrapper.scala 45:29]
  wire  isolation_auto_out_d_safe_source_reset_n; // @[MockAONWrapper.scala 45:29]
  wire  isolation_auto_out_d_safe_sink_reset_n; // @[MockAONWrapper.scala 45:29]
  wire  isolation_io_iso_out; // @[MockAONWrapper.scala 45:29]
  wire  crossing_clock; // @[MockAONWrapper.scala 46:28]
  wire  crossing_reset; // @[MockAONWrapper.scala 46:28]
  wire [2:0] crossing_auto_in_a_mem_0_opcode; // @[MockAONWrapper.scala 46:28]
  wire [2:0] crossing_auto_in_a_mem_0_param; // @[MockAONWrapper.scala 46:28]
  wire [1:0] crossing_auto_in_a_mem_0_size; // @[MockAONWrapper.scala 46:28]
  wire [6:0] crossing_auto_in_a_mem_0_source; // @[MockAONWrapper.scala 46:28]
  wire [28:0] crossing_auto_in_a_mem_0_address; // @[MockAONWrapper.scala 46:28]
  wire [3:0] crossing_auto_in_a_mem_0_mask; // @[MockAONWrapper.scala 46:28]
  wire [31:0] crossing_auto_in_a_mem_0_data; // @[MockAONWrapper.scala 46:28]
  wire  crossing_auto_in_a_mem_0_corrupt; // @[MockAONWrapper.scala 46:28]
  wire  crossing_auto_in_a_ridx; // @[MockAONWrapper.scala 46:28]
  wire  crossing_auto_in_a_widx; // @[MockAONWrapper.scala 46:28]
  wire  crossing_auto_in_a_safe_ridx_valid; // @[MockAONWrapper.scala 46:28]
  wire  crossing_auto_in_a_safe_widx_valid; // @[MockAONWrapper.scala 46:28]
  wire  crossing_auto_in_a_safe_source_reset_n; // @[MockAONWrapper.scala 46:28]
  wire  crossing_auto_in_a_safe_sink_reset_n; // @[MockAONWrapper.scala 46:28]
  wire [2:0] crossing_auto_in_d_mem_0_opcode; // @[MockAONWrapper.scala 46:28]
  wire [1:0] crossing_auto_in_d_mem_0_size; // @[MockAONWrapper.scala 46:28]
  wire [6:0] crossing_auto_in_d_mem_0_source; // @[MockAONWrapper.scala 46:28]
  wire [31:0] crossing_auto_in_d_mem_0_data; // @[MockAONWrapper.scala 46:28]
  wire  crossing_auto_in_d_ridx; // @[MockAONWrapper.scala 46:28]
  wire  crossing_auto_in_d_widx; // @[MockAONWrapper.scala 46:28]
  wire  crossing_auto_in_d_safe_ridx_valid; // @[MockAONWrapper.scala 46:28]
  wire  crossing_auto_in_d_safe_widx_valid; // @[MockAONWrapper.scala 46:28]
  wire  crossing_auto_in_d_safe_source_reset_n; // @[MockAONWrapper.scala 46:28]
  wire  crossing_auto_in_d_safe_sink_reset_n; // @[MockAONWrapper.scala 46:28]
  wire  crossing_auto_out_a_ready; // @[MockAONWrapper.scala 46:28]
  wire  crossing_auto_out_a_valid; // @[MockAONWrapper.scala 46:28]
  wire [2:0] crossing_auto_out_a_bits_opcode; // @[MockAONWrapper.scala 46:28]
  wire [2:0] crossing_auto_out_a_bits_param; // @[MockAONWrapper.scala 46:28]
  wire [1:0] crossing_auto_out_a_bits_size; // @[MockAONWrapper.scala 46:28]
  wire [6:0] crossing_auto_out_a_bits_source; // @[MockAONWrapper.scala 46:28]
  wire [28:0] crossing_auto_out_a_bits_address; // @[MockAONWrapper.scala 46:28]
  wire [3:0] crossing_auto_out_a_bits_mask; // @[MockAONWrapper.scala 46:28]
  wire [31:0] crossing_auto_out_a_bits_data; // @[MockAONWrapper.scala 46:28]
  wire  crossing_auto_out_a_bits_corrupt; // @[MockAONWrapper.scala 46:28]
  wire  crossing_auto_out_d_ready; // @[MockAONWrapper.scala 46:28]
  wire  crossing_auto_out_d_valid; // @[MockAONWrapper.scala 46:28]
  wire [2:0] crossing_auto_out_d_bits_opcode; // @[MockAONWrapper.scala 46:28]
  wire [1:0] crossing_auto_out_d_bits_size; // @[MockAONWrapper.scala 46:28]
  wire [6:0] crossing_auto_out_d_bits_source; // @[MockAONWrapper.scala 46:28]
  wire [31:0] crossing_auto_out_d_bits_data; // @[MockAONWrapper.scala 46:28]
  wire  intsource_auto_in_0; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_1; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_0; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_1; // @[Crossing.scala 26:31]
  wire  aonrst_catch_clock; // @[MockAONWrapper.scala 99:31]
  wire  aonrst_catch_reset; // @[MockAONWrapper.scala 99:31]
  wire  aonrst_catch_io_sync_reset; // @[MockAONWrapper.scala 99:31]
  wire  crossing_slave_reset_catcher_clock; // @[ResetCatchAndSync.scala 39:28]
  wire  crossing_slave_reset_catcher_reset; // @[ResetCatchAndSync.scala 39:28]
  wire  crossing_slave_reset_catcher_io_sync_reset; // @[ResetCatchAndSync.scala 39:28]
  wire  erst = ~io_pins_erst_n_i_ival; // @[MockAONWrapper.scala 67:16]
  wire  _crossing_slave_reset_T = aon_reset; // @[compatibility.scala 290:56]
  TLMockAON aon ( // @[MockAONWrapper.scala 35:23]
    .clock(aon_clock),
    .reset(aon_reset),
    .auto_int_out_0(aon_auto_int_out_0),
    .auto_int_out_1(aon_auto_int_out_1),
    .auto_in_a_ready(aon_auto_in_a_ready),
    .auto_in_a_valid(aon_auto_in_a_valid),
    .auto_in_a_bits_opcode(aon_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(aon_auto_in_a_bits_param),
    .auto_in_a_bits_size(aon_auto_in_a_bits_size),
    .auto_in_a_bits_source(aon_auto_in_a_bits_source),
    .auto_in_a_bits_address(aon_auto_in_a_bits_address),
    .auto_in_a_bits_mask(aon_auto_in_a_bits_mask),
    .auto_in_a_bits_data(aon_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(aon_auto_in_a_bits_corrupt),
    .auto_in_d_ready(aon_auto_in_d_ready),
    .auto_in_d_valid(aon_auto_in_d_valid),
    .auto_in_d_bits_opcode(aon_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(aon_auto_in_d_bits_size),
    .auto_in_d_bits_source(aon_auto_in_d_bits_source),
    .auto_in_d_bits_data(aon_auto_in_d_bits_data),
    .io_moff_corerst(aon_io_moff_corerst),
    .io_wdog_rst(aon_io_wdog_rst),
    .io_lfclk(aon_io_lfclk),
    .io_lfextclk(aon_io_lfextclk),
    .io_resetCauses_wdogrst(aon_io_resetCauses_wdogrst),
    .io_resetCauses_erst(aon_io_resetCauses_erst)
  );
  TLIsolation isolation ( // @[MockAONWrapper.scala 45:29]
    .auto_in_a_mem_0_opcode(isolation_auto_in_a_mem_0_opcode),
    .auto_in_a_mem_0_param(isolation_auto_in_a_mem_0_param),
    .auto_in_a_mem_0_size(isolation_auto_in_a_mem_0_size),
    .auto_in_a_mem_0_source(isolation_auto_in_a_mem_0_source),
    .auto_in_a_mem_0_address(isolation_auto_in_a_mem_0_address),
    .auto_in_a_mem_0_mask(isolation_auto_in_a_mem_0_mask),
    .auto_in_a_mem_0_data(isolation_auto_in_a_mem_0_data),
    .auto_in_a_mem_0_corrupt(isolation_auto_in_a_mem_0_corrupt),
    .auto_in_a_ridx(isolation_auto_in_a_ridx),
    .auto_in_a_widx(isolation_auto_in_a_widx),
    .auto_in_a_safe_ridx_valid(isolation_auto_in_a_safe_ridx_valid),
    .auto_in_a_safe_widx_valid(isolation_auto_in_a_safe_widx_valid),
    .auto_in_a_safe_source_reset_n(isolation_auto_in_a_safe_source_reset_n),
    .auto_in_a_safe_sink_reset_n(isolation_auto_in_a_safe_sink_reset_n),
    .auto_in_d_mem_0_opcode(isolation_auto_in_d_mem_0_opcode),
    .auto_in_d_mem_0_param(isolation_auto_in_d_mem_0_param),
    .auto_in_d_mem_0_size(isolation_auto_in_d_mem_0_size),
    .auto_in_d_mem_0_source(isolation_auto_in_d_mem_0_source),
    .auto_in_d_mem_0_sink(isolation_auto_in_d_mem_0_sink),
    .auto_in_d_mem_0_denied(isolation_auto_in_d_mem_0_denied),
    .auto_in_d_mem_0_data(isolation_auto_in_d_mem_0_data),
    .auto_in_d_mem_0_corrupt(isolation_auto_in_d_mem_0_corrupt),
    .auto_in_d_ridx(isolation_auto_in_d_ridx),
    .auto_in_d_widx(isolation_auto_in_d_widx),
    .auto_in_d_safe_ridx_valid(isolation_auto_in_d_safe_ridx_valid),
    .auto_in_d_safe_widx_valid(isolation_auto_in_d_safe_widx_valid),
    .auto_in_d_safe_source_reset_n(isolation_auto_in_d_safe_source_reset_n),
    .auto_in_d_safe_sink_reset_n(isolation_auto_in_d_safe_sink_reset_n),
    .auto_out_a_mem_0_opcode(isolation_auto_out_a_mem_0_opcode),
    .auto_out_a_mem_0_param(isolation_auto_out_a_mem_0_param),
    .auto_out_a_mem_0_size(isolation_auto_out_a_mem_0_size),
    .auto_out_a_mem_0_source(isolation_auto_out_a_mem_0_source),
    .auto_out_a_mem_0_address(isolation_auto_out_a_mem_0_address),
    .auto_out_a_mem_0_mask(isolation_auto_out_a_mem_0_mask),
    .auto_out_a_mem_0_data(isolation_auto_out_a_mem_0_data),
    .auto_out_a_mem_0_corrupt(isolation_auto_out_a_mem_0_corrupt),
    .auto_out_a_ridx(isolation_auto_out_a_ridx),
    .auto_out_a_widx(isolation_auto_out_a_widx),
    .auto_out_a_safe_ridx_valid(isolation_auto_out_a_safe_ridx_valid),
    .auto_out_a_safe_widx_valid(isolation_auto_out_a_safe_widx_valid),
    .auto_out_a_safe_source_reset_n(isolation_auto_out_a_safe_source_reset_n),
    .auto_out_a_safe_sink_reset_n(isolation_auto_out_a_safe_sink_reset_n),
    .auto_out_d_mem_0_opcode(isolation_auto_out_d_mem_0_opcode),
    .auto_out_d_mem_0_size(isolation_auto_out_d_mem_0_size),
    .auto_out_d_mem_0_source(isolation_auto_out_d_mem_0_source),
    .auto_out_d_mem_0_data(isolation_auto_out_d_mem_0_data),
    .auto_out_d_ridx(isolation_auto_out_d_ridx),
    .auto_out_d_widx(isolation_auto_out_d_widx),
    .auto_out_d_safe_ridx_valid(isolation_auto_out_d_safe_ridx_valid),
    .auto_out_d_safe_widx_valid(isolation_auto_out_d_safe_widx_valid),
    .auto_out_d_safe_source_reset_n(isolation_auto_out_d_safe_source_reset_n),
    .auto_out_d_safe_sink_reset_n(isolation_auto_out_d_safe_sink_reset_n),
    .io_iso_out(isolation_io_iso_out)
  );
  TLAsyncCrossingSink_1 crossing ( // @[MockAONWrapper.scala 46:28]
    .clock(crossing_clock),
    .reset(crossing_reset),
    .auto_in_a_mem_0_opcode(crossing_auto_in_a_mem_0_opcode),
    .auto_in_a_mem_0_param(crossing_auto_in_a_mem_0_param),
    .auto_in_a_mem_0_size(crossing_auto_in_a_mem_0_size),
    .auto_in_a_mem_0_source(crossing_auto_in_a_mem_0_source),
    .auto_in_a_mem_0_address(crossing_auto_in_a_mem_0_address),
    .auto_in_a_mem_0_mask(crossing_auto_in_a_mem_0_mask),
    .auto_in_a_mem_0_data(crossing_auto_in_a_mem_0_data),
    .auto_in_a_mem_0_corrupt(crossing_auto_in_a_mem_0_corrupt),
    .auto_in_a_ridx(crossing_auto_in_a_ridx),
    .auto_in_a_widx(crossing_auto_in_a_widx),
    .auto_in_a_safe_ridx_valid(crossing_auto_in_a_safe_ridx_valid),
    .auto_in_a_safe_widx_valid(crossing_auto_in_a_safe_widx_valid),
    .auto_in_a_safe_source_reset_n(crossing_auto_in_a_safe_source_reset_n),
    .auto_in_a_safe_sink_reset_n(crossing_auto_in_a_safe_sink_reset_n),
    .auto_in_d_mem_0_opcode(crossing_auto_in_d_mem_0_opcode),
    .auto_in_d_mem_0_size(crossing_auto_in_d_mem_0_size),
    .auto_in_d_mem_0_source(crossing_auto_in_d_mem_0_source),
    .auto_in_d_mem_0_data(crossing_auto_in_d_mem_0_data),
    .auto_in_d_ridx(crossing_auto_in_d_ridx),
    .auto_in_d_widx(crossing_auto_in_d_widx),
    .auto_in_d_safe_ridx_valid(crossing_auto_in_d_safe_ridx_valid),
    .auto_in_d_safe_widx_valid(crossing_auto_in_d_safe_widx_valid),
    .auto_in_d_safe_source_reset_n(crossing_auto_in_d_safe_source_reset_n),
    .auto_in_d_safe_sink_reset_n(crossing_auto_in_d_safe_sink_reset_n),
    .auto_out_a_ready(crossing_auto_out_a_ready),
    .auto_out_a_valid(crossing_auto_out_a_valid),
    .auto_out_a_bits_opcode(crossing_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(crossing_auto_out_a_bits_param),
    .auto_out_a_bits_size(crossing_auto_out_a_bits_size),
    .auto_out_a_bits_source(crossing_auto_out_a_bits_source),
    .auto_out_a_bits_address(crossing_auto_out_a_bits_address),
    .auto_out_a_bits_mask(crossing_auto_out_a_bits_mask),
    .auto_out_a_bits_data(crossing_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(crossing_auto_out_a_bits_corrupt),
    .auto_out_d_ready(crossing_auto_out_d_ready),
    .auto_out_d_valid(crossing_auto_out_d_valid),
    .auto_out_d_bits_opcode(crossing_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(crossing_auto_out_d_bits_size),
    .auto_out_d_bits_source(crossing_auto_out_d_bits_source),
    .auto_out_d_bits_data(crossing_auto_out_d_bits_data)
  );
  IntSyncCrossingSource_8 intsource ( // @[Crossing.scala 26:31]
    .auto_in_0(intsource_auto_in_0),
    .auto_in_1(intsource_auto_in_1),
    .auto_out_sync_0(intsource_auto_out_sync_0),
    .auto_out_sync_1(intsource_auto_out_sync_1)
  );
  ResetCatchAndSync_d3 aonrst_catch ( // @[MockAONWrapper.scala 99:31]
    .clock(aonrst_catch_clock),
    .reset(aonrst_catch_reset),
    .io_sync_reset(aonrst_catch_io_sync_reset)
  );
  ResetCatchAndSync_d3_1 crossing_slave_reset_catcher ( // @[ResetCatchAndSync.scala 39:28]
    .clock(crossing_slave_reset_catcher_clock),
    .reset(crossing_slave_reset_catcher_reset),
    .io_sync_reset(crossing_slave_reset_catcher_io_sync_reset)
  );
  assign auto_intsource_out_sync_0 = intsource_auto_out_sync_0; // @[LazyModule.scala 311:12]
  assign auto_intsource_out_sync_1 = intsource_auto_out_sync_1; // @[LazyModule.scala 311:12]
  assign auto_isolation_in_a_ridx = isolation_auto_in_a_ridx; // @[LazyModule.scala 309:16]
  assign auto_isolation_in_a_safe_ridx_valid = isolation_auto_in_a_safe_ridx_valid; // @[LazyModule.scala 309:16]
  assign auto_isolation_in_a_safe_sink_reset_n = isolation_auto_in_a_safe_sink_reset_n; // @[LazyModule.scala 309:16]
  assign auto_isolation_in_d_mem_0_opcode = isolation_auto_in_d_mem_0_opcode; // @[LazyModule.scala 309:16]
  assign auto_isolation_in_d_mem_0_param = isolation_auto_in_d_mem_0_param; // @[LazyModule.scala 309:16]
  assign auto_isolation_in_d_mem_0_size = isolation_auto_in_d_mem_0_size; // @[LazyModule.scala 309:16]
  assign auto_isolation_in_d_mem_0_source = isolation_auto_in_d_mem_0_source; // @[LazyModule.scala 309:16]
  assign auto_isolation_in_d_mem_0_sink = isolation_auto_in_d_mem_0_sink; // @[LazyModule.scala 309:16]
  assign auto_isolation_in_d_mem_0_denied = isolation_auto_in_d_mem_0_denied; // @[LazyModule.scala 309:16]
  assign auto_isolation_in_d_mem_0_data = isolation_auto_in_d_mem_0_data; // @[LazyModule.scala 309:16]
  assign auto_isolation_in_d_mem_0_corrupt = isolation_auto_in_d_mem_0_corrupt; // @[LazyModule.scala 309:16]
  assign auto_isolation_in_d_widx = isolation_auto_in_d_widx; // @[LazyModule.scala 309:16]
  assign auto_isolation_in_d_safe_widx_valid = isolation_auto_in_d_safe_widx_valid; // @[LazyModule.scala 309:16]
  assign auto_isolation_in_d_safe_source_reset_n = isolation_auto_in_d_safe_source_reset_n; // @[LazyModule.scala 309:16]
  assign io_rsts_corerst = aon_io_moff_corerst; // @[MockAONWrapper.scala 81:22]
  assign io_rtc = aon_io_lfclk; // @[MockAONWrapper.scala 143:12]
  assign aon_clock = aon_io_lfclk; // @[MockAONWrapper.scala 104:22]
  assign aon_reset = aonrst_catch_io_sync_reset; // @[MockAONWrapper.scala 102:22]
  assign aon_auto_in_a_valid = crossing_auto_out_a_valid; // @[LazyModule.scala 296:16]
  assign aon_auto_in_a_bits_opcode = crossing_auto_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign aon_auto_in_a_bits_param = crossing_auto_out_a_bits_param; // @[LazyModule.scala 296:16]
  assign aon_auto_in_a_bits_size = crossing_auto_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign aon_auto_in_a_bits_source = crossing_auto_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign aon_auto_in_a_bits_address = crossing_auto_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign aon_auto_in_a_bits_mask = crossing_auto_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign aon_auto_in_a_bits_data = crossing_auto_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign aon_auto_in_a_bits_corrupt = crossing_auto_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
  assign aon_auto_in_d_ready = crossing_auto_out_d_ready; // @[LazyModule.scala 296:16]
  assign aon_io_lfextclk = io_pins_lfextclk_i_ival; // @[MockAONWrapper.scala 94:33]
  assign aon_io_resetCauses_wdogrst = aon_io_wdog_rst; // @[MockAONWrapper.scala 69:32]
  assign aon_io_resetCauses_erst = ~io_pins_erst_n_i_ival; // @[MockAONWrapper.scala 67:16]
  assign isolation_auto_in_a_mem_0_opcode = auto_isolation_in_a_mem_0_opcode; // @[LazyModule.scala 309:16]
  assign isolation_auto_in_a_mem_0_param = auto_isolation_in_a_mem_0_param; // @[LazyModule.scala 309:16]
  assign isolation_auto_in_a_mem_0_size = auto_isolation_in_a_mem_0_size; // @[LazyModule.scala 309:16]
  assign isolation_auto_in_a_mem_0_source = auto_isolation_in_a_mem_0_source; // @[LazyModule.scala 309:16]
  assign isolation_auto_in_a_mem_0_address = auto_isolation_in_a_mem_0_address; // @[LazyModule.scala 309:16]
  assign isolation_auto_in_a_mem_0_mask = auto_isolation_in_a_mem_0_mask; // @[LazyModule.scala 309:16]
  assign isolation_auto_in_a_mem_0_data = auto_isolation_in_a_mem_0_data; // @[LazyModule.scala 309:16]
  assign isolation_auto_in_a_mem_0_corrupt = auto_isolation_in_a_mem_0_corrupt; // @[LazyModule.scala 309:16]
  assign isolation_auto_in_a_widx = auto_isolation_in_a_widx; // @[LazyModule.scala 309:16]
  assign isolation_auto_in_a_safe_widx_valid = auto_isolation_in_a_safe_widx_valid; // @[LazyModule.scala 309:16]
  assign isolation_auto_in_a_safe_source_reset_n = auto_isolation_in_a_safe_source_reset_n; // @[LazyModule.scala 309:16]
  assign isolation_auto_in_d_ridx = auto_isolation_in_d_ridx; // @[LazyModule.scala 309:16]
  assign isolation_auto_in_d_safe_ridx_valid = auto_isolation_in_d_safe_ridx_valid; // @[LazyModule.scala 309:16]
  assign isolation_auto_in_d_safe_sink_reset_n = auto_isolation_in_d_safe_sink_reset_n; // @[LazyModule.scala 309:16]
  assign isolation_auto_out_a_ridx = crossing_auto_in_a_ridx; // @[LazyModule.scala 298:16]
  assign isolation_auto_out_a_safe_ridx_valid = crossing_auto_in_a_safe_ridx_valid; // @[LazyModule.scala 298:16]
  assign isolation_auto_out_a_safe_sink_reset_n = crossing_auto_in_a_safe_sink_reset_n; // @[LazyModule.scala 298:16]
  assign isolation_auto_out_d_mem_0_opcode = crossing_auto_in_d_mem_0_opcode; // @[LazyModule.scala 298:16]
  assign isolation_auto_out_d_mem_0_size = crossing_auto_in_d_mem_0_size; // @[LazyModule.scala 298:16]
  assign isolation_auto_out_d_mem_0_source = crossing_auto_in_d_mem_0_source; // @[LazyModule.scala 298:16]
  assign isolation_auto_out_d_mem_0_data = crossing_auto_in_d_mem_0_data; // @[LazyModule.scala 298:16]
  assign isolation_auto_out_d_widx = crossing_auto_in_d_widx; // @[LazyModule.scala 298:16]
  assign isolation_auto_out_d_safe_widx_valid = crossing_auto_in_d_safe_widx_valid; // @[LazyModule.scala 298:16]
  assign isolation_auto_out_d_safe_source_reset_n = crossing_auto_in_d_safe_source_reset_n; // @[LazyModule.scala 298:16]
  assign isolation_io_iso_out = aon_io_moff_corerst; // @[MockAONWrapper.scala 123:33]
  assign crossing_clock = aon_io_lfclk; // @[MockAONWrapper.scala 118:27]
  assign crossing_reset = crossing_slave_reset_catcher_io_sync_reset; // @[MockAONWrapper.scala 119:27]
  assign crossing_auto_in_a_mem_0_opcode = isolation_auto_out_a_mem_0_opcode; // @[LazyModule.scala 298:16]
  assign crossing_auto_in_a_mem_0_param = isolation_auto_out_a_mem_0_param; // @[LazyModule.scala 298:16]
  assign crossing_auto_in_a_mem_0_size = isolation_auto_out_a_mem_0_size; // @[LazyModule.scala 298:16]
  assign crossing_auto_in_a_mem_0_source = isolation_auto_out_a_mem_0_source; // @[LazyModule.scala 298:16]
  assign crossing_auto_in_a_mem_0_address = isolation_auto_out_a_mem_0_address; // @[LazyModule.scala 298:16]
  assign crossing_auto_in_a_mem_0_mask = isolation_auto_out_a_mem_0_mask; // @[LazyModule.scala 298:16]
  assign crossing_auto_in_a_mem_0_data = isolation_auto_out_a_mem_0_data; // @[LazyModule.scala 298:16]
  assign crossing_auto_in_a_mem_0_corrupt = isolation_auto_out_a_mem_0_corrupt; // @[LazyModule.scala 298:16]
  assign crossing_auto_in_a_widx = isolation_auto_out_a_widx; // @[LazyModule.scala 298:16]
  assign crossing_auto_in_a_safe_widx_valid = isolation_auto_out_a_safe_widx_valid; // @[LazyModule.scala 298:16]
  assign crossing_auto_in_a_safe_source_reset_n = isolation_auto_out_a_safe_source_reset_n; // @[LazyModule.scala 298:16]
  assign crossing_auto_in_d_ridx = isolation_auto_out_d_ridx; // @[LazyModule.scala 298:16]
  assign crossing_auto_in_d_safe_ridx_valid = isolation_auto_out_d_safe_ridx_valid; // @[LazyModule.scala 298:16]
  assign crossing_auto_in_d_safe_sink_reset_n = isolation_auto_out_d_safe_sink_reset_n; // @[LazyModule.scala 298:16]
  assign crossing_auto_out_a_ready = aon_auto_in_a_ready; // @[LazyModule.scala 296:16]
  assign crossing_auto_out_d_valid = aon_auto_in_d_valid; // @[LazyModule.scala 296:16]
  assign crossing_auto_out_d_bits_opcode = aon_auto_in_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign crossing_auto_out_d_bits_size = aon_auto_in_d_bits_size; // @[LazyModule.scala 296:16]
  assign crossing_auto_out_d_bits_source = aon_auto_in_d_bits_source; // @[LazyModule.scala 296:16]
  assign crossing_auto_out_d_bits_data = aon_auto_in_d_bits_data; // @[LazyModule.scala 296:16]
  assign intsource_auto_in_0 = aon_auto_int_out_0; // @[LazyModule.scala 298:16]
  assign intsource_auto_in_1 = aon_auto_int_out_1; // @[LazyModule.scala 298:16]
  assign aonrst_catch_clock = aon_io_lfclk; // @[MockAONWrapper.scala 101:24]
  assign aonrst_catch_reset = erst | aon_io_wdog_rst | io_ndreset; // @[MockAONWrapper.scala 100:50]
  assign crossing_slave_reset_catcher_clock = aon_io_lfclk;
  assign crossing_slave_reset_catcher_reset = aon_io_moff_corerst | _crossing_slave_reset_T; // @[MockAONWrapper.scala 116:34]
endmodule
module SynchronizerShiftReg_w2_d3(
  input        clock,
  input  [1:0] io_d,
  output [1:0] io_q
);
  wire  output_chain_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_1_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_1_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_1_io_q; // @[ShiftReg.scala 45:23]
  wire  output_1 = output_chain_1_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  output_0 = output_chain_io_q; // @[ShiftReg.scala 48:{24,24}]
  NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_clock),
    .io_d(output_chain_io_d),
    .io_q(output_chain_io_q)
  );
  NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain_1 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_1_clock),
    .io_d(output_chain_1_io_d),
    .io_q(output_chain_1_io_q)
  );
  assign io_q = {output_1,output_0}; // @[Cat.scala 31:58]
  assign output_chain_clock = clock;
  assign output_chain_io_d = io_d[0]; // @[SynchronizerReg.scala 173:39]
  assign output_chain_1_clock = clock;
  assign output_chain_1_io_d = io_d[1]; // @[SynchronizerReg.scala 173:39]
endmodule
module IntSyncAsyncCrossingSink_1(
  input   clock,
  input   auto_in_sync_0,
  input   auto_in_sync_1,
  output  auto_out_0,
  output  auto_out_1
);
  wire  chain_clock; // @[ShiftReg.scala 45:23]
  wire [1:0] chain_io_d; // @[ShiftReg.scala 45:23]
  wire [1:0] chain_io_q; // @[ShiftReg.scala 45:23]
  wire [1:0] _WIRE_1 = chain_io_q;
  SynchronizerShiftReg_w2_d3 chain ( // @[ShiftReg.scala 45:23]
    .clock(chain_clock),
    .io_d(chain_io_d),
    .io_q(chain_io_q)
  );
  assign auto_out_0 = _WIRE_1[0]; // @[ShiftReg.scala 48:24]
  assign auto_out_1 = _WIRE_1[1]; // @[ShiftReg.scala 48:24]
  assign chain_clock = clock;
  assign chain_io_d = {auto_in_sync_1,auto_in_sync_0}; // @[ShiftReg.scala 47:22]
endmodule
module TLBuffer_13(
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [1:0]  auto_in_a_bits_size,
  input  [6:0]  auto_in_a_bits_source,
  input  [28:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input  [31:0] auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output [1:0]  auto_in_d_bits_size,
  output [6:0]  auto_in_d_bits_source,
  output [31:0] auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output [1:0]  auto_out_a_bits_size,
  output [6:0]  auto_out_a_bits_source,
  output [28:0] auto_out_a_bits_address,
  output [3:0]  auto_out_a_bits_mask,
  output [31:0] auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input  [1:0]  auto_out_d_bits_size,
  input  [6:0]  auto_out_d_bits_source,
  input  [31:0] auto_out_d_bits_data
);
  assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module TLMonitor_56(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [1:0]  io_in_a_bits_size,
  input  [6:0]  io_in_a_bits_source,
  input  [28:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_size,
  input  [6:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [95:0] _RAND_10;
  reg [383:0] _RAND_11;
  reg [383:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [95:0] _RAND_16;
  reg [383:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T_4 = io_in_a_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire [4:0] _is_aligned_mask_T_1 = 5'h3 << io_in_a_bits_size; // @[package.scala 234:77]
  wire [1:0] is_aligned_mask = ~_is_aligned_mask_T_1[1:0]; // @[package.scala 234:46]
  wire [28:0] _GEN_71 = {{27'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 2'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [28:0] _T_33 = io_in_a_bits_address ^ 29'h10013000; // @[Parameters.scala 137:31]
  wire [29:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
  wire [29:0] _T_36 = $signed(_T_34) & -30'sh1000; // @[Parameters.scala 137:52]
  wire  _T_37 = $signed(_T_36) == 30'sh0; // @[Parameters.scala 137:67]
  wire  _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_74 = _T_73 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_164 = io_in_a_bits_size <= 2'h2; // @[Parameters.scala 92:42]
  wire  _T_172 = _T_164 & _T_37; // @[Parameters.scala 670:56]
  wire  _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_218 = _source_ok_T_4 & _T_172; // @[Monitor.scala 115:71]
  wire  _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_273 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_274 = io_in_a_bits_mask & _T_273; // @[Monitor.scala 127:31]
  wire  _T_275 = _T_274 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_279 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_347 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_355 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_385 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_397 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_10 = io_in_d_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire  _T_401 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_405 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 312:27]
  wire  _T_421 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_449 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_478 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_495 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_513 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [1:0] size; // @[Monitor.scala 386:22]
  reg [6:0] source; // @[Monitor.scala 387:22]
  reg [28:0] address; // @[Monitor.scala 388:22]
  wire  _T_543 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_544 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_548 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_552 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_556 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_560 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] size_1; // @[Monitor.scala 537:22]
  reg [6:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_567 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_568 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_576 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_580 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [95:0] inflight; // @[Monitor.scala 611:27]
  reg [383:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [383:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [8:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [9:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [383:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [383:0] _GEN_73 = {{368'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[383:1]}; // @[Monitor.scala 634:152]
  wire [383:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [383:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
  wire [383:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[383:1]}; // @[Monitor.scala 638:144]
  wire  _T_594 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [127:0] _a_set_wo_ready_T = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_597 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
  wire [8:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [9:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [1026:0] _GEN_1 = {{1023'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [1026:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
  wire [1025:0] _GEN_2 = {{1023'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [1025:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [95:0] _T_599 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_601 = ~_T_599[0]; // @[Monitor.scala 658:17]
  wire [127:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 652:72 653:28]
  wire [1026:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 1027'h0; // @[Monitor.scala 652:72 656:28]
  wire [1025:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 1026'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_605 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_607 = ~_T_401; // @[Monitor.scala 671:74]
  wire  _T_608 = io_in_d_valid & d_first_1 & ~_T_401; // @[Monitor.scala 671:71]
  wire [127:0] _d_clr_wo_ready_T = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [1038:0] _GEN_3 = {{1023'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [1038:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [127:0] _GEN_22 = d_first_done & d_first_1 & _T_607 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 675:91 676:21]
  wire [1038:0] _GEN_23 = d_first_done & d_first_1 & _T_607 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_594 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [95:0] _T_618 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_620 = _T_618[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_625 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_626 = io_in_d_bits_opcode == _GEN_32 | _T_625; // @[Monitor.scala 685:77]
  wire  _T_630 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_637 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_638 = io_in_d_bits_opcode == _GEN_48 | _T_637; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_642 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_652 = _T_605 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_607; // @[Monitor.scala 694:116]
  wire  _T_654 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [95:0] a_set = _GEN_16[95:0];
  wire [95:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [95:0] d_clr = _GEN_22[95:0];
  wire [95:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [95:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [383:0] a_opcodes_set = _GEN_19[383:0];
  wire [383:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [383:0] d_opcodes_clr = _GEN_23[383:0];
  wire [383:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [383:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [383:0] a_sizes_set = _GEN_20[383:0];
  wire [383:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [383:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_663 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [95:0] inflight_1; // @[Monitor.scala 723:35]
  reg [383:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [383:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [383:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
  wire [383:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[383:1]}; // @[Monitor.scala 747:146]
  wire  _T_689 = io_in_d_valid & d_first_2 & _T_401; // @[Monitor.scala 779:71]
  wire [127:0] _GEN_67 = d_first_done & d_first_2 & _T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 783:90 784:21]
  wire [1038:0] _GEN_68 = d_first_done & d_first_2 & _T_401 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 783:90 785:21]
  wire [95:0] _T_697 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_707 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [95:0] d_clr_1 = _GEN_67[95:0];
  wire [95:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [95:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [383:0] d_opcodes_clr_1 = _GEN_68[383:0];
  wire [383:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [383:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_727 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 1'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= 1'h0;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 96'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 384'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 384'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 1'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= 1'h0;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 96'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 384'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= 1'h0;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (d_first_done) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_172 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_172) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_275 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_275) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_309 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_309) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_347 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_347) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_385 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_397 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_397) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_478 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_478 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_495 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_495 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_513 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_513 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_544 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_544) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_548 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_548) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_552 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_552) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_556 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_556) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_560 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_560) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_568 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_568) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_576 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_576) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_580 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_580) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_601 & (_T_597 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_597 & ~reset & ~_T_601) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_620 & (_T_608 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & _T_2 & ~_T_620) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_626 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_626) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_630 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_630) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_638 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_638) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_642 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_642) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_654 & (_T_652 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_652 & _T_2 & ~_T_654) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_663 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_663) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_697[0] & (_T_689 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_689 & _T_2 & ~_T_697[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_707 & (_T_689 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_689 & _T_2 & ~_T_707) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_727 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_727) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[6:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[28:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[6:0];
  _RAND_10 = {3{`RANDOM}};
  inflight = _RAND_10[95:0];
  _RAND_11 = {12{`RANDOM}};
  inflight_opcodes = _RAND_11[383:0];
  _RAND_12 = {12{`RANDOM}};
  inflight_sizes = _RAND_12[383:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {3{`RANDOM}};
  inflight_1 = _RAND_16[95:0];
  _RAND_17 = {12{`RANDOM}};
  inflight_sizes_1 = _RAND_17[383:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module UARTTx(
  input         clock,
  input         reset,
  input         io_en,
  output        io_in_ready,
  input         io_in_valid,
  input  [7:0]  io_in_bits,
  output        io_out,
  input  [15:0] io_div,
  input         io_nstop
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  reg [15:0] prescaler; // @[UARTTx.scala 23:22]
  wire  pulse = prescaler == 16'h0; // @[UARTTx.scala 24:26]
  reg [3:0] counter; // @[UARTTx.scala 27:20]
  reg [8:0] shifter; // @[UARTTx.scala 28:20]
  reg  out; // @[UARTTx.scala 29:16]
  wire  plusarg_tx = |plusarg_reader_out; // @[UARTTx.scala 32:90]
  wire  busy = counter != 4'h0; // @[UARTTx.scala 34:23]
  wire  _T = io_in_ready & io_in_valid; // @[Decoupled.scala 50:35]
  wire [9:0] _shifter_T_1 = {1'h1,io_in_bits,1'h0}; // @[Cat.scala 31:58]
  wire  _counter_T = ~io_nstop; // @[UARTTx.scala 57:19]
  wire [3:0] _counter_T_2 = _counter_T ? 4'ha : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _counter_T_3 = io_nstop ? 4'hb : 4'h0; // @[Mux.scala 27:73]
  wire [3:0] _counter_T_4 = _counter_T_2 | _counter_T_3; // @[Mux.scala 27:73]
  wire [3:0] _counter_T_6 = _counter_T_4 - 4'h0; // @[UARTTx.scala 57:53]
  wire [9:0] _GEN_0 = _T & plusarg_tx ? _shifter_T_1 : {{1'd0}, shifter}; // @[UARTTx.scala 40:37 55:15 28:20]
  wire [15:0] _prescaler_T_2 = prescaler - 16'h1; // @[UARTTx.scala 61:78]
  wire [3:0] _counter_T_8 = counter - 4'h1; // @[UARTTx.scala 64:24]
  wire [8:0] _shifter_T_3 = {1'h1,shifter[8:1]}; // @[Cat.scala 31:58]
  wire [9:0] _GEN_4 = pulse & busy ? {{1'd0}, _shifter_T_3} : _GEN_0; // @[UARTTx.scala 63:24 65:13]
  wire  _GEN_5 = pulse & busy ? shifter[0] : out; // @[UARTTx.scala 29:16 63:24 66:9]
  plusarg_reader #(.FORMAT("uart_tx=%d"), .DEFAULT(1), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  assign io_in_ready = io_en & ~busy; // @[UARTTx.scala 35:24]
  assign io_out = out; // @[UARTTx.scala 30:10]
  always @(posedge clock) begin
    if (reset) begin // @[UARTTx.scala 23:22]
      prescaler <= 16'h0; // @[UARTTx.scala 23:22]
    end else if (busy) begin // @[UARTTx.scala 60:15]
      if (pulse) begin // @[UARTTx.scala 61:21]
        prescaler <= io_div;
      end else begin
        prescaler <= _prescaler_T_2;
      end
    end
    if (reset) begin // @[UARTTx.scala 27:20]
      counter <= 4'h0; // @[UARTTx.scala 27:20]
    end else if (pulse & busy) begin // @[UARTTx.scala 63:24]
      counter <= _counter_T_8; // @[UARTTx.scala 64:13]
    end else if (_T & plusarg_tx) begin // @[UARTTx.scala 40:37]
      counter <= _counter_T_6; // @[UARTTx.scala 56:15]
    end
    shifter <= _GEN_4[8:0];
    out <= reset | _GEN_5; // @[UARTTx.scala 29:{16,16}]
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T & ~reset) begin
          $fwrite(32'h80000002,"UART TX (%x): %c\n",io_in_bits,io_in_bits); // @[UARTTx.scala 38:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  prescaler = _RAND_0[15:0];
  _RAND_1 = {1{`RANDOM}};
  counter = _RAND_1[3:0];
  _RAND_2 = {1{`RANDOM}};
  shifter = _RAND_2[8:0];
  _RAND_3 = {1{`RANDOM}};
  out = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module QueueCompatibility(
  input        clock,
  input        reset,
  output       io_enq_ready,
  input        io_enq_valid,
  input  [7:0] io_enq_bits,
  input        io_deq_ready,
  output       io_deq_valid,
  output [7:0] io_deq_bits,
  output [3:0] io_count
);
`ifdef RANDOMIZE_MEM_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif // RANDOMIZE_REG_INIT
  reg [7:0] ram [0:7]; // @[Decoupled.scala 259:95]
  wire  ram_io_deq_bits_MPORT_en; // @[Decoupled.scala 259:95]
  wire [2:0] ram_io_deq_bits_MPORT_addr; // @[Decoupled.scala 259:95]
  wire [7:0] ram_io_deq_bits_MPORT_data; // @[Decoupled.scala 259:95]
  wire [7:0] ram_MPORT_data; // @[Decoupled.scala 259:95]
  wire [2:0] ram_MPORT_addr; // @[Decoupled.scala 259:95]
  wire  ram_MPORT_mask; // @[Decoupled.scala 259:95]
  wire  ram_MPORT_en; // @[Decoupled.scala 259:95]
  reg [2:0] enq_ptr_value; // @[Counter.scala 62:40]
  reg [2:0] deq_ptr_value; // @[Counter.scala 62:40]
  reg  maybe_full; // @[Decoupled.scala 262:27]
  wire  ptr_match = enq_ptr_value == deq_ptr_value; // @[Decoupled.scala 263:33]
  wire  empty = ptr_match & ~maybe_full; // @[Decoupled.scala 264:25]
  wire  full = ptr_match & maybe_full; // @[Decoupled.scala 265:24]
  wire  do_enq = io_enq_ready & io_enq_valid; // @[Decoupled.scala 50:35]
  wire  do_deq = io_deq_ready & io_deq_valid; // @[Decoupled.scala 50:35]
  wire [2:0] _value_T_1 = enq_ptr_value + 3'h1; // @[Counter.scala 78:24]
  wire [2:0] _value_T_3 = deq_ptr_value + 3'h1; // @[Counter.scala 78:24]
  wire [2:0] ptr_diff = enq_ptr_value - deq_ptr_value; // @[Decoupled.scala 312:32]
  wire [3:0] _io_count_T_1 = maybe_full & ptr_match ? 4'h8 : 4'h0; // @[Decoupled.scala 315:20]
  wire [3:0] _GEN_11 = {{1'd0}, ptr_diff}; // @[Decoupled.scala 315:62]
  assign ram_io_deq_bits_MPORT_en = 1'h1;
  assign ram_io_deq_bits_MPORT_addr = deq_ptr_value;
  assign ram_io_deq_bits_MPORT_data = ram[ram_io_deq_bits_MPORT_addr]; // @[Decoupled.scala 259:95]
  assign ram_MPORT_data = io_enq_bits;
  assign ram_MPORT_addr = enq_ptr_value;
  assign ram_MPORT_mask = 1'h1;
  assign ram_MPORT_en = io_enq_ready & io_enq_valid;
  assign io_enq_ready = ~full; // @[Decoupled.scala 289:19]
  assign io_deq_valid = ~empty; // @[Decoupled.scala 288:19]
  assign io_deq_bits = ram_io_deq_bits_MPORT_data; // @[Decoupled.scala 296:17]
  assign io_count = _io_count_T_1 | _GEN_11; // @[Decoupled.scala 315:62]
  always @(posedge clock) begin
    if (ram_MPORT_en & ram_MPORT_mask) begin
      ram[ram_MPORT_addr] <= ram_MPORT_data; // @[Decoupled.scala 259:95]
    end
    if (reset) begin // @[Counter.scala 62:40]
      enq_ptr_value <= 3'h0; // @[Counter.scala 62:40]
    end else if (do_enq) begin // @[Decoupled.scala 272:16]
      enq_ptr_value <= _value_T_1; // @[Counter.scala 78:15]
    end
    if (reset) begin // @[Counter.scala 62:40]
      deq_ptr_value <= 3'h0; // @[Counter.scala 62:40]
    end else if (do_deq) begin // @[Decoupled.scala 276:16]
      deq_ptr_value <= _value_T_3; // @[Counter.scala 78:15]
    end
    if (reset) begin // @[Decoupled.scala 262:27]
      maybe_full <= 1'h0; // @[Decoupled.scala 262:27]
    end else if (do_enq != do_deq) begin // @[Decoupled.scala 279:27]
      maybe_full <= do_enq; // @[Decoupled.scala 280:16]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_MEM_INIT
  _RAND_0 = {1{`RANDOM}};
  for (initvar = 0; initvar < 8; initvar = initvar+1)
    ram[initvar] = _RAND_0[7:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
  _RAND_1 = {1{`RANDOM}};
  enq_ptr_value = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  deq_ptr_value = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  maybe_full = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module UARTRx(
  input         clock,
  input         reset,
  input         io_en,
  input         io_in,
  output        io_out_valid,
  output [7:0]  io_out_bits,
  input  [15:0] io_div
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
`endif // RANDOMIZE_REG_INIT
  reg [1:0] debounce; // @[UARTRx.scala 24:21]
  wire  debounce_max = debounce == 2'h3; // @[UARTRx.scala 25:32]
  wire  debounce_min = debounce == 2'h0; // @[UARTRx.scala 26:32]
  reg [12:0] prescaler; // @[UARTRx.scala 28:22]
  wire  pulse = prescaler == 13'h0; // @[UARTRx.scala 30:26]
  reg [3:0] data_count; // @[UARTRx.scala 34:23]
  wire  data_last = data_count == 4'h0; // @[UARTRx.scala 35:31]
  reg [3:0] sample_count; // @[UARTRx.scala 37:25]
  wire  sample_mid = sample_count == 4'h7; // @[UARTRx.scala 38:34]
  wire [7:0] _countdown_T = {data_count,sample_count}; // @[Cat.scala 31:58]
  wire [7:0] countdown = _countdown_T - 8'h1; // @[UARTRx.scala 40:49]
  wire [3:0] remainder = io_div[3:0]; // @[UARTRx.scala 45:25]
  wire  extend = sample_count < remainder; // @[UARTRx.scala 46:30]
  reg  state; // @[UARTRx.scala 61:18]
  wire  _T_5 = ~io_in; // @[UARTRx.scala 68:13]
  wire  _GEN_8 = ~io_in & debounce_max; // @[UARTRx.scala 68:21]
  wire  start = ~state & _GEN_8; // @[UARTRx.scala 63:18]
  wire  restore = start | pulse; // @[UARTRx.scala 47:23]
  wire [12:0] prescaler_in = restore ? {{1'd0}, io_div[15:4]} : prescaler; // @[UARTRx.scala 48:25]
  wire  _prescaler_next_T_1 = restore & extend ? 1'h0 : 1'h1; // @[UARTRx.scala 49:42]
  wire [12:0] _GEN_41 = {{12'd0}, _prescaler_next_T_1}; // @[UARTRx.scala 49:37]
  wire [12:0] prescaler_next = prescaler_in - _GEN_41; // @[UARTRx.scala 49:37]
  reg [2:0] sample; // @[UARTRx.scala 51:19]
  wire  _voter_T_3 = sample[0] & sample[1]; // @[Misc.scala 166:48]
  wire  _voter_T_4 = sample[0] & sample[2]; // @[Misc.scala 166:48]
  wire  _voter_T_6 = sample[1] & sample[2]; // @[Misc.scala 166:48]
  wire  voter = _voter_T_3 | _voter_T_4 | _voter_T_6; // @[Misc.scala 167:22]
  reg [7:0] shifter; // @[UARTRx.scala 53:20]
  reg  valid; // @[UARTRx.scala 55:18]
  wire [1:0] _debounce_T_1 = debounce - 2'h1; // @[UARTRx.scala 66:30]
  wire [1:0] _GEN_0 = ~_T_5 & ~debounce_min ? _debounce_T_1 : debounce; // @[UARTRx.scala 65:41 66:18 24:21]
  wire [1:0] _debounce_T_3 = debounce + 2'h1; // @[UARTRx.scala 69:30]
  wire [3:0] _data_count_T_3 = 4'h9 - 4'h0; // @[UARTRx.scala 74:94]
  wire  _GEN_1 = debounce_max | state; // @[UARTRx.scala 70:29 71:17 61:18]
  wire [3:0] _sample_T = {sample,io_in}; // @[Cat.scala 31:58]
  wire [7:0] _shifter_T_1 = {voter,shifter[7:1]}; // @[Cat.scala 31:58]
  wire  _GEN_12 = data_last ? 1'h0 : state; // @[UARTRx.scala 102:30 103:21 61:18]
  wire [7:0] _GEN_14 = data_last ? shifter : _shifter_T_1; // @[UARTRx.scala 102:30 53:20 106:23]
  wire  _GEN_15 = sample_mid ? _GEN_12 : state; // @[UARTRx.scala 61:18 87:27]
  wire  _GEN_16 = sample_mid & data_last; // @[UARTRx.scala 87:27 56:9]
  wire [3:0] _GEN_18 = pulse ? _sample_T : {{1'd0}, sample}; // @[UARTRx.scala 82:20 83:16 51:19]
  wire  _GEN_22 = pulse & _GEN_16; // @[UARTRx.scala 82:20 56:9]
  wire [3:0] _GEN_25 = state ? _GEN_18 : {{1'd0}, sample}; // @[UARTRx.scala 63:18 51:19]
  wire [3:0] _GEN_37 = ~state ? {{1'd0}, sample} : _GEN_25; // @[UARTRx.scala 63:18 51:19]
  assign io_out_valid = valid; // @[UARTRx.scala 57:16]
  assign io_out_bits = shifter; // @[UARTRx.scala 58:15]
  always @(posedge clock) begin
    if (reset) begin // @[UARTRx.scala 24:21]
      debounce <= 2'h0; // @[UARTRx.scala 24:21]
    end else if (~io_en) begin // @[UARTRx.scala 114:17]
      debounce <= 2'h0; // @[UARTRx.scala 115:14]
    end else if (~state) begin // @[UARTRx.scala 63:18]
      if (~io_in) begin // @[UARTRx.scala 68:21]
        debounce <= _debounce_T_3; // @[UARTRx.scala 69:18]
      end else begin
        debounce <= _GEN_0;
      end
    end
    if (~state) begin // @[UARTRx.scala 63:18]
      if (~io_in) begin // @[UARTRx.scala 68:21]
        if (debounce_max) begin // @[UARTRx.scala 70:29]
          prescaler <= prescaler_next; // @[UARTRx.scala 73:21]
        end
      end
    end else if (state) begin // @[UARTRx.scala 63:18]
      prescaler <= prescaler_next; // @[UARTRx.scala 81:17]
    end
    if (~state) begin // @[UARTRx.scala 63:18]
      if (~io_in) begin // @[UARTRx.scala 68:21]
        if (debounce_max) begin // @[UARTRx.scala 70:29]
          data_count <= _data_count_T_3; // @[UARTRx.scala 74:22]
        end
      end
    end else if (state) begin // @[UARTRx.scala 63:18]
      if (pulse) begin // @[UARTRx.scala 82:20]
        data_count <= countdown[7:4]; // @[UARTRx.scala 84:20]
      end
    end
    if (~state) begin // @[UARTRx.scala 63:18]
      if (~io_in) begin // @[UARTRx.scala 68:21]
        if (debounce_max) begin // @[UARTRx.scala 70:29]
          sample_count <= 4'hf; // @[UARTRx.scala 75:24]
        end
      end
    end else if (state) begin // @[UARTRx.scala 63:18]
      if (pulse) begin // @[UARTRx.scala 82:20]
        sample_count <= countdown[3:0]; // @[UARTRx.scala 85:22]
      end
    end
    if (reset) begin // @[UARTRx.scala 61:18]
      state <= 1'h0; // @[UARTRx.scala 61:18]
    end else if (~state) begin // @[UARTRx.scala 63:18]
      if (~io_in) begin // @[UARTRx.scala 68:21]
        state <= _GEN_1;
      end
    end else if (state) begin // @[UARTRx.scala 63:18]
      if (pulse) begin // @[UARTRx.scala 82:20]
        state <= _GEN_15;
      end
    end
    sample <= _GEN_37[2:0];
    if (!(~state)) begin // @[UARTRx.scala 63:18]
      if (state) begin // @[UARTRx.scala 63:18]
        if (pulse) begin // @[UARTRx.scala 82:20]
          if (sample_mid) begin // @[UARTRx.scala 87:27]
            shifter <= _GEN_14;
          end
        end
      end
    end
    if (reset) begin // @[UARTRx.scala 55:18]
      valid <= 1'h0; // @[UARTRx.scala 55:18]
    end else if (~state) begin // @[UARTRx.scala 63:18]
      valid <= 1'h0; // @[UARTRx.scala 56:9]
    end else begin
      valid <= state & _GEN_22;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  debounce = _RAND_0[1:0];
  _RAND_1 = {1{`RANDOM}};
  prescaler = _RAND_1[12:0];
  _RAND_2 = {1{`RANDOM}};
  data_count = _RAND_2[3:0];
  _RAND_3 = {1{`RANDOM}};
  sample_count = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  state = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  sample = _RAND_5[2:0];
  _RAND_6 = {1{`RANDOM}};
  shifter = _RAND_6[7:0];
  _RAND_7 = {1{`RANDOM}};
  valid = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLUART(
  input         clock,
  input         reset,
  output        auto_int_xing_out_sync_0,
  output        auto_control_xing_in_a_ready,
  input         auto_control_xing_in_a_valid,
  input  [2:0]  auto_control_xing_in_a_bits_opcode,
  input  [2:0]  auto_control_xing_in_a_bits_param,
  input  [1:0]  auto_control_xing_in_a_bits_size,
  input  [6:0]  auto_control_xing_in_a_bits_source,
  input  [28:0] auto_control_xing_in_a_bits_address,
  input  [3:0]  auto_control_xing_in_a_bits_mask,
  input  [31:0] auto_control_xing_in_a_bits_data,
  input         auto_control_xing_in_a_bits_corrupt,
  input         auto_control_xing_in_d_ready,
  output        auto_control_xing_in_d_valid,
  output [2:0]  auto_control_xing_in_d_bits_opcode,
  output [1:0]  auto_control_xing_in_d_bits_size,
  output [6:0]  auto_control_xing_in_d_bits_source,
  output [31:0] auto_control_xing_in_d_bits_data,
  output        auto_io_out_txd,
  input         auto_io_out_rxd
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
`endif // RANDOMIZE_REG_INIT
  wire  buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
  wire [28:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
  wire [28:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
  wire  intsource_clock; // @[Crossing.scala 26:31]
  wire  intsource_reset; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_0; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_0; // @[Crossing.scala 26:31]
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  txm_clock; // @[UART.scala 79:19]
  wire  txm_reset; // @[UART.scala 79:19]
  wire  txm_io_en; // @[UART.scala 79:19]
  wire  txm_io_in_ready; // @[UART.scala 79:19]
  wire  txm_io_in_valid; // @[UART.scala 79:19]
  wire [7:0] txm_io_in_bits; // @[UART.scala 79:19]
  wire  txm_io_out; // @[UART.scala 79:19]
  wire [15:0] txm_io_div; // @[UART.scala 79:19]
  wire  txm_io_nstop; // @[UART.scala 79:19]
  wire  txq_clock; // @[UART.scala 80:19]
  wire  txq_reset; // @[UART.scala 80:19]
  wire  txq_io_enq_ready; // @[UART.scala 80:19]
  wire  txq_io_enq_valid; // @[UART.scala 80:19]
  wire [7:0] txq_io_enq_bits; // @[UART.scala 80:19]
  wire  txq_io_deq_ready; // @[UART.scala 80:19]
  wire  txq_io_deq_valid; // @[UART.scala 80:19]
  wire [7:0] txq_io_deq_bits; // @[UART.scala 80:19]
  wire [3:0] txq_io_count; // @[UART.scala 80:19]
  wire  rxm_clock; // @[UART.scala 82:19]
  wire  rxm_reset; // @[UART.scala 82:19]
  wire  rxm_io_en; // @[UART.scala 82:19]
  wire  rxm_io_in; // @[UART.scala 82:19]
  wire  rxm_io_out_valid; // @[UART.scala 82:19]
  wire [7:0] rxm_io_out_bits; // @[UART.scala 82:19]
  wire [15:0] rxm_io_div; // @[UART.scala 82:19]
  wire  rxq_clock; // @[UART.scala 83:19]
  wire  rxq_reset; // @[UART.scala 83:19]
  wire  rxq_io_enq_ready; // @[UART.scala 83:19]
  wire  rxq_io_enq_valid; // @[UART.scala 83:19]
  wire [7:0] rxq_io_enq_bits; // @[UART.scala 83:19]
  wire  rxq_io_deq_ready; // @[UART.scala 83:19]
  wire  rxq_io_deq_valid; // @[UART.scala 83:19]
  wire [7:0] rxq_io_deq_bits; // @[UART.scala 83:19]
  wire [3:0] rxq_io_count; // @[UART.scala 83:19]
  reg [15:0] div; // @[UART.scala 85:16]
  reg  txen; // @[UART.scala 91:17]
  reg  rxen; // @[UART.scala 92:17]
  reg [3:0] txwm; // @[UART.scala 99:17]
  reg [3:0] rxwm; // @[UART.scala 100:17]
  reg  nstop; // @[UART.scala 101:18]
  reg  ie_rxwm; // @[UART.scala 135:15]
  reg  ie_txwm; // @[UART.scala 135:15]
  wire  ip_txwm = txq_io_count < txwm; // @[UART.scala 138:28]
  wire  ip_rxwm = rxq_io_count > rxwm; // @[UART.scala 139:28]
  wire  _T = ~txq_io_enq_ready; // @[RegMapFIFO.scala 25:9]
  wire  _T_1 = ~rxq_io_deq_valid; // @[RegMapFIFO.scala 46:21]
  wire [2:0] bundleIn_0_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  in_bits_read = bundleIn_0_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 72:36]
  wire [28:0] bundleIn_0_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [9:0] in_bits_index = bundleIn_0_a_bits_address[11:2]; // @[RegisterRouter.scala 71:18 73:19]
  wire [9:0] out_findex = in_bits_index & 10'h3f8; // @[RegisterRouter.scala 83:24]
  wire  _out_T = out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [3:0] bundleIn_0_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [7:0] _out_frontMask_T_5 = bundleIn_0_a_bits_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_frontMask_T_7 = bundleIn_0_a_bits_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_frontMask_T_9 = bundleIn_0_a_bits_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_frontMask_T_11 = bundleIn_0_a_bits_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [31:0] out_frontMask = {_out_frontMask_T_11,_out_frontMask_T_9,_out_frontMask_T_7,_out_frontMask_T_5}; // @[Cat.scala 31:58]
  wire  out_rimask = |out_frontMask[7:0]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask = &out_frontMask[7:0]; // @[RegisterRouter.scala 83:24]
  wire  bundleIn_0_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  bundleIn_0_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [2:0] out_oindex = {in_bits_index[2],in_bits_index[1],in_bits_index[0]}; // @[Cat.scala 31:58]
  wire [7:0] _out_frontSel_T = 8'h1 << out_oindex; // @[OneHot.scala 57:35]
  wire  out_frontSel_0 = _out_frontSel_T[0]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_0 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_0 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala 83:24]
  wire [31:0] bundleIn_0_a_bits_data = buffer_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  out_womask_2 = &out_frontMask[31]; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_2 = out_wivalid_0 & out_womask_2; // @[RegisterRouter.scala 83:24]
  wire  quash = out_f_woready_2 & bundleIn_0_a_bits_data[31]; // @[RegMapFIFO.scala 27:26]
  wire [31:0] out_prepend_1 = {_T,31'h0}; // @[Cat.scala 31:58]
  wire  out_wimask_3 = &out_frontMask[0]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_4 = &out_frontMask[1]; // @[RegisterRouter.scala 83:24]
  wire [1:0] out_prepend_2 = {ip_rxwm,ip_txwm}; // @[Cat.scala 31:58]
  wire  out_frontSel_1 = _out_frontSel_T[1]; // @[RegisterRouter.scala 83:24]
  wire  out_rivalid_5 = bundleIn_0_a_valid & bundleIn_0_d_ready & in_bits_read & out_frontSel_1 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [7:0] _out_T_66 = rxq_io_deq_bits; // @[RegisterRouter.scala 83:24]
  wire [8:0] out_prepend_3 = {1'h0,_out_T_66}; // @[Cat.scala 31:58]
  wire [30:0] _out_T_75 = {{22'd0}, out_prepend_3}; // @[RegisterRouter.scala 83:24]
  wire [31:0] out_prepend_4 = {_T_1,_out_T_75}; // @[Cat.scala 31:58]
  wire  out_wimask_8 = &out_frontMask[15:0]; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_6 = _out_frontSel_T[6]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_8 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_6 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_2 = _out_frontSel_T[2]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_9 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_2 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_9 = out_wivalid_9 & out_wimask_3; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_10 = out_wivalid_9 & out_wimask_4; // @[RegisterRouter.scala 83:24]
  wire [1:0] out_prepend_5 = {nstop,txen}; // @[Cat.scala 31:58]
  wire  out_wimask_11 = &out_frontMask[19:16]; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_11 = out_wivalid_9 & out_wimask_11; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_prepend_T_6 = {{14'd0}, out_prepend_5}; // @[RegisterRouter.scala 83:24]
  wire [19:0] out_prepend_6 = {txwm,_out_prepend_T_6}; // @[Cat.scala 31:58]
  wire  out_frontSel_3 = _out_frontSel_T[3]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_12 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_3 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_12 = out_wivalid_12 & out_wimask_3; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_13 = out_wivalid_12 & out_wimask_11; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_prepend_T_7 = {{15'd0}, rxen}; // @[RegisterRouter.scala 83:24]
  wire [19:0] out_prepend_7 = {rxwm,_out_prepend_T_7}; // @[Cat.scala 31:58]
  wire  out_frontSel_4 = _out_frontSel_T[4]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_14 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_4 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_14 = out_wivalid_14 & out_wimask_3; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_15 = out_wivalid_14 & out_wimask_4; // @[RegisterRouter.scala 83:24]
  wire [1:0] out_prepend_8 = {ie_rxwm,ie_txwm}; // @[Cat.scala 31:58]
  wire  _GEN_41 = 3'h1 == out_oindex ? _out_T : _out_T; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_42 = 3'h2 == out_oindex ? _out_T : _GEN_41; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_43 = 3'h3 == out_oindex ? _out_T : _GEN_42; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_44 = 3'h4 == out_oindex ? _out_T : _GEN_43; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_45 = 3'h5 == out_oindex ? _out_T : _GEN_44; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_46 = 3'h6 == out_oindex ? _out_T : _GEN_45; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_47 = 3'h7 == out_oindex | _GEN_46; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_49 = 3'h1 == out_oindex ? out_prepend_4 : out_prepend_1; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_2 = {{12'd0}, out_prepend_6}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_50 = 3'h2 == out_oindex ? _out_out_bits_data_WIRE_1_2 : _GEN_49; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_3 = {{12'd0}, out_prepend_7}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_51 = 3'h3 == out_oindex ? _out_out_bits_data_WIRE_1_3 : _GEN_50; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_4 = {{30'd0}, out_prepend_8}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_52 = 3'h4 == out_oindex ? _out_out_bits_data_WIRE_1_4 : _GEN_51; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_5 = {{30'd0}, out_prepend_2}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_53 = 3'h5 == out_oindex ? _out_out_bits_data_WIRE_1_5 : _GEN_52; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_6 = {{16'd0}, div}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_54 = 3'h6 == out_oindex ? _out_out_bits_data_WIRE_1_6 : _GEN_53; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_55 = 3'h7 == out_oindex ? 32'h0 : _GEN_54; // @[MuxLiteral.scala 48:{10,10}]
  TLBuffer_13 buffer ( // @[Buffer.scala 68:28]
    .auto_in_a_ready(buffer_auto_in_a_ready),
    .auto_in_a_valid(buffer_auto_in_a_valid),
    .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
    .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
    .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
    .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
    .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
    .auto_in_a_bits_data(buffer_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
    .auto_in_d_ready(buffer_auto_in_d_ready),
    .auto_in_d_valid(buffer_auto_in_d_valid),
    .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
    .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
    .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
    .auto_out_a_ready(buffer_auto_out_a_ready),
    .auto_out_a_valid(buffer_auto_out_a_valid),
    .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
    .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
    .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
    .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
    .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
    .auto_out_a_bits_data(buffer_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
    .auto_out_d_ready(buffer_auto_out_d_ready),
    .auto_out_d_valid(buffer_auto_out_d_valid),
    .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
    .auto_out_d_bits_source(buffer_auto_out_d_bits_source),
    .auto_out_d_bits_data(buffer_auto_out_d_bits_data)
  );
  IntSyncCrossingSource_1 intsource ( // @[Crossing.scala 26:31]
    .clock(intsource_clock),
    .reset(intsource_reset),
    .auto_in_0(intsource_auto_in_0),
    .auto_out_sync_0(intsource_auto_out_sync_0)
  );
  TLMonitor_56 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  UARTTx txm ( // @[UART.scala 79:19]
    .clock(txm_clock),
    .reset(txm_reset),
    .io_en(txm_io_en),
    .io_in_ready(txm_io_in_ready),
    .io_in_valid(txm_io_in_valid),
    .io_in_bits(txm_io_in_bits),
    .io_out(txm_io_out),
    .io_div(txm_io_div),
    .io_nstop(txm_io_nstop)
  );
  QueueCompatibility txq ( // @[UART.scala 80:19]
    .clock(txq_clock),
    .reset(txq_reset),
    .io_enq_ready(txq_io_enq_ready),
    .io_enq_valid(txq_io_enq_valid),
    .io_enq_bits(txq_io_enq_bits),
    .io_deq_ready(txq_io_deq_ready),
    .io_deq_valid(txq_io_deq_valid),
    .io_deq_bits(txq_io_deq_bits),
    .io_count(txq_io_count)
  );
  UARTRx rxm ( // @[UART.scala 82:19]
    .clock(rxm_clock),
    .reset(rxm_reset),
    .io_en(rxm_io_en),
    .io_in(rxm_io_in),
    .io_out_valid(rxm_io_out_valid),
    .io_out_bits(rxm_io_out_bits),
    .io_div(rxm_io_div)
  );
  QueueCompatibility rxq ( // @[UART.scala 83:19]
    .clock(rxq_clock),
    .reset(rxq_reset),
    .io_enq_ready(rxq_io_enq_ready),
    .io_enq_valid(rxq_io_enq_valid),
    .io_enq_bits(rxq_io_enq_bits),
    .io_deq_ready(rxq_io_deq_ready),
    .io_deq_valid(rxq_io_deq_valid),
    .io_deq_bits(rxq_io_deq_bits),
    .io_count(rxq_io_count)
  );
  assign auto_int_xing_out_sync_0 = intsource_auto_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_in_a_ready = buffer_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_valid = buffer_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_size = buffer_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_source = buffer_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_data = buffer_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_io_out_txd = txm_io_out; // @[Nodes.scala 1207:84 UART.scala 113:12]
  assign buffer_auto_in_a_valid = auto_control_xing_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_opcode = auto_control_xing_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_param = auto_control_xing_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_size = auto_control_xing_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_source = auto_control_xing_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_address = auto_control_xing_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_mask = auto_control_xing_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_data = auto_control_xing_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_corrupt = auto_control_xing_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_d_ready = auto_control_xing_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_out_a_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign buffer_auto_out_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_data = _GEN_47 ? _GEN_55 : 32'h0; // @[RegisterRouter.scala 83:24]
  assign intsource_clock = clock;
  assign intsource_reset = reset;
  assign intsource_auto_in_0 = ip_txwm & ie_txwm | ip_rxwm & ie_rxwm; // @[UART.scala 140:41]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_param = buffer_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign monitor_io_in_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign txm_clock = clock;
  assign txm_reset = reset;
  assign txm_io_en = txen; // @[UART.scala 109:15]
  assign txm_io_in_valid = txq_io_deq_valid; // @[UART.scala 110:13]
  assign txm_io_in_bits = txq_io_deq_bits; // @[UART.scala 110:13]
  assign txm_io_div = div; // @[UART.scala 111:14]
  assign txm_io_nstop = nstop; // @[UART.scala 112:16]
  assign txq_clock = clock;
  assign txq_reset = reset;
  assign txq_io_enq_valid = out_f_wivalid & ~quash; // @[RegMapFIFO.scala 19:30]
  assign txq_io_enq_bits = bundleIn_0_a_bits_data[7:0]; // @[RegisterRouter.scala 83:24]
  assign txq_io_deq_ready = txm_io_in_ready; // @[UART.scala 110:13]
  assign rxm_clock = clock;
  assign rxm_reset = reset;
  assign rxm_io_en = rxen; // @[UART.scala 120:13]
  assign rxm_io_in = auto_io_out_rxd; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign rxm_io_div = div; // @[UART.scala 123:14]
  assign rxq_clock = clock;
  assign rxq_reset = reset;
  assign rxq_io_enq_valid = rxm_io_out_valid; // @[UART.scala 122:14]
  assign rxq_io_enq_bits = rxm_io_out_bits; // @[UART.scala 122:14]
  assign rxq_io_deq_ready = out_rivalid_5 & out_rimask; // @[RegisterRouter.scala 83:24]
  always @(posedge clock) begin
    if (reset) begin // @[UART.scala 85:16]
      div <= 16'h364; // @[UART.scala 85:16]
    end else if (out_f_wivalid_8) begin // @[RegField.scala 74:88]
      div <= bundleIn_0_a_bits_data[15:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[UART.scala 91:17]
      txen <= 1'h0; // @[UART.scala 91:17]
    end else if (out_f_wivalid_9) begin // @[RegField.scala 74:88]
      txen <= bundleIn_0_a_bits_data[0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[UART.scala 92:17]
      rxen <= 1'h0; // @[UART.scala 92:17]
    end else if (out_f_wivalid_12) begin // @[RegField.scala 74:88]
      rxen <= bundleIn_0_a_bits_data[0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[UART.scala 99:17]
      txwm <= 4'h0; // @[UART.scala 99:17]
    end else if (out_f_wivalid_11) begin // @[RegField.scala 74:88]
      txwm <= bundleIn_0_a_bits_data[19:16]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[UART.scala 100:17]
      rxwm <= 4'h0; // @[UART.scala 100:17]
    end else if (out_f_wivalid_13) begin // @[RegField.scala 74:88]
      rxwm <= bundleIn_0_a_bits_data[19:16]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[UART.scala 101:18]
      nstop <= 1'h0; // @[UART.scala 101:18]
    end else if (out_f_wivalid_10) begin // @[RegField.scala 74:88]
      nstop <= bundleIn_0_a_bits_data[1]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[UART.scala 135:15]
      ie_rxwm <= 1'h0; // @[UART.scala 135:15]
    end else if (out_f_wivalid_15) begin // @[RegField.scala 74:88]
      ie_rxwm <= bundleIn_0_a_bits_data[1]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[UART.scala 135:15]
      ie_txwm <= 1'h0; // @[UART.scala 135:15]
    end else if (out_f_wivalid_14) begin // @[RegField.scala 74:88]
      ie_txwm <= bundleIn_0_a_bits_data[0]; // @[RegField.scala 74:92]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  div = _RAND_0[15:0];
  _RAND_1 = {1{`RANDOM}};
  txen = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  rxen = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  txwm = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  rxwm = _RAND_4[3:0];
  _RAND_5 = {1{`RANDOM}};
  nstop = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  ie_rxwm = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  ie_txwm = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ClockSinkDomain_1(
  output        auto_uart_0_int_xing_out_sync_0,
  output        auto_uart_0_control_xing_in_a_ready,
  input         auto_uart_0_control_xing_in_a_valid,
  input  [2:0]  auto_uart_0_control_xing_in_a_bits_opcode,
  input  [2:0]  auto_uart_0_control_xing_in_a_bits_param,
  input  [1:0]  auto_uart_0_control_xing_in_a_bits_size,
  input  [6:0]  auto_uart_0_control_xing_in_a_bits_source,
  input  [28:0] auto_uart_0_control_xing_in_a_bits_address,
  input  [3:0]  auto_uart_0_control_xing_in_a_bits_mask,
  input  [31:0] auto_uart_0_control_xing_in_a_bits_data,
  input         auto_uart_0_control_xing_in_a_bits_corrupt,
  input         auto_uart_0_control_xing_in_d_ready,
  output        auto_uart_0_control_xing_in_d_valid,
  output [2:0]  auto_uart_0_control_xing_in_d_bits_opcode,
  output [1:0]  auto_uart_0_control_xing_in_d_bits_size,
  output [6:0]  auto_uart_0_control_xing_in_d_bits_source,
  output [31:0] auto_uart_0_control_xing_in_d_bits_data,
  output        auto_uart_0_io_out_txd,
  input         auto_uart_0_io_out_rxd,
  input         auto_clock_in_clock,
  input         auto_clock_in_reset
);
  wire  uart_0_clock; // @[UART.scala 243:51]
  wire  uart_0_reset; // @[UART.scala 243:51]
  wire  uart_0_auto_int_xing_out_sync_0; // @[UART.scala 243:51]
  wire  uart_0_auto_control_xing_in_a_ready; // @[UART.scala 243:51]
  wire  uart_0_auto_control_xing_in_a_valid; // @[UART.scala 243:51]
  wire [2:0] uart_0_auto_control_xing_in_a_bits_opcode; // @[UART.scala 243:51]
  wire [2:0] uart_0_auto_control_xing_in_a_bits_param; // @[UART.scala 243:51]
  wire [1:0] uart_0_auto_control_xing_in_a_bits_size; // @[UART.scala 243:51]
  wire [6:0] uart_0_auto_control_xing_in_a_bits_source; // @[UART.scala 243:51]
  wire [28:0] uart_0_auto_control_xing_in_a_bits_address; // @[UART.scala 243:51]
  wire [3:0] uart_0_auto_control_xing_in_a_bits_mask; // @[UART.scala 243:51]
  wire [31:0] uart_0_auto_control_xing_in_a_bits_data; // @[UART.scala 243:51]
  wire  uart_0_auto_control_xing_in_a_bits_corrupt; // @[UART.scala 243:51]
  wire  uart_0_auto_control_xing_in_d_ready; // @[UART.scala 243:51]
  wire  uart_0_auto_control_xing_in_d_valid; // @[UART.scala 243:51]
  wire [2:0] uart_0_auto_control_xing_in_d_bits_opcode; // @[UART.scala 243:51]
  wire [1:0] uart_0_auto_control_xing_in_d_bits_size; // @[UART.scala 243:51]
  wire [6:0] uart_0_auto_control_xing_in_d_bits_source; // @[UART.scala 243:51]
  wire [31:0] uart_0_auto_control_xing_in_d_bits_data; // @[UART.scala 243:51]
  wire  uart_0_auto_io_out_txd; // @[UART.scala 243:51]
  wire  uart_0_auto_io_out_rxd; // @[UART.scala 243:51]
  TLUART uart_0 ( // @[UART.scala 243:51]
    .clock(uart_0_clock),
    .reset(uart_0_reset),
    .auto_int_xing_out_sync_0(uart_0_auto_int_xing_out_sync_0),
    .auto_control_xing_in_a_ready(uart_0_auto_control_xing_in_a_ready),
    .auto_control_xing_in_a_valid(uart_0_auto_control_xing_in_a_valid),
    .auto_control_xing_in_a_bits_opcode(uart_0_auto_control_xing_in_a_bits_opcode),
    .auto_control_xing_in_a_bits_param(uart_0_auto_control_xing_in_a_bits_param),
    .auto_control_xing_in_a_bits_size(uart_0_auto_control_xing_in_a_bits_size),
    .auto_control_xing_in_a_bits_source(uart_0_auto_control_xing_in_a_bits_source),
    .auto_control_xing_in_a_bits_address(uart_0_auto_control_xing_in_a_bits_address),
    .auto_control_xing_in_a_bits_mask(uart_0_auto_control_xing_in_a_bits_mask),
    .auto_control_xing_in_a_bits_data(uart_0_auto_control_xing_in_a_bits_data),
    .auto_control_xing_in_a_bits_corrupt(uart_0_auto_control_xing_in_a_bits_corrupt),
    .auto_control_xing_in_d_ready(uart_0_auto_control_xing_in_d_ready),
    .auto_control_xing_in_d_valid(uart_0_auto_control_xing_in_d_valid),
    .auto_control_xing_in_d_bits_opcode(uart_0_auto_control_xing_in_d_bits_opcode),
    .auto_control_xing_in_d_bits_size(uart_0_auto_control_xing_in_d_bits_size),
    .auto_control_xing_in_d_bits_source(uart_0_auto_control_xing_in_d_bits_source),
    .auto_control_xing_in_d_bits_data(uart_0_auto_control_xing_in_d_bits_data),
    .auto_io_out_txd(uart_0_auto_io_out_txd),
    .auto_io_out_rxd(uart_0_auto_io_out_rxd)
  );
  assign auto_uart_0_int_xing_out_sync_0 = uart_0_auto_int_xing_out_sync_0; // @[LazyModule.scala 311:12]
  assign auto_uart_0_control_xing_in_a_ready = uart_0_auto_control_xing_in_a_ready; // @[LazyModule.scala 309:16]
  assign auto_uart_0_control_xing_in_d_valid = uart_0_auto_control_xing_in_d_valid; // @[LazyModule.scala 309:16]
  assign auto_uart_0_control_xing_in_d_bits_opcode = uart_0_auto_control_xing_in_d_bits_opcode; // @[LazyModule.scala 309:16]
  assign auto_uart_0_control_xing_in_d_bits_size = uart_0_auto_control_xing_in_d_bits_size; // @[LazyModule.scala 309:16]
  assign auto_uart_0_control_xing_in_d_bits_source = uart_0_auto_control_xing_in_d_bits_source; // @[LazyModule.scala 309:16]
  assign auto_uart_0_control_xing_in_d_bits_data = uart_0_auto_control_xing_in_d_bits_data; // @[LazyModule.scala 309:16]
  assign auto_uart_0_io_out_txd = uart_0_auto_io_out_txd; // @[LazyModule.scala 311:12]
  assign uart_0_clock = auto_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign uart_0_reset = auto_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign uart_0_auto_control_xing_in_a_valid = auto_uart_0_control_xing_in_a_valid; // @[LazyModule.scala 309:16]
  assign uart_0_auto_control_xing_in_a_bits_opcode = auto_uart_0_control_xing_in_a_bits_opcode; // @[LazyModule.scala 309:16]
  assign uart_0_auto_control_xing_in_a_bits_param = auto_uart_0_control_xing_in_a_bits_param; // @[LazyModule.scala 309:16]
  assign uart_0_auto_control_xing_in_a_bits_size = auto_uart_0_control_xing_in_a_bits_size; // @[LazyModule.scala 309:16]
  assign uart_0_auto_control_xing_in_a_bits_source = auto_uart_0_control_xing_in_a_bits_source; // @[LazyModule.scala 309:16]
  assign uart_0_auto_control_xing_in_a_bits_address = auto_uart_0_control_xing_in_a_bits_address; // @[LazyModule.scala 309:16]
  assign uart_0_auto_control_xing_in_a_bits_mask = auto_uart_0_control_xing_in_a_bits_mask; // @[LazyModule.scala 309:16]
  assign uart_0_auto_control_xing_in_a_bits_data = auto_uart_0_control_xing_in_a_bits_data; // @[LazyModule.scala 309:16]
  assign uart_0_auto_control_xing_in_a_bits_corrupt = auto_uart_0_control_xing_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
  assign uart_0_auto_control_xing_in_d_ready = auto_uart_0_control_xing_in_d_ready; // @[LazyModule.scala 309:16]
  assign uart_0_auto_io_out_rxd = auto_uart_0_io_out_rxd; // @[LazyModule.scala 311:12]
endmodule
module TLMonitor_57(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [1:0]  io_in_a_bits_size,
  input  [6:0]  io_in_a_bits_source,
  input  [28:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_size,
  input  [6:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [95:0] _RAND_10;
  reg [383:0] _RAND_11;
  reg [383:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [95:0] _RAND_16;
  reg [383:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T_4 = io_in_a_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire [4:0] _is_aligned_mask_T_1 = 5'h3 << io_in_a_bits_size; // @[package.scala 234:77]
  wire [1:0] is_aligned_mask = ~_is_aligned_mask_T_1[1:0]; // @[package.scala 234:46]
  wire [28:0] _GEN_71 = {{27'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 2'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [28:0] _T_33 = io_in_a_bits_address ^ 29'h10023000; // @[Parameters.scala 137:31]
  wire [29:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
  wire [29:0] _T_36 = $signed(_T_34) & -30'sh1000; // @[Parameters.scala 137:52]
  wire  _T_37 = $signed(_T_36) == 30'sh0; // @[Parameters.scala 137:67]
  wire  _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_74 = _T_73 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_164 = io_in_a_bits_size <= 2'h2; // @[Parameters.scala 92:42]
  wire  _T_172 = _T_164 & _T_37; // @[Parameters.scala 670:56]
  wire  _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_218 = _source_ok_T_4 & _T_172; // @[Monitor.scala 115:71]
  wire  _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_273 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_274 = io_in_a_bits_mask & _T_273; // @[Monitor.scala 127:31]
  wire  _T_275 = _T_274 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_279 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_347 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_355 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_385 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_397 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_10 = io_in_d_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire  _T_401 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_405 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 312:27]
  wire  _T_421 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_449 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_478 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_495 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_513 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [1:0] size; // @[Monitor.scala 386:22]
  reg [6:0] source; // @[Monitor.scala 387:22]
  reg [28:0] address; // @[Monitor.scala 388:22]
  wire  _T_543 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_544 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_548 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_552 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_556 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_560 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] size_1; // @[Monitor.scala 537:22]
  reg [6:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_567 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_568 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_576 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_580 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [95:0] inflight; // @[Monitor.scala 611:27]
  reg [383:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [383:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [8:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [9:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [383:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [383:0] _GEN_73 = {{368'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[383:1]}; // @[Monitor.scala 634:152]
  wire [383:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [383:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
  wire [383:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[383:1]}; // @[Monitor.scala 638:144]
  wire  _T_594 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [127:0] _a_set_wo_ready_T = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_597 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
  wire [8:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [9:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [1026:0] _GEN_1 = {{1023'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [1026:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
  wire [1025:0] _GEN_2 = {{1023'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [1025:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [95:0] _T_599 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_601 = ~_T_599[0]; // @[Monitor.scala 658:17]
  wire [127:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 652:72 653:28]
  wire [1026:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 1027'h0; // @[Monitor.scala 652:72 656:28]
  wire [1025:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 1026'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_605 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_607 = ~_T_401; // @[Monitor.scala 671:74]
  wire  _T_608 = io_in_d_valid & d_first_1 & ~_T_401; // @[Monitor.scala 671:71]
  wire [127:0] _d_clr_wo_ready_T = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [1038:0] _GEN_3 = {{1023'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [1038:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [127:0] _GEN_22 = d_first_done & d_first_1 & _T_607 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 675:91 676:21]
  wire [1038:0] _GEN_23 = d_first_done & d_first_1 & _T_607 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_594 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [95:0] _T_618 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_620 = _T_618[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_625 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_626 = io_in_d_bits_opcode == _GEN_32 | _T_625; // @[Monitor.scala 685:77]
  wire  _T_630 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_637 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_638 = io_in_d_bits_opcode == _GEN_48 | _T_637; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_642 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_652 = _T_605 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_607; // @[Monitor.scala 694:116]
  wire  _T_654 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [95:0] a_set = _GEN_16[95:0];
  wire [95:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [95:0] d_clr = _GEN_22[95:0];
  wire [95:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [95:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [383:0] a_opcodes_set = _GEN_19[383:0];
  wire [383:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [383:0] d_opcodes_clr = _GEN_23[383:0];
  wire [383:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [383:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [383:0] a_sizes_set = _GEN_20[383:0];
  wire [383:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [383:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_663 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [95:0] inflight_1; // @[Monitor.scala 723:35]
  reg [383:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [383:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [383:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
  wire [383:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[383:1]}; // @[Monitor.scala 747:146]
  wire  _T_689 = io_in_d_valid & d_first_2 & _T_401; // @[Monitor.scala 779:71]
  wire [127:0] _GEN_67 = d_first_done & d_first_2 & _T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 783:90 784:21]
  wire [1038:0] _GEN_68 = d_first_done & d_first_2 & _T_401 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 783:90 785:21]
  wire [95:0] _T_697 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_707 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [95:0] d_clr_1 = _GEN_67[95:0];
  wire [95:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [95:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [383:0] d_opcodes_clr_1 = _GEN_68[383:0];
  wire [383:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [383:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_727 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 1'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= 1'h0;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 96'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 384'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 384'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 1'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= 1'h0;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 96'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 384'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= 1'h0;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (d_first_done) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_172 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_172) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_275 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_275) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_309 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_309) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_347 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_347) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_385 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_397 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_397) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_478 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_478 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_495 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_495 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_513 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_513 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_544 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_544) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_548 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_548) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_552 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_552) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_556 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_556) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_560 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_560) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_568 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_568) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_576 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_576) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_580 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_580) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_601 & (_T_597 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_597 & ~reset & ~_T_601) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_620 & (_T_608 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & _T_2 & ~_T_620) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_626 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_626) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_630 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_630) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_638 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_638) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_642 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_642) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_654 & (_T_652 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_652 & _T_2 & ~_T_654) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_663 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_663) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_697[0] & (_T_689 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_689 & _T_2 & ~_T_697[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_707 & (_T_689 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_689 & _T_2 & ~_T_707) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_727 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_727) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[6:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[28:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[6:0];
  _RAND_10 = {3{`RANDOM}};
  inflight = _RAND_10[95:0];
  _RAND_11 = {12{`RANDOM}};
  inflight_opcodes = _RAND_11[383:0];
  _RAND_12 = {12{`RANDOM}};
  inflight_sizes = _RAND_12[383:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {3{`RANDOM}};
  inflight_1 = _RAND_16[95:0];
  _RAND_17 = {12{`RANDOM}};
  inflight_sizes_1 = _RAND_17[383:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLUART_1(
  input         clock,
  input         reset,
  output        auto_int_xing_out_sync_0,
  output        auto_control_xing_in_a_ready,
  input         auto_control_xing_in_a_valid,
  input  [2:0]  auto_control_xing_in_a_bits_opcode,
  input  [2:0]  auto_control_xing_in_a_bits_param,
  input  [1:0]  auto_control_xing_in_a_bits_size,
  input  [6:0]  auto_control_xing_in_a_bits_source,
  input  [28:0] auto_control_xing_in_a_bits_address,
  input  [3:0]  auto_control_xing_in_a_bits_mask,
  input  [31:0] auto_control_xing_in_a_bits_data,
  input         auto_control_xing_in_a_bits_corrupt,
  input         auto_control_xing_in_d_ready,
  output        auto_control_xing_in_d_valid,
  output [2:0]  auto_control_xing_in_d_bits_opcode,
  output [1:0]  auto_control_xing_in_d_bits_size,
  output [6:0]  auto_control_xing_in_d_bits_source,
  output [31:0] auto_control_xing_in_d_bits_data,
  output        auto_io_out_txd,
  input         auto_io_out_rxd
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
`endif // RANDOMIZE_REG_INIT
  wire  buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
  wire [28:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
  wire [28:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
  wire  intsource_clock; // @[Crossing.scala 26:31]
  wire  intsource_reset; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_0; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_0; // @[Crossing.scala 26:31]
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  txm_clock; // @[UART.scala 79:19]
  wire  txm_reset; // @[UART.scala 79:19]
  wire  txm_io_en; // @[UART.scala 79:19]
  wire  txm_io_in_ready; // @[UART.scala 79:19]
  wire  txm_io_in_valid; // @[UART.scala 79:19]
  wire [7:0] txm_io_in_bits; // @[UART.scala 79:19]
  wire  txm_io_out; // @[UART.scala 79:19]
  wire [15:0] txm_io_div; // @[UART.scala 79:19]
  wire  txm_io_nstop; // @[UART.scala 79:19]
  wire  txq_clock; // @[UART.scala 80:19]
  wire  txq_reset; // @[UART.scala 80:19]
  wire  txq_io_enq_ready; // @[UART.scala 80:19]
  wire  txq_io_enq_valid; // @[UART.scala 80:19]
  wire [7:0] txq_io_enq_bits; // @[UART.scala 80:19]
  wire  txq_io_deq_ready; // @[UART.scala 80:19]
  wire  txq_io_deq_valid; // @[UART.scala 80:19]
  wire [7:0] txq_io_deq_bits; // @[UART.scala 80:19]
  wire [3:0] txq_io_count; // @[UART.scala 80:19]
  wire  rxm_clock; // @[UART.scala 82:19]
  wire  rxm_reset; // @[UART.scala 82:19]
  wire  rxm_io_en; // @[UART.scala 82:19]
  wire  rxm_io_in; // @[UART.scala 82:19]
  wire  rxm_io_out_valid; // @[UART.scala 82:19]
  wire [7:0] rxm_io_out_bits; // @[UART.scala 82:19]
  wire [15:0] rxm_io_div; // @[UART.scala 82:19]
  wire  rxq_clock; // @[UART.scala 83:19]
  wire  rxq_reset; // @[UART.scala 83:19]
  wire  rxq_io_enq_ready; // @[UART.scala 83:19]
  wire  rxq_io_enq_valid; // @[UART.scala 83:19]
  wire [7:0] rxq_io_enq_bits; // @[UART.scala 83:19]
  wire  rxq_io_deq_ready; // @[UART.scala 83:19]
  wire  rxq_io_deq_valid; // @[UART.scala 83:19]
  wire [7:0] rxq_io_deq_bits; // @[UART.scala 83:19]
  wire [3:0] rxq_io_count; // @[UART.scala 83:19]
  reg [15:0] div; // @[UART.scala 85:16]
  reg  txen; // @[UART.scala 91:17]
  reg  rxen; // @[UART.scala 92:17]
  reg [3:0] txwm; // @[UART.scala 99:17]
  reg [3:0] rxwm; // @[UART.scala 100:17]
  reg  nstop; // @[UART.scala 101:18]
  reg  ie_rxwm; // @[UART.scala 135:15]
  reg  ie_txwm; // @[UART.scala 135:15]
  wire  ip_txwm = txq_io_count < txwm; // @[UART.scala 138:28]
  wire  ip_rxwm = rxq_io_count > rxwm; // @[UART.scala 139:28]
  wire  _T = ~txq_io_enq_ready; // @[RegMapFIFO.scala 25:9]
  wire  _T_1 = ~rxq_io_deq_valid; // @[RegMapFIFO.scala 46:21]
  wire [2:0] bundleIn_0_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  in_bits_read = bundleIn_0_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 72:36]
  wire [28:0] bundleIn_0_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [9:0] in_bits_index = bundleIn_0_a_bits_address[11:2]; // @[RegisterRouter.scala 71:18 73:19]
  wire [9:0] out_findex = in_bits_index & 10'h3f8; // @[RegisterRouter.scala 83:24]
  wire  _out_T = out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [3:0] bundleIn_0_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [7:0] _out_frontMask_T_5 = bundleIn_0_a_bits_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_frontMask_T_7 = bundleIn_0_a_bits_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_frontMask_T_9 = bundleIn_0_a_bits_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_frontMask_T_11 = bundleIn_0_a_bits_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [31:0] out_frontMask = {_out_frontMask_T_11,_out_frontMask_T_9,_out_frontMask_T_7,_out_frontMask_T_5}; // @[Cat.scala 31:58]
  wire  out_rimask = |out_frontMask[7:0]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask = &out_frontMask[7:0]; // @[RegisterRouter.scala 83:24]
  wire  bundleIn_0_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  bundleIn_0_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [2:0] out_oindex = {in_bits_index[2],in_bits_index[1],in_bits_index[0]}; // @[Cat.scala 31:58]
  wire [7:0] _out_frontSel_T = 8'h1 << out_oindex; // @[OneHot.scala 57:35]
  wire  out_frontSel_0 = _out_frontSel_T[0]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_0 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_0 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala 83:24]
  wire [31:0] bundleIn_0_a_bits_data = buffer_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  out_womask_2 = &out_frontMask[31]; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_2 = out_wivalid_0 & out_womask_2; // @[RegisterRouter.scala 83:24]
  wire  quash = out_f_woready_2 & bundleIn_0_a_bits_data[31]; // @[RegMapFIFO.scala 27:26]
  wire [31:0] out_prepend_1 = {_T,31'h0}; // @[Cat.scala 31:58]
  wire  out_wimask_3 = &out_frontMask[0]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_4 = &out_frontMask[1]; // @[RegisterRouter.scala 83:24]
  wire [1:0] out_prepend_2 = {ip_rxwm,ip_txwm}; // @[Cat.scala 31:58]
  wire  out_frontSel_1 = _out_frontSel_T[1]; // @[RegisterRouter.scala 83:24]
  wire  out_rivalid_5 = bundleIn_0_a_valid & bundleIn_0_d_ready & in_bits_read & out_frontSel_1 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [7:0] _out_T_66 = rxq_io_deq_bits; // @[RegisterRouter.scala 83:24]
  wire [8:0] out_prepend_3 = {1'h0,_out_T_66}; // @[Cat.scala 31:58]
  wire [30:0] _out_T_75 = {{22'd0}, out_prepend_3}; // @[RegisterRouter.scala 83:24]
  wire [31:0] out_prepend_4 = {_T_1,_out_T_75}; // @[Cat.scala 31:58]
  wire  out_wimask_8 = &out_frontMask[15:0]; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_6 = _out_frontSel_T[6]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_8 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_6 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_2 = _out_frontSel_T[2]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_9 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_2 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_9 = out_wivalid_9 & out_wimask_3; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_10 = out_wivalid_9 & out_wimask_4; // @[RegisterRouter.scala 83:24]
  wire [1:0] out_prepend_5 = {nstop,txen}; // @[Cat.scala 31:58]
  wire  out_wimask_11 = &out_frontMask[19:16]; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_11 = out_wivalid_9 & out_wimask_11; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_prepend_T_6 = {{14'd0}, out_prepend_5}; // @[RegisterRouter.scala 83:24]
  wire [19:0] out_prepend_6 = {txwm,_out_prepend_T_6}; // @[Cat.scala 31:58]
  wire  out_frontSel_3 = _out_frontSel_T[3]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_12 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_3 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_12 = out_wivalid_12 & out_wimask_3; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_13 = out_wivalid_12 & out_wimask_11; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_prepend_T_7 = {{15'd0}, rxen}; // @[RegisterRouter.scala 83:24]
  wire [19:0] out_prepend_7 = {rxwm,_out_prepend_T_7}; // @[Cat.scala 31:58]
  wire  out_frontSel_4 = _out_frontSel_T[4]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_14 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_4 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_14 = out_wivalid_14 & out_wimask_3; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_15 = out_wivalid_14 & out_wimask_4; // @[RegisterRouter.scala 83:24]
  wire [1:0] out_prepend_8 = {ie_rxwm,ie_txwm}; // @[Cat.scala 31:58]
  wire  _GEN_41 = 3'h1 == out_oindex ? _out_T : _out_T; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_42 = 3'h2 == out_oindex ? _out_T : _GEN_41; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_43 = 3'h3 == out_oindex ? _out_T : _GEN_42; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_44 = 3'h4 == out_oindex ? _out_T : _GEN_43; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_45 = 3'h5 == out_oindex ? _out_T : _GEN_44; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_46 = 3'h6 == out_oindex ? _out_T : _GEN_45; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_47 = 3'h7 == out_oindex | _GEN_46; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_49 = 3'h1 == out_oindex ? out_prepend_4 : out_prepend_1; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_2 = {{12'd0}, out_prepend_6}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_50 = 3'h2 == out_oindex ? _out_out_bits_data_WIRE_1_2 : _GEN_49; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_3 = {{12'd0}, out_prepend_7}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_51 = 3'h3 == out_oindex ? _out_out_bits_data_WIRE_1_3 : _GEN_50; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_4 = {{30'd0}, out_prepend_8}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_52 = 3'h4 == out_oindex ? _out_out_bits_data_WIRE_1_4 : _GEN_51; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_5 = {{30'd0}, out_prepend_2}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_53 = 3'h5 == out_oindex ? _out_out_bits_data_WIRE_1_5 : _GEN_52; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_6 = {{16'd0}, div}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_54 = 3'h6 == out_oindex ? _out_out_bits_data_WIRE_1_6 : _GEN_53; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_55 = 3'h7 == out_oindex ? 32'h0 : _GEN_54; // @[MuxLiteral.scala 48:{10,10}]
  TLBuffer_13 buffer ( // @[Buffer.scala 68:28]
    .auto_in_a_ready(buffer_auto_in_a_ready),
    .auto_in_a_valid(buffer_auto_in_a_valid),
    .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
    .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
    .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
    .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
    .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
    .auto_in_a_bits_data(buffer_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
    .auto_in_d_ready(buffer_auto_in_d_ready),
    .auto_in_d_valid(buffer_auto_in_d_valid),
    .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
    .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
    .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
    .auto_out_a_ready(buffer_auto_out_a_ready),
    .auto_out_a_valid(buffer_auto_out_a_valid),
    .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
    .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
    .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
    .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
    .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
    .auto_out_a_bits_data(buffer_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
    .auto_out_d_ready(buffer_auto_out_d_ready),
    .auto_out_d_valid(buffer_auto_out_d_valid),
    .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
    .auto_out_d_bits_source(buffer_auto_out_d_bits_source),
    .auto_out_d_bits_data(buffer_auto_out_d_bits_data)
  );
  IntSyncCrossingSource_1 intsource ( // @[Crossing.scala 26:31]
    .clock(intsource_clock),
    .reset(intsource_reset),
    .auto_in_0(intsource_auto_in_0),
    .auto_out_sync_0(intsource_auto_out_sync_0)
  );
  TLMonitor_57 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  UARTTx txm ( // @[UART.scala 79:19]
    .clock(txm_clock),
    .reset(txm_reset),
    .io_en(txm_io_en),
    .io_in_ready(txm_io_in_ready),
    .io_in_valid(txm_io_in_valid),
    .io_in_bits(txm_io_in_bits),
    .io_out(txm_io_out),
    .io_div(txm_io_div),
    .io_nstop(txm_io_nstop)
  );
  QueueCompatibility txq ( // @[UART.scala 80:19]
    .clock(txq_clock),
    .reset(txq_reset),
    .io_enq_ready(txq_io_enq_ready),
    .io_enq_valid(txq_io_enq_valid),
    .io_enq_bits(txq_io_enq_bits),
    .io_deq_ready(txq_io_deq_ready),
    .io_deq_valid(txq_io_deq_valid),
    .io_deq_bits(txq_io_deq_bits),
    .io_count(txq_io_count)
  );
  UARTRx rxm ( // @[UART.scala 82:19]
    .clock(rxm_clock),
    .reset(rxm_reset),
    .io_en(rxm_io_en),
    .io_in(rxm_io_in),
    .io_out_valid(rxm_io_out_valid),
    .io_out_bits(rxm_io_out_bits),
    .io_div(rxm_io_div)
  );
  QueueCompatibility rxq ( // @[UART.scala 83:19]
    .clock(rxq_clock),
    .reset(rxq_reset),
    .io_enq_ready(rxq_io_enq_ready),
    .io_enq_valid(rxq_io_enq_valid),
    .io_enq_bits(rxq_io_enq_bits),
    .io_deq_ready(rxq_io_deq_ready),
    .io_deq_valid(rxq_io_deq_valid),
    .io_deq_bits(rxq_io_deq_bits),
    .io_count(rxq_io_count)
  );
  assign auto_int_xing_out_sync_0 = intsource_auto_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_in_a_ready = buffer_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_valid = buffer_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_size = buffer_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_source = buffer_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_data = buffer_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_io_out_txd = txm_io_out; // @[Nodes.scala 1207:84 UART.scala 113:12]
  assign buffer_auto_in_a_valid = auto_control_xing_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_opcode = auto_control_xing_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_param = auto_control_xing_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_size = auto_control_xing_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_source = auto_control_xing_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_address = auto_control_xing_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_mask = auto_control_xing_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_data = auto_control_xing_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_corrupt = auto_control_xing_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_d_ready = auto_control_xing_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_out_a_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign buffer_auto_out_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_data = _GEN_47 ? _GEN_55 : 32'h0; // @[RegisterRouter.scala 83:24]
  assign intsource_clock = clock;
  assign intsource_reset = reset;
  assign intsource_auto_in_0 = ip_txwm & ie_txwm | ip_rxwm & ie_rxwm; // @[UART.scala 140:41]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_param = buffer_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign monitor_io_in_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign txm_clock = clock;
  assign txm_reset = reset;
  assign txm_io_en = txen; // @[UART.scala 109:15]
  assign txm_io_in_valid = txq_io_deq_valid; // @[UART.scala 110:13]
  assign txm_io_in_bits = txq_io_deq_bits; // @[UART.scala 110:13]
  assign txm_io_div = div; // @[UART.scala 111:14]
  assign txm_io_nstop = nstop; // @[UART.scala 112:16]
  assign txq_clock = clock;
  assign txq_reset = reset;
  assign txq_io_enq_valid = out_f_wivalid & ~quash; // @[RegMapFIFO.scala 19:30]
  assign txq_io_enq_bits = bundleIn_0_a_bits_data[7:0]; // @[RegisterRouter.scala 83:24]
  assign txq_io_deq_ready = txm_io_in_ready; // @[UART.scala 110:13]
  assign rxm_clock = clock;
  assign rxm_reset = reset;
  assign rxm_io_en = rxen; // @[UART.scala 120:13]
  assign rxm_io_in = auto_io_out_rxd; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign rxm_io_div = div; // @[UART.scala 123:14]
  assign rxq_clock = clock;
  assign rxq_reset = reset;
  assign rxq_io_enq_valid = rxm_io_out_valid; // @[UART.scala 122:14]
  assign rxq_io_enq_bits = rxm_io_out_bits; // @[UART.scala 122:14]
  assign rxq_io_deq_ready = out_rivalid_5 & out_rimask; // @[RegisterRouter.scala 83:24]
  always @(posedge clock) begin
    if (reset) begin // @[UART.scala 85:16]
      div <= 16'h364; // @[UART.scala 85:16]
    end else if (out_f_wivalid_8) begin // @[RegField.scala 74:88]
      div <= bundleIn_0_a_bits_data[15:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[UART.scala 91:17]
      txen <= 1'h0; // @[UART.scala 91:17]
    end else if (out_f_wivalid_9) begin // @[RegField.scala 74:88]
      txen <= bundleIn_0_a_bits_data[0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[UART.scala 92:17]
      rxen <= 1'h0; // @[UART.scala 92:17]
    end else if (out_f_wivalid_12) begin // @[RegField.scala 74:88]
      rxen <= bundleIn_0_a_bits_data[0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[UART.scala 99:17]
      txwm <= 4'h0; // @[UART.scala 99:17]
    end else if (out_f_wivalid_11) begin // @[RegField.scala 74:88]
      txwm <= bundleIn_0_a_bits_data[19:16]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[UART.scala 100:17]
      rxwm <= 4'h0; // @[UART.scala 100:17]
    end else if (out_f_wivalid_13) begin // @[RegField.scala 74:88]
      rxwm <= bundleIn_0_a_bits_data[19:16]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[UART.scala 101:18]
      nstop <= 1'h0; // @[UART.scala 101:18]
    end else if (out_f_wivalid_10) begin // @[RegField.scala 74:88]
      nstop <= bundleIn_0_a_bits_data[1]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[UART.scala 135:15]
      ie_rxwm <= 1'h0; // @[UART.scala 135:15]
    end else if (out_f_wivalid_15) begin // @[RegField.scala 74:88]
      ie_rxwm <= bundleIn_0_a_bits_data[1]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[UART.scala 135:15]
      ie_txwm <= 1'h0; // @[UART.scala 135:15]
    end else if (out_f_wivalid_14) begin // @[RegField.scala 74:88]
      ie_txwm <= bundleIn_0_a_bits_data[0]; // @[RegField.scala 74:92]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  div = _RAND_0[15:0];
  _RAND_1 = {1{`RANDOM}};
  txen = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  rxen = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  txwm = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  rxwm = _RAND_4[3:0];
  _RAND_5 = {1{`RANDOM}};
  nstop = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  ie_rxwm = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  ie_txwm = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ClockSinkDomain_2(
  output        auto_uart_1_int_xing_out_sync_0,
  output        auto_uart_1_control_xing_in_a_ready,
  input         auto_uart_1_control_xing_in_a_valid,
  input  [2:0]  auto_uart_1_control_xing_in_a_bits_opcode,
  input  [2:0]  auto_uart_1_control_xing_in_a_bits_param,
  input  [1:0]  auto_uart_1_control_xing_in_a_bits_size,
  input  [6:0]  auto_uart_1_control_xing_in_a_bits_source,
  input  [28:0] auto_uart_1_control_xing_in_a_bits_address,
  input  [3:0]  auto_uart_1_control_xing_in_a_bits_mask,
  input  [31:0] auto_uart_1_control_xing_in_a_bits_data,
  input         auto_uart_1_control_xing_in_a_bits_corrupt,
  input         auto_uart_1_control_xing_in_d_ready,
  output        auto_uart_1_control_xing_in_d_valid,
  output [2:0]  auto_uart_1_control_xing_in_d_bits_opcode,
  output [1:0]  auto_uart_1_control_xing_in_d_bits_size,
  output [6:0]  auto_uart_1_control_xing_in_d_bits_source,
  output [31:0] auto_uart_1_control_xing_in_d_bits_data,
  output        auto_uart_1_io_out_txd,
  input         auto_uart_1_io_out_rxd,
  input         auto_clock_in_clock,
  input         auto_clock_in_reset
);
  wire  uart_1_clock; // @[UART.scala 243:51]
  wire  uart_1_reset; // @[UART.scala 243:51]
  wire  uart_1_auto_int_xing_out_sync_0; // @[UART.scala 243:51]
  wire  uart_1_auto_control_xing_in_a_ready; // @[UART.scala 243:51]
  wire  uart_1_auto_control_xing_in_a_valid; // @[UART.scala 243:51]
  wire [2:0] uart_1_auto_control_xing_in_a_bits_opcode; // @[UART.scala 243:51]
  wire [2:0] uart_1_auto_control_xing_in_a_bits_param; // @[UART.scala 243:51]
  wire [1:0] uart_1_auto_control_xing_in_a_bits_size; // @[UART.scala 243:51]
  wire [6:0] uart_1_auto_control_xing_in_a_bits_source; // @[UART.scala 243:51]
  wire [28:0] uart_1_auto_control_xing_in_a_bits_address; // @[UART.scala 243:51]
  wire [3:0] uart_1_auto_control_xing_in_a_bits_mask; // @[UART.scala 243:51]
  wire [31:0] uart_1_auto_control_xing_in_a_bits_data; // @[UART.scala 243:51]
  wire  uart_1_auto_control_xing_in_a_bits_corrupt; // @[UART.scala 243:51]
  wire  uart_1_auto_control_xing_in_d_ready; // @[UART.scala 243:51]
  wire  uart_1_auto_control_xing_in_d_valid; // @[UART.scala 243:51]
  wire [2:0] uart_1_auto_control_xing_in_d_bits_opcode; // @[UART.scala 243:51]
  wire [1:0] uart_1_auto_control_xing_in_d_bits_size; // @[UART.scala 243:51]
  wire [6:0] uart_1_auto_control_xing_in_d_bits_source; // @[UART.scala 243:51]
  wire [31:0] uart_1_auto_control_xing_in_d_bits_data; // @[UART.scala 243:51]
  wire  uart_1_auto_io_out_txd; // @[UART.scala 243:51]
  wire  uart_1_auto_io_out_rxd; // @[UART.scala 243:51]
  TLUART_1 uart_1 ( // @[UART.scala 243:51]
    .clock(uart_1_clock),
    .reset(uart_1_reset),
    .auto_int_xing_out_sync_0(uart_1_auto_int_xing_out_sync_0),
    .auto_control_xing_in_a_ready(uart_1_auto_control_xing_in_a_ready),
    .auto_control_xing_in_a_valid(uart_1_auto_control_xing_in_a_valid),
    .auto_control_xing_in_a_bits_opcode(uart_1_auto_control_xing_in_a_bits_opcode),
    .auto_control_xing_in_a_bits_param(uart_1_auto_control_xing_in_a_bits_param),
    .auto_control_xing_in_a_bits_size(uart_1_auto_control_xing_in_a_bits_size),
    .auto_control_xing_in_a_bits_source(uart_1_auto_control_xing_in_a_bits_source),
    .auto_control_xing_in_a_bits_address(uart_1_auto_control_xing_in_a_bits_address),
    .auto_control_xing_in_a_bits_mask(uart_1_auto_control_xing_in_a_bits_mask),
    .auto_control_xing_in_a_bits_data(uart_1_auto_control_xing_in_a_bits_data),
    .auto_control_xing_in_a_bits_corrupt(uart_1_auto_control_xing_in_a_bits_corrupt),
    .auto_control_xing_in_d_ready(uart_1_auto_control_xing_in_d_ready),
    .auto_control_xing_in_d_valid(uart_1_auto_control_xing_in_d_valid),
    .auto_control_xing_in_d_bits_opcode(uart_1_auto_control_xing_in_d_bits_opcode),
    .auto_control_xing_in_d_bits_size(uart_1_auto_control_xing_in_d_bits_size),
    .auto_control_xing_in_d_bits_source(uart_1_auto_control_xing_in_d_bits_source),
    .auto_control_xing_in_d_bits_data(uart_1_auto_control_xing_in_d_bits_data),
    .auto_io_out_txd(uart_1_auto_io_out_txd),
    .auto_io_out_rxd(uart_1_auto_io_out_rxd)
  );
  assign auto_uart_1_int_xing_out_sync_0 = uart_1_auto_int_xing_out_sync_0; // @[LazyModule.scala 311:12]
  assign auto_uart_1_control_xing_in_a_ready = uart_1_auto_control_xing_in_a_ready; // @[LazyModule.scala 309:16]
  assign auto_uart_1_control_xing_in_d_valid = uart_1_auto_control_xing_in_d_valid; // @[LazyModule.scala 309:16]
  assign auto_uart_1_control_xing_in_d_bits_opcode = uart_1_auto_control_xing_in_d_bits_opcode; // @[LazyModule.scala 309:16]
  assign auto_uart_1_control_xing_in_d_bits_size = uart_1_auto_control_xing_in_d_bits_size; // @[LazyModule.scala 309:16]
  assign auto_uart_1_control_xing_in_d_bits_source = uart_1_auto_control_xing_in_d_bits_source; // @[LazyModule.scala 309:16]
  assign auto_uart_1_control_xing_in_d_bits_data = uart_1_auto_control_xing_in_d_bits_data; // @[LazyModule.scala 309:16]
  assign auto_uart_1_io_out_txd = uart_1_auto_io_out_txd; // @[LazyModule.scala 311:12]
  assign uart_1_clock = auto_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign uart_1_reset = auto_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign uart_1_auto_control_xing_in_a_valid = auto_uart_1_control_xing_in_a_valid; // @[LazyModule.scala 309:16]
  assign uart_1_auto_control_xing_in_a_bits_opcode = auto_uart_1_control_xing_in_a_bits_opcode; // @[LazyModule.scala 309:16]
  assign uart_1_auto_control_xing_in_a_bits_param = auto_uart_1_control_xing_in_a_bits_param; // @[LazyModule.scala 309:16]
  assign uart_1_auto_control_xing_in_a_bits_size = auto_uart_1_control_xing_in_a_bits_size; // @[LazyModule.scala 309:16]
  assign uart_1_auto_control_xing_in_a_bits_source = auto_uart_1_control_xing_in_a_bits_source; // @[LazyModule.scala 309:16]
  assign uart_1_auto_control_xing_in_a_bits_address = auto_uart_1_control_xing_in_a_bits_address; // @[LazyModule.scala 309:16]
  assign uart_1_auto_control_xing_in_a_bits_mask = auto_uart_1_control_xing_in_a_bits_mask; // @[LazyModule.scala 309:16]
  assign uart_1_auto_control_xing_in_a_bits_data = auto_uart_1_control_xing_in_a_bits_data; // @[LazyModule.scala 309:16]
  assign uart_1_auto_control_xing_in_a_bits_corrupt = auto_uart_1_control_xing_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
  assign uart_1_auto_control_xing_in_d_ready = auto_uart_1_control_xing_in_d_ready; // @[LazyModule.scala 309:16]
  assign uart_1_auto_io_out_rxd = auto_uart_1_io_out_rxd; // @[LazyModule.scala 311:12]
endmodule
module TLMonitor_58(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [1:0]  io_in_a_bits_size,
  input  [6:0]  io_in_a_bits_source,
  input  [28:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_size,
  input  [6:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [95:0] _RAND_10;
  reg [383:0] _RAND_11;
  reg [383:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [95:0] _RAND_16;
  reg [383:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T_4 = io_in_a_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire [4:0] _is_aligned_mask_T_1 = 5'h3 << io_in_a_bits_size; // @[package.scala 234:77]
  wire [1:0] is_aligned_mask = ~_is_aligned_mask_T_1[1:0]; // @[package.scala 234:46]
  wire [28:0] _GEN_71 = {{27'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 2'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [28:0] _T_33 = io_in_a_bits_address ^ 29'h10033000; // @[Parameters.scala 137:31]
  wire [29:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
  wire [29:0] _T_36 = $signed(_T_34) & -30'sh1000; // @[Parameters.scala 137:52]
  wire  _T_37 = $signed(_T_36) == 30'sh0; // @[Parameters.scala 137:67]
  wire  _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_74 = _T_73 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_164 = io_in_a_bits_size <= 2'h2; // @[Parameters.scala 92:42]
  wire  _T_172 = _T_164 & _T_37; // @[Parameters.scala 670:56]
  wire  _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_218 = _source_ok_T_4 & _T_172; // @[Monitor.scala 115:71]
  wire  _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_273 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_274 = io_in_a_bits_mask & _T_273; // @[Monitor.scala 127:31]
  wire  _T_275 = _T_274 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_279 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_347 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_355 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_385 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_397 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_10 = io_in_d_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire  _T_401 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_405 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 312:27]
  wire  _T_421 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_449 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_478 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_495 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_513 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [1:0] size; // @[Monitor.scala 386:22]
  reg [6:0] source; // @[Monitor.scala 387:22]
  reg [28:0] address; // @[Monitor.scala 388:22]
  wire  _T_543 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_544 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_548 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_552 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_556 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_560 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] size_1; // @[Monitor.scala 537:22]
  reg [6:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_567 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_568 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_576 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_580 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [95:0] inflight; // @[Monitor.scala 611:27]
  reg [383:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [383:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [8:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [9:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [383:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [383:0] _GEN_73 = {{368'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[383:1]}; // @[Monitor.scala 634:152]
  wire [383:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [383:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
  wire [383:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[383:1]}; // @[Monitor.scala 638:144]
  wire  _T_594 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [127:0] _a_set_wo_ready_T = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_597 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
  wire [8:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [9:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [1026:0] _GEN_1 = {{1023'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [1026:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
  wire [1025:0] _GEN_2 = {{1023'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [1025:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [95:0] _T_599 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_601 = ~_T_599[0]; // @[Monitor.scala 658:17]
  wire [127:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 652:72 653:28]
  wire [1026:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 1027'h0; // @[Monitor.scala 652:72 656:28]
  wire [1025:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 1026'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_605 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_607 = ~_T_401; // @[Monitor.scala 671:74]
  wire  _T_608 = io_in_d_valid & d_first_1 & ~_T_401; // @[Monitor.scala 671:71]
  wire [127:0] _d_clr_wo_ready_T = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [1038:0] _GEN_3 = {{1023'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [1038:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [127:0] _GEN_22 = d_first_done & d_first_1 & _T_607 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 675:91 676:21]
  wire [1038:0] _GEN_23 = d_first_done & d_first_1 & _T_607 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_594 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [95:0] _T_618 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_620 = _T_618[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_625 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_626 = io_in_d_bits_opcode == _GEN_32 | _T_625; // @[Monitor.scala 685:77]
  wire  _T_630 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_637 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_638 = io_in_d_bits_opcode == _GEN_48 | _T_637; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_642 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_652 = _T_605 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_607; // @[Monitor.scala 694:116]
  wire  _T_654 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [95:0] a_set = _GEN_16[95:0];
  wire [95:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [95:0] d_clr = _GEN_22[95:0];
  wire [95:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [95:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [383:0] a_opcodes_set = _GEN_19[383:0];
  wire [383:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [383:0] d_opcodes_clr = _GEN_23[383:0];
  wire [383:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [383:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [383:0] a_sizes_set = _GEN_20[383:0];
  wire [383:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [383:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_663 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [95:0] inflight_1; // @[Monitor.scala 723:35]
  reg [383:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [383:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [383:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
  wire [383:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[383:1]}; // @[Monitor.scala 747:146]
  wire  _T_689 = io_in_d_valid & d_first_2 & _T_401; // @[Monitor.scala 779:71]
  wire [127:0] _GEN_67 = d_first_done & d_first_2 & _T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 783:90 784:21]
  wire [1038:0] _GEN_68 = d_first_done & d_first_2 & _T_401 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 783:90 785:21]
  wire [95:0] _T_697 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_707 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [95:0] d_clr_1 = _GEN_67[95:0];
  wire [95:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [95:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [383:0] d_opcodes_clr_1 = _GEN_68[383:0];
  wire [383:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [383:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_727 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 1'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= 1'h0;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 96'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 384'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 384'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 1'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= 1'h0;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 96'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 384'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= 1'h0;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (d_first_done) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_172 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_172) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_275 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_275) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_309 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_309) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_347 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_347) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_385 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_397 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_397) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_478 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_478 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_495 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_495 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_513 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_513 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_544 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_544) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_548 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_548) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_552 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_552) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_556 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_556) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_560 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_560) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_568 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_568) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_576 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_576) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_580 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_580) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_601 & (_T_597 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_597 & ~reset & ~_T_601) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_620 & (_T_608 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & _T_2 & ~_T_620) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_626 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_626) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_630 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_630) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_638 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_638) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_642 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_642) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_654 & (_T_652 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_652 & _T_2 & ~_T_654) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_663 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_663) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_697[0] & (_T_689 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_689 & _T_2 & ~_T_697[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_707 & (_T_689 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_689 & _T_2 & ~_T_707) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_727 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_727) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[6:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[28:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[6:0];
  _RAND_10 = {3{`RANDOM}};
  inflight = _RAND_10[95:0];
  _RAND_11 = {12{`RANDOM}};
  inflight_opcodes = _RAND_11[383:0];
  _RAND_12 = {12{`RANDOM}};
  inflight_sizes = _RAND_12[383:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {3{`RANDOM}};
  inflight_1 = _RAND_16[95:0];
  _RAND_17 = {12{`RANDOM}};
  inflight_sizes_1 = _RAND_17[383:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLUART_2(
  input         clock,
  input         reset,
  output        auto_int_xing_out_sync_0,
  output        auto_control_xing_in_a_ready,
  input         auto_control_xing_in_a_valid,
  input  [2:0]  auto_control_xing_in_a_bits_opcode,
  input  [2:0]  auto_control_xing_in_a_bits_param,
  input  [1:0]  auto_control_xing_in_a_bits_size,
  input  [6:0]  auto_control_xing_in_a_bits_source,
  input  [28:0] auto_control_xing_in_a_bits_address,
  input  [3:0]  auto_control_xing_in_a_bits_mask,
  input  [31:0] auto_control_xing_in_a_bits_data,
  input         auto_control_xing_in_a_bits_corrupt,
  input         auto_control_xing_in_d_ready,
  output        auto_control_xing_in_d_valid,
  output [2:0]  auto_control_xing_in_d_bits_opcode,
  output [1:0]  auto_control_xing_in_d_bits_size,
  output [6:0]  auto_control_xing_in_d_bits_source,
  output [31:0] auto_control_xing_in_d_bits_data,
  output        auto_io_out_txd,
  input         auto_io_out_rxd
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
`endif // RANDOMIZE_REG_INIT
  wire  buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
  wire [28:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
  wire [28:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
  wire  intsource_clock; // @[Crossing.scala 26:31]
  wire  intsource_reset; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_0; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_0; // @[Crossing.scala 26:31]
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  txm_clock; // @[UART.scala 79:19]
  wire  txm_reset; // @[UART.scala 79:19]
  wire  txm_io_en; // @[UART.scala 79:19]
  wire  txm_io_in_ready; // @[UART.scala 79:19]
  wire  txm_io_in_valid; // @[UART.scala 79:19]
  wire [7:0] txm_io_in_bits; // @[UART.scala 79:19]
  wire  txm_io_out; // @[UART.scala 79:19]
  wire [15:0] txm_io_div; // @[UART.scala 79:19]
  wire  txm_io_nstop; // @[UART.scala 79:19]
  wire  txq_clock; // @[UART.scala 80:19]
  wire  txq_reset; // @[UART.scala 80:19]
  wire  txq_io_enq_ready; // @[UART.scala 80:19]
  wire  txq_io_enq_valid; // @[UART.scala 80:19]
  wire [7:0] txq_io_enq_bits; // @[UART.scala 80:19]
  wire  txq_io_deq_ready; // @[UART.scala 80:19]
  wire  txq_io_deq_valid; // @[UART.scala 80:19]
  wire [7:0] txq_io_deq_bits; // @[UART.scala 80:19]
  wire [3:0] txq_io_count; // @[UART.scala 80:19]
  wire  rxm_clock; // @[UART.scala 82:19]
  wire  rxm_reset; // @[UART.scala 82:19]
  wire  rxm_io_en; // @[UART.scala 82:19]
  wire  rxm_io_in; // @[UART.scala 82:19]
  wire  rxm_io_out_valid; // @[UART.scala 82:19]
  wire [7:0] rxm_io_out_bits; // @[UART.scala 82:19]
  wire [15:0] rxm_io_div; // @[UART.scala 82:19]
  wire  rxq_clock; // @[UART.scala 83:19]
  wire  rxq_reset; // @[UART.scala 83:19]
  wire  rxq_io_enq_ready; // @[UART.scala 83:19]
  wire  rxq_io_enq_valid; // @[UART.scala 83:19]
  wire [7:0] rxq_io_enq_bits; // @[UART.scala 83:19]
  wire  rxq_io_deq_ready; // @[UART.scala 83:19]
  wire  rxq_io_deq_valid; // @[UART.scala 83:19]
  wire [7:0] rxq_io_deq_bits; // @[UART.scala 83:19]
  wire [3:0] rxq_io_count; // @[UART.scala 83:19]
  reg [15:0] div; // @[UART.scala 85:16]
  reg  txen; // @[UART.scala 91:17]
  reg  rxen; // @[UART.scala 92:17]
  reg [3:0] txwm; // @[UART.scala 99:17]
  reg [3:0] rxwm; // @[UART.scala 100:17]
  reg  nstop; // @[UART.scala 101:18]
  reg  ie_rxwm; // @[UART.scala 135:15]
  reg  ie_txwm; // @[UART.scala 135:15]
  wire  ip_txwm = txq_io_count < txwm; // @[UART.scala 138:28]
  wire  ip_rxwm = rxq_io_count > rxwm; // @[UART.scala 139:28]
  wire  _T = ~txq_io_enq_ready; // @[RegMapFIFO.scala 25:9]
  wire  _T_1 = ~rxq_io_deq_valid; // @[RegMapFIFO.scala 46:21]
  wire [2:0] bundleIn_0_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  in_bits_read = bundleIn_0_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 72:36]
  wire [28:0] bundleIn_0_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [9:0] in_bits_index = bundleIn_0_a_bits_address[11:2]; // @[RegisterRouter.scala 71:18 73:19]
  wire [9:0] out_findex = in_bits_index & 10'h3f8; // @[RegisterRouter.scala 83:24]
  wire  _out_T = out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [3:0] bundleIn_0_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [7:0] _out_frontMask_T_5 = bundleIn_0_a_bits_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_frontMask_T_7 = bundleIn_0_a_bits_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_frontMask_T_9 = bundleIn_0_a_bits_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_frontMask_T_11 = bundleIn_0_a_bits_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [31:0] out_frontMask = {_out_frontMask_T_11,_out_frontMask_T_9,_out_frontMask_T_7,_out_frontMask_T_5}; // @[Cat.scala 31:58]
  wire  out_rimask = |out_frontMask[7:0]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask = &out_frontMask[7:0]; // @[RegisterRouter.scala 83:24]
  wire  bundleIn_0_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  bundleIn_0_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [2:0] out_oindex = {in_bits_index[2],in_bits_index[1],in_bits_index[0]}; // @[Cat.scala 31:58]
  wire [7:0] _out_frontSel_T = 8'h1 << out_oindex; // @[OneHot.scala 57:35]
  wire  out_frontSel_0 = _out_frontSel_T[0]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_0 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_0 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala 83:24]
  wire [31:0] bundleIn_0_a_bits_data = buffer_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  out_womask_2 = &out_frontMask[31]; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_2 = out_wivalid_0 & out_womask_2; // @[RegisterRouter.scala 83:24]
  wire  quash = out_f_woready_2 & bundleIn_0_a_bits_data[31]; // @[RegMapFIFO.scala 27:26]
  wire [31:0] out_prepend_1 = {_T,31'h0}; // @[Cat.scala 31:58]
  wire  out_wimask_3 = &out_frontMask[0]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_4 = &out_frontMask[1]; // @[RegisterRouter.scala 83:24]
  wire [1:0] out_prepend_2 = {ip_rxwm,ip_txwm}; // @[Cat.scala 31:58]
  wire  out_frontSel_1 = _out_frontSel_T[1]; // @[RegisterRouter.scala 83:24]
  wire  out_rivalid_5 = bundleIn_0_a_valid & bundleIn_0_d_ready & in_bits_read & out_frontSel_1 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [7:0] _out_T_66 = rxq_io_deq_bits; // @[RegisterRouter.scala 83:24]
  wire [8:0] out_prepend_3 = {1'h0,_out_T_66}; // @[Cat.scala 31:58]
  wire [30:0] _out_T_75 = {{22'd0}, out_prepend_3}; // @[RegisterRouter.scala 83:24]
  wire [31:0] out_prepend_4 = {_T_1,_out_T_75}; // @[Cat.scala 31:58]
  wire  out_wimask_8 = &out_frontMask[15:0]; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_6 = _out_frontSel_T[6]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_8 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_6 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_2 = _out_frontSel_T[2]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_9 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_2 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_9 = out_wivalid_9 & out_wimask_3; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_10 = out_wivalid_9 & out_wimask_4; // @[RegisterRouter.scala 83:24]
  wire [1:0] out_prepend_5 = {nstop,txen}; // @[Cat.scala 31:58]
  wire  out_wimask_11 = &out_frontMask[19:16]; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_11 = out_wivalid_9 & out_wimask_11; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_prepend_T_6 = {{14'd0}, out_prepend_5}; // @[RegisterRouter.scala 83:24]
  wire [19:0] out_prepend_6 = {txwm,_out_prepend_T_6}; // @[Cat.scala 31:58]
  wire  out_frontSel_3 = _out_frontSel_T[3]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_12 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_3 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_12 = out_wivalid_12 & out_wimask_3; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_13 = out_wivalid_12 & out_wimask_11; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_prepend_T_7 = {{15'd0}, rxen}; // @[RegisterRouter.scala 83:24]
  wire [19:0] out_prepend_7 = {rxwm,_out_prepend_T_7}; // @[Cat.scala 31:58]
  wire  out_frontSel_4 = _out_frontSel_T[4]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_14 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_4 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_14 = out_wivalid_14 & out_wimask_3; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_15 = out_wivalid_14 & out_wimask_4; // @[RegisterRouter.scala 83:24]
  wire [1:0] out_prepend_8 = {ie_rxwm,ie_txwm}; // @[Cat.scala 31:58]
  wire  _GEN_41 = 3'h1 == out_oindex ? _out_T : _out_T; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_42 = 3'h2 == out_oindex ? _out_T : _GEN_41; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_43 = 3'h3 == out_oindex ? _out_T : _GEN_42; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_44 = 3'h4 == out_oindex ? _out_T : _GEN_43; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_45 = 3'h5 == out_oindex ? _out_T : _GEN_44; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_46 = 3'h6 == out_oindex ? _out_T : _GEN_45; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_47 = 3'h7 == out_oindex | _GEN_46; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_49 = 3'h1 == out_oindex ? out_prepend_4 : out_prepend_1; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_2 = {{12'd0}, out_prepend_6}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_50 = 3'h2 == out_oindex ? _out_out_bits_data_WIRE_1_2 : _GEN_49; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_3 = {{12'd0}, out_prepend_7}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_51 = 3'h3 == out_oindex ? _out_out_bits_data_WIRE_1_3 : _GEN_50; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_4 = {{30'd0}, out_prepend_8}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_52 = 3'h4 == out_oindex ? _out_out_bits_data_WIRE_1_4 : _GEN_51; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_5 = {{30'd0}, out_prepend_2}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_53 = 3'h5 == out_oindex ? _out_out_bits_data_WIRE_1_5 : _GEN_52; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_6 = {{16'd0}, div}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_54 = 3'h6 == out_oindex ? _out_out_bits_data_WIRE_1_6 : _GEN_53; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_55 = 3'h7 == out_oindex ? 32'h0 : _GEN_54; // @[MuxLiteral.scala 48:{10,10}]
  TLBuffer_13 buffer ( // @[Buffer.scala 68:28]
    .auto_in_a_ready(buffer_auto_in_a_ready),
    .auto_in_a_valid(buffer_auto_in_a_valid),
    .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
    .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
    .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
    .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
    .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
    .auto_in_a_bits_data(buffer_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
    .auto_in_d_ready(buffer_auto_in_d_ready),
    .auto_in_d_valid(buffer_auto_in_d_valid),
    .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
    .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
    .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
    .auto_out_a_ready(buffer_auto_out_a_ready),
    .auto_out_a_valid(buffer_auto_out_a_valid),
    .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
    .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
    .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
    .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
    .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
    .auto_out_a_bits_data(buffer_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
    .auto_out_d_ready(buffer_auto_out_d_ready),
    .auto_out_d_valid(buffer_auto_out_d_valid),
    .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
    .auto_out_d_bits_source(buffer_auto_out_d_bits_source),
    .auto_out_d_bits_data(buffer_auto_out_d_bits_data)
  );
  IntSyncCrossingSource_1 intsource ( // @[Crossing.scala 26:31]
    .clock(intsource_clock),
    .reset(intsource_reset),
    .auto_in_0(intsource_auto_in_0),
    .auto_out_sync_0(intsource_auto_out_sync_0)
  );
  TLMonitor_58 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  UARTTx txm ( // @[UART.scala 79:19]
    .clock(txm_clock),
    .reset(txm_reset),
    .io_en(txm_io_en),
    .io_in_ready(txm_io_in_ready),
    .io_in_valid(txm_io_in_valid),
    .io_in_bits(txm_io_in_bits),
    .io_out(txm_io_out),
    .io_div(txm_io_div),
    .io_nstop(txm_io_nstop)
  );
  QueueCompatibility txq ( // @[UART.scala 80:19]
    .clock(txq_clock),
    .reset(txq_reset),
    .io_enq_ready(txq_io_enq_ready),
    .io_enq_valid(txq_io_enq_valid),
    .io_enq_bits(txq_io_enq_bits),
    .io_deq_ready(txq_io_deq_ready),
    .io_deq_valid(txq_io_deq_valid),
    .io_deq_bits(txq_io_deq_bits),
    .io_count(txq_io_count)
  );
  UARTRx rxm ( // @[UART.scala 82:19]
    .clock(rxm_clock),
    .reset(rxm_reset),
    .io_en(rxm_io_en),
    .io_in(rxm_io_in),
    .io_out_valid(rxm_io_out_valid),
    .io_out_bits(rxm_io_out_bits),
    .io_div(rxm_io_div)
  );
  QueueCompatibility rxq ( // @[UART.scala 83:19]
    .clock(rxq_clock),
    .reset(rxq_reset),
    .io_enq_ready(rxq_io_enq_ready),
    .io_enq_valid(rxq_io_enq_valid),
    .io_enq_bits(rxq_io_enq_bits),
    .io_deq_ready(rxq_io_deq_ready),
    .io_deq_valid(rxq_io_deq_valid),
    .io_deq_bits(rxq_io_deq_bits),
    .io_count(rxq_io_count)
  );
  assign auto_int_xing_out_sync_0 = intsource_auto_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_in_a_ready = buffer_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_valid = buffer_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_size = buffer_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_source = buffer_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_data = buffer_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_io_out_txd = txm_io_out; // @[Nodes.scala 1207:84 UART.scala 113:12]
  assign buffer_auto_in_a_valid = auto_control_xing_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_opcode = auto_control_xing_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_param = auto_control_xing_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_size = auto_control_xing_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_source = auto_control_xing_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_address = auto_control_xing_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_mask = auto_control_xing_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_data = auto_control_xing_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_corrupt = auto_control_xing_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_d_ready = auto_control_xing_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_out_a_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign buffer_auto_out_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_data = _GEN_47 ? _GEN_55 : 32'h0; // @[RegisterRouter.scala 83:24]
  assign intsource_clock = clock;
  assign intsource_reset = reset;
  assign intsource_auto_in_0 = ip_txwm & ie_txwm | ip_rxwm & ie_rxwm; // @[UART.scala 140:41]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_param = buffer_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign monitor_io_in_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign txm_clock = clock;
  assign txm_reset = reset;
  assign txm_io_en = txen; // @[UART.scala 109:15]
  assign txm_io_in_valid = txq_io_deq_valid; // @[UART.scala 110:13]
  assign txm_io_in_bits = txq_io_deq_bits; // @[UART.scala 110:13]
  assign txm_io_div = div; // @[UART.scala 111:14]
  assign txm_io_nstop = nstop; // @[UART.scala 112:16]
  assign txq_clock = clock;
  assign txq_reset = reset;
  assign txq_io_enq_valid = out_f_wivalid & ~quash; // @[RegMapFIFO.scala 19:30]
  assign txq_io_enq_bits = bundleIn_0_a_bits_data[7:0]; // @[RegisterRouter.scala 83:24]
  assign txq_io_deq_ready = txm_io_in_ready; // @[UART.scala 110:13]
  assign rxm_clock = clock;
  assign rxm_reset = reset;
  assign rxm_io_en = rxen; // @[UART.scala 120:13]
  assign rxm_io_in = auto_io_out_rxd; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign rxm_io_div = div; // @[UART.scala 123:14]
  assign rxq_clock = clock;
  assign rxq_reset = reset;
  assign rxq_io_enq_valid = rxm_io_out_valid; // @[UART.scala 122:14]
  assign rxq_io_enq_bits = rxm_io_out_bits; // @[UART.scala 122:14]
  assign rxq_io_deq_ready = out_rivalid_5 & out_rimask; // @[RegisterRouter.scala 83:24]
  always @(posedge clock) begin
    if (reset) begin // @[UART.scala 85:16]
      div <= 16'h364; // @[UART.scala 85:16]
    end else if (out_f_wivalid_8) begin // @[RegField.scala 74:88]
      div <= bundleIn_0_a_bits_data[15:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[UART.scala 91:17]
      txen <= 1'h0; // @[UART.scala 91:17]
    end else if (out_f_wivalid_9) begin // @[RegField.scala 74:88]
      txen <= bundleIn_0_a_bits_data[0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[UART.scala 92:17]
      rxen <= 1'h0; // @[UART.scala 92:17]
    end else if (out_f_wivalid_12) begin // @[RegField.scala 74:88]
      rxen <= bundleIn_0_a_bits_data[0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[UART.scala 99:17]
      txwm <= 4'h0; // @[UART.scala 99:17]
    end else if (out_f_wivalid_11) begin // @[RegField.scala 74:88]
      txwm <= bundleIn_0_a_bits_data[19:16]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[UART.scala 100:17]
      rxwm <= 4'h0; // @[UART.scala 100:17]
    end else if (out_f_wivalid_13) begin // @[RegField.scala 74:88]
      rxwm <= bundleIn_0_a_bits_data[19:16]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[UART.scala 101:18]
      nstop <= 1'h0; // @[UART.scala 101:18]
    end else if (out_f_wivalid_10) begin // @[RegField.scala 74:88]
      nstop <= bundleIn_0_a_bits_data[1]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[UART.scala 135:15]
      ie_rxwm <= 1'h0; // @[UART.scala 135:15]
    end else if (out_f_wivalid_15) begin // @[RegField.scala 74:88]
      ie_rxwm <= bundleIn_0_a_bits_data[1]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[UART.scala 135:15]
      ie_txwm <= 1'h0; // @[UART.scala 135:15]
    end else if (out_f_wivalid_14) begin // @[RegField.scala 74:88]
      ie_txwm <= bundleIn_0_a_bits_data[0]; // @[RegField.scala 74:92]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  div = _RAND_0[15:0];
  _RAND_1 = {1{`RANDOM}};
  txen = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  rxen = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  txwm = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  rxwm = _RAND_4[3:0];
  _RAND_5 = {1{`RANDOM}};
  nstop = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  ie_rxwm = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  ie_txwm = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ClockSinkDomain_3(
  output        auto_uart_2_int_xing_out_sync_0,
  output        auto_uart_2_control_xing_in_a_ready,
  input         auto_uart_2_control_xing_in_a_valid,
  input  [2:0]  auto_uart_2_control_xing_in_a_bits_opcode,
  input  [2:0]  auto_uart_2_control_xing_in_a_bits_param,
  input  [1:0]  auto_uart_2_control_xing_in_a_bits_size,
  input  [6:0]  auto_uart_2_control_xing_in_a_bits_source,
  input  [28:0] auto_uart_2_control_xing_in_a_bits_address,
  input  [3:0]  auto_uart_2_control_xing_in_a_bits_mask,
  input  [31:0] auto_uart_2_control_xing_in_a_bits_data,
  input         auto_uart_2_control_xing_in_a_bits_corrupt,
  input         auto_uart_2_control_xing_in_d_ready,
  output        auto_uart_2_control_xing_in_d_valid,
  output [2:0]  auto_uart_2_control_xing_in_d_bits_opcode,
  output [1:0]  auto_uart_2_control_xing_in_d_bits_size,
  output [6:0]  auto_uart_2_control_xing_in_d_bits_source,
  output [31:0] auto_uart_2_control_xing_in_d_bits_data,
  output        auto_uart_2_io_out_txd,
  input         auto_uart_2_io_out_rxd,
  input         auto_clock_in_clock,
  input         auto_clock_in_reset
);
  wire  uart_2_clock; // @[UART.scala 243:51]
  wire  uart_2_reset; // @[UART.scala 243:51]
  wire  uart_2_auto_int_xing_out_sync_0; // @[UART.scala 243:51]
  wire  uart_2_auto_control_xing_in_a_ready; // @[UART.scala 243:51]
  wire  uart_2_auto_control_xing_in_a_valid; // @[UART.scala 243:51]
  wire [2:0] uart_2_auto_control_xing_in_a_bits_opcode; // @[UART.scala 243:51]
  wire [2:0] uart_2_auto_control_xing_in_a_bits_param; // @[UART.scala 243:51]
  wire [1:0] uart_2_auto_control_xing_in_a_bits_size; // @[UART.scala 243:51]
  wire [6:0] uart_2_auto_control_xing_in_a_bits_source; // @[UART.scala 243:51]
  wire [28:0] uart_2_auto_control_xing_in_a_bits_address; // @[UART.scala 243:51]
  wire [3:0] uart_2_auto_control_xing_in_a_bits_mask; // @[UART.scala 243:51]
  wire [31:0] uart_2_auto_control_xing_in_a_bits_data; // @[UART.scala 243:51]
  wire  uart_2_auto_control_xing_in_a_bits_corrupt; // @[UART.scala 243:51]
  wire  uart_2_auto_control_xing_in_d_ready; // @[UART.scala 243:51]
  wire  uart_2_auto_control_xing_in_d_valid; // @[UART.scala 243:51]
  wire [2:0] uart_2_auto_control_xing_in_d_bits_opcode; // @[UART.scala 243:51]
  wire [1:0] uart_2_auto_control_xing_in_d_bits_size; // @[UART.scala 243:51]
  wire [6:0] uart_2_auto_control_xing_in_d_bits_source; // @[UART.scala 243:51]
  wire [31:0] uart_2_auto_control_xing_in_d_bits_data; // @[UART.scala 243:51]
  wire  uart_2_auto_io_out_txd; // @[UART.scala 243:51]
  wire  uart_2_auto_io_out_rxd; // @[UART.scala 243:51]
  TLUART_2 uart_2 ( // @[UART.scala 243:51]
    .clock(uart_2_clock),
    .reset(uart_2_reset),
    .auto_int_xing_out_sync_0(uart_2_auto_int_xing_out_sync_0),
    .auto_control_xing_in_a_ready(uart_2_auto_control_xing_in_a_ready),
    .auto_control_xing_in_a_valid(uart_2_auto_control_xing_in_a_valid),
    .auto_control_xing_in_a_bits_opcode(uart_2_auto_control_xing_in_a_bits_opcode),
    .auto_control_xing_in_a_bits_param(uart_2_auto_control_xing_in_a_bits_param),
    .auto_control_xing_in_a_bits_size(uart_2_auto_control_xing_in_a_bits_size),
    .auto_control_xing_in_a_bits_source(uart_2_auto_control_xing_in_a_bits_source),
    .auto_control_xing_in_a_bits_address(uart_2_auto_control_xing_in_a_bits_address),
    .auto_control_xing_in_a_bits_mask(uart_2_auto_control_xing_in_a_bits_mask),
    .auto_control_xing_in_a_bits_data(uart_2_auto_control_xing_in_a_bits_data),
    .auto_control_xing_in_a_bits_corrupt(uart_2_auto_control_xing_in_a_bits_corrupt),
    .auto_control_xing_in_d_ready(uart_2_auto_control_xing_in_d_ready),
    .auto_control_xing_in_d_valid(uart_2_auto_control_xing_in_d_valid),
    .auto_control_xing_in_d_bits_opcode(uart_2_auto_control_xing_in_d_bits_opcode),
    .auto_control_xing_in_d_bits_size(uart_2_auto_control_xing_in_d_bits_size),
    .auto_control_xing_in_d_bits_source(uart_2_auto_control_xing_in_d_bits_source),
    .auto_control_xing_in_d_bits_data(uart_2_auto_control_xing_in_d_bits_data),
    .auto_io_out_txd(uart_2_auto_io_out_txd),
    .auto_io_out_rxd(uart_2_auto_io_out_rxd)
  );
  assign auto_uart_2_int_xing_out_sync_0 = uart_2_auto_int_xing_out_sync_0; // @[LazyModule.scala 311:12]
  assign auto_uart_2_control_xing_in_a_ready = uart_2_auto_control_xing_in_a_ready; // @[LazyModule.scala 309:16]
  assign auto_uart_2_control_xing_in_d_valid = uart_2_auto_control_xing_in_d_valid; // @[LazyModule.scala 309:16]
  assign auto_uart_2_control_xing_in_d_bits_opcode = uart_2_auto_control_xing_in_d_bits_opcode; // @[LazyModule.scala 309:16]
  assign auto_uart_2_control_xing_in_d_bits_size = uart_2_auto_control_xing_in_d_bits_size; // @[LazyModule.scala 309:16]
  assign auto_uart_2_control_xing_in_d_bits_source = uart_2_auto_control_xing_in_d_bits_source; // @[LazyModule.scala 309:16]
  assign auto_uart_2_control_xing_in_d_bits_data = uart_2_auto_control_xing_in_d_bits_data; // @[LazyModule.scala 309:16]
  assign auto_uart_2_io_out_txd = uart_2_auto_io_out_txd; // @[LazyModule.scala 311:12]
  assign uart_2_clock = auto_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign uart_2_reset = auto_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign uart_2_auto_control_xing_in_a_valid = auto_uart_2_control_xing_in_a_valid; // @[LazyModule.scala 309:16]
  assign uart_2_auto_control_xing_in_a_bits_opcode = auto_uart_2_control_xing_in_a_bits_opcode; // @[LazyModule.scala 309:16]
  assign uart_2_auto_control_xing_in_a_bits_param = auto_uart_2_control_xing_in_a_bits_param; // @[LazyModule.scala 309:16]
  assign uart_2_auto_control_xing_in_a_bits_size = auto_uart_2_control_xing_in_a_bits_size; // @[LazyModule.scala 309:16]
  assign uart_2_auto_control_xing_in_a_bits_source = auto_uart_2_control_xing_in_a_bits_source; // @[LazyModule.scala 309:16]
  assign uart_2_auto_control_xing_in_a_bits_address = auto_uart_2_control_xing_in_a_bits_address; // @[LazyModule.scala 309:16]
  assign uart_2_auto_control_xing_in_a_bits_mask = auto_uart_2_control_xing_in_a_bits_mask; // @[LazyModule.scala 309:16]
  assign uart_2_auto_control_xing_in_a_bits_data = auto_uart_2_control_xing_in_a_bits_data; // @[LazyModule.scala 309:16]
  assign uart_2_auto_control_xing_in_a_bits_corrupt = auto_uart_2_control_xing_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
  assign uart_2_auto_control_xing_in_d_ready = auto_uart_2_control_xing_in_d_ready; // @[LazyModule.scala 309:16]
  assign uart_2_auto_io_out_rxd = auto_uart_2_io_out_rxd; // @[LazyModule.scala 311:12]
endmodule
module TLMonitor_59(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [1:0]  io_in_a_bits_size,
  input  [6:0]  io_in_a_bits_source,
  input  [28:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_size,
  input  [6:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [95:0] _RAND_10;
  reg [383:0] _RAND_11;
  reg [383:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [95:0] _RAND_16;
  reg [383:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T_4 = io_in_a_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire [4:0] _is_aligned_mask_T_1 = 5'h3 << io_in_a_bits_size; // @[package.scala 234:77]
  wire [1:0] is_aligned_mask = ~_is_aligned_mask_T_1[1:0]; // @[package.scala 234:46]
  wire [28:0] _GEN_71 = {{27'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 2'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [28:0] _T_33 = io_in_a_bits_address ^ 29'h10043000; // @[Parameters.scala 137:31]
  wire [29:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
  wire [29:0] _T_36 = $signed(_T_34) & -30'sh1000; // @[Parameters.scala 137:52]
  wire  _T_37 = $signed(_T_36) == 30'sh0; // @[Parameters.scala 137:67]
  wire  _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_74 = _T_73 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_164 = io_in_a_bits_size <= 2'h2; // @[Parameters.scala 92:42]
  wire  _T_172 = _T_164 & _T_37; // @[Parameters.scala 670:56]
  wire  _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_218 = _source_ok_T_4 & _T_172; // @[Monitor.scala 115:71]
  wire  _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_273 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_274 = io_in_a_bits_mask & _T_273; // @[Monitor.scala 127:31]
  wire  _T_275 = _T_274 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_279 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_347 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_355 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_385 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_397 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_10 = io_in_d_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire  _T_401 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_405 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 312:27]
  wire  _T_421 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_449 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_478 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_495 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_513 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [1:0] size; // @[Monitor.scala 386:22]
  reg [6:0] source; // @[Monitor.scala 387:22]
  reg [28:0] address; // @[Monitor.scala 388:22]
  wire  _T_543 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_544 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_548 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_552 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_556 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_560 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] size_1; // @[Monitor.scala 537:22]
  reg [6:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_567 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_568 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_576 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_580 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [95:0] inflight; // @[Monitor.scala 611:27]
  reg [383:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [383:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [8:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [9:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [383:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [383:0] _GEN_73 = {{368'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[383:1]}; // @[Monitor.scala 634:152]
  wire [383:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [383:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
  wire [383:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[383:1]}; // @[Monitor.scala 638:144]
  wire  _T_594 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [127:0] _a_set_wo_ready_T = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_597 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
  wire [8:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [9:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [1026:0] _GEN_1 = {{1023'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [1026:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
  wire [1025:0] _GEN_2 = {{1023'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [1025:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [95:0] _T_599 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_601 = ~_T_599[0]; // @[Monitor.scala 658:17]
  wire [127:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 652:72 653:28]
  wire [1026:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 1027'h0; // @[Monitor.scala 652:72 656:28]
  wire [1025:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 1026'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_605 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_607 = ~_T_401; // @[Monitor.scala 671:74]
  wire  _T_608 = io_in_d_valid & d_first_1 & ~_T_401; // @[Monitor.scala 671:71]
  wire [127:0] _d_clr_wo_ready_T = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [1038:0] _GEN_3 = {{1023'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [1038:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [127:0] _GEN_22 = d_first_done & d_first_1 & _T_607 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 675:91 676:21]
  wire [1038:0] _GEN_23 = d_first_done & d_first_1 & _T_607 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_594 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [95:0] _T_618 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_620 = _T_618[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_625 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_626 = io_in_d_bits_opcode == _GEN_32 | _T_625; // @[Monitor.scala 685:77]
  wire  _T_630 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_637 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_638 = io_in_d_bits_opcode == _GEN_48 | _T_637; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_642 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_652 = _T_605 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_607; // @[Monitor.scala 694:116]
  wire  _T_654 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [95:0] a_set = _GEN_16[95:0];
  wire [95:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [95:0] d_clr = _GEN_22[95:0];
  wire [95:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [95:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [383:0] a_opcodes_set = _GEN_19[383:0];
  wire [383:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [383:0] d_opcodes_clr = _GEN_23[383:0];
  wire [383:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [383:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [383:0] a_sizes_set = _GEN_20[383:0];
  wire [383:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [383:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_663 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [95:0] inflight_1; // @[Monitor.scala 723:35]
  reg [383:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [383:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [383:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
  wire [383:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[383:1]}; // @[Monitor.scala 747:146]
  wire  _T_689 = io_in_d_valid & d_first_2 & _T_401; // @[Monitor.scala 779:71]
  wire [127:0] _GEN_67 = d_first_done & d_first_2 & _T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 783:90 784:21]
  wire [1038:0] _GEN_68 = d_first_done & d_first_2 & _T_401 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 783:90 785:21]
  wire [95:0] _T_697 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_707 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [95:0] d_clr_1 = _GEN_67[95:0];
  wire [95:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [95:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [383:0] d_opcodes_clr_1 = _GEN_68[383:0];
  wire [383:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [383:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_727 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 1'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= 1'h0;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 96'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 384'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 384'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 1'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= 1'h0;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 96'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 384'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= 1'h0;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (d_first_done) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_172 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_172) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_275 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_275) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_309 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_309) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_347 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_347) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_385 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_397 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_397) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_478 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_478 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_495 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_495 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_513 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_513 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_544 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_544) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_548 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_548) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_552 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_552) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_556 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_556) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_560 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_560) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_568 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_568) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_576 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_576) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_580 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_580) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_601 & (_T_597 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_597 & ~reset & ~_T_601) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_620 & (_T_608 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & _T_2 & ~_T_620) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_626 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_626) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_630 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_630) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_638 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_638) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_642 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_642) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_654 & (_T_652 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_652 & _T_2 & ~_T_654) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_663 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_663) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_697[0] & (_T_689 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_689 & _T_2 & ~_T_697[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_707 & (_T_689 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_689 & _T_2 & ~_T_707) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_727 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_727) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[6:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[28:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[6:0];
  _RAND_10 = {3{`RANDOM}};
  inflight = _RAND_10[95:0];
  _RAND_11 = {12{`RANDOM}};
  inflight_opcodes = _RAND_11[383:0];
  _RAND_12 = {12{`RANDOM}};
  inflight_sizes = _RAND_12[383:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {3{`RANDOM}};
  inflight_1 = _RAND_16[95:0];
  _RAND_17 = {12{`RANDOM}};
  inflight_sizes_1 = _RAND_17[383:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLUART_3(
  input         clock,
  input         reset,
  output        auto_int_xing_out_sync_0,
  output        auto_control_xing_in_a_ready,
  input         auto_control_xing_in_a_valid,
  input  [2:0]  auto_control_xing_in_a_bits_opcode,
  input  [2:0]  auto_control_xing_in_a_bits_param,
  input  [1:0]  auto_control_xing_in_a_bits_size,
  input  [6:0]  auto_control_xing_in_a_bits_source,
  input  [28:0] auto_control_xing_in_a_bits_address,
  input  [3:0]  auto_control_xing_in_a_bits_mask,
  input  [31:0] auto_control_xing_in_a_bits_data,
  input         auto_control_xing_in_a_bits_corrupt,
  input         auto_control_xing_in_d_ready,
  output        auto_control_xing_in_d_valid,
  output [2:0]  auto_control_xing_in_d_bits_opcode,
  output [1:0]  auto_control_xing_in_d_bits_size,
  output [6:0]  auto_control_xing_in_d_bits_source,
  output [31:0] auto_control_xing_in_d_bits_data,
  output        auto_io_out_txd,
  input         auto_io_out_rxd
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
`endif // RANDOMIZE_REG_INIT
  wire  buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
  wire [28:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
  wire [28:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
  wire  intsource_clock; // @[Crossing.scala 26:31]
  wire  intsource_reset; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_0; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_0; // @[Crossing.scala 26:31]
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  txm_clock; // @[UART.scala 79:19]
  wire  txm_reset; // @[UART.scala 79:19]
  wire  txm_io_en; // @[UART.scala 79:19]
  wire  txm_io_in_ready; // @[UART.scala 79:19]
  wire  txm_io_in_valid; // @[UART.scala 79:19]
  wire [7:0] txm_io_in_bits; // @[UART.scala 79:19]
  wire  txm_io_out; // @[UART.scala 79:19]
  wire [15:0] txm_io_div; // @[UART.scala 79:19]
  wire  txm_io_nstop; // @[UART.scala 79:19]
  wire  txq_clock; // @[UART.scala 80:19]
  wire  txq_reset; // @[UART.scala 80:19]
  wire  txq_io_enq_ready; // @[UART.scala 80:19]
  wire  txq_io_enq_valid; // @[UART.scala 80:19]
  wire [7:0] txq_io_enq_bits; // @[UART.scala 80:19]
  wire  txq_io_deq_ready; // @[UART.scala 80:19]
  wire  txq_io_deq_valid; // @[UART.scala 80:19]
  wire [7:0] txq_io_deq_bits; // @[UART.scala 80:19]
  wire [3:0] txq_io_count; // @[UART.scala 80:19]
  wire  rxm_clock; // @[UART.scala 82:19]
  wire  rxm_reset; // @[UART.scala 82:19]
  wire  rxm_io_en; // @[UART.scala 82:19]
  wire  rxm_io_in; // @[UART.scala 82:19]
  wire  rxm_io_out_valid; // @[UART.scala 82:19]
  wire [7:0] rxm_io_out_bits; // @[UART.scala 82:19]
  wire [15:0] rxm_io_div; // @[UART.scala 82:19]
  wire  rxq_clock; // @[UART.scala 83:19]
  wire  rxq_reset; // @[UART.scala 83:19]
  wire  rxq_io_enq_ready; // @[UART.scala 83:19]
  wire  rxq_io_enq_valid; // @[UART.scala 83:19]
  wire [7:0] rxq_io_enq_bits; // @[UART.scala 83:19]
  wire  rxq_io_deq_ready; // @[UART.scala 83:19]
  wire  rxq_io_deq_valid; // @[UART.scala 83:19]
  wire [7:0] rxq_io_deq_bits; // @[UART.scala 83:19]
  wire [3:0] rxq_io_count; // @[UART.scala 83:19]
  reg [15:0] div; // @[UART.scala 85:16]
  reg  txen; // @[UART.scala 91:17]
  reg  rxen; // @[UART.scala 92:17]
  reg [3:0] txwm; // @[UART.scala 99:17]
  reg [3:0] rxwm; // @[UART.scala 100:17]
  reg  nstop; // @[UART.scala 101:18]
  reg  ie_rxwm; // @[UART.scala 135:15]
  reg  ie_txwm; // @[UART.scala 135:15]
  wire  ip_txwm = txq_io_count < txwm; // @[UART.scala 138:28]
  wire  ip_rxwm = rxq_io_count > rxwm; // @[UART.scala 139:28]
  wire  _T = ~txq_io_enq_ready; // @[RegMapFIFO.scala 25:9]
  wire  _T_1 = ~rxq_io_deq_valid; // @[RegMapFIFO.scala 46:21]
  wire [2:0] bundleIn_0_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  in_bits_read = bundleIn_0_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 72:36]
  wire [28:0] bundleIn_0_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [9:0] in_bits_index = bundleIn_0_a_bits_address[11:2]; // @[RegisterRouter.scala 71:18 73:19]
  wire [9:0] out_findex = in_bits_index & 10'h3f8; // @[RegisterRouter.scala 83:24]
  wire  _out_T = out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [3:0] bundleIn_0_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [7:0] _out_frontMask_T_5 = bundleIn_0_a_bits_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_frontMask_T_7 = bundleIn_0_a_bits_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_frontMask_T_9 = bundleIn_0_a_bits_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_frontMask_T_11 = bundleIn_0_a_bits_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [31:0] out_frontMask = {_out_frontMask_T_11,_out_frontMask_T_9,_out_frontMask_T_7,_out_frontMask_T_5}; // @[Cat.scala 31:58]
  wire  out_rimask = |out_frontMask[7:0]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask = &out_frontMask[7:0]; // @[RegisterRouter.scala 83:24]
  wire  bundleIn_0_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  bundleIn_0_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [2:0] out_oindex = {in_bits_index[2],in_bits_index[1],in_bits_index[0]}; // @[Cat.scala 31:58]
  wire [7:0] _out_frontSel_T = 8'h1 << out_oindex; // @[OneHot.scala 57:35]
  wire  out_frontSel_0 = _out_frontSel_T[0]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_0 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_0 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala 83:24]
  wire [31:0] bundleIn_0_a_bits_data = buffer_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  out_womask_2 = &out_frontMask[31]; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_2 = out_wivalid_0 & out_womask_2; // @[RegisterRouter.scala 83:24]
  wire  quash = out_f_woready_2 & bundleIn_0_a_bits_data[31]; // @[RegMapFIFO.scala 27:26]
  wire [31:0] out_prepend_1 = {_T,31'h0}; // @[Cat.scala 31:58]
  wire  out_wimask_3 = &out_frontMask[0]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_4 = &out_frontMask[1]; // @[RegisterRouter.scala 83:24]
  wire [1:0] out_prepend_2 = {ip_rxwm,ip_txwm}; // @[Cat.scala 31:58]
  wire  out_frontSel_1 = _out_frontSel_T[1]; // @[RegisterRouter.scala 83:24]
  wire  out_rivalid_5 = bundleIn_0_a_valid & bundleIn_0_d_ready & in_bits_read & out_frontSel_1 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [7:0] _out_T_66 = rxq_io_deq_bits; // @[RegisterRouter.scala 83:24]
  wire [8:0] out_prepend_3 = {1'h0,_out_T_66}; // @[Cat.scala 31:58]
  wire [30:0] _out_T_75 = {{22'd0}, out_prepend_3}; // @[RegisterRouter.scala 83:24]
  wire [31:0] out_prepend_4 = {_T_1,_out_T_75}; // @[Cat.scala 31:58]
  wire  out_wimask_8 = &out_frontMask[15:0]; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_6 = _out_frontSel_T[6]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_8 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_6 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_2 = _out_frontSel_T[2]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_9 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_2 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_9 = out_wivalid_9 & out_wimask_3; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_10 = out_wivalid_9 & out_wimask_4; // @[RegisterRouter.scala 83:24]
  wire [1:0] out_prepend_5 = {nstop,txen}; // @[Cat.scala 31:58]
  wire  out_wimask_11 = &out_frontMask[19:16]; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_11 = out_wivalid_9 & out_wimask_11; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_prepend_T_6 = {{14'd0}, out_prepend_5}; // @[RegisterRouter.scala 83:24]
  wire [19:0] out_prepend_6 = {txwm,_out_prepend_T_6}; // @[Cat.scala 31:58]
  wire  out_frontSel_3 = _out_frontSel_T[3]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_12 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_3 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_12 = out_wivalid_12 & out_wimask_3; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_13 = out_wivalid_12 & out_wimask_11; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_prepend_T_7 = {{15'd0}, rxen}; // @[RegisterRouter.scala 83:24]
  wire [19:0] out_prepend_7 = {rxwm,_out_prepend_T_7}; // @[Cat.scala 31:58]
  wire  out_frontSel_4 = _out_frontSel_T[4]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_14 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_4 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_14 = out_wivalid_14 & out_wimask_3; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_15 = out_wivalid_14 & out_wimask_4; // @[RegisterRouter.scala 83:24]
  wire [1:0] out_prepend_8 = {ie_rxwm,ie_txwm}; // @[Cat.scala 31:58]
  wire  _GEN_41 = 3'h1 == out_oindex ? _out_T : _out_T; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_42 = 3'h2 == out_oindex ? _out_T : _GEN_41; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_43 = 3'h3 == out_oindex ? _out_T : _GEN_42; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_44 = 3'h4 == out_oindex ? _out_T : _GEN_43; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_45 = 3'h5 == out_oindex ? _out_T : _GEN_44; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_46 = 3'h6 == out_oindex ? _out_T : _GEN_45; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_47 = 3'h7 == out_oindex | _GEN_46; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_49 = 3'h1 == out_oindex ? out_prepend_4 : out_prepend_1; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_2 = {{12'd0}, out_prepend_6}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_50 = 3'h2 == out_oindex ? _out_out_bits_data_WIRE_1_2 : _GEN_49; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_3 = {{12'd0}, out_prepend_7}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_51 = 3'h3 == out_oindex ? _out_out_bits_data_WIRE_1_3 : _GEN_50; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_4 = {{30'd0}, out_prepend_8}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_52 = 3'h4 == out_oindex ? _out_out_bits_data_WIRE_1_4 : _GEN_51; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_5 = {{30'd0}, out_prepend_2}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_53 = 3'h5 == out_oindex ? _out_out_bits_data_WIRE_1_5 : _GEN_52; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_6 = {{16'd0}, div}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_54 = 3'h6 == out_oindex ? _out_out_bits_data_WIRE_1_6 : _GEN_53; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_55 = 3'h7 == out_oindex ? 32'h0 : _GEN_54; // @[MuxLiteral.scala 48:{10,10}]
  TLBuffer_13 buffer ( // @[Buffer.scala 68:28]
    .auto_in_a_ready(buffer_auto_in_a_ready),
    .auto_in_a_valid(buffer_auto_in_a_valid),
    .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
    .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
    .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
    .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
    .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
    .auto_in_a_bits_data(buffer_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
    .auto_in_d_ready(buffer_auto_in_d_ready),
    .auto_in_d_valid(buffer_auto_in_d_valid),
    .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
    .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
    .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
    .auto_out_a_ready(buffer_auto_out_a_ready),
    .auto_out_a_valid(buffer_auto_out_a_valid),
    .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
    .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
    .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
    .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
    .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
    .auto_out_a_bits_data(buffer_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
    .auto_out_d_ready(buffer_auto_out_d_ready),
    .auto_out_d_valid(buffer_auto_out_d_valid),
    .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
    .auto_out_d_bits_source(buffer_auto_out_d_bits_source),
    .auto_out_d_bits_data(buffer_auto_out_d_bits_data)
  );
  IntSyncCrossingSource_1 intsource ( // @[Crossing.scala 26:31]
    .clock(intsource_clock),
    .reset(intsource_reset),
    .auto_in_0(intsource_auto_in_0),
    .auto_out_sync_0(intsource_auto_out_sync_0)
  );
  TLMonitor_59 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  UARTTx txm ( // @[UART.scala 79:19]
    .clock(txm_clock),
    .reset(txm_reset),
    .io_en(txm_io_en),
    .io_in_ready(txm_io_in_ready),
    .io_in_valid(txm_io_in_valid),
    .io_in_bits(txm_io_in_bits),
    .io_out(txm_io_out),
    .io_div(txm_io_div),
    .io_nstop(txm_io_nstop)
  );
  QueueCompatibility txq ( // @[UART.scala 80:19]
    .clock(txq_clock),
    .reset(txq_reset),
    .io_enq_ready(txq_io_enq_ready),
    .io_enq_valid(txq_io_enq_valid),
    .io_enq_bits(txq_io_enq_bits),
    .io_deq_ready(txq_io_deq_ready),
    .io_deq_valid(txq_io_deq_valid),
    .io_deq_bits(txq_io_deq_bits),
    .io_count(txq_io_count)
  );
  UARTRx rxm ( // @[UART.scala 82:19]
    .clock(rxm_clock),
    .reset(rxm_reset),
    .io_en(rxm_io_en),
    .io_in(rxm_io_in),
    .io_out_valid(rxm_io_out_valid),
    .io_out_bits(rxm_io_out_bits),
    .io_div(rxm_io_div)
  );
  QueueCompatibility rxq ( // @[UART.scala 83:19]
    .clock(rxq_clock),
    .reset(rxq_reset),
    .io_enq_ready(rxq_io_enq_ready),
    .io_enq_valid(rxq_io_enq_valid),
    .io_enq_bits(rxq_io_enq_bits),
    .io_deq_ready(rxq_io_deq_ready),
    .io_deq_valid(rxq_io_deq_valid),
    .io_deq_bits(rxq_io_deq_bits),
    .io_count(rxq_io_count)
  );
  assign auto_int_xing_out_sync_0 = intsource_auto_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_in_a_ready = buffer_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_valid = buffer_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_size = buffer_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_source = buffer_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_data = buffer_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_io_out_txd = txm_io_out; // @[Nodes.scala 1207:84 UART.scala 113:12]
  assign buffer_auto_in_a_valid = auto_control_xing_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_opcode = auto_control_xing_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_param = auto_control_xing_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_size = auto_control_xing_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_source = auto_control_xing_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_address = auto_control_xing_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_mask = auto_control_xing_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_data = auto_control_xing_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_corrupt = auto_control_xing_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_d_ready = auto_control_xing_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_out_a_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign buffer_auto_out_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_data = _GEN_47 ? _GEN_55 : 32'h0; // @[RegisterRouter.scala 83:24]
  assign intsource_clock = clock;
  assign intsource_reset = reset;
  assign intsource_auto_in_0 = ip_txwm & ie_txwm | ip_rxwm & ie_rxwm; // @[UART.scala 140:41]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_param = buffer_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign monitor_io_in_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign txm_clock = clock;
  assign txm_reset = reset;
  assign txm_io_en = txen; // @[UART.scala 109:15]
  assign txm_io_in_valid = txq_io_deq_valid; // @[UART.scala 110:13]
  assign txm_io_in_bits = txq_io_deq_bits; // @[UART.scala 110:13]
  assign txm_io_div = div; // @[UART.scala 111:14]
  assign txm_io_nstop = nstop; // @[UART.scala 112:16]
  assign txq_clock = clock;
  assign txq_reset = reset;
  assign txq_io_enq_valid = out_f_wivalid & ~quash; // @[RegMapFIFO.scala 19:30]
  assign txq_io_enq_bits = bundleIn_0_a_bits_data[7:0]; // @[RegisterRouter.scala 83:24]
  assign txq_io_deq_ready = txm_io_in_ready; // @[UART.scala 110:13]
  assign rxm_clock = clock;
  assign rxm_reset = reset;
  assign rxm_io_en = rxen; // @[UART.scala 120:13]
  assign rxm_io_in = auto_io_out_rxd; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign rxm_io_div = div; // @[UART.scala 123:14]
  assign rxq_clock = clock;
  assign rxq_reset = reset;
  assign rxq_io_enq_valid = rxm_io_out_valid; // @[UART.scala 122:14]
  assign rxq_io_enq_bits = rxm_io_out_bits; // @[UART.scala 122:14]
  assign rxq_io_deq_ready = out_rivalid_5 & out_rimask; // @[RegisterRouter.scala 83:24]
  always @(posedge clock) begin
    if (reset) begin // @[UART.scala 85:16]
      div <= 16'h364; // @[UART.scala 85:16]
    end else if (out_f_wivalid_8) begin // @[RegField.scala 74:88]
      div <= bundleIn_0_a_bits_data[15:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[UART.scala 91:17]
      txen <= 1'h0; // @[UART.scala 91:17]
    end else if (out_f_wivalid_9) begin // @[RegField.scala 74:88]
      txen <= bundleIn_0_a_bits_data[0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[UART.scala 92:17]
      rxen <= 1'h0; // @[UART.scala 92:17]
    end else if (out_f_wivalid_12) begin // @[RegField.scala 74:88]
      rxen <= bundleIn_0_a_bits_data[0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[UART.scala 99:17]
      txwm <= 4'h0; // @[UART.scala 99:17]
    end else if (out_f_wivalid_11) begin // @[RegField.scala 74:88]
      txwm <= bundleIn_0_a_bits_data[19:16]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[UART.scala 100:17]
      rxwm <= 4'h0; // @[UART.scala 100:17]
    end else if (out_f_wivalid_13) begin // @[RegField.scala 74:88]
      rxwm <= bundleIn_0_a_bits_data[19:16]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[UART.scala 101:18]
      nstop <= 1'h0; // @[UART.scala 101:18]
    end else if (out_f_wivalid_10) begin // @[RegField.scala 74:88]
      nstop <= bundleIn_0_a_bits_data[1]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[UART.scala 135:15]
      ie_rxwm <= 1'h0; // @[UART.scala 135:15]
    end else if (out_f_wivalid_15) begin // @[RegField.scala 74:88]
      ie_rxwm <= bundleIn_0_a_bits_data[1]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[UART.scala 135:15]
      ie_txwm <= 1'h0; // @[UART.scala 135:15]
    end else if (out_f_wivalid_14) begin // @[RegField.scala 74:88]
      ie_txwm <= bundleIn_0_a_bits_data[0]; // @[RegField.scala 74:92]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  div = _RAND_0[15:0];
  _RAND_1 = {1{`RANDOM}};
  txen = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  rxen = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  txwm = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  rxwm = _RAND_4[3:0];
  _RAND_5 = {1{`RANDOM}};
  nstop = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  ie_rxwm = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  ie_txwm = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ClockSinkDomain_4(
  output        auto_uart_3_int_xing_out_sync_0,
  output        auto_uart_3_control_xing_in_a_ready,
  input         auto_uart_3_control_xing_in_a_valid,
  input  [2:0]  auto_uart_3_control_xing_in_a_bits_opcode,
  input  [2:0]  auto_uart_3_control_xing_in_a_bits_param,
  input  [1:0]  auto_uart_3_control_xing_in_a_bits_size,
  input  [6:0]  auto_uart_3_control_xing_in_a_bits_source,
  input  [28:0] auto_uart_3_control_xing_in_a_bits_address,
  input  [3:0]  auto_uart_3_control_xing_in_a_bits_mask,
  input  [31:0] auto_uart_3_control_xing_in_a_bits_data,
  input         auto_uart_3_control_xing_in_a_bits_corrupt,
  input         auto_uart_3_control_xing_in_d_ready,
  output        auto_uart_3_control_xing_in_d_valid,
  output [2:0]  auto_uart_3_control_xing_in_d_bits_opcode,
  output [1:0]  auto_uart_3_control_xing_in_d_bits_size,
  output [6:0]  auto_uart_3_control_xing_in_d_bits_source,
  output [31:0] auto_uart_3_control_xing_in_d_bits_data,
  output        auto_uart_3_io_out_txd,
  input         auto_uart_3_io_out_rxd,
  input         auto_clock_in_clock,
  input         auto_clock_in_reset
);
  wire  uart_3_clock; // @[UART.scala 243:51]
  wire  uart_3_reset; // @[UART.scala 243:51]
  wire  uart_3_auto_int_xing_out_sync_0; // @[UART.scala 243:51]
  wire  uart_3_auto_control_xing_in_a_ready; // @[UART.scala 243:51]
  wire  uart_3_auto_control_xing_in_a_valid; // @[UART.scala 243:51]
  wire [2:0] uart_3_auto_control_xing_in_a_bits_opcode; // @[UART.scala 243:51]
  wire [2:0] uart_3_auto_control_xing_in_a_bits_param; // @[UART.scala 243:51]
  wire [1:0] uart_3_auto_control_xing_in_a_bits_size; // @[UART.scala 243:51]
  wire [6:0] uart_3_auto_control_xing_in_a_bits_source; // @[UART.scala 243:51]
  wire [28:0] uart_3_auto_control_xing_in_a_bits_address; // @[UART.scala 243:51]
  wire [3:0] uart_3_auto_control_xing_in_a_bits_mask; // @[UART.scala 243:51]
  wire [31:0] uart_3_auto_control_xing_in_a_bits_data; // @[UART.scala 243:51]
  wire  uart_3_auto_control_xing_in_a_bits_corrupt; // @[UART.scala 243:51]
  wire  uart_3_auto_control_xing_in_d_ready; // @[UART.scala 243:51]
  wire  uart_3_auto_control_xing_in_d_valid; // @[UART.scala 243:51]
  wire [2:0] uart_3_auto_control_xing_in_d_bits_opcode; // @[UART.scala 243:51]
  wire [1:0] uart_3_auto_control_xing_in_d_bits_size; // @[UART.scala 243:51]
  wire [6:0] uart_3_auto_control_xing_in_d_bits_source; // @[UART.scala 243:51]
  wire [31:0] uart_3_auto_control_xing_in_d_bits_data; // @[UART.scala 243:51]
  wire  uart_3_auto_io_out_txd; // @[UART.scala 243:51]
  wire  uart_3_auto_io_out_rxd; // @[UART.scala 243:51]
  TLUART_3 uart_3 ( // @[UART.scala 243:51]
    .clock(uart_3_clock),
    .reset(uart_3_reset),
    .auto_int_xing_out_sync_0(uart_3_auto_int_xing_out_sync_0),
    .auto_control_xing_in_a_ready(uart_3_auto_control_xing_in_a_ready),
    .auto_control_xing_in_a_valid(uart_3_auto_control_xing_in_a_valid),
    .auto_control_xing_in_a_bits_opcode(uart_3_auto_control_xing_in_a_bits_opcode),
    .auto_control_xing_in_a_bits_param(uart_3_auto_control_xing_in_a_bits_param),
    .auto_control_xing_in_a_bits_size(uart_3_auto_control_xing_in_a_bits_size),
    .auto_control_xing_in_a_bits_source(uart_3_auto_control_xing_in_a_bits_source),
    .auto_control_xing_in_a_bits_address(uart_3_auto_control_xing_in_a_bits_address),
    .auto_control_xing_in_a_bits_mask(uart_3_auto_control_xing_in_a_bits_mask),
    .auto_control_xing_in_a_bits_data(uart_3_auto_control_xing_in_a_bits_data),
    .auto_control_xing_in_a_bits_corrupt(uart_3_auto_control_xing_in_a_bits_corrupt),
    .auto_control_xing_in_d_ready(uart_3_auto_control_xing_in_d_ready),
    .auto_control_xing_in_d_valid(uart_3_auto_control_xing_in_d_valid),
    .auto_control_xing_in_d_bits_opcode(uart_3_auto_control_xing_in_d_bits_opcode),
    .auto_control_xing_in_d_bits_size(uart_3_auto_control_xing_in_d_bits_size),
    .auto_control_xing_in_d_bits_source(uart_3_auto_control_xing_in_d_bits_source),
    .auto_control_xing_in_d_bits_data(uart_3_auto_control_xing_in_d_bits_data),
    .auto_io_out_txd(uart_3_auto_io_out_txd),
    .auto_io_out_rxd(uart_3_auto_io_out_rxd)
  );
  assign auto_uart_3_int_xing_out_sync_0 = uart_3_auto_int_xing_out_sync_0; // @[LazyModule.scala 311:12]
  assign auto_uart_3_control_xing_in_a_ready = uart_3_auto_control_xing_in_a_ready; // @[LazyModule.scala 309:16]
  assign auto_uart_3_control_xing_in_d_valid = uart_3_auto_control_xing_in_d_valid; // @[LazyModule.scala 309:16]
  assign auto_uart_3_control_xing_in_d_bits_opcode = uart_3_auto_control_xing_in_d_bits_opcode; // @[LazyModule.scala 309:16]
  assign auto_uart_3_control_xing_in_d_bits_size = uart_3_auto_control_xing_in_d_bits_size; // @[LazyModule.scala 309:16]
  assign auto_uart_3_control_xing_in_d_bits_source = uart_3_auto_control_xing_in_d_bits_source; // @[LazyModule.scala 309:16]
  assign auto_uart_3_control_xing_in_d_bits_data = uart_3_auto_control_xing_in_d_bits_data; // @[LazyModule.scala 309:16]
  assign auto_uart_3_io_out_txd = uart_3_auto_io_out_txd; // @[LazyModule.scala 311:12]
  assign uart_3_clock = auto_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign uart_3_reset = auto_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign uart_3_auto_control_xing_in_a_valid = auto_uart_3_control_xing_in_a_valid; // @[LazyModule.scala 309:16]
  assign uart_3_auto_control_xing_in_a_bits_opcode = auto_uart_3_control_xing_in_a_bits_opcode; // @[LazyModule.scala 309:16]
  assign uart_3_auto_control_xing_in_a_bits_param = auto_uart_3_control_xing_in_a_bits_param; // @[LazyModule.scala 309:16]
  assign uart_3_auto_control_xing_in_a_bits_size = auto_uart_3_control_xing_in_a_bits_size; // @[LazyModule.scala 309:16]
  assign uart_3_auto_control_xing_in_a_bits_source = auto_uart_3_control_xing_in_a_bits_source; // @[LazyModule.scala 309:16]
  assign uart_3_auto_control_xing_in_a_bits_address = auto_uart_3_control_xing_in_a_bits_address; // @[LazyModule.scala 309:16]
  assign uart_3_auto_control_xing_in_a_bits_mask = auto_uart_3_control_xing_in_a_bits_mask; // @[LazyModule.scala 309:16]
  assign uart_3_auto_control_xing_in_a_bits_data = auto_uart_3_control_xing_in_a_bits_data; // @[LazyModule.scala 309:16]
  assign uart_3_auto_control_xing_in_a_bits_corrupt = auto_uart_3_control_xing_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
  assign uart_3_auto_control_xing_in_d_ready = auto_uart_3_control_xing_in_d_ready; // @[LazyModule.scala 309:16]
  assign uart_3_auto_io_out_rxd = auto_uart_3_io_out_rxd; // @[LazyModule.scala 311:12]
endmodule
module TLMonitor_60(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [1:0]  io_in_a_bits_size,
  input  [6:0]  io_in_a_bits_source,
  input  [28:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_size,
  input  [6:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [95:0] _RAND_10;
  reg [383:0] _RAND_11;
  reg [383:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [95:0] _RAND_16;
  reg [383:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T_4 = io_in_a_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire [4:0] _is_aligned_mask_T_1 = 5'h3 << io_in_a_bits_size; // @[package.scala 234:77]
  wire [1:0] is_aligned_mask = ~_is_aligned_mask_T_1[1:0]; // @[package.scala 234:46]
  wire [28:0] _GEN_71 = {{27'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 2'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [28:0] _T_33 = io_in_a_bits_address ^ 29'h10053000; // @[Parameters.scala 137:31]
  wire [29:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
  wire [29:0] _T_36 = $signed(_T_34) & -30'sh1000; // @[Parameters.scala 137:52]
  wire  _T_37 = $signed(_T_36) == 30'sh0; // @[Parameters.scala 137:67]
  wire  _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_74 = _T_73 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_164 = io_in_a_bits_size <= 2'h2; // @[Parameters.scala 92:42]
  wire  _T_172 = _T_164 & _T_37; // @[Parameters.scala 670:56]
  wire  _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_218 = _source_ok_T_4 & _T_172; // @[Monitor.scala 115:71]
  wire  _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_273 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_274 = io_in_a_bits_mask & _T_273; // @[Monitor.scala 127:31]
  wire  _T_275 = _T_274 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_279 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_347 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_355 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_385 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_397 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_10 = io_in_d_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire  _T_401 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_405 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 312:27]
  wire  _T_421 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_449 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_478 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_495 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_513 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [1:0] size; // @[Monitor.scala 386:22]
  reg [6:0] source; // @[Monitor.scala 387:22]
  reg [28:0] address; // @[Monitor.scala 388:22]
  wire  _T_543 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_544 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_548 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_552 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_556 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_560 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] size_1; // @[Monitor.scala 537:22]
  reg [6:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_567 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_568 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_576 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_580 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [95:0] inflight; // @[Monitor.scala 611:27]
  reg [383:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [383:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [8:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [9:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [383:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [383:0] _GEN_73 = {{368'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[383:1]}; // @[Monitor.scala 634:152]
  wire [383:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [383:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
  wire [383:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[383:1]}; // @[Monitor.scala 638:144]
  wire  _T_594 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [127:0] _a_set_wo_ready_T = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_597 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
  wire [8:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [9:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [1026:0] _GEN_1 = {{1023'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [1026:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
  wire [1025:0] _GEN_2 = {{1023'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [1025:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [95:0] _T_599 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_601 = ~_T_599[0]; // @[Monitor.scala 658:17]
  wire [127:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 652:72 653:28]
  wire [1026:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 1027'h0; // @[Monitor.scala 652:72 656:28]
  wire [1025:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 1026'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_605 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_607 = ~_T_401; // @[Monitor.scala 671:74]
  wire  _T_608 = io_in_d_valid & d_first_1 & ~_T_401; // @[Monitor.scala 671:71]
  wire [127:0] _d_clr_wo_ready_T = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [1038:0] _GEN_3 = {{1023'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [1038:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [127:0] _GEN_22 = d_first_done & d_first_1 & _T_607 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 675:91 676:21]
  wire [1038:0] _GEN_23 = d_first_done & d_first_1 & _T_607 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_594 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [95:0] _T_618 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_620 = _T_618[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_625 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_626 = io_in_d_bits_opcode == _GEN_32 | _T_625; // @[Monitor.scala 685:77]
  wire  _T_630 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_637 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_638 = io_in_d_bits_opcode == _GEN_48 | _T_637; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_642 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_652 = _T_605 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_607; // @[Monitor.scala 694:116]
  wire  _T_654 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [95:0] a_set = _GEN_16[95:0];
  wire [95:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [95:0] d_clr = _GEN_22[95:0];
  wire [95:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [95:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [383:0] a_opcodes_set = _GEN_19[383:0];
  wire [383:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [383:0] d_opcodes_clr = _GEN_23[383:0];
  wire [383:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [383:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [383:0] a_sizes_set = _GEN_20[383:0];
  wire [383:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [383:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_663 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [95:0] inflight_1; // @[Monitor.scala 723:35]
  reg [383:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [383:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [383:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
  wire [383:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[383:1]}; // @[Monitor.scala 747:146]
  wire  _T_689 = io_in_d_valid & d_first_2 & _T_401; // @[Monitor.scala 779:71]
  wire [127:0] _GEN_67 = d_first_done & d_first_2 & _T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 783:90 784:21]
  wire [1038:0] _GEN_68 = d_first_done & d_first_2 & _T_401 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 783:90 785:21]
  wire [95:0] _T_697 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_707 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [95:0] d_clr_1 = _GEN_67[95:0];
  wire [95:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [95:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [383:0] d_opcodes_clr_1 = _GEN_68[383:0];
  wire [383:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [383:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_727 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 1'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= 1'h0;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 96'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 384'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 384'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 1'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= 1'h0;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 96'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 384'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= 1'h0;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (d_first_done) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_172 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_172) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_275 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_275) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_309 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_309) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_347 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_347) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_385 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_397 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_397) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_478 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_478 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_495 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_495 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_513 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_513 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_544 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_544) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_548 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_548) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_552 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_552) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_556 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_556) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_560 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_560) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_568 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_568) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_576 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_576) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_580 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_580) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_601 & (_T_597 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_597 & ~reset & ~_T_601) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_620 & (_T_608 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & _T_2 & ~_T_620) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_626 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_626) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_630 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_630) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_638 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_638) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_642 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_642) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_654 & (_T_652 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_652 & _T_2 & ~_T_654) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_663 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_663) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_697[0] & (_T_689 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_689 & _T_2 & ~_T_697[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_707 & (_T_689 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_689 & _T_2 & ~_T_707) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_727 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_727) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[6:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[28:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[6:0];
  _RAND_10 = {3{`RANDOM}};
  inflight = _RAND_10[95:0];
  _RAND_11 = {12{`RANDOM}};
  inflight_opcodes = _RAND_11[383:0];
  _RAND_12 = {12{`RANDOM}};
  inflight_sizes = _RAND_12[383:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {3{`RANDOM}};
  inflight_1 = _RAND_16[95:0];
  _RAND_17 = {12{`RANDOM}};
  inflight_sizes_1 = _RAND_17[383:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLUART_4(
  input         clock,
  input         reset,
  output        auto_int_xing_out_sync_0,
  output        auto_control_xing_in_a_ready,
  input         auto_control_xing_in_a_valid,
  input  [2:0]  auto_control_xing_in_a_bits_opcode,
  input  [2:0]  auto_control_xing_in_a_bits_param,
  input  [1:0]  auto_control_xing_in_a_bits_size,
  input  [6:0]  auto_control_xing_in_a_bits_source,
  input  [28:0] auto_control_xing_in_a_bits_address,
  input  [3:0]  auto_control_xing_in_a_bits_mask,
  input  [31:0] auto_control_xing_in_a_bits_data,
  input         auto_control_xing_in_a_bits_corrupt,
  input         auto_control_xing_in_d_ready,
  output        auto_control_xing_in_d_valid,
  output [2:0]  auto_control_xing_in_d_bits_opcode,
  output [1:0]  auto_control_xing_in_d_bits_size,
  output [6:0]  auto_control_xing_in_d_bits_source,
  output [31:0] auto_control_xing_in_d_bits_data,
  output        auto_io_out_txd,
  input         auto_io_out_rxd
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
`endif // RANDOMIZE_REG_INIT
  wire  buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
  wire [28:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
  wire [28:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
  wire  intsource_clock; // @[Crossing.scala 26:31]
  wire  intsource_reset; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_0; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_0; // @[Crossing.scala 26:31]
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  txm_clock; // @[UART.scala 79:19]
  wire  txm_reset; // @[UART.scala 79:19]
  wire  txm_io_en; // @[UART.scala 79:19]
  wire  txm_io_in_ready; // @[UART.scala 79:19]
  wire  txm_io_in_valid; // @[UART.scala 79:19]
  wire [7:0] txm_io_in_bits; // @[UART.scala 79:19]
  wire  txm_io_out; // @[UART.scala 79:19]
  wire [15:0] txm_io_div; // @[UART.scala 79:19]
  wire  txm_io_nstop; // @[UART.scala 79:19]
  wire  txq_clock; // @[UART.scala 80:19]
  wire  txq_reset; // @[UART.scala 80:19]
  wire  txq_io_enq_ready; // @[UART.scala 80:19]
  wire  txq_io_enq_valid; // @[UART.scala 80:19]
  wire [7:0] txq_io_enq_bits; // @[UART.scala 80:19]
  wire  txq_io_deq_ready; // @[UART.scala 80:19]
  wire  txq_io_deq_valid; // @[UART.scala 80:19]
  wire [7:0] txq_io_deq_bits; // @[UART.scala 80:19]
  wire [3:0] txq_io_count; // @[UART.scala 80:19]
  wire  rxm_clock; // @[UART.scala 82:19]
  wire  rxm_reset; // @[UART.scala 82:19]
  wire  rxm_io_en; // @[UART.scala 82:19]
  wire  rxm_io_in; // @[UART.scala 82:19]
  wire  rxm_io_out_valid; // @[UART.scala 82:19]
  wire [7:0] rxm_io_out_bits; // @[UART.scala 82:19]
  wire [15:0] rxm_io_div; // @[UART.scala 82:19]
  wire  rxq_clock; // @[UART.scala 83:19]
  wire  rxq_reset; // @[UART.scala 83:19]
  wire  rxq_io_enq_ready; // @[UART.scala 83:19]
  wire  rxq_io_enq_valid; // @[UART.scala 83:19]
  wire [7:0] rxq_io_enq_bits; // @[UART.scala 83:19]
  wire  rxq_io_deq_ready; // @[UART.scala 83:19]
  wire  rxq_io_deq_valid; // @[UART.scala 83:19]
  wire [7:0] rxq_io_deq_bits; // @[UART.scala 83:19]
  wire [3:0] rxq_io_count; // @[UART.scala 83:19]
  reg [15:0] div; // @[UART.scala 85:16]
  reg  txen; // @[UART.scala 91:17]
  reg  rxen; // @[UART.scala 92:17]
  reg [3:0] txwm; // @[UART.scala 99:17]
  reg [3:0] rxwm; // @[UART.scala 100:17]
  reg  nstop; // @[UART.scala 101:18]
  reg  ie_rxwm; // @[UART.scala 135:15]
  reg  ie_txwm; // @[UART.scala 135:15]
  wire  ip_txwm = txq_io_count < txwm; // @[UART.scala 138:28]
  wire  ip_rxwm = rxq_io_count > rxwm; // @[UART.scala 139:28]
  wire  _T = ~txq_io_enq_ready; // @[RegMapFIFO.scala 25:9]
  wire  _T_1 = ~rxq_io_deq_valid; // @[RegMapFIFO.scala 46:21]
  wire [2:0] bundleIn_0_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  in_bits_read = bundleIn_0_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 72:36]
  wire [28:0] bundleIn_0_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [9:0] in_bits_index = bundleIn_0_a_bits_address[11:2]; // @[RegisterRouter.scala 71:18 73:19]
  wire [9:0] out_findex = in_bits_index & 10'h3f8; // @[RegisterRouter.scala 83:24]
  wire  _out_T = out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [3:0] bundleIn_0_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [7:0] _out_frontMask_T_5 = bundleIn_0_a_bits_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_frontMask_T_7 = bundleIn_0_a_bits_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_frontMask_T_9 = bundleIn_0_a_bits_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_frontMask_T_11 = bundleIn_0_a_bits_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [31:0] out_frontMask = {_out_frontMask_T_11,_out_frontMask_T_9,_out_frontMask_T_7,_out_frontMask_T_5}; // @[Cat.scala 31:58]
  wire  out_rimask = |out_frontMask[7:0]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask = &out_frontMask[7:0]; // @[RegisterRouter.scala 83:24]
  wire  bundleIn_0_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  bundleIn_0_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [2:0] out_oindex = {in_bits_index[2],in_bits_index[1],in_bits_index[0]}; // @[Cat.scala 31:58]
  wire [7:0] _out_frontSel_T = 8'h1 << out_oindex; // @[OneHot.scala 57:35]
  wire  out_frontSel_0 = _out_frontSel_T[0]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_0 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_0 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala 83:24]
  wire [31:0] bundleIn_0_a_bits_data = buffer_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  out_womask_2 = &out_frontMask[31]; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_2 = out_wivalid_0 & out_womask_2; // @[RegisterRouter.scala 83:24]
  wire  quash = out_f_woready_2 & bundleIn_0_a_bits_data[31]; // @[RegMapFIFO.scala 27:26]
  wire [31:0] out_prepend_1 = {_T,31'h0}; // @[Cat.scala 31:58]
  wire  out_wimask_3 = &out_frontMask[0]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_4 = &out_frontMask[1]; // @[RegisterRouter.scala 83:24]
  wire [1:0] out_prepend_2 = {ip_rxwm,ip_txwm}; // @[Cat.scala 31:58]
  wire  out_frontSel_1 = _out_frontSel_T[1]; // @[RegisterRouter.scala 83:24]
  wire  out_rivalid_5 = bundleIn_0_a_valid & bundleIn_0_d_ready & in_bits_read & out_frontSel_1 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [7:0] _out_T_66 = rxq_io_deq_bits; // @[RegisterRouter.scala 83:24]
  wire [8:0] out_prepend_3 = {1'h0,_out_T_66}; // @[Cat.scala 31:58]
  wire [30:0] _out_T_75 = {{22'd0}, out_prepend_3}; // @[RegisterRouter.scala 83:24]
  wire [31:0] out_prepend_4 = {_T_1,_out_T_75}; // @[Cat.scala 31:58]
  wire  out_wimask_8 = &out_frontMask[15:0]; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_6 = _out_frontSel_T[6]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_8 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_6 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_2 = _out_frontSel_T[2]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_9 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_2 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_9 = out_wivalid_9 & out_wimask_3; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_10 = out_wivalid_9 & out_wimask_4; // @[RegisterRouter.scala 83:24]
  wire [1:0] out_prepend_5 = {nstop,txen}; // @[Cat.scala 31:58]
  wire  out_wimask_11 = &out_frontMask[19:16]; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_11 = out_wivalid_9 & out_wimask_11; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_prepend_T_6 = {{14'd0}, out_prepend_5}; // @[RegisterRouter.scala 83:24]
  wire [19:0] out_prepend_6 = {txwm,_out_prepend_T_6}; // @[Cat.scala 31:58]
  wire  out_frontSel_3 = _out_frontSel_T[3]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_12 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_3 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_12 = out_wivalid_12 & out_wimask_3; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_13 = out_wivalid_12 & out_wimask_11; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_prepend_T_7 = {{15'd0}, rxen}; // @[RegisterRouter.scala 83:24]
  wire [19:0] out_prepend_7 = {rxwm,_out_prepend_T_7}; // @[Cat.scala 31:58]
  wire  out_frontSel_4 = _out_frontSel_T[4]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_14 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_4 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_14 = out_wivalid_14 & out_wimask_3; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_15 = out_wivalid_14 & out_wimask_4; // @[RegisterRouter.scala 83:24]
  wire [1:0] out_prepend_8 = {ie_rxwm,ie_txwm}; // @[Cat.scala 31:58]
  wire  _GEN_41 = 3'h1 == out_oindex ? _out_T : _out_T; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_42 = 3'h2 == out_oindex ? _out_T : _GEN_41; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_43 = 3'h3 == out_oindex ? _out_T : _GEN_42; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_44 = 3'h4 == out_oindex ? _out_T : _GEN_43; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_45 = 3'h5 == out_oindex ? _out_T : _GEN_44; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_46 = 3'h6 == out_oindex ? _out_T : _GEN_45; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_47 = 3'h7 == out_oindex | _GEN_46; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_49 = 3'h1 == out_oindex ? out_prepend_4 : out_prepend_1; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_2 = {{12'd0}, out_prepend_6}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_50 = 3'h2 == out_oindex ? _out_out_bits_data_WIRE_1_2 : _GEN_49; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_3 = {{12'd0}, out_prepend_7}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_51 = 3'h3 == out_oindex ? _out_out_bits_data_WIRE_1_3 : _GEN_50; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_4 = {{30'd0}, out_prepend_8}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_52 = 3'h4 == out_oindex ? _out_out_bits_data_WIRE_1_4 : _GEN_51; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_5 = {{30'd0}, out_prepend_2}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_53 = 3'h5 == out_oindex ? _out_out_bits_data_WIRE_1_5 : _GEN_52; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_6 = {{16'd0}, div}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_54 = 3'h6 == out_oindex ? _out_out_bits_data_WIRE_1_6 : _GEN_53; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_55 = 3'h7 == out_oindex ? 32'h0 : _GEN_54; // @[MuxLiteral.scala 48:{10,10}]
  TLBuffer_13 buffer ( // @[Buffer.scala 68:28]
    .auto_in_a_ready(buffer_auto_in_a_ready),
    .auto_in_a_valid(buffer_auto_in_a_valid),
    .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
    .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
    .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
    .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
    .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
    .auto_in_a_bits_data(buffer_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
    .auto_in_d_ready(buffer_auto_in_d_ready),
    .auto_in_d_valid(buffer_auto_in_d_valid),
    .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
    .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
    .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
    .auto_out_a_ready(buffer_auto_out_a_ready),
    .auto_out_a_valid(buffer_auto_out_a_valid),
    .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
    .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
    .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
    .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
    .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
    .auto_out_a_bits_data(buffer_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
    .auto_out_d_ready(buffer_auto_out_d_ready),
    .auto_out_d_valid(buffer_auto_out_d_valid),
    .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
    .auto_out_d_bits_source(buffer_auto_out_d_bits_source),
    .auto_out_d_bits_data(buffer_auto_out_d_bits_data)
  );
  IntSyncCrossingSource_1 intsource ( // @[Crossing.scala 26:31]
    .clock(intsource_clock),
    .reset(intsource_reset),
    .auto_in_0(intsource_auto_in_0),
    .auto_out_sync_0(intsource_auto_out_sync_0)
  );
  TLMonitor_60 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  UARTTx txm ( // @[UART.scala 79:19]
    .clock(txm_clock),
    .reset(txm_reset),
    .io_en(txm_io_en),
    .io_in_ready(txm_io_in_ready),
    .io_in_valid(txm_io_in_valid),
    .io_in_bits(txm_io_in_bits),
    .io_out(txm_io_out),
    .io_div(txm_io_div),
    .io_nstop(txm_io_nstop)
  );
  QueueCompatibility txq ( // @[UART.scala 80:19]
    .clock(txq_clock),
    .reset(txq_reset),
    .io_enq_ready(txq_io_enq_ready),
    .io_enq_valid(txq_io_enq_valid),
    .io_enq_bits(txq_io_enq_bits),
    .io_deq_ready(txq_io_deq_ready),
    .io_deq_valid(txq_io_deq_valid),
    .io_deq_bits(txq_io_deq_bits),
    .io_count(txq_io_count)
  );
  UARTRx rxm ( // @[UART.scala 82:19]
    .clock(rxm_clock),
    .reset(rxm_reset),
    .io_en(rxm_io_en),
    .io_in(rxm_io_in),
    .io_out_valid(rxm_io_out_valid),
    .io_out_bits(rxm_io_out_bits),
    .io_div(rxm_io_div)
  );
  QueueCompatibility rxq ( // @[UART.scala 83:19]
    .clock(rxq_clock),
    .reset(rxq_reset),
    .io_enq_ready(rxq_io_enq_ready),
    .io_enq_valid(rxq_io_enq_valid),
    .io_enq_bits(rxq_io_enq_bits),
    .io_deq_ready(rxq_io_deq_ready),
    .io_deq_valid(rxq_io_deq_valid),
    .io_deq_bits(rxq_io_deq_bits),
    .io_count(rxq_io_count)
  );
  assign auto_int_xing_out_sync_0 = intsource_auto_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_in_a_ready = buffer_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_valid = buffer_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_size = buffer_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_source = buffer_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_data = buffer_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_io_out_txd = txm_io_out; // @[Nodes.scala 1207:84 UART.scala 113:12]
  assign buffer_auto_in_a_valid = auto_control_xing_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_opcode = auto_control_xing_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_param = auto_control_xing_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_size = auto_control_xing_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_source = auto_control_xing_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_address = auto_control_xing_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_mask = auto_control_xing_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_data = auto_control_xing_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_corrupt = auto_control_xing_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_d_ready = auto_control_xing_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_out_a_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign buffer_auto_out_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_data = _GEN_47 ? _GEN_55 : 32'h0; // @[RegisterRouter.scala 83:24]
  assign intsource_clock = clock;
  assign intsource_reset = reset;
  assign intsource_auto_in_0 = ip_txwm & ie_txwm | ip_rxwm & ie_rxwm; // @[UART.scala 140:41]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_param = buffer_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign monitor_io_in_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign txm_clock = clock;
  assign txm_reset = reset;
  assign txm_io_en = txen; // @[UART.scala 109:15]
  assign txm_io_in_valid = txq_io_deq_valid; // @[UART.scala 110:13]
  assign txm_io_in_bits = txq_io_deq_bits; // @[UART.scala 110:13]
  assign txm_io_div = div; // @[UART.scala 111:14]
  assign txm_io_nstop = nstop; // @[UART.scala 112:16]
  assign txq_clock = clock;
  assign txq_reset = reset;
  assign txq_io_enq_valid = out_f_wivalid & ~quash; // @[RegMapFIFO.scala 19:30]
  assign txq_io_enq_bits = bundleIn_0_a_bits_data[7:0]; // @[RegisterRouter.scala 83:24]
  assign txq_io_deq_ready = txm_io_in_ready; // @[UART.scala 110:13]
  assign rxm_clock = clock;
  assign rxm_reset = reset;
  assign rxm_io_en = rxen; // @[UART.scala 120:13]
  assign rxm_io_in = auto_io_out_rxd; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign rxm_io_div = div; // @[UART.scala 123:14]
  assign rxq_clock = clock;
  assign rxq_reset = reset;
  assign rxq_io_enq_valid = rxm_io_out_valid; // @[UART.scala 122:14]
  assign rxq_io_enq_bits = rxm_io_out_bits; // @[UART.scala 122:14]
  assign rxq_io_deq_ready = out_rivalid_5 & out_rimask; // @[RegisterRouter.scala 83:24]
  always @(posedge clock) begin
    if (reset) begin // @[UART.scala 85:16]
      div <= 16'h364; // @[UART.scala 85:16]
    end else if (out_f_wivalid_8) begin // @[RegField.scala 74:88]
      div <= bundleIn_0_a_bits_data[15:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[UART.scala 91:17]
      txen <= 1'h0; // @[UART.scala 91:17]
    end else if (out_f_wivalid_9) begin // @[RegField.scala 74:88]
      txen <= bundleIn_0_a_bits_data[0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[UART.scala 92:17]
      rxen <= 1'h0; // @[UART.scala 92:17]
    end else if (out_f_wivalid_12) begin // @[RegField.scala 74:88]
      rxen <= bundleIn_0_a_bits_data[0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[UART.scala 99:17]
      txwm <= 4'h0; // @[UART.scala 99:17]
    end else if (out_f_wivalid_11) begin // @[RegField.scala 74:88]
      txwm <= bundleIn_0_a_bits_data[19:16]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[UART.scala 100:17]
      rxwm <= 4'h0; // @[UART.scala 100:17]
    end else if (out_f_wivalid_13) begin // @[RegField.scala 74:88]
      rxwm <= bundleIn_0_a_bits_data[19:16]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[UART.scala 101:18]
      nstop <= 1'h0; // @[UART.scala 101:18]
    end else if (out_f_wivalid_10) begin // @[RegField.scala 74:88]
      nstop <= bundleIn_0_a_bits_data[1]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[UART.scala 135:15]
      ie_rxwm <= 1'h0; // @[UART.scala 135:15]
    end else if (out_f_wivalid_15) begin // @[RegField.scala 74:88]
      ie_rxwm <= bundleIn_0_a_bits_data[1]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[UART.scala 135:15]
      ie_txwm <= 1'h0; // @[UART.scala 135:15]
    end else if (out_f_wivalid_14) begin // @[RegField.scala 74:88]
      ie_txwm <= bundleIn_0_a_bits_data[0]; // @[RegField.scala 74:92]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  div = _RAND_0[15:0];
  _RAND_1 = {1{`RANDOM}};
  txen = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  rxen = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  txwm = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  rxwm = _RAND_4[3:0];
  _RAND_5 = {1{`RANDOM}};
  nstop = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  ie_rxwm = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  ie_txwm = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ClockSinkDomain_5(
  output        auto_uart_4_int_xing_out_sync_0,
  output        auto_uart_4_control_xing_in_a_ready,
  input         auto_uart_4_control_xing_in_a_valid,
  input  [2:0]  auto_uart_4_control_xing_in_a_bits_opcode,
  input  [2:0]  auto_uart_4_control_xing_in_a_bits_param,
  input  [1:0]  auto_uart_4_control_xing_in_a_bits_size,
  input  [6:0]  auto_uart_4_control_xing_in_a_bits_source,
  input  [28:0] auto_uart_4_control_xing_in_a_bits_address,
  input  [3:0]  auto_uart_4_control_xing_in_a_bits_mask,
  input  [31:0] auto_uart_4_control_xing_in_a_bits_data,
  input         auto_uart_4_control_xing_in_a_bits_corrupt,
  input         auto_uart_4_control_xing_in_d_ready,
  output        auto_uart_4_control_xing_in_d_valid,
  output [2:0]  auto_uart_4_control_xing_in_d_bits_opcode,
  output [1:0]  auto_uart_4_control_xing_in_d_bits_size,
  output [6:0]  auto_uart_4_control_xing_in_d_bits_source,
  output [31:0] auto_uart_4_control_xing_in_d_bits_data,
  output        auto_uart_4_io_out_txd,
  input         auto_uart_4_io_out_rxd,
  input         auto_clock_in_clock,
  input         auto_clock_in_reset
);
  wire  uart_4_clock; // @[UART.scala 243:51]
  wire  uart_4_reset; // @[UART.scala 243:51]
  wire  uart_4_auto_int_xing_out_sync_0; // @[UART.scala 243:51]
  wire  uart_4_auto_control_xing_in_a_ready; // @[UART.scala 243:51]
  wire  uart_4_auto_control_xing_in_a_valid; // @[UART.scala 243:51]
  wire [2:0] uart_4_auto_control_xing_in_a_bits_opcode; // @[UART.scala 243:51]
  wire [2:0] uart_4_auto_control_xing_in_a_bits_param; // @[UART.scala 243:51]
  wire [1:0] uart_4_auto_control_xing_in_a_bits_size; // @[UART.scala 243:51]
  wire [6:0] uart_4_auto_control_xing_in_a_bits_source; // @[UART.scala 243:51]
  wire [28:0] uart_4_auto_control_xing_in_a_bits_address; // @[UART.scala 243:51]
  wire [3:0] uart_4_auto_control_xing_in_a_bits_mask; // @[UART.scala 243:51]
  wire [31:0] uart_4_auto_control_xing_in_a_bits_data; // @[UART.scala 243:51]
  wire  uart_4_auto_control_xing_in_a_bits_corrupt; // @[UART.scala 243:51]
  wire  uart_4_auto_control_xing_in_d_ready; // @[UART.scala 243:51]
  wire  uart_4_auto_control_xing_in_d_valid; // @[UART.scala 243:51]
  wire [2:0] uart_4_auto_control_xing_in_d_bits_opcode; // @[UART.scala 243:51]
  wire [1:0] uart_4_auto_control_xing_in_d_bits_size; // @[UART.scala 243:51]
  wire [6:0] uart_4_auto_control_xing_in_d_bits_source; // @[UART.scala 243:51]
  wire [31:0] uart_4_auto_control_xing_in_d_bits_data; // @[UART.scala 243:51]
  wire  uart_4_auto_io_out_txd; // @[UART.scala 243:51]
  wire  uart_4_auto_io_out_rxd; // @[UART.scala 243:51]
  TLUART_4 uart_4 ( // @[UART.scala 243:51]
    .clock(uart_4_clock),
    .reset(uart_4_reset),
    .auto_int_xing_out_sync_0(uart_4_auto_int_xing_out_sync_0),
    .auto_control_xing_in_a_ready(uart_4_auto_control_xing_in_a_ready),
    .auto_control_xing_in_a_valid(uart_4_auto_control_xing_in_a_valid),
    .auto_control_xing_in_a_bits_opcode(uart_4_auto_control_xing_in_a_bits_opcode),
    .auto_control_xing_in_a_bits_param(uart_4_auto_control_xing_in_a_bits_param),
    .auto_control_xing_in_a_bits_size(uart_4_auto_control_xing_in_a_bits_size),
    .auto_control_xing_in_a_bits_source(uart_4_auto_control_xing_in_a_bits_source),
    .auto_control_xing_in_a_bits_address(uart_4_auto_control_xing_in_a_bits_address),
    .auto_control_xing_in_a_bits_mask(uart_4_auto_control_xing_in_a_bits_mask),
    .auto_control_xing_in_a_bits_data(uart_4_auto_control_xing_in_a_bits_data),
    .auto_control_xing_in_a_bits_corrupt(uart_4_auto_control_xing_in_a_bits_corrupt),
    .auto_control_xing_in_d_ready(uart_4_auto_control_xing_in_d_ready),
    .auto_control_xing_in_d_valid(uart_4_auto_control_xing_in_d_valid),
    .auto_control_xing_in_d_bits_opcode(uart_4_auto_control_xing_in_d_bits_opcode),
    .auto_control_xing_in_d_bits_size(uart_4_auto_control_xing_in_d_bits_size),
    .auto_control_xing_in_d_bits_source(uart_4_auto_control_xing_in_d_bits_source),
    .auto_control_xing_in_d_bits_data(uart_4_auto_control_xing_in_d_bits_data),
    .auto_io_out_txd(uart_4_auto_io_out_txd),
    .auto_io_out_rxd(uart_4_auto_io_out_rxd)
  );
  assign auto_uart_4_int_xing_out_sync_0 = uart_4_auto_int_xing_out_sync_0; // @[LazyModule.scala 311:12]
  assign auto_uart_4_control_xing_in_a_ready = uart_4_auto_control_xing_in_a_ready; // @[LazyModule.scala 309:16]
  assign auto_uart_4_control_xing_in_d_valid = uart_4_auto_control_xing_in_d_valid; // @[LazyModule.scala 309:16]
  assign auto_uart_4_control_xing_in_d_bits_opcode = uart_4_auto_control_xing_in_d_bits_opcode; // @[LazyModule.scala 309:16]
  assign auto_uart_4_control_xing_in_d_bits_size = uart_4_auto_control_xing_in_d_bits_size; // @[LazyModule.scala 309:16]
  assign auto_uart_4_control_xing_in_d_bits_source = uart_4_auto_control_xing_in_d_bits_source; // @[LazyModule.scala 309:16]
  assign auto_uart_4_control_xing_in_d_bits_data = uart_4_auto_control_xing_in_d_bits_data; // @[LazyModule.scala 309:16]
  assign auto_uart_4_io_out_txd = uart_4_auto_io_out_txd; // @[LazyModule.scala 311:12]
  assign uart_4_clock = auto_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign uart_4_reset = auto_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign uart_4_auto_control_xing_in_a_valid = auto_uart_4_control_xing_in_a_valid; // @[LazyModule.scala 309:16]
  assign uart_4_auto_control_xing_in_a_bits_opcode = auto_uart_4_control_xing_in_a_bits_opcode; // @[LazyModule.scala 309:16]
  assign uart_4_auto_control_xing_in_a_bits_param = auto_uart_4_control_xing_in_a_bits_param; // @[LazyModule.scala 309:16]
  assign uart_4_auto_control_xing_in_a_bits_size = auto_uart_4_control_xing_in_a_bits_size; // @[LazyModule.scala 309:16]
  assign uart_4_auto_control_xing_in_a_bits_source = auto_uart_4_control_xing_in_a_bits_source; // @[LazyModule.scala 309:16]
  assign uart_4_auto_control_xing_in_a_bits_address = auto_uart_4_control_xing_in_a_bits_address; // @[LazyModule.scala 309:16]
  assign uart_4_auto_control_xing_in_a_bits_mask = auto_uart_4_control_xing_in_a_bits_mask; // @[LazyModule.scala 309:16]
  assign uart_4_auto_control_xing_in_a_bits_data = auto_uart_4_control_xing_in_a_bits_data; // @[LazyModule.scala 309:16]
  assign uart_4_auto_control_xing_in_a_bits_corrupt = auto_uart_4_control_xing_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
  assign uart_4_auto_control_xing_in_d_ready = auto_uart_4_control_xing_in_d_ready; // @[LazyModule.scala 309:16]
  assign uart_4_auto_io_out_rxd = auto_uart_4_io_out_rxd; // @[LazyModule.scala 311:12]
endmodule
module TLBuffer_19(
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input         auto_in_a_bits_size,
  input  [8:0]  auto_in_a_bits_source,
  input  [29:0] auto_in_a_bits_address,
  input         auto_in_a_bits_mask,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output        auto_in_d_bits_size,
  output [8:0]  auto_in_d_bits_source,
  output [7:0]  auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output        auto_out_a_bits_size,
  output [8:0]  auto_out_a_bits_source,
  output [29:0] auto_out_a_bits_address,
  output        auto_out_a_bits_mask,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input         auto_out_d_bits_size,
  input  [8:0]  auto_out_d_bits_source,
  input  [7:0]  auto_out_d_bits_data
);
  assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module TLMonitor_61(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input         io_in_a_bits_size,
  input  [8:0]  io_in_a_bits_source,
  input  [29:0] io_in_a_bits_address,
  input         io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input         io_in_d_bits_size,
  input  [8:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [383:0] _RAND_9;
  reg [1535:0] _RAND_10;
  reg [767:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T_4 = io_in_a_bits_source <= 9'h17f; // @[Parameters.scala 57:20]
  wire  _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [29:0] _T_33 = io_in_a_bits_address ^ 30'h20000000; // @[Parameters.scala 137:31]
  wire [30:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
  wire [30:0] _T_36 = $signed(_T_34) & -31'sh20000000; // @[Parameters.scala 137:52]
  wire  _T_37 = $signed(_T_36) == 31'sh0; // @[Parameters.scala 137:67]
  wire  _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire  _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_74 = ~(~io_in_a_bits_mask); // @[Monitor.scala 88:31]
  wire  _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_163 = ~io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_170 = _T_163 & _T_37; // @[Parameters.scala 670:56]
  wire  _T_181 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_193 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_231 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire  _T_271 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_301 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_309 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_339 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_347 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_377 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _source_ok_T_10 = io_in_d_bits_source <= 9'h17f; // @[Parameters.scala 57:20]
  wire  a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg  size; // @[Monitor.scala 386:22]
  reg [8:0] source; // @[Monitor.scala 387:22]
  reg [29:0] address; // @[Monitor.scala 388:22]
  wire  _T_535 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_536 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_540 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_544 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_548 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_552 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg  size_1; // @[Monitor.scala 537:22]
  reg [8:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_559 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_568 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_572 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [383:0] inflight; // @[Monitor.scala 611:27]
  reg [1535:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [767:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [10:0] _GEN_71 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [11:0] _a_opcode_lookup_T = {{1'd0}, _GEN_71}; // @[Monitor.scala 634:69]
  wire [1535:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [1535:0] _GEN_72 = {{1520'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
  wire [1535:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_72; // @[Monitor.scala 634:97]
  wire [1535:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[1535:1]}; // @[Monitor.scala 634:152]
  wire [9:0] _a_size_lookup_T = {io_in_d_bits_source, 1'h0}; // @[Monitor.scala 638:65]
  wire [767:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala 638:40]
  wire [3:0] _a_size_lookup_T_5 = 4'h4 - 4'h1; // @[Monitor.scala 609:57]
  wire [767:0] _GEN_74 = {{764'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 638:91]
  wire [767:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_74; // @[Monitor.scala 638:91]
  wire [767:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[767:1]}; // @[Monitor.scala 638:144]
  wire  _T_586 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [511:0] _a_set_wo_ready_T = 512'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_589 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [1:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [1:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 2'h1; // @[Monitor.scala 655:59]
  wire [10:0] _GEN_76 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [11:0] _a_opcodes_set_T = {{1'd0}, _GEN_76}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [4098:0] _GEN_1 = {{4095'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [4098:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [9:0] _a_sizes_set_T = {io_in_a_bits_source, 1'h0}; // @[Monitor.scala 657:77]
  wire [1:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 2'h0; // @[Monitor.scala 652:72 655:28]
  wire [1024:0] _GEN_2 = {{1023'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [1024:0] _a_sizes_set_T_1 = _GEN_2 << _a_sizes_set_T; // @[Monitor.scala 657:52]
  wire [383:0] _T_591 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_593 = ~_T_591[0]; // @[Monitor.scala 658:17]
  wire [511:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 512'h0; // @[Monitor.scala 652:72 653:28]
  wire [4098:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 4099'h0; // @[Monitor.scala 652:72 656:28]
  wire [1024:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 1025'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_597 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire [511:0] _d_clr_wo_ready_T = 512'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [4110:0] _GEN_3 = {{4095'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [4110:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [1026:0] _GEN_4 = {{1023'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 678:74]
  wire [1026:0] _d_sizes_clr_T_5 = _GEN_4 << _a_size_lookup_T; // @[Monitor.scala 678:74]
  wire [511:0] _GEN_22 = d_first_done & d_first_1 ? _d_clr_wo_ready_T : 512'h0; // @[Monitor.scala 675:91 676:21]
  wire [4110:0] _GEN_23 = d_first_done & d_first_1 ? _d_opcodes_clr_T_5 : 4111'h0; // @[Monitor.scala 675:91 677:21]
  wire [1026:0] _GEN_24 = d_first_done & d_first_1 ? _d_sizes_clr_T_5 : 1027'h0; // @[Monitor.scala 675:91 678:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_586 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [383:0] _T_610 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_612 = _T_610[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_617 = 3'h1 == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_618 = 3'h1 == _GEN_32 | _T_617; // @[Monitor.scala 685:77]
  wire  _T_622 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_629 = 3'h1 == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_630 = 3'h1 == _GEN_48 | _T_629; // @[Monitor.scala 689:72]
  wire [1:0] a_size_lookup = _a_size_lookup_T_7[1:0];
  wire [1:0] _GEN_78 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_634 = _GEN_78 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_642 = _T_597 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2; // @[Monitor.scala 694:65]
  wire  _T_646 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [383:0] a_set = _GEN_16[383:0];
  wire [383:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [383:0] d_clr = _GEN_22[383:0];
  wire [383:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [383:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [1535:0] a_opcodes_set = _GEN_19[1535:0];
  wire [1535:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [1535:0] d_opcodes_clr = _GEN_23[1535:0];
  wire [1535:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [1535:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [767:0] a_sizes_set = _GEN_20[767:0];
  wire [767:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [767:0] d_sizes_clr = _GEN_24[767:0];
  wire [767:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala 704:56]
  wire [767:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_655 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 1'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= 1'h0;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 384'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 1536'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 768'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 1'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= 1'h0;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_170 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_170) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_181 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_181) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_73 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_73) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_193 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_193 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_193 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_193 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_181 & (io_in_a_valid & _T_193 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_193 & ~reset & ~_T_181) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_73 & (io_in_a_valid & _T_193 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_193 & ~reset & _T_73) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_231 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_231 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_231 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_231 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_181 & (io_in_a_valid & _T_231 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_231 & ~reset & ~_T_181) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_271 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_271 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_271 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_271 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_301 & (io_in_a_valid & _T_271 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_271 & ~reset & ~_T_301) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_73 & (io_in_a_valid & _T_271 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_271 & ~reset & _T_73) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_309 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_309 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_309 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_309 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_339 & (io_in_a_valid & _T_309 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_309 & ~reset & ~_T_339) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_73 & (io_in_a_valid & _T_309 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_309 & ~reset & _T_73) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_347 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_347 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_347 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_347 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_377 & (io_in_a_valid & _T_347 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_347 & ~reset & ~_T_377) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_73 & (io_in_a_valid & _T_347 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_347 & ~reset & _T_73) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_347 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_347 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_536 & (_T_535 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_535 & ~reset & ~_T_536) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_540 & (_T_535 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_535 & ~reset & ~_T_540) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_544 & (_T_535 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_535 & ~reset & ~_T_544) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_548 & (_T_535 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_535 & ~reset & ~_T_548) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_552 & (_T_535 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_535 & ~reset & ~_T_552) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_568 & (_T_559 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_559 & _T_2 & ~_T_568) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_572 & (_T_559 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_559 & _T_2 & ~_T_572) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_593 & (_T_589 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_589 & ~reset & ~_T_593) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_612 & (_T_597 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_597 & _T_2 & ~_T_612) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_618 & (_T_597 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_597 & same_cycle_resp & _T_2 & ~_T_618) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_622 & (_T_597 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_597 & same_cycle_resp & _T_2 & ~_T_622) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_630 & (_T_597 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_597 & ~same_cycle_resp & _T_2 & ~_T_630) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_634 & (_T_597 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_597 & ~same_cycle_resp & _T_2 & ~_T_634) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_646 & (_T_642 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_642 & _T_2 & ~_T_646) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_655 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_655) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[8:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[29:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  size_1 = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  source_1 = _RAND_8[8:0];
  _RAND_9 = {12{`RANDOM}};
  inflight = _RAND_9[383:0];
  _RAND_10 = {48{`RANDOM}};
  inflight_opcodes = _RAND_10[1535:0];
  _RAND_11 = {24{`RANDOM}};
  inflight_sizes = _RAND_11[767:0];
  _RAND_12 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  watchdog = _RAND_14[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLMonitor_62(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [1:0]  io_in_a_bits_size,
  input  [6:0]  io_in_a_bits_source,
  input  [28:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_size,
  input  [6:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [95:0] _RAND_10;
  reg [383:0] _RAND_11;
  reg [383:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [95:0] _RAND_16;
  reg [383:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T_4 = io_in_a_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire [4:0] _is_aligned_mask_T_1 = 5'h3 << io_in_a_bits_size; // @[package.scala 234:77]
  wire [1:0] is_aligned_mask = ~_is_aligned_mask_T_1[1:0]; // @[package.scala 234:46]
  wire [28:0] _GEN_71 = {{27'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 2'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [28:0] _T_33 = io_in_a_bits_address ^ 29'h10014000; // @[Parameters.scala 137:31]
  wire [29:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
  wire [29:0] _T_36 = $signed(_T_34) & -30'sh1000; // @[Parameters.scala 137:52]
  wire  _T_37 = $signed(_T_36) == 30'sh0; // @[Parameters.scala 137:67]
  wire  _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_74 = _T_73 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_164 = io_in_a_bits_size <= 2'h2; // @[Parameters.scala 92:42]
  wire  _T_172 = _T_164 & _T_37; // @[Parameters.scala 670:56]
  wire  _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_218 = _source_ok_T_4 & _T_172; // @[Monitor.scala 115:71]
  wire  _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_273 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_274 = io_in_a_bits_mask & _T_273; // @[Monitor.scala 127:31]
  wire  _T_275 = _T_274 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_279 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_347 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_355 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_385 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_397 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_10 = io_in_d_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire  _T_401 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_405 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 312:27]
  wire  _T_421 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_449 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_478 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_495 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_513 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [1:0] size; // @[Monitor.scala 386:22]
  reg [6:0] source; // @[Monitor.scala 387:22]
  reg [28:0] address; // @[Monitor.scala 388:22]
  wire  _T_543 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_544 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_548 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_552 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_556 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_560 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] size_1; // @[Monitor.scala 537:22]
  reg [6:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_567 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_568 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_576 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_580 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [95:0] inflight; // @[Monitor.scala 611:27]
  reg [383:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [383:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [8:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [9:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [383:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [383:0] _GEN_73 = {{368'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[383:1]}; // @[Monitor.scala 634:152]
  wire [383:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [383:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
  wire [383:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[383:1]}; // @[Monitor.scala 638:144]
  wire  _T_594 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [127:0] _a_set_wo_ready_T = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_597 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
  wire [8:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [9:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [1026:0] _GEN_1 = {{1023'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [1026:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
  wire [1025:0] _GEN_2 = {{1023'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [1025:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [95:0] _T_599 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_601 = ~_T_599[0]; // @[Monitor.scala 658:17]
  wire [127:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 652:72 653:28]
  wire [1026:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 1027'h0; // @[Monitor.scala 652:72 656:28]
  wire [1025:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 1026'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_605 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_607 = ~_T_401; // @[Monitor.scala 671:74]
  wire  _T_608 = io_in_d_valid & d_first_1 & ~_T_401; // @[Monitor.scala 671:71]
  wire [127:0] _d_clr_wo_ready_T = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [1038:0] _GEN_3 = {{1023'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [1038:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [127:0] _GEN_22 = d_first_done & d_first_1 & _T_607 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 675:91 676:21]
  wire [1038:0] _GEN_23 = d_first_done & d_first_1 & _T_607 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_594 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [95:0] _T_618 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_620 = _T_618[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_625 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_626 = io_in_d_bits_opcode == _GEN_32 | _T_625; // @[Monitor.scala 685:77]
  wire  _T_630 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_637 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_638 = io_in_d_bits_opcode == _GEN_48 | _T_637; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_642 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_652 = _T_605 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_607; // @[Monitor.scala 694:116]
  wire  _T_654 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [95:0] a_set = _GEN_16[95:0];
  wire [95:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [95:0] d_clr = _GEN_22[95:0];
  wire [95:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [95:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [383:0] a_opcodes_set = _GEN_19[383:0];
  wire [383:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [383:0] d_opcodes_clr = _GEN_23[383:0];
  wire [383:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [383:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [383:0] a_sizes_set = _GEN_20[383:0];
  wire [383:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [383:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_663 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [95:0] inflight_1; // @[Monitor.scala 723:35]
  reg [383:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [383:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [383:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
  wire [383:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[383:1]}; // @[Monitor.scala 747:146]
  wire  _T_689 = io_in_d_valid & d_first_2 & _T_401; // @[Monitor.scala 779:71]
  wire [127:0] _GEN_67 = d_first_done & d_first_2 & _T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 783:90 784:21]
  wire [1038:0] _GEN_68 = d_first_done & d_first_2 & _T_401 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 783:90 785:21]
  wire [95:0] _T_697 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_707 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [95:0] d_clr_1 = _GEN_67[95:0];
  wire [95:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [95:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [383:0] d_opcodes_clr_1 = _GEN_68[383:0];
  wire [383:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [383:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_727 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 1'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= 1'h0;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 96'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 384'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 384'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 1'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= 1'h0;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 96'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 384'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= 1'h0;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (d_first_done) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_172 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_172) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_275 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_275) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_309 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_309) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_347 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_347) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_385 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_397 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_397) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_478 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_478 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_495 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_495 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_513 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_513 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_544 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_544) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_548 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_548) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_552 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_552) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_556 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_556) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_560 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_560) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_568 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_568) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_576 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_576) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_580 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_580) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_601 & (_T_597 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_597 & ~reset & ~_T_601) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_620 & (_T_608 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & _T_2 & ~_T_620) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_626 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_626) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_630 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_630) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_638 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_638) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_642 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_642) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_654 & (_T_652 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_652 & _T_2 & ~_T_654) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_663 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_663) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_697[0] & (_T_689 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_689 & _T_2 & ~_T_697[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_707 & (_T_689 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_689 & _T_2 & ~_T_707) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_727 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_727) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[6:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[28:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[6:0];
  _RAND_10 = {3{`RANDOM}};
  inflight = _RAND_10[95:0];
  _RAND_11 = {12{`RANDOM}};
  inflight_opcodes = _RAND_11[383:0];
  _RAND_12 = {12{`RANDOM}};
  inflight_sizes = _RAND_12[383:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {3{`RANDOM}};
  inflight_1 = _RAND_16[95:0];
  _RAND_17 = {12{`RANDOM}};
  inflight_sizes_1 = _RAND_17[383:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module SPIFIFO(
  input        clock,
  input        reset,
  input  [1:0] io_ctrl_fmt_proto,
  input        io_ctrl_fmt_endian,
  input        io_ctrl_fmt_iodir,
  input  [3:0] io_ctrl_fmt_len,
  input  [1:0] io_ctrl_cs_mode,
  input  [3:0] io_ctrl_wm_tx,
  input  [3:0] io_ctrl_wm_rx,
  input        io_link_tx_ready,
  output       io_link_tx_valid,
  output [7:0] io_link_tx_bits,
  input        io_link_rx_valid,
  input  [7:0] io_link_rx_bits,
  output [7:0] io_link_cnt,
  output [1:0] io_link_fmt_proto,
  output       io_link_fmt_endian,
  output       io_link_fmt_iodir,
  output       io_link_cs_set,
  output       io_link_cs_clear,
  output       io_link_lock,
  output       io_tx_ready,
  input        io_tx_valid,
  input  [7:0] io_tx_bits,
  input        io_rx_ready,
  output       io_rx_valid,
  output [7:0] io_rx_bits,
  output       io_ip_txwm,
  output       io_ip_rxwm
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
  wire  txq_clock; // @[SPIFIFO.scala 22:19]
  wire  txq_reset; // @[SPIFIFO.scala 22:19]
  wire  txq_io_enq_ready; // @[SPIFIFO.scala 22:19]
  wire  txq_io_enq_valid; // @[SPIFIFO.scala 22:19]
  wire [7:0] txq_io_enq_bits; // @[SPIFIFO.scala 22:19]
  wire  txq_io_deq_ready; // @[SPIFIFO.scala 22:19]
  wire  txq_io_deq_valid; // @[SPIFIFO.scala 22:19]
  wire [7:0] txq_io_deq_bits; // @[SPIFIFO.scala 22:19]
  wire [3:0] txq_io_count; // @[SPIFIFO.scala 22:19]
  wire  rxq_clock; // @[SPIFIFO.scala 23:19]
  wire  rxq_reset; // @[SPIFIFO.scala 23:19]
  wire  rxq_io_enq_ready; // @[SPIFIFO.scala 23:19]
  wire  rxq_io_enq_valid; // @[SPIFIFO.scala 23:19]
  wire [7:0] rxq_io_enq_bits; // @[SPIFIFO.scala 23:19]
  wire  rxq_io_deq_ready; // @[SPIFIFO.scala 23:19]
  wire  rxq_io_deq_valid; // @[SPIFIFO.scala 23:19]
  wire [7:0] rxq_io_deq_bits; // @[SPIFIFO.scala 23:19]
  wire [3:0] rxq_io_count; // @[SPIFIFO.scala 23:19]
  wire  fire_tx = io_link_tx_ready & io_link_tx_valid; // @[Decoupled.scala 50:35]
  reg  rxen; // @[SPIFIFO.scala 30:17]
  wire  _T = 2'h0 == io_link_fmt_proto; // @[SPIConsts.scala 13:48]
  wire  _T_1 = 2'h1 == io_link_fmt_proto; // @[SPIConsts.scala 13:48]
  wire  _T_2 = 2'h2 == io_link_fmt_proto; // @[SPIConsts.scala 13:48]
  wire [3:0] _cnt_quot_T_3 = _T ? io_ctrl_fmt_len : 4'h0; // @[Mux.scala 27:73]
  wire [2:0] _cnt_quot_T_4 = _T_1 ? io_ctrl_fmt_len[3:1] : 3'h0; // @[Mux.scala 27:73]
  wire [1:0] _cnt_quot_T_5 = _T_2 ? io_ctrl_fmt_len[3:2] : 2'h0; // @[Mux.scala 27:73]
  wire [3:0] _GEN_2 = {{1'd0}, _cnt_quot_T_4}; // @[Mux.scala 27:73]
  wire [3:0] _cnt_quot_T_6 = _cnt_quot_T_3 | _GEN_2; // @[Mux.scala 27:73]
  wire [3:0] _GEN_3 = {{2'd0}, _cnt_quot_T_5}; // @[Mux.scala 27:73]
  wire [3:0] cnt_quot = _cnt_quot_T_6 | _GEN_3; // @[Mux.scala 27:73]
  wire  _cnt_rmdr_T_1 = |io_ctrl_fmt_len[0]; // @[SPIFIFO.scala 45:92]
  wire  _cnt_rmdr_T_3 = |io_ctrl_fmt_len[1:0]; // @[SPIFIFO.scala 45:92]
  wire  cnt_rmdr = _T_1 & _cnt_rmdr_T_1 | _T_2 & _cnt_rmdr_T_3; // @[Mux.scala 27:73]
  wire [3:0] _GEN_4 = {{3'd0}, cnt_rmdr}; // @[SPIFIFO.scala 47:27]
  wire [3:0] _io_link_cnt_T_1 = cnt_quot + _GEN_4; // @[SPIFIFO.scala 47:27]
  reg [1:0] cs_mode; // @[SPIFIFO.scala 49:24]
  wire  cs_mode_hold = cs_mode == 2'h2; // @[SPIFIFO.scala 50:31]
  wire  cs_mode_off = cs_mode == 2'h3; // @[SPIFIFO.scala 51:30]
  wire  cs_update = cs_mode != io_ctrl_cs_mode; // @[SPIFIFO.scala 52:28]
  wire  cs_clear = ~(cs_mode_hold | cs_mode_off); // @[SPIFIFO.scala 53:18]
  QueueCompatibility txq ( // @[SPIFIFO.scala 22:19]
    .clock(txq_clock),
    .reset(txq_reset),
    .io_enq_ready(txq_io_enq_ready),
    .io_enq_valid(txq_io_enq_valid),
    .io_enq_bits(txq_io_enq_bits),
    .io_deq_ready(txq_io_deq_ready),
    .io_deq_valid(txq_io_deq_valid),
    .io_deq_bits(txq_io_deq_bits),
    .io_count(txq_io_count)
  );
  QueueCompatibility rxq ( // @[SPIFIFO.scala 23:19]
    .clock(rxq_clock),
    .reset(rxq_reset),
    .io_enq_ready(rxq_io_enq_ready),
    .io_enq_valid(rxq_io_enq_valid),
    .io_enq_bits(rxq_io_enq_bits),
    .io_deq_ready(rxq_io_deq_ready),
    .io_deq_valid(rxq_io_deq_valid),
    .io_deq_bits(rxq_io_deq_bits),
    .io_count(rxq_io_count)
  );
  assign io_link_tx_valid = txq_io_deq_valid; // @[SPIFIFO.scala 26:14]
  assign io_link_tx_bits = txq_io_deq_bits; // @[SPIFIFO.scala 26:14]
  assign io_link_cnt = {{4'd0}, _io_link_cnt_T_1}; // @[SPIFIFO.scala 47:15]
  assign io_link_fmt_proto = io_ctrl_fmt_proto; // @[SPIFIFO.scala 46:15]
  assign io_link_fmt_endian = io_ctrl_fmt_endian; // @[SPIFIFO.scala 46:15]
  assign io_link_fmt_iodir = io_ctrl_fmt_iodir; // @[SPIFIFO.scala 46:15]
  assign io_link_cs_set = ~cs_mode_off; // @[SPIFIFO.scala 55:21]
  assign io_link_cs_clear = cs_update | fire_tx & cs_clear; // @[SPIFIFO.scala 56:33]
  assign io_link_lock = io_link_tx_valid | rxen; // @[SPIFIFO.scala 59:36]
  assign io_tx_ready = txq_io_enq_ready; // @[SPIFIFO.scala 25:14]
  assign io_rx_valid = rxq_io_deq_valid; // @[SPIFIFO.scala 34:9]
  assign io_rx_bits = rxq_io_deq_bits; // @[SPIFIFO.scala 34:9]
  assign io_ip_txwm = txq_io_count < io_ctrl_wm_tx; // @[SPIFIFO.scala 61:31]
  assign io_ip_rxwm = rxq_io_count > io_ctrl_wm_rx; // @[SPIFIFO.scala 62:31]
  assign txq_clock = clock;
  assign txq_reset = reset;
  assign txq_io_enq_valid = io_tx_valid; // @[SPIFIFO.scala 25:14]
  assign txq_io_enq_bits = io_tx_bits; // @[SPIFIFO.scala 25:14]
  assign txq_io_deq_ready = io_link_tx_ready; // @[SPIFIFO.scala 26:14]
  assign rxq_clock = clock;
  assign rxq_reset = reset;
  assign rxq_io_enq_valid = io_link_rx_valid & rxen; // @[SPIFIFO.scala 32:40]
  assign rxq_io_enq_bits = io_link_rx_bits; // @[SPIFIFO.scala 33:19]
  assign rxq_io_deq_ready = io_rx_ready; // @[SPIFIFO.scala 34:9]
  always @(posedge clock) begin
    if (reset) begin // @[SPIFIFO.scala 30:17]
      rxen <= 1'h0; // @[SPIFIFO.scala 30:17]
    end else if (fire_tx) begin // @[SPIFIFO.scala 39:18]
      rxen <= ~io_link_fmt_iodir; // @[SPIFIFO.scala 40:10]
    end else if (io_link_rx_valid) begin // @[SPIFIFO.scala 36:18]
      rxen <= 1'h0; // @[SPIFIFO.scala 37:10]
    end
    if (reset) begin // @[SPIFIFO.scala 49:24]
      cs_mode <= 2'h0; // @[SPIFIFO.scala 49:24]
    end else begin
      cs_mode <= io_ctrl_cs_mode; // @[SPIFIFO.scala 49:24]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  rxen = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  cs_mode = _RAND_1[1:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module SPIPhysical(
  input         clock,
  input         reset,
  output        io_port_sck,
  input         io_port_dq_0_i,
  output        io_port_dq_0_o,
  output        io_port_dq_0_oe,
  input         io_port_dq_1_i,
  output        io_port_dq_1_o,
  output        io_port_dq_1_oe,
  input         io_port_dq_2_i,
  output        io_port_dq_2_o,
  output        io_port_dq_2_oe,
  input         io_port_dq_3_i,
  output        io_port_dq_3_o,
  output        io_port_dq_3_oe,
  input  [11:0] io_ctrl_sck_div,
  input         io_ctrl_sck_pol,
  input         io_ctrl_sck_pha,
  input  [1:0]  io_ctrl_fmt_proto,
  input         io_ctrl_fmt_endian,
  input         io_ctrl_fmt_iodir,
  input  [11:0] io_ctrl_extradel_coarse,
  input  [4:0]  io_ctrl_sampledel_sd,
  output        io_op_ready,
  input         io_op_valid,
  input         io_op_bits_fn,
  input         io_op_bits_stb,
  input  [7:0]  io_op_bits_cnt,
  input  [7:0]  io_op_bits_data,
  output        io_rx_valid,
  output [7:0]  io_rx_bits
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
`endif // RANDOMIZE_REG_INIT
  reg [11:0] ctrl_sck_div; // @[SPIPhysical.scala 52:17]
  reg  ctrl_sck_pol; // @[SPIPhysical.scala 52:17]
  reg  ctrl_sck_pha; // @[SPIPhysical.scala 52:17]
  reg [1:0] ctrl_fmt_proto; // @[SPIPhysical.scala 52:17]
  reg  ctrl_fmt_endian; // @[SPIPhysical.scala 52:17]
  reg  ctrl_fmt_iodir; // @[SPIPhysical.scala 52:17]
  wire  proto_0 = 2'h0 == ctrl_fmt_proto; // @[SPIConsts.scala 13:48]
  wire  proto_1 = 2'h1 == ctrl_fmt_proto; // @[SPIConsts.scala 13:48]
  wire  proto_2 = 2'h2 == ctrl_fmt_proto; // @[SPIConsts.scala 13:48]
  reg  setup_d; // @[SPIPhysical.scala 60:20]
  reg [7:0] scnt; // @[SPIPhysical.scala 62:17]
  reg [11:0] tcnt; // @[SPIPhysical.scala 63:17]
  wire  stop = scnt == 8'h0; // @[SPIPhysical.scala 65:20]
  wire  beat = tcnt == 12'h0; // @[SPIPhysical.scala 66:20]
  wire [11:0] _GEN_78 = {{7'd0}, io_ctrl_sampledel_sd}; // @[SPIPhysical.scala 69:49]
  wire [11:0] totalCoarseDel = io_ctrl_extradel_coarse + _GEN_78; // @[SPIPhysical.scala 69:49]
  reg  sample_d; // @[SPIPhysical.scala 70:25]
  reg [11:0] del_cntr; // @[SPIPhysical.scala 71:25]
  reg  xfr; // @[SPIPhysical.scala 182:16]
  reg  cref; // @[SPIPhysical.scala 117:17]
  wire  _GEN_10 = xfr & cref; // @[SPIPhysical.scala 190:18 192:16]
  wire  _GEN_15 = beat & _GEN_10; // @[SPIPhysical.scala 188:17]
  wire  sample = stop ? 1'h0 : _GEN_15; // @[SPIPhysical.scala 184:15]
  wire [11:0] _del_cntr_T_1 = totalCoarseDel - 12'h1; // @[SPIPhysical.scala 75:34]
  wire [11:0] _del_cntr_T_3 = del_cntr - 12'h1; // @[SPIPhysical.scala 82:28]
  wire  _T_3 = del_cntr == 12'h1; // @[SPIPhysical.scala 86:18]
  reg  last_d; // @[SPIPhysical.scala 92:23]
  reg [11:0] del_cntr_last; // @[SPIPhysical.scala 93:30]
  wire  last = scnt == 8'h1 & (beat & cref & xfr); // @[SPIPhysical.scala 201:27 202:10]
  wire [11:0] _del_cntr_last_T_3 = del_cntr_last - 12'h1; // @[SPIPhysical.scala 103:38]
  wire  _T_7 = del_cntr_last == 12'h1; // @[SPIPhysical.scala 107:23]
  wire [11:0] _decr_T = beat ? {{4'd0}, scnt} : tcnt; // @[SPIPhysical.scala 112:17]
  wire [11:0] decr = _decr_T - 12'h1; // @[SPIPhysical.scala 112:36]
  wire  sched = stop | beat; // @[SPIPhysical.scala 184:15 185:11]
  reg  sck; // @[SPIPhysical.scala 116:16]
  wire  cinv = ctrl_sck_pha ^ ctrl_sck_pol; // @[SPIPhysical.scala 118:27]
  wire [3:0] rxd = {io_port_dq_3_i,io_port_dq_2_i,io_port_dq_1_i,io_port_dq_0_i}; // @[Cat.scala 31:58]
  wire  rxd_delayed_0 = rxd[0]; // @[SPIPhysical.scala 135:24]
  wire  rxd_delayed_1 = rxd[1]; // @[SPIPhysical.scala 135:24]
  wire  rxd_delayed_2 = rxd[2]; // @[SPIPhysical.scala 135:24]
  wire  rxd_delayed_3 = rxd[3]; // @[SPIPhysical.scala 135:24]
  wire [3:0] rxd_fin = {rxd_delayed_3,rxd_delayed_2,rxd_delayed_1,rxd_delayed_0}; // @[SPIPhysical.scala 138:29]
  wire  samples_0 = rxd_fin[1]; // @[SPIPhysical.scala 139:28]
  wire [1:0] samples_1 = rxd_fin[1:0]; // @[SPIPhysical.scala 139:40]
  reg [7:0] buffer; // @[SPIPhysical.scala 141:19]
  wire [7:0] _buffer_in_T_9 = {io_op_bits_data[0],io_op_bits_data[1],io_op_bits_data[2],io_op_bits_data[3],
    io_op_bits_data[4],io_op_bits_data[5],io_op_bits_data[6],io_op_bits_data[7]}; // @[Cat.scala 31:58]
  wire [7:0] buffer_in = ~io_ctrl_fmt_endian ? io_op_bits_data : _buffer_in_T_9; // @[SPIPhysical.scala 121:8]
  wire  shift = totalCoarseDel > 12'h0 ? setup_d | sample_d & stop : sample_d; // @[SPIPhysical.scala 143:19]
  wire [6:0] _buffer_T_2 = shift ? buffer[6:0] : buffer[7:1]; // @[SPIPhysical.scala 147:12]
  wire  _buffer_T_4 = sample_d ? samples_0 : buffer[0]; // @[SPIPhysical.scala 148:12]
  wire [7:0] _buffer_T_5 = {_buffer_T_2,_buffer_T_4}; // @[Cat.scala 31:58]
  wire [5:0] _buffer_T_8 = shift ? buffer[5:0] : buffer[7:2]; // @[SPIPhysical.scala 147:12]
  wire [1:0] _buffer_T_10 = sample_d ? samples_1 : buffer[1:0]; // @[SPIPhysical.scala 148:12]
  wire [7:0] _buffer_T_11 = {_buffer_T_8,_buffer_T_10}; // @[Cat.scala 31:58]
  wire [3:0] _buffer_T_14 = shift ? buffer[3:0] : buffer[7:4]; // @[SPIPhysical.scala 147:12]
  wire [3:0] _buffer_T_16 = sample_d ? rxd_fin : buffer[3:0]; // @[SPIPhysical.scala 148:12]
  wire [7:0] _buffer_T_17 = {_buffer_T_14,_buffer_T_16}; // @[Cat.scala 31:58]
  wire [7:0] _buffer_T_18 = proto_0 ? _buffer_T_5 : 8'h0; // @[Mux.scala 27:73]
  wire [7:0] _buffer_T_19 = proto_1 ? _buffer_T_11 : 8'h0; // @[Mux.scala 27:73]
  wire [7:0] _buffer_T_20 = proto_2 ? _buffer_T_17 : 8'h0; // @[Mux.scala 27:73]
  wire [7:0] _buffer_T_21 = _buffer_T_18 | _buffer_T_19; // @[Mux.scala 27:73]
  wire [7:0] _buffer_T_22 = _buffer_T_21 | _buffer_T_20; // @[Mux.scala 27:73]
  reg [3:0] txd; // @[SPIPhysical.scala 153:16]
  wire  _T_18 = ~cref; // @[SPIPhysical.scala 203:19]
  wire  _GEN_25 = beat & ~cref | stop; // @[SPIPhysical.scala 203:26 204:14]
  wire  accept = scnt == 8'h1 ? _GEN_25 : stop; // @[SPIPhysical.scala 201:27]
  wire [3:0] txd_in = accept ? buffer_in[7:4] : buffer[7:4]; // @[SPIPhysical.scala 154:19]
  wire [1:0] _txd_sel_T = accept ? io_ctrl_fmt_proto : ctrl_fmt_proto; // @[SPIPhysical.scala 155:39]
  wire  txd_sel_0 = 2'h0 == _txd_sel_T; // @[SPIConsts.scala 13:48]
  wire  txd_sel_1 = 2'h1 == _txd_sel_T; // @[SPIConsts.scala 13:48]
  wire  txd_sel_2 = 2'h2 == _txd_sel_T; // @[SPIConsts.scala 13:48]
  wire  txd_shf_0 = txd_in[3]; // @[SPIPhysical.scala 156:55]
  wire [1:0] txd_shf_1 = txd_in[3:2]; // @[SPIPhysical.scala 156:55]
  wire  _txd_T = txd_sel_0 & txd_shf_0; // @[Mux.scala 27:73]
  wire [1:0] _txd_T_1 = txd_sel_1 ? txd_shf_1 : 2'h0; // @[Mux.scala 27:73]
  wire [3:0] _txd_T_2 = txd_sel_2 ? txd_in : 4'h0; // @[Mux.scala 27:73]
  wire [1:0] _GEN_79 = {{1'd0}, _txd_T}; // @[Mux.scala 27:73]
  wire [1:0] _txd_T_3 = _GEN_79 | _txd_T_1; // @[Mux.scala 27:73]
  wire [3:0] _GEN_80 = {{2'd0}, _txd_T_3}; // @[Mux.scala 27:73]
  wire [3:0] _txd_T_4 = _GEN_80 | _txd_T_2; // @[Mux.scala 27:73]
  reg  done; // @[SPIPhysical.scala 176:17]
  wire  _T_21 = ~io_op_bits_fn; // @[SPIPhysical.scala 220:22]
  wire  _GEN_11 = xfr & _T_18; // @[SPIPhysical.scala 190:18 193:15]
  wire  _GEN_16 = beat & _GEN_11; // @[SPIPhysical.scala 188:17]
  wire  _GEN_23 = stop ? 1'h0 : _GEN_16; // @[SPIPhysical.scala 184:15]
  wire  _GEN_26 = beat & ~cref ? 1'h0 : _GEN_23; // @[SPIPhysical.scala 203:26 205:13]
  wire  _GEN_30 = scnt == 8'h1 ? _GEN_26 : _GEN_23; // @[SPIPhysical.scala 201:27]
  wire  _GEN_45 = ~io_op_bits_fn | _GEN_30; // @[SPIPhysical.scala 220:22 224:17]
  wire  _GEN_59 = io_op_valid ? _GEN_45 : _GEN_30; // @[SPIPhysical.scala 212:24]
  wire  setup = accept & done ? _GEN_59 : _GEN_30; // @[SPIPhysical.scala 210:25]
  wire  txen_2 = proto_2 & ctrl_fmt_iodir; // @[SPIPhysical.scala 162:49]
  wire  txen_1 = proto_1 & ctrl_fmt_iodir | txen_2; // @[SPIPhysical.scala 162:82]
  wire [7:0] _io_rx_bits_T_9 = {buffer[0],buffer[1],buffer[2],buffer[3],buffer[4],buffer[5],buffer[6],buffer[7]}; // @[Cat.scala 31:58]
  wire  _GEN_9 = xfr ? cref ^ cinv : sck; // @[SPIPhysical.scala 190:18 191:13 116:16]
  wire [11:0] _GEN_12 = _T_18 ? decr : {{4'd0}, scnt}; // @[SPIPhysical.scala 195:20 196:14 62:17]
  wire  _GEN_13 = beat ? _T_18 : cref; // @[SPIPhysical.scala 188:17 189:12 117:17]
  wire  _GEN_14 = beat ? _GEN_9 : sck; // @[SPIPhysical.scala 116:16 188:17]
  wire [11:0] _GEN_17 = beat ? _GEN_12 : {{4'd0}, scnt}; // @[SPIPhysical.scala 188:17 62:17]
  wire  _GEN_20 = stop ? cref : _GEN_13; // @[SPIPhysical.scala 184:15 117:17]
  wire  _GEN_21 = stop ? sck : _GEN_14; // @[SPIPhysical.scala 184:15 116:16]
  wire [11:0] _GEN_24 = stop ? {{4'd0}, scnt} : _GEN_17; // @[SPIPhysical.scala 184:15 62:17]
  wire  _GEN_27 = beat & ~cref ? ctrl_sck_pol : _GEN_21; // @[SPIPhysical.scala 203:26 206:11]
  wire  _GEN_31 = scnt == 8'h1 ? _GEN_27 : _GEN_21; // @[SPIPhysical.scala 201:27]
  wire  _GEN_35 = io_op_bits_stb ? io_ctrl_sck_pol : _GEN_31; // @[SPIPhysical.scala 229:25 230:17]
  wire [11:0] _GEN_36 = io_op_bits_stb ? io_ctrl_sck_div : ctrl_sck_div; // @[SPIPhysical.scala 229:25 231:22 52:17]
  wire  _GEN_37 = io_op_bits_stb ? io_ctrl_sck_pol : ctrl_sck_pol; // @[SPIPhysical.scala 229:25 231:22 52:17]
  wire  _GEN_38 = io_op_bits_stb ? io_ctrl_sck_pha : ctrl_sck_pha; // @[SPIPhysical.scala 229:25 231:22 52:17]
  wire  _GEN_46 = ~io_op_bits_fn ? io_op_bits_cnt == 8'h0 : done | last_d; // @[SPIPhysical.scala 220:22 225:16 177:8]
  wire [11:0] _GEN_51 = io_op_valid ? {{4'd0}, io_op_bits_cnt} : _GEN_24; // @[SPIPhysical.scala 212:24 213:12]
  wire  _GEN_60 = io_op_valid ? _GEN_46 : done | last_d; // @[SPIPhysical.scala 212:24 177:8]
  wire [11:0] _GEN_65 = accept & done ? _GEN_51 : _GEN_24; // @[SPIPhysical.scala 210:25]
  wire  _GEN_74 = accept & done ? _GEN_60 : done | last_d; // @[SPIPhysical.scala 210:25 177:8]
  assign io_port_sck = sck; // @[SPIPhysical.scala 166:15]
  assign io_port_dq_0_o = txd[0]; // @[SPIPhysical.scala 168:24]
  assign io_port_dq_0_oe = proto_0 | txen_1; // @[SPIPhysical.scala 162:82]
  assign io_port_dq_1_o = txd[1]; // @[SPIPhysical.scala 168:24]
  assign io_port_dq_1_oe = proto_1 & ctrl_fmt_iodir | txen_2; // @[SPIPhysical.scala 162:82]
  assign io_port_dq_2_o = txd[2]; // @[SPIPhysical.scala 168:24]
  assign io_port_dq_2_oe = proto_2 & ctrl_fmt_iodir; // @[SPIPhysical.scala 162:49]
  assign io_port_dq_3_o = txd[3]; // @[SPIPhysical.scala 168:24]
  assign io_port_dq_3_oe = proto_2 & ctrl_fmt_iodir; // @[SPIPhysical.scala 162:49]
  assign io_op_ready = accept & done; // @[SPIPhysical.scala 210:16]
  assign io_rx_valid = done; // @[SPIPhysical.scala 179:15]
  assign io_rx_bits = ~ctrl_fmt_endian ? buffer : _io_rx_bits_T_9; // @[SPIPhysical.scala 121:8]
  always @(posedge clock) begin
    if (accept & done) begin // @[SPIPhysical.scala 210:25]
      if (io_op_valid) begin // @[SPIPhysical.scala 212:24]
        if (!(~io_op_bits_fn)) begin // @[SPIPhysical.scala 220:22]
          if (io_op_bits_fn) begin // @[SPIPhysical.scala 220:22]
            ctrl_sck_div <= _GEN_36;
          end
        end
      end
    end
    if (accept & done) begin // @[SPIPhysical.scala 210:25]
      if (io_op_valid) begin // @[SPIPhysical.scala 212:24]
        if (!(~io_op_bits_fn)) begin // @[SPIPhysical.scala 220:22]
          if (io_op_bits_fn) begin // @[SPIPhysical.scala 220:22]
            ctrl_sck_pol <= _GEN_37;
          end
        end
      end
    end
    if (accept & done) begin // @[SPIPhysical.scala 210:25]
      if (io_op_valid) begin // @[SPIPhysical.scala 212:24]
        if (!(~io_op_bits_fn)) begin // @[SPIPhysical.scala 220:22]
          if (io_op_bits_fn) begin // @[SPIPhysical.scala 220:22]
            ctrl_sck_pha <= _GEN_38;
          end
        end
      end
    end
    if (accept & done) begin // @[SPIPhysical.scala 210:25]
      if (io_op_valid) begin // @[SPIPhysical.scala 212:24]
        if (io_op_bits_stb) begin // @[SPIPhysical.scala 215:21]
          ctrl_fmt_proto <= io_ctrl_fmt_proto; // @[SPIPhysical.scala 216:18]
        end
      end
    end
    if (accept & done) begin // @[SPIPhysical.scala 210:25]
      if (io_op_valid) begin // @[SPIPhysical.scala 212:24]
        if (io_op_bits_stb) begin // @[SPIPhysical.scala 215:21]
          ctrl_fmt_endian <= io_ctrl_fmt_endian; // @[SPIPhysical.scala 216:18]
        end
      end
    end
    if (accept & done) begin // @[SPIPhysical.scala 210:25]
      if (io_op_valid) begin // @[SPIPhysical.scala 212:24]
        if (io_op_bits_stb) begin // @[SPIPhysical.scala 215:21]
          ctrl_fmt_iodir <= io_ctrl_fmt_iodir; // @[SPIPhysical.scala 216:18]
        end
      end
    end
    if (accept & done) begin // @[SPIPhysical.scala 210:25]
      if (io_op_valid) begin // @[SPIPhysical.scala 212:24]
        setup_d <= _GEN_45;
      end else begin
        setup_d <= _GEN_30;
      end
    end else begin
      setup_d <= _GEN_30;
    end
    if (reset) begin // @[SPIPhysical.scala 62:17]
      scnt <= 8'h0; // @[SPIPhysical.scala 62:17]
    end else begin
      scnt <= _GEN_65[7:0];
    end
    if (sched) begin // @[SPIPhysical.scala 114:14]
      tcnt <= ctrl_sck_div;
    end else begin
      tcnt <= decr;
    end
    if (reset) begin // @[SPIPhysical.scala 70:25]
      sample_d <= 1'h0; // @[SPIPhysical.scala 70:25]
    end else begin
      sample_d <= _T_3;
    end
    if (reset) begin // @[SPIPhysical.scala 71:25]
      del_cntr <= 12'h3; // @[SPIPhysical.scala 71:25]
    end else if (beat & sample) begin // @[SPIPhysical.scala 73:25]
      if (totalCoarseDel > 12'h1) begin // @[SPIPhysical.scala 74:32]
        del_cntr <= _del_cntr_T_1; // @[SPIPhysical.scala 75:16]
      end else begin
        del_cntr <= 12'h1; // @[SPIPhysical.scala 78:16]
      end
    end else if (del_cntr != 12'h0) begin // @[SPIPhysical.scala 81:27]
      del_cntr <= _del_cntr_T_3; // @[SPIPhysical.scala 82:16]
    end
    if (accept & done) begin // @[SPIPhysical.scala 210:25]
      if (io_op_valid) begin // @[SPIPhysical.scala 212:24]
        xfr <= _T_21;
      end
    end
    cref <= reset | _GEN_20; // @[SPIPhysical.scala 117:{17,17}]
    if (reset) begin // @[SPIPhysical.scala 92:23]
      last_d <= 1'h0; // @[SPIPhysical.scala 92:23]
    end else begin
      last_d <= _T_7;
    end
    if (reset) begin // @[SPIPhysical.scala 93:30]
      del_cntr_last <= 12'h3; // @[SPIPhysical.scala 93:30]
    end else if (beat & last) begin // @[SPIPhysical.scala 94:23]
      if (totalCoarseDel > 12'h1) begin // @[SPIPhysical.scala 74:32]
        del_cntr_last <= _del_cntr_T_1; // @[SPIPhysical.scala 75:16]
      end else begin
        del_cntr_last <= 12'h1; // @[SPIPhysical.scala 78:16]
      end
    end else if (del_cntr_last != 12'h0) begin // @[SPIPhysical.scala 102:33]
      del_cntr_last <= _del_cntr_last_T_3; // @[SPIPhysical.scala 103:21]
    end
    if (accept & done) begin // @[SPIPhysical.scala 210:25]
      if (io_op_valid) begin // @[SPIPhysical.scala 212:24]
        if (~io_op_bits_fn) begin // @[SPIPhysical.scala 220:22]
          sck <= cinv; // @[SPIPhysical.scala 223:15]
        end else if (io_op_bits_fn) begin // @[SPIPhysical.scala 220:22]
          sck <= _GEN_35;
        end else begin
          sck <= _GEN_31;
        end
      end else begin
        sck <= _GEN_31;
      end
    end else begin
      sck <= _GEN_31;
    end
    if (accept & done) begin // @[SPIPhysical.scala 210:25]
      if (io_op_valid) begin // @[SPIPhysical.scala 212:24]
        if (~io_op_bits_fn) begin // @[SPIPhysical.scala 220:22]
          if (~io_ctrl_fmt_endian) begin // @[SPIPhysical.scala 121:8]
            buffer <= io_op_bits_data;
          end else begin
            buffer <= _buffer_in_T_9;
          end
        end else begin
          buffer <= _buffer_T_22; // @[SPIPhysical.scala 144:10]
        end
      end else begin
        buffer <= _buffer_T_22; // @[SPIPhysical.scala 144:10]
      end
    end else begin
      buffer <= _buffer_T_22; // @[SPIPhysical.scala 144:10]
    end
    if (reset) begin // @[SPIPhysical.scala 153:16]
      txd <= 4'h0; // @[SPIPhysical.scala 153:16]
    end else if (setup) begin // @[SPIPhysical.scala 157:16]
      txd <= _txd_T_4; // @[SPIPhysical.scala 158:9]
    end
    done <= reset | _GEN_74; // @[SPIPhysical.scala 176:{17,17}]
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  ctrl_sck_div = _RAND_0[11:0];
  _RAND_1 = {1{`RANDOM}};
  ctrl_sck_pol = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  ctrl_sck_pha = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  ctrl_fmt_proto = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  ctrl_fmt_endian = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  ctrl_fmt_iodir = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  setup_d = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  scnt = _RAND_7[7:0];
  _RAND_8 = {1{`RANDOM}};
  tcnt = _RAND_8[11:0];
  _RAND_9 = {1{`RANDOM}};
  sample_d = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  del_cntr = _RAND_10[11:0];
  _RAND_11 = {1{`RANDOM}};
  xfr = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  cref = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  last_d = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  del_cntr_last = _RAND_14[11:0];
  _RAND_15 = {1{`RANDOM}};
  sck = _RAND_15[0:0];
  _RAND_16 = {1{`RANDOM}};
  buffer = _RAND_16[7:0];
  _RAND_17 = {1{`RANDOM}};
  txd = _RAND_17[3:0];
  _RAND_18 = {1{`RANDOM}};
  done = _RAND_18[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module SPIMedia(
  input         clock,
  input         reset,
  output        io_port_sck,
  input         io_port_dq_0_i,
  output        io_port_dq_0_o,
  output        io_port_dq_0_oe,
  input         io_port_dq_1_i,
  output        io_port_dq_1_o,
  output        io_port_dq_1_oe,
  input         io_port_dq_2_i,
  output        io_port_dq_2_o,
  output        io_port_dq_2_oe,
  input         io_port_dq_3_i,
  output        io_port_dq_3_o,
  output        io_port_dq_3_oe,
  output        io_port_cs_0,
  input  [11:0] io_ctrl_sck_div,
  input         io_ctrl_sck_pol,
  input         io_ctrl_sck_pha,
  input  [7:0]  io_ctrl_dla_cssck,
  input  [7:0]  io_ctrl_dla_sckcs,
  input  [7:0]  io_ctrl_dla_intercs,
  input  [7:0]  io_ctrl_dla_interxfr,
  input         io_ctrl_cs_id,
  input         io_ctrl_cs_dflt_0,
  input  [11:0] io_ctrl_extradel_coarse,
  input  [4:0]  io_ctrl_sampledel_sd,
  output        io_link_tx_ready,
  input         io_link_tx_valid,
  input  [7:0]  io_link_tx_bits,
  output        io_link_rx_valid,
  output [7:0]  io_link_rx_bits,
  input  [7:0]  io_link_cnt,
  input  [1:0]  io_link_fmt_proto,
  input         io_link_fmt_endian,
  input         io_link_fmt_iodir,
  input         io_link_cs_set,
  input         io_link_cs_clear,
  input         io_link_cs_hold,
  output        io_link_active
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
`endif // RANDOMIZE_REG_INIT
  wire  phy_clock; // @[SPIMedia.scala 36:19]
  wire  phy_reset; // @[SPIMedia.scala 36:19]
  wire  phy_io_port_sck; // @[SPIMedia.scala 36:19]
  wire  phy_io_port_dq_0_i; // @[SPIMedia.scala 36:19]
  wire  phy_io_port_dq_0_o; // @[SPIMedia.scala 36:19]
  wire  phy_io_port_dq_0_oe; // @[SPIMedia.scala 36:19]
  wire  phy_io_port_dq_1_i; // @[SPIMedia.scala 36:19]
  wire  phy_io_port_dq_1_o; // @[SPIMedia.scala 36:19]
  wire  phy_io_port_dq_1_oe; // @[SPIMedia.scala 36:19]
  wire  phy_io_port_dq_2_i; // @[SPIMedia.scala 36:19]
  wire  phy_io_port_dq_2_o; // @[SPIMedia.scala 36:19]
  wire  phy_io_port_dq_2_oe; // @[SPIMedia.scala 36:19]
  wire  phy_io_port_dq_3_i; // @[SPIMedia.scala 36:19]
  wire  phy_io_port_dq_3_o; // @[SPIMedia.scala 36:19]
  wire  phy_io_port_dq_3_oe; // @[SPIMedia.scala 36:19]
  wire [11:0] phy_io_ctrl_sck_div; // @[SPIMedia.scala 36:19]
  wire  phy_io_ctrl_sck_pol; // @[SPIMedia.scala 36:19]
  wire  phy_io_ctrl_sck_pha; // @[SPIMedia.scala 36:19]
  wire [1:0] phy_io_ctrl_fmt_proto; // @[SPIMedia.scala 36:19]
  wire  phy_io_ctrl_fmt_endian; // @[SPIMedia.scala 36:19]
  wire  phy_io_ctrl_fmt_iodir; // @[SPIMedia.scala 36:19]
  wire [11:0] phy_io_ctrl_extradel_coarse; // @[SPIMedia.scala 36:19]
  wire [4:0] phy_io_ctrl_sampledel_sd; // @[SPIMedia.scala 36:19]
  wire  phy_io_op_ready; // @[SPIMedia.scala 36:19]
  wire  phy_io_op_valid; // @[SPIMedia.scala 36:19]
  wire  phy_io_op_bits_fn; // @[SPIMedia.scala 36:19]
  wire  phy_io_op_bits_stb; // @[SPIMedia.scala 36:19]
  wire [7:0] phy_io_op_bits_cnt; // @[SPIMedia.scala 36:19]
  wire [7:0] phy_io_op_bits_data; // @[SPIMedia.scala 36:19]
  wire  phy_io_rx_valid; // @[SPIMedia.scala 36:19]
  wire [7:0] phy_io_rx_bits; // @[SPIMedia.scala 36:19]
  reg  cs_id; // @[SPIMedia.scala 50:15]
  reg  cs_dflt_0; // @[SPIMedia.scala 50:15]
  reg  cs_set; // @[SPIMedia.scala 51:19]
  wire [1:0] _GEN_4 = {{1'd0}, io_link_cs_set}; // @[SPIBundle.scala 49:19]
  wire [1:0] cs_active_mask = _GEN_4 << io_ctrl_cs_id; // @[SPIBundle.scala 49:19]
  wire [1:0] _GEN_54 = {{1'd0}, io_ctrl_cs_dflt_0}; // @[SPIBundle.scala 50:33]
  wire [1:0] cs_active_out = _GEN_54 ^ cs_active_mask; // @[SPIBundle.scala 50:33]
  wire  cs_active_0 = cs_active_out[0]; // @[SPIBundle.scala 51:32]
  wire  cs_update = cs_active_0 != cs_dflt_0; // @[SPIMedia.scala 53:37]
  reg  clear; // @[SPIMedia.scala 55:18]
  reg  cs_assert; // @[SPIMedia.scala 56:22]
  wire  cs_deassert = clear | cs_update & ~io_link_cs_hold; // @[SPIMedia.scala 57:27]
  wire  continuous = io_ctrl_dla_interxfr == 8'h0; // @[SPIMedia.scala 61:42]
  reg [1:0] state; // @[SPIMedia.scala 72:18]
  wire [1:0] _GEN_0 = phy_io_op_ready ? 2'h2 : state; // @[SPIMedia.scala 72:18 79:27 80:19]
  wire  _T_1 = phy_io_op_ready & phy_io_op_valid; // @[Decoupled.scala 50:35]
  wire [1:0] _GEN_1 = _T_1 ? 2'h1 : state; // @[SPIMedia.scala 72:18 88:28 89:19]
  wire [7:0] _GEN_2 = cs_deassert ? io_ctrl_dla_sckcs : io_link_cnt; // @[SPIMedia.scala 46:15 77:28 78:23]
  wire  _GEN_5 = cs_deassert ? 1'h0 : 1'h1; // @[SPIMedia.scala 45:15 77:28 84:23]
  wire  _GEN_6 = cs_deassert | io_link_tx_valid; // @[SPIMedia.scala 43:12 77:28 86:20]
  wire  _GEN_7 = cs_deassert ? 1'h0 : phy_io_op_ready; // @[SPIMedia.scala 68:20 77:28 87:28]
  wire  _GEN_8 = phy_io_op_ready | cs_assert; // @[SPIMedia.scala 95:25 96:21 56:22]
  wire [7:0] _GEN_11 = io_link_tx_valid ? io_ctrl_dla_cssck : 8'h0; // @[SPIMedia.scala 102:21 92:38 94:21]
  wire  _GEN_15 = io_link_tx_valid ? 1'h0 : 1'h1; // @[SPIMedia.scala 45:15 103:21 92:38]
  wire [7:0] _GEN_17 = cs_assert ? _GEN_2 : _GEN_11; // @[SPIMedia.scala 76:24]
  wire  _GEN_19 = cs_assert ? cs_deassert : 1'h1; // @[SPIMedia.scala 44:14 76:24]
  wire  _GEN_20 = cs_assert ? _GEN_5 : _GEN_15; // @[SPIMedia.scala 76:24]
  wire  _GEN_21 = cs_assert ? _GEN_6 : 1'h1; // @[SPIMedia.scala 43:12 76:24]
  wire  _GEN_22 = cs_assert & _GEN_7; // @[SPIMedia.scala 68:20 76:24]
  wire [1:0] _GEN_31 = {{1'd0}, cs_set}; // @[SPIBundle.scala 49:19]
  wire [1:0] mask = _GEN_31 << cs_id; // @[SPIBundle.scala 49:19]
  wire [1:0] _GEN_55 = {{1'd0}, cs_dflt_0}; // @[SPIBundle.scala 50:33]
  wire [1:0] out = _GEN_55 ^ mask; // @[SPIBundle.scala 50:33]
  wire [1:0] _GEN_29 = phy_io_op_ready ? 2'h0 : state; // @[SPIMedia.scala 123:23 125:15 72:18]
  wire [7:0] _GEN_30 = 2'h2 == state ? io_ctrl_dla_intercs : io_link_cnt; // @[SPIMedia.scala 74:18 119:19 46:15]
  wire  _GEN_36 = 2'h1 == state ? ~continuous : 1'h1; // @[SPIMedia.scala 110:16 43:12 74:18]
  wire [7:0] _GEN_37 = 2'h1 == state ? io_ctrl_dla_interxfr : _GEN_30; // @[SPIMedia.scala 74:18 111:19]
  wire  _GEN_39 = 2'h1 == state ? 1'h0 : 2'h2 == state; // @[SPIMedia.scala 45:15 74:18]
  SPIPhysical phy ( // @[SPIMedia.scala 36:19]
    .clock(phy_clock),
    .reset(phy_reset),
    .io_port_sck(phy_io_port_sck),
    .io_port_dq_0_i(phy_io_port_dq_0_i),
    .io_port_dq_0_o(phy_io_port_dq_0_o),
    .io_port_dq_0_oe(phy_io_port_dq_0_oe),
    .io_port_dq_1_i(phy_io_port_dq_1_i),
    .io_port_dq_1_o(phy_io_port_dq_1_o),
    .io_port_dq_1_oe(phy_io_port_dq_1_oe),
    .io_port_dq_2_i(phy_io_port_dq_2_i),
    .io_port_dq_2_o(phy_io_port_dq_2_o),
    .io_port_dq_2_oe(phy_io_port_dq_2_oe),
    .io_port_dq_3_i(phy_io_port_dq_3_i),
    .io_port_dq_3_o(phy_io_port_dq_3_o),
    .io_port_dq_3_oe(phy_io_port_dq_3_oe),
    .io_ctrl_sck_div(phy_io_ctrl_sck_div),
    .io_ctrl_sck_pol(phy_io_ctrl_sck_pol),
    .io_ctrl_sck_pha(phy_io_ctrl_sck_pha),
    .io_ctrl_fmt_proto(phy_io_ctrl_fmt_proto),
    .io_ctrl_fmt_endian(phy_io_ctrl_fmt_endian),
    .io_ctrl_fmt_iodir(phy_io_ctrl_fmt_iodir),
    .io_ctrl_extradel_coarse(phy_io_ctrl_extradel_coarse),
    .io_ctrl_sampledel_sd(phy_io_ctrl_sampledel_sd),
    .io_op_ready(phy_io_op_ready),
    .io_op_valid(phy_io_op_valid),
    .io_op_bits_fn(phy_io_op_bits_fn),
    .io_op_bits_stb(phy_io_op_bits_stb),
    .io_op_bits_cnt(phy_io_op_bits_cnt),
    .io_op_bits_data(phy_io_op_bits_data),
    .io_rx_valid(phy_io_rx_valid),
    .io_rx_bits(phy_io_rx_bits)
  );
  assign io_port_sck = phy_io_port_sck; // @[SPIMedia.scala 63:15]
  assign io_port_dq_0_o = phy_io_port_dq_0_o; // @[SPIMedia.scala 64:14]
  assign io_port_dq_0_oe = phy_io_port_dq_0_oe; // @[SPIMedia.scala 64:14]
  assign io_port_dq_1_o = phy_io_port_dq_1_o; // @[SPIMedia.scala 64:14]
  assign io_port_dq_1_oe = phy_io_port_dq_1_oe; // @[SPIMedia.scala 64:14]
  assign io_port_dq_2_o = phy_io_port_dq_2_o; // @[SPIMedia.scala 64:14]
  assign io_port_dq_2_oe = phy_io_port_dq_2_oe; // @[SPIMedia.scala 64:14]
  assign io_port_dq_3_o = phy_io_port_dq_3_o; // @[SPIMedia.scala 64:14]
  assign io_port_dq_3_oe = phy_io_port_dq_3_oe; // @[SPIMedia.scala 64:14]
  assign io_port_cs_0 = cs_dflt_0; // @[SPIMedia.scala 65:14]
  assign io_link_tx_ready = 2'h0 == state & _GEN_22; // @[SPIMedia.scala 74:18 68:20]
  assign io_link_rx_valid = phy_io_rx_valid; // @[SPIMedia.scala 67:14]
  assign io_link_rx_bits = phy_io_rx_bits; // @[SPIMedia.scala 67:14]
  assign io_link_active = cs_assert; // @[SPIMedia.scala 69:18]
  assign phy_clock = clock;
  assign phy_reset = reset;
  assign phy_io_port_dq_0_i = io_port_dq_0_i; // @[SPIMedia.scala 64:14]
  assign phy_io_port_dq_1_i = io_port_dq_1_i; // @[SPIMedia.scala 64:14]
  assign phy_io_port_dq_2_i = io_port_dq_2_i; // @[SPIMedia.scala 64:14]
  assign phy_io_port_dq_3_i = io_port_dq_3_i; // @[SPIMedia.scala 64:14]
  assign phy_io_ctrl_sck_div = io_ctrl_sck_div; // @[SPIMedia.scala 37:19]
  assign phy_io_ctrl_sck_pol = io_ctrl_sck_pol; // @[SPIMedia.scala 37:19]
  assign phy_io_ctrl_sck_pha = io_ctrl_sck_pha; // @[SPIMedia.scala 37:19]
  assign phy_io_ctrl_fmt_proto = io_link_fmt_proto; // @[SPIMedia.scala 38:19]
  assign phy_io_ctrl_fmt_endian = io_link_fmt_endian; // @[SPIMedia.scala 38:19]
  assign phy_io_ctrl_fmt_iodir = io_link_fmt_iodir; // @[SPIMedia.scala 38:19]
  assign phy_io_ctrl_extradel_coarse = io_ctrl_extradel_coarse; // @[SPIMedia.scala 39:24]
  assign phy_io_ctrl_sampledel_sd = io_ctrl_sampledel_sd; // @[SPIMedia.scala 40:25]
  assign phy_io_op_valid = 2'h0 == state ? _GEN_21 : _GEN_36; // @[SPIMedia.scala 74:18]
  assign phy_io_op_bits_fn = 2'h0 == state ? _GEN_19 : 1'h1; // @[SPIMedia.scala 44:14 74:18]
  assign phy_io_op_bits_stb = 2'h0 == state ? _GEN_20 : _GEN_39; // @[SPIMedia.scala 74:18]
  assign phy_io_op_bits_cnt = 2'h0 == state ? _GEN_17 : _GEN_37; // @[SPIMedia.scala 74:18]
  assign phy_io_op_bits_data = io_link_tx_bits; // @[SPIMedia.scala 47:16]
  always @(posedge clock) begin
    if (2'h0 == state) begin // @[SPIMedia.scala 74:18]
      if (!(cs_assert)) begin // @[SPIMedia.scala 76:24]
        if (!(io_link_tx_valid)) begin // @[SPIMedia.scala 92:38]
          cs_id <= io_ctrl_cs_id; // @[SPIMedia.scala 104:12]
        end
      end
    end
    if (2'h0 == state) begin // @[SPIMedia.scala 74:18]
      if (!(cs_assert)) begin // @[SPIMedia.scala 76:24]
        if (io_link_tx_valid) begin // @[SPIMedia.scala 92:38]
          if (phy_io_op_ready) begin // @[SPIMedia.scala 95:25]
            cs_dflt_0 <= cs_active_0; // @[SPIMedia.scala 98:19]
          end
        end else begin
          cs_dflt_0 <= io_ctrl_cs_dflt_0; // @[SPIMedia.scala 104:12]
        end
      end
    end else if (!(2'h1 == state)) begin // @[SPIMedia.scala 74:18]
      if (2'h2 == state) begin // @[SPIMedia.scala 74:18]
        if (phy_io_op_ready) begin // @[SPIMedia.scala 123:23]
          cs_dflt_0 <= out[0]; // @[SPIMedia.scala 124:17]
        end
      end
    end
    if (2'h0 == state) begin // @[SPIMedia.scala 74:18]
      if (!(cs_assert)) begin // @[SPIMedia.scala 76:24]
        if (io_link_tx_valid) begin // @[SPIMedia.scala 92:38]
          if (phy_io_op_ready) begin // @[SPIMedia.scala 95:25]
            cs_set <= io_link_cs_set; // @[SPIMedia.scala 97:18]
          end
        end
      end
    end
    if (reset) begin // @[SPIMedia.scala 55:18]
      clear <= 1'h0; // @[SPIMedia.scala 55:18]
    end else if (2'h0 == state) begin // @[SPIMedia.scala 74:18]
      clear <= clear | io_link_cs_clear & cs_assert; // @[SPIMedia.scala 59:9]
    end else if (2'h1 == state) begin // @[SPIMedia.scala 74:18]
      clear <= clear | io_link_cs_clear & cs_assert; // @[SPIMedia.scala 59:9]
    end else if (2'h2 == state) begin // @[SPIMedia.scala 74:18]
      clear <= 1'h0; // @[SPIMedia.scala 122:13]
    end else begin
      clear <= clear | io_link_cs_clear & cs_assert; // @[SPIMedia.scala 59:9]
    end
    if (reset) begin // @[SPIMedia.scala 56:22]
      cs_assert <= 1'h0; // @[SPIMedia.scala 56:22]
    end else if (2'h0 == state) begin // @[SPIMedia.scala 74:18]
      if (!(cs_assert)) begin // @[SPIMedia.scala 76:24]
        if (io_link_tx_valid) begin // @[SPIMedia.scala 92:38]
          cs_assert <= _GEN_8;
        end
      end
    end else if (!(2'h1 == state)) begin // @[SPIMedia.scala 74:18]
      if (2'h2 == state) begin // @[SPIMedia.scala 74:18]
        cs_assert <= 1'h0; // @[SPIMedia.scala 121:17]
      end
    end
    if (reset) begin // @[SPIMedia.scala 72:18]
      state <= 2'h0; // @[SPIMedia.scala 72:18]
    end else if (2'h0 == state) begin // @[SPIMedia.scala 74:18]
      if (cs_assert) begin // @[SPIMedia.scala 76:24]
        if (cs_deassert) begin // @[SPIMedia.scala 77:28]
          state <= _GEN_0;
        end else begin
          state <= _GEN_1;
        end
      end
    end else if (2'h1 == state) begin // @[SPIMedia.scala 74:18]
      if (phy_io_op_ready | continuous) begin // @[SPIMedia.scala 112:37]
        state <= 2'h0; // @[SPIMedia.scala 113:15]
      end
    end else if (2'h2 == state) begin // @[SPIMedia.scala 74:18]
      state <= _GEN_29;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  cs_id = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  cs_dflt_0 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  cs_set = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  clear = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  cs_assert = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  state = _RAND_5[1:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module SPIFlashMap(
  input         clock,
  input         reset,
  input         io_en,
  input  [1:0]  io_ctrl_insn_cmd_proto,
  input  [7:0]  io_ctrl_insn_cmd_code,
  input         io_ctrl_insn_cmd_en,
  input  [1:0]  io_ctrl_insn_addr_proto,
  input  [2:0]  io_ctrl_insn_addr_len,
  input  [7:0]  io_ctrl_insn_pad_code,
  input  [3:0]  io_ctrl_insn_pad_cnt,
  input  [1:0]  io_ctrl_insn_data_proto,
  input         io_ctrl_fmt_endian,
  output        io_addr_ready,
  input         io_addr_valid,
  input  [31:0] io_addr_bits_next,
  input  [31:0] io_addr_bits_hold,
  input         io_data_ready,
  output        io_data_valid,
  output [7:0]  io_data_bits,
  input         io_link_tx_ready,
  output        io_link_tx_valid,
  output [7:0]  io_link_tx_bits,
  input         io_link_rx_valid,
  input  [7:0]  io_link_rx_bits,
  output [7:0]  io_link_cnt,
  output [1:0]  io_link_fmt_proto,
  output        io_link_fmt_endian,
  output        io_link_fmt_iodir,
  output        io_link_cs_clear,
  input         io_link_active,
  output        io_link_lock
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] addr = io_addr_bits_hold + 32'h1; // @[SPIFlash.scala 59:32]
  wire  merge = io_link_active & io_addr_bits_next == addr; // @[SPIFlash.scala 60:30]
  wire  _io_link_cnt_T = 2'h0 == io_link_fmt_proto; // @[SPIConsts.scala 13:48]
  wire  _io_link_cnt_T_1 = 2'h1 == io_link_fmt_proto; // @[SPIConsts.scala 13:48]
  wire  _io_link_cnt_T_2 = 2'h2 == io_link_fmt_proto; // @[SPIConsts.scala 13:48]
  wire [3:0] _io_link_cnt_T_3 = _io_link_cnt_T ? 4'h8 : 4'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_link_cnt_T_4 = _io_link_cnt_T_1 ? 3'h4 : 3'h0; // @[Mux.scala 27:73]
  wire [1:0] _io_link_cnt_T_5 = _io_link_cnt_T_2 ? 2'h2 : 2'h0; // @[Mux.scala 27:73]
  wire [3:0] _GEN_73 = {{1'd0}, _io_link_cnt_T_4}; // @[Mux.scala 27:73]
  wire [3:0] _io_link_cnt_T_6 = _io_link_cnt_T_3 | _GEN_73; // @[Mux.scala 27:73]
  wire [3:0] _GEN_74 = {{2'd0}, _io_link_cnt_T_5}; // @[Mux.scala 27:73]
  wire [3:0] _io_link_cnt_T_7 = _io_link_cnt_T_6 | _GEN_74; // @[Mux.scala 27:73]
  reg [3:0] cnt; // @[SPIFlash.scala 81:16]
  wire  cnt_cmp_0 = cnt == 4'h0; // @[SPIFlash.scala 83:48]
  wire  cnt_cmp_1 = cnt == 4'h1; // @[SPIFlash.scala 83:48]
  wire  cnt_cmp_2 = cnt == 4'h2; // @[SPIFlash.scala 83:48]
  wire  cnt_cmp_3 = cnt == 4'h3; // @[SPIFlash.scala 83:48]
  wire  cnt_cmp_4 = cnt == 4'h4; // @[SPIFlash.scala 83:48]
  wire  cnt_last = cnt_cmp_1 & io_link_tx_ready; // @[SPIFlash.scala 85:29]
  wire  cnt_done = cnt_last | cnt_cmp_0; // @[SPIFlash.scala 86:27]
  wire  _T = io_link_tx_ready & io_link_tx_valid; // @[Decoupled.scala 50:35]
  wire [3:0] _cnt_T_1 = cnt - 4'h1; // @[SPIFlash.scala 90:18]
  wire [3:0] _GEN_0 = _T ? _cnt_T_1 : cnt; // @[SPIFlash.scala 89:30 90:11 81:16]
  reg [2:0] state; // @[SPIFlash.scala 95:18]
  wire  _GEN_54 = 3'h1 == state ? 1'h0 : 3'h2 == state; // @[SPIFlash.scala 97:18]
  wire  cnt_en = 3'h0 == state ? 1'h0 : _GEN_54; // @[SPIFlash.scala 97:18]
  wire  _GEN_1 = cnt_en ? ~cnt_cmp_0 : 1'h1; // @[SPIFlash.scala 87:17 63:20 88:22]
  wire [3:0] _GEN_2 = cnt_en ? _GEN_0 : cnt; // @[SPIFlash.scala 81:16 87:17]
  wire [2:0] _state_T = io_ctrl_insn_cmd_en ? 3'h1 : 3'h2; // @[SPIFlash.scala 106:25]
  wire [2:0] _GEN_3 = merge ? 3'h4 : _state_T; // @[SPIFlash.scala 103:24 104:19 106:19]
  wire  _GEN_4 = merge ? 1'h0 : 1'h1; // @[SPIFlash.scala 103:24 72:20 107:30]
  wire  _GEN_6 = io_addr_valid & _GEN_4; // @[SPIFlash.scala 102:30 72:20]
  wire  _GEN_11 = io_en & _GEN_6; // @[SPIFlash.scala 100:20 72:20]
  wire  _GEN_12 = io_en & io_addr_valid; // @[SPIFlash.scala 100:20 114:22]
  wire [7:0] _io_link_tx_bits_T_4 = cnt_cmp_1 ? io_addr_bits_hold[7:0] : 8'h0; // @[Mux.scala 27:73]
  wire [7:0] _io_link_tx_bits_T_5 = cnt_cmp_2 ? io_addr_bits_hold[15:8] : 8'h0; // @[Mux.scala 27:73]
  wire [7:0] _io_link_tx_bits_T_6 = cnt_cmp_3 ? io_addr_bits_hold[23:16] : 8'h0; // @[Mux.scala 27:73]
  wire [7:0] _io_link_tx_bits_T_7 = cnt_cmp_4 ? io_addr_bits_hold[31:24] : 8'h0; // @[Mux.scala 27:73]
  wire [7:0] _io_link_tx_bits_T_8 = _io_link_tx_bits_T_4 | _io_link_tx_bits_T_5; // @[Mux.scala 27:73]
  wire [7:0] _io_link_tx_bits_T_9 = _io_link_tx_bits_T_8 | _io_link_tx_bits_T_6; // @[Mux.scala 27:73]
  wire [7:0] _io_link_tx_bits_T_10 = _io_link_tx_bits_T_9 | _io_link_tx_bits_T_7; // @[Mux.scala 27:73]
  wire [2:0] _GEN_15 = cnt_done ? 3'h3 : state; // @[SPIFlash.scala 139:23 140:15 95:18]
  wire [2:0] _GEN_16 = io_link_tx_ready ? 3'h4 : state; // @[SPIFlash.scala 148:31 149:15 95:18]
  wire [2:0] _GEN_17 = io_link_tx_ready ? 3'h5 : state; // @[SPIFlash.scala 156:31 157:15 95:18]
  wire  _T_7 = io_data_ready & io_data_valid; // @[Decoupled.scala 50:35]
  wire [2:0] _GEN_18 = _T_7 ? 3'h0 : state; // @[SPIFlash.scala 164:29 165:15 95:18]
  wire [2:0] _GEN_19 = io_data_ready ? 3'h0 : state; // @[SPIFlash.scala 172:28 173:15 95:18]
  wire [7:0] _GEN_21 = 3'h6 == state ? 8'h0 : io_link_rx_bits; // @[SPIFlash.scala 97:18 171:20 79:16]
  wire [2:0] _GEN_22 = 3'h6 == state ? _GEN_19 : state; // @[SPIFlash.scala 95:18 97:18]
  wire  _GEN_23 = 3'h5 == state ? 1'h0 : _GEN_1; // @[SPIFlash.scala 97:18 162:24]
  wire  _GEN_24 = 3'h5 == state ? io_link_rx_valid : 3'h6 == state; // @[SPIFlash.scala 97:18 163:21]
  wire [2:0] _GEN_25 = 3'h5 == state ? _GEN_18 : _GEN_22; // @[SPIFlash.scala 97:18]
  wire [7:0] _GEN_26 = 3'h5 == state ? io_link_rx_bits : _GEN_21; // @[SPIFlash.scala 79:16 97:18]
  wire [1:0] _GEN_27 = 3'h4 == state ? io_ctrl_insn_data_proto : io_ctrl_insn_addr_proto; // @[SPIFlash.scala 97:18 154:25 64:21]
  wire  _GEN_28 = 3'h4 == state ? 1'h0 : 1'h1; // @[SPIFlash.scala 97:18 155:25 65:21]
  wire [2:0] _GEN_29 = 3'h4 == state ? _GEN_17 : _GEN_25; // @[SPIFlash.scala 97:18]
  wire  _GEN_30 = 3'h4 == state ? _GEN_1 : _GEN_23; // @[SPIFlash.scala 97:18]
  wire  _GEN_31 = 3'h4 == state ? 1'h0 : _GEN_24; // @[SPIFlash.scala 78:17 97:18]
  wire [7:0] _GEN_32 = 3'h4 == state ? io_link_rx_bits : _GEN_26; // @[SPIFlash.scala 79:16 97:18]
  wire [3:0] _GEN_33 = 3'h3 == state ? io_ctrl_insn_pad_cnt : _io_link_cnt_T_7; // @[SPIFlash.scala 97:18 145:19 67:15]
  wire [2:0] _GEN_35 = 3'h3 == state ? _GEN_16 : _GEN_29; // @[SPIFlash.scala 97:18]
  wire [1:0] _GEN_36 = 3'h3 == state ? io_ctrl_insn_addr_proto : _GEN_27; // @[SPIFlash.scala 97:18 64:21]
  wire  _GEN_38 = 3'h3 == state ? _GEN_1 : _GEN_30; // @[SPIFlash.scala 97:18]
  wire  _GEN_39 = 3'h3 == state ? 1'h0 : _GEN_31; // @[SPIFlash.scala 78:17 97:18]
  wire [7:0] _GEN_40 = 3'h3 == state ? io_link_rx_bits : _GEN_32; // @[SPIFlash.scala 79:16 97:18]
  wire [7:0] _GEN_41 = 3'h2 == state ? _io_link_tx_bits_T_10 : io_ctrl_insn_pad_code; // @[SPIFlash.scala 97:18 131:23]
  wire [3:0] _GEN_44 = 3'h2 == state ? _io_link_cnt_T_7 : _GEN_33; // @[SPIFlash.scala 67:15 97:18]
  wire [1:0] _GEN_45 = 3'h2 == state ? io_ctrl_insn_addr_proto : _GEN_36; // @[SPIFlash.scala 97:18 64:21]
  wire  _GEN_47 = 3'h2 == state ? _GEN_1 : _GEN_38; // @[SPIFlash.scala 97:18]
  wire  _GEN_48 = 3'h2 == state ? 1'h0 : _GEN_39; // @[SPIFlash.scala 78:17 97:18]
  wire [7:0] _GEN_49 = 3'h2 == state ? io_link_rx_bits : _GEN_40; // @[SPIFlash.scala 79:16 97:18]
  wire [1:0] _GEN_50 = 3'h1 == state ? io_ctrl_insn_cmd_proto : _GEN_45; // @[SPIFlash.scala 97:18 122:25]
  wire [3:0] _GEN_55 = 3'h1 == state ? _io_link_cnt_T_7 : _GEN_44; // @[SPIFlash.scala 67:15 97:18]
  wire  _GEN_57 = 3'h1 == state ? _GEN_1 : _GEN_47; // @[SPIFlash.scala 97:18]
  wire  _GEN_58 = 3'h1 == state ? 1'h0 : _GEN_48; // @[SPIFlash.scala 78:17 97:18]
  wire [7:0] _GEN_59 = 3'h1 == state ? io_link_rx_bits : _GEN_49; // @[SPIFlash.scala 79:16 97:18]
  wire [3:0] _GEN_69 = 3'h0 == state ? _io_link_cnt_T_7 : _GEN_55; // @[SPIFlash.scala 67:15 97:18]
  assign io_addr_ready = 3'h0 == state; // @[SPIFlash.scala 97:18]
  assign io_data_valid = 3'h0 == state ? 1'h0 : _GEN_58; // @[SPIFlash.scala 78:17 97:18]
  assign io_data_bits = 3'h0 == state ? io_link_rx_bits : _GEN_59; // @[SPIFlash.scala 79:16 97:18]
  assign io_link_tx_valid = 3'h0 == state ? 1'h0 : _GEN_57; // @[SPIFlash.scala 97:18 99:24]
  assign io_link_tx_bits = 3'h1 == state ? io_ctrl_insn_cmd_code : _GEN_41; // @[SPIFlash.scala 97:18 123:23]
  assign io_link_cnt = {{4'd0}, _GEN_69};
  assign io_link_fmt_proto = 3'h0 == state ? io_ctrl_insn_addr_proto : _GEN_50; // @[SPIFlash.scala 97:18 64:21]
  assign io_link_fmt_endian = io_ctrl_fmt_endian; // @[SPIFlash.scala 66:22]
  assign io_link_fmt_iodir = 3'h0 == state | (3'h1 == state | (3'h2 == state | (3'h3 == state | _GEN_28))); // @[SPIFlash.scala 97:18 65:21]
  assign io_link_cs_clear = 3'h0 == state & _GEN_11; // @[SPIFlash.scala 97:18 72:20]
  assign io_link_lock = 3'h0 == state ? _GEN_12 : 1'h1; // @[SPIFlash.scala 74:16 97:18]
  always @(posedge clock) begin
    if (3'h0 == state) begin // @[SPIFlash.scala 97:18]
      cnt <= _GEN_2;
    end else if (3'h1 == state) begin // @[SPIFlash.scala 97:18]
      if (io_link_tx_ready) begin // @[SPIFlash.scala 124:31]
        cnt <= {{1'd0}, io_ctrl_insn_addr_len}; // @[SPIFlash.scala 126:13]
      end else begin
        cnt <= _GEN_2;
      end
    end else begin
      cnt <= _GEN_2;
    end
    if (reset) begin // @[SPIFlash.scala 95:18]
      state <= 3'h0; // @[SPIFlash.scala 95:18]
    end else if (3'h0 == state) begin // @[SPIFlash.scala 97:18]
      if (io_en) begin // @[SPIFlash.scala 100:20]
        if (io_addr_valid) begin // @[SPIFlash.scala 102:30]
          state <= _GEN_3;
        end
      end else if (io_addr_valid) begin // @[SPIFlash.scala 115:30]
        state <= 3'h6; // @[SPIFlash.scala 116:17]
      end
    end else if (3'h1 == state) begin // @[SPIFlash.scala 97:18]
      if (io_link_tx_ready) begin // @[SPIFlash.scala 124:31]
        state <= 3'h2; // @[SPIFlash.scala 125:15]
      end
    end else if (3'h2 == state) begin // @[SPIFlash.scala 97:18]
      state <= _GEN_15;
    end else begin
      state <= _GEN_35;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  cnt = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  state = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module SPIArbiter(
  input        clock,
  input        reset,
  output       io_inner_0_tx_ready,
  input        io_inner_0_tx_valid,
  input  [7:0] io_inner_0_tx_bits,
  output       io_inner_0_rx_valid,
  output [7:0] io_inner_0_rx_bits,
  input  [7:0] io_inner_0_cnt,
  input  [1:0] io_inner_0_fmt_proto,
  input        io_inner_0_fmt_endian,
  input        io_inner_0_fmt_iodir,
  input        io_inner_0_cs_clear,
  output       io_inner_0_active,
  input        io_inner_0_lock,
  output       io_inner_1_tx_ready,
  input        io_inner_1_tx_valid,
  input  [7:0] io_inner_1_tx_bits,
  output       io_inner_1_rx_valid,
  output [7:0] io_inner_1_rx_bits,
  input  [7:0] io_inner_1_cnt,
  input  [1:0] io_inner_1_fmt_proto,
  input        io_inner_1_fmt_endian,
  input        io_inner_1_fmt_iodir,
  input        io_inner_1_cs_set,
  input        io_inner_1_cs_clear,
  input        io_inner_1_lock,
  input        io_outer_tx_ready,
  output       io_outer_tx_valid,
  output [7:0] io_outer_tx_bits,
  input        io_outer_rx_valid,
  input  [7:0] io_outer_rx_bits,
  output [7:0] io_outer_cnt,
  output [1:0] io_outer_fmt_proto,
  output       io_outer_fmt_endian,
  output       io_outer_fmt_iodir,
  output       io_outer_cs_set,
  output       io_outer_cs_clear,
  output       io_outer_cs_hold,
  input        io_outer_active,
  input        io_sel
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
  reg  sel_0; // @[SPIArbiter.scala 18:16]
  reg  sel_1; // @[SPIArbiter.scala 18:16]
  wire [7:0] _io_outer_tx_bits_T = sel_0 ? io_inner_0_tx_bits : 8'h0; // @[Mux.scala 27:73]
  wire [7:0] _io_outer_tx_bits_T_1 = sel_1 ? io_inner_1_tx_bits : 8'h0; // @[Mux.scala 27:73]
  wire [7:0] _io_outer_cnt_T = sel_0 ? io_inner_0_cnt : 8'h0; // @[Mux.scala 27:73]
  wire [7:0] _io_outer_cnt_T_1 = sel_1 ? io_inner_1_cnt : 8'h0; // @[Mux.scala 27:73]
  wire [1:0] _io_outer_fmt_T_6 = sel_0 ? io_inner_0_fmt_proto : 2'h0; // @[Mux.scala 27:73]
  wire [1:0] _io_outer_fmt_T_7 = sel_1 ? io_inner_1_fmt_proto : 2'h0; // @[Mux.scala 27:73]
  wire  _io_outer_cs_T_clear = sel_0 ? io_inner_0_cs_clear : io_inner_1_cs_clear; // @[SPIArbiter.scala 25:21]
  wire  nsel_0 = ~io_sel; // @[SPIArbiter.scala 36:37]
  wire  lock = sel_0 & io_inner_0_lock | sel_1 & io_inner_1_lock; // @[Mux.scala 27:73]
  wire [1:0] _T_1 = {sel_1,sel_0}; // @[SPIArbiter.scala 40:15]
  wire [1:0] _T_2 = {io_sel,nsel_0}; // @[SPIArbiter.scala 40:31]
  wire  _GEN_0 = _T_1 != _T_2 | _io_outer_cs_T_clear; // @[SPIArbiter.scala 25:15 40:39 41:25]
  wire  _GEN_1 = ~lock ? nsel_0 : sel_0; // @[SPIArbiter.scala 18:16 38:16 39:9]
  assign io_inner_0_tx_ready = io_outer_tx_ready & sel_0; // @[SPIArbiter.scala 30:41]
  assign io_inner_0_rx_valid = io_outer_rx_valid & sel_0; // @[SPIArbiter.scala 31:41]
  assign io_inner_0_rx_bits = io_outer_rx_bits; // @[SPIArbiter.scala 32:19]
  assign io_inner_0_active = io_outer_active & sel_0; // @[SPIArbiter.scala 33:37]
  assign io_inner_1_tx_ready = io_outer_tx_ready & sel_1; // @[SPIArbiter.scala 30:41]
  assign io_inner_1_rx_valid = io_outer_rx_valid & sel_1; // @[SPIArbiter.scala 31:41]
  assign io_inner_1_rx_bits = io_outer_rx_bits; // @[SPIArbiter.scala 32:19]
  assign io_outer_tx_valid = sel_0 & io_inner_0_tx_valid | sel_1 & io_inner_1_tx_valid; // @[Mux.scala 27:73]
  assign io_outer_tx_bits = _io_outer_tx_bits_T | _io_outer_tx_bits_T_1; // @[Mux.scala 27:73]
  assign io_outer_cnt = _io_outer_cnt_T | _io_outer_cnt_T_1; // @[Mux.scala 27:73]
  assign io_outer_fmt_proto = _io_outer_fmt_T_6 | _io_outer_fmt_T_7; // @[Mux.scala 27:73]
  assign io_outer_fmt_endian = sel_0 & io_inner_0_fmt_endian | sel_1 & io_inner_1_fmt_endian; // @[Mux.scala 27:73]
  assign io_outer_fmt_iodir = sel_0 & io_inner_0_fmt_iodir | sel_1 & io_inner_1_fmt_iodir; // @[Mux.scala 27:73]
  assign io_outer_cs_set = sel_0 | io_inner_1_cs_set; // @[SPIArbiter.scala 25:21]
  assign io_outer_cs_clear = ~lock ? _GEN_0 : _io_outer_cs_T_clear; // @[SPIArbiter.scala 25:15 38:16]
  assign io_outer_cs_hold = sel_0; // @[SPIArbiter.scala 25:21]
  always @(posedge clock) begin
    sel_0 <= reset | _GEN_1; // @[SPIArbiter.scala 18:{16,16}]
    if (reset) begin // @[SPIArbiter.scala 18:16]
      sel_1 <= 1'h0; // @[SPIArbiter.scala 18:16]
    end else if (~lock) begin // @[SPIArbiter.scala 38:16]
      sel_1 <= io_sel; // @[SPIArbiter.scala 39:9]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  sel_0 = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  sel_1 = _RAND_1[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLSPIFlash(
  input         clock,
  input         reset,
  output        auto_int_xing_out_sync_0,
  output        auto_mem_xing_in_a_ready,
  input         auto_mem_xing_in_a_valid,
  input  [2:0]  auto_mem_xing_in_a_bits_opcode,
  input  [2:0]  auto_mem_xing_in_a_bits_param,
  input         auto_mem_xing_in_a_bits_size,
  input  [8:0]  auto_mem_xing_in_a_bits_source,
  input  [29:0] auto_mem_xing_in_a_bits_address,
  input         auto_mem_xing_in_a_bits_mask,
  input         auto_mem_xing_in_a_bits_corrupt,
  input         auto_mem_xing_in_d_ready,
  output        auto_mem_xing_in_d_valid,
  output        auto_mem_xing_in_d_bits_size,
  output [8:0]  auto_mem_xing_in_d_bits_source,
  output [7:0]  auto_mem_xing_in_d_bits_data,
  output        auto_control_xing_in_a_ready,
  input         auto_control_xing_in_a_valid,
  input  [2:0]  auto_control_xing_in_a_bits_opcode,
  input  [2:0]  auto_control_xing_in_a_bits_param,
  input  [1:0]  auto_control_xing_in_a_bits_size,
  input  [6:0]  auto_control_xing_in_a_bits_source,
  input  [28:0] auto_control_xing_in_a_bits_address,
  input  [3:0]  auto_control_xing_in_a_bits_mask,
  input  [31:0] auto_control_xing_in_a_bits_data,
  input         auto_control_xing_in_a_bits_corrupt,
  input         auto_control_xing_in_d_ready,
  output        auto_control_xing_in_d_valid,
  output [2:0]  auto_control_xing_in_d_bits_opcode,
  output [1:0]  auto_control_xing_in_d_bits_size,
  output [6:0]  auto_control_xing_in_d_bits_source,
  output [31:0] auto_control_xing_in_d_bits_data,
  output        auto_io_out_sck,
  input         auto_io_out_dq_0_i,
  output        auto_io_out_dq_0_o,
  output        auto_io_out_dq_0_oe,
  input         auto_io_out_dq_1_i,
  output        auto_io_out_dq_1_o,
  output        auto_io_out_dq_1_oe,
  input         auto_io_out_dq_2_i,
  output        auto_io_out_dq_2_o,
  output        auto_io_out_dq_2_oe,
  input         auto_io_out_dq_3_i,
  output        auto_io_out_dq_3_o,
  output        auto_io_out_dq_3_oe,
  output        auto_io_out_cs_0
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
`endif // RANDOMIZE_REG_INIT
  wire  buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
  wire [28:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
  wire [28:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_in_a_bits_param; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_a_bits_size; // @[Buffer.scala 68:28]
  wire [8:0] buffer_1_auto_in_a_bits_source; // @[Buffer.scala 68:28]
  wire [29:0] buffer_1_auto_in_a_bits_address; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_d_valid; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_d_bits_size; // @[Buffer.scala 68:28]
  wire [8:0] buffer_1_auto_in_d_bits_source; // @[Buffer.scala 68:28]
  wire [7:0] buffer_1_auto_in_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_out_a_bits_param; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_a_bits_size; // @[Buffer.scala 68:28]
  wire [8:0] buffer_1_auto_out_a_bits_source; // @[Buffer.scala 68:28]
  wire [29:0] buffer_1_auto_out_a_bits_address; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_d_valid; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_d_bits_size; // @[Buffer.scala 68:28]
  wire [8:0] buffer_1_auto_out_d_bits_source; // @[Buffer.scala 68:28]
  wire [7:0] buffer_1_auto_out_d_bits_data; // @[Buffer.scala 68:28]
  wire  intsource_clock; // @[Crossing.scala 26:31]
  wire  intsource_reset; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_0; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_0; // @[Crossing.scala 26:31]
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [8:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [29:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [8:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  monitor_1_clock; // @[Nodes.scala 24:25]
  wire  monitor_1_reset; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_1_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_1_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [1:0] monitor_1_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_1_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [28:0] monitor_1_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_1_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_1_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_1_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_1_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  fifo_clock; // @[TLSPI.scala 69:20]
  wire  fifo_reset; // @[TLSPI.scala 69:20]
  wire [1:0] fifo_io_ctrl_fmt_proto; // @[TLSPI.scala 69:20]
  wire  fifo_io_ctrl_fmt_endian; // @[TLSPI.scala 69:20]
  wire  fifo_io_ctrl_fmt_iodir; // @[TLSPI.scala 69:20]
  wire [3:0] fifo_io_ctrl_fmt_len; // @[TLSPI.scala 69:20]
  wire [1:0] fifo_io_ctrl_cs_mode; // @[TLSPI.scala 69:20]
  wire [3:0] fifo_io_ctrl_wm_tx; // @[TLSPI.scala 69:20]
  wire [3:0] fifo_io_ctrl_wm_rx; // @[TLSPI.scala 69:20]
  wire  fifo_io_link_tx_ready; // @[TLSPI.scala 69:20]
  wire  fifo_io_link_tx_valid; // @[TLSPI.scala 69:20]
  wire [7:0] fifo_io_link_tx_bits; // @[TLSPI.scala 69:20]
  wire  fifo_io_link_rx_valid; // @[TLSPI.scala 69:20]
  wire [7:0] fifo_io_link_rx_bits; // @[TLSPI.scala 69:20]
  wire [7:0] fifo_io_link_cnt; // @[TLSPI.scala 69:20]
  wire [1:0] fifo_io_link_fmt_proto; // @[TLSPI.scala 69:20]
  wire  fifo_io_link_fmt_endian; // @[TLSPI.scala 69:20]
  wire  fifo_io_link_fmt_iodir; // @[TLSPI.scala 69:20]
  wire  fifo_io_link_cs_set; // @[TLSPI.scala 69:20]
  wire  fifo_io_link_cs_clear; // @[TLSPI.scala 69:20]
  wire  fifo_io_link_lock; // @[TLSPI.scala 69:20]
  wire  fifo_io_tx_ready; // @[TLSPI.scala 69:20]
  wire  fifo_io_tx_valid; // @[TLSPI.scala 69:20]
  wire [7:0] fifo_io_tx_bits; // @[TLSPI.scala 69:20]
  wire  fifo_io_rx_ready; // @[TLSPI.scala 69:20]
  wire  fifo_io_rx_valid; // @[TLSPI.scala 69:20]
  wire [7:0] fifo_io_rx_bits; // @[TLSPI.scala 69:20]
  wire  fifo_io_ip_txwm; // @[TLSPI.scala 69:20]
  wire  fifo_io_ip_rxwm; // @[TLSPI.scala 69:20]
  wire  mac_clock; // @[TLSPI.scala 70:19]
  wire  mac_reset; // @[TLSPI.scala 70:19]
  wire  mac_io_port_sck; // @[TLSPI.scala 70:19]
  wire  mac_io_port_dq_0_i; // @[TLSPI.scala 70:19]
  wire  mac_io_port_dq_0_o; // @[TLSPI.scala 70:19]
  wire  mac_io_port_dq_0_oe; // @[TLSPI.scala 70:19]
  wire  mac_io_port_dq_1_i; // @[TLSPI.scala 70:19]
  wire  mac_io_port_dq_1_o; // @[TLSPI.scala 70:19]
  wire  mac_io_port_dq_1_oe; // @[TLSPI.scala 70:19]
  wire  mac_io_port_dq_2_i; // @[TLSPI.scala 70:19]
  wire  mac_io_port_dq_2_o; // @[TLSPI.scala 70:19]
  wire  mac_io_port_dq_2_oe; // @[TLSPI.scala 70:19]
  wire  mac_io_port_dq_3_i; // @[TLSPI.scala 70:19]
  wire  mac_io_port_dq_3_o; // @[TLSPI.scala 70:19]
  wire  mac_io_port_dq_3_oe; // @[TLSPI.scala 70:19]
  wire  mac_io_port_cs_0; // @[TLSPI.scala 70:19]
  wire [11:0] mac_io_ctrl_sck_div; // @[TLSPI.scala 70:19]
  wire  mac_io_ctrl_sck_pol; // @[TLSPI.scala 70:19]
  wire  mac_io_ctrl_sck_pha; // @[TLSPI.scala 70:19]
  wire [7:0] mac_io_ctrl_dla_cssck; // @[TLSPI.scala 70:19]
  wire [7:0] mac_io_ctrl_dla_sckcs; // @[TLSPI.scala 70:19]
  wire [7:0] mac_io_ctrl_dla_intercs; // @[TLSPI.scala 70:19]
  wire [7:0] mac_io_ctrl_dla_interxfr; // @[TLSPI.scala 70:19]
  wire  mac_io_ctrl_cs_id; // @[TLSPI.scala 70:19]
  wire  mac_io_ctrl_cs_dflt_0; // @[TLSPI.scala 70:19]
  wire [11:0] mac_io_ctrl_extradel_coarse; // @[TLSPI.scala 70:19]
  wire [4:0] mac_io_ctrl_sampledel_sd; // @[TLSPI.scala 70:19]
  wire  mac_io_link_tx_ready; // @[TLSPI.scala 70:19]
  wire  mac_io_link_tx_valid; // @[TLSPI.scala 70:19]
  wire [7:0] mac_io_link_tx_bits; // @[TLSPI.scala 70:19]
  wire  mac_io_link_rx_valid; // @[TLSPI.scala 70:19]
  wire [7:0] mac_io_link_rx_bits; // @[TLSPI.scala 70:19]
  wire [7:0] mac_io_link_cnt; // @[TLSPI.scala 70:19]
  wire [1:0] mac_io_link_fmt_proto; // @[TLSPI.scala 70:19]
  wire  mac_io_link_fmt_endian; // @[TLSPI.scala 70:19]
  wire  mac_io_link_fmt_iodir; // @[TLSPI.scala 70:19]
  wire  mac_io_link_cs_set; // @[TLSPI.scala 70:19]
  wire  mac_io_link_cs_clear; // @[TLSPI.scala 70:19]
  wire  mac_io_link_cs_hold; // @[TLSPI.scala 70:19]
  wire  mac_io_link_active; // @[TLSPI.scala 70:19]
  wire  flash_clock; // @[TLSPIFlash.scala 57:21]
  wire  flash_reset; // @[TLSPIFlash.scala 57:21]
  wire  flash_io_en; // @[TLSPIFlash.scala 57:21]
  wire [1:0] flash_io_ctrl_insn_cmd_proto; // @[TLSPIFlash.scala 57:21]
  wire [7:0] flash_io_ctrl_insn_cmd_code; // @[TLSPIFlash.scala 57:21]
  wire  flash_io_ctrl_insn_cmd_en; // @[TLSPIFlash.scala 57:21]
  wire [1:0] flash_io_ctrl_insn_addr_proto; // @[TLSPIFlash.scala 57:21]
  wire [2:0] flash_io_ctrl_insn_addr_len; // @[TLSPIFlash.scala 57:21]
  wire [7:0] flash_io_ctrl_insn_pad_code; // @[TLSPIFlash.scala 57:21]
  wire [3:0] flash_io_ctrl_insn_pad_cnt; // @[TLSPIFlash.scala 57:21]
  wire [1:0] flash_io_ctrl_insn_data_proto; // @[TLSPIFlash.scala 57:21]
  wire  flash_io_ctrl_fmt_endian; // @[TLSPIFlash.scala 57:21]
  wire  flash_io_addr_ready; // @[TLSPIFlash.scala 57:21]
  wire  flash_io_addr_valid; // @[TLSPIFlash.scala 57:21]
  wire [31:0] flash_io_addr_bits_next; // @[TLSPIFlash.scala 57:21]
  wire [31:0] flash_io_addr_bits_hold; // @[TLSPIFlash.scala 57:21]
  wire  flash_io_data_ready; // @[TLSPIFlash.scala 57:21]
  wire  flash_io_data_valid; // @[TLSPIFlash.scala 57:21]
  wire [7:0] flash_io_data_bits; // @[TLSPIFlash.scala 57:21]
  wire  flash_io_link_tx_ready; // @[TLSPIFlash.scala 57:21]
  wire  flash_io_link_tx_valid; // @[TLSPIFlash.scala 57:21]
  wire [7:0] flash_io_link_tx_bits; // @[TLSPIFlash.scala 57:21]
  wire  flash_io_link_rx_valid; // @[TLSPIFlash.scala 57:21]
  wire [7:0] flash_io_link_rx_bits; // @[TLSPIFlash.scala 57:21]
  wire [7:0] flash_io_link_cnt; // @[TLSPIFlash.scala 57:21]
  wire [1:0] flash_io_link_fmt_proto; // @[TLSPIFlash.scala 57:21]
  wire  flash_io_link_fmt_endian; // @[TLSPIFlash.scala 57:21]
  wire  flash_io_link_fmt_iodir; // @[TLSPIFlash.scala 57:21]
  wire  flash_io_link_cs_clear; // @[TLSPIFlash.scala 57:21]
  wire  flash_io_link_active; // @[TLSPIFlash.scala 57:21]
  wire  flash_io_link_lock; // @[TLSPIFlash.scala 57:21]
  wire  arb_clock; // @[TLSPIFlash.scala 58:19]
  wire  arb_reset; // @[TLSPIFlash.scala 58:19]
  wire  arb_io_inner_0_tx_ready; // @[TLSPIFlash.scala 58:19]
  wire  arb_io_inner_0_tx_valid; // @[TLSPIFlash.scala 58:19]
  wire [7:0] arb_io_inner_0_tx_bits; // @[TLSPIFlash.scala 58:19]
  wire  arb_io_inner_0_rx_valid; // @[TLSPIFlash.scala 58:19]
  wire [7:0] arb_io_inner_0_rx_bits; // @[TLSPIFlash.scala 58:19]
  wire [7:0] arb_io_inner_0_cnt; // @[TLSPIFlash.scala 58:19]
  wire [1:0] arb_io_inner_0_fmt_proto; // @[TLSPIFlash.scala 58:19]
  wire  arb_io_inner_0_fmt_endian; // @[TLSPIFlash.scala 58:19]
  wire  arb_io_inner_0_fmt_iodir; // @[TLSPIFlash.scala 58:19]
  wire  arb_io_inner_0_cs_clear; // @[TLSPIFlash.scala 58:19]
  wire  arb_io_inner_0_active; // @[TLSPIFlash.scala 58:19]
  wire  arb_io_inner_0_lock; // @[TLSPIFlash.scala 58:19]
  wire  arb_io_inner_1_tx_ready; // @[TLSPIFlash.scala 58:19]
  wire  arb_io_inner_1_tx_valid; // @[TLSPIFlash.scala 58:19]
  wire [7:0] arb_io_inner_1_tx_bits; // @[TLSPIFlash.scala 58:19]
  wire  arb_io_inner_1_rx_valid; // @[TLSPIFlash.scala 58:19]
  wire [7:0] arb_io_inner_1_rx_bits; // @[TLSPIFlash.scala 58:19]
  wire [7:0] arb_io_inner_1_cnt; // @[TLSPIFlash.scala 58:19]
  wire [1:0] arb_io_inner_1_fmt_proto; // @[TLSPIFlash.scala 58:19]
  wire  arb_io_inner_1_fmt_endian; // @[TLSPIFlash.scala 58:19]
  wire  arb_io_inner_1_fmt_iodir; // @[TLSPIFlash.scala 58:19]
  wire  arb_io_inner_1_cs_set; // @[TLSPIFlash.scala 58:19]
  wire  arb_io_inner_1_cs_clear; // @[TLSPIFlash.scala 58:19]
  wire  arb_io_inner_1_lock; // @[TLSPIFlash.scala 58:19]
  wire  arb_io_outer_tx_ready; // @[TLSPIFlash.scala 58:19]
  wire  arb_io_outer_tx_valid; // @[TLSPIFlash.scala 58:19]
  wire [7:0] arb_io_outer_tx_bits; // @[TLSPIFlash.scala 58:19]
  wire  arb_io_outer_rx_valid; // @[TLSPIFlash.scala 58:19]
  wire [7:0] arb_io_outer_rx_bits; // @[TLSPIFlash.scala 58:19]
  wire [7:0] arb_io_outer_cnt; // @[TLSPIFlash.scala 58:19]
  wire [1:0] arb_io_outer_fmt_proto; // @[TLSPIFlash.scala 58:19]
  wire  arb_io_outer_fmt_endian; // @[TLSPIFlash.scala 58:19]
  wire  arb_io_outer_fmt_iodir; // @[TLSPIFlash.scala 58:19]
  wire  arb_io_outer_cs_set; // @[TLSPIFlash.scala 58:19]
  wire  arb_io_outer_cs_clear; // @[TLSPIFlash.scala 58:19]
  wire  arb_io_outer_cs_hold; // @[TLSPIFlash.scala 58:19]
  wire  arb_io_outer_active; // @[TLSPIFlash.scala 58:19]
  wire  arb_io_sel; // @[TLSPIFlash.scala 58:19]
  reg [1:0] ctrl_fmt_proto; // @[TLSPI.scala 68:17]
  reg  ctrl_fmt_endian; // @[TLSPI.scala 68:17]
  reg  ctrl_fmt_iodir; // @[TLSPI.scala 68:17]
  reg [3:0] ctrl_fmt_len; // @[TLSPI.scala 68:17]
  reg [11:0] ctrl_sck_div; // @[TLSPI.scala 68:17]
  reg  ctrl_sck_pol; // @[TLSPI.scala 68:17]
  reg  ctrl_sck_pha; // @[TLSPI.scala 68:17]
  reg  ctrl_cs_id; // @[TLSPI.scala 68:17]
  reg  ctrl_cs_dflt_0; // @[TLSPI.scala 68:17]
  reg [1:0] ctrl_cs_mode; // @[TLSPI.scala 68:17]
  reg [7:0] ctrl_dla_cssck; // @[TLSPI.scala 68:17]
  reg [7:0] ctrl_dla_sckcs; // @[TLSPI.scala 68:17]
  reg [7:0] ctrl_dla_intercs; // @[TLSPI.scala 68:17]
  reg [7:0] ctrl_dla_interxfr; // @[TLSPI.scala 68:17]
  reg [3:0] ctrl_wm_tx; // @[TLSPI.scala 68:17]
  reg [3:0] ctrl_wm_rx; // @[TLSPI.scala 68:17]
  reg [11:0] ctrl_extradel_coarse; // @[TLSPI.scala 68:17]
  reg [4:0] ctrl_sampledel_sd; // @[TLSPI.scala 68:17]
  reg  ie_txwm; // @[TLSPI.scala 82:15]
  reg  ie_rxwm; // @[TLSPI.scala 82:15]
  wire  _T = ~fifo_io_tx_ready; // @[RegMapFIFO.scala 25:9]
  wire  _T_1 = ~fifo_io_rx_valid; // @[RegMapFIFO.scala 46:21]
  reg  a_size; // @[TLSPIFlash.scala 66:14]
  reg [8:0] a_source; // @[TLSPIFlash.scala 66:14]
  reg [29:0] a_address; // @[TLSPIFlash.scala 66:14]
  wire  bundleIn_0_a_ready = flash_io_addr_ready; // @[Nodes.scala 1210:84 TLSPIFlash.scala 76:13]
  wire  bundleIn_0_a_valid = buffer_1_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  _T_2 = bundleIn_0_a_ready & bundleIn_0_a_valid; // @[Decoupled.scala 50:35]
  wire  bundleIn_0_a_bits_size = buffer_1_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [8:0] bundleIn_0_a_bits_source = buffer_1_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [29:0] bundleIn_0_a_bits_address = buffer_1_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  reg [1:0] insn_cmd_proto; // @[TLSPIFlash.scala 82:17]
  reg [7:0] insn_cmd_code; // @[TLSPIFlash.scala 82:17]
  reg  insn_cmd_en; // @[TLSPIFlash.scala 82:17]
  reg [1:0] insn_addr_proto; // @[TLSPIFlash.scala 82:17]
  reg [2:0] insn_addr_len; // @[TLSPIFlash.scala 82:17]
  reg [7:0] insn_pad_code; // @[TLSPIFlash.scala 82:17]
  reg [3:0] insn_pad_cnt; // @[TLSPIFlash.scala 82:17]
  reg [1:0] insn_data_proto; // @[TLSPIFlash.scala 82:17]
  reg  flash_en; // @[TLSPIFlash.scala 83:21]
  wire [2:0] bundleIn_0_1_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  in_bits_read = bundleIn_0_1_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 72:36]
  wire [28:0] bundleIn_0_1_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [9:0] in_bits_index = bundleIn_0_1_a_bits_address[11:2]; // @[RegisterRouter.scala 71:18 73:19]
  wire [9:0] out_findex = in_bits_index & 10'h3e0; // @[RegisterRouter.scala 83:24]
  wire  _out_T = out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [3:0] bundleIn_0_1_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [7:0] _out_frontMask_T_5 = bundleIn_0_1_a_bits_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_frontMask_T_7 = bundleIn_0_1_a_bits_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_frontMask_T_9 = bundleIn_0_1_a_bits_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_frontMask_T_11 = bundleIn_0_1_a_bits_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [31:0] out_frontMask = {_out_frontMask_T_11,_out_frontMask_T_9,_out_frontMask_T_7,_out_frontMask_T_5}; // @[Cat.scala 31:58]
  wire  out_wimask = &out_frontMask[11:0]; // @[RegisterRouter.scala 83:24]
  wire  bundleIn_0_1_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  bundleIn_0_1_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [4:0] out_oindex = {in_bits_index[4],in_bits_index[3],in_bits_index[2],in_bits_index[1],in_bits_index[0]}; // @[Cat.scala 31:58]
  wire [31:0] _out_frontSel_T = 32'h1 << out_oindex; // @[OneHot.scala 57:35]
  wire  out_frontSel_0 = _out_frontSel_T[0]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_0 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_0 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala 83:24]
  wire [31:0] bundleIn_0_1_a_bits_data = buffer_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  out_wimask_1 = &out_frontMask[0]; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_5 = _out_frontSel_T[5]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_1 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_5 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala 83:24]
  wire  _GEN_9 = out_f_wivalid_1 ? bundleIn_0_1_a_bits_data[0] : ctrl_cs_dflt_0; // @[RegField.scala 74:{88,92} TLSPI.scala 68:17]
  wire  out_rimask_2 = |out_frontMask[7:0]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_2 = &out_frontMask[7:0]; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_10 = _out_frontSel_T[10]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_2 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_10 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_3 = &out_frontMask[23:16]; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_3 = out_wivalid_2 & out_wimask_3; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_prepend_T = {{8'd0}, ctrl_dla_cssck}; // @[RegisterRouter.scala 83:24]
  wire [23:0] out_prepend = {ctrl_dla_sckcs,_out_prepend_T}; // @[Cat.scala 31:58]
  wire  out_frontSel_24 = _out_frontSel_T[24]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_4 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_24 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_4 = out_wivalid_4 & out_wimask_1; // @[RegisterRouter.scala 83:24]
  wire  _GEN_12 = out_f_wivalid_4 ? bundleIn_0_1_a_bits_data[0] : flash_en; // @[RegField.scala 74:{88,92} TLSPIFlash.scala 83:21]
  wire  out_frontSel_25 = _out_frontSel_T[25]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_5 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_25 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_5 = out_wivalid_5 & out_wimask_1; // @[RegisterRouter.scala 83:24]
  wire  _GEN_13 = out_f_wivalid_5 ? bundleIn_0_1_a_bits_data[0] : insn_cmd_en; // @[RegField.scala 74:{88,92} TLSPIFlash.scala 82:17]
  wire  out_wimask_6 = &out_frontMask[3:1]; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_6 = out_wivalid_5 & out_wimask_6; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_7 = &out_frontMask[7:4]; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_7 = out_wivalid_5 & out_wimask_7; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_8 = &out_frontMask[9:8]; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_8 = out_wivalid_5 & out_wimask_8; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_9 = &out_frontMask[11:10]; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_9 = out_wivalid_5 & out_wimask_9; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_10 = &out_frontMask[13:12]; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_10 = out_wivalid_5 & out_wimask_10; // @[RegisterRouter.scala 83:24]
  wire [13:0] out_prepend_5 = {insn_data_proto,insn_addr_proto,insn_cmd_proto,insn_pad_cnt,insn_addr_len,insn_cmd_en}; // @[Cat.scala 31:58]
  wire  out_f_wivalid_11 = out_wivalid_5 & out_wimask_3; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_prepend_T_6 = {{2'd0}, out_prepend_5}; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_12 = &out_frontMask[31:24]; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_12 = out_wivalid_5 & out_wimask_12; // @[RegisterRouter.scala 83:24]
  wire [31:0] out_prepend_7 = {insn_pad_code,insn_cmd_code,_out_prepend_T_6}; // @[Cat.scala 31:58]
  wire  out_frontSel_14 = _out_frontSel_T[14]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_13 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_14 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_13 = out_wivalid_13 & out_wimask; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_14 = &out_frontMask[3:0]; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_20 = _out_frontSel_T[20]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_14 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_20 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_14 = out_wivalid_14 & out_wimask_14; // @[RegisterRouter.scala 83:24]
  wire  _out_T_208 = fifo_io_ip_txwm; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_16 = &out_frontMask[1]; // @[RegisterRouter.scala 83:24]
  wire [1:0] out_prepend_8 = {fifo_io_ip_rxwm,_out_T_208}; // @[Cat.scala 31:58]
  wire  out_frontSel_1 = _out_frontSel_T[1]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_17 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_1 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_17 = out_wivalid_17 & out_wimask_1; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_18 = out_wivalid_17 & out_wimask_16; // @[RegisterRouter.scala 83:24]
  wire [1:0] out_prepend_9 = {ctrl_sck_pol,ctrl_sck_pha}; // @[Cat.scala 31:58]
  wire  out_wimask_19 = &out_frontMask[1:0]; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_6 = _out_frontSel_T[6]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_19 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_6 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_19 = out_wivalid_19 & out_wimask_19; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_28 = _out_frontSel_T[28]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_20 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_28 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_20 = out_wivalid_20 & out_wimask_1; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_21 = out_wivalid_20 & out_wimask_16; // @[RegisterRouter.scala 83:24]
  wire [1:0] out_prepend_10 = {ie_rxwm,ie_txwm}; // @[Cat.scala 31:58]
  wire  out_frontSel_21 = _out_frontSel_T[21]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_22 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_21 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_22 = out_wivalid_22 & out_wimask_14; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_18 = _out_frontSel_T[18]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_23 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_18 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_23 = out_wivalid_23 & out_wimask_2; // @[RegisterRouter.scala 83:24]
  wire  out_womask_25 = &out_frontMask[31]; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_25 = out_wivalid_23 & out_womask_25; // @[RegisterRouter.scala 83:24]
  wire  quash = out_f_woready_25 & bundleIn_0_1_a_bits_data[31]; // @[RegMapFIFO.scala 27:26]
  wire [31:0] out_prepend_12 = {_T,31'h0}; // @[Cat.scala 31:58]
  wire  out_frontSel_16 = _out_frontSel_T[16]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_26 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_16 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_26 = out_wivalid_26 & out_wimask_19; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_27 = &out_frontMask[2]; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_27 = out_wivalid_26 & out_wimask_27; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_28 = &out_frontMask[3]; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_28 = out_wivalid_26 & out_wimask_28; // @[RegisterRouter.scala 83:24]
  wire [3:0] out_prepend_14 = {ctrl_fmt_iodir,ctrl_fmt_endian,ctrl_fmt_proto}; // @[Cat.scala 31:58]
  wire  out_wimask_29 = &out_frontMask[19:16]; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_29 = out_wivalid_26 & out_wimask_29; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_prepend_T_15 = {{12'd0}, out_prepend_14}; // @[RegisterRouter.scala 83:24]
  wire [19:0] out_prepend_15 = {ctrl_fmt_len,_out_prepend_T_15}; // @[Cat.scala 31:58]
  wire  out_frontSel_11 = _out_frontSel_T[11]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_30 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_11 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_30 = out_wivalid_30 & out_wimask_2; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_31 = out_wivalid_30 & out_wimask_3; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_prepend_T_16 = {{8'd0}, ctrl_dla_intercs}; // @[RegisterRouter.scala 83:24]
  wire [23:0] out_prepend_16 = {ctrl_dla_interxfr,_out_prepend_T_16}; // @[Cat.scala 31:58]
  wire  out_frontSel_19 = _out_frontSel_T[19]; // @[RegisterRouter.scala 83:24]
  wire  out_rivalid_32 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & in_bits_read & out_frontSel_19 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire [7:0] _out_T_385 = fifo_io_rx_bits; // @[RegisterRouter.scala 83:24]
  wire [8:0] out_prepend_17 = {1'h0,_out_T_385}; // @[Cat.scala 31:58]
  wire [30:0] _out_T_394 = {{22'd0}, out_prepend_17}; // @[RegisterRouter.scala 83:24]
  wire [31:0] out_prepend_18 = {_T_1,_out_T_394}; // @[Cat.scala 31:58]
  wire  out_frontSel_4 = _out_frontSel_T[4]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_35 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_4 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_35 = out_wivalid_35 & out_wimask_1; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_36 = &out_frontMask[4:0]; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_15 = _out_frontSel_T[15]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_36 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_15 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_36 = out_wivalid_36 & out_wimask_36; // @[RegisterRouter.scala 83:24]
  wire  _GEN_166 = 5'h1 == out_oindex ? _out_T : _out_T; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_169 = 5'h4 == out_oindex ? _out_T : 5'h3 == out_oindex | (5'h2 == out_oindex | _GEN_166); // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_170 = 5'h5 == out_oindex ? _out_T : _GEN_169; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_171 = 5'h6 == out_oindex ? _out_T : _GEN_170; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_175 = 5'ha == out_oindex ? _out_T : 5'h9 == out_oindex | (5'h8 == out_oindex | (5'h7 == out_oindex |
    _GEN_171)); // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_176 = 5'hb == out_oindex ? _out_T : _GEN_175; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_179 = 5'he == out_oindex ? _out_T : 5'hd == out_oindex | (5'hc == out_oindex | _GEN_176); // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_180 = 5'hf == out_oindex ? _out_T : _GEN_179; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_181 = 5'h10 == out_oindex ? _out_T : _GEN_180; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_183 = 5'h12 == out_oindex ? _out_T : 5'h11 == out_oindex | _GEN_181; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_184 = 5'h13 == out_oindex ? _out_T : _GEN_183; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_185 = 5'h14 == out_oindex ? _out_T : _GEN_184; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_186 = 5'h15 == out_oindex ? _out_T : _GEN_185; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_189 = 5'h18 == out_oindex ? _out_T : 5'h17 == out_oindex | (5'h16 == out_oindex | _GEN_186); // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_190 = 5'h19 == out_oindex ? _out_T : _GEN_189; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_193 = 5'h1c == out_oindex ? _out_T : 5'h1b == out_oindex | (5'h1a == out_oindex | _GEN_190); // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_194 = 5'h1d == out_oindex ? _out_T : _GEN_193; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_196 = 5'h1f == out_oindex | (5'h1e == out_oindex | _GEN_194); // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_0 = {{20'd0}, ctrl_sck_div}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _out_out_bits_data_WIRE_1_1 = {{30'd0}, out_prepend_9}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_198 = 5'h1 == out_oindex ? _out_out_bits_data_WIRE_1_1 : _out_out_bits_data_WIRE_1_0; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_199 = 5'h2 == out_oindex ? 32'h0 : _GEN_198; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_200 = 5'h3 == out_oindex ? 32'h0 : _GEN_199; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_4 = {{31'd0}, ctrl_cs_id}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_201 = 5'h4 == out_oindex ? _out_out_bits_data_WIRE_1_4 : _GEN_200; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_5 = {{31'd0}, ctrl_cs_dflt_0}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_202 = 5'h5 == out_oindex ? _out_out_bits_data_WIRE_1_5 : _GEN_201; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_6 = {{30'd0}, ctrl_cs_mode}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_203 = 5'h6 == out_oindex ? _out_out_bits_data_WIRE_1_6 : _GEN_202; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_204 = 5'h7 == out_oindex ? 32'h0 : _GEN_203; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_205 = 5'h8 == out_oindex ? 32'h0 : _GEN_204; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_206 = 5'h9 == out_oindex ? 32'h0 : _GEN_205; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_10 = {{8'd0}, out_prepend}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_207 = 5'ha == out_oindex ? _out_out_bits_data_WIRE_1_10 : _GEN_206; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_11 = {{8'd0}, out_prepend_16}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_208 = 5'hb == out_oindex ? _out_out_bits_data_WIRE_1_11 : _GEN_207; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_209 = 5'hc == out_oindex ? 32'h0 : _GEN_208; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_210 = 5'hd == out_oindex ? 32'h0 : _GEN_209; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_14 = {{20'd0}, ctrl_extradel_coarse}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_211 = 5'he == out_oindex ? _out_out_bits_data_WIRE_1_14 : _GEN_210; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_15 = {{27'd0}, ctrl_sampledel_sd}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_212 = 5'hf == out_oindex ? _out_out_bits_data_WIRE_1_15 : _GEN_211; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_16 = {{12'd0}, out_prepend_15}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_213 = 5'h10 == out_oindex ? _out_out_bits_data_WIRE_1_16 : _GEN_212; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_214 = 5'h11 == out_oindex ? 32'h0 : _GEN_213; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_215 = 5'h12 == out_oindex ? out_prepend_12 : _GEN_214; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_216 = 5'h13 == out_oindex ? out_prepend_18 : _GEN_215; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_20 = {{28'd0}, ctrl_wm_tx}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_217 = 5'h14 == out_oindex ? _out_out_bits_data_WIRE_1_20 : _GEN_216; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_21 = {{28'd0}, ctrl_wm_rx}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_218 = 5'h15 == out_oindex ? _out_out_bits_data_WIRE_1_21 : _GEN_217; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_219 = 5'h16 == out_oindex ? 32'h0 : _GEN_218; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_220 = 5'h17 == out_oindex ? 32'h0 : _GEN_219; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_24 = {{31'd0}, flash_en}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_221 = 5'h18 == out_oindex ? _out_out_bits_data_WIRE_1_24 : _GEN_220; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_222 = 5'h19 == out_oindex ? out_prepend_7 : _GEN_221; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_223 = 5'h1a == out_oindex ? 32'h0 : _GEN_222; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_224 = 5'h1b == out_oindex ? 32'h0 : _GEN_223; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_28 = {{30'd0}, out_prepend_10}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_225 = 5'h1c == out_oindex ? _out_out_bits_data_WIRE_1_28 : _GEN_224; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_29 = {{30'd0}, out_prepend_8}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_226 = 5'h1d == out_oindex ? _out_out_bits_data_WIRE_1_29 : _GEN_225; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_227 = 5'h1e == out_oindex ? 32'h0 : _GEN_226; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_228 = 5'h1f == out_oindex ? 32'h0 : _GEN_227; // @[MuxLiteral.scala 48:{10,10}]
  TLBuffer_13 buffer ( // @[Buffer.scala 68:28]
    .auto_in_a_ready(buffer_auto_in_a_ready),
    .auto_in_a_valid(buffer_auto_in_a_valid),
    .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
    .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
    .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
    .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
    .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
    .auto_in_a_bits_data(buffer_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
    .auto_in_d_ready(buffer_auto_in_d_ready),
    .auto_in_d_valid(buffer_auto_in_d_valid),
    .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
    .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
    .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
    .auto_out_a_ready(buffer_auto_out_a_ready),
    .auto_out_a_valid(buffer_auto_out_a_valid),
    .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
    .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
    .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
    .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
    .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
    .auto_out_a_bits_data(buffer_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
    .auto_out_d_ready(buffer_auto_out_d_ready),
    .auto_out_d_valid(buffer_auto_out_d_valid),
    .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
    .auto_out_d_bits_source(buffer_auto_out_d_bits_source),
    .auto_out_d_bits_data(buffer_auto_out_d_bits_data)
  );
  TLBuffer_19 buffer_1 ( // @[Buffer.scala 68:28]
    .auto_in_a_ready(buffer_1_auto_in_a_ready),
    .auto_in_a_valid(buffer_1_auto_in_a_valid),
    .auto_in_a_bits_opcode(buffer_1_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(buffer_1_auto_in_a_bits_param),
    .auto_in_a_bits_size(buffer_1_auto_in_a_bits_size),
    .auto_in_a_bits_source(buffer_1_auto_in_a_bits_source),
    .auto_in_a_bits_address(buffer_1_auto_in_a_bits_address),
    .auto_in_a_bits_mask(buffer_1_auto_in_a_bits_mask),
    .auto_in_a_bits_corrupt(buffer_1_auto_in_a_bits_corrupt),
    .auto_in_d_ready(buffer_1_auto_in_d_ready),
    .auto_in_d_valid(buffer_1_auto_in_d_valid),
    .auto_in_d_bits_size(buffer_1_auto_in_d_bits_size),
    .auto_in_d_bits_source(buffer_1_auto_in_d_bits_source),
    .auto_in_d_bits_data(buffer_1_auto_in_d_bits_data),
    .auto_out_a_ready(buffer_1_auto_out_a_ready),
    .auto_out_a_valid(buffer_1_auto_out_a_valid),
    .auto_out_a_bits_opcode(buffer_1_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(buffer_1_auto_out_a_bits_param),
    .auto_out_a_bits_size(buffer_1_auto_out_a_bits_size),
    .auto_out_a_bits_source(buffer_1_auto_out_a_bits_source),
    .auto_out_a_bits_address(buffer_1_auto_out_a_bits_address),
    .auto_out_a_bits_mask(buffer_1_auto_out_a_bits_mask),
    .auto_out_a_bits_corrupt(buffer_1_auto_out_a_bits_corrupt),
    .auto_out_d_ready(buffer_1_auto_out_d_ready),
    .auto_out_d_valid(buffer_1_auto_out_d_valid),
    .auto_out_d_bits_size(buffer_1_auto_out_d_bits_size),
    .auto_out_d_bits_source(buffer_1_auto_out_d_bits_source),
    .auto_out_d_bits_data(buffer_1_auto_out_d_bits_data)
  );
  IntSyncCrossingSource_1 intsource ( // @[Crossing.scala 26:31]
    .clock(intsource_clock),
    .reset(intsource_reset),
    .auto_in_0(intsource_auto_in_0),
    .auto_out_sync_0(intsource_auto_out_sync_0)
  );
  TLMonitor_61 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  TLMonitor_62 monitor_1 ( // @[Nodes.scala 24:25]
    .clock(monitor_1_clock),
    .reset(monitor_1_reset),
    .io_in_a_ready(monitor_1_io_in_a_ready),
    .io_in_a_valid(monitor_1_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_1_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_1_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_1_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_1_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_1_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_1_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_1_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_1_io_in_d_ready),
    .io_in_d_valid(monitor_1_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_1_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_1_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_1_io_in_d_bits_source)
  );
  SPIFIFO fifo ( // @[TLSPI.scala 69:20]
    .clock(fifo_clock),
    .reset(fifo_reset),
    .io_ctrl_fmt_proto(fifo_io_ctrl_fmt_proto),
    .io_ctrl_fmt_endian(fifo_io_ctrl_fmt_endian),
    .io_ctrl_fmt_iodir(fifo_io_ctrl_fmt_iodir),
    .io_ctrl_fmt_len(fifo_io_ctrl_fmt_len),
    .io_ctrl_cs_mode(fifo_io_ctrl_cs_mode),
    .io_ctrl_wm_tx(fifo_io_ctrl_wm_tx),
    .io_ctrl_wm_rx(fifo_io_ctrl_wm_rx),
    .io_link_tx_ready(fifo_io_link_tx_ready),
    .io_link_tx_valid(fifo_io_link_tx_valid),
    .io_link_tx_bits(fifo_io_link_tx_bits),
    .io_link_rx_valid(fifo_io_link_rx_valid),
    .io_link_rx_bits(fifo_io_link_rx_bits),
    .io_link_cnt(fifo_io_link_cnt),
    .io_link_fmt_proto(fifo_io_link_fmt_proto),
    .io_link_fmt_endian(fifo_io_link_fmt_endian),
    .io_link_fmt_iodir(fifo_io_link_fmt_iodir),
    .io_link_cs_set(fifo_io_link_cs_set),
    .io_link_cs_clear(fifo_io_link_cs_clear),
    .io_link_lock(fifo_io_link_lock),
    .io_tx_ready(fifo_io_tx_ready),
    .io_tx_valid(fifo_io_tx_valid),
    .io_tx_bits(fifo_io_tx_bits),
    .io_rx_ready(fifo_io_rx_ready),
    .io_rx_valid(fifo_io_rx_valid),
    .io_rx_bits(fifo_io_rx_bits),
    .io_ip_txwm(fifo_io_ip_txwm),
    .io_ip_rxwm(fifo_io_ip_rxwm)
  );
  SPIMedia mac ( // @[TLSPI.scala 70:19]
    .clock(mac_clock),
    .reset(mac_reset),
    .io_port_sck(mac_io_port_sck),
    .io_port_dq_0_i(mac_io_port_dq_0_i),
    .io_port_dq_0_o(mac_io_port_dq_0_o),
    .io_port_dq_0_oe(mac_io_port_dq_0_oe),
    .io_port_dq_1_i(mac_io_port_dq_1_i),
    .io_port_dq_1_o(mac_io_port_dq_1_o),
    .io_port_dq_1_oe(mac_io_port_dq_1_oe),
    .io_port_dq_2_i(mac_io_port_dq_2_i),
    .io_port_dq_2_o(mac_io_port_dq_2_o),
    .io_port_dq_2_oe(mac_io_port_dq_2_oe),
    .io_port_dq_3_i(mac_io_port_dq_3_i),
    .io_port_dq_3_o(mac_io_port_dq_3_o),
    .io_port_dq_3_oe(mac_io_port_dq_3_oe),
    .io_port_cs_0(mac_io_port_cs_0),
    .io_ctrl_sck_div(mac_io_ctrl_sck_div),
    .io_ctrl_sck_pol(mac_io_ctrl_sck_pol),
    .io_ctrl_sck_pha(mac_io_ctrl_sck_pha),
    .io_ctrl_dla_cssck(mac_io_ctrl_dla_cssck),
    .io_ctrl_dla_sckcs(mac_io_ctrl_dla_sckcs),
    .io_ctrl_dla_intercs(mac_io_ctrl_dla_intercs),
    .io_ctrl_dla_interxfr(mac_io_ctrl_dla_interxfr),
    .io_ctrl_cs_id(mac_io_ctrl_cs_id),
    .io_ctrl_cs_dflt_0(mac_io_ctrl_cs_dflt_0),
    .io_ctrl_extradel_coarse(mac_io_ctrl_extradel_coarse),
    .io_ctrl_sampledel_sd(mac_io_ctrl_sampledel_sd),
    .io_link_tx_ready(mac_io_link_tx_ready),
    .io_link_tx_valid(mac_io_link_tx_valid),
    .io_link_tx_bits(mac_io_link_tx_bits),
    .io_link_rx_valid(mac_io_link_rx_valid),
    .io_link_rx_bits(mac_io_link_rx_bits),
    .io_link_cnt(mac_io_link_cnt),
    .io_link_fmt_proto(mac_io_link_fmt_proto),
    .io_link_fmt_endian(mac_io_link_fmt_endian),
    .io_link_fmt_iodir(mac_io_link_fmt_iodir),
    .io_link_cs_set(mac_io_link_cs_set),
    .io_link_cs_clear(mac_io_link_cs_clear),
    .io_link_cs_hold(mac_io_link_cs_hold),
    .io_link_active(mac_io_link_active)
  );
  SPIFlashMap flash ( // @[TLSPIFlash.scala 57:21]
    .clock(flash_clock),
    .reset(flash_reset),
    .io_en(flash_io_en),
    .io_ctrl_insn_cmd_proto(flash_io_ctrl_insn_cmd_proto),
    .io_ctrl_insn_cmd_code(flash_io_ctrl_insn_cmd_code),
    .io_ctrl_insn_cmd_en(flash_io_ctrl_insn_cmd_en),
    .io_ctrl_insn_addr_proto(flash_io_ctrl_insn_addr_proto),
    .io_ctrl_insn_addr_len(flash_io_ctrl_insn_addr_len),
    .io_ctrl_insn_pad_code(flash_io_ctrl_insn_pad_code),
    .io_ctrl_insn_pad_cnt(flash_io_ctrl_insn_pad_cnt),
    .io_ctrl_insn_data_proto(flash_io_ctrl_insn_data_proto),
    .io_ctrl_fmt_endian(flash_io_ctrl_fmt_endian),
    .io_addr_ready(flash_io_addr_ready),
    .io_addr_valid(flash_io_addr_valid),
    .io_addr_bits_next(flash_io_addr_bits_next),
    .io_addr_bits_hold(flash_io_addr_bits_hold),
    .io_data_ready(flash_io_data_ready),
    .io_data_valid(flash_io_data_valid),
    .io_data_bits(flash_io_data_bits),
    .io_link_tx_ready(flash_io_link_tx_ready),
    .io_link_tx_valid(flash_io_link_tx_valid),
    .io_link_tx_bits(flash_io_link_tx_bits),
    .io_link_rx_valid(flash_io_link_rx_valid),
    .io_link_rx_bits(flash_io_link_rx_bits),
    .io_link_cnt(flash_io_link_cnt),
    .io_link_fmt_proto(flash_io_link_fmt_proto),
    .io_link_fmt_endian(flash_io_link_fmt_endian),
    .io_link_fmt_iodir(flash_io_link_fmt_iodir),
    .io_link_cs_clear(flash_io_link_cs_clear),
    .io_link_active(flash_io_link_active),
    .io_link_lock(flash_io_link_lock)
  );
  SPIArbiter arb ( // @[TLSPIFlash.scala 58:19]
    .clock(arb_clock),
    .reset(arb_reset),
    .io_inner_0_tx_ready(arb_io_inner_0_tx_ready),
    .io_inner_0_tx_valid(arb_io_inner_0_tx_valid),
    .io_inner_0_tx_bits(arb_io_inner_0_tx_bits),
    .io_inner_0_rx_valid(arb_io_inner_0_rx_valid),
    .io_inner_0_rx_bits(arb_io_inner_0_rx_bits),
    .io_inner_0_cnt(arb_io_inner_0_cnt),
    .io_inner_0_fmt_proto(arb_io_inner_0_fmt_proto),
    .io_inner_0_fmt_endian(arb_io_inner_0_fmt_endian),
    .io_inner_0_fmt_iodir(arb_io_inner_0_fmt_iodir),
    .io_inner_0_cs_clear(arb_io_inner_0_cs_clear),
    .io_inner_0_active(arb_io_inner_0_active),
    .io_inner_0_lock(arb_io_inner_0_lock),
    .io_inner_1_tx_ready(arb_io_inner_1_tx_ready),
    .io_inner_1_tx_valid(arb_io_inner_1_tx_valid),
    .io_inner_1_tx_bits(arb_io_inner_1_tx_bits),
    .io_inner_1_rx_valid(arb_io_inner_1_rx_valid),
    .io_inner_1_rx_bits(arb_io_inner_1_rx_bits),
    .io_inner_1_cnt(arb_io_inner_1_cnt),
    .io_inner_1_fmt_proto(arb_io_inner_1_fmt_proto),
    .io_inner_1_fmt_endian(arb_io_inner_1_fmt_endian),
    .io_inner_1_fmt_iodir(arb_io_inner_1_fmt_iodir),
    .io_inner_1_cs_set(arb_io_inner_1_cs_set),
    .io_inner_1_cs_clear(arb_io_inner_1_cs_clear),
    .io_inner_1_lock(arb_io_inner_1_lock),
    .io_outer_tx_ready(arb_io_outer_tx_ready),
    .io_outer_tx_valid(arb_io_outer_tx_valid),
    .io_outer_tx_bits(arb_io_outer_tx_bits),
    .io_outer_rx_valid(arb_io_outer_rx_valid),
    .io_outer_rx_bits(arb_io_outer_rx_bits),
    .io_outer_cnt(arb_io_outer_cnt),
    .io_outer_fmt_proto(arb_io_outer_fmt_proto),
    .io_outer_fmt_endian(arb_io_outer_fmt_endian),
    .io_outer_fmt_iodir(arb_io_outer_fmt_iodir),
    .io_outer_cs_set(arb_io_outer_cs_set),
    .io_outer_cs_clear(arb_io_outer_cs_clear),
    .io_outer_cs_hold(arb_io_outer_cs_hold),
    .io_outer_active(arb_io_outer_active),
    .io_sel(arb_io_sel)
  );
  assign auto_int_xing_out_sync_0 = intsource_auto_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_mem_xing_in_a_ready = buffer_1_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_mem_xing_in_d_valid = buffer_1_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_mem_xing_in_d_bits_size = buffer_1_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_mem_xing_in_d_bits_source = buffer_1_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_mem_xing_in_d_bits_data = buffer_1_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_a_ready = buffer_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_valid = buffer_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_size = buffer_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_source = buffer_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_data = buffer_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_io_out_sck = mac_io_port_sck; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
  assign auto_io_out_dq_0_o = mac_io_port_dq_0_o; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
  assign auto_io_out_dq_0_oe = mac_io_port_dq_0_oe; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
  assign auto_io_out_dq_1_o = mac_io_port_dq_1_o; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
  assign auto_io_out_dq_1_oe = mac_io_port_dq_1_oe; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
  assign auto_io_out_dq_2_o = mac_io_port_dq_2_o; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
  assign auto_io_out_dq_2_oe = mac_io_port_dq_2_oe; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
  assign auto_io_out_dq_3_o = mac_io_port_dq_3_o; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
  assign auto_io_out_dq_3_oe = mac_io_port_dq_3_oe; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
  assign auto_io_out_cs_0 = mac_io_port_cs_0; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
  assign buffer_auto_in_a_valid = auto_control_xing_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_opcode = auto_control_xing_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_param = auto_control_xing_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_size = auto_control_xing_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_source = auto_control_xing_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_address = auto_control_xing_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_mask = auto_control_xing_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_data = auto_control_xing_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_corrupt = auto_control_xing_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_d_ready = auto_control_xing_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_out_a_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign buffer_auto_out_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_data = _GEN_196 ? _GEN_228 : 32'h0; // @[RegisterRouter.scala 83:24]
  assign buffer_1_auto_in_a_valid = auto_mem_xing_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_in_a_bits_opcode = auto_mem_xing_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_in_a_bits_param = auto_mem_xing_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_in_a_bits_size = auto_mem_xing_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_in_a_bits_source = auto_mem_xing_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_in_a_bits_address = auto_mem_xing_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_in_a_bits_mask = auto_mem_xing_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_in_a_bits_corrupt = auto_mem_xing_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_in_d_ready = auto_mem_xing_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_out_a_ready = flash_io_addr_ready; // @[Nodes.scala 1210:84 TLSPIFlash.scala 76:13]
  assign buffer_1_auto_out_d_valid = flash_io_data_valid; // @[Nodes.scala 1210:84 TLSPIFlash.scala 79:13]
  assign buffer_1_auto_out_d_bits_size = a_size; // @[Edges.scala 771:17 774:15]
  assign buffer_1_auto_out_d_bits_source = a_source; // @[Edges.scala 771:17 775:15]
  assign buffer_1_auto_out_d_bits_data = flash_io_data_bits; // @[Edges.scala 771:17 778:15]
  assign intsource_clock = clock;
  assign intsource_reset = reset;
  assign intsource_auto_in_0 = fifo_io_ip_txwm & ie_txwm | fifo_io_ip_rxwm & ie_rxwm; // @[TLSPI.scala 84:47]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = flash_io_addr_ready; // @[Nodes.scala 1210:84 TLSPIFlash.scala 76:13]
  assign monitor_io_in_a_valid = buffer_1_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_opcode = buffer_1_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_param = buffer_1_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_size = buffer_1_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_source = buffer_1_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_address = buffer_1_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_mask = buffer_1_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_corrupt = buffer_1_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_ready = buffer_1_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_valid = flash_io_data_valid; // @[Nodes.scala 1210:84 TLSPIFlash.scala 79:13]
  assign monitor_io_in_d_bits_size = a_size; // @[Edges.scala 771:17 774:15]
  assign monitor_io_in_d_bits_source = a_source; // @[Edges.scala 771:17 775:15]
  assign monitor_1_clock = clock;
  assign monitor_1_reset = reset;
  assign monitor_1_io_in_a_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_1_io_in_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_1_io_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_1_io_in_a_bits_param = buffer_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_1_io_in_a_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_1_io_in_a_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_1_io_in_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_1_io_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_1_io_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_1_io_in_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_1_io_in_d_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_1_io_in_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign monitor_1_io_in_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_1_io_in_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign fifo_clock = clock;
  assign fifo_reset = reset;
  assign fifo_io_ctrl_fmt_proto = ctrl_fmt_proto; // @[TLSPI.scala 73:20]
  assign fifo_io_ctrl_fmt_endian = ctrl_fmt_endian; // @[TLSPI.scala 73:20]
  assign fifo_io_ctrl_fmt_iodir = ctrl_fmt_iodir; // @[TLSPI.scala 73:20]
  assign fifo_io_ctrl_fmt_len = ctrl_fmt_len; // @[TLSPI.scala 73:20]
  assign fifo_io_ctrl_cs_mode = ctrl_cs_mode; // @[TLSPI.scala 74:19]
  assign fifo_io_ctrl_wm_tx = ctrl_wm_tx; // @[TLSPI.scala 75:19]
  assign fifo_io_ctrl_wm_rx = ctrl_wm_rx; // @[TLSPI.scala 75:19]
  assign fifo_io_link_tx_ready = arb_io_inner_1_tx_ready; // @[TLSPIFlash.scala 139:21]
  assign fifo_io_link_rx_valid = arb_io_inner_1_rx_valid; // @[TLSPIFlash.scala 139:21]
  assign fifo_io_link_rx_bits = arb_io_inner_1_rx_bits; // @[TLSPIFlash.scala 139:21]
  assign fifo_io_tx_valid = out_f_wivalid_23 & ~quash; // @[RegMapFIFO.scala 19:30]
  assign fifo_io_tx_bits = bundleIn_0_1_a_bits_data[7:0]; // @[RegisterRouter.scala 83:24]
  assign fifo_io_rx_ready = out_rivalid_32 & out_rimask_2; // @[RegisterRouter.scala 83:24]
  assign mac_clock = clock;
  assign mac_reset = reset;
  assign mac_io_port_dq_0_i = auto_io_out_dq_0_i; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign mac_io_port_dq_1_i = auto_io_out_dq_1_i; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign mac_io_port_dq_2_i = auto_io_out_dq_2_i; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign mac_io_port_dq_3_i = auto_io_out_dq_3_i; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign mac_io_ctrl_sck_div = ctrl_sck_div; // @[TLSPI.scala 76:19]
  assign mac_io_ctrl_sck_pol = ctrl_sck_pol; // @[TLSPI.scala 76:19]
  assign mac_io_ctrl_sck_pha = ctrl_sck_pha; // @[TLSPI.scala 76:19]
  assign mac_io_ctrl_dla_cssck = ctrl_dla_cssck; // @[TLSPI.scala 79:19]
  assign mac_io_ctrl_dla_sckcs = ctrl_dla_sckcs; // @[TLSPI.scala 79:19]
  assign mac_io_ctrl_dla_intercs = ctrl_dla_intercs; // @[TLSPI.scala 79:19]
  assign mac_io_ctrl_dla_interxfr = ctrl_dla_interxfr; // @[TLSPI.scala 79:19]
  assign mac_io_ctrl_cs_id = ctrl_cs_id; // @[TLSPI.scala 80:18]
  assign mac_io_ctrl_cs_dflt_0 = ctrl_cs_dflt_0; // @[TLSPI.scala 80:18]
  assign mac_io_ctrl_extradel_coarse = ctrl_extradel_coarse; // @[TLSPI.scala 77:24]
  assign mac_io_ctrl_sampledel_sd = ctrl_sampledel_sd; // @[TLSPI.scala 78:25]
  assign mac_io_link_tx_valid = arb_io_outer_tx_valid; // @[TLSPIFlash.scala 140:17]
  assign mac_io_link_tx_bits = arb_io_outer_tx_bits; // @[TLSPIFlash.scala 140:17]
  assign mac_io_link_cnt = arb_io_outer_cnt; // @[TLSPIFlash.scala 140:17]
  assign mac_io_link_fmt_proto = arb_io_outer_fmt_proto; // @[TLSPIFlash.scala 140:17]
  assign mac_io_link_fmt_endian = arb_io_outer_fmt_endian; // @[TLSPIFlash.scala 140:17]
  assign mac_io_link_fmt_iodir = arb_io_outer_fmt_iodir; // @[TLSPIFlash.scala 140:17]
  assign mac_io_link_cs_set = arb_io_outer_cs_set; // @[TLSPIFlash.scala 140:17]
  assign mac_io_link_cs_clear = arb_io_outer_cs_clear; // @[TLSPIFlash.scala 140:17]
  assign mac_io_link_cs_hold = arb_io_outer_cs_hold; // @[TLSPIFlash.scala 140:17]
  assign flash_clock = clock;
  assign flash_reset = reset;
  assign flash_io_en = flash_en; // @[TLSPIFlash.scala 87:15]
  assign flash_io_ctrl_insn_cmd_proto = insn_cmd_proto; // @[TLSPIFlash.scala 85:22]
  assign flash_io_ctrl_insn_cmd_code = insn_cmd_code; // @[TLSPIFlash.scala 85:22]
  assign flash_io_ctrl_insn_cmd_en = insn_cmd_en; // @[TLSPIFlash.scala 85:22]
  assign flash_io_ctrl_insn_addr_proto = insn_addr_proto; // @[TLSPIFlash.scala 85:22]
  assign flash_io_ctrl_insn_addr_len = insn_addr_len; // @[TLSPIFlash.scala 85:22]
  assign flash_io_ctrl_insn_pad_code = insn_pad_code; // @[TLSPIFlash.scala 85:22]
  assign flash_io_ctrl_insn_pad_cnt = insn_pad_cnt; // @[TLSPIFlash.scala 85:22]
  assign flash_io_ctrl_insn_data_proto = insn_data_proto; // @[TLSPIFlash.scala 85:22]
  assign flash_io_ctrl_fmt_endian = ctrl_fmt_endian; // @[TLSPIFlash.scala 86:21]
  assign flash_io_addr_valid = buffer_1_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign flash_io_addr_bits_next = {{3'd0}, bundleIn_0_a_bits_address[28:0]}; // @[TLSPIFlash.scala 73:27]
  assign flash_io_addr_bits_hold = {{3'd0}, a_address[28:0]}; // @[TLSPIFlash.scala 74:27]
  assign flash_io_data_ready = buffer_1_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign flash_io_link_tx_ready = arb_io_inner_0_tx_ready; // @[TLSPIFlash.scala 138:21]
  assign flash_io_link_rx_valid = arb_io_inner_0_rx_valid; // @[TLSPIFlash.scala 138:21]
  assign flash_io_link_rx_bits = arb_io_inner_0_rx_bits; // @[TLSPIFlash.scala 138:21]
  assign flash_io_link_active = arb_io_inner_0_active; // @[TLSPIFlash.scala 138:21]
  assign arb_clock = clock;
  assign arb_reset = reset;
  assign arb_io_inner_0_tx_valid = flash_io_link_tx_valid; // @[TLSPIFlash.scala 138:21]
  assign arb_io_inner_0_tx_bits = flash_io_link_tx_bits; // @[TLSPIFlash.scala 138:21]
  assign arb_io_inner_0_cnt = flash_io_link_cnt; // @[TLSPIFlash.scala 138:21]
  assign arb_io_inner_0_fmt_proto = flash_io_link_fmt_proto; // @[TLSPIFlash.scala 138:21]
  assign arb_io_inner_0_fmt_endian = flash_io_link_fmt_endian; // @[TLSPIFlash.scala 138:21]
  assign arb_io_inner_0_fmt_iodir = flash_io_link_fmt_iodir; // @[TLSPIFlash.scala 138:21]
  assign arb_io_inner_0_cs_clear = flash_io_link_cs_clear; // @[TLSPIFlash.scala 138:21]
  assign arb_io_inner_0_lock = flash_io_link_lock; // @[TLSPIFlash.scala 138:21]
  assign arb_io_inner_1_tx_valid = fifo_io_link_tx_valid; // @[TLSPIFlash.scala 139:21]
  assign arb_io_inner_1_tx_bits = fifo_io_link_tx_bits; // @[TLSPIFlash.scala 139:21]
  assign arb_io_inner_1_cnt = fifo_io_link_cnt; // @[TLSPIFlash.scala 139:21]
  assign arb_io_inner_1_fmt_proto = fifo_io_link_fmt_proto; // @[TLSPIFlash.scala 139:21]
  assign arb_io_inner_1_fmt_endian = fifo_io_link_fmt_endian; // @[TLSPIFlash.scala 139:21]
  assign arb_io_inner_1_fmt_iodir = fifo_io_link_fmt_iodir; // @[TLSPIFlash.scala 139:21]
  assign arb_io_inner_1_cs_set = fifo_io_link_cs_set; // @[TLSPIFlash.scala 139:21]
  assign arb_io_inner_1_cs_clear = fifo_io_link_cs_clear; // @[TLSPIFlash.scala 139:21]
  assign arb_io_inner_1_lock = fifo_io_link_lock; // @[TLSPIFlash.scala 139:21]
  assign arb_io_outer_tx_ready = mac_io_link_tx_ready; // @[TLSPIFlash.scala 140:17]
  assign arb_io_outer_rx_valid = mac_io_link_rx_valid; // @[TLSPIFlash.scala 140:17]
  assign arb_io_outer_rx_bits = mac_io_link_rx_bits; // @[TLSPIFlash.scala 140:17]
  assign arb_io_outer_active = mac_io_link_active; // @[TLSPIFlash.scala 140:17]
  assign arb_io_sel = ~flash_en; // @[TLSPIFlash.scala 88:17]
  always @(posedge clock) begin
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_fmt_proto <= 2'h0; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_26) begin // @[RegField.scala 74:88]
      ctrl_fmt_proto <= bundleIn_0_1_a_bits_data[1:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_fmt_endian <= 1'h0; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_27) begin // @[RegField.scala 74:88]
      ctrl_fmt_endian <= bundleIn_0_1_a_bits_data[2]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_fmt_iodir <= 1'h0; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_28) begin // @[RegField.scala 74:88]
      ctrl_fmt_iodir <= bundleIn_0_1_a_bits_data[3]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_fmt_len <= 4'h8; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_29) begin // @[RegField.scala 74:88]
      ctrl_fmt_len <= bundleIn_0_1_a_bits_data[19:16]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_sck_div <= 12'h3; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid) begin // @[RegField.scala 74:88]
      ctrl_sck_div <= bundleIn_0_1_a_bits_data[11:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_sck_pol <= 1'h0; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_18) begin // @[RegField.scala 74:88]
      ctrl_sck_pol <= bundleIn_0_1_a_bits_data[1]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_sck_pha <= 1'h0; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_17) begin // @[RegField.scala 74:88]
      ctrl_sck_pha <= bundleIn_0_1_a_bits_data[0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_cs_id <= 1'h0; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_35) begin // @[RegField.scala 74:88]
      ctrl_cs_id <= bundleIn_0_1_a_bits_data[0]; // @[RegField.scala 74:92]
    end
    ctrl_cs_dflt_0 <= reset | _GEN_9; // @[TLSPI.scala 68:{17,17}]
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_cs_mode <= 2'h0; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_19) begin // @[RegField.scala 74:88]
      ctrl_cs_mode <= bundleIn_0_1_a_bits_data[1:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_dla_cssck <= 8'h1; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_2) begin // @[RegField.scala 74:88]
      ctrl_dla_cssck <= bundleIn_0_1_a_bits_data[7:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_dla_sckcs <= 8'h1; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_3) begin // @[RegField.scala 74:88]
      ctrl_dla_sckcs <= bundleIn_0_1_a_bits_data[23:16]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_dla_intercs <= 8'h1; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_30) begin // @[RegField.scala 74:88]
      ctrl_dla_intercs <= bundleIn_0_1_a_bits_data[7:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_dla_interxfr <= 8'h0; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_31) begin // @[RegField.scala 74:88]
      ctrl_dla_interxfr <= bundleIn_0_1_a_bits_data[23:16]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_wm_tx <= 4'h0; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_14) begin // @[RegField.scala 74:88]
      ctrl_wm_tx <= bundleIn_0_1_a_bits_data[3:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_wm_rx <= 4'h0; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_22) begin // @[RegField.scala 74:88]
      ctrl_wm_rx <= bundleIn_0_1_a_bits_data[3:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_extradel_coarse <= 12'h0; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_13) begin // @[RegField.scala 74:88]
      ctrl_extradel_coarse <= bundleIn_0_1_a_bits_data[11:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_sampledel_sd <= 5'h3; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_36) begin // @[RegField.scala 74:88]
      ctrl_sampledel_sd <= bundleIn_0_1_a_bits_data[4:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 82:15]
      ie_txwm <= 1'h0; // @[TLSPI.scala 82:15]
    end else if (out_f_wivalid_20) begin // @[RegField.scala 74:88]
      ie_txwm <= bundleIn_0_1_a_bits_data[0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 82:15]
      ie_rxwm <= 1'h0; // @[TLSPI.scala 82:15]
    end else if (out_f_wivalid_21) begin // @[RegField.scala 74:88]
      ie_rxwm <= bundleIn_0_1_a_bits_data[1]; // @[RegField.scala 74:92]
    end
    if (_T_2) begin // @[TLSPIFlash.scala 69:21]
      a_size <= bundleIn_0_a_bits_size; // @[TLSPIFlash.scala 70:7]
    end
    if (_T_2) begin // @[TLSPIFlash.scala 69:21]
      a_source <= bundleIn_0_a_bits_source; // @[TLSPIFlash.scala 70:7]
    end
    if (_T_2) begin // @[TLSPIFlash.scala 69:21]
      a_address <= bundleIn_0_a_bits_address; // @[TLSPIFlash.scala 70:7]
    end
    if (reset) begin // @[TLSPIFlash.scala 82:17]
      insn_cmd_proto <= 2'h0; // @[TLSPIFlash.scala 82:17]
    end else if (out_f_wivalid_8) begin // @[RegField.scala 74:88]
      insn_cmd_proto <= bundleIn_0_1_a_bits_data[9:8]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPIFlash.scala 82:17]
      insn_cmd_code <= 8'h3; // @[TLSPIFlash.scala 82:17]
    end else if (out_f_wivalid_11) begin // @[RegField.scala 74:88]
      insn_cmd_code <= bundleIn_0_1_a_bits_data[23:16]; // @[RegField.scala 74:92]
    end
    insn_cmd_en <= reset | _GEN_13; // @[TLSPIFlash.scala 82:{17,17}]
    if (reset) begin // @[TLSPIFlash.scala 82:17]
      insn_addr_proto <= 2'h0; // @[TLSPIFlash.scala 82:17]
    end else if (out_f_wivalid_9) begin // @[RegField.scala 74:88]
      insn_addr_proto <= bundleIn_0_1_a_bits_data[11:10]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPIFlash.scala 82:17]
      insn_addr_len <= 3'h3; // @[TLSPIFlash.scala 82:17]
    end else if (out_f_wivalid_6) begin // @[RegField.scala 74:88]
      insn_addr_len <= bundleIn_0_1_a_bits_data[3:1]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPIFlash.scala 82:17]
      insn_pad_code <= 8'h0; // @[TLSPIFlash.scala 82:17]
    end else if (out_f_wivalid_12) begin // @[RegField.scala 74:88]
      insn_pad_code <= bundleIn_0_1_a_bits_data[31:24]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPIFlash.scala 82:17]
      insn_pad_cnt <= 4'h0; // @[TLSPIFlash.scala 82:17]
    end else if (out_f_wivalid_7) begin // @[RegField.scala 74:88]
      insn_pad_cnt <= bundleIn_0_1_a_bits_data[7:4]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPIFlash.scala 82:17]
      insn_data_proto <= 2'h0; // @[TLSPIFlash.scala 82:17]
    end else if (out_f_wivalid_10) begin // @[RegField.scala 74:88]
      insn_data_proto <= bundleIn_0_1_a_bits_data[13:12]; // @[RegField.scala 74:92]
    end
    flash_en <= reset | _GEN_12; // @[TLSPIFlash.scala 83:{21,21}]
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  ctrl_fmt_proto = _RAND_0[1:0];
  _RAND_1 = {1{`RANDOM}};
  ctrl_fmt_endian = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  ctrl_fmt_iodir = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  ctrl_fmt_len = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  ctrl_sck_div = _RAND_4[11:0];
  _RAND_5 = {1{`RANDOM}};
  ctrl_sck_pol = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  ctrl_sck_pha = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  ctrl_cs_id = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  ctrl_cs_dflt_0 = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  ctrl_cs_mode = _RAND_9[1:0];
  _RAND_10 = {1{`RANDOM}};
  ctrl_dla_cssck = _RAND_10[7:0];
  _RAND_11 = {1{`RANDOM}};
  ctrl_dla_sckcs = _RAND_11[7:0];
  _RAND_12 = {1{`RANDOM}};
  ctrl_dla_intercs = _RAND_12[7:0];
  _RAND_13 = {1{`RANDOM}};
  ctrl_dla_interxfr = _RAND_13[7:0];
  _RAND_14 = {1{`RANDOM}};
  ctrl_wm_tx = _RAND_14[3:0];
  _RAND_15 = {1{`RANDOM}};
  ctrl_wm_rx = _RAND_15[3:0];
  _RAND_16 = {1{`RANDOM}};
  ctrl_extradel_coarse = _RAND_16[11:0];
  _RAND_17 = {1{`RANDOM}};
  ctrl_sampledel_sd = _RAND_17[4:0];
  _RAND_18 = {1{`RANDOM}};
  ie_txwm = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  ie_rxwm = _RAND_19[0:0];
  _RAND_20 = {1{`RANDOM}};
  a_size = _RAND_20[0:0];
  _RAND_21 = {1{`RANDOM}};
  a_source = _RAND_21[8:0];
  _RAND_22 = {1{`RANDOM}};
  a_address = _RAND_22[29:0];
  _RAND_23 = {1{`RANDOM}};
  insn_cmd_proto = _RAND_23[1:0];
  _RAND_24 = {1{`RANDOM}};
  insn_cmd_code = _RAND_24[7:0];
  _RAND_25 = {1{`RANDOM}};
  insn_cmd_en = _RAND_25[0:0];
  _RAND_26 = {1{`RANDOM}};
  insn_addr_proto = _RAND_26[1:0];
  _RAND_27 = {1{`RANDOM}};
  insn_addr_len = _RAND_27[2:0];
  _RAND_28 = {1{`RANDOM}};
  insn_pad_code = _RAND_28[7:0];
  _RAND_29 = {1{`RANDOM}};
  insn_pad_cnt = _RAND_29[3:0];
  _RAND_30 = {1{`RANDOM}};
  insn_data_proto = _RAND_30[1:0];
  _RAND_31 = {1{`RANDOM}};
  flash_en = _RAND_31[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ClockSinkDomain_6(
  output        auto_qspi_0_int_xing_out_sync_0,
  output        auto_qspi_0_mem_xing_in_a_ready,
  input         auto_qspi_0_mem_xing_in_a_valid,
  input  [2:0]  auto_qspi_0_mem_xing_in_a_bits_opcode,
  input  [2:0]  auto_qspi_0_mem_xing_in_a_bits_param,
  input         auto_qspi_0_mem_xing_in_a_bits_size,
  input  [8:0]  auto_qspi_0_mem_xing_in_a_bits_source,
  input  [29:0] auto_qspi_0_mem_xing_in_a_bits_address,
  input         auto_qspi_0_mem_xing_in_a_bits_mask,
  input         auto_qspi_0_mem_xing_in_a_bits_corrupt,
  input         auto_qspi_0_mem_xing_in_d_ready,
  output        auto_qspi_0_mem_xing_in_d_valid,
  output        auto_qspi_0_mem_xing_in_d_bits_size,
  output [8:0]  auto_qspi_0_mem_xing_in_d_bits_source,
  output [7:0]  auto_qspi_0_mem_xing_in_d_bits_data,
  output        auto_qspi_0_control_xing_in_a_ready,
  input         auto_qspi_0_control_xing_in_a_valid,
  input  [2:0]  auto_qspi_0_control_xing_in_a_bits_opcode,
  input  [2:0]  auto_qspi_0_control_xing_in_a_bits_param,
  input  [1:0]  auto_qspi_0_control_xing_in_a_bits_size,
  input  [6:0]  auto_qspi_0_control_xing_in_a_bits_source,
  input  [28:0] auto_qspi_0_control_xing_in_a_bits_address,
  input  [3:0]  auto_qspi_0_control_xing_in_a_bits_mask,
  input  [31:0] auto_qspi_0_control_xing_in_a_bits_data,
  input         auto_qspi_0_control_xing_in_a_bits_corrupt,
  input         auto_qspi_0_control_xing_in_d_ready,
  output        auto_qspi_0_control_xing_in_d_valid,
  output [2:0]  auto_qspi_0_control_xing_in_d_bits_opcode,
  output [1:0]  auto_qspi_0_control_xing_in_d_bits_size,
  output [6:0]  auto_qspi_0_control_xing_in_d_bits_source,
  output [31:0] auto_qspi_0_control_xing_in_d_bits_data,
  output        auto_qspi_0_io_out_sck,
  input         auto_qspi_0_io_out_dq_0_i,
  output        auto_qspi_0_io_out_dq_0_o,
  output        auto_qspi_0_io_out_dq_0_oe,
  input         auto_qspi_0_io_out_dq_1_i,
  output        auto_qspi_0_io_out_dq_1_o,
  output        auto_qspi_0_io_out_dq_1_oe,
  input         auto_qspi_0_io_out_dq_2_i,
  output        auto_qspi_0_io_out_dq_2_o,
  output        auto_qspi_0_io_out_dq_2_oe,
  input         auto_qspi_0_io_out_dq_3_i,
  output        auto_qspi_0_io_out_dq_3_o,
  output        auto_qspi_0_io_out_dq_3_oe,
  output        auto_qspi_0_io_out_cs_0,
  input         auto_clock_in_clock,
  input         auto_clock_in_reset
);
  wire  qspi_0_clock; // @[SPI.scala 93:51]
  wire  qspi_0_reset; // @[SPI.scala 93:51]
  wire  qspi_0_auto_int_xing_out_sync_0; // @[SPI.scala 93:51]
  wire  qspi_0_auto_mem_xing_in_a_ready; // @[SPI.scala 93:51]
  wire  qspi_0_auto_mem_xing_in_a_valid; // @[SPI.scala 93:51]
  wire [2:0] qspi_0_auto_mem_xing_in_a_bits_opcode; // @[SPI.scala 93:51]
  wire [2:0] qspi_0_auto_mem_xing_in_a_bits_param; // @[SPI.scala 93:51]
  wire  qspi_0_auto_mem_xing_in_a_bits_size; // @[SPI.scala 93:51]
  wire [8:0] qspi_0_auto_mem_xing_in_a_bits_source; // @[SPI.scala 93:51]
  wire [29:0] qspi_0_auto_mem_xing_in_a_bits_address; // @[SPI.scala 93:51]
  wire  qspi_0_auto_mem_xing_in_a_bits_mask; // @[SPI.scala 93:51]
  wire  qspi_0_auto_mem_xing_in_a_bits_corrupt; // @[SPI.scala 93:51]
  wire  qspi_0_auto_mem_xing_in_d_ready; // @[SPI.scala 93:51]
  wire  qspi_0_auto_mem_xing_in_d_valid; // @[SPI.scala 93:51]
  wire  qspi_0_auto_mem_xing_in_d_bits_size; // @[SPI.scala 93:51]
  wire [8:0] qspi_0_auto_mem_xing_in_d_bits_source; // @[SPI.scala 93:51]
  wire [7:0] qspi_0_auto_mem_xing_in_d_bits_data; // @[SPI.scala 93:51]
  wire  qspi_0_auto_control_xing_in_a_ready; // @[SPI.scala 93:51]
  wire  qspi_0_auto_control_xing_in_a_valid; // @[SPI.scala 93:51]
  wire [2:0] qspi_0_auto_control_xing_in_a_bits_opcode; // @[SPI.scala 93:51]
  wire [2:0] qspi_0_auto_control_xing_in_a_bits_param; // @[SPI.scala 93:51]
  wire [1:0] qspi_0_auto_control_xing_in_a_bits_size; // @[SPI.scala 93:51]
  wire [6:0] qspi_0_auto_control_xing_in_a_bits_source; // @[SPI.scala 93:51]
  wire [28:0] qspi_0_auto_control_xing_in_a_bits_address; // @[SPI.scala 93:51]
  wire [3:0] qspi_0_auto_control_xing_in_a_bits_mask; // @[SPI.scala 93:51]
  wire [31:0] qspi_0_auto_control_xing_in_a_bits_data; // @[SPI.scala 93:51]
  wire  qspi_0_auto_control_xing_in_a_bits_corrupt; // @[SPI.scala 93:51]
  wire  qspi_0_auto_control_xing_in_d_ready; // @[SPI.scala 93:51]
  wire  qspi_0_auto_control_xing_in_d_valid; // @[SPI.scala 93:51]
  wire [2:0] qspi_0_auto_control_xing_in_d_bits_opcode; // @[SPI.scala 93:51]
  wire [1:0] qspi_0_auto_control_xing_in_d_bits_size; // @[SPI.scala 93:51]
  wire [6:0] qspi_0_auto_control_xing_in_d_bits_source; // @[SPI.scala 93:51]
  wire [31:0] qspi_0_auto_control_xing_in_d_bits_data; // @[SPI.scala 93:51]
  wire  qspi_0_auto_io_out_sck; // @[SPI.scala 93:51]
  wire  qspi_0_auto_io_out_dq_0_i; // @[SPI.scala 93:51]
  wire  qspi_0_auto_io_out_dq_0_o; // @[SPI.scala 93:51]
  wire  qspi_0_auto_io_out_dq_0_oe; // @[SPI.scala 93:51]
  wire  qspi_0_auto_io_out_dq_1_i; // @[SPI.scala 93:51]
  wire  qspi_0_auto_io_out_dq_1_o; // @[SPI.scala 93:51]
  wire  qspi_0_auto_io_out_dq_1_oe; // @[SPI.scala 93:51]
  wire  qspi_0_auto_io_out_dq_2_i; // @[SPI.scala 93:51]
  wire  qspi_0_auto_io_out_dq_2_o; // @[SPI.scala 93:51]
  wire  qspi_0_auto_io_out_dq_2_oe; // @[SPI.scala 93:51]
  wire  qspi_0_auto_io_out_dq_3_i; // @[SPI.scala 93:51]
  wire  qspi_0_auto_io_out_dq_3_o; // @[SPI.scala 93:51]
  wire  qspi_0_auto_io_out_dq_3_oe; // @[SPI.scala 93:51]
  wire  qspi_0_auto_io_out_cs_0; // @[SPI.scala 93:51]
  TLSPIFlash qspi_0 ( // @[SPI.scala 93:51]
    .clock(qspi_0_clock),
    .reset(qspi_0_reset),
    .auto_int_xing_out_sync_0(qspi_0_auto_int_xing_out_sync_0),
    .auto_mem_xing_in_a_ready(qspi_0_auto_mem_xing_in_a_ready),
    .auto_mem_xing_in_a_valid(qspi_0_auto_mem_xing_in_a_valid),
    .auto_mem_xing_in_a_bits_opcode(qspi_0_auto_mem_xing_in_a_bits_opcode),
    .auto_mem_xing_in_a_bits_param(qspi_0_auto_mem_xing_in_a_bits_param),
    .auto_mem_xing_in_a_bits_size(qspi_0_auto_mem_xing_in_a_bits_size),
    .auto_mem_xing_in_a_bits_source(qspi_0_auto_mem_xing_in_a_bits_source),
    .auto_mem_xing_in_a_bits_address(qspi_0_auto_mem_xing_in_a_bits_address),
    .auto_mem_xing_in_a_bits_mask(qspi_0_auto_mem_xing_in_a_bits_mask),
    .auto_mem_xing_in_a_bits_corrupt(qspi_0_auto_mem_xing_in_a_bits_corrupt),
    .auto_mem_xing_in_d_ready(qspi_0_auto_mem_xing_in_d_ready),
    .auto_mem_xing_in_d_valid(qspi_0_auto_mem_xing_in_d_valid),
    .auto_mem_xing_in_d_bits_size(qspi_0_auto_mem_xing_in_d_bits_size),
    .auto_mem_xing_in_d_bits_source(qspi_0_auto_mem_xing_in_d_bits_source),
    .auto_mem_xing_in_d_bits_data(qspi_0_auto_mem_xing_in_d_bits_data),
    .auto_control_xing_in_a_ready(qspi_0_auto_control_xing_in_a_ready),
    .auto_control_xing_in_a_valid(qspi_0_auto_control_xing_in_a_valid),
    .auto_control_xing_in_a_bits_opcode(qspi_0_auto_control_xing_in_a_bits_opcode),
    .auto_control_xing_in_a_bits_param(qspi_0_auto_control_xing_in_a_bits_param),
    .auto_control_xing_in_a_bits_size(qspi_0_auto_control_xing_in_a_bits_size),
    .auto_control_xing_in_a_bits_source(qspi_0_auto_control_xing_in_a_bits_source),
    .auto_control_xing_in_a_bits_address(qspi_0_auto_control_xing_in_a_bits_address),
    .auto_control_xing_in_a_bits_mask(qspi_0_auto_control_xing_in_a_bits_mask),
    .auto_control_xing_in_a_bits_data(qspi_0_auto_control_xing_in_a_bits_data),
    .auto_control_xing_in_a_bits_corrupt(qspi_0_auto_control_xing_in_a_bits_corrupt),
    .auto_control_xing_in_d_ready(qspi_0_auto_control_xing_in_d_ready),
    .auto_control_xing_in_d_valid(qspi_0_auto_control_xing_in_d_valid),
    .auto_control_xing_in_d_bits_opcode(qspi_0_auto_control_xing_in_d_bits_opcode),
    .auto_control_xing_in_d_bits_size(qspi_0_auto_control_xing_in_d_bits_size),
    .auto_control_xing_in_d_bits_source(qspi_0_auto_control_xing_in_d_bits_source),
    .auto_control_xing_in_d_bits_data(qspi_0_auto_control_xing_in_d_bits_data),
    .auto_io_out_sck(qspi_0_auto_io_out_sck),
    .auto_io_out_dq_0_i(qspi_0_auto_io_out_dq_0_i),
    .auto_io_out_dq_0_o(qspi_0_auto_io_out_dq_0_o),
    .auto_io_out_dq_0_oe(qspi_0_auto_io_out_dq_0_oe),
    .auto_io_out_dq_1_i(qspi_0_auto_io_out_dq_1_i),
    .auto_io_out_dq_1_o(qspi_0_auto_io_out_dq_1_o),
    .auto_io_out_dq_1_oe(qspi_0_auto_io_out_dq_1_oe),
    .auto_io_out_dq_2_i(qspi_0_auto_io_out_dq_2_i),
    .auto_io_out_dq_2_o(qspi_0_auto_io_out_dq_2_o),
    .auto_io_out_dq_2_oe(qspi_0_auto_io_out_dq_2_oe),
    .auto_io_out_dq_3_i(qspi_0_auto_io_out_dq_3_i),
    .auto_io_out_dq_3_o(qspi_0_auto_io_out_dq_3_o),
    .auto_io_out_dq_3_oe(qspi_0_auto_io_out_dq_3_oe),
    .auto_io_out_cs_0(qspi_0_auto_io_out_cs_0)
  );
  assign auto_qspi_0_int_xing_out_sync_0 = qspi_0_auto_int_xing_out_sync_0; // @[LazyModule.scala 311:12]
  assign auto_qspi_0_mem_xing_in_a_ready = qspi_0_auto_mem_xing_in_a_ready; // @[LazyModule.scala 309:16]
  assign auto_qspi_0_mem_xing_in_d_valid = qspi_0_auto_mem_xing_in_d_valid; // @[LazyModule.scala 309:16]
  assign auto_qspi_0_mem_xing_in_d_bits_size = qspi_0_auto_mem_xing_in_d_bits_size; // @[LazyModule.scala 309:16]
  assign auto_qspi_0_mem_xing_in_d_bits_source = qspi_0_auto_mem_xing_in_d_bits_source; // @[LazyModule.scala 309:16]
  assign auto_qspi_0_mem_xing_in_d_bits_data = qspi_0_auto_mem_xing_in_d_bits_data; // @[LazyModule.scala 309:16]
  assign auto_qspi_0_control_xing_in_a_ready = qspi_0_auto_control_xing_in_a_ready; // @[LazyModule.scala 309:16]
  assign auto_qspi_0_control_xing_in_d_valid = qspi_0_auto_control_xing_in_d_valid; // @[LazyModule.scala 309:16]
  assign auto_qspi_0_control_xing_in_d_bits_opcode = qspi_0_auto_control_xing_in_d_bits_opcode; // @[LazyModule.scala 309:16]
  assign auto_qspi_0_control_xing_in_d_bits_size = qspi_0_auto_control_xing_in_d_bits_size; // @[LazyModule.scala 309:16]
  assign auto_qspi_0_control_xing_in_d_bits_source = qspi_0_auto_control_xing_in_d_bits_source; // @[LazyModule.scala 309:16]
  assign auto_qspi_0_control_xing_in_d_bits_data = qspi_0_auto_control_xing_in_d_bits_data; // @[LazyModule.scala 309:16]
  assign auto_qspi_0_io_out_sck = qspi_0_auto_io_out_sck; // @[LazyModule.scala 311:12]
  assign auto_qspi_0_io_out_dq_0_o = qspi_0_auto_io_out_dq_0_o; // @[LazyModule.scala 311:12]
  assign auto_qspi_0_io_out_dq_0_oe = qspi_0_auto_io_out_dq_0_oe; // @[LazyModule.scala 311:12]
  assign auto_qspi_0_io_out_dq_1_o = qspi_0_auto_io_out_dq_1_o; // @[LazyModule.scala 311:12]
  assign auto_qspi_0_io_out_dq_1_oe = qspi_0_auto_io_out_dq_1_oe; // @[LazyModule.scala 311:12]
  assign auto_qspi_0_io_out_dq_2_o = qspi_0_auto_io_out_dq_2_o; // @[LazyModule.scala 311:12]
  assign auto_qspi_0_io_out_dq_2_oe = qspi_0_auto_io_out_dq_2_oe; // @[LazyModule.scala 311:12]
  assign auto_qspi_0_io_out_dq_3_o = qspi_0_auto_io_out_dq_3_o; // @[LazyModule.scala 311:12]
  assign auto_qspi_0_io_out_dq_3_oe = qspi_0_auto_io_out_dq_3_oe; // @[LazyModule.scala 311:12]
  assign auto_qspi_0_io_out_cs_0 = qspi_0_auto_io_out_cs_0; // @[LazyModule.scala 311:12]
  assign qspi_0_clock = auto_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign qspi_0_reset = auto_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign qspi_0_auto_mem_xing_in_a_valid = auto_qspi_0_mem_xing_in_a_valid; // @[LazyModule.scala 309:16]
  assign qspi_0_auto_mem_xing_in_a_bits_opcode = auto_qspi_0_mem_xing_in_a_bits_opcode; // @[LazyModule.scala 309:16]
  assign qspi_0_auto_mem_xing_in_a_bits_param = auto_qspi_0_mem_xing_in_a_bits_param; // @[LazyModule.scala 309:16]
  assign qspi_0_auto_mem_xing_in_a_bits_size = auto_qspi_0_mem_xing_in_a_bits_size; // @[LazyModule.scala 309:16]
  assign qspi_0_auto_mem_xing_in_a_bits_source = auto_qspi_0_mem_xing_in_a_bits_source; // @[LazyModule.scala 309:16]
  assign qspi_0_auto_mem_xing_in_a_bits_address = auto_qspi_0_mem_xing_in_a_bits_address; // @[LazyModule.scala 309:16]
  assign qspi_0_auto_mem_xing_in_a_bits_mask = auto_qspi_0_mem_xing_in_a_bits_mask; // @[LazyModule.scala 309:16]
  assign qspi_0_auto_mem_xing_in_a_bits_corrupt = auto_qspi_0_mem_xing_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
  assign qspi_0_auto_mem_xing_in_d_ready = auto_qspi_0_mem_xing_in_d_ready; // @[LazyModule.scala 309:16]
  assign qspi_0_auto_control_xing_in_a_valid = auto_qspi_0_control_xing_in_a_valid; // @[LazyModule.scala 309:16]
  assign qspi_0_auto_control_xing_in_a_bits_opcode = auto_qspi_0_control_xing_in_a_bits_opcode; // @[LazyModule.scala 309:16]
  assign qspi_0_auto_control_xing_in_a_bits_param = auto_qspi_0_control_xing_in_a_bits_param; // @[LazyModule.scala 309:16]
  assign qspi_0_auto_control_xing_in_a_bits_size = auto_qspi_0_control_xing_in_a_bits_size; // @[LazyModule.scala 309:16]
  assign qspi_0_auto_control_xing_in_a_bits_source = auto_qspi_0_control_xing_in_a_bits_source; // @[LazyModule.scala 309:16]
  assign qspi_0_auto_control_xing_in_a_bits_address = auto_qspi_0_control_xing_in_a_bits_address; // @[LazyModule.scala 309:16]
  assign qspi_0_auto_control_xing_in_a_bits_mask = auto_qspi_0_control_xing_in_a_bits_mask; // @[LazyModule.scala 309:16]
  assign qspi_0_auto_control_xing_in_a_bits_data = auto_qspi_0_control_xing_in_a_bits_data; // @[LazyModule.scala 309:16]
  assign qspi_0_auto_control_xing_in_a_bits_corrupt = auto_qspi_0_control_xing_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
  assign qspi_0_auto_control_xing_in_d_ready = auto_qspi_0_control_xing_in_d_ready; // @[LazyModule.scala 309:16]
  assign qspi_0_auto_io_out_dq_0_i = auto_qspi_0_io_out_dq_0_i; // @[LazyModule.scala 311:12]
  assign qspi_0_auto_io_out_dq_1_i = auto_qspi_0_io_out_dq_1_i; // @[LazyModule.scala 311:12]
  assign qspi_0_auto_io_out_dq_2_i = auto_qspi_0_io_out_dq_2_i; // @[LazyModule.scala 311:12]
  assign qspi_0_auto_io_out_dq_3_i = auto_qspi_0_io_out_dq_3_i; // @[LazyModule.scala 311:12]
endmodule
module TLBuffer_21(
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input         auto_in_a_bits_size,
  input  [10:0] auto_in_a_bits_source,
  input  [30:0] auto_in_a_bits_address,
  input         auto_in_a_bits_mask,
  input  [7:0]  auto_in_a_bits_data,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [2:0]  auto_in_d_bits_opcode,
  output        auto_in_d_bits_size,
  output [10:0] auto_in_d_bits_source,
  output [7:0]  auto_in_d_bits_data,
  input         auto_out_a_ready,
  output        auto_out_a_valid,
  output [2:0]  auto_out_a_bits_opcode,
  output [2:0]  auto_out_a_bits_param,
  output        auto_out_a_bits_size,
  output [10:0] auto_out_a_bits_source,
  output [30:0] auto_out_a_bits_address,
  output        auto_out_a_bits_mask,
  output [7:0]  auto_out_a_bits_data,
  output        auto_out_a_bits_corrupt,
  output        auto_out_d_ready,
  input         auto_out_d_valid,
  input  [2:0]  auto_out_d_bits_opcode,
  input         auto_out_d_bits_size,
  input  [10:0] auto_out_d_bits_source,
  input  [7:0]  auto_out_d_bits_data
);
  assign auto_in_a_ready = auto_out_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_valid = auto_out_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_in_d_bits_data = auto_out_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign auto_out_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_data = auto_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module TLMonitor_63(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input         io_in_a_bits_size,
  input  [10:0] io_in_a_bits_source,
  input  [30:0] io_in_a_bits_address,
  input         io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input         io_in_d_bits_size,
  input  [10:0] io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [2047:0] _RAND_10;
  reg [8191:0] _RAND_11;
  reg [4095:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [2047:0] _RAND_16;
  reg [4095:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [30:0] _T_33 = io_in_a_bits_address ^ 31'h40000000; // @[Parameters.scala 137:31]
  wire [31:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
  wire [31:0] _T_36 = $signed(_T_34) & -32'sh20000000; // @[Parameters.scala 137:52]
  wire  _T_37 = $signed(_T_36) == 32'sh0; // @[Parameters.scala 137:67]
  wire  _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire  _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_74 = ~(~io_in_a_bits_mask); // @[Monitor.scala 88:31]
  wire  _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_163 = ~io_in_a_bits_size; // @[Parameters.scala 91:48]
  wire  _T_170 = _T_163 & _T_37; // @[Parameters.scala 670:56]
  wire  _T_181 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_193 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_232 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire  _T_272 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_302 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_310 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_340 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_348 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_378 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_390 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _T_394 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_414 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_442 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg  size; // @[Monitor.scala 386:22]
  reg [10:0] source; // @[Monitor.scala 387:22]
  reg [30:0] address; // @[Monitor.scala 388:22]
  wire  _T_536 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_537 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_541 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_545 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_549 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_553 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg  size_1; // @[Monitor.scala 537:22]
  reg [10:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_560 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_561 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_569 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_573 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [2047:0] inflight; // @[Monitor.scala 611:27]
  reg [8191:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [4095:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [12:0] _GEN_71 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [13:0] _a_opcode_lookup_T = {{1'd0}, _GEN_71}; // @[Monitor.scala 634:69]
  wire [8191:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [8191:0] _GEN_72 = {{8176'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
  wire [8191:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_72; // @[Monitor.scala 634:97]
  wire [8191:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[8191:1]}; // @[Monitor.scala 634:152]
  wire [11:0] _a_size_lookup_T = {io_in_d_bits_source, 1'h0}; // @[Monitor.scala 638:65]
  wire [4095:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala 638:40]
  wire [3:0] _a_size_lookup_T_5 = 4'h4 - 4'h1; // @[Monitor.scala 609:57]
  wire [4095:0] _GEN_74 = {{4092'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 638:91]
  wire [4095:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_74; // @[Monitor.scala 638:91]
  wire [4095:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[4095:1]}; // @[Monitor.scala 638:144]
  wire  _T_587 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [2047:0] _a_set_wo_ready_T = 2048'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_590 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [1:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [1:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 2'h1; // @[Monitor.scala 655:59]
  wire [12:0] _GEN_76 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [13:0] _a_opcodes_set_T = {{1'd0}, _GEN_76}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [16386:0] _GEN_1 = {{16383'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [16386:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [11:0] _a_sizes_set_T = {io_in_a_bits_source, 1'h0}; // @[Monitor.scala 657:77]
  wire [1:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 2'h0; // @[Monitor.scala 652:72 655:28]
  wire [4096:0] _GEN_2 = {{4095'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [4096:0] _a_sizes_set_T_1 = _GEN_2 << _a_sizes_set_T; // @[Monitor.scala 657:52]
  wire [2047:0] _T_592 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_594 = ~_T_592[0]; // @[Monitor.scala 658:17]
  wire [2047:0] a_set = a_first_done & a_first_1 ? _a_set_wo_ready_T : 2048'h0; // @[Monitor.scala 652:72 653:28]
  wire [16386:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 16387'h0; // @[Monitor.scala 652:72 656:28]
  wire [4096:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 4097'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_598 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_600 = ~_T_394; // @[Monitor.scala 671:74]
  wire  _T_601 = io_in_d_valid & d_first_1 & ~_T_394; // @[Monitor.scala 671:71]
  wire [2047:0] _d_clr_wo_ready_T = 2048'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [16398:0] _GEN_3 = {{16383'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [16398:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [4098:0] _GEN_4 = {{4095'd0}, _a_size_lookup_T_5}; // @[Monitor.scala 678:74]
  wire [4098:0] _d_sizes_clr_T_5 = _GEN_4 << _a_size_lookup_T; // @[Monitor.scala 678:74]
  wire [2047:0] d_clr = d_first_done & d_first_1 & _T_600 ? _d_clr_wo_ready_T : 2048'h0; // @[Monitor.scala 675:91 676:21]
  wire [16398:0] _GEN_23 = d_first_done & d_first_1 & _T_600 ? _d_opcodes_clr_T_5 : 16399'h0; // @[Monitor.scala 675:91 677:21]
  wire [4098:0] _GEN_24 = d_first_done & d_first_1 & _T_600 ? _d_sizes_clr_T_5 : 4099'h0; // @[Monitor.scala 675:91 678:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_587 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [2047:0] _T_611 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_613 = _T_611[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_618 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_619 = io_in_d_bits_opcode == _GEN_32 | _T_618; // @[Monitor.scala 685:77]
  wire  _T_623 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_630 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_631 = io_in_d_bits_opcode == _GEN_48 | _T_630; // @[Monitor.scala 689:72]
  wire [1:0] a_size_lookup = _a_size_lookup_T_7[1:0];
  wire [1:0] _GEN_78 = {{1'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_635 = _GEN_78 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_645 = _T_598 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_600; // @[Monitor.scala 694:116]
  wire  _T_647 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [2047:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [2047:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [2047:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [8191:0] a_opcodes_set = _GEN_19[8191:0];
  wire [8191:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [8191:0] d_opcodes_clr = _GEN_23[8191:0];
  wire [8191:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [8191:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [4095:0] a_sizes_set = _GEN_20[4095:0];
  wire [4095:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [4095:0] d_sizes_clr = _GEN_24[4095:0];
  wire [4095:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala 704:56]
  wire [4095:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_656 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [2047:0] inflight_1; // @[Monitor.scala 723:35]
  reg [4095:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [4095:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_size_lookup_T; // @[Monitor.scala 747:42]
  wire [4095:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_74; // @[Monitor.scala 747:93]
  wire [4095:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[4095:1]}; // @[Monitor.scala 747:146]
  wire  _T_682 = io_in_d_valid & d_first_2 & _T_394; // @[Monitor.scala 779:71]
  wire [2047:0] d_clr_1 = d_first_done & d_first_2 & _T_394 ? _d_clr_wo_ready_T : 2048'h0; // @[Monitor.scala 783:90 784:21]
  wire [4098:0] _GEN_69 = d_first_done & d_first_2 & _T_394 ? _d_sizes_clr_T_5 : 4099'h0; // @[Monitor.scala 783:90 786:21]
  wire [2047:0] _T_690 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [1:0] c_size_lookup = _c_size_lookup_T_7[1:0];
  wire  _T_700 = _GEN_78 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [2047:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [2047:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [4095:0] d_sizes_clr_1 = _GEN_69[4095:0];
  wire [4095:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala 811:58]
  wire [4095:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_sizes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_720 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 1'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= 1'h0;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 2048'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 8192'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 4096'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 1'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= 1'h0;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 2048'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 4096'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= 1'h0;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (d_first_done) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_170 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_170) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_181 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_181) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_73 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_73) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_170 & (io_in_a_valid & _T_193 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_193 & ~reset & ~_T_170) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_181 & (io_in_a_valid & _T_193 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_193 & ~reset & ~_T_181) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_73 & (io_in_a_valid & _T_193 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_193 & ~reset & _T_73) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_232 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_232 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_181 & (io_in_a_valid & _T_232 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_232 & ~reset & ~_T_181) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_272 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_272 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_302 & (io_in_a_valid & _T_272 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_272 & ~reset & ~_T_302) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_73 & (io_in_a_valid & _T_272 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_272 & ~reset & _T_73) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_310 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_310 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_340 & (io_in_a_valid & _T_310 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_310 & ~reset & ~_T_340) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_73 & (io_in_a_valid & _T_310 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_310 & ~reset & _T_73) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_348 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_348 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_378 & (io_in_a_valid & _T_348 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_348 & ~reset & ~_T_378) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_73 & (io_in_a_valid & _T_348 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_348 & ~reset & _T_73) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_348 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_348 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_390 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_390) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_414 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_414 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_442 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_442 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_537 & (_T_536 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_536 & ~reset & ~_T_537) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_541 & (_T_536 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_536 & ~reset & ~_T_541) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_545 & (_T_536 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_536 & ~reset & ~_T_545) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_549 & (_T_536 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_536 & ~reset & ~_T_549) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_553 & (_T_536 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_536 & ~reset & ~_T_553) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_561 & (_T_560 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_560 & _T_2 & ~_T_561) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_569 & (_T_560 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_560 & _T_2 & ~_T_569) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_573 & (_T_560 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_560 & _T_2 & ~_T_573) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_594 & (_T_590 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_590 & ~reset & ~_T_594) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_613 & (_T_601 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_601 & _T_2 & ~_T_613) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_619 & (_T_601 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_601 & same_cycle_resp & _T_2 & ~_T_619) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_623 & (_T_601 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_601 & same_cycle_resp & _T_2 & ~_T_623) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_631 & (_T_601 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_601 & ~same_cycle_resp & _T_2 & ~_T_631) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_635 & (_T_601 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_601 & ~same_cycle_resp & _T_2 & ~_T_635) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_647 & (_T_645 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_645 & _T_2 & ~_T_647) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_656 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_656) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_690[0] & (_T_682 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_682 & _T_2 & ~_T_690[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_700 & (_T_682 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_682 & _T_2 & ~_T_700) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_720 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_720) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[10:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[30:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[10:0];
  _RAND_10 = {64{`RANDOM}};
  inflight = _RAND_10[2047:0];
  _RAND_11 = {256{`RANDOM}};
  inflight_opcodes = _RAND_11[8191:0];
  _RAND_12 = {128{`RANDOM}};
  inflight_sizes = _RAND_12[4095:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {64{`RANDOM}};
  inflight_1 = _RAND_16[2047:0];
  _RAND_17 = {128{`RANDOM}};
  inflight_sizes_1 = _RAND_17[4095:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLMonitor_64(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [1:0]  io_in_a_bits_size,
  input  [6:0]  io_in_a_bits_source,
  input  [28:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_size,
  input  [6:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [95:0] _RAND_10;
  reg [383:0] _RAND_11;
  reg [383:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [95:0] _RAND_16;
  reg [383:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T_4 = io_in_a_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire [4:0] _is_aligned_mask_T_1 = 5'h3 << io_in_a_bits_size; // @[package.scala 234:77]
  wire [1:0] is_aligned_mask = ~_is_aligned_mask_T_1[1:0]; // @[package.scala 234:46]
  wire [28:0] _GEN_71 = {{27'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 2'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [28:0] _T_33 = io_in_a_bits_address ^ 29'h10034000; // @[Parameters.scala 137:31]
  wire [29:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
  wire [29:0] _T_36 = $signed(_T_34) & -30'sh1000; // @[Parameters.scala 137:52]
  wire  _T_37 = $signed(_T_36) == 30'sh0; // @[Parameters.scala 137:67]
  wire  _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_74 = _T_73 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_164 = io_in_a_bits_size <= 2'h2; // @[Parameters.scala 92:42]
  wire  _T_172 = _T_164 & _T_37; // @[Parameters.scala 670:56]
  wire  _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_218 = _source_ok_T_4 & _T_172; // @[Monitor.scala 115:71]
  wire  _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_273 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_274 = io_in_a_bits_mask & _T_273; // @[Monitor.scala 127:31]
  wire  _T_275 = _T_274 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_279 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_347 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_355 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_385 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_397 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_10 = io_in_d_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire  _T_401 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_405 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 312:27]
  wire  _T_421 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_449 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_478 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_495 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_513 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [1:0] size; // @[Monitor.scala 386:22]
  reg [6:0] source; // @[Monitor.scala 387:22]
  reg [28:0] address; // @[Monitor.scala 388:22]
  wire  _T_543 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_544 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_548 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_552 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_556 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_560 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] size_1; // @[Monitor.scala 537:22]
  reg [6:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_567 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_568 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_576 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_580 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [95:0] inflight; // @[Monitor.scala 611:27]
  reg [383:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [383:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [8:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [9:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [383:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [383:0] _GEN_73 = {{368'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[383:1]}; // @[Monitor.scala 634:152]
  wire [383:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [383:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
  wire [383:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[383:1]}; // @[Monitor.scala 638:144]
  wire  _T_594 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [127:0] _a_set_wo_ready_T = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_597 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
  wire [8:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [9:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [1026:0] _GEN_1 = {{1023'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [1026:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
  wire [1025:0] _GEN_2 = {{1023'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [1025:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [95:0] _T_599 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_601 = ~_T_599[0]; // @[Monitor.scala 658:17]
  wire [127:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 652:72 653:28]
  wire [1026:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 1027'h0; // @[Monitor.scala 652:72 656:28]
  wire [1025:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 1026'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_605 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_607 = ~_T_401; // @[Monitor.scala 671:74]
  wire  _T_608 = io_in_d_valid & d_first_1 & ~_T_401; // @[Monitor.scala 671:71]
  wire [127:0] _d_clr_wo_ready_T = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [1038:0] _GEN_3 = {{1023'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [1038:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [127:0] _GEN_22 = d_first_done & d_first_1 & _T_607 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 675:91 676:21]
  wire [1038:0] _GEN_23 = d_first_done & d_first_1 & _T_607 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_594 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [95:0] _T_618 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_620 = _T_618[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_625 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_626 = io_in_d_bits_opcode == _GEN_32 | _T_625; // @[Monitor.scala 685:77]
  wire  _T_630 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_637 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_638 = io_in_d_bits_opcode == _GEN_48 | _T_637; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_642 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_652 = _T_605 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_607; // @[Monitor.scala 694:116]
  wire  _T_654 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [95:0] a_set = _GEN_16[95:0];
  wire [95:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [95:0] d_clr = _GEN_22[95:0];
  wire [95:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [95:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [383:0] a_opcodes_set = _GEN_19[383:0];
  wire [383:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [383:0] d_opcodes_clr = _GEN_23[383:0];
  wire [383:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [383:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [383:0] a_sizes_set = _GEN_20[383:0];
  wire [383:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [383:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_663 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [95:0] inflight_1; // @[Monitor.scala 723:35]
  reg [383:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [383:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [383:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
  wire [383:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[383:1]}; // @[Monitor.scala 747:146]
  wire  _T_689 = io_in_d_valid & d_first_2 & _T_401; // @[Monitor.scala 779:71]
  wire [127:0] _GEN_67 = d_first_done & d_first_2 & _T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 783:90 784:21]
  wire [1038:0] _GEN_68 = d_first_done & d_first_2 & _T_401 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 783:90 785:21]
  wire [95:0] _T_697 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_707 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [95:0] d_clr_1 = _GEN_67[95:0];
  wire [95:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [95:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [383:0] d_opcodes_clr_1 = _GEN_68[383:0];
  wire [383:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [383:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_727 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 1'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= 1'h0;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 96'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 384'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 384'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 1'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= 1'h0;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 96'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 384'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= 1'h0;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (d_first_done) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_172 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_172) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_275 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_275) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_309 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_309) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_347 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_347) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_385 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_397 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_397) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_478 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_478 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_495 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_495 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_513 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_513 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_544 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_544) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_548 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_548) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_552 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_552) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_556 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_556) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_560 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_560) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_568 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_568) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_576 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_576) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_580 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_580) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_601 & (_T_597 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_597 & ~reset & ~_T_601) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_620 & (_T_608 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & _T_2 & ~_T_620) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_626 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_626) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_630 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_630) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_638 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_638) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_642 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_642) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_654 & (_T_652 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_652 & _T_2 & ~_T_654) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_663 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_663) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_697[0] & (_T_689 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_689 & _T_2 & ~_T_697[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_707 & (_T_689 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_689 & _T_2 & ~_T_707) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_727 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_727) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[6:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[28:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[6:0];
  _RAND_10 = {3{`RANDOM}};
  inflight = _RAND_10[95:0];
  _RAND_11 = {12{`RANDOM}};
  inflight_opcodes = _RAND_11[383:0];
  _RAND_12 = {12{`RANDOM}};
  inflight_sizes = _RAND_12[383:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {3{`RANDOM}};
  inflight_1 = _RAND_16[95:0];
  _RAND_17 = {12{`RANDOM}};
  inflight_sizes_1 = _RAND_17[383:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module SPIRAMMap(
  input         clock,
  input         reset,
  input         io_en,
  input  [1:0]  io_ctrl_insn_cmd_proto,
  input  [7:0]  io_ctrl_insn_cmd_code,
  input         io_ctrl_insn_cmd_en,
  input  [7:0]  io_ctrl_insn_wcmd_code,
  input  [1:0]  io_ctrl_insn_addr_proto,
  input  [2:0]  io_ctrl_insn_addr_len,
  input  [7:0]  io_ctrl_insn_pad_code,
  input  [3:0]  io_ctrl_insn_pad_cnt,
  input  [1:0]  io_ctrl_insn_data_proto,
  input  [3:0]  io_ctrl_insn_pgsz,
  input  [11:0] io_ctrl_insn_max_cen_cyc,
  input         io_ctrl_fmt_endian,
  output        io_addr_ready,
  input         io_addr_valid,
  input  [31:0] io_addr_bits_next,
  input  [31:0] io_addr_bits_hold,
  input  [2:0]  io_opcode_next,
  input  [2:0]  io_opcode_hold,
  input  [7:0]  io_wdata,
  input         io_data_ready,
  output        io_data_valid,
  output [7:0]  io_data_bits,
  input         io_link_tx_ready,
  output        io_link_tx_valid,
  output [7:0]  io_link_tx_bits,
  input         io_link_rx_valid,
  input  [7:0]  io_link_rx_bits,
  output [7:0]  io_link_cnt,
  output [1:0]  io_link_fmt_proto,
  output        io_link_fmt_endian,
  output        io_link_fmt_iodir,
  output        io_link_cs_clear,
  input         io_link_active,
  output        io_link_lock
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] addr = io_addr_bits_hold + 32'h1; // @[SPIRAM.scala 76:32]
  wire  _GEN_0 = io_ctrl_insn_pgsz == 4'hc ? ~(|addr[11:0]) : 1'h1; // @[SPIRAM.scala 105:31 106:13 108:13]
  wire  _GEN_1 = io_ctrl_insn_pgsz == 4'hb ? ~(|addr[10:0]) : _GEN_0; // @[SPIRAM.scala 103:31 104:13]
  wire  _GEN_2 = io_ctrl_insn_pgsz == 4'ha ? ~(|addr[9:0]) : _GEN_1; // @[SPIRAM.scala 101:31 102:13]
  wire  _GEN_3 = io_ctrl_insn_pgsz == 4'h9 ? ~(|addr[8:0]) : _GEN_2; // @[SPIRAM.scala 100:13 99:30]
  wire  _GEN_4 = io_ctrl_insn_pgsz == 4'h8 ? ~(|addr[7:0]) : _GEN_3; // @[SPIRAM.scala 97:30 98:13]
  wire  _GEN_5 = io_ctrl_insn_pgsz == 4'h7 ? ~(|addr[6:0]) : _GEN_4; // @[SPIRAM.scala 95:30 96:13]
  wire  _GEN_6 = io_ctrl_insn_pgsz == 4'h6 ? ~(|addr[5:0]) : _GEN_5; // @[SPIRAM.scala 93:30 94:13]
  wire  _GEN_7 = io_ctrl_insn_pgsz == 4'h5 ? ~(|addr[4:0]) : _GEN_6; // @[SPIRAM.scala 91:30 92:13]
  wire  _GEN_8 = io_ctrl_insn_pgsz == 4'h4 ? ~(|addr[3:0]) : _GEN_7; // @[SPIRAM.scala 89:30 90:13]
  wire  _GEN_9 = io_ctrl_insn_pgsz == 4'h3 ? ~(|addr[2:0]) : _GEN_8; // @[SPIRAM.scala 87:30 88:13]
  wire  _GEN_10 = io_ctrl_insn_pgsz == 4'h2 ? ~(|addr[1:0]) : _GEN_9; // @[SPIRAM.scala 85:30 86:13]
  wire  _GEN_11 = io_ctrl_insn_pgsz == 4'h1 ? ~(|addr[0]) : _GEN_10; // @[SPIRAM.scala 83:30 84:13]
  wire  newpage = io_ctrl_insn_pgsz == 4'h0 | _GEN_11; // @[SPIRAM.scala 81:23 82:13]
  wire  _io_link_cnt_T = 2'h0 == io_link_fmt_proto; // @[SPIConsts.scala 13:48]
  wire  _io_link_cnt_T_1 = 2'h1 == io_link_fmt_proto; // @[SPIConsts.scala 13:48]
  wire  _io_link_cnt_T_2 = 2'h2 == io_link_fmt_proto; // @[SPIConsts.scala 13:48]
  wire [3:0] _io_link_cnt_T_3 = _io_link_cnt_T ? 4'h8 : 4'h0; // @[Mux.scala 27:73]
  wire [2:0] _io_link_cnt_T_4 = _io_link_cnt_T_1 ? 3'h4 : 3'h0; // @[Mux.scala 27:73]
  wire [1:0] _io_link_cnt_T_5 = _io_link_cnt_T_2 ? 2'h2 : 2'h0; // @[Mux.scala 27:73]
  wire [3:0] _GEN_116 = {{1'd0}, _io_link_cnt_T_4}; // @[Mux.scala 27:73]
  wire [3:0] _io_link_cnt_T_6 = _io_link_cnt_T_3 | _GEN_116; // @[Mux.scala 27:73]
  wire [3:0] _GEN_117 = {{2'd0}, _io_link_cnt_T_5}; // @[Mux.scala 27:73]
  wire [3:0] _io_link_cnt_T_7 = _io_link_cnt_T_6 | _GEN_117; // @[Mux.scala 27:73]
  reg [3:0] cnt; // @[SPIRAM.scala 130:16]
  wire  cnt_cmp_0 = cnt == 4'h0; // @[SPIRAM.scala 132:48]
  wire  cnt_cmp_1 = cnt == 4'h1; // @[SPIRAM.scala 132:48]
  wire  cnt_cmp_2 = cnt == 4'h2; // @[SPIRAM.scala 132:48]
  wire  cnt_cmp_3 = cnt == 4'h3; // @[SPIRAM.scala 132:48]
  wire  cnt_cmp_4 = cnt == 4'h4; // @[SPIRAM.scala 132:48]
  wire  cnt_last = cnt_cmp_1 & io_link_tx_ready; // @[SPIRAM.scala 134:29]
  wire  cnt_done = cnt_last | cnt_cmp_0; // @[SPIRAM.scala 135:27]
  wire  _T_13 = io_link_tx_ready & io_link_tx_valid; // @[Decoupled.scala 50:35]
  wire [3:0] _cnt_T_1 = cnt - 4'h1; // @[SPIRAM.scala 139:18]
  wire [3:0] _GEN_13 = _T_13 ? _cnt_T_1 : cnt; // @[SPIRAM.scala 138:28 139:11 130:16]
  reg [2:0] state; // @[SPIRAM.scala 156:18]
  wire  _GEN_94 = 3'h1 == state ? 1'h0 : 3'h2 == state; // @[SPIRAM.scala 158:18]
  wire  cnt_en = 3'h0 == state ? 1'h0 : _GEN_94; // @[SPIRAM.scala 158:18]
  wire  _GEN_14 = cnt_en ? ~cnt_cmp_0 : 1'h1; // @[SPIRAM.scala 136:17 112:20 137:22]
  wire [3:0] _GEN_15 = cnt_en ? _GEN_13 : cnt; // @[SPIRAM.scala 130:16 136:17]
  reg [15:0] cen_cnt; // @[SPIRAM.scala 144:24]
  wire [15:0] _cen_cnt_T_1 = cen_cnt + 16'h1; // @[SPIRAM.scala 146:24]
  reg  no_merge; // @[SPIRAM.scala 152:25]
  wire  merge = ~no_merge & io_link_active & ~newpage & io_addr_bits_next == addr & io_opcode_next == io_opcode_hold; // @[SPIRAM.scala 153:87]
  wire [2:0] _state_T = io_ctrl_insn_cmd_en ? 3'h1 : 3'h2; // @[SPIRAM.scala 167:25]
  wire [2:0] _GEN_17 = merge ? 3'h4 : _state_T; // @[SPIRAM.scala 164:24 165:19 167:19]
  wire  _GEN_18 = merge ? 1'h0 : 1'h1; // @[SPIRAM.scala 121:20 164:24 168:30]
  wire [15:0] _GEN_118 = {{4'd0}, io_ctrl_insn_max_cen_cyc}; // @[SPIRAM.scala 174:25]
  wire  _T_15 = cen_cnt >= _GEN_118; // @[SPIRAM.scala 174:25]
  wire  _GEN_20 = cen_cnt >= _GEN_118 | no_merge; // @[SPIRAM.scala 174:46 176:22 152:25]
  wire  _GEN_22 = io_addr_valid ? _GEN_18 : _T_15; // @[SPIRAM.scala 163:30]
  wire  _GEN_28 = io_en & _GEN_22; // @[SPIRAM.scala 121:20 161:20]
  wire  _GEN_30 = io_en & io_addr_valid; // @[SPIRAM.scala 161:20 181:22]
  wire  _T_17 = io_opcode_hold == 3'h0; // @[SPIRAM.scala 190:28]
  wire [7:0] _GEN_31 = io_opcode_hold == 3'h0 ? io_ctrl_insn_wcmd_code : io_ctrl_insn_cmd_code; // @[SPIRAM.scala 190:56 191:25 193:25]
  wire [7:0] _io_link_tx_bits_T_4 = cnt_cmp_1 ? io_addr_bits_hold[7:0] : 8'h0; // @[Mux.scala 27:73]
  wire [7:0] _io_link_tx_bits_T_5 = cnt_cmp_2 ? io_addr_bits_hold[15:8] : 8'h0; // @[Mux.scala 27:73]
  wire [7:0] _io_link_tx_bits_T_6 = cnt_cmp_3 ? io_addr_bits_hold[23:16] : 8'h0; // @[Mux.scala 27:73]
  wire [7:0] _io_link_tx_bits_T_7 = cnt_cmp_4 ? io_addr_bits_hold[31:24] : 8'h0; // @[Mux.scala 27:73]
  wire [7:0] _io_link_tx_bits_T_8 = _io_link_tx_bits_T_4 | _io_link_tx_bits_T_5; // @[Mux.scala 27:73]
  wire [7:0] _io_link_tx_bits_T_9 = _io_link_tx_bits_T_8 | _io_link_tx_bits_T_6; // @[Mux.scala 27:73]
  wire [7:0] _io_link_tx_bits_T_10 = _io_link_tx_bits_T_9 | _io_link_tx_bits_T_7; // @[Mux.scala 27:73]
  wire [2:0] _GEN_34 = cnt_done ? 3'h3 : state; // @[SPIRAM.scala 210:23 211:15 156:18]
  wire [3:0] _GEN_35 = _T_17 ? 4'h0 : io_ctrl_insn_pad_cnt; // @[SPIRAM.scala 216:56 217:21 219:21]
  wire [2:0] _GEN_36 = io_link_tx_ready ? 3'h4 : state; // @[SPIRAM.scala 224:31 225:15 156:18]
  wire  _GEN_38 = _T_17 | _GEN_14; // @[SPIRAM.scala 231:56 233:26]
  wire [2:0] _GEN_40 = io_link_tx_ready ? 3'h5 : state; // @[SPIRAM.scala 239:31 240:15 156:18]
  wire  _GEN_42 = _T_17 | io_link_rx_valid; // @[SPIRAM.scala 245:56 247:23 250:23]
  wire  _T_26 = io_data_ready & io_data_valid; // @[Decoupled.scala 50:35]
  wire [2:0] _GEN_46 = _T_26 ? 3'h0 : state; // @[SPIRAM.scala 259:27 260:15 156:18]
  wire [2:0] _GEN_47 = io_data_ready ? 3'h0 : state; // @[SPIRAM.scala 272:30 273:17 156:18]
  wire [2:0] _GEN_50 = _T_17 ? 3'h0 : _GEN_47; // @[SPIRAM.scala 265:56 268:15]
  wire [7:0] _GEN_52 = 3'h6 == state ? 8'h0 : io_link_rx_bits; // @[SPIRAM.scala 128:16 158:18]
  wire [2:0] _GEN_53 = 3'h6 == state ? _GEN_50 : state; // @[SPIRAM.scala 156:18 158:18]
  wire  _GEN_54 = 3'h5 == state ? 1'h0 : _GEN_14; // @[SPIRAM.scala 158:18]
  wire  _GEN_55 = 3'h5 == state ? _GEN_42 : 3'h6 == state; // @[SPIRAM.scala 158:18]
  wire [7:0] _GEN_56 = 3'h5 == state ? io_link_rx_bits : _GEN_52; // @[SPIRAM.scala 158:18]
  wire  _GEN_58 = 3'h5 == state ? _GEN_20 : no_merge; // @[SPIRAM.scala 158:18 152:25]
  wire [2:0] _GEN_59 = 3'h5 == state ? _GEN_46 : _GEN_53; // @[SPIRAM.scala 158:18]
  wire [1:0] _GEN_60 = 3'h4 == state ? io_ctrl_insn_data_proto : io_ctrl_insn_addr_proto; // @[SPIRAM.scala 158:18 113:21 230:25]
  wire  _GEN_61 = 3'h4 == state ? _T_17 : 1'h1; // @[SPIRAM.scala 158:18 114:21]
  wire  _GEN_62 = 3'h4 == state ? _GEN_38 : _GEN_54; // @[SPIRAM.scala 158:18]
  wire [2:0] _GEN_64 = 3'h4 == state ? _GEN_40 : _GEN_59; // @[SPIRAM.scala 158:18]
  wire  _GEN_65 = 3'h4 == state ? 1'h0 : _GEN_55; // @[SPIRAM.scala 127:17 158:18]
  wire [7:0] _GEN_66 = 3'h4 == state ? io_link_rx_bits : _GEN_56; // @[SPIRAM.scala 128:16 158:18]
  wire  _GEN_67 = 3'h4 == state ? 1'h0 : 3'h5 == state & _T_15; // @[SPIRAM.scala 158:18 121:20]
  wire  _GEN_68 = 3'h4 == state ? no_merge : _GEN_58; // @[SPIRAM.scala 158:18 152:25]
  wire [3:0] _GEN_69 = 3'h3 == state ? _GEN_35 : _io_link_cnt_T_7; // @[SPIRAM.scala 116:15 158:18]
  wire [7:0] _GEN_70 = 3'h3 == state ? io_ctrl_insn_pad_code : io_wdata; // @[SPIRAM.scala 158:18 222:23]
  wire [2:0] _GEN_71 = 3'h3 == state ? _GEN_36 : _GEN_64; // @[SPIRAM.scala 158:18]
  wire [1:0] _GEN_72 = 3'h3 == state ? io_ctrl_insn_addr_proto : _GEN_60; // @[SPIRAM.scala 158:18 113:21]
  wire  _GEN_74 = 3'h3 == state ? _GEN_14 : _GEN_62; // @[SPIRAM.scala 158:18]
  wire  _GEN_75 = 3'h3 == state ? 1'h0 : _GEN_65; // @[SPIRAM.scala 127:17 158:18]
  wire [7:0] _GEN_76 = 3'h3 == state ? io_link_rx_bits : _GEN_66; // @[SPIRAM.scala 128:16 158:18]
  wire  _GEN_77 = 3'h3 == state ? 1'h0 : _GEN_67; // @[SPIRAM.scala 158:18 121:20]
  wire  _GEN_78 = 3'h3 == state ? no_merge : _GEN_68; // @[SPIRAM.scala 158:18 152:25]
  wire [7:0] _GEN_79 = 3'h2 == state ? _io_link_tx_bits_T_10 : _GEN_70; // @[SPIRAM.scala 158:18 202:23]
  wire [3:0] _GEN_82 = 3'h2 == state ? _io_link_cnt_T_7 : _GEN_69; // @[SPIRAM.scala 116:15 158:18]
  wire [1:0] _GEN_83 = 3'h2 == state ? io_ctrl_insn_addr_proto : _GEN_72; // @[SPIRAM.scala 158:18 113:21]
  wire  _GEN_85 = 3'h2 == state ? _GEN_14 : _GEN_74; // @[SPIRAM.scala 158:18]
  wire  _GEN_86 = 3'h2 == state ? 1'h0 : _GEN_75; // @[SPIRAM.scala 127:17 158:18]
  wire [7:0] _GEN_87 = 3'h2 == state ? io_link_rx_bits : _GEN_76; // @[SPIRAM.scala 128:16 158:18]
  wire  _GEN_88 = 3'h2 == state ? 1'h0 : _GEN_77; // @[SPIRAM.scala 158:18 121:20]
  wire [1:0] _GEN_90 = 3'h1 == state ? io_ctrl_insn_cmd_proto : _GEN_83; // @[SPIRAM.scala 158:18 189:25]
  wire [3:0] _GEN_95 = 3'h1 == state ? _io_link_cnt_T_7 : _GEN_82; // @[SPIRAM.scala 116:15 158:18]
  wire  _GEN_97 = 3'h1 == state ? _GEN_14 : _GEN_85; // @[SPIRAM.scala 158:18]
  wire  _GEN_98 = 3'h1 == state ? 1'h0 : _GEN_86; // @[SPIRAM.scala 127:17 158:18]
  wire [7:0] _GEN_99 = 3'h1 == state ? io_link_rx_bits : _GEN_87; // @[SPIRAM.scala 128:16 158:18]
  wire  _GEN_100 = 3'h1 == state ? 1'h0 : _GEN_88; // @[SPIRAM.scala 158:18 121:20]
  wire [3:0] _GEN_112 = 3'h0 == state ? _io_link_cnt_T_7 : _GEN_95; // @[SPIRAM.scala 116:15 158:18]
  assign io_addr_ready = 3'h0 == state; // @[SPIRAM.scala 158:18]
  assign io_data_valid = 3'h0 == state ? 1'h0 : _GEN_98; // @[SPIRAM.scala 127:17 158:18]
  assign io_data_bits = 3'h0 == state ? io_link_rx_bits : _GEN_99; // @[SPIRAM.scala 128:16 158:18]
  assign io_link_tx_valid = 3'h0 == state ? 1'h0 : _GEN_97; // @[SPIRAM.scala 158:18 160:24]
  assign io_link_tx_bits = 3'h1 == state ? _GEN_31 : _GEN_79; // @[SPIRAM.scala 158:18]
  assign io_link_cnt = {{4'd0}, _GEN_112};
  assign io_link_fmt_proto = 3'h0 == state ? io_ctrl_insn_addr_proto : _GEN_90; // @[SPIRAM.scala 158:18 113:21]
  assign io_link_fmt_endian = io_ctrl_fmt_endian; // @[SPIRAM.scala 115:22]
  assign io_link_fmt_iodir = 3'h0 == state | (3'h1 == state | (3'h2 == state | (3'h3 == state | _GEN_61))); // @[SPIRAM.scala 158:18 114:21]
  assign io_link_cs_clear = 3'h0 == state ? _GEN_28 : _GEN_100; // @[SPIRAM.scala 158:18]
  assign io_link_lock = 3'h0 == state ? _GEN_30 : 1'h1; // @[SPIRAM.scala 123:16 158:18]
  always @(posedge clock) begin
    if (3'h0 == state) begin // @[SPIRAM.scala 158:18]
      cnt <= _GEN_15;
    end else if (3'h1 == state) begin // @[SPIRAM.scala 158:18]
      if (io_link_tx_ready) begin // @[SPIRAM.scala 195:31]
        cnt <= {{1'd0}, io_ctrl_insn_addr_len}; // @[SPIRAM.scala 197:13]
      end else begin
        cnt <= _GEN_15;
      end
    end else begin
      cnt <= _GEN_15;
    end
    if (reset) begin // @[SPIRAM.scala 156:18]
      state <= 3'h0; // @[SPIRAM.scala 156:18]
    end else if (3'h0 == state) begin // @[SPIRAM.scala 158:18]
      if (io_en) begin // @[SPIRAM.scala 161:20]
        if (io_addr_valid) begin // @[SPIRAM.scala 163:30]
          state <= _GEN_17;
        end
      end else if (io_addr_valid) begin // @[SPIRAM.scala 182:30]
        state <= 3'h6; // @[SPIRAM.scala 183:17]
      end
    end else if (3'h1 == state) begin // @[SPIRAM.scala 158:18]
      if (io_link_tx_ready) begin // @[SPIRAM.scala 195:31]
        state <= 3'h2; // @[SPIRAM.scala 196:15]
      end
    end else if (3'h2 == state) begin // @[SPIRAM.scala 158:18]
      state <= _GEN_34;
    end else begin
      state <= _GEN_71;
    end
    if (reset) begin // @[SPIRAM.scala 144:24]
      cen_cnt <= 16'h0; // @[SPIRAM.scala 144:24]
    end else if (io_link_active) begin // @[SPIRAM.scala 145:25]
      cen_cnt <= _cen_cnt_T_1; // @[SPIRAM.scala 146:13]
    end else begin
      cen_cnt <= 16'h0; // @[SPIRAM.scala 148:13]
    end
    if (reset) begin // @[SPIRAM.scala 152:25]
      no_merge <= 1'h0; // @[SPIRAM.scala 152:25]
    end else if (3'h0 == state) begin // @[SPIRAM.scala 158:18]
      if (io_en) begin // @[SPIRAM.scala 161:20]
        if (io_addr_valid) begin // @[SPIRAM.scala 163:30]
          no_merge <= 1'h0; // @[SPIRAM.scala 170:20]
        end else begin
          no_merge <= _GEN_20;
        end
      end
    end else if (!(3'h1 == state)) begin // @[SPIRAM.scala 158:18]
      if (!(3'h2 == state)) begin // @[SPIRAM.scala 158:18]
        no_merge <= _GEN_78;
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  cnt = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  state = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  cen_cnt = _RAND_2[15:0];
  _RAND_3 = {1{`RANDOM}};
  no_merge = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLSPIRAM(
  input         clock,
  input         reset,
  output        auto_int_xing_out_sync_0,
  output        auto_mem_xing_in_a_ready,
  input         auto_mem_xing_in_a_valid,
  input  [2:0]  auto_mem_xing_in_a_bits_opcode,
  input  [2:0]  auto_mem_xing_in_a_bits_param,
  input         auto_mem_xing_in_a_bits_size,
  input  [10:0] auto_mem_xing_in_a_bits_source,
  input  [30:0] auto_mem_xing_in_a_bits_address,
  input         auto_mem_xing_in_a_bits_mask,
  input  [7:0]  auto_mem_xing_in_a_bits_data,
  input         auto_mem_xing_in_a_bits_corrupt,
  input         auto_mem_xing_in_d_ready,
  output        auto_mem_xing_in_d_valid,
  output [2:0]  auto_mem_xing_in_d_bits_opcode,
  output        auto_mem_xing_in_d_bits_size,
  output [10:0] auto_mem_xing_in_d_bits_source,
  output [7:0]  auto_mem_xing_in_d_bits_data,
  output        auto_control_xing_in_a_ready,
  input         auto_control_xing_in_a_valid,
  input  [2:0]  auto_control_xing_in_a_bits_opcode,
  input  [2:0]  auto_control_xing_in_a_bits_param,
  input  [1:0]  auto_control_xing_in_a_bits_size,
  input  [6:0]  auto_control_xing_in_a_bits_source,
  input  [28:0] auto_control_xing_in_a_bits_address,
  input  [3:0]  auto_control_xing_in_a_bits_mask,
  input  [31:0] auto_control_xing_in_a_bits_data,
  input         auto_control_xing_in_a_bits_corrupt,
  input         auto_control_xing_in_d_ready,
  output        auto_control_xing_in_d_valid,
  output [2:0]  auto_control_xing_in_d_bits_opcode,
  output [1:0]  auto_control_xing_in_d_bits_size,
  output [6:0]  auto_control_xing_in_d_bits_source,
  output [31:0] auto_control_xing_in_d_bits_data,
  output        auto_io_out_sck,
  input         auto_io_out_dq_0_i,
  output        auto_io_out_dq_0_o,
  output        auto_io_out_dq_0_oe,
  input         auto_io_out_dq_1_i,
  output        auto_io_out_dq_1_o,
  output        auto_io_out_dq_1_oe,
  input         auto_io_out_dq_2_i,
  output        auto_io_out_dq_2_o,
  output        auto_io_out_dq_2_oe,
  input         auto_io_out_dq_3_i,
  output        auto_io_out_dq_3_o,
  output        auto_io_out_dq_3_oe,
  output        auto_io_out_cs_0
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [31:0] _RAND_33;
  reg [31:0] _RAND_34;
  reg [31:0] _RAND_35;
  reg [31:0] _RAND_36;
`endif // RANDOMIZE_REG_INIT
  wire  buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
  wire [28:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
  wire [28:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_in_a_bits_param; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_a_bits_size; // @[Buffer.scala 68:28]
  wire [10:0] buffer_1_auto_in_a_bits_source; // @[Buffer.scala 68:28]
  wire [30:0] buffer_1_auto_in_a_bits_address; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
  wire [7:0] buffer_1_auto_in_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_in_d_bits_size; // @[Buffer.scala 68:28]
  wire [10:0] buffer_1_auto_in_d_bits_source; // @[Buffer.scala 68:28]
  wire [7:0] buffer_1_auto_in_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_out_a_bits_param; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_a_bits_size; // @[Buffer.scala 68:28]
  wire [10:0] buffer_1_auto_out_a_bits_source; // @[Buffer.scala 68:28]
  wire [30:0] buffer_1_auto_out_a_bits_address; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
  wire [7:0] buffer_1_auto_out_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_1_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
  wire  buffer_1_auto_out_d_bits_size; // @[Buffer.scala 68:28]
  wire [10:0] buffer_1_auto_out_d_bits_source; // @[Buffer.scala 68:28]
  wire [7:0] buffer_1_auto_out_d_bits_data; // @[Buffer.scala 68:28]
  wire  intsource_clock; // @[Crossing.scala 26:31]
  wire  intsource_reset; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_0; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_0; // @[Crossing.scala 26:31]
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [10:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [30:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [10:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  monitor_1_clock; // @[Nodes.scala 24:25]
  wire  monitor_1_reset; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_1_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_1_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [1:0] monitor_1_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_1_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [28:0] monitor_1_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_1_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_1_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_1_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_1_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_1_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  fifo_clock; // @[TLSPI.scala 69:20]
  wire  fifo_reset; // @[TLSPI.scala 69:20]
  wire [1:0] fifo_io_ctrl_fmt_proto; // @[TLSPI.scala 69:20]
  wire  fifo_io_ctrl_fmt_endian; // @[TLSPI.scala 69:20]
  wire  fifo_io_ctrl_fmt_iodir; // @[TLSPI.scala 69:20]
  wire [3:0] fifo_io_ctrl_fmt_len; // @[TLSPI.scala 69:20]
  wire [1:0] fifo_io_ctrl_cs_mode; // @[TLSPI.scala 69:20]
  wire [3:0] fifo_io_ctrl_wm_tx; // @[TLSPI.scala 69:20]
  wire [3:0] fifo_io_ctrl_wm_rx; // @[TLSPI.scala 69:20]
  wire  fifo_io_link_tx_ready; // @[TLSPI.scala 69:20]
  wire  fifo_io_link_tx_valid; // @[TLSPI.scala 69:20]
  wire [7:0] fifo_io_link_tx_bits; // @[TLSPI.scala 69:20]
  wire  fifo_io_link_rx_valid; // @[TLSPI.scala 69:20]
  wire [7:0] fifo_io_link_rx_bits; // @[TLSPI.scala 69:20]
  wire [7:0] fifo_io_link_cnt; // @[TLSPI.scala 69:20]
  wire [1:0] fifo_io_link_fmt_proto; // @[TLSPI.scala 69:20]
  wire  fifo_io_link_fmt_endian; // @[TLSPI.scala 69:20]
  wire  fifo_io_link_fmt_iodir; // @[TLSPI.scala 69:20]
  wire  fifo_io_link_cs_set; // @[TLSPI.scala 69:20]
  wire  fifo_io_link_cs_clear; // @[TLSPI.scala 69:20]
  wire  fifo_io_link_lock; // @[TLSPI.scala 69:20]
  wire  fifo_io_tx_ready; // @[TLSPI.scala 69:20]
  wire  fifo_io_tx_valid; // @[TLSPI.scala 69:20]
  wire [7:0] fifo_io_tx_bits; // @[TLSPI.scala 69:20]
  wire  fifo_io_rx_ready; // @[TLSPI.scala 69:20]
  wire  fifo_io_rx_valid; // @[TLSPI.scala 69:20]
  wire [7:0] fifo_io_rx_bits; // @[TLSPI.scala 69:20]
  wire  fifo_io_ip_txwm; // @[TLSPI.scala 69:20]
  wire  fifo_io_ip_rxwm; // @[TLSPI.scala 69:20]
  wire  mac_clock; // @[TLSPI.scala 70:19]
  wire  mac_reset; // @[TLSPI.scala 70:19]
  wire  mac_io_port_sck; // @[TLSPI.scala 70:19]
  wire  mac_io_port_dq_0_i; // @[TLSPI.scala 70:19]
  wire  mac_io_port_dq_0_o; // @[TLSPI.scala 70:19]
  wire  mac_io_port_dq_0_oe; // @[TLSPI.scala 70:19]
  wire  mac_io_port_dq_1_i; // @[TLSPI.scala 70:19]
  wire  mac_io_port_dq_1_o; // @[TLSPI.scala 70:19]
  wire  mac_io_port_dq_1_oe; // @[TLSPI.scala 70:19]
  wire  mac_io_port_dq_2_i; // @[TLSPI.scala 70:19]
  wire  mac_io_port_dq_2_o; // @[TLSPI.scala 70:19]
  wire  mac_io_port_dq_2_oe; // @[TLSPI.scala 70:19]
  wire  mac_io_port_dq_3_i; // @[TLSPI.scala 70:19]
  wire  mac_io_port_dq_3_o; // @[TLSPI.scala 70:19]
  wire  mac_io_port_dq_3_oe; // @[TLSPI.scala 70:19]
  wire  mac_io_port_cs_0; // @[TLSPI.scala 70:19]
  wire [11:0] mac_io_ctrl_sck_div; // @[TLSPI.scala 70:19]
  wire  mac_io_ctrl_sck_pol; // @[TLSPI.scala 70:19]
  wire  mac_io_ctrl_sck_pha; // @[TLSPI.scala 70:19]
  wire [7:0] mac_io_ctrl_dla_cssck; // @[TLSPI.scala 70:19]
  wire [7:0] mac_io_ctrl_dla_sckcs; // @[TLSPI.scala 70:19]
  wire [7:0] mac_io_ctrl_dla_intercs; // @[TLSPI.scala 70:19]
  wire [7:0] mac_io_ctrl_dla_interxfr; // @[TLSPI.scala 70:19]
  wire  mac_io_ctrl_cs_id; // @[TLSPI.scala 70:19]
  wire  mac_io_ctrl_cs_dflt_0; // @[TLSPI.scala 70:19]
  wire [11:0] mac_io_ctrl_extradel_coarse; // @[TLSPI.scala 70:19]
  wire [4:0] mac_io_ctrl_sampledel_sd; // @[TLSPI.scala 70:19]
  wire  mac_io_link_tx_ready; // @[TLSPI.scala 70:19]
  wire  mac_io_link_tx_valid; // @[TLSPI.scala 70:19]
  wire [7:0] mac_io_link_tx_bits; // @[TLSPI.scala 70:19]
  wire  mac_io_link_rx_valid; // @[TLSPI.scala 70:19]
  wire [7:0] mac_io_link_rx_bits; // @[TLSPI.scala 70:19]
  wire [7:0] mac_io_link_cnt; // @[TLSPI.scala 70:19]
  wire [1:0] mac_io_link_fmt_proto; // @[TLSPI.scala 70:19]
  wire  mac_io_link_fmt_endian; // @[TLSPI.scala 70:19]
  wire  mac_io_link_fmt_iodir; // @[TLSPI.scala 70:19]
  wire  mac_io_link_cs_set; // @[TLSPI.scala 70:19]
  wire  mac_io_link_cs_clear; // @[TLSPI.scala 70:19]
  wire  mac_io_link_cs_hold; // @[TLSPI.scala 70:19]
  wire  mac_io_link_active; // @[TLSPI.scala 70:19]
  wire  ram_clock; // @[TLSPIRAM.scala 58:19]
  wire  ram_reset; // @[TLSPIRAM.scala 58:19]
  wire  ram_io_en; // @[TLSPIRAM.scala 58:19]
  wire [1:0] ram_io_ctrl_insn_cmd_proto; // @[TLSPIRAM.scala 58:19]
  wire [7:0] ram_io_ctrl_insn_cmd_code; // @[TLSPIRAM.scala 58:19]
  wire  ram_io_ctrl_insn_cmd_en; // @[TLSPIRAM.scala 58:19]
  wire [7:0] ram_io_ctrl_insn_wcmd_code; // @[TLSPIRAM.scala 58:19]
  wire [1:0] ram_io_ctrl_insn_addr_proto; // @[TLSPIRAM.scala 58:19]
  wire [2:0] ram_io_ctrl_insn_addr_len; // @[TLSPIRAM.scala 58:19]
  wire [7:0] ram_io_ctrl_insn_pad_code; // @[TLSPIRAM.scala 58:19]
  wire [3:0] ram_io_ctrl_insn_pad_cnt; // @[TLSPIRAM.scala 58:19]
  wire [1:0] ram_io_ctrl_insn_data_proto; // @[TLSPIRAM.scala 58:19]
  wire [3:0] ram_io_ctrl_insn_pgsz; // @[TLSPIRAM.scala 58:19]
  wire [11:0] ram_io_ctrl_insn_max_cen_cyc; // @[TLSPIRAM.scala 58:19]
  wire  ram_io_ctrl_fmt_endian; // @[TLSPIRAM.scala 58:19]
  wire  ram_io_addr_ready; // @[TLSPIRAM.scala 58:19]
  wire  ram_io_addr_valid; // @[TLSPIRAM.scala 58:19]
  wire [31:0] ram_io_addr_bits_next; // @[TLSPIRAM.scala 58:19]
  wire [31:0] ram_io_addr_bits_hold; // @[TLSPIRAM.scala 58:19]
  wire [2:0] ram_io_opcode_next; // @[TLSPIRAM.scala 58:19]
  wire [2:0] ram_io_opcode_hold; // @[TLSPIRAM.scala 58:19]
  wire [7:0] ram_io_wdata; // @[TLSPIRAM.scala 58:19]
  wire  ram_io_data_ready; // @[TLSPIRAM.scala 58:19]
  wire  ram_io_data_valid; // @[TLSPIRAM.scala 58:19]
  wire [7:0] ram_io_data_bits; // @[TLSPIRAM.scala 58:19]
  wire  ram_io_link_tx_ready; // @[TLSPIRAM.scala 58:19]
  wire  ram_io_link_tx_valid; // @[TLSPIRAM.scala 58:19]
  wire [7:0] ram_io_link_tx_bits; // @[TLSPIRAM.scala 58:19]
  wire  ram_io_link_rx_valid; // @[TLSPIRAM.scala 58:19]
  wire [7:0] ram_io_link_rx_bits; // @[TLSPIRAM.scala 58:19]
  wire [7:0] ram_io_link_cnt; // @[TLSPIRAM.scala 58:19]
  wire [1:0] ram_io_link_fmt_proto; // @[TLSPIRAM.scala 58:19]
  wire  ram_io_link_fmt_endian; // @[TLSPIRAM.scala 58:19]
  wire  ram_io_link_fmt_iodir; // @[TLSPIRAM.scala 58:19]
  wire  ram_io_link_cs_clear; // @[TLSPIRAM.scala 58:19]
  wire  ram_io_link_active; // @[TLSPIRAM.scala 58:19]
  wire  ram_io_link_lock; // @[TLSPIRAM.scala 58:19]
  wire  arb_clock; // @[TLSPIRAM.scala 59:19]
  wire  arb_reset; // @[TLSPIRAM.scala 59:19]
  wire  arb_io_inner_0_tx_ready; // @[TLSPIRAM.scala 59:19]
  wire  arb_io_inner_0_tx_valid; // @[TLSPIRAM.scala 59:19]
  wire [7:0] arb_io_inner_0_tx_bits; // @[TLSPIRAM.scala 59:19]
  wire  arb_io_inner_0_rx_valid; // @[TLSPIRAM.scala 59:19]
  wire [7:0] arb_io_inner_0_rx_bits; // @[TLSPIRAM.scala 59:19]
  wire [7:0] arb_io_inner_0_cnt; // @[TLSPIRAM.scala 59:19]
  wire [1:0] arb_io_inner_0_fmt_proto; // @[TLSPIRAM.scala 59:19]
  wire  arb_io_inner_0_fmt_endian; // @[TLSPIRAM.scala 59:19]
  wire  arb_io_inner_0_fmt_iodir; // @[TLSPIRAM.scala 59:19]
  wire  arb_io_inner_0_cs_clear; // @[TLSPIRAM.scala 59:19]
  wire  arb_io_inner_0_active; // @[TLSPIRAM.scala 59:19]
  wire  arb_io_inner_0_lock; // @[TLSPIRAM.scala 59:19]
  wire  arb_io_inner_1_tx_ready; // @[TLSPIRAM.scala 59:19]
  wire  arb_io_inner_1_tx_valid; // @[TLSPIRAM.scala 59:19]
  wire [7:0] arb_io_inner_1_tx_bits; // @[TLSPIRAM.scala 59:19]
  wire  arb_io_inner_1_rx_valid; // @[TLSPIRAM.scala 59:19]
  wire [7:0] arb_io_inner_1_rx_bits; // @[TLSPIRAM.scala 59:19]
  wire [7:0] arb_io_inner_1_cnt; // @[TLSPIRAM.scala 59:19]
  wire [1:0] arb_io_inner_1_fmt_proto; // @[TLSPIRAM.scala 59:19]
  wire  arb_io_inner_1_fmt_endian; // @[TLSPIRAM.scala 59:19]
  wire  arb_io_inner_1_fmt_iodir; // @[TLSPIRAM.scala 59:19]
  wire  arb_io_inner_1_cs_set; // @[TLSPIRAM.scala 59:19]
  wire  arb_io_inner_1_cs_clear; // @[TLSPIRAM.scala 59:19]
  wire  arb_io_inner_1_lock; // @[TLSPIRAM.scala 59:19]
  wire  arb_io_outer_tx_ready; // @[TLSPIRAM.scala 59:19]
  wire  arb_io_outer_tx_valid; // @[TLSPIRAM.scala 59:19]
  wire [7:0] arb_io_outer_tx_bits; // @[TLSPIRAM.scala 59:19]
  wire  arb_io_outer_rx_valid; // @[TLSPIRAM.scala 59:19]
  wire [7:0] arb_io_outer_rx_bits; // @[TLSPIRAM.scala 59:19]
  wire [7:0] arb_io_outer_cnt; // @[TLSPIRAM.scala 59:19]
  wire [1:0] arb_io_outer_fmt_proto; // @[TLSPIRAM.scala 59:19]
  wire  arb_io_outer_fmt_endian; // @[TLSPIRAM.scala 59:19]
  wire  arb_io_outer_fmt_iodir; // @[TLSPIRAM.scala 59:19]
  wire  arb_io_outer_cs_set; // @[TLSPIRAM.scala 59:19]
  wire  arb_io_outer_cs_clear; // @[TLSPIRAM.scala 59:19]
  wire  arb_io_outer_cs_hold; // @[TLSPIRAM.scala 59:19]
  wire  arb_io_outer_active; // @[TLSPIRAM.scala 59:19]
  wire  arb_io_sel; // @[TLSPIRAM.scala 59:19]
  reg [1:0] ctrl_fmt_proto; // @[TLSPI.scala 68:17]
  reg  ctrl_fmt_endian; // @[TLSPI.scala 68:17]
  reg  ctrl_fmt_iodir; // @[TLSPI.scala 68:17]
  reg [3:0] ctrl_fmt_len; // @[TLSPI.scala 68:17]
  reg [11:0] ctrl_sck_div; // @[TLSPI.scala 68:17]
  reg  ctrl_sck_pol; // @[TLSPI.scala 68:17]
  reg  ctrl_sck_pha; // @[TLSPI.scala 68:17]
  reg  ctrl_cs_id; // @[TLSPI.scala 68:17]
  reg  ctrl_cs_dflt_0; // @[TLSPI.scala 68:17]
  reg [1:0] ctrl_cs_mode; // @[TLSPI.scala 68:17]
  reg [7:0] ctrl_dla_cssck; // @[TLSPI.scala 68:17]
  reg [7:0] ctrl_dla_sckcs; // @[TLSPI.scala 68:17]
  reg [7:0] ctrl_dla_intercs; // @[TLSPI.scala 68:17]
  reg [7:0] ctrl_dla_interxfr; // @[TLSPI.scala 68:17]
  reg [3:0] ctrl_wm_tx; // @[TLSPI.scala 68:17]
  reg [3:0] ctrl_wm_rx; // @[TLSPI.scala 68:17]
  reg [11:0] ctrl_extradel_coarse; // @[TLSPI.scala 68:17]
  reg [4:0] ctrl_sampledel_sd; // @[TLSPI.scala 68:17]
  reg  ie_txwm; // @[TLSPI.scala 82:15]
  reg  ie_rxwm; // @[TLSPI.scala 82:15]
  wire  _T = ~fifo_io_tx_ready; // @[RegMapFIFO.scala 25:9]
  wire  _T_1 = ~fifo_io_rx_valid; // @[RegMapFIFO.scala 46:21]
  reg [2:0] a_opcode; // @[TLSPIRAM.scala 67:14]
  reg  a_size; // @[TLSPIRAM.scala 67:14]
  reg [10:0] a_source; // @[TLSPIRAM.scala 67:14]
  reg [30:0] a_address; // @[TLSPIRAM.scala 67:14]
  reg [7:0] a_data; // @[TLSPIRAM.scala 67:14]
  wire  bundleIn_0_a_ready = ram_io_addr_ready; // @[Nodes.scala 1210:84 TLSPIRAM.scala 80:13]
  wire  bundleIn_0_a_valid = buffer_1_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  _T_2 = bundleIn_0_a_ready & bundleIn_0_a_valid; // @[Decoupled.scala 50:35]
  wire [2:0] bundleIn_0_a_bits_opcode = buffer_1_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  bundleIn_0_a_bits_size = buffer_1_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [10:0] bundleIn_0_a_bits_source = buffer_1_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [30:0] bundleIn_0_a_bits_address = buffer_1_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [7:0] bundleIn_0_a_bits_data = buffer_1_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [7:0] bundleIn_0_d_bits_d_1_data = ram_io_data_bits; // @[Edges.scala 771:17 778:15]
  reg [1:0] insn_cmd_proto; // @[TLSPIRAM.scala 90:17]
  reg [7:0] insn_cmd_code; // @[TLSPIRAM.scala 90:17]
  reg  insn_cmd_en; // @[TLSPIRAM.scala 90:17]
  reg [7:0] insn_wcmd_code; // @[TLSPIRAM.scala 90:17]
  reg [1:0] insn_addr_proto; // @[TLSPIRAM.scala 90:17]
  reg [2:0] insn_addr_len; // @[TLSPIRAM.scala 90:17]
  reg [7:0] insn_pad_code; // @[TLSPIRAM.scala 90:17]
  reg [3:0] insn_pad_cnt; // @[TLSPIRAM.scala 90:17]
  reg [1:0] insn_data_proto; // @[TLSPIRAM.scala 90:17]
  reg [3:0] insn_pgsz; // @[TLSPIRAM.scala 90:17]
  reg [11:0] insn_max_cen_cyc; // @[TLSPIRAM.scala 90:17]
  reg  ram_en; // @[TLSPIRAM.scala 91:19]
  wire [2:0] bundleIn_0_1_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  in_bits_read = bundleIn_0_1_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 72:36]
  wire [28:0] bundleIn_0_1_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [9:0] in_bits_index = bundleIn_0_1_a_bits_address[11:2]; // @[RegisterRouter.scala 71:18 73:19]
  wire [9:0] out_findex = in_bits_index & 10'h3e0; // @[RegisterRouter.scala 83:24]
  wire  _out_T = out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [3:0] bundleIn_0_1_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [7:0] _out_frontMask_T_5 = bundleIn_0_1_a_bits_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_frontMask_T_7 = bundleIn_0_1_a_bits_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_frontMask_T_9 = bundleIn_0_1_a_bits_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_frontMask_T_11 = bundleIn_0_1_a_bits_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [31:0] out_frontMask = {_out_frontMask_T_11,_out_frontMask_T_9,_out_frontMask_T_7,_out_frontMask_T_5}; // @[Cat.scala 31:58]
  wire  out_wimask = &out_frontMask[11:0]; // @[RegisterRouter.scala 83:24]
  wire  bundleIn_0_1_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  bundleIn_0_1_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [4:0] out_oindex = {in_bits_index[4],in_bits_index[3],in_bits_index[2],in_bits_index[1],in_bits_index[0]}; // @[Cat.scala 31:58]
  wire [31:0] _out_frontSel_T = 32'h1 << out_oindex; // @[OneHot.scala 57:35]
  wire  out_frontSel_0 = _out_frontSel_T[0]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_0 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_0 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala 83:24]
  wire [31:0] bundleIn_0_1_a_bits_data = buffer_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  out_wimask_1 = &out_frontMask[0]; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_5 = _out_frontSel_T[5]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_1 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_5 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala 83:24]
  wire  _GEN_17 = out_f_wivalid_1 ? bundleIn_0_1_a_bits_data[0] : ctrl_cs_dflt_0; // @[RegField.scala 74:{88,92} TLSPI.scala 68:17]
  wire  out_rimask_2 = |out_frontMask[7:0]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_2 = &out_frontMask[7:0]; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_10 = _out_frontSel_T[10]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_2 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_10 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_3 = &out_frontMask[23:16]; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_3 = out_wivalid_2 & out_wimask_3; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_prepend_T = {{8'd0}, ctrl_dla_cssck}; // @[RegisterRouter.scala 83:24]
  wire [23:0] out_prepend = {ctrl_dla_sckcs,_out_prepend_T}; // @[Cat.scala 31:58]
  wire  out_frontSel_24 = _out_frontSel_T[24]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_4 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_24 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_4 = out_wivalid_4 & out_wimask_1; // @[RegisterRouter.scala 83:24]
  wire  _GEN_20 = out_f_wivalid_4 ? bundleIn_0_1_a_bits_data[0] : ram_en; // @[RegField.scala 74:{88,92} TLSPIRAM.scala 91:19]
  wire  out_frontSel_25 = _out_frontSel_T[25]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_5 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_25 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_5 = out_wivalid_5 & out_wimask_1; // @[RegisterRouter.scala 83:24]
  wire  _GEN_21 = out_f_wivalid_5 ? bundleIn_0_1_a_bits_data[0] : insn_cmd_en; // @[RegField.scala 74:{88,92} TLSPIRAM.scala 90:17]
  wire  out_wimask_6 = &out_frontMask[3:1]; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_6 = out_wivalid_5 & out_wimask_6; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_7 = &out_frontMask[7:4]; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_7 = out_wivalid_5 & out_wimask_7; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_8 = &out_frontMask[9:8]; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_8 = out_wivalid_5 & out_wimask_8; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_9 = &out_frontMask[11:10]; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_9 = out_wivalid_5 & out_wimask_9; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_10 = &out_frontMask[13:12]; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_10 = out_wivalid_5 & out_wimask_10; // @[RegisterRouter.scala 83:24]
  wire [13:0] out_prepend_5 = {insn_data_proto,insn_addr_proto,insn_cmd_proto,insn_pad_cnt,insn_addr_len,insn_cmd_en}; // @[Cat.scala 31:58]
  wire  out_f_wivalid_11 = out_wivalid_5 & out_wimask_3; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_prepend_T_6 = {{2'd0}, out_prepend_5}; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_12 = &out_frontMask[31:24]; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_12 = out_wivalid_5 & out_wimask_12; // @[RegisterRouter.scala 83:24]
  wire [31:0] out_prepend_7 = {insn_pad_code,insn_cmd_code,_out_prepend_T_6}; // @[Cat.scala 31:58]
  wire  out_frontSel_14 = _out_frontSel_T[14]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_13 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_14 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_13 = out_wivalid_13 & out_wimask; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_14 = &out_frontMask[3:0]; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_20 = _out_frontSel_T[20]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_14 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_20 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_14 = out_wivalid_14 & out_wimask_14; // @[RegisterRouter.scala 83:24]
  wire  _out_T_210 = fifo_io_ip_txwm; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_16 = &out_frontMask[1]; // @[RegisterRouter.scala 83:24]
  wire [1:0] out_prepend_8 = {fifo_io_ip_rxwm,_out_T_210}; // @[Cat.scala 31:58]
  wire  out_frontSel_1 = _out_frontSel_T[1]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_17 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_1 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_17 = out_wivalid_17 & out_wimask_1; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_18 = out_wivalid_17 & out_wimask_16; // @[RegisterRouter.scala 83:24]
  wire [1:0] out_prepend_9 = {ctrl_sck_pol,ctrl_sck_pha}; // @[Cat.scala 31:58]
  wire  out_wimask_19 = &out_frontMask[1:0]; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_6 = _out_frontSel_T[6]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_19 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_6 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_19 = out_wivalid_19 & out_wimask_19; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_28 = _out_frontSel_T[28]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_20 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_28 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_20 = out_wivalid_20 & out_wimask_1; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_21 = out_wivalid_20 & out_wimask_16; // @[RegisterRouter.scala 83:24]
  wire [1:0] out_prepend_10 = {ie_rxwm,ie_txwm}; // @[Cat.scala 31:58]
  wire  out_frontSel_21 = _out_frontSel_T[21]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_22 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_21 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_22 = out_wivalid_22 & out_wimask_14; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_18 = _out_frontSel_T[18]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_23 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_18 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_23 = out_wivalid_23 & out_wimask_2; // @[RegisterRouter.scala 83:24]
  wire  out_womask_25 = &out_frontMask[31]; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_25 = out_wivalid_23 & out_womask_25; // @[RegisterRouter.scala 83:24]
  wire  quash = out_f_woready_25 & bundleIn_0_1_a_bits_data[31]; // @[RegMapFIFO.scala 27:26]
  wire [31:0] out_prepend_12 = {_T,31'h0}; // @[Cat.scala 31:58]
  wire  out_frontSel_16 = _out_frontSel_T[16]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_26 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_16 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_26 = out_wivalid_26 & out_wimask_19; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_27 = &out_frontMask[2]; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_27 = out_wivalid_26 & out_wimask_27; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_28 = &out_frontMask[3]; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_28 = out_wivalid_26 & out_wimask_28; // @[RegisterRouter.scala 83:24]
  wire [3:0] out_prepend_14 = {ctrl_fmt_iodir,ctrl_fmt_endian,ctrl_fmt_proto}; // @[Cat.scala 31:58]
  wire  out_wimask_29 = &out_frontMask[19:16]; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_29 = out_wivalid_26 & out_wimask_29; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_prepend_T_15 = {{12'd0}, out_prepend_14}; // @[RegisterRouter.scala 83:24]
  wire [19:0] out_prepend_15 = {ctrl_fmt_len,_out_prepend_T_15}; // @[Cat.scala 31:58]
  wire  out_frontSel_11 = _out_frontSel_T[11]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_30 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_11 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_30 = out_wivalid_30 & out_wimask_2; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_31 = out_wivalid_30 & out_wimask_3; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_prepend_T_16 = {{8'd0}, ctrl_dla_intercs}; // @[RegisterRouter.scala 83:24]
  wire [23:0] out_prepend_16 = {ctrl_dla_interxfr,_out_prepend_T_16}; // @[Cat.scala 31:58]
  wire  out_frontSel_26 = _out_frontSel_T[26]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_32 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_26 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_32 = out_wivalid_32 & out_wimask_2; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_33 = &out_frontMask[11:8]; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_33 = out_wivalid_32 & out_wimask_33; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_34 = &out_frontMask[23:12]; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_34 = out_wivalid_32 & out_wimask_34; // @[RegisterRouter.scala 83:24]
  wire [23:0] out_prepend_18 = {insn_max_cen_cyc,insn_pgsz,insn_wcmd_code}; // @[Cat.scala 31:58]
  wire  out_frontSel_19 = _out_frontSel_T[19]; // @[RegisterRouter.scala 83:24]
  wire  out_rivalid_35 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & in_bits_read & out_frontSel_19 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire [7:0] _out_T_420 = fifo_io_rx_bits; // @[RegisterRouter.scala 83:24]
  wire [8:0] out_prepend_19 = {1'h0,_out_T_420}; // @[Cat.scala 31:58]
  wire [30:0] _out_T_429 = {{22'd0}, out_prepend_19}; // @[RegisterRouter.scala 83:24]
  wire [31:0] out_prepend_20 = {_T_1,_out_T_429}; // @[Cat.scala 31:58]
  wire  out_frontSel_4 = _out_frontSel_T[4]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_38 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_4 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_38 = out_wivalid_38 & out_wimask_1; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_39 = &out_frontMask[4:0]; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_15 = _out_frontSel_T[15]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_39 = bundleIn_0_1_a_valid & bundleIn_0_1_d_ready & ~in_bits_read & out_frontSel_15 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_39 = out_wivalid_39 & out_wimask_39; // @[RegisterRouter.scala 83:24]
  wire  _GEN_177 = 5'h1 == out_oindex ? _out_T : _out_T; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_180 = 5'h4 == out_oindex ? _out_T : 5'h3 == out_oindex | (5'h2 == out_oindex | _GEN_177); // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_181 = 5'h5 == out_oindex ? _out_T : _GEN_180; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_182 = 5'h6 == out_oindex ? _out_T : _GEN_181; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_186 = 5'ha == out_oindex ? _out_T : 5'h9 == out_oindex | (5'h8 == out_oindex | (5'h7 == out_oindex |
    _GEN_182)); // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_187 = 5'hb == out_oindex ? _out_T : _GEN_186; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_190 = 5'he == out_oindex ? _out_T : 5'hd == out_oindex | (5'hc == out_oindex | _GEN_187); // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_191 = 5'hf == out_oindex ? _out_T : _GEN_190; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_192 = 5'h10 == out_oindex ? _out_T : _GEN_191; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_194 = 5'h12 == out_oindex ? _out_T : 5'h11 == out_oindex | _GEN_192; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_195 = 5'h13 == out_oindex ? _out_T : _GEN_194; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_196 = 5'h14 == out_oindex ? _out_T : _GEN_195; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_197 = 5'h15 == out_oindex ? _out_T : _GEN_196; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_200 = 5'h18 == out_oindex ? _out_T : 5'h17 == out_oindex | (5'h16 == out_oindex | _GEN_197); // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_201 = 5'h19 == out_oindex ? _out_T : _GEN_200; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_202 = 5'h1a == out_oindex ? _out_T : _GEN_201; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_204 = 5'h1c == out_oindex ? _out_T : 5'h1b == out_oindex | _GEN_202; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_205 = 5'h1d == out_oindex ? _out_T : _GEN_204; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_207 = 5'h1f == out_oindex | (5'h1e == out_oindex | _GEN_205); // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_0 = {{20'd0}, ctrl_sck_div}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _out_out_bits_data_WIRE_1_1 = {{30'd0}, out_prepend_9}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_209 = 5'h1 == out_oindex ? _out_out_bits_data_WIRE_1_1 : _out_out_bits_data_WIRE_1_0; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_210 = 5'h2 == out_oindex ? 32'h0 : _GEN_209; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_211 = 5'h3 == out_oindex ? 32'h0 : _GEN_210; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_4 = {{31'd0}, ctrl_cs_id}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_212 = 5'h4 == out_oindex ? _out_out_bits_data_WIRE_1_4 : _GEN_211; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_5 = {{31'd0}, ctrl_cs_dflt_0}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_213 = 5'h5 == out_oindex ? _out_out_bits_data_WIRE_1_5 : _GEN_212; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_6 = {{30'd0}, ctrl_cs_mode}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_214 = 5'h6 == out_oindex ? _out_out_bits_data_WIRE_1_6 : _GEN_213; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_215 = 5'h7 == out_oindex ? 32'h0 : _GEN_214; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_216 = 5'h8 == out_oindex ? 32'h0 : _GEN_215; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_217 = 5'h9 == out_oindex ? 32'h0 : _GEN_216; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_10 = {{8'd0}, out_prepend}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_218 = 5'ha == out_oindex ? _out_out_bits_data_WIRE_1_10 : _GEN_217; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_11 = {{8'd0}, out_prepend_16}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_219 = 5'hb == out_oindex ? _out_out_bits_data_WIRE_1_11 : _GEN_218; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_220 = 5'hc == out_oindex ? 32'h0 : _GEN_219; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_221 = 5'hd == out_oindex ? 32'h0 : _GEN_220; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_14 = {{20'd0}, ctrl_extradel_coarse}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_222 = 5'he == out_oindex ? _out_out_bits_data_WIRE_1_14 : _GEN_221; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_15 = {{27'd0}, ctrl_sampledel_sd}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_223 = 5'hf == out_oindex ? _out_out_bits_data_WIRE_1_15 : _GEN_222; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_16 = {{12'd0}, out_prepend_15}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_224 = 5'h10 == out_oindex ? _out_out_bits_data_WIRE_1_16 : _GEN_223; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_225 = 5'h11 == out_oindex ? 32'h0 : _GEN_224; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_226 = 5'h12 == out_oindex ? out_prepend_12 : _GEN_225; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_227 = 5'h13 == out_oindex ? out_prepend_20 : _GEN_226; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_20 = {{28'd0}, ctrl_wm_tx}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_228 = 5'h14 == out_oindex ? _out_out_bits_data_WIRE_1_20 : _GEN_227; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_21 = {{28'd0}, ctrl_wm_rx}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_229 = 5'h15 == out_oindex ? _out_out_bits_data_WIRE_1_21 : _GEN_228; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_230 = 5'h16 == out_oindex ? 32'h0 : _GEN_229; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_231 = 5'h17 == out_oindex ? 32'h0 : _GEN_230; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_24 = {{31'd0}, ram_en}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_232 = 5'h18 == out_oindex ? _out_out_bits_data_WIRE_1_24 : _GEN_231; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_233 = 5'h19 == out_oindex ? out_prepend_7 : _GEN_232; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_26 = {{8'd0}, out_prepend_18}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_234 = 5'h1a == out_oindex ? _out_out_bits_data_WIRE_1_26 : _GEN_233; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_235 = 5'h1b == out_oindex ? 32'h0 : _GEN_234; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_28 = {{30'd0}, out_prepend_10}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_236 = 5'h1c == out_oindex ? _out_out_bits_data_WIRE_1_28 : _GEN_235; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_29 = {{30'd0}, out_prepend_8}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_237 = 5'h1d == out_oindex ? _out_out_bits_data_WIRE_1_29 : _GEN_236; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_238 = 5'h1e == out_oindex ? 32'h0 : _GEN_237; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_239 = 5'h1f == out_oindex ? 32'h0 : _GEN_238; // @[MuxLiteral.scala 48:{10,10}]
  TLBuffer_13 buffer ( // @[Buffer.scala 68:28]
    .auto_in_a_ready(buffer_auto_in_a_ready),
    .auto_in_a_valid(buffer_auto_in_a_valid),
    .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
    .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
    .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
    .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
    .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
    .auto_in_a_bits_data(buffer_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
    .auto_in_d_ready(buffer_auto_in_d_ready),
    .auto_in_d_valid(buffer_auto_in_d_valid),
    .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
    .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
    .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
    .auto_out_a_ready(buffer_auto_out_a_ready),
    .auto_out_a_valid(buffer_auto_out_a_valid),
    .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
    .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
    .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
    .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
    .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
    .auto_out_a_bits_data(buffer_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
    .auto_out_d_ready(buffer_auto_out_d_ready),
    .auto_out_d_valid(buffer_auto_out_d_valid),
    .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
    .auto_out_d_bits_source(buffer_auto_out_d_bits_source),
    .auto_out_d_bits_data(buffer_auto_out_d_bits_data)
  );
  TLBuffer_21 buffer_1 ( // @[Buffer.scala 68:28]
    .auto_in_a_ready(buffer_1_auto_in_a_ready),
    .auto_in_a_valid(buffer_1_auto_in_a_valid),
    .auto_in_a_bits_opcode(buffer_1_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(buffer_1_auto_in_a_bits_param),
    .auto_in_a_bits_size(buffer_1_auto_in_a_bits_size),
    .auto_in_a_bits_source(buffer_1_auto_in_a_bits_source),
    .auto_in_a_bits_address(buffer_1_auto_in_a_bits_address),
    .auto_in_a_bits_mask(buffer_1_auto_in_a_bits_mask),
    .auto_in_a_bits_data(buffer_1_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(buffer_1_auto_in_a_bits_corrupt),
    .auto_in_d_ready(buffer_1_auto_in_d_ready),
    .auto_in_d_valid(buffer_1_auto_in_d_valid),
    .auto_in_d_bits_opcode(buffer_1_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(buffer_1_auto_in_d_bits_size),
    .auto_in_d_bits_source(buffer_1_auto_in_d_bits_source),
    .auto_in_d_bits_data(buffer_1_auto_in_d_bits_data),
    .auto_out_a_ready(buffer_1_auto_out_a_ready),
    .auto_out_a_valid(buffer_1_auto_out_a_valid),
    .auto_out_a_bits_opcode(buffer_1_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(buffer_1_auto_out_a_bits_param),
    .auto_out_a_bits_size(buffer_1_auto_out_a_bits_size),
    .auto_out_a_bits_source(buffer_1_auto_out_a_bits_source),
    .auto_out_a_bits_address(buffer_1_auto_out_a_bits_address),
    .auto_out_a_bits_mask(buffer_1_auto_out_a_bits_mask),
    .auto_out_a_bits_data(buffer_1_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(buffer_1_auto_out_a_bits_corrupt),
    .auto_out_d_ready(buffer_1_auto_out_d_ready),
    .auto_out_d_valid(buffer_1_auto_out_d_valid),
    .auto_out_d_bits_opcode(buffer_1_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(buffer_1_auto_out_d_bits_size),
    .auto_out_d_bits_source(buffer_1_auto_out_d_bits_source),
    .auto_out_d_bits_data(buffer_1_auto_out_d_bits_data)
  );
  IntSyncCrossingSource_1 intsource ( // @[Crossing.scala 26:31]
    .clock(intsource_clock),
    .reset(intsource_reset),
    .auto_in_0(intsource_auto_in_0),
    .auto_out_sync_0(intsource_auto_out_sync_0)
  );
  TLMonitor_63 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  TLMonitor_64 monitor_1 ( // @[Nodes.scala 24:25]
    .clock(monitor_1_clock),
    .reset(monitor_1_reset),
    .io_in_a_ready(monitor_1_io_in_a_ready),
    .io_in_a_valid(monitor_1_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_1_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_1_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_1_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_1_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_1_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_1_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_1_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_1_io_in_d_ready),
    .io_in_d_valid(monitor_1_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_1_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_1_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_1_io_in_d_bits_source)
  );
  SPIFIFO fifo ( // @[TLSPI.scala 69:20]
    .clock(fifo_clock),
    .reset(fifo_reset),
    .io_ctrl_fmt_proto(fifo_io_ctrl_fmt_proto),
    .io_ctrl_fmt_endian(fifo_io_ctrl_fmt_endian),
    .io_ctrl_fmt_iodir(fifo_io_ctrl_fmt_iodir),
    .io_ctrl_fmt_len(fifo_io_ctrl_fmt_len),
    .io_ctrl_cs_mode(fifo_io_ctrl_cs_mode),
    .io_ctrl_wm_tx(fifo_io_ctrl_wm_tx),
    .io_ctrl_wm_rx(fifo_io_ctrl_wm_rx),
    .io_link_tx_ready(fifo_io_link_tx_ready),
    .io_link_tx_valid(fifo_io_link_tx_valid),
    .io_link_tx_bits(fifo_io_link_tx_bits),
    .io_link_rx_valid(fifo_io_link_rx_valid),
    .io_link_rx_bits(fifo_io_link_rx_bits),
    .io_link_cnt(fifo_io_link_cnt),
    .io_link_fmt_proto(fifo_io_link_fmt_proto),
    .io_link_fmt_endian(fifo_io_link_fmt_endian),
    .io_link_fmt_iodir(fifo_io_link_fmt_iodir),
    .io_link_cs_set(fifo_io_link_cs_set),
    .io_link_cs_clear(fifo_io_link_cs_clear),
    .io_link_lock(fifo_io_link_lock),
    .io_tx_ready(fifo_io_tx_ready),
    .io_tx_valid(fifo_io_tx_valid),
    .io_tx_bits(fifo_io_tx_bits),
    .io_rx_ready(fifo_io_rx_ready),
    .io_rx_valid(fifo_io_rx_valid),
    .io_rx_bits(fifo_io_rx_bits),
    .io_ip_txwm(fifo_io_ip_txwm),
    .io_ip_rxwm(fifo_io_ip_rxwm)
  );
  SPIMedia mac ( // @[TLSPI.scala 70:19]
    .clock(mac_clock),
    .reset(mac_reset),
    .io_port_sck(mac_io_port_sck),
    .io_port_dq_0_i(mac_io_port_dq_0_i),
    .io_port_dq_0_o(mac_io_port_dq_0_o),
    .io_port_dq_0_oe(mac_io_port_dq_0_oe),
    .io_port_dq_1_i(mac_io_port_dq_1_i),
    .io_port_dq_1_o(mac_io_port_dq_1_o),
    .io_port_dq_1_oe(mac_io_port_dq_1_oe),
    .io_port_dq_2_i(mac_io_port_dq_2_i),
    .io_port_dq_2_o(mac_io_port_dq_2_o),
    .io_port_dq_2_oe(mac_io_port_dq_2_oe),
    .io_port_dq_3_i(mac_io_port_dq_3_i),
    .io_port_dq_3_o(mac_io_port_dq_3_o),
    .io_port_dq_3_oe(mac_io_port_dq_3_oe),
    .io_port_cs_0(mac_io_port_cs_0),
    .io_ctrl_sck_div(mac_io_ctrl_sck_div),
    .io_ctrl_sck_pol(mac_io_ctrl_sck_pol),
    .io_ctrl_sck_pha(mac_io_ctrl_sck_pha),
    .io_ctrl_dla_cssck(mac_io_ctrl_dla_cssck),
    .io_ctrl_dla_sckcs(mac_io_ctrl_dla_sckcs),
    .io_ctrl_dla_intercs(mac_io_ctrl_dla_intercs),
    .io_ctrl_dla_interxfr(mac_io_ctrl_dla_interxfr),
    .io_ctrl_cs_id(mac_io_ctrl_cs_id),
    .io_ctrl_cs_dflt_0(mac_io_ctrl_cs_dflt_0),
    .io_ctrl_extradel_coarse(mac_io_ctrl_extradel_coarse),
    .io_ctrl_sampledel_sd(mac_io_ctrl_sampledel_sd),
    .io_link_tx_ready(mac_io_link_tx_ready),
    .io_link_tx_valid(mac_io_link_tx_valid),
    .io_link_tx_bits(mac_io_link_tx_bits),
    .io_link_rx_valid(mac_io_link_rx_valid),
    .io_link_rx_bits(mac_io_link_rx_bits),
    .io_link_cnt(mac_io_link_cnt),
    .io_link_fmt_proto(mac_io_link_fmt_proto),
    .io_link_fmt_endian(mac_io_link_fmt_endian),
    .io_link_fmt_iodir(mac_io_link_fmt_iodir),
    .io_link_cs_set(mac_io_link_cs_set),
    .io_link_cs_clear(mac_io_link_cs_clear),
    .io_link_cs_hold(mac_io_link_cs_hold),
    .io_link_active(mac_io_link_active)
  );
  SPIRAMMap ram ( // @[TLSPIRAM.scala 58:19]
    .clock(ram_clock),
    .reset(ram_reset),
    .io_en(ram_io_en),
    .io_ctrl_insn_cmd_proto(ram_io_ctrl_insn_cmd_proto),
    .io_ctrl_insn_cmd_code(ram_io_ctrl_insn_cmd_code),
    .io_ctrl_insn_cmd_en(ram_io_ctrl_insn_cmd_en),
    .io_ctrl_insn_wcmd_code(ram_io_ctrl_insn_wcmd_code),
    .io_ctrl_insn_addr_proto(ram_io_ctrl_insn_addr_proto),
    .io_ctrl_insn_addr_len(ram_io_ctrl_insn_addr_len),
    .io_ctrl_insn_pad_code(ram_io_ctrl_insn_pad_code),
    .io_ctrl_insn_pad_cnt(ram_io_ctrl_insn_pad_cnt),
    .io_ctrl_insn_data_proto(ram_io_ctrl_insn_data_proto),
    .io_ctrl_insn_pgsz(ram_io_ctrl_insn_pgsz),
    .io_ctrl_insn_max_cen_cyc(ram_io_ctrl_insn_max_cen_cyc),
    .io_ctrl_fmt_endian(ram_io_ctrl_fmt_endian),
    .io_addr_ready(ram_io_addr_ready),
    .io_addr_valid(ram_io_addr_valid),
    .io_addr_bits_next(ram_io_addr_bits_next),
    .io_addr_bits_hold(ram_io_addr_bits_hold),
    .io_opcode_next(ram_io_opcode_next),
    .io_opcode_hold(ram_io_opcode_hold),
    .io_wdata(ram_io_wdata),
    .io_data_ready(ram_io_data_ready),
    .io_data_valid(ram_io_data_valid),
    .io_data_bits(ram_io_data_bits),
    .io_link_tx_ready(ram_io_link_tx_ready),
    .io_link_tx_valid(ram_io_link_tx_valid),
    .io_link_tx_bits(ram_io_link_tx_bits),
    .io_link_rx_valid(ram_io_link_rx_valid),
    .io_link_rx_bits(ram_io_link_rx_bits),
    .io_link_cnt(ram_io_link_cnt),
    .io_link_fmt_proto(ram_io_link_fmt_proto),
    .io_link_fmt_endian(ram_io_link_fmt_endian),
    .io_link_fmt_iodir(ram_io_link_fmt_iodir),
    .io_link_cs_clear(ram_io_link_cs_clear),
    .io_link_active(ram_io_link_active),
    .io_link_lock(ram_io_link_lock)
  );
  SPIArbiter arb ( // @[TLSPIRAM.scala 59:19]
    .clock(arb_clock),
    .reset(arb_reset),
    .io_inner_0_tx_ready(arb_io_inner_0_tx_ready),
    .io_inner_0_tx_valid(arb_io_inner_0_tx_valid),
    .io_inner_0_tx_bits(arb_io_inner_0_tx_bits),
    .io_inner_0_rx_valid(arb_io_inner_0_rx_valid),
    .io_inner_0_rx_bits(arb_io_inner_0_rx_bits),
    .io_inner_0_cnt(arb_io_inner_0_cnt),
    .io_inner_0_fmt_proto(arb_io_inner_0_fmt_proto),
    .io_inner_0_fmt_endian(arb_io_inner_0_fmt_endian),
    .io_inner_0_fmt_iodir(arb_io_inner_0_fmt_iodir),
    .io_inner_0_cs_clear(arb_io_inner_0_cs_clear),
    .io_inner_0_active(arb_io_inner_0_active),
    .io_inner_0_lock(arb_io_inner_0_lock),
    .io_inner_1_tx_ready(arb_io_inner_1_tx_ready),
    .io_inner_1_tx_valid(arb_io_inner_1_tx_valid),
    .io_inner_1_tx_bits(arb_io_inner_1_tx_bits),
    .io_inner_1_rx_valid(arb_io_inner_1_rx_valid),
    .io_inner_1_rx_bits(arb_io_inner_1_rx_bits),
    .io_inner_1_cnt(arb_io_inner_1_cnt),
    .io_inner_1_fmt_proto(arb_io_inner_1_fmt_proto),
    .io_inner_1_fmt_endian(arb_io_inner_1_fmt_endian),
    .io_inner_1_fmt_iodir(arb_io_inner_1_fmt_iodir),
    .io_inner_1_cs_set(arb_io_inner_1_cs_set),
    .io_inner_1_cs_clear(arb_io_inner_1_cs_clear),
    .io_inner_1_lock(arb_io_inner_1_lock),
    .io_outer_tx_ready(arb_io_outer_tx_ready),
    .io_outer_tx_valid(arb_io_outer_tx_valid),
    .io_outer_tx_bits(arb_io_outer_tx_bits),
    .io_outer_rx_valid(arb_io_outer_rx_valid),
    .io_outer_rx_bits(arb_io_outer_rx_bits),
    .io_outer_cnt(arb_io_outer_cnt),
    .io_outer_fmt_proto(arb_io_outer_fmt_proto),
    .io_outer_fmt_endian(arb_io_outer_fmt_endian),
    .io_outer_fmt_iodir(arb_io_outer_fmt_iodir),
    .io_outer_cs_set(arb_io_outer_cs_set),
    .io_outer_cs_clear(arb_io_outer_cs_clear),
    .io_outer_cs_hold(arb_io_outer_cs_hold),
    .io_outer_active(arb_io_outer_active),
    .io_sel(arb_io_sel)
  );
  assign auto_int_xing_out_sync_0 = intsource_auto_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_mem_xing_in_a_ready = buffer_1_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_mem_xing_in_d_valid = buffer_1_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_mem_xing_in_d_bits_opcode = buffer_1_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_mem_xing_in_d_bits_size = buffer_1_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_mem_xing_in_d_bits_source = buffer_1_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_mem_xing_in_d_bits_data = buffer_1_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_a_ready = buffer_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_valid = buffer_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_size = buffer_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_source = buffer_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_data = buffer_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_io_out_sck = mac_io_port_sck; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
  assign auto_io_out_dq_0_o = mac_io_port_dq_0_o; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
  assign auto_io_out_dq_0_oe = mac_io_port_dq_0_oe; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
  assign auto_io_out_dq_1_o = mac_io_port_dq_1_o; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
  assign auto_io_out_dq_1_oe = mac_io_port_dq_1_oe; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
  assign auto_io_out_dq_2_o = mac_io_port_dq_2_o; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
  assign auto_io_out_dq_2_oe = mac_io_port_dq_2_oe; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
  assign auto_io_out_dq_3_o = mac_io_port_dq_3_o; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
  assign auto_io_out_dq_3_oe = mac_io_port_dq_3_oe; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
  assign auto_io_out_cs_0 = mac_io_port_cs_0; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
  assign buffer_auto_in_a_valid = auto_control_xing_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_opcode = auto_control_xing_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_param = auto_control_xing_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_size = auto_control_xing_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_source = auto_control_xing_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_address = auto_control_xing_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_mask = auto_control_xing_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_data = auto_control_xing_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_corrupt = auto_control_xing_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_d_ready = auto_control_xing_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_out_a_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign buffer_auto_out_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_data = _GEN_207 ? _GEN_239 : 32'h0; // @[RegisterRouter.scala 83:24]
  assign buffer_1_auto_in_a_valid = auto_mem_xing_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_in_a_bits_opcode = auto_mem_xing_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_in_a_bits_param = auto_mem_xing_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_in_a_bits_size = auto_mem_xing_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_in_a_bits_source = auto_mem_xing_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_in_a_bits_address = auto_mem_xing_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_in_a_bits_mask = auto_mem_xing_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_in_a_bits_data = auto_mem_xing_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_in_a_bits_corrupt = auto_mem_xing_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_in_d_ready = auto_mem_xing_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_1_auto_out_a_ready = ram_io_addr_ready; // @[Nodes.scala 1210:84 TLSPIRAM.scala 80:13]
  assign buffer_1_auto_out_d_valid = ram_io_data_valid; // @[Nodes.scala 1210:84 TLSPIRAM.scala 87:13]
  assign buffer_1_auto_out_d_bits_opcode = a_opcode == 3'h0 ? 3'h0 : 3'h1; // @[TLSPIRAM.scala 82:46 83:14 85:14]
  assign buffer_1_auto_out_d_bits_size = a_size; // @[TLSPIRAM.scala 82:46 83:14 85:14]
  assign buffer_1_auto_out_d_bits_source = a_source; // @[TLSPIRAM.scala 82:46 83:14 85:14]
  assign buffer_1_auto_out_d_bits_data = a_opcode == 3'h0 ? 8'h0 : bundleIn_0_d_bits_d_1_data; // @[TLSPIRAM.scala 82:46 83:14 85:14]
  assign intsource_clock = clock;
  assign intsource_reset = reset;
  assign intsource_auto_in_0 = fifo_io_ip_txwm & ie_txwm | fifo_io_ip_rxwm & ie_rxwm; // @[TLSPI.scala 84:47]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = ram_io_addr_ready; // @[Nodes.scala 1210:84 TLSPIRAM.scala 80:13]
  assign monitor_io_in_a_valid = buffer_1_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_opcode = buffer_1_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_param = buffer_1_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_size = buffer_1_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_source = buffer_1_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_address = buffer_1_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_mask = buffer_1_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_corrupt = buffer_1_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_ready = buffer_1_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_valid = ram_io_data_valid; // @[Nodes.scala 1210:84 TLSPIRAM.scala 87:13]
  assign monitor_io_in_d_bits_opcode = a_opcode == 3'h0 ? 3'h0 : 3'h1; // @[TLSPIRAM.scala 82:46 83:14 85:14]
  assign monitor_io_in_d_bits_size = a_size; // @[TLSPIRAM.scala 82:46 83:14 85:14]
  assign monitor_io_in_d_bits_source = a_source; // @[TLSPIRAM.scala 82:46 83:14 85:14]
  assign monitor_1_clock = clock;
  assign monitor_1_reset = reset;
  assign monitor_1_io_in_a_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_1_io_in_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_1_io_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_1_io_in_a_bits_param = buffer_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_1_io_in_a_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_1_io_in_a_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_1_io_in_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_1_io_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_1_io_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_1_io_in_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_1_io_in_d_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_1_io_in_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign monitor_1_io_in_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_1_io_in_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign fifo_clock = clock;
  assign fifo_reset = reset;
  assign fifo_io_ctrl_fmt_proto = ctrl_fmt_proto; // @[TLSPI.scala 73:20]
  assign fifo_io_ctrl_fmt_endian = ctrl_fmt_endian; // @[TLSPI.scala 73:20]
  assign fifo_io_ctrl_fmt_iodir = ctrl_fmt_iodir; // @[TLSPI.scala 73:20]
  assign fifo_io_ctrl_fmt_len = ctrl_fmt_len; // @[TLSPI.scala 73:20]
  assign fifo_io_ctrl_cs_mode = ctrl_cs_mode; // @[TLSPI.scala 74:19]
  assign fifo_io_ctrl_wm_tx = ctrl_wm_tx; // @[TLSPI.scala 75:19]
  assign fifo_io_ctrl_wm_rx = ctrl_wm_rx; // @[TLSPI.scala 75:19]
  assign fifo_io_link_tx_ready = arb_io_inner_1_tx_ready; // @[TLSPIRAM.scala 157:21]
  assign fifo_io_link_rx_valid = arb_io_inner_1_rx_valid; // @[TLSPIRAM.scala 157:21]
  assign fifo_io_link_rx_bits = arb_io_inner_1_rx_bits; // @[TLSPIRAM.scala 157:21]
  assign fifo_io_tx_valid = out_f_wivalid_23 & ~quash; // @[RegMapFIFO.scala 19:30]
  assign fifo_io_tx_bits = bundleIn_0_1_a_bits_data[7:0]; // @[RegisterRouter.scala 83:24]
  assign fifo_io_rx_ready = out_rivalid_35 & out_rimask_2; // @[RegisterRouter.scala 83:24]
  assign mac_clock = clock;
  assign mac_reset = reset;
  assign mac_io_port_dq_0_i = auto_io_out_dq_0_i; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign mac_io_port_dq_1_i = auto_io_out_dq_1_i; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign mac_io_port_dq_2_i = auto_io_out_dq_2_i; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign mac_io_port_dq_3_i = auto_io_out_dq_3_i; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign mac_io_ctrl_sck_div = ctrl_sck_div; // @[TLSPI.scala 76:19]
  assign mac_io_ctrl_sck_pol = ctrl_sck_pol; // @[TLSPI.scala 76:19]
  assign mac_io_ctrl_sck_pha = ctrl_sck_pha; // @[TLSPI.scala 76:19]
  assign mac_io_ctrl_dla_cssck = ctrl_dla_cssck; // @[TLSPI.scala 79:19]
  assign mac_io_ctrl_dla_sckcs = ctrl_dla_sckcs; // @[TLSPI.scala 79:19]
  assign mac_io_ctrl_dla_intercs = ctrl_dla_intercs; // @[TLSPI.scala 79:19]
  assign mac_io_ctrl_dla_interxfr = ctrl_dla_interxfr; // @[TLSPI.scala 79:19]
  assign mac_io_ctrl_cs_id = ctrl_cs_id; // @[TLSPI.scala 80:18]
  assign mac_io_ctrl_cs_dflt_0 = ctrl_cs_dflt_0; // @[TLSPI.scala 80:18]
  assign mac_io_ctrl_extradel_coarse = ctrl_extradel_coarse; // @[TLSPI.scala 77:24]
  assign mac_io_ctrl_sampledel_sd = ctrl_sampledel_sd; // @[TLSPI.scala 78:25]
  assign mac_io_link_tx_valid = arb_io_outer_tx_valid; // @[TLSPIRAM.scala 158:17]
  assign mac_io_link_tx_bits = arb_io_outer_tx_bits; // @[TLSPIRAM.scala 158:17]
  assign mac_io_link_cnt = arb_io_outer_cnt; // @[TLSPIRAM.scala 158:17]
  assign mac_io_link_fmt_proto = arb_io_outer_fmt_proto; // @[TLSPIRAM.scala 158:17]
  assign mac_io_link_fmt_endian = arb_io_outer_fmt_endian; // @[TLSPIRAM.scala 158:17]
  assign mac_io_link_fmt_iodir = arb_io_outer_fmt_iodir; // @[TLSPIRAM.scala 158:17]
  assign mac_io_link_cs_set = arb_io_outer_cs_set; // @[TLSPIRAM.scala 158:17]
  assign mac_io_link_cs_clear = arb_io_outer_cs_clear; // @[TLSPIRAM.scala 158:17]
  assign mac_io_link_cs_hold = arb_io_outer_cs_hold; // @[TLSPIRAM.scala 158:17]
  assign ram_clock = clock;
  assign ram_reset = reset;
  assign ram_io_en = ram_en; // @[TLSPIRAM.scala 95:13]
  assign ram_io_ctrl_insn_cmd_proto = insn_cmd_proto; // @[TLSPIRAM.scala 93:20]
  assign ram_io_ctrl_insn_cmd_code = insn_cmd_code; // @[TLSPIRAM.scala 93:20]
  assign ram_io_ctrl_insn_cmd_en = insn_cmd_en; // @[TLSPIRAM.scala 93:20]
  assign ram_io_ctrl_insn_wcmd_code = insn_wcmd_code; // @[TLSPIRAM.scala 93:20]
  assign ram_io_ctrl_insn_addr_proto = insn_addr_proto; // @[TLSPIRAM.scala 93:20]
  assign ram_io_ctrl_insn_addr_len = insn_addr_len; // @[TLSPIRAM.scala 93:20]
  assign ram_io_ctrl_insn_pad_code = insn_pad_code; // @[TLSPIRAM.scala 93:20]
  assign ram_io_ctrl_insn_pad_cnt = insn_pad_cnt; // @[TLSPIRAM.scala 93:20]
  assign ram_io_ctrl_insn_data_proto = insn_data_proto; // @[TLSPIRAM.scala 93:20]
  assign ram_io_ctrl_insn_pgsz = insn_pgsz; // @[TLSPIRAM.scala 93:20]
  assign ram_io_ctrl_insn_max_cen_cyc = insn_max_cen_cyc; // @[TLSPIRAM.scala 93:20]
  assign ram_io_ctrl_fmt_endian = ctrl_fmt_endian; // @[TLSPIRAM.scala 94:19]
  assign ram_io_addr_valid = buffer_1_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign ram_io_addr_bits_next = {{3'd0}, bundleIn_0_a_bits_address[28:0]}; // @[TLSPIRAM.scala 74:25]
  assign ram_io_addr_bits_hold = {{3'd0}, a_address[28:0]}; // @[TLSPIRAM.scala 75:25]
  assign ram_io_opcode_next = buffer_1_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign ram_io_opcode_hold = a_opcode; // @[TLSPIRAM.scala 77:22]
  assign ram_io_wdata = a_data; // @[TLSPIRAM.scala 78:16]
  assign ram_io_data_ready = buffer_1_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign ram_io_link_tx_ready = arb_io_inner_0_tx_ready; // @[TLSPIRAM.scala 156:21]
  assign ram_io_link_rx_valid = arb_io_inner_0_rx_valid; // @[TLSPIRAM.scala 156:21]
  assign ram_io_link_rx_bits = arb_io_inner_0_rx_bits; // @[TLSPIRAM.scala 156:21]
  assign ram_io_link_active = arb_io_inner_0_active; // @[TLSPIRAM.scala 156:21]
  assign arb_clock = clock;
  assign arb_reset = reset;
  assign arb_io_inner_0_tx_valid = ram_io_link_tx_valid; // @[TLSPIRAM.scala 156:21]
  assign arb_io_inner_0_tx_bits = ram_io_link_tx_bits; // @[TLSPIRAM.scala 156:21]
  assign arb_io_inner_0_cnt = ram_io_link_cnt; // @[TLSPIRAM.scala 156:21]
  assign arb_io_inner_0_fmt_proto = ram_io_link_fmt_proto; // @[TLSPIRAM.scala 156:21]
  assign arb_io_inner_0_fmt_endian = ram_io_link_fmt_endian; // @[TLSPIRAM.scala 156:21]
  assign arb_io_inner_0_fmt_iodir = ram_io_link_fmt_iodir; // @[TLSPIRAM.scala 156:21]
  assign arb_io_inner_0_cs_clear = ram_io_link_cs_clear; // @[TLSPIRAM.scala 156:21]
  assign arb_io_inner_0_lock = ram_io_link_lock; // @[TLSPIRAM.scala 156:21]
  assign arb_io_inner_1_tx_valid = fifo_io_link_tx_valid; // @[TLSPIRAM.scala 157:21]
  assign arb_io_inner_1_tx_bits = fifo_io_link_tx_bits; // @[TLSPIRAM.scala 157:21]
  assign arb_io_inner_1_cnt = fifo_io_link_cnt; // @[TLSPIRAM.scala 157:21]
  assign arb_io_inner_1_fmt_proto = fifo_io_link_fmt_proto; // @[TLSPIRAM.scala 157:21]
  assign arb_io_inner_1_fmt_endian = fifo_io_link_fmt_endian; // @[TLSPIRAM.scala 157:21]
  assign arb_io_inner_1_fmt_iodir = fifo_io_link_fmt_iodir; // @[TLSPIRAM.scala 157:21]
  assign arb_io_inner_1_cs_set = fifo_io_link_cs_set; // @[TLSPIRAM.scala 157:21]
  assign arb_io_inner_1_cs_clear = fifo_io_link_cs_clear; // @[TLSPIRAM.scala 157:21]
  assign arb_io_inner_1_lock = fifo_io_link_lock; // @[TLSPIRAM.scala 157:21]
  assign arb_io_outer_tx_ready = mac_io_link_tx_ready; // @[TLSPIRAM.scala 158:17]
  assign arb_io_outer_rx_valid = mac_io_link_rx_valid; // @[TLSPIRAM.scala 158:17]
  assign arb_io_outer_rx_bits = mac_io_link_rx_bits; // @[TLSPIRAM.scala 158:17]
  assign arb_io_outer_active = mac_io_link_active; // @[TLSPIRAM.scala 158:17]
  assign arb_io_sel = ~ram_en; // @[TLSPIRAM.scala 96:17]
  always @(posedge clock) begin
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_fmt_proto <= 2'h0; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_26) begin // @[RegField.scala 74:88]
      ctrl_fmt_proto <= bundleIn_0_1_a_bits_data[1:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_fmt_endian <= 1'h0; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_27) begin // @[RegField.scala 74:88]
      ctrl_fmt_endian <= bundleIn_0_1_a_bits_data[2]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_fmt_iodir <= 1'h0; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_28) begin // @[RegField.scala 74:88]
      ctrl_fmt_iodir <= bundleIn_0_1_a_bits_data[3]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_fmt_len <= 4'h8; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_29) begin // @[RegField.scala 74:88]
      ctrl_fmt_len <= bundleIn_0_1_a_bits_data[19:16]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_sck_div <= 12'h3; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid) begin // @[RegField.scala 74:88]
      ctrl_sck_div <= bundleIn_0_1_a_bits_data[11:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_sck_pol <= 1'h0; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_18) begin // @[RegField.scala 74:88]
      ctrl_sck_pol <= bundleIn_0_1_a_bits_data[1]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_sck_pha <= 1'h0; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_17) begin // @[RegField.scala 74:88]
      ctrl_sck_pha <= bundleIn_0_1_a_bits_data[0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_cs_id <= 1'h0; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_38) begin // @[RegField.scala 74:88]
      ctrl_cs_id <= bundleIn_0_1_a_bits_data[0]; // @[RegField.scala 74:92]
    end
    ctrl_cs_dflt_0 <= reset | _GEN_17; // @[TLSPI.scala 68:{17,17}]
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_cs_mode <= 2'h0; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_19) begin // @[RegField.scala 74:88]
      ctrl_cs_mode <= bundleIn_0_1_a_bits_data[1:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_dla_cssck <= 8'h1; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_2) begin // @[RegField.scala 74:88]
      ctrl_dla_cssck <= bundleIn_0_1_a_bits_data[7:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_dla_sckcs <= 8'h1; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_3) begin // @[RegField.scala 74:88]
      ctrl_dla_sckcs <= bundleIn_0_1_a_bits_data[23:16]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_dla_intercs <= 8'h1; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_30) begin // @[RegField.scala 74:88]
      ctrl_dla_intercs <= bundleIn_0_1_a_bits_data[7:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_dla_interxfr <= 8'h0; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_31) begin // @[RegField.scala 74:88]
      ctrl_dla_interxfr <= bundleIn_0_1_a_bits_data[23:16]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_wm_tx <= 4'h0; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_14) begin // @[RegField.scala 74:88]
      ctrl_wm_tx <= bundleIn_0_1_a_bits_data[3:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_wm_rx <= 4'h0; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_22) begin // @[RegField.scala 74:88]
      ctrl_wm_rx <= bundleIn_0_1_a_bits_data[3:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_extradel_coarse <= 12'h0; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_13) begin // @[RegField.scala 74:88]
      ctrl_extradel_coarse <= bundleIn_0_1_a_bits_data[11:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_sampledel_sd <= 5'h3; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_39) begin // @[RegField.scala 74:88]
      ctrl_sampledel_sd <= bundleIn_0_1_a_bits_data[4:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 82:15]
      ie_txwm <= 1'h0; // @[TLSPI.scala 82:15]
    end else if (out_f_wivalid_20) begin // @[RegField.scala 74:88]
      ie_txwm <= bundleIn_0_1_a_bits_data[0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 82:15]
      ie_rxwm <= 1'h0; // @[TLSPI.scala 82:15]
    end else if (out_f_wivalid_21) begin // @[RegField.scala 74:88]
      ie_rxwm <= bundleIn_0_1_a_bits_data[1]; // @[RegField.scala 74:92]
    end
    if (_T_2) begin // @[TLSPIRAM.scala 70:19]
      a_opcode <= bundleIn_0_a_bits_opcode; // @[TLSPIRAM.scala 71:7]
    end
    if (_T_2) begin // @[TLSPIRAM.scala 70:19]
      a_size <= bundleIn_0_a_bits_size; // @[TLSPIRAM.scala 71:7]
    end
    if (_T_2) begin // @[TLSPIRAM.scala 70:19]
      a_source <= bundleIn_0_a_bits_source; // @[TLSPIRAM.scala 71:7]
    end
    if (_T_2) begin // @[TLSPIRAM.scala 70:19]
      a_address <= bundleIn_0_a_bits_address; // @[TLSPIRAM.scala 71:7]
    end
    if (_T_2) begin // @[TLSPIRAM.scala 70:19]
      a_data <= bundleIn_0_a_bits_data; // @[TLSPIRAM.scala 71:7]
    end
    if (reset) begin // @[TLSPIRAM.scala 90:17]
      insn_cmd_proto <= 2'h0; // @[TLSPIRAM.scala 90:17]
    end else if (out_f_wivalid_8) begin // @[RegField.scala 74:88]
      insn_cmd_proto <= bundleIn_0_1_a_bits_data[9:8]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPIRAM.scala 90:17]
      insn_cmd_code <= 8'h3; // @[TLSPIRAM.scala 90:17]
    end else if (out_f_wivalid_11) begin // @[RegField.scala 74:88]
      insn_cmd_code <= bundleIn_0_1_a_bits_data[23:16]; // @[RegField.scala 74:92]
    end
    insn_cmd_en <= reset | _GEN_21; // @[TLSPIRAM.scala 90:{17,17}]
    if (reset) begin // @[TLSPIRAM.scala 90:17]
      insn_wcmd_code <= 8'h2; // @[TLSPIRAM.scala 90:17]
    end else if (out_f_wivalid_32) begin // @[RegField.scala 74:88]
      insn_wcmd_code <= bundleIn_0_1_a_bits_data[7:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPIRAM.scala 90:17]
      insn_addr_proto <= 2'h0; // @[TLSPIRAM.scala 90:17]
    end else if (out_f_wivalid_9) begin // @[RegField.scala 74:88]
      insn_addr_proto <= bundleIn_0_1_a_bits_data[11:10]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPIRAM.scala 90:17]
      insn_addr_len <= 3'h3; // @[TLSPIRAM.scala 90:17]
    end else if (out_f_wivalid_6) begin // @[RegField.scala 74:88]
      insn_addr_len <= bundleIn_0_1_a_bits_data[3:1]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPIRAM.scala 90:17]
      insn_pad_code <= 8'h0; // @[TLSPIRAM.scala 90:17]
    end else if (out_f_wivalid_12) begin // @[RegField.scala 74:88]
      insn_pad_code <= bundleIn_0_1_a_bits_data[31:24]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPIRAM.scala 90:17]
      insn_pad_cnt <= 4'h0; // @[TLSPIRAM.scala 90:17]
    end else if (out_f_wivalid_7) begin // @[RegField.scala 74:88]
      insn_pad_cnt <= bundleIn_0_1_a_bits_data[7:4]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPIRAM.scala 90:17]
      insn_data_proto <= 2'h0; // @[TLSPIRAM.scala 90:17]
    end else if (out_f_wivalid_10) begin // @[RegField.scala 74:88]
      insn_data_proto <= bundleIn_0_1_a_bits_data[13:12]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPIRAM.scala 90:17]
      insn_pgsz <= 4'h9; // @[TLSPIRAM.scala 90:17]
    end else if (out_f_wivalid_33) begin // @[RegField.scala 74:88]
      insn_pgsz <= bundleIn_0_1_a_bits_data[11:8]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPIRAM.scala 90:17]
      insn_max_cen_cyc <= 12'h80; // @[TLSPIRAM.scala 90:17]
    end else if (out_f_wivalid_34) begin // @[RegField.scala 74:88]
      insn_max_cen_cyc <= bundleIn_0_1_a_bits_data[23:12]; // @[RegField.scala 74:92]
    end
    ram_en <= reset | _GEN_20; // @[TLSPIRAM.scala 91:{19,19}]
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  ctrl_fmt_proto = _RAND_0[1:0];
  _RAND_1 = {1{`RANDOM}};
  ctrl_fmt_endian = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  ctrl_fmt_iodir = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  ctrl_fmt_len = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  ctrl_sck_div = _RAND_4[11:0];
  _RAND_5 = {1{`RANDOM}};
  ctrl_sck_pol = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  ctrl_sck_pha = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  ctrl_cs_id = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  ctrl_cs_dflt_0 = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  ctrl_cs_mode = _RAND_9[1:0];
  _RAND_10 = {1{`RANDOM}};
  ctrl_dla_cssck = _RAND_10[7:0];
  _RAND_11 = {1{`RANDOM}};
  ctrl_dla_sckcs = _RAND_11[7:0];
  _RAND_12 = {1{`RANDOM}};
  ctrl_dla_intercs = _RAND_12[7:0];
  _RAND_13 = {1{`RANDOM}};
  ctrl_dla_interxfr = _RAND_13[7:0];
  _RAND_14 = {1{`RANDOM}};
  ctrl_wm_tx = _RAND_14[3:0];
  _RAND_15 = {1{`RANDOM}};
  ctrl_wm_rx = _RAND_15[3:0];
  _RAND_16 = {1{`RANDOM}};
  ctrl_extradel_coarse = _RAND_16[11:0];
  _RAND_17 = {1{`RANDOM}};
  ctrl_sampledel_sd = _RAND_17[4:0];
  _RAND_18 = {1{`RANDOM}};
  ie_txwm = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  ie_rxwm = _RAND_19[0:0];
  _RAND_20 = {1{`RANDOM}};
  a_opcode = _RAND_20[2:0];
  _RAND_21 = {1{`RANDOM}};
  a_size = _RAND_21[0:0];
  _RAND_22 = {1{`RANDOM}};
  a_source = _RAND_22[10:0];
  _RAND_23 = {1{`RANDOM}};
  a_address = _RAND_23[30:0];
  _RAND_24 = {1{`RANDOM}};
  a_data = _RAND_24[7:0];
  _RAND_25 = {1{`RANDOM}};
  insn_cmd_proto = _RAND_25[1:0];
  _RAND_26 = {1{`RANDOM}};
  insn_cmd_code = _RAND_26[7:0];
  _RAND_27 = {1{`RANDOM}};
  insn_cmd_en = _RAND_27[0:0];
  _RAND_28 = {1{`RANDOM}};
  insn_wcmd_code = _RAND_28[7:0];
  _RAND_29 = {1{`RANDOM}};
  insn_addr_proto = _RAND_29[1:0];
  _RAND_30 = {1{`RANDOM}};
  insn_addr_len = _RAND_30[2:0];
  _RAND_31 = {1{`RANDOM}};
  insn_pad_code = _RAND_31[7:0];
  _RAND_32 = {1{`RANDOM}};
  insn_pad_cnt = _RAND_32[3:0];
  _RAND_33 = {1{`RANDOM}};
  insn_data_proto = _RAND_33[1:0];
  _RAND_34 = {1{`RANDOM}};
  insn_pgsz = _RAND_34[3:0];
  _RAND_35 = {1{`RANDOM}};
  insn_max_cen_cyc = _RAND_35[11:0];
  _RAND_36 = {1{`RANDOM}};
  ram_en = _RAND_36[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ClockSinkDomain_7(
  output        auto_qspi_ram_0_int_xing_out_sync_0,
  output        auto_qspi_ram_0_mem_xing_in_a_ready,
  input         auto_qspi_ram_0_mem_xing_in_a_valid,
  input  [2:0]  auto_qspi_ram_0_mem_xing_in_a_bits_opcode,
  input  [2:0]  auto_qspi_ram_0_mem_xing_in_a_bits_param,
  input         auto_qspi_ram_0_mem_xing_in_a_bits_size,
  input  [10:0] auto_qspi_ram_0_mem_xing_in_a_bits_source,
  input  [30:0] auto_qspi_ram_0_mem_xing_in_a_bits_address,
  input         auto_qspi_ram_0_mem_xing_in_a_bits_mask,
  input  [7:0]  auto_qspi_ram_0_mem_xing_in_a_bits_data,
  input         auto_qspi_ram_0_mem_xing_in_a_bits_corrupt,
  input         auto_qspi_ram_0_mem_xing_in_d_ready,
  output        auto_qspi_ram_0_mem_xing_in_d_valid,
  output [2:0]  auto_qspi_ram_0_mem_xing_in_d_bits_opcode,
  output        auto_qspi_ram_0_mem_xing_in_d_bits_size,
  output [10:0] auto_qspi_ram_0_mem_xing_in_d_bits_source,
  output [7:0]  auto_qspi_ram_0_mem_xing_in_d_bits_data,
  output        auto_qspi_ram_0_control_xing_in_a_ready,
  input         auto_qspi_ram_0_control_xing_in_a_valid,
  input  [2:0]  auto_qspi_ram_0_control_xing_in_a_bits_opcode,
  input  [2:0]  auto_qspi_ram_0_control_xing_in_a_bits_param,
  input  [1:0]  auto_qspi_ram_0_control_xing_in_a_bits_size,
  input  [6:0]  auto_qspi_ram_0_control_xing_in_a_bits_source,
  input  [28:0] auto_qspi_ram_0_control_xing_in_a_bits_address,
  input  [3:0]  auto_qspi_ram_0_control_xing_in_a_bits_mask,
  input  [31:0] auto_qspi_ram_0_control_xing_in_a_bits_data,
  input         auto_qspi_ram_0_control_xing_in_a_bits_corrupt,
  input         auto_qspi_ram_0_control_xing_in_d_ready,
  output        auto_qspi_ram_0_control_xing_in_d_valid,
  output [2:0]  auto_qspi_ram_0_control_xing_in_d_bits_opcode,
  output [1:0]  auto_qspi_ram_0_control_xing_in_d_bits_size,
  output [6:0]  auto_qspi_ram_0_control_xing_in_d_bits_source,
  output [31:0] auto_qspi_ram_0_control_xing_in_d_bits_data,
  output        auto_qspi_ram_0_io_out_sck,
  input         auto_qspi_ram_0_io_out_dq_0_i,
  output        auto_qspi_ram_0_io_out_dq_0_o,
  output        auto_qspi_ram_0_io_out_dq_0_oe,
  input         auto_qspi_ram_0_io_out_dq_1_i,
  output        auto_qspi_ram_0_io_out_dq_1_o,
  output        auto_qspi_ram_0_io_out_dq_1_oe,
  input         auto_qspi_ram_0_io_out_dq_2_i,
  output        auto_qspi_ram_0_io_out_dq_2_o,
  output        auto_qspi_ram_0_io_out_dq_2_oe,
  input         auto_qspi_ram_0_io_out_dq_3_i,
  output        auto_qspi_ram_0_io_out_dq_3_o,
  output        auto_qspi_ram_0_io_out_dq_3_oe,
  output        auto_qspi_ram_0_io_out_cs_0,
  input         auto_clock_in_clock,
  input         auto_clock_in_reset
);
  wire  qspi_ram_0_clock; // @[SPI.scala 40:51]
  wire  qspi_ram_0_reset; // @[SPI.scala 40:51]
  wire  qspi_ram_0_auto_int_xing_out_sync_0; // @[SPI.scala 40:51]
  wire  qspi_ram_0_auto_mem_xing_in_a_ready; // @[SPI.scala 40:51]
  wire  qspi_ram_0_auto_mem_xing_in_a_valid; // @[SPI.scala 40:51]
  wire [2:0] qspi_ram_0_auto_mem_xing_in_a_bits_opcode; // @[SPI.scala 40:51]
  wire [2:0] qspi_ram_0_auto_mem_xing_in_a_bits_param; // @[SPI.scala 40:51]
  wire  qspi_ram_0_auto_mem_xing_in_a_bits_size; // @[SPI.scala 40:51]
  wire [10:0] qspi_ram_0_auto_mem_xing_in_a_bits_source; // @[SPI.scala 40:51]
  wire [30:0] qspi_ram_0_auto_mem_xing_in_a_bits_address; // @[SPI.scala 40:51]
  wire  qspi_ram_0_auto_mem_xing_in_a_bits_mask; // @[SPI.scala 40:51]
  wire [7:0] qspi_ram_0_auto_mem_xing_in_a_bits_data; // @[SPI.scala 40:51]
  wire  qspi_ram_0_auto_mem_xing_in_a_bits_corrupt; // @[SPI.scala 40:51]
  wire  qspi_ram_0_auto_mem_xing_in_d_ready; // @[SPI.scala 40:51]
  wire  qspi_ram_0_auto_mem_xing_in_d_valid; // @[SPI.scala 40:51]
  wire [2:0] qspi_ram_0_auto_mem_xing_in_d_bits_opcode; // @[SPI.scala 40:51]
  wire  qspi_ram_0_auto_mem_xing_in_d_bits_size; // @[SPI.scala 40:51]
  wire [10:0] qspi_ram_0_auto_mem_xing_in_d_bits_source; // @[SPI.scala 40:51]
  wire [7:0] qspi_ram_0_auto_mem_xing_in_d_bits_data; // @[SPI.scala 40:51]
  wire  qspi_ram_0_auto_control_xing_in_a_ready; // @[SPI.scala 40:51]
  wire  qspi_ram_0_auto_control_xing_in_a_valid; // @[SPI.scala 40:51]
  wire [2:0] qspi_ram_0_auto_control_xing_in_a_bits_opcode; // @[SPI.scala 40:51]
  wire [2:0] qspi_ram_0_auto_control_xing_in_a_bits_param; // @[SPI.scala 40:51]
  wire [1:0] qspi_ram_0_auto_control_xing_in_a_bits_size; // @[SPI.scala 40:51]
  wire [6:0] qspi_ram_0_auto_control_xing_in_a_bits_source; // @[SPI.scala 40:51]
  wire [28:0] qspi_ram_0_auto_control_xing_in_a_bits_address; // @[SPI.scala 40:51]
  wire [3:0] qspi_ram_0_auto_control_xing_in_a_bits_mask; // @[SPI.scala 40:51]
  wire [31:0] qspi_ram_0_auto_control_xing_in_a_bits_data; // @[SPI.scala 40:51]
  wire  qspi_ram_0_auto_control_xing_in_a_bits_corrupt; // @[SPI.scala 40:51]
  wire  qspi_ram_0_auto_control_xing_in_d_ready; // @[SPI.scala 40:51]
  wire  qspi_ram_0_auto_control_xing_in_d_valid; // @[SPI.scala 40:51]
  wire [2:0] qspi_ram_0_auto_control_xing_in_d_bits_opcode; // @[SPI.scala 40:51]
  wire [1:0] qspi_ram_0_auto_control_xing_in_d_bits_size; // @[SPI.scala 40:51]
  wire [6:0] qspi_ram_0_auto_control_xing_in_d_bits_source; // @[SPI.scala 40:51]
  wire [31:0] qspi_ram_0_auto_control_xing_in_d_bits_data; // @[SPI.scala 40:51]
  wire  qspi_ram_0_auto_io_out_sck; // @[SPI.scala 40:51]
  wire  qspi_ram_0_auto_io_out_dq_0_i; // @[SPI.scala 40:51]
  wire  qspi_ram_0_auto_io_out_dq_0_o; // @[SPI.scala 40:51]
  wire  qspi_ram_0_auto_io_out_dq_0_oe; // @[SPI.scala 40:51]
  wire  qspi_ram_0_auto_io_out_dq_1_i; // @[SPI.scala 40:51]
  wire  qspi_ram_0_auto_io_out_dq_1_o; // @[SPI.scala 40:51]
  wire  qspi_ram_0_auto_io_out_dq_1_oe; // @[SPI.scala 40:51]
  wire  qspi_ram_0_auto_io_out_dq_2_i; // @[SPI.scala 40:51]
  wire  qspi_ram_0_auto_io_out_dq_2_o; // @[SPI.scala 40:51]
  wire  qspi_ram_0_auto_io_out_dq_2_oe; // @[SPI.scala 40:51]
  wire  qspi_ram_0_auto_io_out_dq_3_i; // @[SPI.scala 40:51]
  wire  qspi_ram_0_auto_io_out_dq_3_o; // @[SPI.scala 40:51]
  wire  qspi_ram_0_auto_io_out_dq_3_oe; // @[SPI.scala 40:51]
  wire  qspi_ram_0_auto_io_out_cs_0; // @[SPI.scala 40:51]
  TLSPIRAM qspi_ram_0 ( // @[SPI.scala 40:51]
    .clock(qspi_ram_0_clock),
    .reset(qspi_ram_0_reset),
    .auto_int_xing_out_sync_0(qspi_ram_0_auto_int_xing_out_sync_0),
    .auto_mem_xing_in_a_ready(qspi_ram_0_auto_mem_xing_in_a_ready),
    .auto_mem_xing_in_a_valid(qspi_ram_0_auto_mem_xing_in_a_valid),
    .auto_mem_xing_in_a_bits_opcode(qspi_ram_0_auto_mem_xing_in_a_bits_opcode),
    .auto_mem_xing_in_a_bits_param(qspi_ram_0_auto_mem_xing_in_a_bits_param),
    .auto_mem_xing_in_a_bits_size(qspi_ram_0_auto_mem_xing_in_a_bits_size),
    .auto_mem_xing_in_a_bits_source(qspi_ram_0_auto_mem_xing_in_a_bits_source),
    .auto_mem_xing_in_a_bits_address(qspi_ram_0_auto_mem_xing_in_a_bits_address),
    .auto_mem_xing_in_a_bits_mask(qspi_ram_0_auto_mem_xing_in_a_bits_mask),
    .auto_mem_xing_in_a_bits_data(qspi_ram_0_auto_mem_xing_in_a_bits_data),
    .auto_mem_xing_in_a_bits_corrupt(qspi_ram_0_auto_mem_xing_in_a_bits_corrupt),
    .auto_mem_xing_in_d_ready(qspi_ram_0_auto_mem_xing_in_d_ready),
    .auto_mem_xing_in_d_valid(qspi_ram_0_auto_mem_xing_in_d_valid),
    .auto_mem_xing_in_d_bits_opcode(qspi_ram_0_auto_mem_xing_in_d_bits_opcode),
    .auto_mem_xing_in_d_bits_size(qspi_ram_0_auto_mem_xing_in_d_bits_size),
    .auto_mem_xing_in_d_bits_source(qspi_ram_0_auto_mem_xing_in_d_bits_source),
    .auto_mem_xing_in_d_bits_data(qspi_ram_0_auto_mem_xing_in_d_bits_data),
    .auto_control_xing_in_a_ready(qspi_ram_0_auto_control_xing_in_a_ready),
    .auto_control_xing_in_a_valid(qspi_ram_0_auto_control_xing_in_a_valid),
    .auto_control_xing_in_a_bits_opcode(qspi_ram_0_auto_control_xing_in_a_bits_opcode),
    .auto_control_xing_in_a_bits_param(qspi_ram_0_auto_control_xing_in_a_bits_param),
    .auto_control_xing_in_a_bits_size(qspi_ram_0_auto_control_xing_in_a_bits_size),
    .auto_control_xing_in_a_bits_source(qspi_ram_0_auto_control_xing_in_a_bits_source),
    .auto_control_xing_in_a_bits_address(qspi_ram_0_auto_control_xing_in_a_bits_address),
    .auto_control_xing_in_a_bits_mask(qspi_ram_0_auto_control_xing_in_a_bits_mask),
    .auto_control_xing_in_a_bits_data(qspi_ram_0_auto_control_xing_in_a_bits_data),
    .auto_control_xing_in_a_bits_corrupt(qspi_ram_0_auto_control_xing_in_a_bits_corrupt),
    .auto_control_xing_in_d_ready(qspi_ram_0_auto_control_xing_in_d_ready),
    .auto_control_xing_in_d_valid(qspi_ram_0_auto_control_xing_in_d_valid),
    .auto_control_xing_in_d_bits_opcode(qspi_ram_0_auto_control_xing_in_d_bits_opcode),
    .auto_control_xing_in_d_bits_size(qspi_ram_0_auto_control_xing_in_d_bits_size),
    .auto_control_xing_in_d_bits_source(qspi_ram_0_auto_control_xing_in_d_bits_source),
    .auto_control_xing_in_d_bits_data(qspi_ram_0_auto_control_xing_in_d_bits_data),
    .auto_io_out_sck(qspi_ram_0_auto_io_out_sck),
    .auto_io_out_dq_0_i(qspi_ram_0_auto_io_out_dq_0_i),
    .auto_io_out_dq_0_o(qspi_ram_0_auto_io_out_dq_0_o),
    .auto_io_out_dq_0_oe(qspi_ram_0_auto_io_out_dq_0_oe),
    .auto_io_out_dq_1_i(qspi_ram_0_auto_io_out_dq_1_i),
    .auto_io_out_dq_1_o(qspi_ram_0_auto_io_out_dq_1_o),
    .auto_io_out_dq_1_oe(qspi_ram_0_auto_io_out_dq_1_oe),
    .auto_io_out_dq_2_i(qspi_ram_0_auto_io_out_dq_2_i),
    .auto_io_out_dq_2_o(qspi_ram_0_auto_io_out_dq_2_o),
    .auto_io_out_dq_2_oe(qspi_ram_0_auto_io_out_dq_2_oe),
    .auto_io_out_dq_3_i(qspi_ram_0_auto_io_out_dq_3_i),
    .auto_io_out_dq_3_o(qspi_ram_0_auto_io_out_dq_3_o),
    .auto_io_out_dq_3_oe(qspi_ram_0_auto_io_out_dq_3_oe),
    .auto_io_out_cs_0(qspi_ram_0_auto_io_out_cs_0)
  );
  assign auto_qspi_ram_0_int_xing_out_sync_0 = qspi_ram_0_auto_int_xing_out_sync_0; // @[LazyModule.scala 311:12]
  assign auto_qspi_ram_0_mem_xing_in_a_ready = qspi_ram_0_auto_mem_xing_in_a_ready; // @[LazyModule.scala 309:16]
  assign auto_qspi_ram_0_mem_xing_in_d_valid = qspi_ram_0_auto_mem_xing_in_d_valid; // @[LazyModule.scala 309:16]
  assign auto_qspi_ram_0_mem_xing_in_d_bits_opcode = qspi_ram_0_auto_mem_xing_in_d_bits_opcode; // @[LazyModule.scala 309:16]
  assign auto_qspi_ram_0_mem_xing_in_d_bits_size = qspi_ram_0_auto_mem_xing_in_d_bits_size; // @[LazyModule.scala 309:16]
  assign auto_qspi_ram_0_mem_xing_in_d_bits_source = qspi_ram_0_auto_mem_xing_in_d_bits_source; // @[LazyModule.scala 309:16]
  assign auto_qspi_ram_0_mem_xing_in_d_bits_data = qspi_ram_0_auto_mem_xing_in_d_bits_data; // @[LazyModule.scala 309:16]
  assign auto_qspi_ram_0_control_xing_in_a_ready = qspi_ram_0_auto_control_xing_in_a_ready; // @[LazyModule.scala 309:16]
  assign auto_qspi_ram_0_control_xing_in_d_valid = qspi_ram_0_auto_control_xing_in_d_valid; // @[LazyModule.scala 309:16]
  assign auto_qspi_ram_0_control_xing_in_d_bits_opcode = qspi_ram_0_auto_control_xing_in_d_bits_opcode; // @[LazyModule.scala 309:16]
  assign auto_qspi_ram_0_control_xing_in_d_bits_size = qspi_ram_0_auto_control_xing_in_d_bits_size; // @[LazyModule.scala 309:16]
  assign auto_qspi_ram_0_control_xing_in_d_bits_source = qspi_ram_0_auto_control_xing_in_d_bits_source; // @[LazyModule.scala 309:16]
  assign auto_qspi_ram_0_control_xing_in_d_bits_data = qspi_ram_0_auto_control_xing_in_d_bits_data; // @[LazyModule.scala 309:16]
  assign auto_qspi_ram_0_io_out_sck = qspi_ram_0_auto_io_out_sck; // @[LazyModule.scala 311:12]
  assign auto_qspi_ram_0_io_out_dq_0_o = qspi_ram_0_auto_io_out_dq_0_o; // @[LazyModule.scala 311:12]
  assign auto_qspi_ram_0_io_out_dq_0_oe = qspi_ram_0_auto_io_out_dq_0_oe; // @[LazyModule.scala 311:12]
  assign auto_qspi_ram_0_io_out_dq_1_o = qspi_ram_0_auto_io_out_dq_1_o; // @[LazyModule.scala 311:12]
  assign auto_qspi_ram_0_io_out_dq_1_oe = qspi_ram_0_auto_io_out_dq_1_oe; // @[LazyModule.scala 311:12]
  assign auto_qspi_ram_0_io_out_dq_2_o = qspi_ram_0_auto_io_out_dq_2_o; // @[LazyModule.scala 311:12]
  assign auto_qspi_ram_0_io_out_dq_2_oe = qspi_ram_0_auto_io_out_dq_2_oe; // @[LazyModule.scala 311:12]
  assign auto_qspi_ram_0_io_out_dq_3_o = qspi_ram_0_auto_io_out_dq_3_o; // @[LazyModule.scala 311:12]
  assign auto_qspi_ram_0_io_out_dq_3_oe = qspi_ram_0_auto_io_out_dq_3_oe; // @[LazyModule.scala 311:12]
  assign auto_qspi_ram_0_io_out_cs_0 = qspi_ram_0_auto_io_out_cs_0; // @[LazyModule.scala 311:12]
  assign qspi_ram_0_clock = auto_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign qspi_ram_0_reset = auto_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign qspi_ram_0_auto_mem_xing_in_a_valid = auto_qspi_ram_0_mem_xing_in_a_valid; // @[LazyModule.scala 309:16]
  assign qspi_ram_0_auto_mem_xing_in_a_bits_opcode = auto_qspi_ram_0_mem_xing_in_a_bits_opcode; // @[LazyModule.scala 309:16]
  assign qspi_ram_0_auto_mem_xing_in_a_bits_param = auto_qspi_ram_0_mem_xing_in_a_bits_param; // @[LazyModule.scala 309:16]
  assign qspi_ram_0_auto_mem_xing_in_a_bits_size = auto_qspi_ram_0_mem_xing_in_a_bits_size; // @[LazyModule.scala 309:16]
  assign qspi_ram_0_auto_mem_xing_in_a_bits_source = auto_qspi_ram_0_mem_xing_in_a_bits_source; // @[LazyModule.scala 309:16]
  assign qspi_ram_0_auto_mem_xing_in_a_bits_address = auto_qspi_ram_0_mem_xing_in_a_bits_address; // @[LazyModule.scala 309:16]
  assign qspi_ram_0_auto_mem_xing_in_a_bits_mask = auto_qspi_ram_0_mem_xing_in_a_bits_mask; // @[LazyModule.scala 309:16]
  assign qspi_ram_0_auto_mem_xing_in_a_bits_data = auto_qspi_ram_0_mem_xing_in_a_bits_data; // @[LazyModule.scala 309:16]
  assign qspi_ram_0_auto_mem_xing_in_a_bits_corrupt = auto_qspi_ram_0_mem_xing_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
  assign qspi_ram_0_auto_mem_xing_in_d_ready = auto_qspi_ram_0_mem_xing_in_d_ready; // @[LazyModule.scala 309:16]
  assign qspi_ram_0_auto_control_xing_in_a_valid = auto_qspi_ram_0_control_xing_in_a_valid; // @[LazyModule.scala 309:16]
  assign qspi_ram_0_auto_control_xing_in_a_bits_opcode = auto_qspi_ram_0_control_xing_in_a_bits_opcode; // @[LazyModule.scala 309:16]
  assign qspi_ram_0_auto_control_xing_in_a_bits_param = auto_qspi_ram_0_control_xing_in_a_bits_param; // @[LazyModule.scala 309:16]
  assign qspi_ram_0_auto_control_xing_in_a_bits_size = auto_qspi_ram_0_control_xing_in_a_bits_size; // @[LazyModule.scala 309:16]
  assign qspi_ram_0_auto_control_xing_in_a_bits_source = auto_qspi_ram_0_control_xing_in_a_bits_source; // @[LazyModule.scala 309:16]
  assign qspi_ram_0_auto_control_xing_in_a_bits_address = auto_qspi_ram_0_control_xing_in_a_bits_address; // @[LazyModule.scala 309:16]
  assign qspi_ram_0_auto_control_xing_in_a_bits_mask = auto_qspi_ram_0_control_xing_in_a_bits_mask; // @[LazyModule.scala 309:16]
  assign qspi_ram_0_auto_control_xing_in_a_bits_data = auto_qspi_ram_0_control_xing_in_a_bits_data; // @[LazyModule.scala 309:16]
  assign qspi_ram_0_auto_control_xing_in_a_bits_corrupt = auto_qspi_ram_0_control_xing_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
  assign qspi_ram_0_auto_control_xing_in_d_ready = auto_qspi_ram_0_control_xing_in_d_ready; // @[LazyModule.scala 309:16]
  assign qspi_ram_0_auto_io_out_dq_0_i = auto_qspi_ram_0_io_out_dq_0_i; // @[LazyModule.scala 311:12]
  assign qspi_ram_0_auto_io_out_dq_1_i = auto_qspi_ram_0_io_out_dq_1_i; // @[LazyModule.scala 311:12]
  assign qspi_ram_0_auto_io_out_dq_2_i = auto_qspi_ram_0_io_out_dq_2_i; // @[LazyModule.scala 311:12]
  assign qspi_ram_0_auto_io_out_dq_3_i = auto_qspi_ram_0_io_out_dq_3_i; // @[LazyModule.scala 311:12]
endmodule
module TLMonitor_65(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [1:0]  io_in_a_bits_size,
  input  [6:0]  io_in_a_bits_source,
  input  [28:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_size,
  input  [6:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [95:0] _RAND_10;
  reg [383:0] _RAND_11;
  reg [383:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [95:0] _RAND_16;
  reg [383:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T_4 = io_in_a_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire [4:0] _is_aligned_mask_T_1 = 5'h3 << io_in_a_bits_size; // @[package.scala 234:77]
  wire [1:0] is_aligned_mask = ~_is_aligned_mask_T_1[1:0]; // @[package.scala 234:46]
  wire [28:0] _GEN_71 = {{27'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 2'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [28:0] _T_33 = io_in_a_bits_address ^ 29'h10024000; // @[Parameters.scala 137:31]
  wire [29:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
  wire [29:0] _T_36 = $signed(_T_34) & -30'sh1000; // @[Parameters.scala 137:52]
  wire  _T_37 = $signed(_T_36) == 30'sh0; // @[Parameters.scala 137:67]
  wire  _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_74 = _T_73 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_164 = io_in_a_bits_size <= 2'h2; // @[Parameters.scala 92:42]
  wire  _T_172 = _T_164 & _T_37; // @[Parameters.scala 670:56]
  wire  _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_218 = _source_ok_T_4 & _T_172; // @[Monitor.scala 115:71]
  wire  _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_273 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_274 = io_in_a_bits_mask & _T_273; // @[Monitor.scala 127:31]
  wire  _T_275 = _T_274 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_279 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_347 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_355 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_385 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_397 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_10 = io_in_d_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire  _T_401 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_405 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 312:27]
  wire  _T_421 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_449 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_478 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_495 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_513 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [1:0] size; // @[Monitor.scala 386:22]
  reg [6:0] source; // @[Monitor.scala 387:22]
  reg [28:0] address; // @[Monitor.scala 388:22]
  wire  _T_543 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_544 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_548 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_552 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_556 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_560 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] size_1; // @[Monitor.scala 537:22]
  reg [6:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_567 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_568 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_576 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_580 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [95:0] inflight; // @[Monitor.scala 611:27]
  reg [383:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [383:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [8:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [9:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [383:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [383:0] _GEN_73 = {{368'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[383:1]}; // @[Monitor.scala 634:152]
  wire [383:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [383:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
  wire [383:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[383:1]}; // @[Monitor.scala 638:144]
  wire  _T_594 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [127:0] _a_set_wo_ready_T = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_597 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
  wire [8:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [9:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [1026:0] _GEN_1 = {{1023'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [1026:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
  wire [1025:0] _GEN_2 = {{1023'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [1025:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [95:0] _T_599 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_601 = ~_T_599[0]; // @[Monitor.scala 658:17]
  wire [127:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 652:72 653:28]
  wire [1026:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 1027'h0; // @[Monitor.scala 652:72 656:28]
  wire [1025:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 1026'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_605 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_607 = ~_T_401; // @[Monitor.scala 671:74]
  wire  _T_608 = io_in_d_valid & d_first_1 & ~_T_401; // @[Monitor.scala 671:71]
  wire [127:0] _d_clr_wo_ready_T = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [1038:0] _GEN_3 = {{1023'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [1038:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [127:0] _GEN_22 = d_first_done & d_first_1 & _T_607 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 675:91 676:21]
  wire [1038:0] _GEN_23 = d_first_done & d_first_1 & _T_607 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_594 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [95:0] _T_618 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_620 = _T_618[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_625 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_626 = io_in_d_bits_opcode == _GEN_32 | _T_625; // @[Monitor.scala 685:77]
  wire  _T_630 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_637 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_638 = io_in_d_bits_opcode == _GEN_48 | _T_637; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_642 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_652 = _T_605 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_607; // @[Monitor.scala 694:116]
  wire  _T_654 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [95:0] a_set = _GEN_16[95:0];
  wire [95:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [95:0] d_clr = _GEN_22[95:0];
  wire [95:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [95:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [383:0] a_opcodes_set = _GEN_19[383:0];
  wire [383:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [383:0] d_opcodes_clr = _GEN_23[383:0];
  wire [383:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [383:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [383:0] a_sizes_set = _GEN_20[383:0];
  wire [383:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [383:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_663 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [95:0] inflight_1; // @[Monitor.scala 723:35]
  reg [383:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [383:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [383:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
  wire [383:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[383:1]}; // @[Monitor.scala 747:146]
  wire  _T_689 = io_in_d_valid & d_first_2 & _T_401; // @[Monitor.scala 779:71]
  wire [127:0] _GEN_67 = d_first_done & d_first_2 & _T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 783:90 784:21]
  wire [1038:0] _GEN_68 = d_first_done & d_first_2 & _T_401 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 783:90 785:21]
  wire [95:0] _T_697 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_707 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [95:0] d_clr_1 = _GEN_67[95:0];
  wire [95:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [95:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [383:0] d_opcodes_clr_1 = _GEN_68[383:0];
  wire [383:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [383:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_727 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 1'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= 1'h0;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 96'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 384'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 384'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 1'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= 1'h0;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 96'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 384'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= 1'h0;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (d_first_done) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_172 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_172) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_275 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_275) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_309 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_309) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_347 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_347) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_385 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_397 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_397) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_478 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_478 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_495 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_495 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_513 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_513 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_544 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_544) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_548 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_548) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_552 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_552) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_556 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_556) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_560 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_560) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_568 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_568) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_576 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_576) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_580 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_580) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_601 & (_T_597 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_597 & ~reset & ~_T_601) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_620 & (_T_608 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & _T_2 & ~_T_620) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_626 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_626) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_630 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_630) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_638 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_638) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_642 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_642) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_654 & (_T_652 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_652 & _T_2 & ~_T_654) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_663 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_663) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_697[0] & (_T_689 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_689 & _T_2 & ~_T_697[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_707 & (_T_689 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_689 & _T_2 & ~_T_707) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_727 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_727) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[6:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[28:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[6:0];
  _RAND_10 = {3{`RANDOM}};
  inflight = _RAND_10[95:0];
  _RAND_11 = {12{`RANDOM}};
  inflight_opcodes = _RAND_11[383:0];
  _RAND_12 = {12{`RANDOM}};
  inflight_sizes = _RAND_12[383:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {3{`RANDOM}};
  inflight_1 = _RAND_16[95:0];
  _RAND_17 = {12{`RANDOM}};
  inflight_sizes_1 = _RAND_17[383:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module SPIPhysical_2(
  input         clock,
  input         reset,
  output        io_port_sck,
  input         io_port_dq_0_i,
  output        io_port_dq_0_o,
  output        io_port_dq_0_oe,
  input         io_port_dq_1_i,
  output        io_port_dq_1_o,
  output        io_port_dq_1_oe,
  input         io_port_dq_2_i,
  output        io_port_dq_2_o,
  output        io_port_dq_2_oe,
  input         io_port_dq_3_i,
  output        io_port_dq_3_o,
  output        io_port_dq_3_oe,
  input  [11:0] io_ctrl_sck_div,
  input         io_ctrl_sck_pol,
  input         io_ctrl_sck_pha,
  input  [1:0]  io_ctrl_fmt_proto,
  input         io_ctrl_fmt_endian,
  input         io_ctrl_fmt_iodir,
  input  [11:0] io_ctrl_extradel_coarse,
  input  [4:0]  io_ctrl_sampledel_sd,
  output        io_op_ready,
  input         io_op_valid,
  input         io_op_bits_fn,
  input         io_op_bits_stb,
  input  [7:0]  io_op_bits_cnt,
  input  [7:0]  io_op_bits_data,
  output        io_rx_valid,
  output [7:0]  io_rx_bits
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
`endif // RANDOMIZE_REG_INIT
  reg [11:0] ctrl_sck_div; // @[SPIPhysical.scala 52:17]
  reg  ctrl_sck_pol; // @[SPIPhysical.scala 52:17]
  reg  ctrl_sck_pha; // @[SPIPhysical.scala 52:17]
  reg [1:0] ctrl_fmt_proto; // @[SPIPhysical.scala 52:17]
  reg  ctrl_fmt_endian; // @[SPIPhysical.scala 52:17]
  reg  ctrl_fmt_iodir; // @[SPIPhysical.scala 52:17]
  wire  proto_0 = 2'h0 == ctrl_fmt_proto; // @[SPIConsts.scala 13:48]
  wire  proto_1 = 2'h1 == ctrl_fmt_proto; // @[SPIConsts.scala 13:48]
  wire  proto_2 = 2'h2 == ctrl_fmt_proto; // @[SPIConsts.scala 13:48]
  reg  setup_d; // @[SPIPhysical.scala 60:20]
  reg [7:0] scnt; // @[SPIPhysical.scala 62:17]
  reg [11:0] tcnt; // @[SPIPhysical.scala 63:17]
  wire  stop = scnt == 8'h0; // @[SPIPhysical.scala 65:20]
  wire  beat = tcnt == 12'h0; // @[SPIPhysical.scala 66:20]
  wire [11:0] _GEN_78 = {{7'd0}, io_ctrl_sampledel_sd}; // @[SPIPhysical.scala 69:49]
  wire [11:0] totalCoarseDel = io_ctrl_extradel_coarse + _GEN_78; // @[SPIPhysical.scala 69:49]
  reg  sample_d; // @[SPIPhysical.scala 70:25]
  reg [11:0] del_cntr; // @[SPIPhysical.scala 71:25]
  reg  xfr; // @[SPIPhysical.scala 182:16]
  reg  cref; // @[SPIPhysical.scala 117:17]
  wire  _GEN_10 = xfr & cref; // @[SPIPhysical.scala 190:18 192:16]
  wire  _GEN_15 = beat & _GEN_10; // @[SPIPhysical.scala 188:17]
  wire  sample = stop ? 1'h0 : _GEN_15; // @[SPIPhysical.scala 184:15]
  wire [11:0] _del_cntr_T_1 = totalCoarseDel - 12'h1; // @[SPIPhysical.scala 75:34]
  wire [11:0] _del_cntr_T_3 = del_cntr - 12'h1; // @[SPIPhysical.scala 82:28]
  wire  _T_3 = del_cntr == 12'h1; // @[SPIPhysical.scala 86:18]
  reg  last_d; // @[SPIPhysical.scala 92:23]
  reg [11:0] del_cntr_last; // @[SPIPhysical.scala 93:30]
  wire  last = scnt == 8'h1 & (beat & cref & xfr); // @[SPIPhysical.scala 201:27 202:10]
  wire [11:0] _del_cntr_last_T_3 = del_cntr_last - 12'h1; // @[SPIPhysical.scala 103:38]
  wire  _T_7 = del_cntr_last == 12'h1; // @[SPIPhysical.scala 107:23]
  wire [11:0] _decr_T = beat ? {{4'd0}, scnt} : tcnt; // @[SPIPhysical.scala 112:17]
  wire [11:0] decr = _decr_T - 12'h1; // @[SPIPhysical.scala 112:36]
  wire  sched = stop | beat; // @[SPIPhysical.scala 184:15 185:11]
  reg  sck; // @[SPIPhysical.scala 116:16]
  wire  cinv = ctrl_sck_pha ^ ctrl_sck_pol; // @[SPIPhysical.scala 118:27]
  wire [3:0] rxd = {io_port_dq_3_i,io_port_dq_2_i,io_port_dq_1_i,io_port_dq_0_i}; // @[Cat.scala 31:58]
  wire  rxd_delayed_0 = rxd[0]; // @[SPIPhysical.scala 135:24]
  wire  rxd_delayed_1 = rxd[1]; // @[SPIPhysical.scala 135:24]
  wire  rxd_delayed_2 = rxd[2]; // @[SPIPhysical.scala 135:24]
  wire  rxd_delayed_3 = rxd[3]; // @[SPIPhysical.scala 135:24]
  wire [3:0] rxd_fin = {rxd_delayed_3,rxd_delayed_2,rxd_delayed_1,rxd_delayed_0}; // @[SPIPhysical.scala 138:29]
  wire  samples_0 = rxd_fin[1]; // @[SPIPhysical.scala 139:28]
  wire [1:0] samples_1 = rxd_fin[1:0]; // @[SPIPhysical.scala 139:40]
  reg [7:0] buffer; // @[SPIPhysical.scala 141:19]
  wire [7:0] _buffer_in_T_9 = {io_op_bits_data[0],io_op_bits_data[1],io_op_bits_data[2],io_op_bits_data[3],
    io_op_bits_data[4],io_op_bits_data[5],io_op_bits_data[6],io_op_bits_data[7]}; // @[Cat.scala 31:58]
  wire [7:0] buffer_in = ~io_ctrl_fmt_endian ? io_op_bits_data : _buffer_in_T_9; // @[SPIPhysical.scala 121:8]
  wire  shift = totalCoarseDel > 12'h0 ? setup_d | sample_d & stop : sample_d; // @[SPIPhysical.scala 143:19]
  wire [6:0] _buffer_T_2 = shift ? buffer[6:0] : buffer[7:1]; // @[SPIPhysical.scala 147:12]
  wire  _buffer_T_4 = sample_d ? samples_0 : buffer[0]; // @[SPIPhysical.scala 148:12]
  wire [7:0] _buffer_T_5 = {_buffer_T_2,_buffer_T_4}; // @[Cat.scala 31:58]
  wire [5:0] _buffer_T_8 = shift ? buffer[5:0] : buffer[7:2]; // @[SPIPhysical.scala 147:12]
  wire [1:0] _buffer_T_10 = sample_d ? samples_1 : buffer[1:0]; // @[SPIPhysical.scala 148:12]
  wire [7:0] _buffer_T_11 = {_buffer_T_8,_buffer_T_10}; // @[Cat.scala 31:58]
  wire [3:0] _buffer_T_14 = shift ? buffer[3:0] : buffer[7:4]; // @[SPIPhysical.scala 147:12]
  wire [3:0] _buffer_T_16 = sample_d ? rxd_fin : buffer[3:0]; // @[SPIPhysical.scala 148:12]
  wire [7:0] _buffer_T_17 = {_buffer_T_14,_buffer_T_16}; // @[Cat.scala 31:58]
  wire [7:0] _buffer_T_18 = proto_0 ? _buffer_T_5 : 8'h0; // @[Mux.scala 27:73]
  wire [7:0] _buffer_T_19 = proto_1 ? _buffer_T_11 : 8'h0; // @[Mux.scala 27:73]
  wire [7:0] _buffer_T_20 = proto_2 ? _buffer_T_17 : 8'h0; // @[Mux.scala 27:73]
  wire [7:0] _buffer_T_21 = _buffer_T_18 | _buffer_T_19; // @[Mux.scala 27:73]
  wire [7:0] _buffer_T_22 = _buffer_T_21 | _buffer_T_20; // @[Mux.scala 27:73]
  reg [3:0] txd; // @[SPIPhysical.scala 153:16]
  wire  _T_18 = ~cref; // @[SPIPhysical.scala 203:19]
  wire  _GEN_25 = beat & ~cref | stop; // @[SPIPhysical.scala 203:26 204:14]
  wire  accept = scnt == 8'h1 ? _GEN_25 : stop; // @[SPIPhysical.scala 201:27]
  wire [3:0] txd_in = accept ? buffer_in[7:4] : buffer[7:4]; // @[SPIPhysical.scala 154:19]
  wire [1:0] _txd_sel_T = accept ? io_ctrl_fmt_proto : ctrl_fmt_proto; // @[SPIPhysical.scala 155:39]
  wire  txd_sel_0 = 2'h0 == _txd_sel_T; // @[SPIConsts.scala 13:48]
  wire  txd_sel_1 = 2'h1 == _txd_sel_T; // @[SPIConsts.scala 13:48]
  wire  txd_sel_2 = 2'h2 == _txd_sel_T; // @[SPIConsts.scala 13:48]
  wire  txd_shf_0 = txd_in[3]; // @[SPIPhysical.scala 156:55]
  wire [1:0] txd_shf_1 = txd_in[3:2]; // @[SPIPhysical.scala 156:55]
  wire  _txd_T = txd_sel_0 & txd_shf_0; // @[Mux.scala 27:73]
  wire [1:0] _txd_T_1 = txd_sel_1 ? txd_shf_1 : 2'h0; // @[Mux.scala 27:73]
  wire [3:0] _txd_T_2 = txd_sel_2 ? txd_in : 4'h0; // @[Mux.scala 27:73]
  wire [1:0] _GEN_79 = {{1'd0}, _txd_T}; // @[Mux.scala 27:73]
  wire [1:0] _txd_T_3 = _GEN_79 | _txd_T_1; // @[Mux.scala 27:73]
  wire [3:0] _GEN_80 = {{2'd0}, _txd_T_3}; // @[Mux.scala 27:73]
  wire [3:0] _txd_T_4 = _GEN_80 | _txd_T_2; // @[Mux.scala 27:73]
  reg  done; // @[SPIPhysical.scala 176:17]
  wire  _T_21 = ~io_op_bits_fn; // @[SPIPhysical.scala 220:22]
  wire  _GEN_11 = xfr & _T_18; // @[SPIPhysical.scala 190:18 193:15]
  wire  _GEN_16 = beat & _GEN_11; // @[SPIPhysical.scala 188:17]
  wire  _GEN_23 = stop ? 1'h0 : _GEN_16; // @[SPIPhysical.scala 184:15]
  wire  _GEN_26 = beat & ~cref ? 1'h0 : _GEN_23; // @[SPIPhysical.scala 203:26 205:13]
  wire  _GEN_30 = scnt == 8'h1 ? _GEN_26 : _GEN_23; // @[SPIPhysical.scala 201:27]
  wire  _GEN_45 = ~io_op_bits_fn | _GEN_30; // @[SPIPhysical.scala 220:22 224:17]
  wire  _GEN_59 = io_op_valid ? _GEN_45 : _GEN_30; // @[SPIPhysical.scala 212:24]
  wire  setup = accept & done ? _GEN_59 : _GEN_30; // @[SPIPhysical.scala 210:25]
  wire  txen_2 = proto_2 & ctrl_fmt_iodir; // @[SPIPhysical.scala 162:49]
  wire  txen_1 = proto_1 & ctrl_fmt_iodir | txen_2; // @[SPIPhysical.scala 162:82]
  wire [7:0] _io_rx_bits_T_9 = {buffer[0],buffer[1],buffer[2],buffer[3],buffer[4],buffer[5],buffer[6],buffer[7]}; // @[Cat.scala 31:58]
  wire  _GEN_9 = xfr ? cref ^ cinv : sck; // @[SPIPhysical.scala 190:18 191:13 116:16]
  wire [11:0] _GEN_12 = _T_18 ? decr : {{4'd0}, scnt}; // @[SPIPhysical.scala 195:20 196:14 62:17]
  wire  _GEN_13 = beat ? _T_18 : cref; // @[SPIPhysical.scala 188:17 189:12 117:17]
  wire  _GEN_14 = beat ? _GEN_9 : sck; // @[SPIPhysical.scala 116:16 188:17]
  wire [11:0] _GEN_17 = beat ? _GEN_12 : {{4'd0}, scnt}; // @[SPIPhysical.scala 188:17 62:17]
  wire  _GEN_20 = stop ? cref : _GEN_13; // @[SPIPhysical.scala 184:15 117:17]
  wire  _GEN_21 = stop ? sck : _GEN_14; // @[SPIPhysical.scala 184:15 116:16]
  wire [11:0] _GEN_24 = stop ? {{4'd0}, scnt} : _GEN_17; // @[SPIPhysical.scala 184:15 62:17]
  wire  _GEN_27 = beat & ~cref ? ctrl_sck_pol : _GEN_21; // @[SPIPhysical.scala 203:26 206:11]
  wire  _GEN_31 = scnt == 8'h1 ? _GEN_27 : _GEN_21; // @[SPIPhysical.scala 201:27]
  wire  _GEN_35 = io_op_bits_stb ? io_ctrl_sck_pol : _GEN_31; // @[SPIPhysical.scala 229:25 230:17]
  wire [11:0] _GEN_36 = io_op_bits_stb ? io_ctrl_sck_div : ctrl_sck_div; // @[SPIPhysical.scala 229:25 231:22 52:17]
  wire  _GEN_37 = io_op_bits_stb ? io_ctrl_sck_pol : ctrl_sck_pol; // @[SPIPhysical.scala 229:25 231:22 52:17]
  wire  _GEN_38 = io_op_bits_stb ? io_ctrl_sck_pha : ctrl_sck_pha; // @[SPIPhysical.scala 229:25 231:22 52:17]
  wire  _GEN_46 = ~io_op_bits_fn ? io_op_bits_cnt == 8'h0 : done | last_d; // @[SPIPhysical.scala 220:22 225:16 177:8]
  wire [11:0] _GEN_51 = io_op_valid ? {{4'd0}, io_op_bits_cnt} : _GEN_24; // @[SPIPhysical.scala 212:24 213:12]
  wire  _GEN_60 = io_op_valid ? _GEN_46 : done | last_d; // @[SPIPhysical.scala 212:24 177:8]
  wire [11:0] _GEN_65 = accept & done ? _GEN_51 : _GEN_24; // @[SPIPhysical.scala 210:25]
  wire  _GEN_74 = accept & done ? _GEN_60 : done | last_d; // @[SPIPhysical.scala 210:25 177:8]
  assign io_port_sck = sck; // @[SPIPhysical.scala 166:15]
  assign io_port_dq_0_o = txd[0]; // @[SPIPhysical.scala 168:24]
  assign io_port_dq_0_oe = proto_0 | txen_1; // @[SPIPhysical.scala 162:82]
  assign io_port_dq_1_o = txd[1]; // @[SPIPhysical.scala 168:24]
  assign io_port_dq_1_oe = proto_1 & ctrl_fmt_iodir | txen_2; // @[SPIPhysical.scala 162:82]
  assign io_port_dq_2_o = txd[2]; // @[SPIPhysical.scala 168:24]
  assign io_port_dq_2_oe = proto_2 & ctrl_fmt_iodir; // @[SPIPhysical.scala 162:49]
  assign io_port_dq_3_o = txd[3]; // @[SPIPhysical.scala 168:24]
  assign io_port_dq_3_oe = proto_2 & ctrl_fmt_iodir; // @[SPIPhysical.scala 162:49]
  assign io_op_ready = accept & done; // @[SPIPhysical.scala 210:16]
  assign io_rx_valid = done; // @[SPIPhysical.scala 179:15]
  assign io_rx_bits = ~ctrl_fmt_endian ? buffer : _io_rx_bits_T_9; // @[SPIPhysical.scala 121:8]
  always @(posedge clock) begin
    if (accept & done) begin // @[SPIPhysical.scala 210:25]
      if (io_op_valid) begin // @[SPIPhysical.scala 212:24]
        if (!(~io_op_bits_fn)) begin // @[SPIPhysical.scala 220:22]
          if (io_op_bits_fn) begin // @[SPIPhysical.scala 220:22]
            ctrl_sck_div <= _GEN_36;
          end
        end
      end
    end
    if (accept & done) begin // @[SPIPhysical.scala 210:25]
      if (io_op_valid) begin // @[SPIPhysical.scala 212:24]
        if (!(~io_op_bits_fn)) begin // @[SPIPhysical.scala 220:22]
          if (io_op_bits_fn) begin // @[SPIPhysical.scala 220:22]
            ctrl_sck_pol <= _GEN_37;
          end
        end
      end
    end
    if (accept & done) begin // @[SPIPhysical.scala 210:25]
      if (io_op_valid) begin // @[SPIPhysical.scala 212:24]
        if (!(~io_op_bits_fn)) begin // @[SPIPhysical.scala 220:22]
          if (io_op_bits_fn) begin // @[SPIPhysical.scala 220:22]
            ctrl_sck_pha <= _GEN_38;
          end
        end
      end
    end
    if (accept & done) begin // @[SPIPhysical.scala 210:25]
      if (io_op_valid) begin // @[SPIPhysical.scala 212:24]
        if (io_op_bits_stb) begin // @[SPIPhysical.scala 215:21]
          ctrl_fmt_proto <= io_ctrl_fmt_proto; // @[SPIPhysical.scala 216:18]
        end
      end
    end
    if (accept & done) begin // @[SPIPhysical.scala 210:25]
      if (io_op_valid) begin // @[SPIPhysical.scala 212:24]
        if (io_op_bits_stb) begin // @[SPIPhysical.scala 215:21]
          ctrl_fmt_endian <= io_ctrl_fmt_endian; // @[SPIPhysical.scala 216:18]
        end
      end
    end
    if (accept & done) begin // @[SPIPhysical.scala 210:25]
      if (io_op_valid) begin // @[SPIPhysical.scala 212:24]
        if (io_op_bits_stb) begin // @[SPIPhysical.scala 215:21]
          ctrl_fmt_iodir <= io_ctrl_fmt_iodir; // @[SPIPhysical.scala 216:18]
        end
      end
    end
    if (accept & done) begin // @[SPIPhysical.scala 210:25]
      if (io_op_valid) begin // @[SPIPhysical.scala 212:24]
        setup_d <= _GEN_45;
      end else begin
        setup_d <= _GEN_30;
      end
    end else begin
      setup_d <= _GEN_30;
    end
    if (reset) begin // @[SPIPhysical.scala 62:17]
      scnt <= 8'h0; // @[SPIPhysical.scala 62:17]
    end else begin
      scnt <= _GEN_65[7:0];
    end
    if (sched) begin // @[SPIPhysical.scala 114:14]
      tcnt <= ctrl_sck_div;
    end else begin
      tcnt <= decr;
    end
    if (reset) begin // @[SPIPhysical.scala 70:25]
      sample_d <= 1'h0; // @[SPIPhysical.scala 70:25]
    end else begin
      sample_d <= _T_3;
    end
    if (reset) begin // @[SPIPhysical.scala 71:25]
      del_cntr <= 12'h3; // @[SPIPhysical.scala 71:25]
    end else if (beat & sample) begin // @[SPIPhysical.scala 73:25]
      if (totalCoarseDel > 12'h1) begin // @[SPIPhysical.scala 74:32]
        del_cntr <= _del_cntr_T_1; // @[SPIPhysical.scala 75:16]
      end else begin
        del_cntr <= 12'h1; // @[SPIPhysical.scala 78:16]
      end
    end else if (del_cntr != 12'h0) begin // @[SPIPhysical.scala 81:27]
      del_cntr <= _del_cntr_T_3; // @[SPIPhysical.scala 82:16]
    end
    if (accept & done) begin // @[SPIPhysical.scala 210:25]
      if (io_op_valid) begin // @[SPIPhysical.scala 212:24]
        xfr <= _T_21;
      end
    end
    cref <= reset | _GEN_20; // @[SPIPhysical.scala 117:{17,17}]
    if (reset) begin // @[SPIPhysical.scala 92:23]
      last_d <= 1'h0; // @[SPIPhysical.scala 92:23]
    end else begin
      last_d <= _T_7;
    end
    if (reset) begin // @[SPIPhysical.scala 93:30]
      del_cntr_last <= 12'h3; // @[SPIPhysical.scala 93:30]
    end else if (beat & last) begin // @[SPIPhysical.scala 94:23]
      if (totalCoarseDel > 12'h1) begin // @[SPIPhysical.scala 74:32]
        del_cntr_last <= _del_cntr_T_1; // @[SPIPhysical.scala 75:16]
      end else begin
        del_cntr_last <= 12'h1; // @[SPIPhysical.scala 78:16]
      end
    end else if (del_cntr_last != 12'h0) begin // @[SPIPhysical.scala 102:33]
      del_cntr_last <= _del_cntr_last_T_3; // @[SPIPhysical.scala 103:21]
    end
    if (accept & done) begin // @[SPIPhysical.scala 210:25]
      if (io_op_valid) begin // @[SPIPhysical.scala 212:24]
        if (~io_op_bits_fn) begin // @[SPIPhysical.scala 220:22]
          sck <= cinv; // @[SPIPhysical.scala 223:15]
        end else if (io_op_bits_fn) begin // @[SPIPhysical.scala 220:22]
          sck <= _GEN_35;
        end else begin
          sck <= _GEN_31;
        end
      end else begin
        sck <= _GEN_31;
      end
    end else begin
      sck <= _GEN_31;
    end
    if (accept & done) begin // @[SPIPhysical.scala 210:25]
      if (io_op_valid) begin // @[SPIPhysical.scala 212:24]
        if (~io_op_bits_fn) begin // @[SPIPhysical.scala 220:22]
          if (~io_ctrl_fmt_endian) begin // @[SPIPhysical.scala 121:8]
            buffer <= io_op_bits_data;
          end else begin
            buffer <= _buffer_in_T_9;
          end
        end else begin
          buffer <= _buffer_T_22; // @[SPIPhysical.scala 144:10]
        end
      end else begin
        buffer <= _buffer_T_22; // @[SPIPhysical.scala 144:10]
      end
    end else begin
      buffer <= _buffer_T_22; // @[SPIPhysical.scala 144:10]
    end
    if (reset) begin // @[SPIPhysical.scala 153:16]
      txd <= 4'h0; // @[SPIPhysical.scala 153:16]
    end else if (setup) begin // @[SPIPhysical.scala 157:16]
      txd <= _txd_T_4; // @[SPIPhysical.scala 158:9]
    end
    done <= reset | _GEN_74; // @[SPIPhysical.scala 176:{17,17}]
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  ctrl_sck_div = _RAND_0[11:0];
  _RAND_1 = {1{`RANDOM}};
  ctrl_sck_pol = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  ctrl_sck_pha = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  ctrl_fmt_proto = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  ctrl_fmt_endian = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  ctrl_fmt_iodir = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  setup_d = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  scnt = _RAND_7[7:0];
  _RAND_8 = {1{`RANDOM}};
  tcnt = _RAND_8[11:0];
  _RAND_9 = {1{`RANDOM}};
  sample_d = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  del_cntr = _RAND_10[11:0];
  _RAND_11 = {1{`RANDOM}};
  xfr = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  cref = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  last_d = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  del_cntr_last = _RAND_14[11:0];
  _RAND_15 = {1{`RANDOM}};
  sck = _RAND_15[0:0];
  _RAND_16 = {1{`RANDOM}};
  buffer = _RAND_16[7:0];
  _RAND_17 = {1{`RANDOM}};
  txd = _RAND_17[3:0];
  _RAND_18 = {1{`RANDOM}};
  done = _RAND_18[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module SPIMedia_2(
  input         clock,
  input         reset,
  output        io_port_sck,
  input         io_port_dq_0_i,
  output        io_port_dq_0_o,
  output        io_port_dq_0_oe,
  input         io_port_dq_1_i,
  output        io_port_dq_1_o,
  output        io_port_dq_1_oe,
  input         io_port_dq_2_i,
  output        io_port_dq_2_o,
  output        io_port_dq_2_oe,
  input         io_port_dq_3_i,
  output        io_port_dq_3_o,
  output        io_port_dq_3_oe,
  output        io_port_cs_0,
  output        io_port_cs_1,
  input  [11:0] io_ctrl_sck_div,
  input         io_ctrl_sck_pol,
  input         io_ctrl_sck_pha,
  input  [7:0]  io_ctrl_dla_cssck,
  input  [7:0]  io_ctrl_dla_sckcs,
  input  [7:0]  io_ctrl_dla_intercs,
  input  [7:0]  io_ctrl_dla_interxfr,
  input         io_ctrl_cs_id,
  input         io_ctrl_cs_dflt_0,
  input         io_ctrl_cs_dflt_1,
  input  [11:0] io_ctrl_extradel_coarse,
  input  [4:0]  io_ctrl_sampledel_sd,
  output        io_link_tx_ready,
  input         io_link_tx_valid,
  input  [7:0]  io_link_tx_bits,
  output        io_link_rx_valid,
  output [7:0]  io_link_rx_bits,
  input  [7:0]  io_link_cnt,
  input  [1:0]  io_link_fmt_proto,
  input         io_link_fmt_endian,
  input         io_link_fmt_iodir,
  input         io_link_cs_set,
  input         io_link_cs_clear
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
`endif // RANDOMIZE_REG_INIT
  wire  phy_clock; // @[SPIMedia.scala 36:19]
  wire  phy_reset; // @[SPIMedia.scala 36:19]
  wire  phy_io_port_sck; // @[SPIMedia.scala 36:19]
  wire  phy_io_port_dq_0_i; // @[SPIMedia.scala 36:19]
  wire  phy_io_port_dq_0_o; // @[SPIMedia.scala 36:19]
  wire  phy_io_port_dq_0_oe; // @[SPIMedia.scala 36:19]
  wire  phy_io_port_dq_1_i; // @[SPIMedia.scala 36:19]
  wire  phy_io_port_dq_1_o; // @[SPIMedia.scala 36:19]
  wire  phy_io_port_dq_1_oe; // @[SPIMedia.scala 36:19]
  wire  phy_io_port_dq_2_i; // @[SPIMedia.scala 36:19]
  wire  phy_io_port_dq_2_o; // @[SPIMedia.scala 36:19]
  wire  phy_io_port_dq_2_oe; // @[SPIMedia.scala 36:19]
  wire  phy_io_port_dq_3_i; // @[SPIMedia.scala 36:19]
  wire  phy_io_port_dq_3_o; // @[SPIMedia.scala 36:19]
  wire  phy_io_port_dq_3_oe; // @[SPIMedia.scala 36:19]
  wire [11:0] phy_io_ctrl_sck_div; // @[SPIMedia.scala 36:19]
  wire  phy_io_ctrl_sck_pol; // @[SPIMedia.scala 36:19]
  wire  phy_io_ctrl_sck_pha; // @[SPIMedia.scala 36:19]
  wire [1:0] phy_io_ctrl_fmt_proto; // @[SPIMedia.scala 36:19]
  wire  phy_io_ctrl_fmt_endian; // @[SPIMedia.scala 36:19]
  wire  phy_io_ctrl_fmt_iodir; // @[SPIMedia.scala 36:19]
  wire [11:0] phy_io_ctrl_extradel_coarse; // @[SPIMedia.scala 36:19]
  wire [4:0] phy_io_ctrl_sampledel_sd; // @[SPIMedia.scala 36:19]
  wire  phy_io_op_ready; // @[SPIMedia.scala 36:19]
  wire  phy_io_op_valid; // @[SPIMedia.scala 36:19]
  wire  phy_io_op_bits_fn; // @[SPIMedia.scala 36:19]
  wire  phy_io_op_bits_stb; // @[SPIMedia.scala 36:19]
  wire [7:0] phy_io_op_bits_cnt; // @[SPIMedia.scala 36:19]
  wire [7:0] phy_io_op_bits_data; // @[SPIMedia.scala 36:19]
  wire  phy_io_rx_valid; // @[SPIMedia.scala 36:19]
  wire [7:0] phy_io_rx_bits; // @[SPIMedia.scala 36:19]
  reg  cs_id; // @[SPIMedia.scala 50:15]
  reg  cs_dflt_0; // @[SPIMedia.scala 50:15]
  reg  cs_dflt_1; // @[SPIMedia.scala 50:15]
  reg  cs_set; // @[SPIMedia.scala 51:19]
  wire [1:0] _GEN_4 = {{1'd0}, io_link_cs_set}; // @[SPIBundle.scala 49:19]
  wire [1:0] cs_active_mask = _GEN_4 << io_ctrl_cs_id; // @[SPIBundle.scala 49:19]
  wire [1:0] _cs_active_out_T = {io_ctrl_cs_dflt_1,io_ctrl_cs_dflt_0}; // @[Cat.scala 31:58]
  wire [1:0] cs_active_out = _cs_active_out_T ^ cs_active_mask; // @[SPIBundle.scala 50:33]
  wire  cs_active_0 = cs_active_out[0]; // @[SPIBundle.scala 51:32]
  wire  cs_active_1 = cs_active_out[1]; // @[SPIBundle.scala 51:32]
  wire [1:0] _cs_update_T = {cs_active_1,cs_active_0}; // @[SPIMedia.scala 53:30]
  wire [1:0] _cs_update_T_1 = {cs_dflt_1,cs_dflt_0}; // @[SPIMedia.scala 53:49]
  wire  cs_update = _cs_update_T != _cs_update_T_1; // @[SPIMedia.scala 53:37]
  reg  clear; // @[SPIMedia.scala 55:18]
  reg  cs_assert; // @[SPIMedia.scala 56:22]
  wire  cs_deassert = clear | cs_update; // @[SPIMedia.scala 57:27]
  wire  continuous = io_ctrl_dla_interxfr == 8'h0; // @[SPIMedia.scala 61:42]
  reg [1:0] state; // @[SPIMedia.scala 72:18]
  wire [1:0] _GEN_0 = phy_io_op_ready ? 2'h2 : state; // @[SPIMedia.scala 72:18 79:27 80:19]
  wire  _T_1 = phy_io_op_ready & phy_io_op_valid; // @[Decoupled.scala 50:35]
  wire [1:0] _GEN_1 = _T_1 ? 2'h1 : state; // @[SPIMedia.scala 72:18 88:28 89:19]
  wire [7:0] _GEN_2 = cs_deassert ? io_ctrl_dla_sckcs : io_link_cnt; // @[SPIMedia.scala 46:15 77:28 78:23]
  wire  _GEN_5 = cs_deassert ? 1'h0 : 1'h1; // @[SPIMedia.scala 45:15 77:28 84:23]
  wire  _GEN_6 = cs_deassert | io_link_tx_valid; // @[SPIMedia.scala 43:12 77:28 86:20]
  wire  _GEN_7 = cs_deassert ? 1'h0 : phy_io_op_ready; // @[SPIMedia.scala 68:20 77:28 87:28]
  wire  _GEN_8 = phy_io_op_ready | cs_assert; // @[SPIMedia.scala 95:25 96:21 56:22]
  wire [7:0] _GEN_12 = io_link_tx_valid ? io_ctrl_dla_cssck : 8'h0; // @[SPIMedia.scala 102:21 92:38 94:21]
  wire  _GEN_17 = io_link_tx_valid ? 1'h0 : 1'h1; // @[SPIMedia.scala 45:15 103:21 92:38]
  wire [7:0] _GEN_19 = cs_assert ? _GEN_2 : _GEN_12; // @[SPIMedia.scala 76:24]
  wire  _GEN_21 = cs_assert ? cs_deassert : 1'h1; // @[SPIMedia.scala 44:14 76:24]
  wire  _GEN_22 = cs_assert ? _GEN_5 : _GEN_17; // @[SPIMedia.scala 76:24]
  wire  _GEN_23 = cs_assert ? _GEN_6 : 1'h1; // @[SPIMedia.scala 43:12 76:24]
  wire  _GEN_24 = cs_assert & _GEN_7; // @[SPIMedia.scala 68:20 76:24]
  wire [1:0] _GEN_35 = {{1'd0}, cs_set}; // @[SPIBundle.scala 49:19]
  wire [1:0] mask = _GEN_35 << cs_id; // @[SPIBundle.scala 49:19]
  wire [1:0] out = _cs_update_T_1 ^ mask; // @[SPIBundle.scala 50:33]
  wire [1:0] _GEN_33 = phy_io_op_ready ? 2'h0 : state; // @[SPIMedia.scala 123:23 125:15 72:18]
  wire [7:0] _GEN_34 = 2'h2 == state ? io_ctrl_dla_intercs : io_link_cnt; // @[SPIMedia.scala 74:18 119:19 46:15]
  wire  _GEN_41 = 2'h1 == state ? ~continuous : 1'h1; // @[SPIMedia.scala 110:16 43:12 74:18]
  wire [7:0] _GEN_42 = 2'h1 == state ? io_ctrl_dla_interxfr : _GEN_34; // @[SPIMedia.scala 74:18 111:19]
  wire  _GEN_44 = 2'h1 == state ? 1'h0 : 2'h2 == state; // @[SPIMedia.scala 45:15 74:18]
  SPIPhysical_2 phy ( // @[SPIMedia.scala 36:19]
    .clock(phy_clock),
    .reset(phy_reset),
    .io_port_sck(phy_io_port_sck),
    .io_port_dq_0_i(phy_io_port_dq_0_i),
    .io_port_dq_0_o(phy_io_port_dq_0_o),
    .io_port_dq_0_oe(phy_io_port_dq_0_oe),
    .io_port_dq_1_i(phy_io_port_dq_1_i),
    .io_port_dq_1_o(phy_io_port_dq_1_o),
    .io_port_dq_1_oe(phy_io_port_dq_1_oe),
    .io_port_dq_2_i(phy_io_port_dq_2_i),
    .io_port_dq_2_o(phy_io_port_dq_2_o),
    .io_port_dq_2_oe(phy_io_port_dq_2_oe),
    .io_port_dq_3_i(phy_io_port_dq_3_i),
    .io_port_dq_3_o(phy_io_port_dq_3_o),
    .io_port_dq_3_oe(phy_io_port_dq_3_oe),
    .io_ctrl_sck_div(phy_io_ctrl_sck_div),
    .io_ctrl_sck_pol(phy_io_ctrl_sck_pol),
    .io_ctrl_sck_pha(phy_io_ctrl_sck_pha),
    .io_ctrl_fmt_proto(phy_io_ctrl_fmt_proto),
    .io_ctrl_fmt_endian(phy_io_ctrl_fmt_endian),
    .io_ctrl_fmt_iodir(phy_io_ctrl_fmt_iodir),
    .io_ctrl_extradel_coarse(phy_io_ctrl_extradel_coarse),
    .io_ctrl_sampledel_sd(phy_io_ctrl_sampledel_sd),
    .io_op_ready(phy_io_op_ready),
    .io_op_valid(phy_io_op_valid),
    .io_op_bits_fn(phy_io_op_bits_fn),
    .io_op_bits_stb(phy_io_op_bits_stb),
    .io_op_bits_cnt(phy_io_op_bits_cnt),
    .io_op_bits_data(phy_io_op_bits_data),
    .io_rx_valid(phy_io_rx_valid),
    .io_rx_bits(phy_io_rx_bits)
  );
  assign io_port_sck = phy_io_port_sck; // @[SPIMedia.scala 63:15]
  assign io_port_dq_0_o = phy_io_port_dq_0_o; // @[SPIMedia.scala 64:14]
  assign io_port_dq_0_oe = phy_io_port_dq_0_oe; // @[SPIMedia.scala 64:14]
  assign io_port_dq_1_o = phy_io_port_dq_1_o; // @[SPIMedia.scala 64:14]
  assign io_port_dq_1_oe = phy_io_port_dq_1_oe; // @[SPIMedia.scala 64:14]
  assign io_port_dq_2_o = phy_io_port_dq_2_o; // @[SPIMedia.scala 64:14]
  assign io_port_dq_2_oe = phy_io_port_dq_2_oe; // @[SPIMedia.scala 64:14]
  assign io_port_dq_3_o = phy_io_port_dq_3_o; // @[SPIMedia.scala 64:14]
  assign io_port_dq_3_oe = phy_io_port_dq_3_oe; // @[SPIMedia.scala 64:14]
  assign io_port_cs_0 = cs_dflt_0; // @[SPIMedia.scala 65:14]
  assign io_port_cs_1 = cs_dflt_1; // @[SPIMedia.scala 65:14]
  assign io_link_tx_ready = 2'h0 == state & _GEN_24; // @[SPIMedia.scala 74:18 68:20]
  assign io_link_rx_valid = phy_io_rx_valid; // @[SPIMedia.scala 67:14]
  assign io_link_rx_bits = phy_io_rx_bits; // @[SPIMedia.scala 67:14]
  assign phy_clock = clock;
  assign phy_reset = reset;
  assign phy_io_port_dq_0_i = io_port_dq_0_i; // @[SPIMedia.scala 64:14]
  assign phy_io_port_dq_1_i = io_port_dq_1_i; // @[SPIMedia.scala 64:14]
  assign phy_io_port_dq_2_i = io_port_dq_2_i; // @[SPIMedia.scala 64:14]
  assign phy_io_port_dq_3_i = io_port_dq_3_i; // @[SPIMedia.scala 64:14]
  assign phy_io_ctrl_sck_div = io_ctrl_sck_div; // @[SPIMedia.scala 37:19]
  assign phy_io_ctrl_sck_pol = io_ctrl_sck_pol; // @[SPIMedia.scala 37:19]
  assign phy_io_ctrl_sck_pha = io_ctrl_sck_pha; // @[SPIMedia.scala 37:19]
  assign phy_io_ctrl_fmt_proto = io_link_fmt_proto; // @[SPIMedia.scala 38:19]
  assign phy_io_ctrl_fmt_endian = io_link_fmt_endian; // @[SPIMedia.scala 38:19]
  assign phy_io_ctrl_fmt_iodir = io_link_fmt_iodir; // @[SPIMedia.scala 38:19]
  assign phy_io_ctrl_extradel_coarse = io_ctrl_extradel_coarse; // @[SPIMedia.scala 39:24]
  assign phy_io_ctrl_sampledel_sd = io_ctrl_sampledel_sd; // @[SPIMedia.scala 40:25]
  assign phy_io_op_valid = 2'h0 == state ? _GEN_23 : _GEN_41; // @[SPIMedia.scala 74:18]
  assign phy_io_op_bits_fn = 2'h0 == state ? _GEN_21 : 1'h1; // @[SPIMedia.scala 44:14 74:18]
  assign phy_io_op_bits_stb = 2'h0 == state ? _GEN_22 : _GEN_44; // @[SPIMedia.scala 74:18]
  assign phy_io_op_bits_cnt = 2'h0 == state ? _GEN_19 : _GEN_42; // @[SPIMedia.scala 74:18]
  assign phy_io_op_bits_data = io_link_tx_bits; // @[SPIMedia.scala 47:16]
  always @(posedge clock) begin
    if (2'h0 == state) begin // @[SPIMedia.scala 74:18]
      if (!(cs_assert)) begin // @[SPIMedia.scala 76:24]
        if (!(io_link_tx_valid)) begin // @[SPIMedia.scala 92:38]
          cs_id <= io_ctrl_cs_id; // @[SPIMedia.scala 104:12]
        end
      end
    end
    if (2'h0 == state) begin // @[SPIMedia.scala 74:18]
      if (!(cs_assert)) begin // @[SPIMedia.scala 76:24]
        if (io_link_tx_valid) begin // @[SPIMedia.scala 92:38]
          if (phy_io_op_ready) begin // @[SPIMedia.scala 95:25]
            cs_dflt_0 <= cs_active_0; // @[SPIMedia.scala 98:19]
          end
        end else begin
          cs_dflt_0 <= io_ctrl_cs_dflt_0; // @[SPIMedia.scala 104:12]
        end
      end
    end else if (!(2'h1 == state)) begin // @[SPIMedia.scala 74:18]
      if (2'h2 == state) begin // @[SPIMedia.scala 74:18]
        if (phy_io_op_ready) begin // @[SPIMedia.scala 123:23]
          cs_dflt_0 <= out[0]; // @[SPIMedia.scala 124:17]
        end
      end
    end
    if (2'h0 == state) begin // @[SPIMedia.scala 74:18]
      if (!(cs_assert)) begin // @[SPIMedia.scala 76:24]
        if (io_link_tx_valid) begin // @[SPIMedia.scala 92:38]
          if (phy_io_op_ready) begin // @[SPIMedia.scala 95:25]
            cs_dflt_1 <= cs_active_1; // @[SPIMedia.scala 98:19]
          end
        end else begin
          cs_dflt_1 <= io_ctrl_cs_dflt_1; // @[SPIMedia.scala 104:12]
        end
      end
    end else if (!(2'h1 == state)) begin // @[SPIMedia.scala 74:18]
      if (2'h2 == state) begin // @[SPIMedia.scala 74:18]
        if (phy_io_op_ready) begin // @[SPIMedia.scala 123:23]
          cs_dflt_1 <= out[1]; // @[SPIMedia.scala 124:17]
        end
      end
    end
    if (2'h0 == state) begin // @[SPIMedia.scala 74:18]
      if (!(cs_assert)) begin // @[SPIMedia.scala 76:24]
        if (io_link_tx_valid) begin // @[SPIMedia.scala 92:38]
          if (phy_io_op_ready) begin // @[SPIMedia.scala 95:25]
            cs_set <= io_link_cs_set; // @[SPIMedia.scala 97:18]
          end
        end
      end
    end
    if (reset) begin // @[SPIMedia.scala 55:18]
      clear <= 1'h0; // @[SPIMedia.scala 55:18]
    end else if (2'h0 == state) begin // @[SPIMedia.scala 74:18]
      clear <= clear | io_link_cs_clear & cs_assert; // @[SPIMedia.scala 59:9]
    end else if (2'h1 == state) begin // @[SPIMedia.scala 74:18]
      clear <= clear | io_link_cs_clear & cs_assert; // @[SPIMedia.scala 59:9]
    end else if (2'h2 == state) begin // @[SPIMedia.scala 74:18]
      clear <= 1'h0; // @[SPIMedia.scala 122:13]
    end else begin
      clear <= clear | io_link_cs_clear & cs_assert; // @[SPIMedia.scala 59:9]
    end
    if (reset) begin // @[SPIMedia.scala 56:22]
      cs_assert <= 1'h0; // @[SPIMedia.scala 56:22]
    end else if (2'h0 == state) begin // @[SPIMedia.scala 74:18]
      if (!(cs_assert)) begin // @[SPIMedia.scala 76:24]
        if (io_link_tx_valid) begin // @[SPIMedia.scala 92:38]
          cs_assert <= _GEN_8;
        end
      end
    end else if (!(2'h1 == state)) begin // @[SPIMedia.scala 74:18]
      if (2'h2 == state) begin // @[SPIMedia.scala 74:18]
        cs_assert <= 1'h0; // @[SPIMedia.scala 121:17]
      end
    end
    if (reset) begin // @[SPIMedia.scala 72:18]
      state <= 2'h0; // @[SPIMedia.scala 72:18]
    end else if (2'h0 == state) begin // @[SPIMedia.scala 74:18]
      if (cs_assert) begin // @[SPIMedia.scala 76:24]
        if (cs_deassert) begin // @[SPIMedia.scala 77:28]
          state <= _GEN_0;
        end else begin
          state <= _GEN_1;
        end
      end
    end else if (2'h1 == state) begin // @[SPIMedia.scala 74:18]
      if (phy_io_op_ready | continuous) begin // @[SPIMedia.scala 112:37]
        state <= 2'h0; // @[SPIMedia.scala 113:15]
      end
    end else if (2'h2 == state) begin // @[SPIMedia.scala 74:18]
      state <= _GEN_33;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  cs_id = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  cs_dflt_0 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  cs_dflt_1 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  cs_set = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  clear = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  cs_assert = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  state = _RAND_6[1:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLSPI(
  input         clock,
  input         reset,
  output        auto_int_xing_out_sync_0,
  output        auto_control_xing_in_a_ready,
  input         auto_control_xing_in_a_valid,
  input  [2:0]  auto_control_xing_in_a_bits_opcode,
  input  [2:0]  auto_control_xing_in_a_bits_param,
  input  [1:0]  auto_control_xing_in_a_bits_size,
  input  [6:0]  auto_control_xing_in_a_bits_source,
  input  [28:0] auto_control_xing_in_a_bits_address,
  input  [3:0]  auto_control_xing_in_a_bits_mask,
  input  [31:0] auto_control_xing_in_a_bits_data,
  input         auto_control_xing_in_a_bits_corrupt,
  input         auto_control_xing_in_d_ready,
  output        auto_control_xing_in_d_valid,
  output [2:0]  auto_control_xing_in_d_bits_opcode,
  output [1:0]  auto_control_xing_in_d_bits_size,
  output [6:0]  auto_control_xing_in_d_bits_source,
  output [31:0] auto_control_xing_in_d_bits_data,
  output        auto_io_out_sck,
  input         auto_io_out_dq_0_i,
  output        auto_io_out_dq_0_o,
  output        auto_io_out_dq_0_oe,
  input         auto_io_out_dq_1_i,
  output        auto_io_out_dq_1_o,
  output        auto_io_out_dq_1_oe,
  input         auto_io_out_dq_2_i,
  output        auto_io_out_dq_2_o,
  output        auto_io_out_dq_2_oe,
  input         auto_io_out_dq_3_i,
  output        auto_io_out_dq_3_o,
  output        auto_io_out_dq_3_oe,
  output        auto_io_out_cs_0,
  output        auto_io_out_cs_1
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
`endif // RANDOMIZE_REG_INIT
  wire  buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
  wire [28:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
  wire [28:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
  wire  intsource_clock; // @[Crossing.scala 26:31]
  wire  intsource_reset; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_0; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_0; // @[Crossing.scala 26:31]
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  fifo_clock; // @[TLSPI.scala 69:20]
  wire  fifo_reset; // @[TLSPI.scala 69:20]
  wire [1:0] fifo_io_ctrl_fmt_proto; // @[TLSPI.scala 69:20]
  wire  fifo_io_ctrl_fmt_endian; // @[TLSPI.scala 69:20]
  wire  fifo_io_ctrl_fmt_iodir; // @[TLSPI.scala 69:20]
  wire [3:0] fifo_io_ctrl_fmt_len; // @[TLSPI.scala 69:20]
  wire [1:0] fifo_io_ctrl_cs_mode; // @[TLSPI.scala 69:20]
  wire [3:0] fifo_io_ctrl_wm_tx; // @[TLSPI.scala 69:20]
  wire [3:0] fifo_io_ctrl_wm_rx; // @[TLSPI.scala 69:20]
  wire  fifo_io_link_tx_ready; // @[TLSPI.scala 69:20]
  wire  fifo_io_link_tx_valid; // @[TLSPI.scala 69:20]
  wire [7:0] fifo_io_link_tx_bits; // @[TLSPI.scala 69:20]
  wire  fifo_io_link_rx_valid; // @[TLSPI.scala 69:20]
  wire [7:0] fifo_io_link_rx_bits; // @[TLSPI.scala 69:20]
  wire [7:0] fifo_io_link_cnt; // @[TLSPI.scala 69:20]
  wire [1:0] fifo_io_link_fmt_proto; // @[TLSPI.scala 69:20]
  wire  fifo_io_link_fmt_endian; // @[TLSPI.scala 69:20]
  wire  fifo_io_link_fmt_iodir; // @[TLSPI.scala 69:20]
  wire  fifo_io_link_cs_set; // @[TLSPI.scala 69:20]
  wire  fifo_io_link_cs_clear; // @[TLSPI.scala 69:20]
  wire  fifo_io_link_lock; // @[TLSPI.scala 69:20]
  wire  fifo_io_tx_ready; // @[TLSPI.scala 69:20]
  wire  fifo_io_tx_valid; // @[TLSPI.scala 69:20]
  wire [7:0] fifo_io_tx_bits; // @[TLSPI.scala 69:20]
  wire  fifo_io_rx_ready; // @[TLSPI.scala 69:20]
  wire  fifo_io_rx_valid; // @[TLSPI.scala 69:20]
  wire [7:0] fifo_io_rx_bits; // @[TLSPI.scala 69:20]
  wire  fifo_io_ip_txwm; // @[TLSPI.scala 69:20]
  wire  fifo_io_ip_rxwm; // @[TLSPI.scala 69:20]
  wire  mac_clock; // @[TLSPI.scala 70:19]
  wire  mac_reset; // @[TLSPI.scala 70:19]
  wire  mac_io_port_sck; // @[TLSPI.scala 70:19]
  wire  mac_io_port_dq_0_i; // @[TLSPI.scala 70:19]
  wire  mac_io_port_dq_0_o; // @[TLSPI.scala 70:19]
  wire  mac_io_port_dq_0_oe; // @[TLSPI.scala 70:19]
  wire  mac_io_port_dq_1_i; // @[TLSPI.scala 70:19]
  wire  mac_io_port_dq_1_o; // @[TLSPI.scala 70:19]
  wire  mac_io_port_dq_1_oe; // @[TLSPI.scala 70:19]
  wire  mac_io_port_dq_2_i; // @[TLSPI.scala 70:19]
  wire  mac_io_port_dq_2_o; // @[TLSPI.scala 70:19]
  wire  mac_io_port_dq_2_oe; // @[TLSPI.scala 70:19]
  wire  mac_io_port_dq_3_i; // @[TLSPI.scala 70:19]
  wire  mac_io_port_dq_3_o; // @[TLSPI.scala 70:19]
  wire  mac_io_port_dq_3_oe; // @[TLSPI.scala 70:19]
  wire  mac_io_port_cs_0; // @[TLSPI.scala 70:19]
  wire  mac_io_port_cs_1; // @[TLSPI.scala 70:19]
  wire [11:0] mac_io_ctrl_sck_div; // @[TLSPI.scala 70:19]
  wire  mac_io_ctrl_sck_pol; // @[TLSPI.scala 70:19]
  wire  mac_io_ctrl_sck_pha; // @[TLSPI.scala 70:19]
  wire [7:0] mac_io_ctrl_dla_cssck; // @[TLSPI.scala 70:19]
  wire [7:0] mac_io_ctrl_dla_sckcs; // @[TLSPI.scala 70:19]
  wire [7:0] mac_io_ctrl_dla_intercs; // @[TLSPI.scala 70:19]
  wire [7:0] mac_io_ctrl_dla_interxfr; // @[TLSPI.scala 70:19]
  wire  mac_io_ctrl_cs_id; // @[TLSPI.scala 70:19]
  wire  mac_io_ctrl_cs_dflt_0; // @[TLSPI.scala 70:19]
  wire  mac_io_ctrl_cs_dflt_1; // @[TLSPI.scala 70:19]
  wire [11:0] mac_io_ctrl_extradel_coarse; // @[TLSPI.scala 70:19]
  wire [4:0] mac_io_ctrl_sampledel_sd; // @[TLSPI.scala 70:19]
  wire  mac_io_link_tx_ready; // @[TLSPI.scala 70:19]
  wire  mac_io_link_tx_valid; // @[TLSPI.scala 70:19]
  wire [7:0] mac_io_link_tx_bits; // @[TLSPI.scala 70:19]
  wire  mac_io_link_rx_valid; // @[TLSPI.scala 70:19]
  wire [7:0] mac_io_link_rx_bits; // @[TLSPI.scala 70:19]
  wire [7:0] mac_io_link_cnt; // @[TLSPI.scala 70:19]
  wire [1:0] mac_io_link_fmt_proto; // @[TLSPI.scala 70:19]
  wire  mac_io_link_fmt_endian; // @[TLSPI.scala 70:19]
  wire  mac_io_link_fmt_iodir; // @[TLSPI.scala 70:19]
  wire  mac_io_link_cs_set; // @[TLSPI.scala 70:19]
  wire  mac_io_link_cs_clear; // @[TLSPI.scala 70:19]
  reg [1:0] ctrl_fmt_proto; // @[TLSPI.scala 68:17]
  reg  ctrl_fmt_endian; // @[TLSPI.scala 68:17]
  reg  ctrl_fmt_iodir; // @[TLSPI.scala 68:17]
  reg [3:0] ctrl_fmt_len; // @[TLSPI.scala 68:17]
  reg [11:0] ctrl_sck_div; // @[TLSPI.scala 68:17]
  reg  ctrl_sck_pol; // @[TLSPI.scala 68:17]
  reg  ctrl_sck_pha; // @[TLSPI.scala 68:17]
  reg  ctrl_cs_id; // @[TLSPI.scala 68:17]
  reg  ctrl_cs_dflt_0; // @[TLSPI.scala 68:17]
  reg  ctrl_cs_dflt_1; // @[TLSPI.scala 68:17]
  reg [1:0] ctrl_cs_mode; // @[TLSPI.scala 68:17]
  reg [7:0] ctrl_dla_cssck; // @[TLSPI.scala 68:17]
  reg [7:0] ctrl_dla_sckcs; // @[TLSPI.scala 68:17]
  reg [7:0] ctrl_dla_intercs; // @[TLSPI.scala 68:17]
  reg [7:0] ctrl_dla_interxfr; // @[TLSPI.scala 68:17]
  reg [3:0] ctrl_wm_tx; // @[TLSPI.scala 68:17]
  reg [3:0] ctrl_wm_rx; // @[TLSPI.scala 68:17]
  reg [11:0] ctrl_extradel_coarse; // @[TLSPI.scala 68:17]
  reg [4:0] ctrl_sampledel_sd; // @[TLSPI.scala 68:17]
  reg  ie_txwm; // @[TLSPI.scala 82:15]
  reg  ie_rxwm; // @[TLSPI.scala 82:15]
  wire  _T = ~fifo_io_tx_ready; // @[RegMapFIFO.scala 25:9]
  wire  _T_1 = ~fifo_io_rx_valid; // @[RegMapFIFO.scala 46:21]
  wire [2:0] bundleIn_0_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  in_bits_read = bundleIn_0_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 72:36]
  wire [28:0] bundleIn_0_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [9:0] in_bits_index = bundleIn_0_a_bits_address[11:2]; // @[RegisterRouter.scala 71:18 73:19]
  wire [9:0] out_findex = in_bits_index & 10'h3e0; // @[RegisterRouter.scala 83:24]
  wire  _out_T = out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [3:0] bundleIn_0_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [7:0] _out_frontMask_T_5 = bundleIn_0_a_bits_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_frontMask_T_7 = bundleIn_0_a_bits_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_frontMask_T_9 = bundleIn_0_a_bits_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_frontMask_T_11 = bundleIn_0_a_bits_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [31:0] out_frontMask = {_out_frontMask_T_11,_out_frontMask_T_9,_out_frontMask_T_7,_out_frontMask_T_5}; // @[Cat.scala 31:58]
  wire  out_wimask = &out_frontMask[11:0]; // @[RegisterRouter.scala 83:24]
  wire  bundleIn_0_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  bundleIn_0_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [4:0] out_oindex = {in_bits_index[4],in_bits_index[3],in_bits_index[2],in_bits_index[1],in_bits_index[0]}; // @[Cat.scala 31:58]
  wire [31:0] _out_frontSel_T = 32'h1 << out_oindex; // @[OneHot.scala 57:35]
  wire  out_frontSel_0 = _out_frontSel_T[0]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_0 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_0 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala 83:24]
  wire [31:0] bundleIn_0_a_bits_data = buffer_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  out_wimask_1 = &out_frontMask[0]; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_5 = _out_frontSel_T[5]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_1 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_5 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala 83:24]
  wire  _GEN_1 = out_f_wivalid_1 ? bundleIn_0_a_bits_data[0] : ctrl_cs_dflt_0; // @[RegField.scala 74:{88,92} TLSPI.scala 68:17]
  wire  out_wimask_2 = &out_frontMask[1]; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_2 = out_wivalid_1 & out_wimask_2; // @[RegisterRouter.scala 83:24]
  wire  _GEN_2 = out_f_wivalid_2 ? bundleIn_0_a_bits_data[1] : ctrl_cs_dflt_1; // @[RegField.scala 74:{88,92} TLSPI.scala 68:17]
  wire [1:0] out_prepend = {ctrl_cs_dflt_1,ctrl_cs_dflt_0}; // @[Cat.scala 31:58]
  wire  out_rimask_3 = |out_frontMask[7:0]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_3 = &out_frontMask[7:0]; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_10 = _out_frontSel_T[10]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_3 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_10 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_4 = &out_frontMask[23:16]; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_4 = out_wivalid_3 & out_wimask_4; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_prepend_T_1 = {{8'd0}, ctrl_dla_cssck}; // @[RegisterRouter.scala 83:24]
  wire [23:0] out_prepend_1 = {ctrl_dla_sckcs,_out_prepend_T_1}; // @[Cat.scala 31:58]
  wire  out_frontSel_14 = _out_frontSel_T[14]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_5 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_14 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_5 = out_wivalid_5 & out_wimask; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_6 = &out_frontMask[3:0]; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_20 = _out_frontSel_T[20]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_6 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_20 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala 83:24]
  wire  _out_T_116 = fifo_io_ip_txwm; // @[RegisterRouter.scala 83:24]
  wire [1:0] out_prepend_2 = {fifo_io_ip_rxwm,_out_T_116}; // @[Cat.scala 31:58]
  wire  out_frontSel_1 = _out_frontSel_T[1]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_9 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_1 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_9 = out_wivalid_9 & out_wimask_1; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_10 = out_wivalid_9 & out_wimask_2; // @[RegisterRouter.scala 83:24]
  wire [1:0] out_prepend_3 = {ctrl_sck_pol,ctrl_sck_pha}; // @[Cat.scala 31:58]
  wire  out_wimask_11 = &out_frontMask[1:0]; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_6 = _out_frontSel_T[6]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_11 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_6 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_11 = out_wivalid_11 & out_wimask_11; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_28 = _out_frontSel_T[28]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_12 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_28 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_12 = out_wivalid_12 & out_wimask_1; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_13 = out_wivalid_12 & out_wimask_2; // @[RegisterRouter.scala 83:24]
  wire [1:0] out_prepend_4 = {ie_rxwm,ie_txwm}; // @[Cat.scala 31:58]
  wire  out_frontSel_21 = _out_frontSel_T[21]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_14 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_21 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_14 = out_wivalid_14 & out_wimask_6; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_18 = _out_frontSel_T[18]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_15 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_18 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_15 = out_wivalid_15 & out_wimask_3; // @[RegisterRouter.scala 83:24]
  wire  out_womask_17 = &out_frontMask[31]; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_17 = out_wivalid_15 & out_womask_17; // @[RegisterRouter.scala 83:24]
  wire  quash = out_f_woready_17 & bundleIn_0_a_bits_data[31]; // @[RegMapFIFO.scala 27:26]
  wire [31:0] out_prepend_6 = {_T,31'h0}; // @[Cat.scala 31:58]
  wire  out_frontSel_16 = _out_frontSel_T[16]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_18 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_16 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_18 = out_wivalid_18 & out_wimask_11; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_19 = &out_frontMask[2]; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_19 = out_wivalid_18 & out_wimask_19; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_20 = &out_frontMask[3]; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_20 = out_wivalid_18 & out_wimask_20; // @[RegisterRouter.scala 83:24]
  wire [3:0] out_prepend_8 = {ctrl_fmt_iodir,ctrl_fmt_endian,ctrl_fmt_proto}; // @[Cat.scala 31:58]
  wire  out_wimask_21 = &out_frontMask[19:16]; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_21 = out_wivalid_18 & out_wimask_21; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_prepend_T_9 = {{12'd0}, out_prepend_8}; // @[RegisterRouter.scala 83:24]
  wire [19:0] out_prepend_9 = {ctrl_fmt_len,_out_prepend_T_9}; // @[Cat.scala 31:58]
  wire  out_frontSel_11 = _out_frontSel_T[11]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_22 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_11 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_22 = out_wivalid_22 & out_wimask_3; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_23 = out_wivalid_22 & out_wimask_4; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_prepend_T_10 = {{8'd0}, ctrl_dla_intercs}; // @[RegisterRouter.scala 83:24]
  wire [23:0] out_prepend_10 = {ctrl_dla_interxfr,_out_prepend_T_10}; // @[Cat.scala 31:58]
  wire  out_frontSel_19 = _out_frontSel_T[19]; // @[RegisterRouter.scala 83:24]
  wire  out_rivalid_24 = bundleIn_0_a_valid & bundleIn_0_d_ready & in_bits_read & out_frontSel_19 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [7:0] _out_T_293 = fifo_io_rx_bits; // @[RegisterRouter.scala 83:24]
  wire [8:0] out_prepend_11 = {1'h0,_out_T_293}; // @[Cat.scala 31:58]
  wire [30:0] _out_T_302 = {{22'd0}, out_prepend_11}; // @[RegisterRouter.scala 83:24]
  wire [31:0] out_prepend_12 = {_T_1,_out_T_302}; // @[Cat.scala 31:58]
  wire  out_frontSel_4 = _out_frontSel_T[4]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_27 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_4 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_27 = out_wivalid_27 & out_wimask_1; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_28 = &out_frontMask[4:0]; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_15 = _out_frontSel_T[15]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_28 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_15 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_28 = out_wivalid_28 & out_wimask_28; // @[RegisterRouter.scala 83:24]
  wire  _GEN_150 = 5'h1 == out_oindex ? _out_T : _out_T; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_153 = 5'h4 == out_oindex ? _out_T : 5'h3 == out_oindex | (5'h2 == out_oindex | _GEN_150); // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_154 = 5'h5 == out_oindex ? _out_T : _GEN_153; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_155 = 5'h6 == out_oindex ? _out_T : _GEN_154; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_159 = 5'ha == out_oindex ? _out_T : 5'h9 == out_oindex | (5'h8 == out_oindex | (5'h7 == out_oindex |
    _GEN_155)); // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_160 = 5'hb == out_oindex ? _out_T : _GEN_159; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_163 = 5'he == out_oindex ? _out_T : 5'hd == out_oindex | (5'hc == out_oindex | _GEN_160); // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_164 = 5'hf == out_oindex ? _out_T : _GEN_163; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_165 = 5'h10 == out_oindex ? _out_T : _GEN_164; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_167 = 5'h12 == out_oindex ? _out_T : 5'h11 == out_oindex | _GEN_165; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_168 = 5'h13 == out_oindex ? _out_T : _GEN_167; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_169 = 5'h14 == out_oindex ? _out_T : _GEN_168; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_170 = 5'h15 == out_oindex ? _out_T : _GEN_169; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_177 = 5'h1c == out_oindex ? _out_T : 5'h1b == out_oindex | (5'h1a == out_oindex | (5'h19 == out_oindex | (5'h18
     == out_oindex | (5'h17 == out_oindex | (5'h16 == out_oindex | _GEN_170))))); // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_178 = 5'h1d == out_oindex ? _out_T : _GEN_177; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_180 = 5'h1f == out_oindex | (5'h1e == out_oindex | _GEN_178); // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_0 = {{20'd0}, ctrl_sck_div}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _out_out_bits_data_WIRE_1_1 = {{30'd0}, out_prepend_3}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_182 = 5'h1 == out_oindex ? _out_out_bits_data_WIRE_1_1 : _out_out_bits_data_WIRE_1_0; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_183 = 5'h2 == out_oindex ? 32'h0 : _GEN_182; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_184 = 5'h3 == out_oindex ? 32'h0 : _GEN_183; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_4 = {{31'd0}, ctrl_cs_id}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_185 = 5'h4 == out_oindex ? _out_out_bits_data_WIRE_1_4 : _GEN_184; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_5 = {{30'd0}, out_prepend}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_186 = 5'h5 == out_oindex ? _out_out_bits_data_WIRE_1_5 : _GEN_185; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_6 = {{30'd0}, ctrl_cs_mode}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_187 = 5'h6 == out_oindex ? _out_out_bits_data_WIRE_1_6 : _GEN_186; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_188 = 5'h7 == out_oindex ? 32'h0 : _GEN_187; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_189 = 5'h8 == out_oindex ? 32'h0 : _GEN_188; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_190 = 5'h9 == out_oindex ? 32'h0 : _GEN_189; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_10 = {{8'd0}, out_prepend_1}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_191 = 5'ha == out_oindex ? _out_out_bits_data_WIRE_1_10 : _GEN_190; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_11 = {{8'd0}, out_prepend_10}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_192 = 5'hb == out_oindex ? _out_out_bits_data_WIRE_1_11 : _GEN_191; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_193 = 5'hc == out_oindex ? 32'h0 : _GEN_192; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_194 = 5'hd == out_oindex ? 32'h0 : _GEN_193; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_14 = {{20'd0}, ctrl_extradel_coarse}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_195 = 5'he == out_oindex ? _out_out_bits_data_WIRE_1_14 : _GEN_194; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_15 = {{27'd0}, ctrl_sampledel_sd}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_196 = 5'hf == out_oindex ? _out_out_bits_data_WIRE_1_15 : _GEN_195; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_16 = {{12'd0}, out_prepend_9}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_197 = 5'h10 == out_oindex ? _out_out_bits_data_WIRE_1_16 : _GEN_196; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_198 = 5'h11 == out_oindex ? 32'h0 : _GEN_197; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_199 = 5'h12 == out_oindex ? out_prepend_6 : _GEN_198; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_200 = 5'h13 == out_oindex ? out_prepend_12 : _GEN_199; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_20 = {{28'd0}, ctrl_wm_tx}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_201 = 5'h14 == out_oindex ? _out_out_bits_data_WIRE_1_20 : _GEN_200; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_21 = {{28'd0}, ctrl_wm_rx}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_202 = 5'h15 == out_oindex ? _out_out_bits_data_WIRE_1_21 : _GEN_201; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_203 = 5'h16 == out_oindex ? 32'h0 : _GEN_202; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_204 = 5'h17 == out_oindex ? 32'h0 : _GEN_203; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_205 = 5'h18 == out_oindex ? 32'h0 : _GEN_204; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_206 = 5'h19 == out_oindex ? 32'h0 : _GEN_205; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_207 = 5'h1a == out_oindex ? 32'h0 : _GEN_206; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_208 = 5'h1b == out_oindex ? 32'h0 : _GEN_207; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_28 = {{30'd0}, out_prepend_4}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_209 = 5'h1c == out_oindex ? _out_out_bits_data_WIRE_1_28 : _GEN_208; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_29 = {{30'd0}, out_prepend_2}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_210 = 5'h1d == out_oindex ? _out_out_bits_data_WIRE_1_29 : _GEN_209; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_211 = 5'h1e == out_oindex ? 32'h0 : _GEN_210; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_212 = 5'h1f == out_oindex ? 32'h0 : _GEN_211; // @[MuxLiteral.scala 48:{10,10}]
  TLBuffer_13 buffer ( // @[Buffer.scala 68:28]
    .auto_in_a_ready(buffer_auto_in_a_ready),
    .auto_in_a_valid(buffer_auto_in_a_valid),
    .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
    .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
    .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
    .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
    .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
    .auto_in_a_bits_data(buffer_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
    .auto_in_d_ready(buffer_auto_in_d_ready),
    .auto_in_d_valid(buffer_auto_in_d_valid),
    .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
    .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
    .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
    .auto_out_a_ready(buffer_auto_out_a_ready),
    .auto_out_a_valid(buffer_auto_out_a_valid),
    .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
    .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
    .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
    .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
    .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
    .auto_out_a_bits_data(buffer_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
    .auto_out_d_ready(buffer_auto_out_d_ready),
    .auto_out_d_valid(buffer_auto_out_d_valid),
    .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
    .auto_out_d_bits_source(buffer_auto_out_d_bits_source),
    .auto_out_d_bits_data(buffer_auto_out_d_bits_data)
  );
  IntSyncCrossingSource_1 intsource ( // @[Crossing.scala 26:31]
    .clock(intsource_clock),
    .reset(intsource_reset),
    .auto_in_0(intsource_auto_in_0),
    .auto_out_sync_0(intsource_auto_out_sync_0)
  );
  TLMonitor_65 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  SPIFIFO fifo ( // @[TLSPI.scala 69:20]
    .clock(fifo_clock),
    .reset(fifo_reset),
    .io_ctrl_fmt_proto(fifo_io_ctrl_fmt_proto),
    .io_ctrl_fmt_endian(fifo_io_ctrl_fmt_endian),
    .io_ctrl_fmt_iodir(fifo_io_ctrl_fmt_iodir),
    .io_ctrl_fmt_len(fifo_io_ctrl_fmt_len),
    .io_ctrl_cs_mode(fifo_io_ctrl_cs_mode),
    .io_ctrl_wm_tx(fifo_io_ctrl_wm_tx),
    .io_ctrl_wm_rx(fifo_io_ctrl_wm_rx),
    .io_link_tx_ready(fifo_io_link_tx_ready),
    .io_link_tx_valid(fifo_io_link_tx_valid),
    .io_link_tx_bits(fifo_io_link_tx_bits),
    .io_link_rx_valid(fifo_io_link_rx_valid),
    .io_link_rx_bits(fifo_io_link_rx_bits),
    .io_link_cnt(fifo_io_link_cnt),
    .io_link_fmt_proto(fifo_io_link_fmt_proto),
    .io_link_fmt_endian(fifo_io_link_fmt_endian),
    .io_link_fmt_iodir(fifo_io_link_fmt_iodir),
    .io_link_cs_set(fifo_io_link_cs_set),
    .io_link_cs_clear(fifo_io_link_cs_clear),
    .io_link_lock(fifo_io_link_lock),
    .io_tx_ready(fifo_io_tx_ready),
    .io_tx_valid(fifo_io_tx_valid),
    .io_tx_bits(fifo_io_tx_bits),
    .io_rx_ready(fifo_io_rx_ready),
    .io_rx_valid(fifo_io_rx_valid),
    .io_rx_bits(fifo_io_rx_bits),
    .io_ip_txwm(fifo_io_ip_txwm),
    .io_ip_rxwm(fifo_io_ip_rxwm)
  );
  SPIMedia_2 mac ( // @[TLSPI.scala 70:19]
    .clock(mac_clock),
    .reset(mac_reset),
    .io_port_sck(mac_io_port_sck),
    .io_port_dq_0_i(mac_io_port_dq_0_i),
    .io_port_dq_0_o(mac_io_port_dq_0_o),
    .io_port_dq_0_oe(mac_io_port_dq_0_oe),
    .io_port_dq_1_i(mac_io_port_dq_1_i),
    .io_port_dq_1_o(mac_io_port_dq_1_o),
    .io_port_dq_1_oe(mac_io_port_dq_1_oe),
    .io_port_dq_2_i(mac_io_port_dq_2_i),
    .io_port_dq_2_o(mac_io_port_dq_2_o),
    .io_port_dq_2_oe(mac_io_port_dq_2_oe),
    .io_port_dq_3_i(mac_io_port_dq_3_i),
    .io_port_dq_3_o(mac_io_port_dq_3_o),
    .io_port_dq_3_oe(mac_io_port_dq_3_oe),
    .io_port_cs_0(mac_io_port_cs_0),
    .io_port_cs_1(mac_io_port_cs_1),
    .io_ctrl_sck_div(mac_io_ctrl_sck_div),
    .io_ctrl_sck_pol(mac_io_ctrl_sck_pol),
    .io_ctrl_sck_pha(mac_io_ctrl_sck_pha),
    .io_ctrl_dla_cssck(mac_io_ctrl_dla_cssck),
    .io_ctrl_dla_sckcs(mac_io_ctrl_dla_sckcs),
    .io_ctrl_dla_intercs(mac_io_ctrl_dla_intercs),
    .io_ctrl_dla_interxfr(mac_io_ctrl_dla_interxfr),
    .io_ctrl_cs_id(mac_io_ctrl_cs_id),
    .io_ctrl_cs_dflt_0(mac_io_ctrl_cs_dflt_0),
    .io_ctrl_cs_dflt_1(mac_io_ctrl_cs_dflt_1),
    .io_ctrl_extradel_coarse(mac_io_ctrl_extradel_coarse),
    .io_ctrl_sampledel_sd(mac_io_ctrl_sampledel_sd),
    .io_link_tx_ready(mac_io_link_tx_ready),
    .io_link_tx_valid(mac_io_link_tx_valid),
    .io_link_tx_bits(mac_io_link_tx_bits),
    .io_link_rx_valid(mac_io_link_rx_valid),
    .io_link_rx_bits(mac_io_link_rx_bits),
    .io_link_cnt(mac_io_link_cnt),
    .io_link_fmt_proto(mac_io_link_fmt_proto),
    .io_link_fmt_endian(mac_io_link_fmt_endian),
    .io_link_fmt_iodir(mac_io_link_fmt_iodir),
    .io_link_cs_set(mac_io_link_cs_set),
    .io_link_cs_clear(mac_io_link_cs_clear)
  );
  assign auto_int_xing_out_sync_0 = intsource_auto_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_in_a_ready = buffer_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_valid = buffer_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_size = buffer_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_source = buffer_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_data = buffer_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_io_out_sck = mac_io_port_sck; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
  assign auto_io_out_dq_0_o = mac_io_port_dq_0_o; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
  assign auto_io_out_dq_0_oe = mac_io_port_dq_0_oe; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
  assign auto_io_out_dq_1_o = mac_io_port_dq_1_o; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
  assign auto_io_out_dq_1_oe = mac_io_port_dq_1_oe; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
  assign auto_io_out_dq_2_o = mac_io_port_dq_2_o; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
  assign auto_io_out_dq_2_oe = mac_io_port_dq_2_oe; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
  assign auto_io_out_dq_3_o = mac_io_port_dq_3_o; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
  assign auto_io_out_dq_3_oe = mac_io_port_dq_3_oe; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
  assign auto_io_out_cs_0 = mac_io_port_cs_0; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
  assign auto_io_out_cs_1 = mac_io_port_cs_1; // @[Nodes.scala 1207:84 TLSPI.scala 72:14]
  assign buffer_auto_in_a_valid = auto_control_xing_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_opcode = auto_control_xing_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_param = auto_control_xing_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_size = auto_control_xing_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_source = auto_control_xing_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_address = auto_control_xing_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_mask = auto_control_xing_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_data = auto_control_xing_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_corrupt = auto_control_xing_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_d_ready = auto_control_xing_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_out_a_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign buffer_auto_out_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_data = _GEN_180 ? _GEN_212 : 32'h0; // @[RegisterRouter.scala 83:24]
  assign intsource_clock = clock;
  assign intsource_reset = reset;
  assign intsource_auto_in_0 = fifo_io_ip_txwm & ie_txwm | fifo_io_ip_rxwm & ie_rxwm; // @[TLSPI.scala 84:47]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_param = buffer_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign monitor_io_in_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign fifo_clock = clock;
  assign fifo_reset = reset;
  assign fifo_io_ctrl_fmt_proto = ctrl_fmt_proto; // @[TLSPI.scala 73:20]
  assign fifo_io_ctrl_fmt_endian = ctrl_fmt_endian; // @[TLSPI.scala 73:20]
  assign fifo_io_ctrl_fmt_iodir = ctrl_fmt_iodir; // @[TLSPI.scala 73:20]
  assign fifo_io_ctrl_fmt_len = ctrl_fmt_len; // @[TLSPI.scala 73:20]
  assign fifo_io_ctrl_cs_mode = ctrl_cs_mode; // @[TLSPI.scala 74:19]
  assign fifo_io_ctrl_wm_tx = ctrl_wm_tx; // @[TLSPI.scala 75:19]
  assign fifo_io_ctrl_wm_rx = ctrl_wm_rx; // @[TLSPI.scala 75:19]
  assign fifo_io_link_tx_ready = mac_io_link_tx_ready; // @[TLSPI.scala 196:17]
  assign fifo_io_link_rx_valid = mac_io_link_rx_valid; // @[TLSPI.scala 196:17]
  assign fifo_io_link_rx_bits = mac_io_link_rx_bits; // @[TLSPI.scala 196:17]
  assign fifo_io_tx_valid = out_f_wivalid_15 & ~quash; // @[RegMapFIFO.scala 19:30]
  assign fifo_io_tx_bits = bundleIn_0_a_bits_data[7:0]; // @[RegisterRouter.scala 83:24]
  assign fifo_io_rx_ready = out_rivalid_24 & out_rimask_3; // @[RegisterRouter.scala 83:24]
  assign mac_clock = clock;
  assign mac_reset = reset;
  assign mac_io_port_dq_0_i = auto_io_out_dq_0_i; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign mac_io_port_dq_1_i = auto_io_out_dq_1_i; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign mac_io_port_dq_2_i = auto_io_out_dq_2_i; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign mac_io_port_dq_3_i = auto_io_out_dq_3_i; // @[Nodes.scala 1207:84 LazyModule.scala 311:12]
  assign mac_io_ctrl_sck_div = ctrl_sck_div; // @[TLSPI.scala 76:19]
  assign mac_io_ctrl_sck_pol = ctrl_sck_pol; // @[TLSPI.scala 76:19]
  assign mac_io_ctrl_sck_pha = ctrl_sck_pha; // @[TLSPI.scala 76:19]
  assign mac_io_ctrl_dla_cssck = ctrl_dla_cssck; // @[TLSPI.scala 79:19]
  assign mac_io_ctrl_dla_sckcs = ctrl_dla_sckcs; // @[TLSPI.scala 79:19]
  assign mac_io_ctrl_dla_intercs = ctrl_dla_intercs; // @[TLSPI.scala 79:19]
  assign mac_io_ctrl_dla_interxfr = ctrl_dla_interxfr; // @[TLSPI.scala 79:19]
  assign mac_io_ctrl_cs_id = ctrl_cs_id; // @[TLSPI.scala 80:18]
  assign mac_io_ctrl_cs_dflt_0 = ctrl_cs_dflt_0; // @[TLSPI.scala 80:18]
  assign mac_io_ctrl_cs_dflt_1 = ctrl_cs_dflt_1; // @[TLSPI.scala 80:18]
  assign mac_io_ctrl_extradel_coarse = ctrl_extradel_coarse; // @[TLSPI.scala 77:24]
  assign mac_io_ctrl_sampledel_sd = ctrl_sampledel_sd; // @[TLSPI.scala 78:25]
  assign mac_io_link_tx_valid = fifo_io_link_tx_valid; // @[TLSPI.scala 196:17]
  assign mac_io_link_tx_bits = fifo_io_link_tx_bits; // @[TLSPI.scala 196:17]
  assign mac_io_link_cnt = fifo_io_link_cnt; // @[TLSPI.scala 196:17]
  assign mac_io_link_fmt_proto = fifo_io_link_fmt_proto; // @[TLSPI.scala 196:17]
  assign mac_io_link_fmt_endian = fifo_io_link_fmt_endian; // @[TLSPI.scala 196:17]
  assign mac_io_link_fmt_iodir = fifo_io_link_fmt_iodir; // @[TLSPI.scala 196:17]
  assign mac_io_link_cs_set = fifo_io_link_cs_set; // @[TLSPI.scala 196:17]
  assign mac_io_link_cs_clear = fifo_io_link_cs_clear; // @[TLSPI.scala 196:17]
  always @(posedge clock) begin
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_fmt_proto <= 2'h0; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_18) begin // @[RegField.scala 74:88]
      ctrl_fmt_proto <= bundleIn_0_a_bits_data[1:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_fmt_endian <= 1'h0; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_19) begin // @[RegField.scala 74:88]
      ctrl_fmt_endian <= bundleIn_0_a_bits_data[2]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_fmt_iodir <= 1'h0; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_20) begin // @[RegField.scala 74:88]
      ctrl_fmt_iodir <= bundleIn_0_a_bits_data[3]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_fmt_len <= 4'h8; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_21) begin // @[RegField.scala 74:88]
      ctrl_fmt_len <= bundleIn_0_a_bits_data[19:16]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_sck_div <= 12'h3; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid) begin // @[RegField.scala 74:88]
      ctrl_sck_div <= bundleIn_0_a_bits_data[11:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_sck_pol <= 1'h0; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_10) begin // @[RegField.scala 74:88]
      ctrl_sck_pol <= bundleIn_0_a_bits_data[1]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_sck_pha <= 1'h0; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_9) begin // @[RegField.scala 74:88]
      ctrl_sck_pha <= bundleIn_0_a_bits_data[0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_cs_id <= 1'h0; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_27) begin // @[RegField.scala 74:88]
      ctrl_cs_id <= bundleIn_0_a_bits_data[0]; // @[RegField.scala 74:92]
    end
    ctrl_cs_dflt_0 <= reset | _GEN_1; // @[TLSPI.scala 68:{17,17}]
    ctrl_cs_dflt_1 <= reset | _GEN_2; // @[TLSPI.scala 68:{17,17}]
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_cs_mode <= 2'h0; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_11) begin // @[RegField.scala 74:88]
      ctrl_cs_mode <= bundleIn_0_a_bits_data[1:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_dla_cssck <= 8'h1; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_3) begin // @[RegField.scala 74:88]
      ctrl_dla_cssck <= bundleIn_0_a_bits_data[7:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_dla_sckcs <= 8'h1; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_4) begin // @[RegField.scala 74:88]
      ctrl_dla_sckcs <= bundleIn_0_a_bits_data[23:16]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_dla_intercs <= 8'h1; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_22) begin // @[RegField.scala 74:88]
      ctrl_dla_intercs <= bundleIn_0_a_bits_data[7:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_dla_interxfr <= 8'h0; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_23) begin // @[RegField.scala 74:88]
      ctrl_dla_interxfr <= bundleIn_0_a_bits_data[23:16]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_wm_tx <= 4'h0; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_6) begin // @[RegField.scala 74:88]
      ctrl_wm_tx <= bundleIn_0_a_bits_data[3:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_wm_rx <= 4'h0; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_14) begin // @[RegField.scala 74:88]
      ctrl_wm_rx <= bundleIn_0_a_bits_data[3:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_extradel_coarse <= 12'h0; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_5) begin // @[RegField.scala 74:88]
      ctrl_extradel_coarse <= bundleIn_0_a_bits_data[11:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 68:17]
      ctrl_sampledel_sd <= 5'h3; // @[TLSPI.scala 68:17]
    end else if (out_f_wivalid_28) begin // @[RegField.scala 74:88]
      ctrl_sampledel_sd <= bundleIn_0_a_bits_data[4:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 82:15]
      ie_txwm <= 1'h0; // @[TLSPI.scala 82:15]
    end else if (out_f_wivalid_12) begin // @[RegField.scala 74:88]
      ie_txwm <= bundleIn_0_a_bits_data[0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[TLSPI.scala 82:15]
      ie_rxwm <= 1'h0; // @[TLSPI.scala 82:15]
    end else if (out_f_wivalid_13) begin // @[RegField.scala 74:88]
      ie_rxwm <= bundleIn_0_a_bits_data[1]; // @[RegField.scala 74:92]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  ctrl_fmt_proto = _RAND_0[1:0];
  _RAND_1 = {1{`RANDOM}};
  ctrl_fmt_endian = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  ctrl_fmt_iodir = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  ctrl_fmt_len = _RAND_3[3:0];
  _RAND_4 = {1{`RANDOM}};
  ctrl_sck_div = _RAND_4[11:0];
  _RAND_5 = {1{`RANDOM}};
  ctrl_sck_pol = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  ctrl_sck_pha = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  ctrl_cs_id = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  ctrl_cs_dflt_0 = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  ctrl_cs_dflt_1 = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  ctrl_cs_mode = _RAND_10[1:0];
  _RAND_11 = {1{`RANDOM}};
  ctrl_dla_cssck = _RAND_11[7:0];
  _RAND_12 = {1{`RANDOM}};
  ctrl_dla_sckcs = _RAND_12[7:0];
  _RAND_13 = {1{`RANDOM}};
  ctrl_dla_intercs = _RAND_13[7:0];
  _RAND_14 = {1{`RANDOM}};
  ctrl_dla_interxfr = _RAND_14[7:0];
  _RAND_15 = {1{`RANDOM}};
  ctrl_wm_tx = _RAND_15[3:0];
  _RAND_16 = {1{`RANDOM}};
  ctrl_wm_rx = _RAND_16[3:0];
  _RAND_17 = {1{`RANDOM}};
  ctrl_extradel_coarse = _RAND_17[11:0];
  _RAND_18 = {1{`RANDOM}};
  ctrl_sampledel_sd = _RAND_18[4:0];
  _RAND_19 = {1{`RANDOM}};
  ie_txwm = _RAND_19[0:0];
  _RAND_20 = {1{`RANDOM}};
  ie_rxwm = _RAND_20[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ClockSinkDomain_8(
  output        auto_spi_0_int_xing_out_sync_0,
  output        auto_spi_0_control_xing_in_a_ready,
  input         auto_spi_0_control_xing_in_a_valid,
  input  [2:0]  auto_spi_0_control_xing_in_a_bits_opcode,
  input  [2:0]  auto_spi_0_control_xing_in_a_bits_param,
  input  [1:0]  auto_spi_0_control_xing_in_a_bits_size,
  input  [6:0]  auto_spi_0_control_xing_in_a_bits_source,
  input  [28:0] auto_spi_0_control_xing_in_a_bits_address,
  input  [3:0]  auto_spi_0_control_xing_in_a_bits_mask,
  input  [31:0] auto_spi_0_control_xing_in_a_bits_data,
  input         auto_spi_0_control_xing_in_a_bits_corrupt,
  input         auto_spi_0_control_xing_in_d_ready,
  output        auto_spi_0_control_xing_in_d_valid,
  output [2:0]  auto_spi_0_control_xing_in_d_bits_opcode,
  output [1:0]  auto_spi_0_control_xing_in_d_bits_size,
  output [6:0]  auto_spi_0_control_xing_in_d_bits_source,
  output [31:0] auto_spi_0_control_xing_in_d_bits_data,
  output        auto_spi_0_io_out_sck,
  input         auto_spi_0_io_out_dq_0_i,
  output        auto_spi_0_io_out_dq_0_o,
  output        auto_spi_0_io_out_dq_0_oe,
  input         auto_spi_0_io_out_dq_1_i,
  output        auto_spi_0_io_out_dq_1_o,
  output        auto_spi_0_io_out_dq_1_oe,
  input         auto_spi_0_io_out_dq_2_i,
  output        auto_spi_0_io_out_dq_2_o,
  output        auto_spi_0_io_out_dq_2_oe,
  input         auto_spi_0_io_out_dq_3_i,
  output        auto_spi_0_io_out_dq_3_o,
  output        auto_spi_0_io_out_dq_3_oe,
  output        auto_spi_0_io_out_cs_0,
  output        auto_spi_0_io_out_cs_1,
  input         auto_clock_in_clock,
  input         auto_clock_in_reset
);
  wire  spi_0_clock; // @[SPI.scala 36:49]
  wire  spi_0_reset; // @[SPI.scala 36:49]
  wire  spi_0_auto_int_xing_out_sync_0; // @[SPI.scala 36:49]
  wire  spi_0_auto_control_xing_in_a_ready; // @[SPI.scala 36:49]
  wire  spi_0_auto_control_xing_in_a_valid; // @[SPI.scala 36:49]
  wire [2:0] spi_0_auto_control_xing_in_a_bits_opcode; // @[SPI.scala 36:49]
  wire [2:0] spi_0_auto_control_xing_in_a_bits_param; // @[SPI.scala 36:49]
  wire [1:0] spi_0_auto_control_xing_in_a_bits_size; // @[SPI.scala 36:49]
  wire [6:0] spi_0_auto_control_xing_in_a_bits_source; // @[SPI.scala 36:49]
  wire [28:0] spi_0_auto_control_xing_in_a_bits_address; // @[SPI.scala 36:49]
  wire [3:0] spi_0_auto_control_xing_in_a_bits_mask; // @[SPI.scala 36:49]
  wire [31:0] spi_0_auto_control_xing_in_a_bits_data; // @[SPI.scala 36:49]
  wire  spi_0_auto_control_xing_in_a_bits_corrupt; // @[SPI.scala 36:49]
  wire  spi_0_auto_control_xing_in_d_ready; // @[SPI.scala 36:49]
  wire  spi_0_auto_control_xing_in_d_valid; // @[SPI.scala 36:49]
  wire [2:0] spi_0_auto_control_xing_in_d_bits_opcode; // @[SPI.scala 36:49]
  wire [1:0] spi_0_auto_control_xing_in_d_bits_size; // @[SPI.scala 36:49]
  wire [6:0] spi_0_auto_control_xing_in_d_bits_source; // @[SPI.scala 36:49]
  wire [31:0] spi_0_auto_control_xing_in_d_bits_data; // @[SPI.scala 36:49]
  wire  spi_0_auto_io_out_sck; // @[SPI.scala 36:49]
  wire  spi_0_auto_io_out_dq_0_i; // @[SPI.scala 36:49]
  wire  spi_0_auto_io_out_dq_0_o; // @[SPI.scala 36:49]
  wire  spi_0_auto_io_out_dq_0_oe; // @[SPI.scala 36:49]
  wire  spi_0_auto_io_out_dq_1_i; // @[SPI.scala 36:49]
  wire  spi_0_auto_io_out_dq_1_o; // @[SPI.scala 36:49]
  wire  spi_0_auto_io_out_dq_1_oe; // @[SPI.scala 36:49]
  wire  spi_0_auto_io_out_dq_2_i; // @[SPI.scala 36:49]
  wire  spi_0_auto_io_out_dq_2_o; // @[SPI.scala 36:49]
  wire  spi_0_auto_io_out_dq_2_oe; // @[SPI.scala 36:49]
  wire  spi_0_auto_io_out_dq_3_i; // @[SPI.scala 36:49]
  wire  spi_0_auto_io_out_dq_3_o; // @[SPI.scala 36:49]
  wire  spi_0_auto_io_out_dq_3_oe; // @[SPI.scala 36:49]
  wire  spi_0_auto_io_out_cs_0; // @[SPI.scala 36:49]
  wire  spi_0_auto_io_out_cs_1; // @[SPI.scala 36:49]
  TLSPI spi_0 ( // @[SPI.scala 36:49]
    .clock(spi_0_clock),
    .reset(spi_0_reset),
    .auto_int_xing_out_sync_0(spi_0_auto_int_xing_out_sync_0),
    .auto_control_xing_in_a_ready(spi_0_auto_control_xing_in_a_ready),
    .auto_control_xing_in_a_valid(spi_0_auto_control_xing_in_a_valid),
    .auto_control_xing_in_a_bits_opcode(spi_0_auto_control_xing_in_a_bits_opcode),
    .auto_control_xing_in_a_bits_param(spi_0_auto_control_xing_in_a_bits_param),
    .auto_control_xing_in_a_bits_size(spi_0_auto_control_xing_in_a_bits_size),
    .auto_control_xing_in_a_bits_source(spi_0_auto_control_xing_in_a_bits_source),
    .auto_control_xing_in_a_bits_address(spi_0_auto_control_xing_in_a_bits_address),
    .auto_control_xing_in_a_bits_mask(spi_0_auto_control_xing_in_a_bits_mask),
    .auto_control_xing_in_a_bits_data(spi_0_auto_control_xing_in_a_bits_data),
    .auto_control_xing_in_a_bits_corrupt(spi_0_auto_control_xing_in_a_bits_corrupt),
    .auto_control_xing_in_d_ready(spi_0_auto_control_xing_in_d_ready),
    .auto_control_xing_in_d_valid(spi_0_auto_control_xing_in_d_valid),
    .auto_control_xing_in_d_bits_opcode(spi_0_auto_control_xing_in_d_bits_opcode),
    .auto_control_xing_in_d_bits_size(spi_0_auto_control_xing_in_d_bits_size),
    .auto_control_xing_in_d_bits_source(spi_0_auto_control_xing_in_d_bits_source),
    .auto_control_xing_in_d_bits_data(spi_0_auto_control_xing_in_d_bits_data),
    .auto_io_out_sck(spi_0_auto_io_out_sck),
    .auto_io_out_dq_0_i(spi_0_auto_io_out_dq_0_i),
    .auto_io_out_dq_0_o(spi_0_auto_io_out_dq_0_o),
    .auto_io_out_dq_0_oe(spi_0_auto_io_out_dq_0_oe),
    .auto_io_out_dq_1_i(spi_0_auto_io_out_dq_1_i),
    .auto_io_out_dq_1_o(spi_0_auto_io_out_dq_1_o),
    .auto_io_out_dq_1_oe(spi_0_auto_io_out_dq_1_oe),
    .auto_io_out_dq_2_i(spi_0_auto_io_out_dq_2_i),
    .auto_io_out_dq_2_o(spi_0_auto_io_out_dq_2_o),
    .auto_io_out_dq_2_oe(spi_0_auto_io_out_dq_2_oe),
    .auto_io_out_dq_3_i(spi_0_auto_io_out_dq_3_i),
    .auto_io_out_dq_3_o(spi_0_auto_io_out_dq_3_o),
    .auto_io_out_dq_3_oe(spi_0_auto_io_out_dq_3_oe),
    .auto_io_out_cs_0(spi_0_auto_io_out_cs_0),
    .auto_io_out_cs_1(spi_0_auto_io_out_cs_1)
  );
  assign auto_spi_0_int_xing_out_sync_0 = spi_0_auto_int_xing_out_sync_0; // @[LazyModule.scala 311:12]
  assign auto_spi_0_control_xing_in_a_ready = spi_0_auto_control_xing_in_a_ready; // @[LazyModule.scala 309:16]
  assign auto_spi_0_control_xing_in_d_valid = spi_0_auto_control_xing_in_d_valid; // @[LazyModule.scala 309:16]
  assign auto_spi_0_control_xing_in_d_bits_opcode = spi_0_auto_control_xing_in_d_bits_opcode; // @[LazyModule.scala 309:16]
  assign auto_spi_0_control_xing_in_d_bits_size = spi_0_auto_control_xing_in_d_bits_size; // @[LazyModule.scala 309:16]
  assign auto_spi_0_control_xing_in_d_bits_source = spi_0_auto_control_xing_in_d_bits_source; // @[LazyModule.scala 309:16]
  assign auto_spi_0_control_xing_in_d_bits_data = spi_0_auto_control_xing_in_d_bits_data; // @[LazyModule.scala 309:16]
  assign auto_spi_0_io_out_sck = spi_0_auto_io_out_sck; // @[LazyModule.scala 311:12]
  assign auto_spi_0_io_out_dq_0_o = spi_0_auto_io_out_dq_0_o; // @[LazyModule.scala 311:12]
  assign auto_spi_0_io_out_dq_0_oe = spi_0_auto_io_out_dq_0_oe; // @[LazyModule.scala 311:12]
  assign auto_spi_0_io_out_dq_1_o = spi_0_auto_io_out_dq_1_o; // @[LazyModule.scala 311:12]
  assign auto_spi_0_io_out_dq_1_oe = spi_0_auto_io_out_dq_1_oe; // @[LazyModule.scala 311:12]
  assign auto_spi_0_io_out_dq_2_o = spi_0_auto_io_out_dq_2_o; // @[LazyModule.scala 311:12]
  assign auto_spi_0_io_out_dq_2_oe = spi_0_auto_io_out_dq_2_oe; // @[LazyModule.scala 311:12]
  assign auto_spi_0_io_out_dq_3_o = spi_0_auto_io_out_dq_3_o; // @[LazyModule.scala 311:12]
  assign auto_spi_0_io_out_dq_3_oe = spi_0_auto_io_out_dq_3_oe; // @[LazyModule.scala 311:12]
  assign auto_spi_0_io_out_cs_0 = spi_0_auto_io_out_cs_0; // @[LazyModule.scala 311:12]
  assign auto_spi_0_io_out_cs_1 = spi_0_auto_io_out_cs_1; // @[LazyModule.scala 311:12]
  assign spi_0_clock = auto_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign spi_0_reset = auto_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign spi_0_auto_control_xing_in_a_valid = auto_spi_0_control_xing_in_a_valid; // @[LazyModule.scala 309:16]
  assign spi_0_auto_control_xing_in_a_bits_opcode = auto_spi_0_control_xing_in_a_bits_opcode; // @[LazyModule.scala 309:16]
  assign spi_0_auto_control_xing_in_a_bits_param = auto_spi_0_control_xing_in_a_bits_param; // @[LazyModule.scala 309:16]
  assign spi_0_auto_control_xing_in_a_bits_size = auto_spi_0_control_xing_in_a_bits_size; // @[LazyModule.scala 309:16]
  assign spi_0_auto_control_xing_in_a_bits_source = auto_spi_0_control_xing_in_a_bits_source; // @[LazyModule.scala 309:16]
  assign spi_0_auto_control_xing_in_a_bits_address = auto_spi_0_control_xing_in_a_bits_address; // @[LazyModule.scala 309:16]
  assign spi_0_auto_control_xing_in_a_bits_mask = auto_spi_0_control_xing_in_a_bits_mask; // @[LazyModule.scala 309:16]
  assign spi_0_auto_control_xing_in_a_bits_data = auto_spi_0_control_xing_in_a_bits_data; // @[LazyModule.scala 309:16]
  assign spi_0_auto_control_xing_in_a_bits_corrupt = auto_spi_0_control_xing_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
  assign spi_0_auto_control_xing_in_d_ready = auto_spi_0_control_xing_in_d_ready; // @[LazyModule.scala 309:16]
  assign spi_0_auto_io_out_dq_0_i = auto_spi_0_io_out_dq_0_i; // @[LazyModule.scala 311:12]
  assign spi_0_auto_io_out_dq_1_i = auto_spi_0_io_out_dq_1_i; // @[LazyModule.scala 311:12]
  assign spi_0_auto_io_out_dq_2_i = auto_spi_0_io_out_dq_2_i; // @[LazyModule.scala 311:12]
  assign spi_0_auto_io_out_dq_3_i = auto_spi_0_io_out_dq_3_i; // @[LazyModule.scala 311:12]
endmodule
module AsyncResetRegVec_w32_i0(
  input         clock,
  input         reset,
  input  [31:0] io_d,
  output [31:0] io_q,
  input         io_en
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg [31:0] reg_; // @[AsyncResetReg.scala 64:50]
  assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[AsyncResetReg.scala 65:16]
      reg_ <= 32'h0; // @[AsyncResetReg.scala 66:9]
    end else if (io_en) begin // @[AsyncResetReg.scala 64:50]
      reg_ <= io_d;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  reg_ = _RAND_0[31:0];
`endif // RANDOMIZE_REG_INIT
  if (reset) begin
    reg_ = 32'h0;
  end
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module IntSyncCrossingSource_17(
  input   clock,
  input   reset,
  input   auto_in_0,
  input   auto_in_1,
  input   auto_in_2,
  input   auto_in_3,
  input   auto_in_4,
  input   auto_in_5,
  input   auto_in_6,
  input   auto_in_7,
  input   auto_in_8,
  input   auto_in_9,
  input   auto_in_10,
  input   auto_in_11,
  input   auto_in_12,
  input   auto_in_13,
  input   auto_in_14,
  input   auto_in_15,
  input   auto_in_16,
  input   auto_in_17,
  input   auto_in_18,
  input   auto_in_19,
  input   auto_in_20,
  input   auto_in_21,
  input   auto_in_22,
  input   auto_in_23,
  input   auto_in_24,
  input   auto_in_25,
  input   auto_in_26,
  input   auto_in_27,
  input   auto_in_28,
  input   auto_in_29,
  input   auto_in_30,
  input   auto_in_31,
  output  auto_out_sync_0,
  output  auto_out_sync_1,
  output  auto_out_sync_2,
  output  auto_out_sync_3,
  output  auto_out_sync_4,
  output  auto_out_sync_5,
  output  auto_out_sync_6,
  output  auto_out_sync_7,
  output  auto_out_sync_8,
  output  auto_out_sync_9,
  output  auto_out_sync_10,
  output  auto_out_sync_11,
  output  auto_out_sync_12,
  output  auto_out_sync_13,
  output  auto_out_sync_14,
  output  auto_out_sync_15,
  output  auto_out_sync_16,
  output  auto_out_sync_17,
  output  auto_out_sync_18,
  output  auto_out_sync_19,
  output  auto_out_sync_20,
  output  auto_out_sync_21,
  output  auto_out_sync_22,
  output  auto_out_sync_23,
  output  auto_out_sync_24,
  output  auto_out_sync_25,
  output  auto_out_sync_26,
  output  auto_out_sync_27,
  output  auto_out_sync_28,
  output  auto_out_sync_29,
  output  auto_out_sync_30,
  output  auto_out_sync_31
);
  wire  reg__clock; // @[AsyncResetReg.scala 89:21]
  wire  reg__reset; // @[AsyncResetReg.scala 89:21]
  wire [31:0] reg__io_d; // @[AsyncResetReg.scala 89:21]
  wire [31:0] reg__io_q; // @[AsyncResetReg.scala 89:21]
  wire  reg__io_en; // @[AsyncResetReg.scala 89:21]
  wire [7:0] lo_lo = {auto_in_7,auto_in_6,auto_in_5,auto_in_4,auto_in_3,auto_in_2,auto_in_1,auto_in_0}; // @[Cat.scala 31:58]
  wire [15:0] lo = {auto_in_15,auto_in_14,auto_in_13,auto_in_12,auto_in_11,auto_in_10,auto_in_9,auto_in_8,lo_lo}; // @[Cat.scala 31:58]
  wire [7:0] hi_lo = {auto_in_23,auto_in_22,auto_in_21,auto_in_20,auto_in_19,auto_in_18,auto_in_17,auto_in_16}; // @[Cat.scala 31:58]
  wire [15:0] hi = {auto_in_31,auto_in_30,auto_in_29,auto_in_28,auto_in_27,auto_in_26,auto_in_25,auto_in_24,hi_lo}; // @[Cat.scala 31:58]
  AsyncResetRegVec_w32_i0 reg_ ( // @[AsyncResetReg.scala 89:21]
    .clock(reg__clock),
    .reset(reg__reset),
    .io_d(reg__io_d),
    .io_q(reg__io_q),
    .io_en(reg__io_en)
  );
  assign auto_out_sync_0 = reg__io_q[0]; // @[Crossing.scala 41:52]
  assign auto_out_sync_1 = reg__io_q[1]; // @[Crossing.scala 41:52]
  assign auto_out_sync_2 = reg__io_q[2]; // @[Crossing.scala 41:52]
  assign auto_out_sync_3 = reg__io_q[3]; // @[Crossing.scala 41:52]
  assign auto_out_sync_4 = reg__io_q[4]; // @[Crossing.scala 41:52]
  assign auto_out_sync_5 = reg__io_q[5]; // @[Crossing.scala 41:52]
  assign auto_out_sync_6 = reg__io_q[6]; // @[Crossing.scala 41:52]
  assign auto_out_sync_7 = reg__io_q[7]; // @[Crossing.scala 41:52]
  assign auto_out_sync_8 = reg__io_q[8]; // @[Crossing.scala 41:52]
  assign auto_out_sync_9 = reg__io_q[9]; // @[Crossing.scala 41:52]
  assign auto_out_sync_10 = reg__io_q[10]; // @[Crossing.scala 41:52]
  assign auto_out_sync_11 = reg__io_q[11]; // @[Crossing.scala 41:52]
  assign auto_out_sync_12 = reg__io_q[12]; // @[Crossing.scala 41:52]
  assign auto_out_sync_13 = reg__io_q[13]; // @[Crossing.scala 41:52]
  assign auto_out_sync_14 = reg__io_q[14]; // @[Crossing.scala 41:52]
  assign auto_out_sync_15 = reg__io_q[15]; // @[Crossing.scala 41:52]
  assign auto_out_sync_16 = reg__io_q[16]; // @[Crossing.scala 41:52]
  assign auto_out_sync_17 = reg__io_q[17]; // @[Crossing.scala 41:52]
  assign auto_out_sync_18 = reg__io_q[18]; // @[Crossing.scala 41:52]
  assign auto_out_sync_19 = reg__io_q[19]; // @[Crossing.scala 41:52]
  assign auto_out_sync_20 = reg__io_q[20]; // @[Crossing.scala 41:52]
  assign auto_out_sync_21 = reg__io_q[21]; // @[Crossing.scala 41:52]
  assign auto_out_sync_22 = reg__io_q[22]; // @[Crossing.scala 41:52]
  assign auto_out_sync_23 = reg__io_q[23]; // @[Crossing.scala 41:52]
  assign auto_out_sync_24 = reg__io_q[24]; // @[Crossing.scala 41:52]
  assign auto_out_sync_25 = reg__io_q[25]; // @[Crossing.scala 41:52]
  assign auto_out_sync_26 = reg__io_q[26]; // @[Crossing.scala 41:52]
  assign auto_out_sync_27 = reg__io_q[27]; // @[Crossing.scala 41:52]
  assign auto_out_sync_28 = reg__io_q[28]; // @[Crossing.scala 41:52]
  assign auto_out_sync_29 = reg__io_q[29]; // @[Crossing.scala 41:52]
  assign auto_out_sync_30 = reg__io_q[30]; // @[Crossing.scala 41:52]
  assign auto_out_sync_31 = reg__io_q[31]; // @[Crossing.scala 41:52]
  assign reg__clock = clock;
  assign reg__reset = reset;
  assign reg__io_d = {hi,lo}; // @[Cat.scala 31:58]
  assign reg__io_en = 1'h1; // @[AsyncResetReg.scala 92:15]
endmodule
module TLMonitor_66(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [1:0]  io_in_a_bits_size,
  input  [6:0]  io_in_a_bits_source,
  input  [28:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_size,
  input  [6:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [95:0] _RAND_10;
  reg [383:0] _RAND_11;
  reg [383:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [95:0] _RAND_16;
  reg [383:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T_4 = io_in_a_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire [4:0] _is_aligned_mask_T_1 = 5'h3 << io_in_a_bits_size; // @[package.scala 234:77]
  wire [1:0] is_aligned_mask = ~_is_aligned_mask_T_1[1:0]; // @[package.scala 234:46]
  wire [28:0] _GEN_71 = {{27'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 2'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [28:0] _T_33 = io_in_a_bits_address ^ 29'h10012000; // @[Parameters.scala 137:31]
  wire [29:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
  wire [29:0] _T_36 = $signed(_T_34) & -30'sh1000; // @[Parameters.scala 137:52]
  wire  _T_37 = $signed(_T_36) == 30'sh0; // @[Parameters.scala 137:67]
  wire  _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_74 = _T_73 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_164 = io_in_a_bits_size <= 2'h2; // @[Parameters.scala 92:42]
  wire  _T_172 = _T_164 & _T_37; // @[Parameters.scala 670:56]
  wire  _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_218 = _source_ok_T_4 & _T_172; // @[Monitor.scala 115:71]
  wire  _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_273 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_274 = io_in_a_bits_mask & _T_273; // @[Monitor.scala 127:31]
  wire  _T_275 = _T_274 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_279 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_347 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_355 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_385 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_397 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_10 = io_in_d_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire  _T_401 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_405 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 312:27]
  wire  _T_421 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_449 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_478 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_495 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_513 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [1:0] size; // @[Monitor.scala 386:22]
  reg [6:0] source; // @[Monitor.scala 387:22]
  reg [28:0] address; // @[Monitor.scala 388:22]
  wire  _T_543 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_544 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_548 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_552 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_556 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_560 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] size_1; // @[Monitor.scala 537:22]
  reg [6:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_567 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_568 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_576 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_580 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [95:0] inflight; // @[Monitor.scala 611:27]
  reg [383:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [383:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [8:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [9:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [383:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [383:0] _GEN_73 = {{368'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[383:1]}; // @[Monitor.scala 634:152]
  wire [383:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [383:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
  wire [383:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[383:1]}; // @[Monitor.scala 638:144]
  wire  _T_594 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [127:0] _a_set_wo_ready_T = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_597 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
  wire [8:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [9:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [1026:0] _GEN_1 = {{1023'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [1026:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
  wire [1025:0] _GEN_2 = {{1023'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [1025:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [95:0] _T_599 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_601 = ~_T_599[0]; // @[Monitor.scala 658:17]
  wire [127:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 652:72 653:28]
  wire [1026:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 1027'h0; // @[Monitor.scala 652:72 656:28]
  wire [1025:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 1026'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_605 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_607 = ~_T_401; // @[Monitor.scala 671:74]
  wire  _T_608 = io_in_d_valid & d_first_1 & ~_T_401; // @[Monitor.scala 671:71]
  wire [127:0] _d_clr_wo_ready_T = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [1038:0] _GEN_3 = {{1023'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [1038:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [127:0] _GEN_22 = d_first_done & d_first_1 & _T_607 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 675:91 676:21]
  wire [1038:0] _GEN_23 = d_first_done & d_first_1 & _T_607 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_594 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [95:0] _T_618 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_620 = _T_618[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_625 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_626 = io_in_d_bits_opcode == _GEN_32 | _T_625; // @[Monitor.scala 685:77]
  wire  _T_630 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_637 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_638 = io_in_d_bits_opcode == _GEN_48 | _T_637; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_642 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_652 = _T_605 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_607; // @[Monitor.scala 694:116]
  wire  _T_654 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [95:0] a_set = _GEN_16[95:0];
  wire [95:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [95:0] d_clr = _GEN_22[95:0];
  wire [95:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [95:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [383:0] a_opcodes_set = _GEN_19[383:0];
  wire [383:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [383:0] d_opcodes_clr = _GEN_23[383:0];
  wire [383:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [383:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [383:0] a_sizes_set = _GEN_20[383:0];
  wire [383:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [383:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_663 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [95:0] inflight_1; // @[Monitor.scala 723:35]
  reg [383:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [383:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [383:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
  wire [383:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[383:1]}; // @[Monitor.scala 747:146]
  wire  _T_689 = io_in_d_valid & d_first_2 & _T_401; // @[Monitor.scala 779:71]
  wire [127:0] _GEN_67 = d_first_done & d_first_2 & _T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 783:90 784:21]
  wire [1038:0] _GEN_68 = d_first_done & d_first_2 & _T_401 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 783:90 785:21]
  wire [95:0] _T_697 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_707 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [95:0] d_clr_1 = _GEN_67[95:0];
  wire [95:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [95:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [383:0] d_opcodes_clr_1 = _GEN_68[383:0];
  wire [383:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [383:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_727 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 1'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= 1'h0;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 96'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 384'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 384'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 1'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= 1'h0;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 96'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 384'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= 1'h0;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (d_first_done) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_172 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_172) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_275 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_275) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_309 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_309) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_347 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_347) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_385 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_397 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_397) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_478 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_478 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_495 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_495 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_513 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_513 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_544 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_544) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_548 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_548) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_552 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_552) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_556 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_556) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_560 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_560) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_568 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_568) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_576 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_576) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_580 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_580) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_601 & (_T_597 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_597 & ~reset & ~_T_601) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_620 & (_T_608 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & _T_2 & ~_T_620) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_626 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_626) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_630 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_630) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_638 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_638) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_642 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_642) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_654 & (_T_652 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_652 & _T_2 & ~_T_654) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_663 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_663) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_697[0] & (_T_689 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_689 & _T_2 & ~_T_697[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_707 & (_T_689 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_689 & _T_2 & ~_T_707) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_727 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_727) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[6:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[28:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[6:0];
  _RAND_10 = {3{`RANDOM}};
  inflight = _RAND_10[95:0];
  _RAND_11 = {12{`RANDOM}};
  inflight_opcodes = _RAND_11[383:0];
  _RAND_12 = {12{`RANDOM}};
  inflight_sizes = _RAND_12[383:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {3{`RANDOM}};
  inflight_1 = _RAND_16[95:0];
  _RAND_17 = {12{`RANDOM}};
  inflight_sizes_1 = _RAND_17[383:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module SynchronizerShiftReg_w32_d3(
  input         clock,
  input  [31:0] io_d,
  output [31:0] io_q
);
  wire  output_chain_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_1_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_1_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_1_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_2_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_2_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_2_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_3_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_3_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_3_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_4_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_4_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_4_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_5_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_5_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_5_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_6_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_6_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_6_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_7_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_7_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_7_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_8_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_8_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_8_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_9_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_9_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_9_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_10_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_10_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_10_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_11_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_11_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_11_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_12_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_12_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_12_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_13_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_13_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_13_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_14_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_14_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_14_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_15_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_15_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_15_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_16_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_16_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_16_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_17_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_17_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_17_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_18_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_18_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_18_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_19_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_19_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_19_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_20_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_20_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_20_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_21_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_21_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_21_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_22_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_22_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_22_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_23_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_23_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_23_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_24_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_24_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_24_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_25_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_25_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_25_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_26_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_26_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_26_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_27_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_27_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_27_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_28_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_28_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_28_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_29_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_29_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_29_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_30_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_30_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_30_io_q; // @[ShiftReg.scala 45:23]
  wire  output_chain_31_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_31_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_31_io_q; // @[ShiftReg.scala 45:23]
  wire  output_1 = output_chain_1_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  output_0 = output_chain_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  output_3 = output_chain_3_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  output_2 = output_chain_2_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  output_5 = output_chain_5_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  output_4 = output_chain_4_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  output_7 = output_chain_7_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  output_6 = output_chain_6_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire [7:0] io_q_lo_lo = {output_7,output_6,output_5,output_4,output_3,output_2,output_1,output_0}; // @[Cat.scala 31:58]
  wire  output_9 = output_chain_9_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  output_8 = output_chain_8_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  output_11 = output_chain_11_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  output_10 = output_chain_10_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  output_13 = output_chain_13_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  output_12 = output_chain_12_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  output_15 = output_chain_15_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  output_14 = output_chain_14_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire [15:0] io_q_lo = {output_15,output_14,output_13,output_12,output_11,output_10,output_9,output_8,io_q_lo_lo}; // @[Cat.scala 31:58]
  wire  output_17 = output_chain_17_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  output_16 = output_chain_16_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  output_19 = output_chain_19_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  output_18 = output_chain_18_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  output_21 = output_chain_21_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  output_20 = output_chain_20_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  output_23 = output_chain_23_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  output_22 = output_chain_22_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire [7:0] io_q_hi_lo = {output_23,output_22,output_21,output_20,output_19,output_18,output_17,output_16}; // @[Cat.scala 31:58]
  wire  output_25 = output_chain_25_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  output_24 = output_chain_24_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  output_27 = output_chain_27_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  output_26 = output_chain_26_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  output_29 = output_chain_29_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  output_28 = output_chain_28_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  output_31 = output_chain_31_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  output_30 = output_chain_30_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire [15:0] io_q_hi = {output_31,output_30,output_29,output_28,output_27,output_26,output_25,output_24,io_q_hi_lo}; // @[Cat.scala 31:58]
  NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_clock),
    .io_d(output_chain_io_d),
    .io_q(output_chain_io_q)
  );
  NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain_1 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_1_clock),
    .io_d(output_chain_1_io_d),
    .io_q(output_chain_1_io_q)
  );
  NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain_2 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_2_clock),
    .io_d(output_chain_2_io_d),
    .io_q(output_chain_2_io_q)
  );
  NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain_3 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_3_clock),
    .io_d(output_chain_3_io_d),
    .io_q(output_chain_3_io_q)
  );
  NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain_4 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_4_clock),
    .io_d(output_chain_4_io_d),
    .io_q(output_chain_4_io_q)
  );
  NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain_5 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_5_clock),
    .io_d(output_chain_5_io_d),
    .io_q(output_chain_5_io_q)
  );
  NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain_6 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_6_clock),
    .io_d(output_chain_6_io_d),
    .io_q(output_chain_6_io_q)
  );
  NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain_7 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_7_clock),
    .io_d(output_chain_7_io_d),
    .io_q(output_chain_7_io_q)
  );
  NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain_8 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_8_clock),
    .io_d(output_chain_8_io_d),
    .io_q(output_chain_8_io_q)
  );
  NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain_9 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_9_clock),
    .io_d(output_chain_9_io_d),
    .io_q(output_chain_9_io_q)
  );
  NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain_10 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_10_clock),
    .io_d(output_chain_10_io_d),
    .io_q(output_chain_10_io_q)
  );
  NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain_11 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_11_clock),
    .io_d(output_chain_11_io_d),
    .io_q(output_chain_11_io_q)
  );
  NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain_12 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_12_clock),
    .io_d(output_chain_12_io_d),
    .io_q(output_chain_12_io_q)
  );
  NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain_13 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_13_clock),
    .io_d(output_chain_13_io_d),
    .io_q(output_chain_13_io_q)
  );
  NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain_14 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_14_clock),
    .io_d(output_chain_14_io_d),
    .io_q(output_chain_14_io_q)
  );
  NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain_15 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_15_clock),
    .io_d(output_chain_15_io_d),
    .io_q(output_chain_15_io_q)
  );
  NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain_16 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_16_clock),
    .io_d(output_chain_16_io_d),
    .io_q(output_chain_16_io_q)
  );
  NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain_17 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_17_clock),
    .io_d(output_chain_17_io_d),
    .io_q(output_chain_17_io_q)
  );
  NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain_18 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_18_clock),
    .io_d(output_chain_18_io_d),
    .io_q(output_chain_18_io_q)
  );
  NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain_19 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_19_clock),
    .io_d(output_chain_19_io_d),
    .io_q(output_chain_19_io_q)
  );
  NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain_20 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_20_clock),
    .io_d(output_chain_20_io_d),
    .io_q(output_chain_20_io_q)
  );
  NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain_21 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_21_clock),
    .io_d(output_chain_21_io_d),
    .io_q(output_chain_21_io_q)
  );
  NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain_22 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_22_clock),
    .io_d(output_chain_22_io_d),
    .io_q(output_chain_22_io_q)
  );
  NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain_23 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_23_clock),
    .io_d(output_chain_23_io_d),
    .io_q(output_chain_23_io_q)
  );
  NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain_24 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_24_clock),
    .io_d(output_chain_24_io_d),
    .io_q(output_chain_24_io_q)
  );
  NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain_25 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_25_clock),
    .io_d(output_chain_25_io_d),
    .io_q(output_chain_25_io_q)
  );
  NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain_26 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_26_clock),
    .io_d(output_chain_26_io_d),
    .io_q(output_chain_26_io_q)
  );
  NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain_27 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_27_clock),
    .io_d(output_chain_27_io_d),
    .io_q(output_chain_27_io_q)
  );
  NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain_28 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_28_clock),
    .io_d(output_chain_28_io_d),
    .io_q(output_chain_28_io_q)
  );
  NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain_29 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_29_clock),
    .io_d(output_chain_29_io_d),
    .io_q(output_chain_29_io_q)
  );
  NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain_30 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_30_clock),
    .io_d(output_chain_30_io_d),
    .io_q(output_chain_30_io_q)
  );
  NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain_31 ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_31_clock),
    .io_d(output_chain_31_io_d),
    .io_q(output_chain_31_io_q)
  );
  assign io_q = {io_q_hi,io_q_lo}; // @[Cat.scala 31:58]
  assign output_chain_clock = clock;
  assign output_chain_io_d = io_d[0]; // @[SynchronizerReg.scala 173:39]
  assign output_chain_1_clock = clock;
  assign output_chain_1_io_d = io_d[1]; // @[SynchronizerReg.scala 173:39]
  assign output_chain_2_clock = clock;
  assign output_chain_2_io_d = io_d[2]; // @[SynchronizerReg.scala 173:39]
  assign output_chain_3_clock = clock;
  assign output_chain_3_io_d = io_d[3]; // @[SynchronizerReg.scala 173:39]
  assign output_chain_4_clock = clock;
  assign output_chain_4_io_d = io_d[4]; // @[SynchronizerReg.scala 173:39]
  assign output_chain_5_clock = clock;
  assign output_chain_5_io_d = io_d[5]; // @[SynchronizerReg.scala 173:39]
  assign output_chain_6_clock = clock;
  assign output_chain_6_io_d = io_d[6]; // @[SynchronizerReg.scala 173:39]
  assign output_chain_7_clock = clock;
  assign output_chain_7_io_d = io_d[7]; // @[SynchronizerReg.scala 173:39]
  assign output_chain_8_clock = clock;
  assign output_chain_8_io_d = io_d[8]; // @[SynchronizerReg.scala 173:39]
  assign output_chain_9_clock = clock;
  assign output_chain_9_io_d = io_d[9]; // @[SynchronizerReg.scala 173:39]
  assign output_chain_10_clock = clock;
  assign output_chain_10_io_d = io_d[10]; // @[SynchronizerReg.scala 173:39]
  assign output_chain_11_clock = clock;
  assign output_chain_11_io_d = io_d[11]; // @[SynchronizerReg.scala 173:39]
  assign output_chain_12_clock = clock;
  assign output_chain_12_io_d = io_d[12]; // @[SynchronizerReg.scala 173:39]
  assign output_chain_13_clock = clock;
  assign output_chain_13_io_d = io_d[13]; // @[SynchronizerReg.scala 173:39]
  assign output_chain_14_clock = clock;
  assign output_chain_14_io_d = io_d[14]; // @[SynchronizerReg.scala 173:39]
  assign output_chain_15_clock = clock;
  assign output_chain_15_io_d = io_d[15]; // @[SynchronizerReg.scala 173:39]
  assign output_chain_16_clock = clock;
  assign output_chain_16_io_d = io_d[16]; // @[SynchronizerReg.scala 173:39]
  assign output_chain_17_clock = clock;
  assign output_chain_17_io_d = io_d[17]; // @[SynchronizerReg.scala 173:39]
  assign output_chain_18_clock = clock;
  assign output_chain_18_io_d = io_d[18]; // @[SynchronizerReg.scala 173:39]
  assign output_chain_19_clock = clock;
  assign output_chain_19_io_d = io_d[19]; // @[SynchronizerReg.scala 173:39]
  assign output_chain_20_clock = clock;
  assign output_chain_20_io_d = io_d[20]; // @[SynchronizerReg.scala 173:39]
  assign output_chain_21_clock = clock;
  assign output_chain_21_io_d = io_d[21]; // @[SynchronizerReg.scala 173:39]
  assign output_chain_22_clock = clock;
  assign output_chain_22_io_d = io_d[22]; // @[SynchronizerReg.scala 173:39]
  assign output_chain_23_clock = clock;
  assign output_chain_23_io_d = io_d[23]; // @[SynchronizerReg.scala 173:39]
  assign output_chain_24_clock = clock;
  assign output_chain_24_io_d = io_d[24]; // @[SynchronizerReg.scala 173:39]
  assign output_chain_25_clock = clock;
  assign output_chain_25_io_d = io_d[25]; // @[SynchronizerReg.scala 173:39]
  assign output_chain_26_clock = clock;
  assign output_chain_26_io_d = io_d[26]; // @[SynchronizerReg.scala 173:39]
  assign output_chain_27_clock = clock;
  assign output_chain_27_io_d = io_d[27]; // @[SynchronizerReg.scala 173:39]
  assign output_chain_28_clock = clock;
  assign output_chain_28_io_d = io_d[28]; // @[SynchronizerReg.scala 173:39]
  assign output_chain_29_clock = clock;
  assign output_chain_29_io_d = io_d[29]; // @[SynchronizerReg.scala 173:39]
  assign output_chain_30_clock = clock;
  assign output_chain_30_io_d = io_d[30]; // @[SynchronizerReg.scala 173:39]
  assign output_chain_31_clock = clock;
  assign output_chain_31_io_d = io_d[31]; // @[SynchronizerReg.scala 173:39]
endmodule
module TLGPIO(
  input         clock,
  input         reset,
  output        auto_int_xing_out_sync_0,
  output        auto_int_xing_out_sync_1,
  output        auto_int_xing_out_sync_2,
  output        auto_int_xing_out_sync_3,
  output        auto_int_xing_out_sync_4,
  output        auto_int_xing_out_sync_5,
  output        auto_int_xing_out_sync_6,
  output        auto_int_xing_out_sync_7,
  output        auto_int_xing_out_sync_8,
  output        auto_int_xing_out_sync_9,
  output        auto_int_xing_out_sync_10,
  output        auto_int_xing_out_sync_11,
  output        auto_int_xing_out_sync_12,
  output        auto_int_xing_out_sync_13,
  output        auto_int_xing_out_sync_14,
  output        auto_int_xing_out_sync_15,
  output        auto_int_xing_out_sync_16,
  output        auto_int_xing_out_sync_17,
  output        auto_int_xing_out_sync_18,
  output        auto_int_xing_out_sync_19,
  output        auto_int_xing_out_sync_20,
  output        auto_int_xing_out_sync_21,
  output        auto_int_xing_out_sync_22,
  output        auto_int_xing_out_sync_23,
  output        auto_int_xing_out_sync_24,
  output        auto_int_xing_out_sync_25,
  output        auto_int_xing_out_sync_26,
  output        auto_int_xing_out_sync_27,
  output        auto_int_xing_out_sync_28,
  output        auto_int_xing_out_sync_29,
  output        auto_int_xing_out_sync_30,
  output        auto_int_xing_out_sync_31,
  output        auto_control_xing_in_a_ready,
  input         auto_control_xing_in_a_valid,
  input  [2:0]  auto_control_xing_in_a_bits_opcode,
  input  [2:0]  auto_control_xing_in_a_bits_param,
  input  [1:0]  auto_control_xing_in_a_bits_size,
  input  [6:0]  auto_control_xing_in_a_bits_source,
  input  [28:0] auto_control_xing_in_a_bits_address,
  input  [3:0]  auto_control_xing_in_a_bits_mask,
  input  [31:0] auto_control_xing_in_a_bits_data,
  input         auto_control_xing_in_a_bits_corrupt,
  input         auto_control_xing_in_d_ready,
  output        auto_control_xing_in_d_valid,
  output [2:0]  auto_control_xing_in_d_bits_opcode,
  output [1:0]  auto_control_xing_in_d_bits_size,
  output [6:0]  auto_control_xing_in_d_bits_source,
  output [31:0] auto_control_xing_in_d_bits_data,
  input         auto_iof_out_iof_0_0_o_oval,
  input         auto_iof_out_iof_0_1_o_oval,
  output        auto_iof_out_iof_0_2_i_ival,
  input         auto_iof_out_iof_0_2_o_oval,
  input         auto_iof_out_iof_0_2_o_oe,
  input         auto_iof_out_iof_0_2_o_ie,
  output        auto_iof_out_iof_0_3_i_ival,
  input         auto_iof_out_iof_0_3_o_oval,
  input         auto_iof_out_iof_0_3_o_oe,
  input         auto_iof_out_iof_0_3_o_ie,
  output        auto_iof_out_iof_0_4_i_ival,
  input         auto_iof_out_iof_0_4_o_oval,
  input         auto_iof_out_iof_0_4_o_oe,
  input         auto_iof_out_iof_0_4_o_ie,
  output        auto_iof_out_iof_0_5_i_ival,
  input         auto_iof_out_iof_0_5_o_oval,
  input         auto_iof_out_iof_0_5_o_oe,
  input         auto_iof_out_iof_0_5_o_ie,
  output        auto_iof_out_iof_0_12_i_ival,
  input         auto_iof_out_iof_0_12_o_oe,
  output        auto_iof_out_iof_0_13_i_ival,
  input         auto_iof_out_iof_0_13_o_oe,
  output        auto_iof_out_iof_0_14_i_ival,
  input         auto_iof_out_iof_0_14_o_oe,
  output        auto_iof_out_iof_0_15_i_ival,
  input         auto_iof_out_iof_0_15_o_oe,
  output        auto_iof_out_iof_0_16_i_ival,
  input         auto_iof_out_iof_0_17_o_oval,
  output        auto_iof_out_iof_0_18_i_ival,
  input         auto_iof_out_iof_0_19_o_oval,
  output        auto_iof_out_iof_0_20_i_ival,
  input         auto_iof_out_iof_0_21_o_oval,
  output        auto_iof_out_iof_0_22_i_ival,
  input         auto_iof_out_iof_0_23_o_oval,
  input         auto_iof_out_iof_0_24_o_oval,
  input         auto_iof_out_iof_1_12_o_oval,
  input         auto_iof_out_iof_1_13_o_oval,
  input         auto_iof_out_iof_1_14_o_oval,
  input         auto_iof_out_iof_1_15_o_oval,
  input         auto_iof_out_iof_1_16_o_oval,
  input         auto_iof_out_iof_1_17_o_oval,
  input         auto_iof_out_iof_1_18_o_oval,
  input         auto_iof_out_iof_1_19_o_oval,
  input         auto_iof_out_iof_1_20_o_oval,
  input         auto_iof_out_iof_1_21_o_oval,
  input         auto_iof_out_iof_1_22_o_oval,
  input         auto_iof_out_iof_1_23_o_oval,
  input         auto_io_out_pins_0_i_ival,
  output        auto_io_out_pins_0_o_oval,
  output        auto_io_out_pins_0_o_oe,
  output        auto_io_out_pins_0_o_ie,
  input         auto_io_out_pins_1_i_ival,
  output        auto_io_out_pins_1_o_oval,
  output        auto_io_out_pins_1_o_oe,
  output        auto_io_out_pins_1_o_ie,
  input         auto_io_out_pins_2_i_ival,
  output        auto_io_out_pins_2_o_oval,
  output        auto_io_out_pins_2_o_oe,
  output        auto_io_out_pins_2_o_ie,
  input         auto_io_out_pins_3_i_ival,
  output        auto_io_out_pins_3_o_oval,
  output        auto_io_out_pins_3_o_oe,
  output        auto_io_out_pins_3_o_ie,
  input         auto_io_out_pins_4_i_ival,
  output        auto_io_out_pins_4_o_oval,
  output        auto_io_out_pins_4_o_oe,
  output        auto_io_out_pins_4_o_ie,
  input         auto_io_out_pins_5_i_ival,
  output        auto_io_out_pins_5_o_oval,
  output        auto_io_out_pins_5_o_oe,
  output        auto_io_out_pins_5_o_ie,
  input         auto_io_out_pins_6_i_ival,
  output        auto_io_out_pins_6_o_oval,
  output        auto_io_out_pins_6_o_oe,
  input         auto_io_out_pins_7_i_ival,
  output        auto_io_out_pins_7_o_oval,
  output        auto_io_out_pins_7_o_oe,
  input         auto_io_out_pins_8_i_ival,
  output        auto_io_out_pins_8_o_oval,
  output        auto_io_out_pins_8_o_oe,
  input         auto_io_out_pins_9_i_ival,
  output        auto_io_out_pins_9_o_oval,
  output        auto_io_out_pins_9_o_oe,
  input         auto_io_out_pins_10_i_ival,
  output        auto_io_out_pins_10_o_oval,
  output        auto_io_out_pins_10_o_oe,
  input         auto_io_out_pins_11_i_ival,
  output        auto_io_out_pins_11_o_oval,
  output        auto_io_out_pins_11_o_oe,
  input         auto_io_out_pins_12_i_ival,
  output        auto_io_out_pins_12_o_oval,
  output        auto_io_out_pins_12_o_oe,
  output        auto_io_out_pins_12_o_ie,
  input         auto_io_out_pins_13_i_ival,
  output        auto_io_out_pins_13_o_oval,
  output        auto_io_out_pins_13_o_oe,
  output        auto_io_out_pins_13_o_ie,
  input         auto_io_out_pins_14_i_ival,
  output        auto_io_out_pins_14_o_oval,
  output        auto_io_out_pins_14_o_oe,
  output        auto_io_out_pins_14_o_ie,
  input         auto_io_out_pins_15_i_ival,
  output        auto_io_out_pins_15_o_oval,
  output        auto_io_out_pins_15_o_oe,
  output        auto_io_out_pins_15_o_ie,
  input         auto_io_out_pins_16_i_ival,
  output        auto_io_out_pins_16_o_oval,
  output        auto_io_out_pins_16_o_oe,
  output        auto_io_out_pins_16_o_ie,
  input         auto_io_out_pins_17_i_ival,
  output        auto_io_out_pins_17_o_oval,
  output        auto_io_out_pins_17_o_oe,
  output        auto_io_out_pins_17_o_ie,
  input         auto_io_out_pins_18_i_ival,
  output        auto_io_out_pins_18_o_oval,
  output        auto_io_out_pins_18_o_oe,
  output        auto_io_out_pins_18_o_ie,
  input         auto_io_out_pins_19_i_ival,
  output        auto_io_out_pins_19_o_oval,
  output        auto_io_out_pins_19_o_oe,
  output        auto_io_out_pins_19_o_ie,
  input         auto_io_out_pins_20_i_ival,
  output        auto_io_out_pins_20_o_oval,
  output        auto_io_out_pins_20_o_oe,
  output        auto_io_out_pins_20_o_ie,
  input         auto_io_out_pins_21_i_ival,
  output        auto_io_out_pins_21_o_oval,
  output        auto_io_out_pins_21_o_oe,
  output        auto_io_out_pins_21_o_ie,
  input         auto_io_out_pins_22_i_ival,
  output        auto_io_out_pins_22_o_oval,
  output        auto_io_out_pins_22_o_oe,
  output        auto_io_out_pins_22_o_ie,
  input         auto_io_out_pins_23_i_ival,
  output        auto_io_out_pins_23_o_oval,
  output        auto_io_out_pins_23_o_oe,
  output        auto_io_out_pins_23_o_ie,
  input         auto_io_out_pins_24_i_ival,
  output        auto_io_out_pins_24_o_oval,
  output        auto_io_out_pins_24_o_oe,
  output        auto_io_out_pins_24_o_ie,
  input         auto_io_out_pins_25_i_ival,
  output        auto_io_out_pins_25_o_oval,
  output        auto_io_out_pins_25_o_oe,
  input         auto_io_out_pins_26_i_ival,
  output        auto_io_out_pins_26_o_oval,
  output        auto_io_out_pins_26_o_oe,
  input         auto_io_out_pins_27_i_ival,
  output        auto_io_out_pins_27_o_oval,
  output        auto_io_out_pins_27_o_oe,
  input         auto_io_out_pins_28_i_ival,
  output        auto_io_out_pins_28_o_oval,
  output        auto_io_out_pins_28_o_oe,
  input         auto_io_out_pins_29_i_ival,
  output        auto_io_out_pins_29_o_oval,
  output        auto_io_out_pins_29_o_oe,
  input         auto_io_out_pins_30_i_ival,
  output        auto_io_out_pins_30_o_oval,
  output        auto_io_out_pins_30_o_oe,
  input         auto_io_out_pins_31_i_ival,
  output        auto_io_out_pins_31_o_oval,
  output        auto_io_out_pins_31_o_oe
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
`endif // RANDOMIZE_REG_INIT
  wire  buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
  wire [28:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
  wire [28:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
  wire  intsource_clock; // @[Crossing.scala 26:31]
  wire  intsource_reset; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_0; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_1; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_2; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_3; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_4; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_5; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_6; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_7; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_8; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_9; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_10; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_11; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_12; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_13; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_14; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_15; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_16; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_17; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_18; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_19; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_20; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_21; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_22; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_23; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_24; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_25; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_26; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_27; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_28; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_29; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_30; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_31; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_0; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_1; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_2; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_3; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_4; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_5; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_6; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_7; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_8; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_9; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_10; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_11; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_12; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_13; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_14; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_15; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_16; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_17; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_18; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_19; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_20; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_21; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_22; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_23; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_24; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_25; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_26; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_27; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_28; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_29; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_30; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_31; // @[Crossing.scala 26:31]
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  oeReg_clock; // @[GPIO.scala 79:22]
  wire  oeReg_reset; // @[GPIO.scala 79:22]
  wire [31:0] oeReg_io_d; // @[GPIO.scala 79:22]
  wire [31:0] oeReg_io_q; // @[GPIO.scala 79:22]
  wire  oeReg_io_en; // @[GPIO.scala 79:22]
  wire  pueReg_clock; // @[GPIO.scala 80:22]
  wire  pueReg_reset; // @[GPIO.scala 80:22]
  wire [31:0] pueReg_io_d; // @[GPIO.scala 80:22]
  wire [31:0] pueReg_io_q; // @[GPIO.scala 80:22]
  wire  pueReg_io_en; // @[GPIO.scala 80:22]
  wire  ieReg_clock; // @[GPIO.scala 82:22]
  wire  ieReg_reset; // @[GPIO.scala 82:22]
  wire [31:0] ieReg_io_d; // @[GPIO.scala 82:22]
  wire [31:0] ieReg_io_q; // @[GPIO.scala 82:22]
  wire  ieReg_io_en; // @[GPIO.scala 82:22]
  wire  poeReg_clock; // @[GPIO.scala 84:22]
  wire  poeReg_reset; // @[GPIO.scala 84:22]
  wire [31:0] poeReg_io_d; // @[GPIO.scala 84:22]
  wire [31:0] poeReg_io_q; // @[GPIO.scala 84:22]
  wire  poeReg_io_en; // @[GPIO.scala 84:22]
  wire  inSyncReg_inSyncReg_clock; // @[ShiftReg.scala 45:23]
  wire [31:0] inSyncReg_inSyncReg_io_d; // @[ShiftReg.scala 45:23]
  wire [31:0] inSyncReg_inSyncReg_io_q; // @[ShiftReg.scala 45:23]
  wire  iofEnReg_clock; // @[GPIO.scala 105:25]
  wire  iofEnReg_reset; // @[GPIO.scala 105:25]
  wire [31:0] iofEnReg_io_d; // @[GPIO.scala 105:25]
  wire [31:0] iofEnReg_io_q; // @[GPIO.scala 105:25]
  wire  iofEnReg_io_en; // @[GPIO.scala 105:25]
  reg [31:0] portReg; // @[GPIO.scala 77:20]
  reg [31:0] dsReg_0; // @[GPIO.scala 81:23]
  wire [7:0] inVal_lo_lo = {auto_io_out_pins_7_i_ival,auto_io_out_pins_6_i_ival,auto_io_out_pins_5_i_ival,
    auto_io_out_pins_4_i_ival,auto_io_out_pins_3_i_ival,auto_io_out_pins_2_i_ival,auto_io_out_pins_1_i_ival,
    auto_io_out_pins_0_i_ival}; // @[GPIO.scala 88:41]
  wire [15:0] inVal_lo = {auto_io_out_pins_15_i_ival,auto_io_out_pins_14_i_ival,auto_io_out_pins_13_i_ival,
    auto_io_out_pins_12_i_ival,auto_io_out_pins_11_i_ival,auto_io_out_pins_10_i_ival,auto_io_out_pins_9_i_ival,
    auto_io_out_pins_8_i_ival,inVal_lo_lo}; // @[GPIO.scala 88:41]
  wire [7:0] inVal_hi_lo = {auto_io_out_pins_23_i_ival,auto_io_out_pins_22_i_ival,auto_io_out_pins_21_i_ival,
    auto_io_out_pins_20_i_ival,auto_io_out_pins_19_i_ival,auto_io_out_pins_18_i_ival,auto_io_out_pins_17_i_ival,
    auto_io_out_pins_16_i_ival}; // @[GPIO.scala 88:41]
  wire [15:0] inVal_hi = {auto_io_out_pins_31_i_ival,auto_io_out_pins_30_i_ival,auto_io_out_pins_29_i_ival,
    auto_io_out_pins_28_i_ival,auto_io_out_pins_27_i_ival,auto_io_out_pins_26_i_ival,auto_io_out_pins_25_i_ival,
    auto_io_out_pins_24_i_ival,inVal_hi_lo}; // @[GPIO.scala 88:41]
  reg [31:0] valueReg; // @[GPIO.scala 90:23]
  reg [31:0] highIeReg; // @[GPIO.scala 93:22]
  reg [31:0] lowIeReg; // @[GPIO.scala 94:22]
  reg [31:0] riseIeReg; // @[GPIO.scala 95:22]
  reg [31:0] fallIeReg; // @[GPIO.scala 96:22]
  reg [31:0] highIpReg; // @[GPIO.scala 97:22]
  reg [31:0] lowIpReg; // @[GPIO.scala 98:22]
  reg [31:0] riseIpReg; // @[GPIO.scala 99:22]
  reg [31:0] fallIpReg; // @[GPIO.scala 100:22]
  reg [31:0] passthruHighIeReg; // @[GPIO.scala 101:30]
  reg [31:0] passthruLowIeReg; // @[GPIO.scala 102:30]
  reg [31:0] iofSelReg; // @[GPIO.scala 106:22]
  reg [31:0] xorReg; // @[GPIO.scala 109:22]
  wire [31:0] _rise_T = ~valueReg; // @[GPIO.scala 115:14]
  wire [31:0] inSyncReg = inSyncReg_inSyncReg_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire [31:0] rise = _rise_T & inSyncReg; // @[GPIO.scala 115:24]
  wire [31:0] _fall_T = ~inSyncReg; // @[GPIO.scala 116:25]
  wire [31:0] fall = valueReg & _fall_T; // @[GPIO.scala 116:23]
  wire [2:0] bundleIn_0_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  in_bits_read = bundleIn_0_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 72:36]
  wire [28:0] bundleIn_0_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [9:0] in_bits_index = bundleIn_0_a_bits_address[11:2]; // @[RegisterRouter.scala 71:18 73:19]
  wire [9:0] out_findex = in_bits_index & 10'h3e0; // @[RegisterRouter.scala 83:24]
  wire  _out_T = out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [3:0] bundleIn_0_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [7:0] _out_frontMask_T_5 = bundleIn_0_a_bits_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_frontMask_T_7 = bundleIn_0_a_bits_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_frontMask_T_9 = bundleIn_0_a_bits_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_frontMask_T_11 = bundleIn_0_a_bits_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [31:0] out_frontMask = {_out_frontMask_T_11,_out_frontMask_T_9,_out_frontMask_T_7,_out_frontMask_T_5}; // @[Cat.scala 31:58]
  wire  out_wimask = &out_frontMask; // @[RegisterRouter.scala 83:24]
  wire  bundleIn_0_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  bundleIn_0_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [4:0] out_oindex = {in_bits_index[4],in_bits_index[3],in_bits_index[2],in_bits_index[1],in_bits_index[0]}; // @[Cat.scala 31:58]
  wire [31:0] _out_frontSel_T = 32'h1 << out_oindex; // @[OneHot.scala 57:35]
  wire [31:0] bundleIn_0_a_bits_data = buffer_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  out_frontSel_5 = _out_frontSel_T[5]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_1 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_5 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_1 = out_wivalid_1 & out_wimask; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_10 = _out_frontSel_T[10]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_2 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_10 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_2 = out_wivalid_2 & out_wimask; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_14 = _out_frontSel_T[14]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_3 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_14 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [31:0] _out_T_82 = iofEnReg_io_q; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_1 = _out_frontSel_T[1]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_5 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_1 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [31:0] _out_T_102 = ieReg_io_q; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_6 = _out_frontSel_T[6]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_6 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_6 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_6 = out_wivalid_6 & out_wimask; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_9 = _out_frontSel_T[9]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_7 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_9 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_7 = out_wivalid_7 & out_wimask; // @[RegisterRouter.scala 83:24]
  wire [31:0] _out_fallIpReg_T = ~fallIpReg; // @[RegField.scala 128:61]
  wire [31:0] _out_fallIpReg_T_1 = out_f_wivalid_7 ? bundleIn_0_a_bits_data : 32'h0; // @[RegField.scala 128:71]
  wire [31:0] _out_fallIpReg_T_2 = _out_fallIpReg_T | _out_fallIpReg_T_1; // @[RegField.scala 128:66]
  wire [31:0] _out_fallIpReg_T_3 = ~_out_fallIpReg_T_2; // @[RegField.scala 128:59]
  wire [31:0] _out_fallIpReg_T_4 = _out_fallIpReg_T_3 | fall; // @[RegField.scala 128:95]
  wire  out_frontSel_13 = _out_frontSel_T[13]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_8 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_13 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_8 = out_wivalid_8 & out_wimask; // @[RegisterRouter.scala 83:24]
  wire [31:0] _out_lowIpReg_T = ~lowIpReg; // @[RegField.scala 128:61]
  wire [31:0] _out_lowIpReg_T_1 = out_f_wivalid_8 ? bundleIn_0_a_bits_data : 32'h0; // @[RegField.scala 128:71]
  wire [31:0] _out_lowIpReg_T_2 = _out_lowIpReg_T | _out_lowIpReg_T_1; // @[RegField.scala 128:66]
  wire [31:0] _out_lowIpReg_T_3 = ~_out_lowIpReg_T_2; // @[RegField.scala 128:59]
  wire [31:0] _out_lowIpReg_T_4 = _out_lowIpReg_T_3 | _rise_T; // @[RegField.scala 128:95]
  wire  out_frontSel_2 = _out_frontSel_T[2]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_9 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_2 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [31:0] _out_T_146 = oeReg_io_q; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_17 = _out_frontSel_T[17]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_10 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_17 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_10 = out_wivalid_10 & out_wimask; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_12 = _out_frontSel_T[12]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_11 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_12 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_11 = out_wivalid_11 & out_wimask; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_7 = _out_frontSel_T[7]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_12 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_7 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_12 = out_wivalid_12 & out_wimask; // @[RegisterRouter.scala 83:24]
  wire [31:0] _out_riseIpReg_T = ~riseIpReg; // @[RegField.scala 128:61]
  wire [31:0] _out_riseIpReg_T_1 = out_f_wivalid_12 ? bundleIn_0_a_bits_data : 32'h0; // @[RegField.scala 128:71]
  wire [31:0] _out_riseIpReg_T_2 = _out_riseIpReg_T | _out_riseIpReg_T_1; // @[RegField.scala 128:66]
  wire [31:0] _out_riseIpReg_T_3 = ~_out_riseIpReg_T_2; // @[RegField.scala 128:59]
  wire [31:0] _out_riseIpReg_T_4 = _out_riseIpReg_T_3 | rise; // @[RegField.scala 128:95]
  wire  out_frontSel_3 = _out_frontSel_T[3]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_13 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_3 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_13 = out_wivalid_13 & out_wimask; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_18 = _out_frontSel_T[18]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_14 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_18 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_14 = out_wivalid_14 & out_wimask; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_16 = _out_frontSel_T[16]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_15 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_16 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_15 = out_wivalid_15 & out_wimask; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_11 = _out_frontSel_T[11]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_16 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_11 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_16 = out_wivalid_16 & out_wimask; // @[RegisterRouter.scala 83:24]
  wire [31:0] _out_highIpReg_T = ~highIpReg; // @[RegField.scala 128:61]
  wire [31:0] _out_highIpReg_T_1 = out_f_wivalid_16 ? bundleIn_0_a_bits_data : 32'h0; // @[RegField.scala 128:71]
  wire [31:0] _out_highIpReg_T_2 = _out_highIpReg_T | _out_highIpReg_T_1; // @[RegField.scala 128:66]
  wire [31:0] _out_highIpReg_T_3 = ~_out_highIpReg_T_2; // @[RegField.scala 128:59]
  wire [31:0] _out_highIpReg_T_4 = _out_highIpReg_T_3 | valueReg; // @[RegField.scala 128:95]
  wire  out_frontSel_8 = _out_frontSel_T[8]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_17 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_8 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_17 = out_wivalid_17 & out_wimask; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_4 = _out_frontSel_T[4]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_19 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_4 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [31:0] _out_T_254 = pueReg_io_q; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_15 = _out_frontSel_T[15]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_20 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_15 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire  out_f_wivalid_20 = out_wivalid_20 & out_wimask; // @[RegisterRouter.scala 83:24]
  wire  _GEN_139 = 5'h1 == out_oindex ? _out_T : _out_T; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_140 = 5'h2 == out_oindex ? _out_T : _GEN_139; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_141 = 5'h3 == out_oindex ? _out_T : _GEN_140; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_142 = 5'h4 == out_oindex ? _out_T : _GEN_141; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_143 = 5'h5 == out_oindex ? _out_T : _GEN_142; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_144 = 5'h6 == out_oindex ? _out_T : _GEN_143; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_145 = 5'h7 == out_oindex ? _out_T : _GEN_144; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_146 = 5'h8 == out_oindex ? _out_T : _GEN_145; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_147 = 5'h9 == out_oindex ? _out_T : _GEN_146; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_148 = 5'ha == out_oindex ? _out_T : _GEN_147; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_149 = 5'hb == out_oindex ? _out_T : _GEN_148; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_150 = 5'hc == out_oindex ? _out_T : _GEN_149; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_151 = 5'hd == out_oindex ? _out_T : _GEN_150; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_152 = 5'he == out_oindex ? _out_T : _GEN_151; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_153 = 5'hf == out_oindex ? _out_T : _GEN_152; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_154 = 5'h10 == out_oindex ? _out_T : _GEN_153; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_155 = 5'h11 == out_oindex ? _out_T : _GEN_154; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_156 = 5'h12 == out_oindex ? _out_T : _GEN_155; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_157 = 5'h13 == out_oindex ? _out_T : _GEN_156; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_158 = 5'h14 == out_oindex ? _out_T : _GEN_157; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_169 = 5'h1f == out_oindex | (5'h1e == out_oindex | (5'h1d == out_oindex | (5'h1c == out_oindex | (5'h1b ==
    out_oindex | (5'h1a == out_oindex | (5'h19 == out_oindex | (5'h18 == out_oindex | (5'h17 == out_oindex | (5'h16 ==
    out_oindex | (5'h15 == out_oindex | _GEN_158)))))))))); // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_171 = 5'h1 == out_oindex ? _out_T_102 : valueReg; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_172 = 5'h2 == out_oindex ? _out_T_146 : _GEN_171; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_173 = 5'h3 == out_oindex ? portReg : _GEN_172; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_174 = 5'h4 == out_oindex ? _out_T_254 : _GEN_173; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_175 = 5'h5 == out_oindex ? dsReg_0 : _GEN_174; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_176 = 5'h6 == out_oindex ? riseIeReg : _GEN_175; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_177 = 5'h7 == out_oindex ? riseIpReg : _GEN_176; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_178 = 5'h8 == out_oindex ? fallIeReg : _GEN_177; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_179 = 5'h9 == out_oindex ? fallIpReg : _GEN_178; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_180 = 5'ha == out_oindex ? highIeReg : _GEN_179; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_181 = 5'hb == out_oindex ? highIpReg : _GEN_180; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_182 = 5'hc == out_oindex ? lowIeReg : _GEN_181; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_183 = 5'hd == out_oindex ? lowIpReg : _GEN_182; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_184 = 5'he == out_oindex ? _out_T_82 : _GEN_183; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_185 = 5'hf == out_oindex ? iofSelReg : _GEN_184; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_186 = 5'h10 == out_oindex ? xorReg : _GEN_185; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_187 = 5'h11 == out_oindex ? passthruHighIeReg : _GEN_186; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_188 = 5'h12 == out_oindex ? passthruLowIeReg : _GEN_187; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_189 = 5'h13 == out_oindex ? 32'h0 : _GEN_188; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_190 = 5'h14 == out_oindex ? 32'h0 : _GEN_189; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_191 = 5'h15 == out_oindex ? 32'h0 : _GEN_190; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_192 = 5'h16 == out_oindex ? 32'h0 : _GEN_191; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_193 = 5'h17 == out_oindex ? 32'h0 : _GEN_192; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_194 = 5'h18 == out_oindex ? 32'h0 : _GEN_193; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_195 = 5'h19 == out_oindex ? 32'h0 : _GEN_194; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_196 = 5'h1a == out_oindex ? 32'h0 : _GEN_195; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_197 = 5'h1b == out_oindex ? 32'h0 : _GEN_196; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_198 = 5'h1c == out_oindex ? 32'h0 : _GEN_197; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_199 = 5'h1d == out_oindex ? 32'h0 : _GEN_198; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_200 = 5'h1e == out_oindex ? 32'h0 : _GEN_199; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_201 = 5'h1f == out_oindex ? 32'h0 : _GEN_200; // @[MuxLiteral.scala 48:{10,10}]
  wire  swPinCtrl_0_oval = portReg[0]; // @[GPIO.scala 199:37]
  wire  swPinCtrl_0_oe = oeReg_io_q[0]; // @[GPIO.scala 200:40]
  wire  swPinCtrl_0_ie = ieReg_io_q[0]; // @[GPIO.scala 202:40]
  wire  iofCtrl_0_oval = iofSelReg[0] ? swPinCtrl_0_oval : auto_iof_out_iof_0_0_o_oval; // @[GPIO.scala 222:32]
  wire  iofCtrl_0_oe = iofSelReg[0] ? swPinCtrl_0_oe : 1'h1; // @[GPIO.scala 222:32]
  wire  iofCtrl_0_ie = iofSelReg[0] & swPinCtrl_0_ie; // @[GPIO.scala 222:32]
  wire  pre_xor_oval = iofEnReg_io_q[0] ? iofCtrl_0_oval : swPinCtrl_0_oval; // @[GPIO.scala 229:22]
  wire  _bundleOut_0_0_T_5 = fallIpReg[0] & fallIeReg[0]; // @[GPIO.scala 239:42]
  wire  _bundleOut_0_0_T_6 = riseIpReg[0] & riseIeReg[0] | _bundleOut_0_0_T_5; // @[GPIO.scala 238:58]
  wire  _bundleOut_0_0_T_9 = highIpReg[0] & highIeReg[0]; // @[GPIO.scala 240:42]
  wire  _bundleOut_0_0_T_10 = _bundleOut_0_0_T_6 | _bundleOut_0_0_T_9; // @[GPIO.scala 239:60]
  wire  _bundleOut_0_0_T_13 = lowIpReg[0] & lowIeReg[0]; // @[GPIO.scala 241:41]
  wire  _bundleOut_0_0_T_14 = _bundleOut_0_0_T_10 | _bundleOut_0_0_T_13; // @[GPIO.scala 240:60]
  wire  _bundleOut_0_0_T_17 = valueReg[0] & passthruHighIeReg[0]; // @[GPIO.scala 242:41]
  wire  _bundleOut_0_0_T_18 = _bundleOut_0_0_T_14 | _bundleOut_0_0_T_17; // @[GPIO.scala 241:58]
  wire  _bundleOut_0_0_T_22 = ~valueReg[0] & passthruLowIeReg[0]; // @[GPIO.scala 243:42]
  wire  swPinCtrl_1_oval = portReg[1]; // @[GPIO.scala 199:37]
  wire  swPinCtrl_1_oe = oeReg_io_q[1]; // @[GPIO.scala 200:40]
  wire  swPinCtrl_1_ie = ieReg_io_q[1]; // @[GPIO.scala 202:40]
  wire  iofCtrl_1_oval = iofSelReg[1] ? swPinCtrl_1_oval : auto_iof_out_iof_0_1_o_oval; // @[GPIO.scala 222:32]
  wire  iofCtrl_1_oe = iofSelReg[1] ? swPinCtrl_1_oe : 1'h1; // @[GPIO.scala 222:32]
  wire  iofCtrl_1_ie = iofSelReg[1] & swPinCtrl_1_ie; // @[GPIO.scala 222:32]
  wire  pre_xor_1_oval = iofEnReg_io_q[1] ? iofCtrl_1_oval : swPinCtrl_1_oval; // @[GPIO.scala 229:22]
  wire  _bundleOut_0_1_T_5 = fallIpReg[1] & fallIeReg[1]; // @[GPIO.scala 239:42]
  wire  _bundleOut_0_1_T_6 = riseIpReg[1] & riseIeReg[1] | _bundleOut_0_1_T_5; // @[GPIO.scala 238:58]
  wire  _bundleOut_0_1_T_9 = highIpReg[1] & highIeReg[1]; // @[GPIO.scala 240:42]
  wire  _bundleOut_0_1_T_10 = _bundleOut_0_1_T_6 | _bundleOut_0_1_T_9; // @[GPIO.scala 239:60]
  wire  _bundleOut_0_1_T_13 = lowIpReg[1] & lowIeReg[1]; // @[GPIO.scala 241:41]
  wire  _bundleOut_0_1_T_14 = _bundleOut_0_1_T_10 | _bundleOut_0_1_T_13; // @[GPIO.scala 240:60]
  wire  _bundleOut_0_1_T_17 = valueReg[1] & passthruHighIeReg[1]; // @[GPIO.scala 242:41]
  wire  _bundleOut_0_1_T_18 = _bundleOut_0_1_T_14 | _bundleOut_0_1_T_17; // @[GPIO.scala 241:58]
  wire  _bundleOut_0_1_T_22 = ~valueReg[1] & passthruLowIeReg[1]; // @[GPIO.scala 243:42]
  wire  swPinCtrl_2_oval = portReg[2]; // @[GPIO.scala 199:37]
  wire  swPinCtrl_2_oe = oeReg_io_q[2]; // @[GPIO.scala 200:40]
  wire  swPinCtrl_2_ie = ieReg_io_q[2]; // @[GPIO.scala 202:40]
  wire  iofCtrl_2_oval = iofSelReg[2] ? swPinCtrl_2_oval : auto_iof_out_iof_0_2_o_oval; // @[GPIO.scala 222:32]
  wire  iofCtrl_2_oe = iofSelReg[2] ? swPinCtrl_2_oe : auto_iof_out_iof_0_2_o_oe; // @[GPIO.scala 222:32]
  wire  iofCtrl_2_ie = iofSelReg[2] ? swPinCtrl_2_ie : auto_iof_out_iof_0_2_o_ie; // @[GPIO.scala 222:32]
  wire  pre_xor_2_oval = iofEnReg_io_q[2] ? iofCtrl_2_oval : swPinCtrl_2_oval; // @[GPIO.scala 229:22]
  wire  _bundleOut_0_2_T_5 = fallIpReg[2] & fallIeReg[2]; // @[GPIO.scala 239:42]
  wire  _bundleOut_0_2_T_6 = riseIpReg[2] & riseIeReg[2] | _bundleOut_0_2_T_5; // @[GPIO.scala 238:58]
  wire  _bundleOut_0_2_T_9 = highIpReg[2] & highIeReg[2]; // @[GPIO.scala 240:42]
  wire  _bundleOut_0_2_T_10 = _bundleOut_0_2_T_6 | _bundleOut_0_2_T_9; // @[GPIO.scala 239:60]
  wire  _bundleOut_0_2_T_13 = lowIpReg[2] & lowIeReg[2]; // @[GPIO.scala 241:41]
  wire  _bundleOut_0_2_T_14 = _bundleOut_0_2_T_10 | _bundleOut_0_2_T_13; // @[GPIO.scala 240:60]
  wire  _bundleOut_0_2_T_17 = valueReg[2] & passthruHighIeReg[2]; // @[GPIO.scala 242:41]
  wire  _bundleOut_0_2_T_18 = _bundleOut_0_2_T_14 | _bundleOut_0_2_T_17; // @[GPIO.scala 241:58]
  wire  _bundleOut_0_2_T_22 = ~valueReg[2] & passthruLowIeReg[2]; // @[GPIO.scala 243:42]
  wire  swPinCtrl_3_oval = portReg[3]; // @[GPIO.scala 199:37]
  wire  swPinCtrl_3_oe = oeReg_io_q[3]; // @[GPIO.scala 200:40]
  wire  swPinCtrl_3_ie = ieReg_io_q[3]; // @[GPIO.scala 202:40]
  wire  iofCtrl_3_oval = iofSelReg[3] ? swPinCtrl_3_oval : auto_iof_out_iof_0_3_o_oval; // @[GPIO.scala 222:32]
  wire  iofCtrl_3_oe = iofSelReg[3] ? swPinCtrl_3_oe : auto_iof_out_iof_0_3_o_oe; // @[GPIO.scala 222:32]
  wire  iofCtrl_3_ie = iofSelReg[3] ? swPinCtrl_3_ie : auto_iof_out_iof_0_3_o_ie; // @[GPIO.scala 222:32]
  wire  pre_xor_3_oval = iofEnReg_io_q[3] ? iofCtrl_3_oval : swPinCtrl_3_oval; // @[GPIO.scala 229:22]
  wire  _bundleOut_0_3_T_5 = fallIpReg[3] & fallIeReg[3]; // @[GPIO.scala 239:42]
  wire  _bundleOut_0_3_T_6 = riseIpReg[3] & riseIeReg[3] | _bundleOut_0_3_T_5; // @[GPIO.scala 238:58]
  wire  _bundleOut_0_3_T_9 = highIpReg[3] & highIeReg[3]; // @[GPIO.scala 240:42]
  wire  _bundleOut_0_3_T_10 = _bundleOut_0_3_T_6 | _bundleOut_0_3_T_9; // @[GPIO.scala 239:60]
  wire  _bundleOut_0_3_T_13 = lowIpReg[3] & lowIeReg[3]; // @[GPIO.scala 241:41]
  wire  _bundleOut_0_3_T_14 = _bundleOut_0_3_T_10 | _bundleOut_0_3_T_13; // @[GPIO.scala 240:60]
  wire  _bundleOut_0_3_T_17 = valueReg[3] & passthruHighIeReg[3]; // @[GPIO.scala 242:41]
  wire  _bundleOut_0_3_T_18 = _bundleOut_0_3_T_14 | _bundleOut_0_3_T_17; // @[GPIO.scala 241:58]
  wire  _bundleOut_0_3_T_22 = ~valueReg[3] & passthruLowIeReg[3]; // @[GPIO.scala 243:42]
  wire  swPinCtrl_4_oval = portReg[4]; // @[GPIO.scala 199:37]
  wire  swPinCtrl_4_oe = oeReg_io_q[4]; // @[GPIO.scala 200:40]
  wire  swPinCtrl_4_ie = ieReg_io_q[4]; // @[GPIO.scala 202:40]
  wire  iofCtrl_4_oval = iofSelReg[4] ? swPinCtrl_4_oval : auto_iof_out_iof_0_4_o_oval; // @[GPIO.scala 222:32]
  wire  iofCtrl_4_oe = iofSelReg[4] ? swPinCtrl_4_oe : auto_iof_out_iof_0_4_o_oe; // @[GPIO.scala 222:32]
  wire  iofCtrl_4_ie = iofSelReg[4] ? swPinCtrl_4_ie : auto_iof_out_iof_0_4_o_ie; // @[GPIO.scala 222:32]
  wire  pre_xor_4_oval = iofEnReg_io_q[4] ? iofCtrl_4_oval : swPinCtrl_4_oval; // @[GPIO.scala 229:22]
  wire  _bundleOut_0_4_T_5 = fallIpReg[4] & fallIeReg[4]; // @[GPIO.scala 239:42]
  wire  _bundleOut_0_4_T_6 = riseIpReg[4] & riseIeReg[4] | _bundleOut_0_4_T_5; // @[GPIO.scala 238:58]
  wire  _bundleOut_0_4_T_9 = highIpReg[4] & highIeReg[4]; // @[GPIO.scala 240:42]
  wire  _bundleOut_0_4_T_10 = _bundleOut_0_4_T_6 | _bundleOut_0_4_T_9; // @[GPIO.scala 239:60]
  wire  _bundleOut_0_4_T_13 = lowIpReg[4] & lowIeReg[4]; // @[GPIO.scala 241:41]
  wire  _bundleOut_0_4_T_14 = _bundleOut_0_4_T_10 | _bundleOut_0_4_T_13; // @[GPIO.scala 240:60]
  wire  _bundleOut_0_4_T_17 = valueReg[4] & passthruHighIeReg[4]; // @[GPIO.scala 242:41]
  wire  _bundleOut_0_4_T_18 = _bundleOut_0_4_T_14 | _bundleOut_0_4_T_17; // @[GPIO.scala 241:58]
  wire  _bundleOut_0_4_T_22 = ~valueReg[4] & passthruLowIeReg[4]; // @[GPIO.scala 243:42]
  wire  swPinCtrl_5_oval = portReg[5]; // @[GPIO.scala 199:37]
  wire  swPinCtrl_5_oe = oeReg_io_q[5]; // @[GPIO.scala 200:40]
  wire  swPinCtrl_5_ie = ieReg_io_q[5]; // @[GPIO.scala 202:40]
  wire  iofCtrl_5_oval = iofSelReg[5] ? swPinCtrl_5_oval : auto_iof_out_iof_0_5_o_oval; // @[GPIO.scala 222:32]
  wire  iofCtrl_5_oe = iofSelReg[5] ? swPinCtrl_5_oe : auto_iof_out_iof_0_5_o_oe; // @[GPIO.scala 222:32]
  wire  iofCtrl_5_ie = iofSelReg[5] ? swPinCtrl_5_ie : auto_iof_out_iof_0_5_o_ie; // @[GPIO.scala 222:32]
  wire  pre_xor_5_oval = iofEnReg_io_q[5] ? iofCtrl_5_oval : swPinCtrl_5_oval; // @[GPIO.scala 229:22]
  wire  _bundleOut_0_5_T_5 = fallIpReg[5] & fallIeReg[5]; // @[GPIO.scala 239:42]
  wire  _bundleOut_0_5_T_6 = riseIpReg[5] & riseIeReg[5] | _bundleOut_0_5_T_5; // @[GPIO.scala 238:58]
  wire  _bundleOut_0_5_T_9 = highIpReg[5] & highIeReg[5]; // @[GPIO.scala 240:42]
  wire  _bundleOut_0_5_T_10 = _bundleOut_0_5_T_6 | _bundleOut_0_5_T_9; // @[GPIO.scala 239:60]
  wire  _bundleOut_0_5_T_13 = lowIpReg[5] & lowIeReg[5]; // @[GPIO.scala 241:41]
  wire  _bundleOut_0_5_T_14 = _bundleOut_0_5_T_10 | _bundleOut_0_5_T_13; // @[GPIO.scala 240:60]
  wire  _bundleOut_0_5_T_17 = valueReg[5] & passthruHighIeReg[5]; // @[GPIO.scala 242:41]
  wire  _bundleOut_0_5_T_18 = _bundleOut_0_5_T_14 | _bundleOut_0_5_T_17; // @[GPIO.scala 241:58]
  wire  _bundleOut_0_5_T_22 = ~valueReg[5] & passthruLowIeReg[5]; // @[GPIO.scala 243:42]
  wire  swPinCtrl_6_oval = portReg[6]; // @[GPIO.scala 199:37]
  wire  _bundleOut_0_6_T_5 = fallIpReg[6] & fallIeReg[6]; // @[GPIO.scala 239:42]
  wire  _bundleOut_0_6_T_6 = riseIpReg[6] & riseIeReg[6] | _bundleOut_0_6_T_5; // @[GPIO.scala 238:58]
  wire  _bundleOut_0_6_T_9 = highIpReg[6] & highIeReg[6]; // @[GPIO.scala 240:42]
  wire  _bundleOut_0_6_T_10 = _bundleOut_0_6_T_6 | _bundleOut_0_6_T_9; // @[GPIO.scala 239:60]
  wire  _bundleOut_0_6_T_13 = lowIpReg[6] & lowIeReg[6]; // @[GPIO.scala 241:41]
  wire  _bundleOut_0_6_T_14 = _bundleOut_0_6_T_10 | _bundleOut_0_6_T_13; // @[GPIO.scala 240:60]
  wire  _bundleOut_0_6_T_17 = valueReg[6] & passthruHighIeReg[6]; // @[GPIO.scala 242:41]
  wire  _bundleOut_0_6_T_18 = _bundleOut_0_6_T_14 | _bundleOut_0_6_T_17; // @[GPIO.scala 241:58]
  wire  _bundleOut_0_6_T_22 = ~valueReg[6] & passthruLowIeReg[6]; // @[GPIO.scala 243:42]
  wire  swPinCtrl_7_oval = portReg[7]; // @[GPIO.scala 199:37]
  wire  _bundleOut_0_7_T_5 = fallIpReg[7] & fallIeReg[7]; // @[GPIO.scala 239:42]
  wire  _bundleOut_0_7_T_6 = riseIpReg[7] & riseIeReg[7] | _bundleOut_0_7_T_5; // @[GPIO.scala 238:58]
  wire  _bundleOut_0_7_T_9 = highIpReg[7] & highIeReg[7]; // @[GPIO.scala 240:42]
  wire  _bundleOut_0_7_T_10 = _bundleOut_0_7_T_6 | _bundleOut_0_7_T_9; // @[GPIO.scala 239:60]
  wire  _bundleOut_0_7_T_13 = lowIpReg[7] & lowIeReg[7]; // @[GPIO.scala 241:41]
  wire  _bundleOut_0_7_T_14 = _bundleOut_0_7_T_10 | _bundleOut_0_7_T_13; // @[GPIO.scala 240:60]
  wire  _bundleOut_0_7_T_17 = valueReg[7] & passthruHighIeReg[7]; // @[GPIO.scala 242:41]
  wire  _bundleOut_0_7_T_18 = _bundleOut_0_7_T_14 | _bundleOut_0_7_T_17; // @[GPIO.scala 241:58]
  wire  _bundleOut_0_7_T_22 = ~valueReg[7] & passthruLowIeReg[7]; // @[GPIO.scala 243:42]
  wire  swPinCtrl_8_oval = portReg[8]; // @[GPIO.scala 199:37]
  wire  _bundleOut_0_8_T_5 = fallIpReg[8] & fallIeReg[8]; // @[GPIO.scala 239:42]
  wire  _bundleOut_0_8_T_6 = riseIpReg[8] & riseIeReg[8] | _bundleOut_0_8_T_5; // @[GPIO.scala 238:58]
  wire  _bundleOut_0_8_T_9 = highIpReg[8] & highIeReg[8]; // @[GPIO.scala 240:42]
  wire  _bundleOut_0_8_T_10 = _bundleOut_0_8_T_6 | _bundleOut_0_8_T_9; // @[GPIO.scala 239:60]
  wire  _bundleOut_0_8_T_13 = lowIpReg[8] & lowIeReg[8]; // @[GPIO.scala 241:41]
  wire  _bundleOut_0_8_T_14 = _bundleOut_0_8_T_10 | _bundleOut_0_8_T_13; // @[GPIO.scala 240:60]
  wire  _bundleOut_0_8_T_17 = valueReg[8] & passthruHighIeReg[8]; // @[GPIO.scala 242:41]
  wire  _bundleOut_0_8_T_18 = _bundleOut_0_8_T_14 | _bundleOut_0_8_T_17; // @[GPIO.scala 241:58]
  wire  _bundleOut_0_8_T_22 = ~valueReg[8] & passthruLowIeReg[8]; // @[GPIO.scala 243:42]
  wire  swPinCtrl_9_oval = portReg[9]; // @[GPIO.scala 199:37]
  wire  _bundleOut_0_9_T_5 = fallIpReg[9] & fallIeReg[9]; // @[GPIO.scala 239:42]
  wire  _bundleOut_0_9_T_6 = riseIpReg[9] & riseIeReg[9] | _bundleOut_0_9_T_5; // @[GPIO.scala 238:58]
  wire  _bundleOut_0_9_T_9 = highIpReg[9] & highIeReg[9]; // @[GPIO.scala 240:42]
  wire  _bundleOut_0_9_T_10 = _bundleOut_0_9_T_6 | _bundleOut_0_9_T_9; // @[GPIO.scala 239:60]
  wire  _bundleOut_0_9_T_13 = lowIpReg[9] & lowIeReg[9]; // @[GPIO.scala 241:41]
  wire  _bundleOut_0_9_T_14 = _bundleOut_0_9_T_10 | _bundleOut_0_9_T_13; // @[GPIO.scala 240:60]
  wire  _bundleOut_0_9_T_17 = valueReg[9] & passthruHighIeReg[9]; // @[GPIO.scala 242:41]
  wire  _bundleOut_0_9_T_18 = _bundleOut_0_9_T_14 | _bundleOut_0_9_T_17; // @[GPIO.scala 241:58]
  wire  _bundleOut_0_9_T_22 = ~valueReg[9] & passthruLowIeReg[9]; // @[GPIO.scala 243:42]
  wire  swPinCtrl_10_oval = portReg[10]; // @[GPIO.scala 199:37]
  wire  _bundleOut_0_10_T_5 = fallIpReg[10] & fallIeReg[10]; // @[GPIO.scala 239:42]
  wire  _bundleOut_0_10_T_6 = riseIpReg[10] & riseIeReg[10] | _bundleOut_0_10_T_5; // @[GPIO.scala 238:58]
  wire  _bundleOut_0_10_T_9 = highIpReg[10] & highIeReg[10]; // @[GPIO.scala 240:42]
  wire  _bundleOut_0_10_T_10 = _bundleOut_0_10_T_6 | _bundleOut_0_10_T_9; // @[GPIO.scala 239:60]
  wire  _bundleOut_0_10_T_13 = lowIpReg[10] & lowIeReg[10]; // @[GPIO.scala 241:41]
  wire  _bundleOut_0_10_T_14 = _bundleOut_0_10_T_10 | _bundleOut_0_10_T_13; // @[GPIO.scala 240:60]
  wire  _bundleOut_0_10_T_17 = valueReg[10] & passthruHighIeReg[10]; // @[GPIO.scala 242:41]
  wire  _bundleOut_0_10_T_18 = _bundleOut_0_10_T_14 | _bundleOut_0_10_T_17; // @[GPIO.scala 241:58]
  wire  _bundleOut_0_10_T_22 = ~valueReg[10] & passthruLowIeReg[10]; // @[GPIO.scala 243:42]
  wire  swPinCtrl_11_oval = portReg[11]; // @[GPIO.scala 199:37]
  wire  _bundleOut_0_11_T_5 = fallIpReg[11] & fallIeReg[11]; // @[GPIO.scala 239:42]
  wire  _bundleOut_0_11_T_6 = riseIpReg[11] & riseIeReg[11] | _bundleOut_0_11_T_5; // @[GPIO.scala 238:58]
  wire  _bundleOut_0_11_T_9 = highIpReg[11] & highIeReg[11]; // @[GPIO.scala 240:42]
  wire  _bundleOut_0_11_T_10 = _bundleOut_0_11_T_6 | _bundleOut_0_11_T_9; // @[GPIO.scala 239:60]
  wire  _bundleOut_0_11_T_13 = lowIpReg[11] & lowIeReg[11]; // @[GPIO.scala 241:41]
  wire  _bundleOut_0_11_T_14 = _bundleOut_0_11_T_10 | _bundleOut_0_11_T_13; // @[GPIO.scala 240:60]
  wire  _bundleOut_0_11_T_17 = valueReg[11] & passthruHighIeReg[11]; // @[GPIO.scala 242:41]
  wire  _bundleOut_0_11_T_18 = _bundleOut_0_11_T_14 | _bundleOut_0_11_T_17; // @[GPIO.scala 241:58]
  wire  _bundleOut_0_11_T_22 = ~valueReg[11] & passthruLowIeReg[11]; // @[GPIO.scala 243:42]
  wire  swPinCtrl_12_oval = portReg[12]; // @[GPIO.scala 199:37]
  wire  swPinCtrl_12_oe = oeReg_io_q[12]; // @[GPIO.scala 200:40]
  wire  swPinCtrl_12_ie = ieReg_io_q[12]; // @[GPIO.scala 202:40]
  wire  iofCtrl_12_oval = iofSelReg[12] & auto_iof_out_iof_1_12_o_oval; // @[GPIO.scala 222:32]
  wire  iofCtrl_12_oe = iofSelReg[12] | auto_iof_out_iof_0_12_o_oe; // @[GPIO.scala 222:32]
  wire  iofCtrl_12_ie = iofSelReg[12] ? 1'h0 : 1'h1; // @[GPIO.scala 222:32]
  wire  pre_xor_12_oval = iofEnReg_io_q[12] ? iofCtrl_12_oval : swPinCtrl_12_oval; // @[GPIO.scala 229:22]
  wire  _bundleOut_0_12_T_5 = fallIpReg[12] & fallIeReg[12]; // @[GPIO.scala 239:42]
  wire  _bundleOut_0_12_T_6 = riseIpReg[12] & riseIeReg[12] | _bundleOut_0_12_T_5; // @[GPIO.scala 238:58]
  wire  _bundleOut_0_12_T_9 = highIpReg[12] & highIeReg[12]; // @[GPIO.scala 240:42]
  wire  _bundleOut_0_12_T_10 = _bundleOut_0_12_T_6 | _bundleOut_0_12_T_9; // @[GPIO.scala 239:60]
  wire  _bundleOut_0_12_T_13 = lowIpReg[12] & lowIeReg[12]; // @[GPIO.scala 241:41]
  wire  _bundleOut_0_12_T_14 = _bundleOut_0_12_T_10 | _bundleOut_0_12_T_13; // @[GPIO.scala 240:60]
  wire  _bundleOut_0_12_T_17 = valueReg[12] & passthruHighIeReg[12]; // @[GPIO.scala 242:41]
  wire  _bundleOut_0_12_T_18 = _bundleOut_0_12_T_14 | _bundleOut_0_12_T_17; // @[GPIO.scala 241:58]
  wire  _bundleOut_0_12_T_22 = ~valueReg[12] & passthruLowIeReg[12]; // @[GPIO.scala 243:42]
  wire  swPinCtrl_13_oval = portReg[13]; // @[GPIO.scala 199:37]
  wire  swPinCtrl_13_oe = oeReg_io_q[13]; // @[GPIO.scala 200:40]
  wire  swPinCtrl_13_ie = ieReg_io_q[13]; // @[GPIO.scala 202:40]
  wire  iofCtrl_13_oval = iofSelReg[13] & auto_iof_out_iof_1_13_o_oval; // @[GPIO.scala 222:32]
  wire  iofCtrl_13_oe = iofSelReg[13] | auto_iof_out_iof_0_13_o_oe; // @[GPIO.scala 222:32]
  wire  iofCtrl_13_ie = iofSelReg[13] ? 1'h0 : 1'h1; // @[GPIO.scala 222:32]
  wire  pre_xor_13_oval = iofEnReg_io_q[13] ? iofCtrl_13_oval : swPinCtrl_13_oval; // @[GPIO.scala 229:22]
  wire  _bundleOut_0_13_T_5 = fallIpReg[13] & fallIeReg[13]; // @[GPIO.scala 239:42]
  wire  _bundleOut_0_13_T_6 = riseIpReg[13] & riseIeReg[13] | _bundleOut_0_13_T_5; // @[GPIO.scala 238:58]
  wire  _bundleOut_0_13_T_9 = highIpReg[13] & highIeReg[13]; // @[GPIO.scala 240:42]
  wire  _bundleOut_0_13_T_10 = _bundleOut_0_13_T_6 | _bundleOut_0_13_T_9; // @[GPIO.scala 239:60]
  wire  _bundleOut_0_13_T_13 = lowIpReg[13] & lowIeReg[13]; // @[GPIO.scala 241:41]
  wire  _bundleOut_0_13_T_14 = _bundleOut_0_13_T_10 | _bundleOut_0_13_T_13; // @[GPIO.scala 240:60]
  wire  _bundleOut_0_13_T_17 = valueReg[13] & passthruHighIeReg[13]; // @[GPIO.scala 242:41]
  wire  _bundleOut_0_13_T_18 = _bundleOut_0_13_T_14 | _bundleOut_0_13_T_17; // @[GPIO.scala 241:58]
  wire  _bundleOut_0_13_T_22 = ~valueReg[13] & passthruLowIeReg[13]; // @[GPIO.scala 243:42]
  wire  swPinCtrl_14_oval = portReg[14]; // @[GPIO.scala 199:37]
  wire  swPinCtrl_14_oe = oeReg_io_q[14]; // @[GPIO.scala 200:40]
  wire  swPinCtrl_14_ie = ieReg_io_q[14]; // @[GPIO.scala 202:40]
  wire  iofCtrl_14_oval = iofSelReg[14] & auto_iof_out_iof_1_14_o_oval; // @[GPIO.scala 222:32]
  wire  iofCtrl_14_oe = iofSelReg[14] | auto_iof_out_iof_0_14_o_oe; // @[GPIO.scala 222:32]
  wire  iofCtrl_14_ie = iofSelReg[14] ? 1'h0 : 1'h1; // @[GPIO.scala 222:32]
  wire  pre_xor_14_oval = iofEnReg_io_q[14] ? iofCtrl_14_oval : swPinCtrl_14_oval; // @[GPIO.scala 229:22]
  wire  _bundleOut_0_14_T_5 = fallIpReg[14] & fallIeReg[14]; // @[GPIO.scala 239:42]
  wire  _bundleOut_0_14_T_6 = riseIpReg[14] & riseIeReg[14] | _bundleOut_0_14_T_5; // @[GPIO.scala 238:58]
  wire  _bundleOut_0_14_T_9 = highIpReg[14] & highIeReg[14]; // @[GPIO.scala 240:42]
  wire  _bundleOut_0_14_T_10 = _bundleOut_0_14_T_6 | _bundleOut_0_14_T_9; // @[GPIO.scala 239:60]
  wire  _bundleOut_0_14_T_13 = lowIpReg[14] & lowIeReg[14]; // @[GPIO.scala 241:41]
  wire  _bundleOut_0_14_T_14 = _bundleOut_0_14_T_10 | _bundleOut_0_14_T_13; // @[GPIO.scala 240:60]
  wire  _bundleOut_0_14_T_17 = valueReg[14] & passthruHighIeReg[14]; // @[GPIO.scala 242:41]
  wire  _bundleOut_0_14_T_18 = _bundleOut_0_14_T_14 | _bundleOut_0_14_T_17; // @[GPIO.scala 241:58]
  wire  _bundleOut_0_14_T_22 = ~valueReg[14] & passthruLowIeReg[14]; // @[GPIO.scala 243:42]
  wire  swPinCtrl_15_oval = portReg[15]; // @[GPIO.scala 199:37]
  wire  swPinCtrl_15_oe = oeReg_io_q[15]; // @[GPIO.scala 200:40]
  wire  swPinCtrl_15_ie = ieReg_io_q[15]; // @[GPIO.scala 202:40]
  wire  iofCtrl_15_oval = iofSelReg[15] & auto_iof_out_iof_1_15_o_oval; // @[GPIO.scala 222:32]
  wire  iofCtrl_15_oe = iofSelReg[15] | auto_iof_out_iof_0_15_o_oe; // @[GPIO.scala 222:32]
  wire  iofCtrl_15_ie = iofSelReg[15] ? 1'h0 : 1'h1; // @[GPIO.scala 222:32]
  wire  pre_xor_15_oval = iofEnReg_io_q[15] ? iofCtrl_15_oval : swPinCtrl_15_oval; // @[GPIO.scala 229:22]
  wire  _bundleOut_0_15_T_5 = fallIpReg[15] & fallIeReg[15]; // @[GPIO.scala 239:42]
  wire  _bundleOut_0_15_T_6 = riseIpReg[15] & riseIeReg[15] | _bundleOut_0_15_T_5; // @[GPIO.scala 238:58]
  wire  _bundleOut_0_15_T_9 = highIpReg[15] & highIeReg[15]; // @[GPIO.scala 240:42]
  wire  _bundleOut_0_15_T_10 = _bundleOut_0_15_T_6 | _bundleOut_0_15_T_9; // @[GPIO.scala 239:60]
  wire  _bundleOut_0_15_T_13 = lowIpReg[15] & lowIeReg[15]; // @[GPIO.scala 241:41]
  wire  _bundleOut_0_15_T_14 = _bundleOut_0_15_T_10 | _bundleOut_0_15_T_13; // @[GPIO.scala 240:60]
  wire  _bundleOut_0_15_T_17 = valueReg[15] & passthruHighIeReg[15]; // @[GPIO.scala 242:41]
  wire  _bundleOut_0_15_T_18 = _bundleOut_0_15_T_14 | _bundleOut_0_15_T_17; // @[GPIO.scala 241:58]
  wire  _bundleOut_0_15_T_22 = ~valueReg[15] & passthruLowIeReg[15]; // @[GPIO.scala 243:42]
  wire  swPinCtrl_16_oval = portReg[16]; // @[GPIO.scala 199:37]
  wire  swPinCtrl_16_oe = oeReg_io_q[16]; // @[GPIO.scala 200:40]
  wire  swPinCtrl_16_ie = ieReg_io_q[16]; // @[GPIO.scala 202:40]
  wire  iofCtrl_16_oe = iofSelReg[16]; // @[GPIO.scala 222:42]
  wire  iofCtrl_16_oval = iofCtrl_16_oe & auto_iof_out_iof_1_16_o_oval; // @[GPIO.scala 222:32]
  wire  iofCtrl_16_ie = iofCtrl_16_oe ? 1'h0 : 1'h1; // @[GPIO.scala 222:32]
  wire  pre_xor_16_oval = iofEnReg_io_q[16] ? iofCtrl_16_oval : swPinCtrl_16_oval; // @[GPIO.scala 229:22]
  wire  _bundleOut_0_16_T_5 = fallIpReg[16] & fallIeReg[16]; // @[GPIO.scala 239:42]
  wire  _bundleOut_0_16_T_6 = riseIpReg[16] & riseIeReg[16] | _bundleOut_0_16_T_5; // @[GPIO.scala 238:58]
  wire  _bundleOut_0_16_T_9 = highIpReg[16] & highIeReg[16]; // @[GPIO.scala 240:42]
  wire  _bundleOut_0_16_T_10 = _bundleOut_0_16_T_6 | _bundleOut_0_16_T_9; // @[GPIO.scala 239:60]
  wire  _bundleOut_0_16_T_13 = lowIpReg[16] & lowIeReg[16]; // @[GPIO.scala 241:41]
  wire  _bundleOut_0_16_T_14 = _bundleOut_0_16_T_10 | _bundleOut_0_16_T_13; // @[GPIO.scala 240:60]
  wire  _bundleOut_0_16_T_17 = valueReg[16] & passthruHighIeReg[16]; // @[GPIO.scala 242:41]
  wire  _bundleOut_0_16_T_18 = _bundleOut_0_16_T_14 | _bundleOut_0_16_T_17; // @[GPIO.scala 241:58]
  wire  _bundleOut_0_16_T_22 = ~valueReg[16] & passthruLowIeReg[16]; // @[GPIO.scala 243:42]
  wire  swPinCtrl_17_oval = portReg[17]; // @[GPIO.scala 199:37]
  wire  swPinCtrl_17_oe = oeReg_io_q[17]; // @[GPIO.scala 200:40]
  wire  swPinCtrl_17_ie = ieReg_io_q[17]; // @[GPIO.scala 202:40]
  wire  iofCtrl_17_oval = iofSelReg[17] ? auto_iof_out_iof_1_17_o_oval : auto_iof_out_iof_0_17_o_oval; // @[GPIO.scala 222:32]
  wire  pre_xor_17_oval = iofEnReg_io_q[17] ? iofCtrl_17_oval : swPinCtrl_17_oval; // @[GPIO.scala 229:22]
  wire  _bundleOut_0_17_T_5 = fallIpReg[17] & fallIeReg[17]; // @[GPIO.scala 239:42]
  wire  _bundleOut_0_17_T_6 = riseIpReg[17] & riseIeReg[17] | _bundleOut_0_17_T_5; // @[GPIO.scala 238:58]
  wire  _bundleOut_0_17_T_9 = highIpReg[17] & highIeReg[17]; // @[GPIO.scala 240:42]
  wire  _bundleOut_0_17_T_10 = _bundleOut_0_17_T_6 | _bundleOut_0_17_T_9; // @[GPIO.scala 239:60]
  wire  _bundleOut_0_17_T_13 = lowIpReg[17] & lowIeReg[17]; // @[GPIO.scala 241:41]
  wire  _bundleOut_0_17_T_14 = _bundleOut_0_17_T_10 | _bundleOut_0_17_T_13; // @[GPIO.scala 240:60]
  wire  _bundleOut_0_17_T_17 = valueReg[17] & passthruHighIeReg[17]; // @[GPIO.scala 242:41]
  wire  _bundleOut_0_17_T_18 = _bundleOut_0_17_T_14 | _bundleOut_0_17_T_17; // @[GPIO.scala 241:58]
  wire  _bundleOut_0_17_T_22 = ~valueReg[17] & passthruLowIeReg[17]; // @[GPIO.scala 243:42]
  wire  swPinCtrl_18_oval = portReg[18]; // @[GPIO.scala 199:37]
  wire  swPinCtrl_18_oe = oeReg_io_q[18]; // @[GPIO.scala 200:40]
  wire  swPinCtrl_18_ie = ieReg_io_q[18]; // @[GPIO.scala 202:40]
  wire  iofCtrl_18_oe = iofSelReg[18]; // @[GPIO.scala 222:42]
  wire  iofCtrl_18_oval = iofCtrl_18_oe & auto_iof_out_iof_1_18_o_oval; // @[GPIO.scala 222:32]
  wire  iofCtrl_18_ie = iofCtrl_18_oe ? 1'h0 : 1'h1; // @[GPIO.scala 222:32]
  wire  pre_xor_18_oval = iofEnReg_io_q[18] ? iofCtrl_18_oval : swPinCtrl_18_oval; // @[GPIO.scala 229:22]
  wire  _bundleOut_0_18_T_5 = fallIpReg[18] & fallIeReg[18]; // @[GPIO.scala 239:42]
  wire  _bundleOut_0_18_T_6 = riseIpReg[18] & riseIeReg[18] | _bundleOut_0_18_T_5; // @[GPIO.scala 238:58]
  wire  _bundleOut_0_18_T_9 = highIpReg[18] & highIeReg[18]; // @[GPIO.scala 240:42]
  wire  _bundleOut_0_18_T_10 = _bundleOut_0_18_T_6 | _bundleOut_0_18_T_9; // @[GPIO.scala 239:60]
  wire  _bundleOut_0_18_T_13 = lowIpReg[18] & lowIeReg[18]; // @[GPIO.scala 241:41]
  wire  _bundleOut_0_18_T_14 = _bundleOut_0_18_T_10 | _bundleOut_0_18_T_13; // @[GPIO.scala 240:60]
  wire  _bundleOut_0_18_T_17 = valueReg[18] & passthruHighIeReg[18]; // @[GPIO.scala 242:41]
  wire  _bundleOut_0_18_T_18 = _bundleOut_0_18_T_14 | _bundleOut_0_18_T_17; // @[GPIO.scala 241:58]
  wire  _bundleOut_0_18_T_22 = ~valueReg[18] & passthruLowIeReg[18]; // @[GPIO.scala 243:42]
  wire  swPinCtrl_19_oval = portReg[19]; // @[GPIO.scala 199:37]
  wire  swPinCtrl_19_oe = oeReg_io_q[19]; // @[GPIO.scala 200:40]
  wire  swPinCtrl_19_ie = ieReg_io_q[19]; // @[GPIO.scala 202:40]
  wire  iofCtrl_19_oval = iofSelReg[19] ? auto_iof_out_iof_1_19_o_oval : auto_iof_out_iof_0_19_o_oval; // @[GPIO.scala 222:32]
  wire  pre_xor_19_oval = iofEnReg_io_q[19] ? iofCtrl_19_oval : swPinCtrl_19_oval; // @[GPIO.scala 229:22]
  wire  _bundleOut_0_19_T_5 = fallIpReg[19] & fallIeReg[19]; // @[GPIO.scala 239:42]
  wire  _bundleOut_0_19_T_6 = riseIpReg[19] & riseIeReg[19] | _bundleOut_0_19_T_5; // @[GPIO.scala 238:58]
  wire  _bundleOut_0_19_T_9 = highIpReg[19] & highIeReg[19]; // @[GPIO.scala 240:42]
  wire  _bundleOut_0_19_T_10 = _bundleOut_0_19_T_6 | _bundleOut_0_19_T_9; // @[GPIO.scala 239:60]
  wire  _bundleOut_0_19_T_13 = lowIpReg[19] & lowIeReg[19]; // @[GPIO.scala 241:41]
  wire  _bundleOut_0_19_T_14 = _bundleOut_0_19_T_10 | _bundleOut_0_19_T_13; // @[GPIO.scala 240:60]
  wire  _bundleOut_0_19_T_17 = valueReg[19] & passthruHighIeReg[19]; // @[GPIO.scala 242:41]
  wire  _bundleOut_0_19_T_18 = _bundleOut_0_19_T_14 | _bundleOut_0_19_T_17; // @[GPIO.scala 241:58]
  wire  _bundleOut_0_19_T_22 = ~valueReg[19] & passthruLowIeReg[19]; // @[GPIO.scala 243:42]
  wire  swPinCtrl_20_oval = portReg[20]; // @[GPIO.scala 199:37]
  wire  swPinCtrl_20_oe = oeReg_io_q[20]; // @[GPIO.scala 200:40]
  wire  swPinCtrl_20_ie = ieReg_io_q[20]; // @[GPIO.scala 202:40]
  wire  iofCtrl_20_oe = iofSelReg[20]; // @[GPIO.scala 222:42]
  wire  iofCtrl_20_oval = iofCtrl_20_oe & auto_iof_out_iof_1_20_o_oval; // @[GPIO.scala 222:32]
  wire  iofCtrl_20_ie = iofCtrl_20_oe ? 1'h0 : 1'h1; // @[GPIO.scala 222:32]
  wire  pre_xor_20_oval = iofEnReg_io_q[20] ? iofCtrl_20_oval : swPinCtrl_20_oval; // @[GPIO.scala 229:22]
  wire  _bundleOut_0_20_T_5 = fallIpReg[20] & fallIeReg[20]; // @[GPIO.scala 239:42]
  wire  _bundleOut_0_20_T_6 = riseIpReg[20] & riseIeReg[20] | _bundleOut_0_20_T_5; // @[GPIO.scala 238:58]
  wire  _bundleOut_0_20_T_9 = highIpReg[20] & highIeReg[20]; // @[GPIO.scala 240:42]
  wire  _bundleOut_0_20_T_10 = _bundleOut_0_20_T_6 | _bundleOut_0_20_T_9; // @[GPIO.scala 239:60]
  wire  _bundleOut_0_20_T_13 = lowIpReg[20] & lowIeReg[20]; // @[GPIO.scala 241:41]
  wire  _bundleOut_0_20_T_14 = _bundleOut_0_20_T_10 | _bundleOut_0_20_T_13; // @[GPIO.scala 240:60]
  wire  _bundleOut_0_20_T_17 = valueReg[20] & passthruHighIeReg[20]; // @[GPIO.scala 242:41]
  wire  _bundleOut_0_20_T_18 = _bundleOut_0_20_T_14 | _bundleOut_0_20_T_17; // @[GPIO.scala 241:58]
  wire  _bundleOut_0_20_T_22 = ~valueReg[20] & passthruLowIeReg[20]; // @[GPIO.scala 243:42]
  wire  swPinCtrl_21_oval = portReg[21]; // @[GPIO.scala 199:37]
  wire  swPinCtrl_21_oe = oeReg_io_q[21]; // @[GPIO.scala 200:40]
  wire  swPinCtrl_21_ie = ieReg_io_q[21]; // @[GPIO.scala 202:40]
  wire  iofCtrl_21_oval = iofSelReg[21] ? auto_iof_out_iof_1_21_o_oval : auto_iof_out_iof_0_21_o_oval; // @[GPIO.scala 222:32]
  wire  pre_xor_21_oval = iofEnReg_io_q[21] ? iofCtrl_21_oval : swPinCtrl_21_oval; // @[GPIO.scala 229:22]
  wire  _bundleOut_0_21_T_5 = fallIpReg[21] & fallIeReg[21]; // @[GPIO.scala 239:42]
  wire  _bundleOut_0_21_T_6 = riseIpReg[21] & riseIeReg[21] | _bundleOut_0_21_T_5; // @[GPIO.scala 238:58]
  wire  _bundleOut_0_21_T_9 = highIpReg[21] & highIeReg[21]; // @[GPIO.scala 240:42]
  wire  _bundleOut_0_21_T_10 = _bundleOut_0_21_T_6 | _bundleOut_0_21_T_9; // @[GPIO.scala 239:60]
  wire  _bundleOut_0_21_T_13 = lowIpReg[21] & lowIeReg[21]; // @[GPIO.scala 241:41]
  wire  _bundleOut_0_21_T_14 = _bundleOut_0_21_T_10 | _bundleOut_0_21_T_13; // @[GPIO.scala 240:60]
  wire  _bundleOut_0_21_T_17 = valueReg[21] & passthruHighIeReg[21]; // @[GPIO.scala 242:41]
  wire  _bundleOut_0_21_T_18 = _bundleOut_0_21_T_14 | _bundleOut_0_21_T_17; // @[GPIO.scala 241:58]
  wire  _bundleOut_0_21_T_22 = ~valueReg[21] & passthruLowIeReg[21]; // @[GPIO.scala 243:42]
  wire  swPinCtrl_22_oval = portReg[22]; // @[GPIO.scala 199:37]
  wire  swPinCtrl_22_oe = oeReg_io_q[22]; // @[GPIO.scala 200:40]
  wire  swPinCtrl_22_ie = ieReg_io_q[22]; // @[GPIO.scala 202:40]
  wire  iofCtrl_22_oe = iofSelReg[22]; // @[GPIO.scala 222:42]
  wire  iofCtrl_22_oval = iofCtrl_22_oe & auto_iof_out_iof_1_22_o_oval; // @[GPIO.scala 222:32]
  wire  iofCtrl_22_ie = iofCtrl_22_oe ? 1'h0 : 1'h1; // @[GPIO.scala 222:32]
  wire  pre_xor_22_oval = iofEnReg_io_q[22] ? iofCtrl_22_oval : swPinCtrl_22_oval; // @[GPIO.scala 229:22]
  wire  _bundleOut_0_22_T_5 = fallIpReg[22] & fallIeReg[22]; // @[GPIO.scala 239:42]
  wire  _bundleOut_0_22_T_6 = riseIpReg[22] & riseIeReg[22] | _bundleOut_0_22_T_5; // @[GPIO.scala 238:58]
  wire  _bundleOut_0_22_T_9 = highIpReg[22] & highIeReg[22]; // @[GPIO.scala 240:42]
  wire  _bundleOut_0_22_T_10 = _bundleOut_0_22_T_6 | _bundleOut_0_22_T_9; // @[GPIO.scala 239:60]
  wire  _bundleOut_0_22_T_13 = lowIpReg[22] & lowIeReg[22]; // @[GPIO.scala 241:41]
  wire  _bundleOut_0_22_T_14 = _bundleOut_0_22_T_10 | _bundleOut_0_22_T_13; // @[GPIO.scala 240:60]
  wire  _bundleOut_0_22_T_17 = valueReg[22] & passthruHighIeReg[22]; // @[GPIO.scala 242:41]
  wire  _bundleOut_0_22_T_18 = _bundleOut_0_22_T_14 | _bundleOut_0_22_T_17; // @[GPIO.scala 241:58]
  wire  _bundleOut_0_22_T_22 = ~valueReg[22] & passthruLowIeReg[22]; // @[GPIO.scala 243:42]
  wire  swPinCtrl_23_oval = portReg[23]; // @[GPIO.scala 199:37]
  wire  swPinCtrl_23_oe = oeReg_io_q[23]; // @[GPIO.scala 200:40]
  wire  swPinCtrl_23_ie = ieReg_io_q[23]; // @[GPIO.scala 202:40]
  wire  iofCtrl_23_oval = iofSelReg[23] ? auto_iof_out_iof_1_23_o_oval : auto_iof_out_iof_0_23_o_oval; // @[GPIO.scala 222:32]
  wire  pre_xor_23_oval = iofEnReg_io_q[23] ? iofCtrl_23_oval : swPinCtrl_23_oval; // @[GPIO.scala 229:22]
  wire  _bundleOut_0_23_T_5 = fallIpReg[23] & fallIeReg[23]; // @[GPIO.scala 239:42]
  wire  _bundleOut_0_23_T_6 = riseIpReg[23] & riseIeReg[23] | _bundleOut_0_23_T_5; // @[GPIO.scala 238:58]
  wire  _bundleOut_0_23_T_9 = highIpReg[23] & highIeReg[23]; // @[GPIO.scala 240:42]
  wire  _bundleOut_0_23_T_10 = _bundleOut_0_23_T_6 | _bundleOut_0_23_T_9; // @[GPIO.scala 239:60]
  wire  _bundleOut_0_23_T_13 = lowIpReg[23] & lowIeReg[23]; // @[GPIO.scala 241:41]
  wire  _bundleOut_0_23_T_14 = _bundleOut_0_23_T_10 | _bundleOut_0_23_T_13; // @[GPIO.scala 240:60]
  wire  _bundleOut_0_23_T_17 = valueReg[23] & passthruHighIeReg[23]; // @[GPIO.scala 242:41]
  wire  _bundleOut_0_23_T_18 = _bundleOut_0_23_T_14 | _bundleOut_0_23_T_17; // @[GPIO.scala 241:58]
  wire  _bundleOut_0_23_T_22 = ~valueReg[23] & passthruLowIeReg[23]; // @[GPIO.scala 243:42]
  wire  swPinCtrl_24_oval = portReg[24]; // @[GPIO.scala 199:37]
  wire  swPinCtrl_24_oe = oeReg_io_q[24]; // @[GPIO.scala 200:40]
  wire  swPinCtrl_24_ie = ieReg_io_q[24]; // @[GPIO.scala 202:40]
  wire  iofCtrl_24_oval = iofSelReg[24] ? swPinCtrl_24_oval : auto_iof_out_iof_0_24_o_oval; // @[GPIO.scala 222:32]
  wire  iofCtrl_24_oe = iofSelReg[24] ? swPinCtrl_24_oe : 1'h1; // @[GPIO.scala 222:32]
  wire  iofCtrl_24_ie = iofSelReg[24] & swPinCtrl_24_ie; // @[GPIO.scala 222:32]
  wire  pre_xor_24_oval = iofEnReg_io_q[24] ? iofCtrl_24_oval : swPinCtrl_24_oval; // @[GPIO.scala 229:22]
  wire  _bundleOut_0_24_T_5 = fallIpReg[24] & fallIeReg[24]; // @[GPIO.scala 239:42]
  wire  _bundleOut_0_24_T_6 = riseIpReg[24] & riseIeReg[24] | _bundleOut_0_24_T_5; // @[GPIO.scala 238:58]
  wire  _bundleOut_0_24_T_9 = highIpReg[24] & highIeReg[24]; // @[GPIO.scala 240:42]
  wire  _bundleOut_0_24_T_10 = _bundleOut_0_24_T_6 | _bundleOut_0_24_T_9; // @[GPIO.scala 239:60]
  wire  _bundleOut_0_24_T_13 = lowIpReg[24] & lowIeReg[24]; // @[GPIO.scala 241:41]
  wire  _bundleOut_0_24_T_14 = _bundleOut_0_24_T_10 | _bundleOut_0_24_T_13; // @[GPIO.scala 240:60]
  wire  _bundleOut_0_24_T_17 = valueReg[24] & passthruHighIeReg[24]; // @[GPIO.scala 242:41]
  wire  _bundleOut_0_24_T_18 = _bundleOut_0_24_T_14 | _bundleOut_0_24_T_17; // @[GPIO.scala 241:58]
  wire  _bundleOut_0_24_T_22 = ~valueReg[24] & passthruLowIeReg[24]; // @[GPIO.scala 243:42]
  wire  swPinCtrl_25_oval = portReg[25]; // @[GPIO.scala 199:37]
  wire  _bundleOut_0_25_T_5 = fallIpReg[25] & fallIeReg[25]; // @[GPIO.scala 239:42]
  wire  _bundleOut_0_25_T_6 = riseIpReg[25] & riseIeReg[25] | _bundleOut_0_25_T_5; // @[GPIO.scala 238:58]
  wire  _bundleOut_0_25_T_9 = highIpReg[25] & highIeReg[25]; // @[GPIO.scala 240:42]
  wire  _bundleOut_0_25_T_10 = _bundleOut_0_25_T_6 | _bundleOut_0_25_T_9; // @[GPIO.scala 239:60]
  wire  _bundleOut_0_25_T_13 = lowIpReg[25] & lowIeReg[25]; // @[GPIO.scala 241:41]
  wire  _bundleOut_0_25_T_14 = _bundleOut_0_25_T_10 | _bundleOut_0_25_T_13; // @[GPIO.scala 240:60]
  wire  _bundleOut_0_25_T_17 = valueReg[25] & passthruHighIeReg[25]; // @[GPIO.scala 242:41]
  wire  _bundleOut_0_25_T_18 = _bundleOut_0_25_T_14 | _bundleOut_0_25_T_17; // @[GPIO.scala 241:58]
  wire  _bundleOut_0_25_T_22 = ~valueReg[25] & passthruLowIeReg[25]; // @[GPIO.scala 243:42]
  wire  swPinCtrl_26_oval = portReg[26]; // @[GPIO.scala 199:37]
  wire  _bundleOut_0_26_T_5 = fallIpReg[26] & fallIeReg[26]; // @[GPIO.scala 239:42]
  wire  _bundleOut_0_26_T_6 = riseIpReg[26] & riseIeReg[26] | _bundleOut_0_26_T_5; // @[GPIO.scala 238:58]
  wire  _bundleOut_0_26_T_9 = highIpReg[26] & highIeReg[26]; // @[GPIO.scala 240:42]
  wire  _bundleOut_0_26_T_10 = _bundleOut_0_26_T_6 | _bundleOut_0_26_T_9; // @[GPIO.scala 239:60]
  wire  _bundleOut_0_26_T_13 = lowIpReg[26] & lowIeReg[26]; // @[GPIO.scala 241:41]
  wire  _bundleOut_0_26_T_14 = _bundleOut_0_26_T_10 | _bundleOut_0_26_T_13; // @[GPIO.scala 240:60]
  wire  _bundleOut_0_26_T_17 = valueReg[26] & passthruHighIeReg[26]; // @[GPIO.scala 242:41]
  wire  _bundleOut_0_26_T_18 = _bundleOut_0_26_T_14 | _bundleOut_0_26_T_17; // @[GPIO.scala 241:58]
  wire  _bundleOut_0_26_T_22 = ~valueReg[26] & passthruLowIeReg[26]; // @[GPIO.scala 243:42]
  wire  swPinCtrl_27_oval = portReg[27]; // @[GPIO.scala 199:37]
  wire  _bundleOut_0_27_T_5 = fallIpReg[27] & fallIeReg[27]; // @[GPIO.scala 239:42]
  wire  _bundleOut_0_27_T_6 = riseIpReg[27] & riseIeReg[27] | _bundleOut_0_27_T_5; // @[GPIO.scala 238:58]
  wire  _bundleOut_0_27_T_9 = highIpReg[27] & highIeReg[27]; // @[GPIO.scala 240:42]
  wire  _bundleOut_0_27_T_10 = _bundleOut_0_27_T_6 | _bundleOut_0_27_T_9; // @[GPIO.scala 239:60]
  wire  _bundleOut_0_27_T_13 = lowIpReg[27] & lowIeReg[27]; // @[GPIO.scala 241:41]
  wire  _bundleOut_0_27_T_14 = _bundleOut_0_27_T_10 | _bundleOut_0_27_T_13; // @[GPIO.scala 240:60]
  wire  _bundleOut_0_27_T_17 = valueReg[27] & passthruHighIeReg[27]; // @[GPIO.scala 242:41]
  wire  _bundleOut_0_27_T_18 = _bundleOut_0_27_T_14 | _bundleOut_0_27_T_17; // @[GPIO.scala 241:58]
  wire  _bundleOut_0_27_T_22 = ~valueReg[27] & passthruLowIeReg[27]; // @[GPIO.scala 243:42]
  wire  swPinCtrl_28_oval = portReg[28]; // @[GPIO.scala 199:37]
  wire  _bundleOut_0_28_T_5 = fallIpReg[28] & fallIeReg[28]; // @[GPIO.scala 239:42]
  wire  _bundleOut_0_28_T_6 = riseIpReg[28] & riseIeReg[28] | _bundleOut_0_28_T_5; // @[GPIO.scala 238:58]
  wire  _bundleOut_0_28_T_9 = highIpReg[28] & highIeReg[28]; // @[GPIO.scala 240:42]
  wire  _bundleOut_0_28_T_10 = _bundleOut_0_28_T_6 | _bundleOut_0_28_T_9; // @[GPIO.scala 239:60]
  wire  _bundleOut_0_28_T_13 = lowIpReg[28] & lowIeReg[28]; // @[GPIO.scala 241:41]
  wire  _bundleOut_0_28_T_14 = _bundleOut_0_28_T_10 | _bundleOut_0_28_T_13; // @[GPIO.scala 240:60]
  wire  _bundleOut_0_28_T_17 = valueReg[28] & passthruHighIeReg[28]; // @[GPIO.scala 242:41]
  wire  _bundleOut_0_28_T_18 = _bundleOut_0_28_T_14 | _bundleOut_0_28_T_17; // @[GPIO.scala 241:58]
  wire  _bundleOut_0_28_T_22 = ~valueReg[28] & passthruLowIeReg[28]; // @[GPIO.scala 243:42]
  wire  swPinCtrl_29_oval = portReg[29]; // @[GPIO.scala 199:37]
  wire  _bundleOut_0_29_T_5 = fallIpReg[29] & fallIeReg[29]; // @[GPIO.scala 239:42]
  wire  _bundleOut_0_29_T_6 = riseIpReg[29] & riseIeReg[29] | _bundleOut_0_29_T_5; // @[GPIO.scala 238:58]
  wire  _bundleOut_0_29_T_9 = highIpReg[29] & highIeReg[29]; // @[GPIO.scala 240:42]
  wire  _bundleOut_0_29_T_10 = _bundleOut_0_29_T_6 | _bundleOut_0_29_T_9; // @[GPIO.scala 239:60]
  wire  _bundleOut_0_29_T_13 = lowIpReg[29] & lowIeReg[29]; // @[GPIO.scala 241:41]
  wire  _bundleOut_0_29_T_14 = _bundleOut_0_29_T_10 | _bundleOut_0_29_T_13; // @[GPIO.scala 240:60]
  wire  _bundleOut_0_29_T_17 = valueReg[29] & passthruHighIeReg[29]; // @[GPIO.scala 242:41]
  wire  _bundleOut_0_29_T_18 = _bundleOut_0_29_T_14 | _bundleOut_0_29_T_17; // @[GPIO.scala 241:58]
  wire  _bundleOut_0_29_T_22 = ~valueReg[29] & passthruLowIeReg[29]; // @[GPIO.scala 243:42]
  wire  swPinCtrl_30_oval = portReg[30]; // @[GPIO.scala 199:37]
  wire  _bundleOut_0_30_T_5 = fallIpReg[30] & fallIeReg[30]; // @[GPIO.scala 239:42]
  wire  _bundleOut_0_30_T_6 = riseIpReg[30] & riseIeReg[30] | _bundleOut_0_30_T_5; // @[GPIO.scala 238:58]
  wire  _bundleOut_0_30_T_9 = highIpReg[30] & highIeReg[30]; // @[GPIO.scala 240:42]
  wire  _bundleOut_0_30_T_10 = _bundleOut_0_30_T_6 | _bundleOut_0_30_T_9; // @[GPIO.scala 239:60]
  wire  _bundleOut_0_30_T_13 = lowIpReg[30] & lowIeReg[30]; // @[GPIO.scala 241:41]
  wire  _bundleOut_0_30_T_14 = _bundleOut_0_30_T_10 | _bundleOut_0_30_T_13; // @[GPIO.scala 240:60]
  wire  _bundleOut_0_30_T_17 = valueReg[30] & passthruHighIeReg[30]; // @[GPIO.scala 242:41]
  wire  _bundleOut_0_30_T_18 = _bundleOut_0_30_T_14 | _bundleOut_0_30_T_17; // @[GPIO.scala 241:58]
  wire  _bundleOut_0_30_T_22 = ~valueReg[30] & passthruLowIeReg[30]; // @[GPIO.scala 243:42]
  wire  swPinCtrl_31_oval = portReg[31]; // @[GPIO.scala 199:37]
  wire  _bundleOut_0_31_T_5 = fallIpReg[31] & fallIeReg[31]; // @[GPIO.scala 239:42]
  wire  _bundleOut_0_31_T_6 = riseIpReg[31] & riseIeReg[31] | _bundleOut_0_31_T_5; // @[GPIO.scala 238:58]
  wire  _bundleOut_0_31_T_9 = highIpReg[31] & highIeReg[31]; // @[GPIO.scala 240:42]
  wire  _bundleOut_0_31_T_10 = _bundleOut_0_31_T_6 | _bundleOut_0_31_T_9; // @[GPIO.scala 239:60]
  wire  _bundleOut_0_31_T_13 = lowIpReg[31] & lowIeReg[31]; // @[GPIO.scala 241:41]
  wire  _bundleOut_0_31_T_14 = _bundleOut_0_31_T_10 | _bundleOut_0_31_T_13; // @[GPIO.scala 240:60]
  wire  _bundleOut_0_31_T_17 = valueReg[31] & passthruHighIeReg[31]; // @[GPIO.scala 242:41]
  wire  _bundleOut_0_31_T_18 = _bundleOut_0_31_T_14 | _bundleOut_0_31_T_17; // @[GPIO.scala 241:58]
  wire  _bundleOut_0_31_T_22 = ~valueReg[31] & passthruLowIeReg[31]; // @[GPIO.scala 243:42]
  TLBuffer_13 buffer ( // @[Buffer.scala 68:28]
    .auto_in_a_ready(buffer_auto_in_a_ready),
    .auto_in_a_valid(buffer_auto_in_a_valid),
    .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
    .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
    .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
    .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
    .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
    .auto_in_a_bits_data(buffer_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
    .auto_in_d_ready(buffer_auto_in_d_ready),
    .auto_in_d_valid(buffer_auto_in_d_valid),
    .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
    .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
    .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
    .auto_out_a_ready(buffer_auto_out_a_ready),
    .auto_out_a_valid(buffer_auto_out_a_valid),
    .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
    .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
    .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
    .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
    .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
    .auto_out_a_bits_data(buffer_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
    .auto_out_d_ready(buffer_auto_out_d_ready),
    .auto_out_d_valid(buffer_auto_out_d_valid),
    .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
    .auto_out_d_bits_source(buffer_auto_out_d_bits_source),
    .auto_out_d_bits_data(buffer_auto_out_d_bits_data)
  );
  IntSyncCrossingSource_17 intsource ( // @[Crossing.scala 26:31]
    .clock(intsource_clock),
    .reset(intsource_reset),
    .auto_in_0(intsource_auto_in_0),
    .auto_in_1(intsource_auto_in_1),
    .auto_in_2(intsource_auto_in_2),
    .auto_in_3(intsource_auto_in_3),
    .auto_in_4(intsource_auto_in_4),
    .auto_in_5(intsource_auto_in_5),
    .auto_in_6(intsource_auto_in_6),
    .auto_in_7(intsource_auto_in_7),
    .auto_in_8(intsource_auto_in_8),
    .auto_in_9(intsource_auto_in_9),
    .auto_in_10(intsource_auto_in_10),
    .auto_in_11(intsource_auto_in_11),
    .auto_in_12(intsource_auto_in_12),
    .auto_in_13(intsource_auto_in_13),
    .auto_in_14(intsource_auto_in_14),
    .auto_in_15(intsource_auto_in_15),
    .auto_in_16(intsource_auto_in_16),
    .auto_in_17(intsource_auto_in_17),
    .auto_in_18(intsource_auto_in_18),
    .auto_in_19(intsource_auto_in_19),
    .auto_in_20(intsource_auto_in_20),
    .auto_in_21(intsource_auto_in_21),
    .auto_in_22(intsource_auto_in_22),
    .auto_in_23(intsource_auto_in_23),
    .auto_in_24(intsource_auto_in_24),
    .auto_in_25(intsource_auto_in_25),
    .auto_in_26(intsource_auto_in_26),
    .auto_in_27(intsource_auto_in_27),
    .auto_in_28(intsource_auto_in_28),
    .auto_in_29(intsource_auto_in_29),
    .auto_in_30(intsource_auto_in_30),
    .auto_in_31(intsource_auto_in_31),
    .auto_out_sync_0(intsource_auto_out_sync_0),
    .auto_out_sync_1(intsource_auto_out_sync_1),
    .auto_out_sync_2(intsource_auto_out_sync_2),
    .auto_out_sync_3(intsource_auto_out_sync_3),
    .auto_out_sync_4(intsource_auto_out_sync_4),
    .auto_out_sync_5(intsource_auto_out_sync_5),
    .auto_out_sync_6(intsource_auto_out_sync_6),
    .auto_out_sync_7(intsource_auto_out_sync_7),
    .auto_out_sync_8(intsource_auto_out_sync_8),
    .auto_out_sync_9(intsource_auto_out_sync_9),
    .auto_out_sync_10(intsource_auto_out_sync_10),
    .auto_out_sync_11(intsource_auto_out_sync_11),
    .auto_out_sync_12(intsource_auto_out_sync_12),
    .auto_out_sync_13(intsource_auto_out_sync_13),
    .auto_out_sync_14(intsource_auto_out_sync_14),
    .auto_out_sync_15(intsource_auto_out_sync_15),
    .auto_out_sync_16(intsource_auto_out_sync_16),
    .auto_out_sync_17(intsource_auto_out_sync_17),
    .auto_out_sync_18(intsource_auto_out_sync_18),
    .auto_out_sync_19(intsource_auto_out_sync_19),
    .auto_out_sync_20(intsource_auto_out_sync_20),
    .auto_out_sync_21(intsource_auto_out_sync_21),
    .auto_out_sync_22(intsource_auto_out_sync_22),
    .auto_out_sync_23(intsource_auto_out_sync_23),
    .auto_out_sync_24(intsource_auto_out_sync_24),
    .auto_out_sync_25(intsource_auto_out_sync_25),
    .auto_out_sync_26(intsource_auto_out_sync_26),
    .auto_out_sync_27(intsource_auto_out_sync_27),
    .auto_out_sync_28(intsource_auto_out_sync_28),
    .auto_out_sync_29(intsource_auto_out_sync_29),
    .auto_out_sync_30(intsource_auto_out_sync_30),
    .auto_out_sync_31(intsource_auto_out_sync_31)
  );
  TLMonitor_66 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  AsyncResetRegVec_w32_i0 oeReg ( // @[GPIO.scala 79:22]
    .clock(oeReg_clock),
    .reset(oeReg_reset),
    .io_d(oeReg_io_d),
    .io_q(oeReg_io_q),
    .io_en(oeReg_io_en)
  );
  AsyncResetRegVec_w32_i0 pueReg ( // @[GPIO.scala 80:22]
    .clock(pueReg_clock),
    .reset(pueReg_reset),
    .io_d(pueReg_io_d),
    .io_q(pueReg_io_q),
    .io_en(pueReg_io_en)
  );
  AsyncResetRegVec_w32_i0 ieReg ( // @[GPIO.scala 82:22]
    .clock(ieReg_clock),
    .reset(ieReg_reset),
    .io_d(ieReg_io_d),
    .io_q(ieReg_io_q),
    .io_en(ieReg_io_en)
  );
  AsyncResetRegVec_w32_i0 poeReg ( // @[GPIO.scala 84:22]
    .clock(poeReg_clock),
    .reset(poeReg_reset),
    .io_d(poeReg_io_d),
    .io_q(poeReg_io_q),
    .io_en(poeReg_io_en)
  );
  SynchronizerShiftReg_w32_d3 inSyncReg_inSyncReg ( // @[ShiftReg.scala 45:23]
    .clock(inSyncReg_inSyncReg_clock),
    .io_d(inSyncReg_inSyncReg_io_d),
    .io_q(inSyncReg_inSyncReg_io_q)
  );
  AsyncResetRegVec_w32_i0 iofEnReg ( // @[GPIO.scala 105:25]
    .clock(iofEnReg_clock),
    .reset(iofEnReg_reset),
    .io_d(iofEnReg_io_d),
    .io_q(iofEnReg_io_q),
    .io_en(iofEnReg_io_en)
  );
  assign auto_int_xing_out_sync_0 = intsource_auto_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_1 = intsource_auto_out_sync_1; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_2 = intsource_auto_out_sync_2; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_3 = intsource_auto_out_sync_3; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_4 = intsource_auto_out_sync_4; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_5 = intsource_auto_out_sync_5; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_6 = intsource_auto_out_sync_6; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_7 = intsource_auto_out_sync_7; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_8 = intsource_auto_out_sync_8; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_9 = intsource_auto_out_sync_9; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_10 = intsource_auto_out_sync_10; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_11 = intsource_auto_out_sync_11; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_12 = intsource_auto_out_sync_12; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_13 = intsource_auto_out_sync_13; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_14 = intsource_auto_out_sync_14; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_15 = intsource_auto_out_sync_15; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_16 = intsource_auto_out_sync_16; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_17 = intsource_auto_out_sync_17; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_18 = intsource_auto_out_sync_18; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_19 = intsource_auto_out_sync_19; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_20 = intsource_auto_out_sync_20; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_21 = intsource_auto_out_sync_21; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_22 = intsource_auto_out_sync_22; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_23 = intsource_auto_out_sync_23; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_24 = intsource_auto_out_sync_24; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_25 = intsource_auto_out_sync_25; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_26 = intsource_auto_out_sync_26; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_27 = intsource_auto_out_sync_27; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_28 = intsource_auto_out_sync_28; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_29 = intsource_auto_out_sync_29; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_30 = intsource_auto_out_sync_30; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_31 = intsource_auto_out_sync_31; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_in_a_ready = buffer_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_valid = buffer_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_size = buffer_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_source = buffer_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_data = buffer_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_iof_out_iof_0_2_i_ival = inSyncReg[2]; // @[GPIO.scala 247:49]
  assign auto_iof_out_iof_0_3_i_ival = inSyncReg[3]; // @[GPIO.scala 247:49]
  assign auto_iof_out_iof_0_4_i_ival = inSyncReg[4]; // @[GPIO.scala 247:49]
  assign auto_iof_out_iof_0_5_i_ival = inSyncReg[5]; // @[GPIO.scala 247:49]
  assign auto_iof_out_iof_0_12_i_ival = inSyncReg[12]; // @[GPIO.scala 247:49]
  assign auto_iof_out_iof_0_13_i_ival = inSyncReg[13]; // @[GPIO.scala 247:49]
  assign auto_iof_out_iof_0_14_i_ival = inSyncReg[14]; // @[GPIO.scala 247:49]
  assign auto_iof_out_iof_0_15_i_ival = inSyncReg[15]; // @[GPIO.scala 247:49]
  assign auto_iof_out_iof_0_16_i_ival = inSyncReg[16]; // @[GPIO.scala 247:49]
  assign auto_iof_out_iof_0_18_i_ival = inSyncReg[18]; // @[GPIO.scala 247:49]
  assign auto_iof_out_iof_0_20_i_ival = inSyncReg[20]; // @[GPIO.scala 247:49]
  assign auto_iof_out_iof_0_22_i_ival = inSyncReg[22]; // @[GPIO.scala 247:49]
  assign auto_io_out_pins_0_o_oval = pre_xor_oval ^ xorReg[0]; // @[GPIO.scala 235:43]
  assign auto_io_out_pins_0_o_oe = iofEnReg_io_q[0] ? iofCtrl_0_oe : swPinCtrl_0_oe; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_0_o_ie = iofEnReg_io_q[0] ? iofCtrl_0_ie : swPinCtrl_0_ie; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_1_o_oval = pre_xor_1_oval ^ xorReg[1]; // @[GPIO.scala 235:43]
  assign auto_io_out_pins_1_o_oe = iofEnReg_io_q[1] ? iofCtrl_1_oe : swPinCtrl_1_oe; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_1_o_ie = iofEnReg_io_q[1] ? iofCtrl_1_ie : swPinCtrl_1_ie; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_2_o_oval = pre_xor_2_oval ^ xorReg[2]; // @[GPIO.scala 235:43]
  assign auto_io_out_pins_2_o_oe = iofEnReg_io_q[2] ? iofCtrl_2_oe : swPinCtrl_2_oe; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_2_o_ie = iofEnReg_io_q[2] ? iofCtrl_2_ie : swPinCtrl_2_ie; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_3_o_oval = pre_xor_3_oval ^ xorReg[3]; // @[GPIO.scala 235:43]
  assign auto_io_out_pins_3_o_oe = iofEnReg_io_q[3] ? iofCtrl_3_oe : swPinCtrl_3_oe; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_3_o_ie = iofEnReg_io_q[3] ? iofCtrl_3_ie : swPinCtrl_3_ie; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_4_o_oval = pre_xor_4_oval ^ xorReg[4]; // @[GPIO.scala 235:43]
  assign auto_io_out_pins_4_o_oe = iofEnReg_io_q[4] ? iofCtrl_4_oe : swPinCtrl_4_oe; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_4_o_ie = iofEnReg_io_q[4] ? iofCtrl_4_ie : swPinCtrl_4_ie; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_5_o_oval = pre_xor_5_oval ^ xorReg[5]; // @[GPIO.scala 235:43]
  assign auto_io_out_pins_5_o_oe = iofEnReg_io_q[5] ? iofCtrl_5_oe : swPinCtrl_5_oe; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_5_o_ie = iofEnReg_io_q[5] ? iofCtrl_5_ie : swPinCtrl_5_ie; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_6_o_oval = swPinCtrl_6_oval ^ xorReg[6]; // @[GPIO.scala 235:43]
  assign auto_io_out_pins_6_o_oe = oeReg_io_q[6]; // @[GPIO.scala 200:40]
  assign auto_io_out_pins_7_o_oval = swPinCtrl_7_oval ^ xorReg[7]; // @[GPIO.scala 235:43]
  assign auto_io_out_pins_7_o_oe = oeReg_io_q[7]; // @[GPIO.scala 200:40]
  assign auto_io_out_pins_8_o_oval = swPinCtrl_8_oval ^ xorReg[8]; // @[GPIO.scala 235:43]
  assign auto_io_out_pins_8_o_oe = oeReg_io_q[8]; // @[GPIO.scala 200:40]
  assign auto_io_out_pins_9_o_oval = swPinCtrl_9_oval ^ xorReg[9]; // @[GPIO.scala 235:43]
  assign auto_io_out_pins_9_o_oe = oeReg_io_q[9]; // @[GPIO.scala 200:40]
  assign auto_io_out_pins_10_o_oval = swPinCtrl_10_oval ^ xorReg[10]; // @[GPIO.scala 235:43]
  assign auto_io_out_pins_10_o_oe = oeReg_io_q[10]; // @[GPIO.scala 200:40]
  assign auto_io_out_pins_11_o_oval = swPinCtrl_11_oval ^ xorReg[11]; // @[GPIO.scala 235:43]
  assign auto_io_out_pins_11_o_oe = oeReg_io_q[11]; // @[GPIO.scala 200:40]
  assign auto_io_out_pins_12_o_oval = pre_xor_12_oval ^ xorReg[12]; // @[GPIO.scala 235:43]
  assign auto_io_out_pins_12_o_oe = iofEnReg_io_q[12] ? iofCtrl_12_oe : swPinCtrl_12_oe; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_12_o_ie = iofEnReg_io_q[12] ? iofCtrl_12_ie : swPinCtrl_12_ie; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_13_o_oval = pre_xor_13_oval ^ xorReg[13]; // @[GPIO.scala 235:43]
  assign auto_io_out_pins_13_o_oe = iofEnReg_io_q[13] ? iofCtrl_13_oe : swPinCtrl_13_oe; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_13_o_ie = iofEnReg_io_q[13] ? iofCtrl_13_ie : swPinCtrl_13_ie; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_14_o_oval = pre_xor_14_oval ^ xorReg[14]; // @[GPIO.scala 235:43]
  assign auto_io_out_pins_14_o_oe = iofEnReg_io_q[14] ? iofCtrl_14_oe : swPinCtrl_14_oe; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_14_o_ie = iofEnReg_io_q[14] ? iofCtrl_14_ie : swPinCtrl_14_ie; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_15_o_oval = pre_xor_15_oval ^ xorReg[15]; // @[GPIO.scala 235:43]
  assign auto_io_out_pins_15_o_oe = iofEnReg_io_q[15] ? iofCtrl_15_oe : swPinCtrl_15_oe; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_15_o_ie = iofEnReg_io_q[15] ? iofCtrl_15_ie : swPinCtrl_15_ie; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_16_o_oval = pre_xor_16_oval ^ xorReg[16]; // @[GPIO.scala 235:43]
  assign auto_io_out_pins_16_o_oe = iofEnReg_io_q[16] ? iofCtrl_16_oe : swPinCtrl_16_oe; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_16_o_ie = iofEnReg_io_q[16] ? iofCtrl_16_ie : swPinCtrl_16_ie; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_17_o_oval = pre_xor_17_oval ^ xorReg[17]; // @[GPIO.scala 235:43]
  assign auto_io_out_pins_17_o_oe = iofEnReg_io_q[17] | swPinCtrl_17_oe; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_17_o_ie = iofEnReg_io_q[17] ? 1'h0 : swPinCtrl_17_ie; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_18_o_oval = pre_xor_18_oval ^ xorReg[18]; // @[GPIO.scala 235:43]
  assign auto_io_out_pins_18_o_oe = iofEnReg_io_q[18] ? iofCtrl_18_oe : swPinCtrl_18_oe; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_18_o_ie = iofEnReg_io_q[18] ? iofCtrl_18_ie : swPinCtrl_18_ie; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_19_o_oval = pre_xor_19_oval ^ xorReg[19]; // @[GPIO.scala 235:43]
  assign auto_io_out_pins_19_o_oe = iofEnReg_io_q[19] | swPinCtrl_19_oe; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_19_o_ie = iofEnReg_io_q[19] ? 1'h0 : swPinCtrl_19_ie; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_20_o_oval = pre_xor_20_oval ^ xorReg[20]; // @[GPIO.scala 235:43]
  assign auto_io_out_pins_20_o_oe = iofEnReg_io_q[20] ? iofCtrl_20_oe : swPinCtrl_20_oe; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_20_o_ie = iofEnReg_io_q[20] ? iofCtrl_20_ie : swPinCtrl_20_ie; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_21_o_oval = pre_xor_21_oval ^ xorReg[21]; // @[GPIO.scala 235:43]
  assign auto_io_out_pins_21_o_oe = iofEnReg_io_q[21] | swPinCtrl_21_oe; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_21_o_ie = iofEnReg_io_q[21] ? 1'h0 : swPinCtrl_21_ie; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_22_o_oval = pre_xor_22_oval ^ xorReg[22]; // @[GPIO.scala 235:43]
  assign auto_io_out_pins_22_o_oe = iofEnReg_io_q[22] ? iofCtrl_22_oe : swPinCtrl_22_oe; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_22_o_ie = iofEnReg_io_q[22] ? iofCtrl_22_ie : swPinCtrl_22_ie; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_23_o_oval = pre_xor_23_oval ^ xorReg[23]; // @[GPIO.scala 235:43]
  assign auto_io_out_pins_23_o_oe = iofEnReg_io_q[23] | swPinCtrl_23_oe; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_23_o_ie = iofEnReg_io_q[23] ? 1'h0 : swPinCtrl_23_ie; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_24_o_oval = pre_xor_24_oval ^ xorReg[24]; // @[GPIO.scala 235:43]
  assign auto_io_out_pins_24_o_oe = iofEnReg_io_q[24] ? iofCtrl_24_oe : swPinCtrl_24_oe; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_24_o_ie = iofEnReg_io_q[24] ? iofCtrl_24_ie : swPinCtrl_24_ie; // @[GPIO.scala 229:22]
  assign auto_io_out_pins_25_o_oval = swPinCtrl_25_oval ^ xorReg[25]; // @[GPIO.scala 235:43]
  assign auto_io_out_pins_25_o_oe = oeReg_io_q[25]; // @[GPIO.scala 200:40]
  assign auto_io_out_pins_26_o_oval = swPinCtrl_26_oval ^ xorReg[26]; // @[GPIO.scala 235:43]
  assign auto_io_out_pins_26_o_oe = oeReg_io_q[26]; // @[GPIO.scala 200:40]
  assign auto_io_out_pins_27_o_oval = swPinCtrl_27_oval ^ xorReg[27]; // @[GPIO.scala 235:43]
  assign auto_io_out_pins_27_o_oe = oeReg_io_q[27]; // @[GPIO.scala 200:40]
  assign auto_io_out_pins_28_o_oval = swPinCtrl_28_oval ^ xorReg[28]; // @[GPIO.scala 235:43]
  assign auto_io_out_pins_28_o_oe = oeReg_io_q[28]; // @[GPIO.scala 200:40]
  assign auto_io_out_pins_29_o_oval = swPinCtrl_29_oval ^ xorReg[29]; // @[GPIO.scala 235:43]
  assign auto_io_out_pins_29_o_oe = oeReg_io_q[29]; // @[GPIO.scala 200:40]
  assign auto_io_out_pins_30_o_oval = swPinCtrl_30_oval ^ xorReg[30]; // @[GPIO.scala 235:43]
  assign auto_io_out_pins_30_o_oe = oeReg_io_q[30]; // @[GPIO.scala 200:40]
  assign auto_io_out_pins_31_o_oval = swPinCtrl_31_oval ^ xorReg[31]; // @[GPIO.scala 235:43]
  assign auto_io_out_pins_31_o_oe = oeReg_io_q[31]; // @[GPIO.scala 200:40]
  assign buffer_auto_in_a_valid = auto_control_xing_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_opcode = auto_control_xing_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_param = auto_control_xing_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_size = auto_control_xing_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_source = auto_control_xing_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_address = auto_control_xing_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_mask = auto_control_xing_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_data = auto_control_xing_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_corrupt = auto_control_xing_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_d_ready = auto_control_xing_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_out_a_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign buffer_auto_out_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_data = _GEN_169 ? _GEN_201 : 32'h0; // @[RegisterRouter.scala 83:24]
  assign intsource_clock = clock;
  assign intsource_reset = reset;
  assign intsource_auto_in_0 = _bundleOut_0_0_T_18 | _bundleOut_0_0_T_22; // @[GPIO.scala 242:67]
  assign intsource_auto_in_1 = _bundleOut_0_1_T_18 | _bundleOut_0_1_T_22; // @[GPIO.scala 242:67]
  assign intsource_auto_in_2 = _bundleOut_0_2_T_18 | _bundleOut_0_2_T_22; // @[GPIO.scala 242:67]
  assign intsource_auto_in_3 = _bundleOut_0_3_T_18 | _bundleOut_0_3_T_22; // @[GPIO.scala 242:67]
  assign intsource_auto_in_4 = _bundleOut_0_4_T_18 | _bundleOut_0_4_T_22; // @[GPIO.scala 242:67]
  assign intsource_auto_in_5 = _bundleOut_0_5_T_18 | _bundleOut_0_5_T_22; // @[GPIO.scala 242:67]
  assign intsource_auto_in_6 = _bundleOut_0_6_T_18 | _bundleOut_0_6_T_22; // @[GPIO.scala 242:67]
  assign intsource_auto_in_7 = _bundleOut_0_7_T_18 | _bundleOut_0_7_T_22; // @[GPIO.scala 242:67]
  assign intsource_auto_in_8 = _bundleOut_0_8_T_18 | _bundleOut_0_8_T_22; // @[GPIO.scala 242:67]
  assign intsource_auto_in_9 = _bundleOut_0_9_T_18 | _bundleOut_0_9_T_22; // @[GPIO.scala 242:67]
  assign intsource_auto_in_10 = _bundleOut_0_10_T_18 | _bundleOut_0_10_T_22; // @[GPIO.scala 242:67]
  assign intsource_auto_in_11 = _bundleOut_0_11_T_18 | _bundleOut_0_11_T_22; // @[GPIO.scala 242:67]
  assign intsource_auto_in_12 = _bundleOut_0_12_T_18 | _bundleOut_0_12_T_22; // @[GPIO.scala 242:67]
  assign intsource_auto_in_13 = _bundleOut_0_13_T_18 | _bundleOut_0_13_T_22; // @[GPIO.scala 242:67]
  assign intsource_auto_in_14 = _bundleOut_0_14_T_18 | _bundleOut_0_14_T_22; // @[GPIO.scala 242:67]
  assign intsource_auto_in_15 = _bundleOut_0_15_T_18 | _bundleOut_0_15_T_22; // @[GPIO.scala 242:67]
  assign intsource_auto_in_16 = _bundleOut_0_16_T_18 | _bundleOut_0_16_T_22; // @[GPIO.scala 242:67]
  assign intsource_auto_in_17 = _bundleOut_0_17_T_18 | _bundleOut_0_17_T_22; // @[GPIO.scala 242:67]
  assign intsource_auto_in_18 = _bundleOut_0_18_T_18 | _bundleOut_0_18_T_22; // @[GPIO.scala 242:67]
  assign intsource_auto_in_19 = _bundleOut_0_19_T_18 | _bundleOut_0_19_T_22; // @[GPIO.scala 242:67]
  assign intsource_auto_in_20 = _bundleOut_0_20_T_18 | _bundleOut_0_20_T_22; // @[GPIO.scala 242:67]
  assign intsource_auto_in_21 = _bundleOut_0_21_T_18 | _bundleOut_0_21_T_22; // @[GPIO.scala 242:67]
  assign intsource_auto_in_22 = _bundleOut_0_22_T_18 | _bundleOut_0_22_T_22; // @[GPIO.scala 242:67]
  assign intsource_auto_in_23 = _bundleOut_0_23_T_18 | _bundleOut_0_23_T_22; // @[GPIO.scala 242:67]
  assign intsource_auto_in_24 = _bundleOut_0_24_T_18 | _bundleOut_0_24_T_22; // @[GPIO.scala 242:67]
  assign intsource_auto_in_25 = _bundleOut_0_25_T_18 | _bundleOut_0_25_T_22; // @[GPIO.scala 242:67]
  assign intsource_auto_in_26 = _bundleOut_0_26_T_18 | _bundleOut_0_26_T_22; // @[GPIO.scala 242:67]
  assign intsource_auto_in_27 = _bundleOut_0_27_T_18 | _bundleOut_0_27_T_22; // @[GPIO.scala 242:67]
  assign intsource_auto_in_28 = _bundleOut_0_28_T_18 | _bundleOut_0_28_T_22; // @[GPIO.scala 242:67]
  assign intsource_auto_in_29 = _bundleOut_0_29_T_18 | _bundleOut_0_29_T_22; // @[GPIO.scala 242:67]
  assign intsource_auto_in_30 = _bundleOut_0_30_T_18 | _bundleOut_0_30_T_22; // @[GPIO.scala 242:67]
  assign intsource_auto_in_31 = _bundleOut_0_31_T_18 | _bundleOut_0_31_T_22; // @[GPIO.scala 242:67]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_param = buffer_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign monitor_io_in_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign oeReg_clock = clock;
  assign oeReg_reset = reset;
  assign oeReg_io_d = buffer_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign oeReg_io_en = out_wivalid_9 & out_wimask; // @[RegisterRouter.scala 83:24]
  assign pueReg_clock = clock;
  assign pueReg_reset = reset;
  assign pueReg_io_d = buffer_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign pueReg_io_en = out_wivalid_19 & out_wimask; // @[RegisterRouter.scala 83:24]
  assign ieReg_clock = clock;
  assign ieReg_reset = reset;
  assign ieReg_io_d = buffer_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign ieReg_io_en = out_wivalid_5 & out_wimask; // @[RegisterRouter.scala 83:24]
  assign poeReg_clock = clock;
  assign poeReg_reset = reset;
  assign poeReg_io_d = 32'h0;
  assign poeReg_io_en = 1'h0;
  assign inSyncReg_inSyncReg_clock = clock;
  assign inSyncReg_inSyncReg_io_d = {inVal_hi,inVal_lo}; // @[GPIO.scala 88:41]
  assign iofEnReg_clock = clock;
  assign iofEnReg_reset = reset;
  assign iofEnReg_io_d = buffer_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign iofEnReg_io_en = out_wivalid_3 & out_wimask; // @[RegisterRouter.scala 83:24]
  always @(posedge clock) begin
    if (reset) begin // @[GPIO.scala 77:20]
      portReg <= 32'h0; // @[GPIO.scala 77:20]
    end else if (out_f_wivalid_13) begin // @[RegField.scala 74:88]
      portReg <= bundleIn_0_a_bits_data; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[GPIO.scala 81:23]
      dsReg_0 <= 32'h0; // @[GPIO.scala 81:23]
    end else if (out_f_wivalid_1) begin // @[RegField.scala 74:88]
      dsReg_0 <= bundleIn_0_a_bits_data; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[GPIO.scala 90:23]
      valueReg <= 32'h0; // @[GPIO.scala 90:23]
    end else begin
      valueReg <= inSyncReg; // @[GPIO.scala 90:23]
    end
    if (reset) begin // @[GPIO.scala 93:22]
      highIeReg <= 32'h0; // @[GPIO.scala 93:22]
    end else if (out_f_wivalid_2) begin // @[RegField.scala 74:88]
      highIeReg <= bundleIn_0_a_bits_data; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[GPIO.scala 94:22]
      lowIeReg <= 32'h0; // @[GPIO.scala 94:22]
    end else if (out_f_wivalid_11) begin // @[RegField.scala 74:88]
      lowIeReg <= bundleIn_0_a_bits_data; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[GPIO.scala 95:22]
      riseIeReg <= 32'h0; // @[GPIO.scala 95:22]
    end else if (out_f_wivalid_6) begin // @[RegField.scala 74:88]
      riseIeReg <= bundleIn_0_a_bits_data; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[GPIO.scala 96:22]
      fallIeReg <= 32'h0; // @[GPIO.scala 96:22]
    end else if (out_f_wivalid_17) begin // @[RegField.scala 74:88]
      fallIeReg <= bundleIn_0_a_bits_data; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[GPIO.scala 97:22]
      highIpReg <= 32'h0; // @[GPIO.scala 97:22]
    end else begin
      highIpReg <= _out_highIpReg_T_4; // @[RegField.scala 128:56]
    end
    if (reset) begin // @[GPIO.scala 98:22]
      lowIpReg <= 32'h0; // @[GPIO.scala 98:22]
    end else begin
      lowIpReg <= _out_lowIpReg_T_4; // @[RegField.scala 128:56]
    end
    if (reset) begin // @[GPIO.scala 99:22]
      riseIpReg <= 32'h0; // @[GPIO.scala 99:22]
    end else begin
      riseIpReg <= _out_riseIpReg_T_4; // @[RegField.scala 128:56]
    end
    if (reset) begin // @[GPIO.scala 100:22]
      fallIpReg <= 32'h0; // @[GPIO.scala 100:22]
    end else begin
      fallIpReg <= _out_fallIpReg_T_4; // @[RegField.scala 128:56]
    end
    if (reset) begin // @[GPIO.scala 101:30]
      passthruHighIeReg <= 32'h0; // @[GPIO.scala 101:30]
    end else if (out_f_wivalid_10) begin // @[RegField.scala 74:88]
      passthruHighIeReg <= bundleIn_0_a_bits_data; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[GPIO.scala 102:30]
      passthruLowIeReg <= 32'h0; // @[GPIO.scala 102:30]
    end else if (out_f_wivalid_14) begin // @[RegField.scala 74:88]
      passthruLowIeReg <= bundleIn_0_a_bits_data; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[GPIO.scala 106:22]
      iofSelReg <= 32'h0; // @[GPIO.scala 106:22]
    end else if (out_f_wivalid_20) begin // @[RegField.scala 74:88]
      iofSelReg <= bundleIn_0_a_bits_data; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[GPIO.scala 109:22]
      xorReg <= 32'h0; // @[GPIO.scala 109:22]
    end else if (out_f_wivalid_15) begin // @[RegField.scala 74:88]
      xorReg <= bundleIn_0_a_bits_data; // @[RegField.scala 74:92]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  portReg = _RAND_0[31:0];
  _RAND_1 = {1{`RANDOM}};
  dsReg_0 = _RAND_1[31:0];
  _RAND_2 = {1{`RANDOM}};
  valueReg = _RAND_2[31:0];
  _RAND_3 = {1{`RANDOM}};
  highIeReg = _RAND_3[31:0];
  _RAND_4 = {1{`RANDOM}};
  lowIeReg = _RAND_4[31:0];
  _RAND_5 = {1{`RANDOM}};
  riseIeReg = _RAND_5[31:0];
  _RAND_6 = {1{`RANDOM}};
  fallIeReg = _RAND_6[31:0];
  _RAND_7 = {1{`RANDOM}};
  highIpReg = _RAND_7[31:0];
  _RAND_8 = {1{`RANDOM}};
  lowIpReg = _RAND_8[31:0];
  _RAND_9 = {1{`RANDOM}};
  riseIpReg = _RAND_9[31:0];
  _RAND_10 = {1{`RANDOM}};
  fallIpReg = _RAND_10[31:0];
  _RAND_11 = {1{`RANDOM}};
  passthruHighIeReg = _RAND_11[31:0];
  _RAND_12 = {1{`RANDOM}};
  passthruLowIeReg = _RAND_12[31:0];
  _RAND_13 = {1{`RANDOM}};
  iofSelReg = _RAND_13[31:0];
  _RAND_14 = {1{`RANDOM}};
  xorReg = _RAND_14[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ClockSinkDomain_9(
  output        auto_gpio_0_int_xing_out_sync_0,
  output        auto_gpio_0_int_xing_out_sync_1,
  output        auto_gpio_0_int_xing_out_sync_2,
  output        auto_gpio_0_int_xing_out_sync_3,
  output        auto_gpio_0_int_xing_out_sync_4,
  output        auto_gpio_0_int_xing_out_sync_5,
  output        auto_gpio_0_int_xing_out_sync_6,
  output        auto_gpio_0_int_xing_out_sync_7,
  output        auto_gpio_0_int_xing_out_sync_8,
  output        auto_gpio_0_int_xing_out_sync_9,
  output        auto_gpio_0_int_xing_out_sync_10,
  output        auto_gpio_0_int_xing_out_sync_11,
  output        auto_gpio_0_int_xing_out_sync_12,
  output        auto_gpio_0_int_xing_out_sync_13,
  output        auto_gpio_0_int_xing_out_sync_14,
  output        auto_gpio_0_int_xing_out_sync_15,
  output        auto_gpio_0_int_xing_out_sync_16,
  output        auto_gpio_0_int_xing_out_sync_17,
  output        auto_gpio_0_int_xing_out_sync_18,
  output        auto_gpio_0_int_xing_out_sync_19,
  output        auto_gpio_0_int_xing_out_sync_20,
  output        auto_gpio_0_int_xing_out_sync_21,
  output        auto_gpio_0_int_xing_out_sync_22,
  output        auto_gpio_0_int_xing_out_sync_23,
  output        auto_gpio_0_int_xing_out_sync_24,
  output        auto_gpio_0_int_xing_out_sync_25,
  output        auto_gpio_0_int_xing_out_sync_26,
  output        auto_gpio_0_int_xing_out_sync_27,
  output        auto_gpio_0_int_xing_out_sync_28,
  output        auto_gpio_0_int_xing_out_sync_29,
  output        auto_gpio_0_int_xing_out_sync_30,
  output        auto_gpio_0_int_xing_out_sync_31,
  output        auto_gpio_0_control_xing_in_a_ready,
  input         auto_gpio_0_control_xing_in_a_valid,
  input  [2:0]  auto_gpio_0_control_xing_in_a_bits_opcode,
  input  [2:0]  auto_gpio_0_control_xing_in_a_bits_param,
  input  [1:0]  auto_gpio_0_control_xing_in_a_bits_size,
  input  [6:0]  auto_gpio_0_control_xing_in_a_bits_source,
  input  [28:0] auto_gpio_0_control_xing_in_a_bits_address,
  input  [3:0]  auto_gpio_0_control_xing_in_a_bits_mask,
  input  [31:0] auto_gpio_0_control_xing_in_a_bits_data,
  input         auto_gpio_0_control_xing_in_a_bits_corrupt,
  input         auto_gpio_0_control_xing_in_d_ready,
  output        auto_gpio_0_control_xing_in_d_valid,
  output [2:0]  auto_gpio_0_control_xing_in_d_bits_opcode,
  output [1:0]  auto_gpio_0_control_xing_in_d_bits_size,
  output [6:0]  auto_gpio_0_control_xing_in_d_bits_source,
  output [31:0] auto_gpio_0_control_xing_in_d_bits_data,
  input         auto_gpio_0_iof_out_iof_0_0_o_oval,
  input         auto_gpio_0_iof_out_iof_0_1_o_oval,
  output        auto_gpio_0_iof_out_iof_0_2_i_ival,
  input         auto_gpio_0_iof_out_iof_0_2_o_oval,
  input         auto_gpio_0_iof_out_iof_0_2_o_oe,
  input         auto_gpio_0_iof_out_iof_0_2_o_ie,
  output        auto_gpio_0_iof_out_iof_0_3_i_ival,
  input         auto_gpio_0_iof_out_iof_0_3_o_oval,
  input         auto_gpio_0_iof_out_iof_0_3_o_oe,
  input         auto_gpio_0_iof_out_iof_0_3_o_ie,
  output        auto_gpio_0_iof_out_iof_0_4_i_ival,
  input         auto_gpio_0_iof_out_iof_0_4_o_oval,
  input         auto_gpio_0_iof_out_iof_0_4_o_oe,
  input         auto_gpio_0_iof_out_iof_0_4_o_ie,
  output        auto_gpio_0_iof_out_iof_0_5_i_ival,
  input         auto_gpio_0_iof_out_iof_0_5_o_oval,
  input         auto_gpio_0_iof_out_iof_0_5_o_oe,
  input         auto_gpio_0_iof_out_iof_0_5_o_ie,
  output        auto_gpio_0_iof_out_iof_0_12_i_ival,
  input         auto_gpio_0_iof_out_iof_0_12_o_oe,
  output        auto_gpio_0_iof_out_iof_0_13_i_ival,
  input         auto_gpio_0_iof_out_iof_0_13_o_oe,
  output        auto_gpio_0_iof_out_iof_0_14_i_ival,
  input         auto_gpio_0_iof_out_iof_0_14_o_oe,
  output        auto_gpio_0_iof_out_iof_0_15_i_ival,
  input         auto_gpio_0_iof_out_iof_0_15_o_oe,
  output        auto_gpio_0_iof_out_iof_0_16_i_ival,
  input         auto_gpio_0_iof_out_iof_0_17_o_oval,
  output        auto_gpio_0_iof_out_iof_0_18_i_ival,
  input         auto_gpio_0_iof_out_iof_0_19_o_oval,
  output        auto_gpio_0_iof_out_iof_0_20_i_ival,
  input         auto_gpio_0_iof_out_iof_0_21_o_oval,
  output        auto_gpio_0_iof_out_iof_0_22_i_ival,
  input         auto_gpio_0_iof_out_iof_0_23_o_oval,
  input         auto_gpio_0_iof_out_iof_0_24_o_oval,
  input         auto_gpio_0_iof_out_iof_1_12_o_oval,
  input         auto_gpio_0_iof_out_iof_1_13_o_oval,
  input         auto_gpio_0_iof_out_iof_1_14_o_oval,
  input         auto_gpio_0_iof_out_iof_1_15_o_oval,
  input         auto_gpio_0_iof_out_iof_1_16_o_oval,
  input         auto_gpio_0_iof_out_iof_1_17_o_oval,
  input         auto_gpio_0_iof_out_iof_1_18_o_oval,
  input         auto_gpio_0_iof_out_iof_1_19_o_oval,
  input         auto_gpio_0_iof_out_iof_1_20_o_oval,
  input         auto_gpio_0_iof_out_iof_1_21_o_oval,
  input         auto_gpio_0_iof_out_iof_1_22_o_oval,
  input         auto_gpio_0_iof_out_iof_1_23_o_oval,
  input         auto_gpio_0_io_out_pins_0_i_ival,
  output        auto_gpio_0_io_out_pins_0_o_oval,
  output        auto_gpio_0_io_out_pins_0_o_oe,
  output        auto_gpio_0_io_out_pins_0_o_ie,
  input         auto_gpio_0_io_out_pins_1_i_ival,
  output        auto_gpio_0_io_out_pins_1_o_oval,
  output        auto_gpio_0_io_out_pins_1_o_oe,
  output        auto_gpio_0_io_out_pins_1_o_ie,
  input         auto_gpio_0_io_out_pins_2_i_ival,
  output        auto_gpio_0_io_out_pins_2_o_oval,
  output        auto_gpio_0_io_out_pins_2_o_oe,
  output        auto_gpio_0_io_out_pins_2_o_ie,
  input         auto_gpio_0_io_out_pins_3_i_ival,
  output        auto_gpio_0_io_out_pins_3_o_oval,
  output        auto_gpio_0_io_out_pins_3_o_oe,
  output        auto_gpio_0_io_out_pins_3_o_ie,
  input         auto_gpio_0_io_out_pins_4_i_ival,
  output        auto_gpio_0_io_out_pins_4_o_oval,
  output        auto_gpio_0_io_out_pins_4_o_oe,
  output        auto_gpio_0_io_out_pins_4_o_ie,
  input         auto_gpio_0_io_out_pins_5_i_ival,
  output        auto_gpio_0_io_out_pins_5_o_oval,
  output        auto_gpio_0_io_out_pins_5_o_oe,
  output        auto_gpio_0_io_out_pins_5_o_ie,
  input         auto_gpio_0_io_out_pins_6_i_ival,
  output        auto_gpio_0_io_out_pins_6_o_oval,
  output        auto_gpio_0_io_out_pins_6_o_oe,
  input         auto_gpio_0_io_out_pins_7_i_ival,
  output        auto_gpio_0_io_out_pins_7_o_oval,
  output        auto_gpio_0_io_out_pins_7_o_oe,
  input         auto_gpio_0_io_out_pins_8_i_ival,
  output        auto_gpio_0_io_out_pins_8_o_oval,
  output        auto_gpio_0_io_out_pins_8_o_oe,
  input         auto_gpio_0_io_out_pins_9_i_ival,
  output        auto_gpio_0_io_out_pins_9_o_oval,
  output        auto_gpio_0_io_out_pins_9_o_oe,
  input         auto_gpio_0_io_out_pins_10_i_ival,
  output        auto_gpio_0_io_out_pins_10_o_oval,
  output        auto_gpio_0_io_out_pins_10_o_oe,
  input         auto_gpio_0_io_out_pins_11_i_ival,
  output        auto_gpio_0_io_out_pins_11_o_oval,
  output        auto_gpio_0_io_out_pins_11_o_oe,
  input         auto_gpio_0_io_out_pins_12_i_ival,
  output        auto_gpio_0_io_out_pins_12_o_oval,
  output        auto_gpio_0_io_out_pins_12_o_oe,
  output        auto_gpio_0_io_out_pins_12_o_ie,
  input         auto_gpio_0_io_out_pins_13_i_ival,
  output        auto_gpio_0_io_out_pins_13_o_oval,
  output        auto_gpio_0_io_out_pins_13_o_oe,
  output        auto_gpio_0_io_out_pins_13_o_ie,
  input         auto_gpio_0_io_out_pins_14_i_ival,
  output        auto_gpio_0_io_out_pins_14_o_oval,
  output        auto_gpio_0_io_out_pins_14_o_oe,
  output        auto_gpio_0_io_out_pins_14_o_ie,
  input         auto_gpio_0_io_out_pins_15_i_ival,
  output        auto_gpio_0_io_out_pins_15_o_oval,
  output        auto_gpio_0_io_out_pins_15_o_oe,
  output        auto_gpio_0_io_out_pins_15_o_ie,
  input         auto_gpio_0_io_out_pins_16_i_ival,
  output        auto_gpio_0_io_out_pins_16_o_oval,
  output        auto_gpio_0_io_out_pins_16_o_oe,
  output        auto_gpio_0_io_out_pins_16_o_ie,
  input         auto_gpio_0_io_out_pins_17_i_ival,
  output        auto_gpio_0_io_out_pins_17_o_oval,
  output        auto_gpio_0_io_out_pins_17_o_oe,
  output        auto_gpio_0_io_out_pins_17_o_ie,
  input         auto_gpio_0_io_out_pins_18_i_ival,
  output        auto_gpio_0_io_out_pins_18_o_oval,
  output        auto_gpio_0_io_out_pins_18_o_oe,
  output        auto_gpio_0_io_out_pins_18_o_ie,
  input         auto_gpio_0_io_out_pins_19_i_ival,
  output        auto_gpio_0_io_out_pins_19_o_oval,
  output        auto_gpio_0_io_out_pins_19_o_oe,
  output        auto_gpio_0_io_out_pins_19_o_ie,
  input         auto_gpio_0_io_out_pins_20_i_ival,
  output        auto_gpio_0_io_out_pins_20_o_oval,
  output        auto_gpio_0_io_out_pins_20_o_oe,
  output        auto_gpio_0_io_out_pins_20_o_ie,
  input         auto_gpio_0_io_out_pins_21_i_ival,
  output        auto_gpio_0_io_out_pins_21_o_oval,
  output        auto_gpio_0_io_out_pins_21_o_oe,
  output        auto_gpio_0_io_out_pins_21_o_ie,
  input         auto_gpio_0_io_out_pins_22_i_ival,
  output        auto_gpio_0_io_out_pins_22_o_oval,
  output        auto_gpio_0_io_out_pins_22_o_oe,
  output        auto_gpio_0_io_out_pins_22_o_ie,
  input         auto_gpio_0_io_out_pins_23_i_ival,
  output        auto_gpio_0_io_out_pins_23_o_oval,
  output        auto_gpio_0_io_out_pins_23_o_oe,
  output        auto_gpio_0_io_out_pins_23_o_ie,
  input         auto_gpio_0_io_out_pins_24_i_ival,
  output        auto_gpio_0_io_out_pins_24_o_oval,
  output        auto_gpio_0_io_out_pins_24_o_oe,
  output        auto_gpio_0_io_out_pins_24_o_ie,
  input         auto_gpio_0_io_out_pins_25_i_ival,
  output        auto_gpio_0_io_out_pins_25_o_oval,
  output        auto_gpio_0_io_out_pins_25_o_oe,
  input         auto_gpio_0_io_out_pins_26_i_ival,
  output        auto_gpio_0_io_out_pins_26_o_oval,
  output        auto_gpio_0_io_out_pins_26_o_oe,
  input         auto_gpio_0_io_out_pins_27_i_ival,
  output        auto_gpio_0_io_out_pins_27_o_oval,
  output        auto_gpio_0_io_out_pins_27_o_oe,
  input         auto_gpio_0_io_out_pins_28_i_ival,
  output        auto_gpio_0_io_out_pins_28_o_oval,
  output        auto_gpio_0_io_out_pins_28_o_oe,
  input         auto_gpio_0_io_out_pins_29_i_ival,
  output        auto_gpio_0_io_out_pins_29_o_oval,
  output        auto_gpio_0_io_out_pins_29_o_oe,
  input         auto_gpio_0_io_out_pins_30_i_ival,
  output        auto_gpio_0_io_out_pins_30_o_oval,
  output        auto_gpio_0_io_out_pins_30_o_oe,
  input         auto_gpio_0_io_out_pins_31_i_ival,
  output        auto_gpio_0_io_out_pins_31_o_oval,
  output        auto_gpio_0_io_out_pins_31_o_oe,
  input         auto_clock_in_clock,
  input         auto_clock_in_reset
);
  wire  gpio_0_clock; // @[GPIO.scala 282:51]
  wire  gpio_0_reset; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_int_xing_out_sync_0; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_int_xing_out_sync_1; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_int_xing_out_sync_2; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_int_xing_out_sync_3; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_int_xing_out_sync_4; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_int_xing_out_sync_5; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_int_xing_out_sync_6; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_int_xing_out_sync_7; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_int_xing_out_sync_8; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_int_xing_out_sync_9; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_int_xing_out_sync_10; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_int_xing_out_sync_11; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_int_xing_out_sync_12; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_int_xing_out_sync_13; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_int_xing_out_sync_14; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_int_xing_out_sync_15; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_int_xing_out_sync_16; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_int_xing_out_sync_17; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_int_xing_out_sync_18; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_int_xing_out_sync_19; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_int_xing_out_sync_20; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_int_xing_out_sync_21; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_int_xing_out_sync_22; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_int_xing_out_sync_23; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_int_xing_out_sync_24; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_int_xing_out_sync_25; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_int_xing_out_sync_26; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_int_xing_out_sync_27; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_int_xing_out_sync_28; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_int_xing_out_sync_29; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_int_xing_out_sync_30; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_int_xing_out_sync_31; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_control_xing_in_a_ready; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_control_xing_in_a_valid; // @[GPIO.scala 282:51]
  wire [2:0] gpio_0_auto_control_xing_in_a_bits_opcode; // @[GPIO.scala 282:51]
  wire [2:0] gpio_0_auto_control_xing_in_a_bits_param; // @[GPIO.scala 282:51]
  wire [1:0] gpio_0_auto_control_xing_in_a_bits_size; // @[GPIO.scala 282:51]
  wire [6:0] gpio_0_auto_control_xing_in_a_bits_source; // @[GPIO.scala 282:51]
  wire [28:0] gpio_0_auto_control_xing_in_a_bits_address; // @[GPIO.scala 282:51]
  wire [3:0] gpio_0_auto_control_xing_in_a_bits_mask; // @[GPIO.scala 282:51]
  wire [31:0] gpio_0_auto_control_xing_in_a_bits_data; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_control_xing_in_a_bits_corrupt; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_control_xing_in_d_ready; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_control_xing_in_d_valid; // @[GPIO.scala 282:51]
  wire [2:0] gpio_0_auto_control_xing_in_d_bits_opcode; // @[GPIO.scala 282:51]
  wire [1:0] gpio_0_auto_control_xing_in_d_bits_size; // @[GPIO.scala 282:51]
  wire [6:0] gpio_0_auto_control_xing_in_d_bits_source; // @[GPIO.scala 282:51]
  wire [31:0] gpio_0_auto_control_xing_in_d_bits_data; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_0_0_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_0_1_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_0_2_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_0_2_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_0_2_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_0_2_o_ie; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_0_3_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_0_3_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_0_3_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_0_3_o_ie; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_0_4_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_0_4_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_0_4_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_0_4_o_ie; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_0_5_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_0_5_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_0_5_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_0_5_o_ie; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_0_12_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_0_12_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_0_13_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_0_13_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_0_14_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_0_14_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_0_15_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_0_15_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_0_16_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_0_17_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_0_18_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_0_19_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_0_20_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_0_21_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_0_22_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_0_23_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_0_24_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_1_12_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_1_13_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_1_14_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_1_15_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_1_16_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_1_17_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_1_18_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_1_19_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_1_20_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_1_21_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_1_22_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_iof_out_iof_1_23_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_0_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_0_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_0_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_0_o_ie; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_1_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_1_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_1_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_1_o_ie; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_2_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_2_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_2_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_2_o_ie; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_3_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_3_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_3_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_3_o_ie; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_4_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_4_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_4_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_4_o_ie; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_5_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_5_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_5_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_5_o_ie; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_6_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_6_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_6_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_7_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_7_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_7_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_8_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_8_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_8_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_9_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_9_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_9_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_10_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_10_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_10_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_11_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_11_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_11_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_12_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_12_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_12_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_12_o_ie; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_13_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_13_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_13_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_13_o_ie; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_14_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_14_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_14_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_14_o_ie; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_15_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_15_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_15_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_15_o_ie; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_16_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_16_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_16_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_16_o_ie; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_17_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_17_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_17_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_17_o_ie; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_18_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_18_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_18_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_18_o_ie; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_19_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_19_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_19_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_19_o_ie; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_20_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_20_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_20_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_20_o_ie; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_21_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_21_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_21_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_21_o_ie; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_22_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_22_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_22_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_22_o_ie; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_23_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_23_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_23_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_23_o_ie; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_24_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_24_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_24_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_24_o_ie; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_25_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_25_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_25_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_26_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_26_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_26_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_27_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_27_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_27_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_28_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_28_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_28_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_29_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_29_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_29_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_30_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_30_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_30_o_oe; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_31_i_ival; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_31_o_oval; // @[GPIO.scala 282:51]
  wire  gpio_0_auto_io_out_pins_31_o_oe; // @[GPIO.scala 282:51]
  TLGPIO gpio_0 ( // @[GPIO.scala 282:51]
    .clock(gpio_0_clock),
    .reset(gpio_0_reset),
    .auto_int_xing_out_sync_0(gpio_0_auto_int_xing_out_sync_0),
    .auto_int_xing_out_sync_1(gpio_0_auto_int_xing_out_sync_1),
    .auto_int_xing_out_sync_2(gpio_0_auto_int_xing_out_sync_2),
    .auto_int_xing_out_sync_3(gpio_0_auto_int_xing_out_sync_3),
    .auto_int_xing_out_sync_4(gpio_0_auto_int_xing_out_sync_4),
    .auto_int_xing_out_sync_5(gpio_0_auto_int_xing_out_sync_5),
    .auto_int_xing_out_sync_6(gpio_0_auto_int_xing_out_sync_6),
    .auto_int_xing_out_sync_7(gpio_0_auto_int_xing_out_sync_7),
    .auto_int_xing_out_sync_8(gpio_0_auto_int_xing_out_sync_8),
    .auto_int_xing_out_sync_9(gpio_0_auto_int_xing_out_sync_9),
    .auto_int_xing_out_sync_10(gpio_0_auto_int_xing_out_sync_10),
    .auto_int_xing_out_sync_11(gpio_0_auto_int_xing_out_sync_11),
    .auto_int_xing_out_sync_12(gpio_0_auto_int_xing_out_sync_12),
    .auto_int_xing_out_sync_13(gpio_0_auto_int_xing_out_sync_13),
    .auto_int_xing_out_sync_14(gpio_0_auto_int_xing_out_sync_14),
    .auto_int_xing_out_sync_15(gpio_0_auto_int_xing_out_sync_15),
    .auto_int_xing_out_sync_16(gpio_0_auto_int_xing_out_sync_16),
    .auto_int_xing_out_sync_17(gpio_0_auto_int_xing_out_sync_17),
    .auto_int_xing_out_sync_18(gpio_0_auto_int_xing_out_sync_18),
    .auto_int_xing_out_sync_19(gpio_0_auto_int_xing_out_sync_19),
    .auto_int_xing_out_sync_20(gpio_0_auto_int_xing_out_sync_20),
    .auto_int_xing_out_sync_21(gpio_0_auto_int_xing_out_sync_21),
    .auto_int_xing_out_sync_22(gpio_0_auto_int_xing_out_sync_22),
    .auto_int_xing_out_sync_23(gpio_0_auto_int_xing_out_sync_23),
    .auto_int_xing_out_sync_24(gpio_0_auto_int_xing_out_sync_24),
    .auto_int_xing_out_sync_25(gpio_0_auto_int_xing_out_sync_25),
    .auto_int_xing_out_sync_26(gpio_0_auto_int_xing_out_sync_26),
    .auto_int_xing_out_sync_27(gpio_0_auto_int_xing_out_sync_27),
    .auto_int_xing_out_sync_28(gpio_0_auto_int_xing_out_sync_28),
    .auto_int_xing_out_sync_29(gpio_0_auto_int_xing_out_sync_29),
    .auto_int_xing_out_sync_30(gpio_0_auto_int_xing_out_sync_30),
    .auto_int_xing_out_sync_31(gpio_0_auto_int_xing_out_sync_31),
    .auto_control_xing_in_a_ready(gpio_0_auto_control_xing_in_a_ready),
    .auto_control_xing_in_a_valid(gpio_0_auto_control_xing_in_a_valid),
    .auto_control_xing_in_a_bits_opcode(gpio_0_auto_control_xing_in_a_bits_opcode),
    .auto_control_xing_in_a_bits_param(gpio_0_auto_control_xing_in_a_bits_param),
    .auto_control_xing_in_a_bits_size(gpio_0_auto_control_xing_in_a_bits_size),
    .auto_control_xing_in_a_bits_source(gpio_0_auto_control_xing_in_a_bits_source),
    .auto_control_xing_in_a_bits_address(gpio_0_auto_control_xing_in_a_bits_address),
    .auto_control_xing_in_a_bits_mask(gpio_0_auto_control_xing_in_a_bits_mask),
    .auto_control_xing_in_a_bits_data(gpio_0_auto_control_xing_in_a_bits_data),
    .auto_control_xing_in_a_bits_corrupt(gpio_0_auto_control_xing_in_a_bits_corrupt),
    .auto_control_xing_in_d_ready(gpio_0_auto_control_xing_in_d_ready),
    .auto_control_xing_in_d_valid(gpio_0_auto_control_xing_in_d_valid),
    .auto_control_xing_in_d_bits_opcode(gpio_0_auto_control_xing_in_d_bits_opcode),
    .auto_control_xing_in_d_bits_size(gpio_0_auto_control_xing_in_d_bits_size),
    .auto_control_xing_in_d_bits_source(gpio_0_auto_control_xing_in_d_bits_source),
    .auto_control_xing_in_d_bits_data(gpio_0_auto_control_xing_in_d_bits_data),
    .auto_iof_out_iof_0_0_o_oval(gpio_0_auto_iof_out_iof_0_0_o_oval),
    .auto_iof_out_iof_0_1_o_oval(gpio_0_auto_iof_out_iof_0_1_o_oval),
    .auto_iof_out_iof_0_2_i_ival(gpio_0_auto_iof_out_iof_0_2_i_ival),
    .auto_iof_out_iof_0_2_o_oval(gpio_0_auto_iof_out_iof_0_2_o_oval),
    .auto_iof_out_iof_0_2_o_oe(gpio_0_auto_iof_out_iof_0_2_o_oe),
    .auto_iof_out_iof_0_2_o_ie(gpio_0_auto_iof_out_iof_0_2_o_ie),
    .auto_iof_out_iof_0_3_i_ival(gpio_0_auto_iof_out_iof_0_3_i_ival),
    .auto_iof_out_iof_0_3_o_oval(gpio_0_auto_iof_out_iof_0_3_o_oval),
    .auto_iof_out_iof_0_3_o_oe(gpio_0_auto_iof_out_iof_0_3_o_oe),
    .auto_iof_out_iof_0_3_o_ie(gpio_0_auto_iof_out_iof_0_3_o_ie),
    .auto_iof_out_iof_0_4_i_ival(gpio_0_auto_iof_out_iof_0_4_i_ival),
    .auto_iof_out_iof_0_4_o_oval(gpio_0_auto_iof_out_iof_0_4_o_oval),
    .auto_iof_out_iof_0_4_o_oe(gpio_0_auto_iof_out_iof_0_4_o_oe),
    .auto_iof_out_iof_0_4_o_ie(gpio_0_auto_iof_out_iof_0_4_o_ie),
    .auto_iof_out_iof_0_5_i_ival(gpio_0_auto_iof_out_iof_0_5_i_ival),
    .auto_iof_out_iof_0_5_o_oval(gpio_0_auto_iof_out_iof_0_5_o_oval),
    .auto_iof_out_iof_0_5_o_oe(gpio_0_auto_iof_out_iof_0_5_o_oe),
    .auto_iof_out_iof_0_5_o_ie(gpio_0_auto_iof_out_iof_0_5_o_ie),
    .auto_iof_out_iof_0_12_i_ival(gpio_0_auto_iof_out_iof_0_12_i_ival),
    .auto_iof_out_iof_0_12_o_oe(gpio_0_auto_iof_out_iof_0_12_o_oe),
    .auto_iof_out_iof_0_13_i_ival(gpio_0_auto_iof_out_iof_0_13_i_ival),
    .auto_iof_out_iof_0_13_o_oe(gpio_0_auto_iof_out_iof_0_13_o_oe),
    .auto_iof_out_iof_0_14_i_ival(gpio_0_auto_iof_out_iof_0_14_i_ival),
    .auto_iof_out_iof_0_14_o_oe(gpio_0_auto_iof_out_iof_0_14_o_oe),
    .auto_iof_out_iof_0_15_i_ival(gpio_0_auto_iof_out_iof_0_15_i_ival),
    .auto_iof_out_iof_0_15_o_oe(gpio_0_auto_iof_out_iof_0_15_o_oe),
    .auto_iof_out_iof_0_16_i_ival(gpio_0_auto_iof_out_iof_0_16_i_ival),
    .auto_iof_out_iof_0_17_o_oval(gpio_0_auto_iof_out_iof_0_17_o_oval),
    .auto_iof_out_iof_0_18_i_ival(gpio_0_auto_iof_out_iof_0_18_i_ival),
    .auto_iof_out_iof_0_19_o_oval(gpio_0_auto_iof_out_iof_0_19_o_oval),
    .auto_iof_out_iof_0_20_i_ival(gpio_0_auto_iof_out_iof_0_20_i_ival),
    .auto_iof_out_iof_0_21_o_oval(gpio_0_auto_iof_out_iof_0_21_o_oval),
    .auto_iof_out_iof_0_22_i_ival(gpio_0_auto_iof_out_iof_0_22_i_ival),
    .auto_iof_out_iof_0_23_o_oval(gpio_0_auto_iof_out_iof_0_23_o_oval),
    .auto_iof_out_iof_0_24_o_oval(gpio_0_auto_iof_out_iof_0_24_o_oval),
    .auto_iof_out_iof_1_12_o_oval(gpio_0_auto_iof_out_iof_1_12_o_oval),
    .auto_iof_out_iof_1_13_o_oval(gpio_0_auto_iof_out_iof_1_13_o_oval),
    .auto_iof_out_iof_1_14_o_oval(gpio_0_auto_iof_out_iof_1_14_o_oval),
    .auto_iof_out_iof_1_15_o_oval(gpio_0_auto_iof_out_iof_1_15_o_oval),
    .auto_iof_out_iof_1_16_o_oval(gpio_0_auto_iof_out_iof_1_16_o_oval),
    .auto_iof_out_iof_1_17_o_oval(gpio_0_auto_iof_out_iof_1_17_o_oval),
    .auto_iof_out_iof_1_18_o_oval(gpio_0_auto_iof_out_iof_1_18_o_oval),
    .auto_iof_out_iof_1_19_o_oval(gpio_0_auto_iof_out_iof_1_19_o_oval),
    .auto_iof_out_iof_1_20_o_oval(gpio_0_auto_iof_out_iof_1_20_o_oval),
    .auto_iof_out_iof_1_21_o_oval(gpio_0_auto_iof_out_iof_1_21_o_oval),
    .auto_iof_out_iof_1_22_o_oval(gpio_0_auto_iof_out_iof_1_22_o_oval),
    .auto_iof_out_iof_1_23_o_oval(gpio_0_auto_iof_out_iof_1_23_o_oval),
    .auto_io_out_pins_0_i_ival(gpio_0_auto_io_out_pins_0_i_ival),
    .auto_io_out_pins_0_o_oval(gpio_0_auto_io_out_pins_0_o_oval),
    .auto_io_out_pins_0_o_oe(gpio_0_auto_io_out_pins_0_o_oe),
    .auto_io_out_pins_0_o_ie(gpio_0_auto_io_out_pins_0_o_ie),
    .auto_io_out_pins_1_i_ival(gpio_0_auto_io_out_pins_1_i_ival),
    .auto_io_out_pins_1_o_oval(gpio_0_auto_io_out_pins_1_o_oval),
    .auto_io_out_pins_1_o_oe(gpio_0_auto_io_out_pins_1_o_oe),
    .auto_io_out_pins_1_o_ie(gpio_0_auto_io_out_pins_1_o_ie),
    .auto_io_out_pins_2_i_ival(gpio_0_auto_io_out_pins_2_i_ival),
    .auto_io_out_pins_2_o_oval(gpio_0_auto_io_out_pins_2_o_oval),
    .auto_io_out_pins_2_o_oe(gpio_0_auto_io_out_pins_2_o_oe),
    .auto_io_out_pins_2_o_ie(gpio_0_auto_io_out_pins_2_o_ie),
    .auto_io_out_pins_3_i_ival(gpio_0_auto_io_out_pins_3_i_ival),
    .auto_io_out_pins_3_o_oval(gpio_0_auto_io_out_pins_3_o_oval),
    .auto_io_out_pins_3_o_oe(gpio_0_auto_io_out_pins_3_o_oe),
    .auto_io_out_pins_3_o_ie(gpio_0_auto_io_out_pins_3_o_ie),
    .auto_io_out_pins_4_i_ival(gpio_0_auto_io_out_pins_4_i_ival),
    .auto_io_out_pins_4_o_oval(gpio_0_auto_io_out_pins_4_o_oval),
    .auto_io_out_pins_4_o_oe(gpio_0_auto_io_out_pins_4_o_oe),
    .auto_io_out_pins_4_o_ie(gpio_0_auto_io_out_pins_4_o_ie),
    .auto_io_out_pins_5_i_ival(gpio_0_auto_io_out_pins_5_i_ival),
    .auto_io_out_pins_5_o_oval(gpio_0_auto_io_out_pins_5_o_oval),
    .auto_io_out_pins_5_o_oe(gpio_0_auto_io_out_pins_5_o_oe),
    .auto_io_out_pins_5_o_ie(gpio_0_auto_io_out_pins_5_o_ie),
    .auto_io_out_pins_6_i_ival(gpio_0_auto_io_out_pins_6_i_ival),
    .auto_io_out_pins_6_o_oval(gpio_0_auto_io_out_pins_6_o_oval),
    .auto_io_out_pins_6_o_oe(gpio_0_auto_io_out_pins_6_o_oe),
    .auto_io_out_pins_7_i_ival(gpio_0_auto_io_out_pins_7_i_ival),
    .auto_io_out_pins_7_o_oval(gpio_0_auto_io_out_pins_7_o_oval),
    .auto_io_out_pins_7_o_oe(gpio_0_auto_io_out_pins_7_o_oe),
    .auto_io_out_pins_8_i_ival(gpio_0_auto_io_out_pins_8_i_ival),
    .auto_io_out_pins_8_o_oval(gpio_0_auto_io_out_pins_8_o_oval),
    .auto_io_out_pins_8_o_oe(gpio_0_auto_io_out_pins_8_o_oe),
    .auto_io_out_pins_9_i_ival(gpio_0_auto_io_out_pins_9_i_ival),
    .auto_io_out_pins_9_o_oval(gpio_0_auto_io_out_pins_9_o_oval),
    .auto_io_out_pins_9_o_oe(gpio_0_auto_io_out_pins_9_o_oe),
    .auto_io_out_pins_10_i_ival(gpio_0_auto_io_out_pins_10_i_ival),
    .auto_io_out_pins_10_o_oval(gpio_0_auto_io_out_pins_10_o_oval),
    .auto_io_out_pins_10_o_oe(gpio_0_auto_io_out_pins_10_o_oe),
    .auto_io_out_pins_11_i_ival(gpio_0_auto_io_out_pins_11_i_ival),
    .auto_io_out_pins_11_o_oval(gpio_0_auto_io_out_pins_11_o_oval),
    .auto_io_out_pins_11_o_oe(gpio_0_auto_io_out_pins_11_o_oe),
    .auto_io_out_pins_12_i_ival(gpio_0_auto_io_out_pins_12_i_ival),
    .auto_io_out_pins_12_o_oval(gpio_0_auto_io_out_pins_12_o_oval),
    .auto_io_out_pins_12_o_oe(gpio_0_auto_io_out_pins_12_o_oe),
    .auto_io_out_pins_12_o_ie(gpio_0_auto_io_out_pins_12_o_ie),
    .auto_io_out_pins_13_i_ival(gpio_0_auto_io_out_pins_13_i_ival),
    .auto_io_out_pins_13_o_oval(gpio_0_auto_io_out_pins_13_o_oval),
    .auto_io_out_pins_13_o_oe(gpio_0_auto_io_out_pins_13_o_oe),
    .auto_io_out_pins_13_o_ie(gpio_0_auto_io_out_pins_13_o_ie),
    .auto_io_out_pins_14_i_ival(gpio_0_auto_io_out_pins_14_i_ival),
    .auto_io_out_pins_14_o_oval(gpio_0_auto_io_out_pins_14_o_oval),
    .auto_io_out_pins_14_o_oe(gpio_0_auto_io_out_pins_14_o_oe),
    .auto_io_out_pins_14_o_ie(gpio_0_auto_io_out_pins_14_o_ie),
    .auto_io_out_pins_15_i_ival(gpio_0_auto_io_out_pins_15_i_ival),
    .auto_io_out_pins_15_o_oval(gpio_0_auto_io_out_pins_15_o_oval),
    .auto_io_out_pins_15_o_oe(gpio_0_auto_io_out_pins_15_o_oe),
    .auto_io_out_pins_15_o_ie(gpio_0_auto_io_out_pins_15_o_ie),
    .auto_io_out_pins_16_i_ival(gpio_0_auto_io_out_pins_16_i_ival),
    .auto_io_out_pins_16_o_oval(gpio_0_auto_io_out_pins_16_o_oval),
    .auto_io_out_pins_16_o_oe(gpio_0_auto_io_out_pins_16_o_oe),
    .auto_io_out_pins_16_o_ie(gpio_0_auto_io_out_pins_16_o_ie),
    .auto_io_out_pins_17_i_ival(gpio_0_auto_io_out_pins_17_i_ival),
    .auto_io_out_pins_17_o_oval(gpio_0_auto_io_out_pins_17_o_oval),
    .auto_io_out_pins_17_o_oe(gpio_0_auto_io_out_pins_17_o_oe),
    .auto_io_out_pins_17_o_ie(gpio_0_auto_io_out_pins_17_o_ie),
    .auto_io_out_pins_18_i_ival(gpio_0_auto_io_out_pins_18_i_ival),
    .auto_io_out_pins_18_o_oval(gpio_0_auto_io_out_pins_18_o_oval),
    .auto_io_out_pins_18_o_oe(gpio_0_auto_io_out_pins_18_o_oe),
    .auto_io_out_pins_18_o_ie(gpio_0_auto_io_out_pins_18_o_ie),
    .auto_io_out_pins_19_i_ival(gpio_0_auto_io_out_pins_19_i_ival),
    .auto_io_out_pins_19_o_oval(gpio_0_auto_io_out_pins_19_o_oval),
    .auto_io_out_pins_19_o_oe(gpio_0_auto_io_out_pins_19_o_oe),
    .auto_io_out_pins_19_o_ie(gpio_0_auto_io_out_pins_19_o_ie),
    .auto_io_out_pins_20_i_ival(gpio_0_auto_io_out_pins_20_i_ival),
    .auto_io_out_pins_20_o_oval(gpio_0_auto_io_out_pins_20_o_oval),
    .auto_io_out_pins_20_o_oe(gpio_0_auto_io_out_pins_20_o_oe),
    .auto_io_out_pins_20_o_ie(gpio_0_auto_io_out_pins_20_o_ie),
    .auto_io_out_pins_21_i_ival(gpio_0_auto_io_out_pins_21_i_ival),
    .auto_io_out_pins_21_o_oval(gpio_0_auto_io_out_pins_21_o_oval),
    .auto_io_out_pins_21_o_oe(gpio_0_auto_io_out_pins_21_o_oe),
    .auto_io_out_pins_21_o_ie(gpio_0_auto_io_out_pins_21_o_ie),
    .auto_io_out_pins_22_i_ival(gpio_0_auto_io_out_pins_22_i_ival),
    .auto_io_out_pins_22_o_oval(gpio_0_auto_io_out_pins_22_o_oval),
    .auto_io_out_pins_22_o_oe(gpio_0_auto_io_out_pins_22_o_oe),
    .auto_io_out_pins_22_o_ie(gpio_0_auto_io_out_pins_22_o_ie),
    .auto_io_out_pins_23_i_ival(gpio_0_auto_io_out_pins_23_i_ival),
    .auto_io_out_pins_23_o_oval(gpio_0_auto_io_out_pins_23_o_oval),
    .auto_io_out_pins_23_o_oe(gpio_0_auto_io_out_pins_23_o_oe),
    .auto_io_out_pins_23_o_ie(gpio_0_auto_io_out_pins_23_o_ie),
    .auto_io_out_pins_24_i_ival(gpio_0_auto_io_out_pins_24_i_ival),
    .auto_io_out_pins_24_o_oval(gpio_0_auto_io_out_pins_24_o_oval),
    .auto_io_out_pins_24_o_oe(gpio_0_auto_io_out_pins_24_o_oe),
    .auto_io_out_pins_24_o_ie(gpio_0_auto_io_out_pins_24_o_ie),
    .auto_io_out_pins_25_i_ival(gpio_0_auto_io_out_pins_25_i_ival),
    .auto_io_out_pins_25_o_oval(gpio_0_auto_io_out_pins_25_o_oval),
    .auto_io_out_pins_25_o_oe(gpio_0_auto_io_out_pins_25_o_oe),
    .auto_io_out_pins_26_i_ival(gpio_0_auto_io_out_pins_26_i_ival),
    .auto_io_out_pins_26_o_oval(gpio_0_auto_io_out_pins_26_o_oval),
    .auto_io_out_pins_26_o_oe(gpio_0_auto_io_out_pins_26_o_oe),
    .auto_io_out_pins_27_i_ival(gpio_0_auto_io_out_pins_27_i_ival),
    .auto_io_out_pins_27_o_oval(gpio_0_auto_io_out_pins_27_o_oval),
    .auto_io_out_pins_27_o_oe(gpio_0_auto_io_out_pins_27_o_oe),
    .auto_io_out_pins_28_i_ival(gpio_0_auto_io_out_pins_28_i_ival),
    .auto_io_out_pins_28_o_oval(gpio_0_auto_io_out_pins_28_o_oval),
    .auto_io_out_pins_28_o_oe(gpio_0_auto_io_out_pins_28_o_oe),
    .auto_io_out_pins_29_i_ival(gpio_0_auto_io_out_pins_29_i_ival),
    .auto_io_out_pins_29_o_oval(gpio_0_auto_io_out_pins_29_o_oval),
    .auto_io_out_pins_29_o_oe(gpio_0_auto_io_out_pins_29_o_oe),
    .auto_io_out_pins_30_i_ival(gpio_0_auto_io_out_pins_30_i_ival),
    .auto_io_out_pins_30_o_oval(gpio_0_auto_io_out_pins_30_o_oval),
    .auto_io_out_pins_30_o_oe(gpio_0_auto_io_out_pins_30_o_oe),
    .auto_io_out_pins_31_i_ival(gpio_0_auto_io_out_pins_31_i_ival),
    .auto_io_out_pins_31_o_oval(gpio_0_auto_io_out_pins_31_o_oval),
    .auto_io_out_pins_31_o_oe(gpio_0_auto_io_out_pins_31_o_oe)
  );
  assign auto_gpio_0_int_xing_out_sync_0 = gpio_0_auto_int_xing_out_sync_0; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_int_xing_out_sync_1 = gpio_0_auto_int_xing_out_sync_1; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_int_xing_out_sync_2 = gpio_0_auto_int_xing_out_sync_2; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_int_xing_out_sync_3 = gpio_0_auto_int_xing_out_sync_3; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_int_xing_out_sync_4 = gpio_0_auto_int_xing_out_sync_4; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_int_xing_out_sync_5 = gpio_0_auto_int_xing_out_sync_5; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_int_xing_out_sync_6 = gpio_0_auto_int_xing_out_sync_6; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_int_xing_out_sync_7 = gpio_0_auto_int_xing_out_sync_7; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_int_xing_out_sync_8 = gpio_0_auto_int_xing_out_sync_8; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_int_xing_out_sync_9 = gpio_0_auto_int_xing_out_sync_9; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_int_xing_out_sync_10 = gpio_0_auto_int_xing_out_sync_10; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_int_xing_out_sync_11 = gpio_0_auto_int_xing_out_sync_11; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_int_xing_out_sync_12 = gpio_0_auto_int_xing_out_sync_12; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_int_xing_out_sync_13 = gpio_0_auto_int_xing_out_sync_13; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_int_xing_out_sync_14 = gpio_0_auto_int_xing_out_sync_14; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_int_xing_out_sync_15 = gpio_0_auto_int_xing_out_sync_15; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_int_xing_out_sync_16 = gpio_0_auto_int_xing_out_sync_16; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_int_xing_out_sync_17 = gpio_0_auto_int_xing_out_sync_17; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_int_xing_out_sync_18 = gpio_0_auto_int_xing_out_sync_18; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_int_xing_out_sync_19 = gpio_0_auto_int_xing_out_sync_19; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_int_xing_out_sync_20 = gpio_0_auto_int_xing_out_sync_20; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_int_xing_out_sync_21 = gpio_0_auto_int_xing_out_sync_21; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_int_xing_out_sync_22 = gpio_0_auto_int_xing_out_sync_22; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_int_xing_out_sync_23 = gpio_0_auto_int_xing_out_sync_23; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_int_xing_out_sync_24 = gpio_0_auto_int_xing_out_sync_24; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_int_xing_out_sync_25 = gpio_0_auto_int_xing_out_sync_25; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_int_xing_out_sync_26 = gpio_0_auto_int_xing_out_sync_26; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_int_xing_out_sync_27 = gpio_0_auto_int_xing_out_sync_27; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_int_xing_out_sync_28 = gpio_0_auto_int_xing_out_sync_28; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_int_xing_out_sync_29 = gpio_0_auto_int_xing_out_sync_29; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_int_xing_out_sync_30 = gpio_0_auto_int_xing_out_sync_30; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_int_xing_out_sync_31 = gpio_0_auto_int_xing_out_sync_31; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_control_xing_in_a_ready = gpio_0_auto_control_xing_in_a_ready; // @[LazyModule.scala 309:16]
  assign auto_gpio_0_control_xing_in_d_valid = gpio_0_auto_control_xing_in_d_valid; // @[LazyModule.scala 309:16]
  assign auto_gpio_0_control_xing_in_d_bits_opcode = gpio_0_auto_control_xing_in_d_bits_opcode; // @[LazyModule.scala 309:16]
  assign auto_gpio_0_control_xing_in_d_bits_size = gpio_0_auto_control_xing_in_d_bits_size; // @[LazyModule.scala 309:16]
  assign auto_gpio_0_control_xing_in_d_bits_source = gpio_0_auto_control_xing_in_d_bits_source; // @[LazyModule.scala 309:16]
  assign auto_gpio_0_control_xing_in_d_bits_data = gpio_0_auto_control_xing_in_d_bits_data; // @[LazyModule.scala 309:16]
  assign auto_gpio_0_iof_out_iof_0_2_i_ival = gpio_0_auto_iof_out_iof_0_2_i_ival; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_iof_out_iof_0_3_i_ival = gpio_0_auto_iof_out_iof_0_3_i_ival; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_iof_out_iof_0_4_i_ival = gpio_0_auto_iof_out_iof_0_4_i_ival; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_iof_out_iof_0_5_i_ival = gpio_0_auto_iof_out_iof_0_5_i_ival; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_iof_out_iof_0_12_i_ival = gpio_0_auto_iof_out_iof_0_12_i_ival; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_iof_out_iof_0_13_i_ival = gpio_0_auto_iof_out_iof_0_13_i_ival; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_iof_out_iof_0_14_i_ival = gpio_0_auto_iof_out_iof_0_14_i_ival; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_iof_out_iof_0_15_i_ival = gpio_0_auto_iof_out_iof_0_15_i_ival; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_iof_out_iof_0_16_i_ival = gpio_0_auto_iof_out_iof_0_16_i_ival; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_iof_out_iof_0_18_i_ival = gpio_0_auto_iof_out_iof_0_18_i_ival; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_iof_out_iof_0_20_i_ival = gpio_0_auto_iof_out_iof_0_20_i_ival; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_iof_out_iof_0_22_i_ival = gpio_0_auto_iof_out_iof_0_22_i_ival; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_0_o_oval = gpio_0_auto_io_out_pins_0_o_oval; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_0_o_oe = gpio_0_auto_io_out_pins_0_o_oe; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_0_o_ie = gpio_0_auto_io_out_pins_0_o_ie; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_1_o_oval = gpio_0_auto_io_out_pins_1_o_oval; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_1_o_oe = gpio_0_auto_io_out_pins_1_o_oe; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_1_o_ie = gpio_0_auto_io_out_pins_1_o_ie; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_2_o_oval = gpio_0_auto_io_out_pins_2_o_oval; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_2_o_oe = gpio_0_auto_io_out_pins_2_o_oe; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_2_o_ie = gpio_0_auto_io_out_pins_2_o_ie; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_3_o_oval = gpio_0_auto_io_out_pins_3_o_oval; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_3_o_oe = gpio_0_auto_io_out_pins_3_o_oe; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_3_o_ie = gpio_0_auto_io_out_pins_3_o_ie; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_4_o_oval = gpio_0_auto_io_out_pins_4_o_oval; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_4_o_oe = gpio_0_auto_io_out_pins_4_o_oe; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_4_o_ie = gpio_0_auto_io_out_pins_4_o_ie; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_5_o_oval = gpio_0_auto_io_out_pins_5_o_oval; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_5_o_oe = gpio_0_auto_io_out_pins_5_o_oe; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_5_o_ie = gpio_0_auto_io_out_pins_5_o_ie; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_6_o_oval = gpio_0_auto_io_out_pins_6_o_oval; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_6_o_oe = gpio_0_auto_io_out_pins_6_o_oe; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_7_o_oval = gpio_0_auto_io_out_pins_7_o_oval; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_7_o_oe = gpio_0_auto_io_out_pins_7_o_oe; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_8_o_oval = gpio_0_auto_io_out_pins_8_o_oval; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_8_o_oe = gpio_0_auto_io_out_pins_8_o_oe; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_9_o_oval = gpio_0_auto_io_out_pins_9_o_oval; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_9_o_oe = gpio_0_auto_io_out_pins_9_o_oe; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_10_o_oval = gpio_0_auto_io_out_pins_10_o_oval; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_10_o_oe = gpio_0_auto_io_out_pins_10_o_oe; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_11_o_oval = gpio_0_auto_io_out_pins_11_o_oval; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_11_o_oe = gpio_0_auto_io_out_pins_11_o_oe; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_12_o_oval = gpio_0_auto_io_out_pins_12_o_oval; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_12_o_oe = gpio_0_auto_io_out_pins_12_o_oe; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_12_o_ie = gpio_0_auto_io_out_pins_12_o_ie; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_13_o_oval = gpio_0_auto_io_out_pins_13_o_oval; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_13_o_oe = gpio_0_auto_io_out_pins_13_o_oe; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_13_o_ie = gpio_0_auto_io_out_pins_13_o_ie; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_14_o_oval = gpio_0_auto_io_out_pins_14_o_oval; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_14_o_oe = gpio_0_auto_io_out_pins_14_o_oe; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_14_o_ie = gpio_0_auto_io_out_pins_14_o_ie; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_15_o_oval = gpio_0_auto_io_out_pins_15_o_oval; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_15_o_oe = gpio_0_auto_io_out_pins_15_o_oe; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_15_o_ie = gpio_0_auto_io_out_pins_15_o_ie; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_16_o_oval = gpio_0_auto_io_out_pins_16_o_oval; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_16_o_oe = gpio_0_auto_io_out_pins_16_o_oe; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_16_o_ie = gpio_0_auto_io_out_pins_16_o_ie; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_17_o_oval = gpio_0_auto_io_out_pins_17_o_oval; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_17_o_oe = gpio_0_auto_io_out_pins_17_o_oe; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_17_o_ie = gpio_0_auto_io_out_pins_17_o_ie; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_18_o_oval = gpio_0_auto_io_out_pins_18_o_oval; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_18_o_oe = gpio_0_auto_io_out_pins_18_o_oe; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_18_o_ie = gpio_0_auto_io_out_pins_18_o_ie; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_19_o_oval = gpio_0_auto_io_out_pins_19_o_oval; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_19_o_oe = gpio_0_auto_io_out_pins_19_o_oe; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_19_o_ie = gpio_0_auto_io_out_pins_19_o_ie; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_20_o_oval = gpio_0_auto_io_out_pins_20_o_oval; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_20_o_oe = gpio_0_auto_io_out_pins_20_o_oe; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_20_o_ie = gpio_0_auto_io_out_pins_20_o_ie; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_21_o_oval = gpio_0_auto_io_out_pins_21_o_oval; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_21_o_oe = gpio_0_auto_io_out_pins_21_o_oe; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_21_o_ie = gpio_0_auto_io_out_pins_21_o_ie; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_22_o_oval = gpio_0_auto_io_out_pins_22_o_oval; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_22_o_oe = gpio_0_auto_io_out_pins_22_o_oe; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_22_o_ie = gpio_0_auto_io_out_pins_22_o_ie; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_23_o_oval = gpio_0_auto_io_out_pins_23_o_oval; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_23_o_oe = gpio_0_auto_io_out_pins_23_o_oe; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_23_o_ie = gpio_0_auto_io_out_pins_23_o_ie; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_24_o_oval = gpio_0_auto_io_out_pins_24_o_oval; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_24_o_oe = gpio_0_auto_io_out_pins_24_o_oe; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_24_o_ie = gpio_0_auto_io_out_pins_24_o_ie; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_25_o_oval = gpio_0_auto_io_out_pins_25_o_oval; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_25_o_oe = gpio_0_auto_io_out_pins_25_o_oe; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_26_o_oval = gpio_0_auto_io_out_pins_26_o_oval; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_26_o_oe = gpio_0_auto_io_out_pins_26_o_oe; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_27_o_oval = gpio_0_auto_io_out_pins_27_o_oval; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_27_o_oe = gpio_0_auto_io_out_pins_27_o_oe; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_28_o_oval = gpio_0_auto_io_out_pins_28_o_oval; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_28_o_oe = gpio_0_auto_io_out_pins_28_o_oe; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_29_o_oval = gpio_0_auto_io_out_pins_29_o_oval; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_29_o_oe = gpio_0_auto_io_out_pins_29_o_oe; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_30_o_oval = gpio_0_auto_io_out_pins_30_o_oval; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_30_o_oe = gpio_0_auto_io_out_pins_30_o_oe; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_31_o_oval = gpio_0_auto_io_out_pins_31_o_oval; // @[LazyModule.scala 311:12]
  assign auto_gpio_0_io_out_pins_31_o_oe = gpio_0_auto_io_out_pins_31_o_oe; // @[LazyModule.scala 311:12]
  assign gpio_0_clock = auto_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gpio_0_reset = auto_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign gpio_0_auto_control_xing_in_a_valid = auto_gpio_0_control_xing_in_a_valid; // @[LazyModule.scala 309:16]
  assign gpio_0_auto_control_xing_in_a_bits_opcode = auto_gpio_0_control_xing_in_a_bits_opcode; // @[LazyModule.scala 309:16]
  assign gpio_0_auto_control_xing_in_a_bits_param = auto_gpio_0_control_xing_in_a_bits_param; // @[LazyModule.scala 309:16]
  assign gpio_0_auto_control_xing_in_a_bits_size = auto_gpio_0_control_xing_in_a_bits_size; // @[LazyModule.scala 309:16]
  assign gpio_0_auto_control_xing_in_a_bits_source = auto_gpio_0_control_xing_in_a_bits_source; // @[LazyModule.scala 309:16]
  assign gpio_0_auto_control_xing_in_a_bits_address = auto_gpio_0_control_xing_in_a_bits_address; // @[LazyModule.scala 309:16]
  assign gpio_0_auto_control_xing_in_a_bits_mask = auto_gpio_0_control_xing_in_a_bits_mask; // @[LazyModule.scala 309:16]
  assign gpio_0_auto_control_xing_in_a_bits_data = auto_gpio_0_control_xing_in_a_bits_data; // @[LazyModule.scala 309:16]
  assign gpio_0_auto_control_xing_in_a_bits_corrupt = auto_gpio_0_control_xing_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
  assign gpio_0_auto_control_xing_in_d_ready = auto_gpio_0_control_xing_in_d_ready; // @[LazyModule.scala 309:16]
  assign gpio_0_auto_iof_out_iof_0_0_o_oval = auto_gpio_0_iof_out_iof_0_0_o_oval; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_iof_out_iof_0_1_o_oval = auto_gpio_0_iof_out_iof_0_1_o_oval; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_iof_out_iof_0_2_o_oval = auto_gpio_0_iof_out_iof_0_2_o_oval; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_iof_out_iof_0_2_o_oe = auto_gpio_0_iof_out_iof_0_2_o_oe; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_iof_out_iof_0_2_o_ie = auto_gpio_0_iof_out_iof_0_2_o_ie; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_iof_out_iof_0_3_o_oval = auto_gpio_0_iof_out_iof_0_3_o_oval; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_iof_out_iof_0_3_o_oe = auto_gpio_0_iof_out_iof_0_3_o_oe; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_iof_out_iof_0_3_o_ie = auto_gpio_0_iof_out_iof_0_3_o_ie; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_iof_out_iof_0_4_o_oval = auto_gpio_0_iof_out_iof_0_4_o_oval; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_iof_out_iof_0_4_o_oe = auto_gpio_0_iof_out_iof_0_4_o_oe; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_iof_out_iof_0_4_o_ie = auto_gpio_0_iof_out_iof_0_4_o_ie; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_iof_out_iof_0_5_o_oval = auto_gpio_0_iof_out_iof_0_5_o_oval; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_iof_out_iof_0_5_o_oe = auto_gpio_0_iof_out_iof_0_5_o_oe; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_iof_out_iof_0_5_o_ie = auto_gpio_0_iof_out_iof_0_5_o_ie; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_iof_out_iof_0_12_o_oe = auto_gpio_0_iof_out_iof_0_12_o_oe; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_iof_out_iof_0_13_o_oe = auto_gpio_0_iof_out_iof_0_13_o_oe; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_iof_out_iof_0_14_o_oe = auto_gpio_0_iof_out_iof_0_14_o_oe; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_iof_out_iof_0_15_o_oe = auto_gpio_0_iof_out_iof_0_15_o_oe; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_iof_out_iof_0_17_o_oval = auto_gpio_0_iof_out_iof_0_17_o_oval; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_iof_out_iof_0_19_o_oval = auto_gpio_0_iof_out_iof_0_19_o_oval; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_iof_out_iof_0_21_o_oval = auto_gpio_0_iof_out_iof_0_21_o_oval; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_iof_out_iof_0_23_o_oval = auto_gpio_0_iof_out_iof_0_23_o_oval; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_iof_out_iof_0_24_o_oval = auto_gpio_0_iof_out_iof_0_24_o_oval; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_iof_out_iof_1_12_o_oval = auto_gpio_0_iof_out_iof_1_12_o_oval; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_iof_out_iof_1_13_o_oval = auto_gpio_0_iof_out_iof_1_13_o_oval; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_iof_out_iof_1_14_o_oval = auto_gpio_0_iof_out_iof_1_14_o_oval; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_iof_out_iof_1_15_o_oval = auto_gpio_0_iof_out_iof_1_15_o_oval; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_iof_out_iof_1_16_o_oval = auto_gpio_0_iof_out_iof_1_16_o_oval; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_iof_out_iof_1_17_o_oval = auto_gpio_0_iof_out_iof_1_17_o_oval; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_iof_out_iof_1_18_o_oval = auto_gpio_0_iof_out_iof_1_18_o_oval; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_iof_out_iof_1_19_o_oval = auto_gpio_0_iof_out_iof_1_19_o_oval; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_iof_out_iof_1_20_o_oval = auto_gpio_0_iof_out_iof_1_20_o_oval; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_iof_out_iof_1_21_o_oval = auto_gpio_0_iof_out_iof_1_21_o_oval; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_iof_out_iof_1_22_o_oval = auto_gpio_0_iof_out_iof_1_22_o_oval; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_iof_out_iof_1_23_o_oval = auto_gpio_0_iof_out_iof_1_23_o_oval; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_io_out_pins_0_i_ival = auto_gpio_0_io_out_pins_0_i_ival; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_io_out_pins_1_i_ival = auto_gpio_0_io_out_pins_1_i_ival; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_io_out_pins_2_i_ival = auto_gpio_0_io_out_pins_2_i_ival; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_io_out_pins_3_i_ival = auto_gpio_0_io_out_pins_3_i_ival; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_io_out_pins_4_i_ival = auto_gpio_0_io_out_pins_4_i_ival; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_io_out_pins_5_i_ival = auto_gpio_0_io_out_pins_5_i_ival; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_io_out_pins_6_i_ival = auto_gpio_0_io_out_pins_6_i_ival; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_io_out_pins_7_i_ival = auto_gpio_0_io_out_pins_7_i_ival; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_io_out_pins_8_i_ival = auto_gpio_0_io_out_pins_8_i_ival; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_io_out_pins_9_i_ival = auto_gpio_0_io_out_pins_9_i_ival; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_io_out_pins_10_i_ival = auto_gpio_0_io_out_pins_10_i_ival; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_io_out_pins_11_i_ival = auto_gpio_0_io_out_pins_11_i_ival; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_io_out_pins_12_i_ival = auto_gpio_0_io_out_pins_12_i_ival; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_io_out_pins_13_i_ival = auto_gpio_0_io_out_pins_13_i_ival; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_io_out_pins_14_i_ival = auto_gpio_0_io_out_pins_14_i_ival; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_io_out_pins_15_i_ival = auto_gpio_0_io_out_pins_15_i_ival; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_io_out_pins_16_i_ival = auto_gpio_0_io_out_pins_16_i_ival; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_io_out_pins_17_i_ival = auto_gpio_0_io_out_pins_17_i_ival; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_io_out_pins_18_i_ival = auto_gpio_0_io_out_pins_18_i_ival; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_io_out_pins_19_i_ival = auto_gpio_0_io_out_pins_19_i_ival; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_io_out_pins_20_i_ival = auto_gpio_0_io_out_pins_20_i_ival; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_io_out_pins_21_i_ival = auto_gpio_0_io_out_pins_21_i_ival; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_io_out_pins_22_i_ival = auto_gpio_0_io_out_pins_22_i_ival; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_io_out_pins_23_i_ival = auto_gpio_0_io_out_pins_23_i_ival; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_io_out_pins_24_i_ival = auto_gpio_0_io_out_pins_24_i_ival; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_io_out_pins_25_i_ival = auto_gpio_0_io_out_pins_25_i_ival; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_io_out_pins_26_i_ival = auto_gpio_0_io_out_pins_26_i_ival; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_io_out_pins_27_i_ival = auto_gpio_0_io_out_pins_27_i_ival; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_io_out_pins_28_i_ival = auto_gpio_0_io_out_pins_28_i_ival; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_io_out_pins_29_i_ival = auto_gpio_0_io_out_pins_29_i_ival; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_io_out_pins_30_i_ival = auto_gpio_0_io_out_pins_30_i_ival; // @[LazyModule.scala 311:12]
  assign gpio_0_auto_io_out_pins_31_i_ival = auto_gpio_0_io_out_pins_31_i_ival; // @[LazyModule.scala 311:12]
endmodule
module IntSyncSyncCrossingSink_15(
  input   auto_in_sync_0,
  input   auto_in_sync_1,
  input   auto_in_sync_2,
  input   auto_in_sync_3,
  input   auto_in_sync_4,
  input   auto_in_sync_5,
  input   auto_in_sync_6,
  input   auto_in_sync_7,
  input   auto_in_sync_8,
  input   auto_in_sync_9,
  input   auto_in_sync_10,
  input   auto_in_sync_11,
  input   auto_in_sync_12,
  input   auto_in_sync_13,
  input   auto_in_sync_14,
  input   auto_in_sync_15,
  input   auto_in_sync_16,
  input   auto_in_sync_17,
  input   auto_in_sync_18,
  input   auto_in_sync_19,
  input   auto_in_sync_20,
  input   auto_in_sync_21,
  input   auto_in_sync_22,
  input   auto_in_sync_23,
  input   auto_in_sync_24,
  input   auto_in_sync_25,
  input   auto_in_sync_26,
  input   auto_in_sync_27,
  input   auto_in_sync_28,
  input   auto_in_sync_29,
  input   auto_in_sync_30,
  input   auto_in_sync_31,
  output  auto_out_0,
  output  auto_out_1,
  output  auto_out_2,
  output  auto_out_3,
  output  auto_out_4,
  output  auto_out_5,
  output  auto_out_6,
  output  auto_out_7,
  output  auto_out_8,
  output  auto_out_9,
  output  auto_out_10,
  output  auto_out_11,
  output  auto_out_12,
  output  auto_out_13,
  output  auto_out_14,
  output  auto_out_15,
  output  auto_out_16,
  output  auto_out_17,
  output  auto_out_18,
  output  auto_out_19,
  output  auto_out_20,
  output  auto_out_21,
  output  auto_out_22,
  output  auto_out_23,
  output  auto_out_24,
  output  auto_out_25,
  output  auto_out_26,
  output  auto_out_27,
  output  auto_out_28,
  output  auto_out_29,
  output  auto_out_30,
  output  auto_out_31
);
  assign auto_out_0 = auto_in_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1 = auto_in_sync_1; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_2 = auto_in_sync_2; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_3 = auto_in_sync_3; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_4 = auto_in_sync_4; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_5 = auto_in_sync_5; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_6 = auto_in_sync_6; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_7 = auto_in_sync_7; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_8 = auto_in_sync_8; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_9 = auto_in_sync_9; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_10 = auto_in_sync_10; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_11 = auto_in_sync_11; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_12 = auto_in_sync_12; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_13 = auto_in_sync_13; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_14 = auto_in_sync_14; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_15 = auto_in_sync_15; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_16 = auto_in_sync_16; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_17 = auto_in_sync_17; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_18 = auto_in_sync_18; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_19 = auto_in_sync_19; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_20 = auto_in_sync_20; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_21 = auto_in_sync_21; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_22 = auto_in_sync_22; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_23 = auto_in_sync_23; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_24 = auto_in_sync_24; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_25 = auto_in_sync_25; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_26 = auto_in_sync_26; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_27 = auto_in_sync_27; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_28 = auto_in_sync_28; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_29 = auto_in_sync_29; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_30 = auto_in_sync_30; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_31 = auto_in_sync_31; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module AsyncResetRegVec_w4_i0(
  input        clock,
  input        reset,
  input  [3:0] io_d,
  output [3:0] io_q
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg [3:0] reg_; // @[AsyncResetReg.scala 64:50]
  assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[AsyncResetReg.scala 65:16]
      reg_ <= 4'h0; // @[AsyncResetReg.scala 66:9]
    end else begin
      reg_ <= io_d; // @[AsyncResetReg.scala 64:50]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  reg_ = _RAND_0[3:0];
`endif // RANDOMIZE_REG_INIT
  if (reset) begin
    reg_ = 4'h0;
  end
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module IntSyncCrossingSource_18(
  input   clock,
  input   reset,
  input   auto_in_0,
  input   auto_in_1,
  input   auto_in_2,
  input   auto_in_3,
  output  auto_out_sync_0,
  output  auto_out_sync_1,
  output  auto_out_sync_2,
  output  auto_out_sync_3
);
  wire  reg__clock; // @[AsyncResetReg.scala 89:21]
  wire  reg__reset; // @[AsyncResetReg.scala 89:21]
  wire [3:0] reg__io_d; // @[AsyncResetReg.scala 89:21]
  wire [3:0] reg__io_q; // @[AsyncResetReg.scala 89:21]
  wire [1:0] lo = {auto_in_1,auto_in_0}; // @[Cat.scala 31:58]
  wire [1:0] hi = {auto_in_3,auto_in_2}; // @[Cat.scala 31:58]
  AsyncResetRegVec_w4_i0 reg_ ( // @[AsyncResetReg.scala 89:21]
    .clock(reg__clock),
    .reset(reg__reset),
    .io_d(reg__io_d),
    .io_q(reg__io_q)
  );
  assign auto_out_sync_0 = reg__io_q[0]; // @[Crossing.scala 41:52]
  assign auto_out_sync_1 = reg__io_q[1]; // @[Crossing.scala 41:52]
  assign auto_out_sync_2 = reg__io_q[2]; // @[Crossing.scala 41:52]
  assign auto_out_sync_3 = reg__io_q[3]; // @[Crossing.scala 41:52]
  assign reg__clock = clock;
  assign reg__reset = reset;
  assign reg__io_d = {hi,lo}; // @[Cat.scala 31:58]
endmodule
module TLMonitor_67(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [1:0]  io_in_a_bits_size,
  input  [6:0]  io_in_a_bits_source,
  input  [28:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_size,
  input  [6:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [95:0] _RAND_10;
  reg [383:0] _RAND_11;
  reg [383:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [95:0] _RAND_16;
  reg [383:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T_4 = io_in_a_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire [4:0] _is_aligned_mask_T_1 = 5'h3 << io_in_a_bits_size; // @[package.scala 234:77]
  wire [1:0] is_aligned_mask = ~_is_aligned_mask_T_1[1:0]; // @[package.scala 234:46]
  wire [28:0] _GEN_71 = {{27'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 2'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [28:0] _T_33 = io_in_a_bits_address ^ 29'h10015000; // @[Parameters.scala 137:31]
  wire [29:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
  wire [29:0] _T_36 = $signed(_T_34) & -30'sh1000; // @[Parameters.scala 137:52]
  wire  _T_37 = $signed(_T_36) == 30'sh0; // @[Parameters.scala 137:67]
  wire  _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_74 = _T_73 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_164 = io_in_a_bits_size <= 2'h2; // @[Parameters.scala 92:42]
  wire  _T_172 = _T_164 & _T_37; // @[Parameters.scala 670:56]
  wire  _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_218 = _source_ok_T_4 & _T_172; // @[Monitor.scala 115:71]
  wire  _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_273 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_274 = io_in_a_bits_mask & _T_273; // @[Monitor.scala 127:31]
  wire  _T_275 = _T_274 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_279 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_347 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_355 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_385 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_397 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_10 = io_in_d_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire  _T_401 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_405 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 312:27]
  wire  _T_421 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_449 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_478 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_495 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_513 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [1:0] size; // @[Monitor.scala 386:22]
  reg [6:0] source; // @[Monitor.scala 387:22]
  reg [28:0] address; // @[Monitor.scala 388:22]
  wire  _T_543 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_544 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_548 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_552 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_556 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_560 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] size_1; // @[Monitor.scala 537:22]
  reg [6:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_567 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_568 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_576 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_580 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [95:0] inflight; // @[Monitor.scala 611:27]
  reg [383:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [383:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [8:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [9:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [383:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [383:0] _GEN_73 = {{368'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[383:1]}; // @[Monitor.scala 634:152]
  wire [383:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [383:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
  wire [383:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[383:1]}; // @[Monitor.scala 638:144]
  wire  _T_594 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [127:0] _a_set_wo_ready_T = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_597 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
  wire [8:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [9:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [1026:0] _GEN_1 = {{1023'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [1026:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
  wire [1025:0] _GEN_2 = {{1023'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [1025:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [95:0] _T_599 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_601 = ~_T_599[0]; // @[Monitor.scala 658:17]
  wire [127:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 652:72 653:28]
  wire [1026:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 1027'h0; // @[Monitor.scala 652:72 656:28]
  wire [1025:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 1026'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_605 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_607 = ~_T_401; // @[Monitor.scala 671:74]
  wire  _T_608 = io_in_d_valid & d_first_1 & ~_T_401; // @[Monitor.scala 671:71]
  wire [127:0] _d_clr_wo_ready_T = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [1038:0] _GEN_3 = {{1023'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [1038:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [127:0] _GEN_22 = d_first_done & d_first_1 & _T_607 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 675:91 676:21]
  wire [1038:0] _GEN_23 = d_first_done & d_first_1 & _T_607 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_594 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [95:0] _T_618 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_620 = _T_618[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_625 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_626 = io_in_d_bits_opcode == _GEN_32 | _T_625; // @[Monitor.scala 685:77]
  wire  _T_630 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_637 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_638 = io_in_d_bits_opcode == _GEN_48 | _T_637; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_642 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_652 = _T_605 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_607; // @[Monitor.scala 694:116]
  wire  _T_654 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [95:0] a_set = _GEN_16[95:0];
  wire [95:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [95:0] d_clr = _GEN_22[95:0];
  wire [95:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [95:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [383:0] a_opcodes_set = _GEN_19[383:0];
  wire [383:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [383:0] d_opcodes_clr = _GEN_23[383:0];
  wire [383:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [383:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [383:0] a_sizes_set = _GEN_20[383:0];
  wire [383:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [383:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_663 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [95:0] inflight_1; // @[Monitor.scala 723:35]
  reg [383:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [383:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [383:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
  wire [383:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[383:1]}; // @[Monitor.scala 747:146]
  wire  _T_689 = io_in_d_valid & d_first_2 & _T_401; // @[Monitor.scala 779:71]
  wire [127:0] _GEN_67 = d_first_done & d_first_2 & _T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 783:90 784:21]
  wire [1038:0] _GEN_68 = d_first_done & d_first_2 & _T_401 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 783:90 785:21]
  wire [95:0] _T_697 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_707 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [95:0] d_clr_1 = _GEN_67[95:0];
  wire [95:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [95:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [383:0] d_opcodes_clr_1 = _GEN_68[383:0];
  wire [383:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [383:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_727 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 1'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= 1'h0;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 96'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 384'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 384'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 1'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= 1'h0;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 96'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 384'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= 1'h0;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (d_first_done) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_172 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_172) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_275 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_275) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_309 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_309) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_347 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_347) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_385 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_397 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_397) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_478 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_478 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_495 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_495 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_513 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_513 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_544 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_544) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_548 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_548) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_552 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_552) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_556 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_556) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_560 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_560) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_568 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_568) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_576 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_576) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_580 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_580) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_601 & (_T_597 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_597 & ~reset & ~_T_601) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_620 & (_T_608 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & _T_2 & ~_T_620) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_626 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_626) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_630 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_630) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_638 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_638) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_642 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_642) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_654 & (_T_652 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_652 & _T_2 & ~_T_654) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_663 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_663) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_697[0] & (_T_689 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_689 & _T_2 & ~_T_697[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_707 & (_T_689 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_689 & _T_2 & ~_T_707) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_727 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_727) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[6:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[28:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[6:0];
  _RAND_10 = {3{`RANDOM}};
  inflight = _RAND_10[95:0];
  _RAND_11 = {12{`RANDOM}};
  inflight_opcodes = _RAND_11[383:0];
  _RAND_12 = {12{`RANDOM}};
  inflight_sizes = _RAND_12[383:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {3{`RANDOM}};
  inflight_1 = _RAND_16[95:0];
  _RAND_17 = {12{`RANDOM}};
  inflight_sizes_1 = _RAND_17[383:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module PWMTimer(
  input         clock,
  input         reset,
  input         scale_io_regs_cfg_write__ip_0,
  input         scale_io_regs_cfg_write__ip_1,
  input         scale_io_regs_cfg_write__ip_2,
  input         scale_io_regs_cfg_write__ip_3,
  input         scale_io_regs_cfg_write__gang_0,
  input         scale_io_regs_cfg_write__gang_1,
  input         scale_io_regs_cfg_write__gang_2,
  input         scale_io_regs_cfg_write__gang_3,
  input         scale_io_regs_cfg_write__extra_0,
  input         scale_io_regs_cfg_write__extra_1,
  input         scale_io_regs_cfg_write__extra_2,
  input         scale_io_regs_cfg_write__extra_3,
  input         scale_io_regs_cfg_write__center_0,
  input         scale_io_regs_cfg_write__center_1,
  input         scale_io_regs_cfg_write__center_2,
  input         scale_io_regs_cfg_write__center_3,
  input         scale_io_regs_cfg_write__running,
  input         scale_io_regs_cfg_write__countAlways,
  input         scale_io_regs_cfg_write__deglitch,
  input         scale_io_regs_cfg_write__zerocmp,
  input         scale_io_regs_cfg_write__sticky,
  input  [3:0]  scale_io_regs_cfg_write__scale,
  output        scale_io_regs_cfg_read_ip_0,
  output        scale_io_regs_cfg_read_ip_1,
  output        scale_io_regs_cfg_read_ip_2,
  output        scale_io_regs_cfg_read_ip_3,
  output        scale_io_regs_cfg_read_gang_0,
  output        scale_io_regs_cfg_read_gang_1,
  output        scale_io_regs_cfg_read_gang_2,
  output        scale_io_regs_cfg_read_gang_3,
  output        scale_io_regs_cfg_read_extra_0,
  output        scale_io_regs_cfg_read_extra_1,
  output        scale_io_regs_cfg_read_extra_2,
  output        scale_io_regs_cfg_read_extra_3,
  output        scale_io_regs_cfg_read_center_0,
  output        scale_io_regs_cfg_read_center_1,
  output        scale_io_regs_cfg_read_center_2,
  output        scale_io_regs_cfg_read_center_3,
  output        scale_io_regs_cfg_read_running,
  output        scale_io_regs_cfg_read_countAlways,
  output        scale_io_regs_cfg_read_deglitch,
  output        scale_io_regs_cfg_read_zerocmp,
  output        scale_io_regs_cfg_read_sticky,
  output [3:0]  scale_io_regs_cfg_read_scale,
  input         scale_io_regs_cfg_write_ip_0,
  input         scale_io_regs_cfg_write_ip_1,
  input         scale_io_regs_cfg_write_ip_2,
  input         scale_io_regs_cfg_write_ip_3,
  input         scale_io_regs_cfg_write_gang_0,
  input         scale_io_regs_cfg_write_gang_1,
  input         scale_io_regs_cfg_write_gang_2,
  input         scale_io_regs_cfg_write_gang_3,
  input         scale_io_regs_cfg_write_extra_0,
  input         scale_io_regs_cfg_write_extra_1,
  input         scale_io_regs_cfg_write_extra_2,
  input         scale_io_regs_cfg_write_extra_3,
  input         scale_io_regs_cfg_write_center_0,
  input         scale_io_regs_cfg_write_center_1,
  input         scale_io_regs_cfg_write_center_2,
  input         scale_io_regs_cfg_write_center_3,
  input         scale_io_regs_cfg_write_running,
  input         scale_io_regs_cfg_write_countAlways,
  input         scale_io_regs_cfg_write_deglitch,
  input         scale_io_regs_cfg_write_zerocmp,
  input         scale_io_regs_cfg_write_sticky,
  input         scale_io_regs_cfg_write_scale,
  input         scale_io_regs_countLo_write_valid,
  input  [30:0] scale_io_regs_countLo_write_bits,
  output [30:0] scale_io_regs_countLo_read,
  output [15:0] scale_io_regs_s_read,
  input         scale_io_regs_cmp_0_write_valid,
  input  [15:0] scale_io_regs_cmp_0_write_bits,
  output [15:0] scale_io_regs_cmp_0_read,
  input         scale_io_regs_cmp_1_write_valid,
  input  [15:0] scale_io_regs_cmp_1_write_bits,
  output [15:0] scale_io_regs_cmp_1_read,
  input         scale_io_regs_cmp_2_write_valid,
  input  [15:0] scale_io_regs_cmp_2_write_bits,
  output [15:0] scale_io_regs_cmp_2_read,
  input         scale_io_regs_cmp_3_write_valid,
  input  [15:0] scale_io_regs_cmp_3_write_bits,
  output [15:0] scale_io_regs_cmp_3_read,
  output        scale_io_ip_0,
  output        scale_io_ip_1,
  output        scale_io_ip_2,
  output        scale_io_ip_3,
  output        scale_io_gpio_0,
  output        scale_io_gpio_1,
  output        scale_io_gpio_2,
  output        scale_io_gpio_3
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
`endif // RANDOMIZE_REG_INIT
  reg [3:0] scale; // @[Reg.scala 16:16]
  reg [15:0] cmp_0; // @[Reg.scala 16:16]
  reg [15:0] cmp_1; // @[Reg.scala 16:16]
  reg [15:0] cmp_2; // @[Reg.scala 16:16]
  reg [15:0] cmp_3; // @[Reg.scala 16:16]
  reg [4:0] small_; // @[Counters.scala 45:37]
  reg  countAlways; // @[Reg.scala 28:20]
  reg  oneShot; // @[Reg.scala 28:20]
  wire  countEn = countAlways | oneShot; // @[PWM.scala 63:26]
  wire [4:0] _GEN_32 = {{4'd0}, countEn}; // @[Counters.scala 46:33]
  wire [5:0] nextSmall = small_ + _GEN_32; // @[Counters.scala 46:33]
  reg [25:0] large_; // @[Counters.scala 50:27]
  wire [26:0] _large_r_T = large_ + 26'h1; // @[Counters.scala 51:55]
  wire [25:0] _large_r_T_1 = large_ + 26'h1; // @[Counters.scala 51:55]
  wire [25:0] _GEN_6 = nextSmall[5] ? _large_r_T_1 : large_; // @[Counters.scala 50:27 51:{46,50}]
  wire [30:0] value = {large_,small_}; // @[Cat.scala 31:58]
  wire [30:0] _s_T = value >> scale; // @[Timer.scala 209:28]
  wire [15:0] s = _s_T[15:0]; // @[Timer.scala 209:37]
  wire  _elapsed_center_T_3 = scale_io_regs_cfg_write_center_0 | scale_io_regs_cfg_write_center_1 |
    scale_io_regs_cfg_write_center_2 | scale_io_regs_cfg_write_center_3; // @[PWM.scala 27:59]
  reg  center_0; // @[Reg.scala 16:16]
  reg  center_1; // @[Reg.scala 16:16]
  reg  center_2; // @[Reg.scala 16:16]
  reg  center_3; // @[Reg.scala 16:16]
  wire  _elapsed_T_1 = s[15] & center_0; // @[Timer.scala 211:69]
  wire [15:0] _elapsed_T_2 = ~s; // @[Timer.scala 211:83]
  wire [15:0] _elapsed_T_3 = s[15] & center_0 ? _elapsed_T_2 : s; // @[Timer.scala 211:54]
  wire  elapsed_0 = _elapsed_T_3 >= cmp_0; // @[Timer.scala 211:90]
  wire  _elapsed_T_6 = s[15] & center_1; // @[Timer.scala 211:69]
  wire [15:0] _elapsed_T_8 = s[15] & center_1 ? _elapsed_T_2 : s; // @[Timer.scala 211:54]
  wire  elapsed_1 = _elapsed_T_8 >= cmp_1; // @[Timer.scala 211:90]
  wire  _elapsed_T_11 = s[15] & center_2; // @[Timer.scala 211:69]
  wire [15:0] _elapsed_T_13 = s[15] & center_2 ? _elapsed_T_2 : s; // @[Timer.scala 211:54]
  wire  elapsed_2 = _elapsed_T_13 >= cmp_2; // @[Timer.scala 211:90]
  wire  _elapsed_T_16 = s[15] & center_3; // @[Timer.scala 211:69]
  wire [15:0] _elapsed_T_18 = s[15] & center_3 ? _elapsed_T_2 : s; // @[Timer.scala 211:54]
  wire  elapsed_3 = _elapsed_T_18 >= cmp_3; // @[Timer.scala 211:90]
  wire [5:0] _GEN_33 = {{1'd0}, small_}; // @[Counters.scala 57:21]
  wire [5:0] _countReset_feed_carryOut_lo_T = _GEN_33 ^ nextSmall; // @[Counters.scala 57:21]
  wire [4:0] countReset_feed_carryOut_lo = _countReset_feed_carryOut_lo_T[5:1]; // @[Counters.scala 57:34]
  wire [26:0] _GEN_34 = {{1'd0}, large_}; // @[Counters.scala 59:49]
  wire [26:0] _countReset_feed_carryOut_hi_T_2 = _GEN_34 ^ _large_r_T; // @[Counters.scala 59:49]
  wire [26:0] _countReset_feed_carryOut_hi_T_3 = nextSmall[5] ? _countReset_feed_carryOut_hi_T_2 : 27'h0; // @[Counters.scala 59:19]
  wire [25:0] countReset_feed_carryOut_hi = _countReset_feed_carryOut_hi_T_3[26:1]; // @[Counters.scala 59:80]
  wire [30:0] countReset_feed_carryOut = {countReset_feed_carryOut_hi,countReset_feed_carryOut_lo}; // @[Cat.scala 31:58]
  wire [4:0] _GEN_35 = {{1'd0}, scale}; // @[PWM.scala 30:50]
  wire [4:0] _countReset_feed_T_1 = _GEN_35 + 5'h10; // @[PWM.scala 30:50]
  wire [30:0] _countReset_feed_T_2 = countReset_feed_carryOut >> _countReset_feed_T_1; // @[PWM.scala 30:43]
  wire  feed = _countReset_feed_T_2[0]; // @[PWM.scala 30:43]
  reg  zerocmp; // @[Reg.scala 16:16]
  wire  countReset = feed | zerocmp & elapsed_0; // @[Timer.scala 212:35]
  wire [5:0] _GEN_12 = countReset ? 6'h0 : nextSmall; // @[Timer.scala 213:21 Counters.scala 65:11]
  wire [25:0] _GEN_13 = countReset ? 26'h0 : _GEN_6; // @[Timer.scala 213:21 Counters.scala 66:23]
  wire [31:0] _T_3 = {1'h0,scale_io_regs_countLo_write_bits}; // @[Cat.scala 31:58]
  wire [31:0] _GEN_14 = scale_io_regs_countLo_write_valid ? _T_3 : {{26'd0}, _GEN_12}; // @[Timer.scala 214:50 Counters.scala 65:11]
  wire [26:0] _GEN_15 = scale_io_regs_countLo_write_valid ? _T_3[31:5] : {{1'd0}, _GEN_13}; // @[Timer.scala 214:50 Counters.scala 66:23]
  reg  ip_doSticky_x1_deglitch_r; // @[Reg.scala 16:16]
  wire  _ip_doSticky_x1_T = ~countReset; // @[PWM.scala 39:44]
  reg  ip_doSticky_x1_sticky_r; // @[Reg.scala 16:16]
  reg  ip_doSticky; // @[PWM.scala 39:23]
  reg  ip_0; // @[PWM.scala 41:18]
  reg  ip_1; // @[PWM.scala 41:18]
  reg  ip_2; // @[PWM.scala 41:18]
  reg  ip_3; // @[PWM.scala 41:18]
  wire  _ip_T = _elapsed_T_1 & elapsed_0; // @[package.scala 65:72]
  wire  _ip_T_1 = _elapsed_T_6 & elapsed_1; // @[package.scala 65:72]
  wire  _ip_T_2 = _elapsed_T_11 & elapsed_2; // @[package.scala 65:72]
  wire  _ip_T_3 = _elapsed_T_16 & elapsed_3; // @[package.scala 65:72]
  wire  _ip_T_4 = ~_elapsed_T_1; // @[package.scala 70:38]
  wire  _ip_T_5 = ~_elapsed_T_6; // @[package.scala 70:38]
  wire  _ip_T_6 = ~_elapsed_T_11; // @[package.scala 70:38]
  wire  _ip_T_7 = ~_elapsed_T_16; // @[package.scala 70:38]
  wire  _ip_T_8 = ip_doSticky & ip_0; // @[package.scala 65:72]
  wire  _ip_T_9 = ip_doSticky & ip_1; // @[package.scala 65:72]
  wire  _ip_T_10 = ip_doSticky & ip_2; // @[package.scala 65:72]
  wire  _ip_T_11 = ip_doSticky & ip_3; // @[package.scala 65:72]
  wire  _ip_T_12 = elapsed_0 | _ip_T_8; // @[package.scala 66:75]
  wire  _ip_T_13 = elapsed_1 | _ip_T_9; // @[package.scala 66:75]
  wire  _ip_T_14 = elapsed_2 | _ip_T_10; // @[package.scala 66:75]
  wire  _ip_T_15 = elapsed_3 | _ip_T_11; // @[package.scala 66:75]
  wire  _ip_T_16 = _ip_T_4 & _ip_T_12; // @[package.scala 65:72]
  wire  _ip_T_17 = _ip_T_5 & _ip_T_13; // @[package.scala 65:72]
  wire  _ip_T_18 = _ip_T_6 & _ip_T_14; // @[package.scala 65:72]
  wire  _ip_T_19 = _ip_T_7 & _ip_T_15; // @[package.scala 65:72]
  wire  _ip_T_20 = _ip_T | _ip_T_16; // @[package.scala 66:75]
  wire  _ip_T_21 = _ip_T_1 | _ip_T_17; // @[package.scala 66:75]
  wire  _ip_T_22 = _ip_T_2 | _ip_T_18; // @[package.scala 66:75]
  wire  _ip_T_23 = _ip_T_3 | _ip_T_19; // @[package.scala 66:75]
  wire  _ip_T_27 = scale_io_regs_cfg_write_ip_0 | scale_io_regs_cfg_write_ip_1 | scale_io_regs_cfg_write_ip_2 |
    scale_io_regs_cfg_write_ip_3; // @[PWM.scala 27:59]
  wire  _gang_T_3 = scale_io_regs_cfg_write_gang_0 | scale_io_regs_cfg_write_gang_1 | scale_io_regs_cfg_write_gang_2 |
    scale_io_regs_cfg_write_gang_3; // @[PWM.scala 27:59]
  reg  gang_0; // @[Reg.scala 16:16]
  reg  gang_1; // @[Reg.scala 16:16]
  reg  gang_2; // @[Reg.scala 16:16]
  reg  gang_3; // @[Reg.scala 16:16]
  wire  _extra_T_3 = scale_io_regs_cfg_write_extra_0 | scale_io_regs_cfg_write_extra_1 | scale_io_regs_cfg_write_extra_2
     | scale_io_regs_cfg_write_extra_3; // @[PWM.scala 27:59]
  reg  extra_0; // @[Reg.scala 28:20]
  reg  extra_1; // @[Reg.scala 28:20]
  reg  extra_2; // @[Reg.scala 28:20]
  reg  extra_3; // @[Reg.scala 28:20]
  wire  _io_regs_cfg_read_running_oneShot_T_1 = scale_io_regs_cfg_write__running & _ip_doSticky_x1_T; // @[PWM.scala 32:77]
  wire  _io_regs_cfg_read_running_oneShot_T_3 = scale_io_regs_cfg_write_running | countReset; // @[PWM.scala 32:146]
  wire [3:0] invert = {extra_3,extra_2,extra_1,extra_0}; // @[PWM.scala 57:22]
  wire [3:0] ipU = {ip_3,ip_2,ip_1,ip_0}; // @[PWM.scala 59:16]
  wire [3:0] gangU = {gang_3,gang_2,gang_1,gang_0}; // @[PWM.scala 60:20]
  wire [3:0] _T_6 = {ipU[0],ipU[3:1]}; // @[Cat.scala 31:58]
  wire [3:0] _T_7 = gangU & _T_6; // @[PWM.scala 62:46]
  wire [3:0] _T_8 = ~_T_7; // @[PWM.scala 62:38]
  wire [3:0] _T_9 = ipU & _T_8; // @[PWM.scala 62:36]
  wire [3:0] _T_10 = _T_9 ^ invert; // @[PWM.scala 62:72]
  assign scale_io_regs_cfg_read_ip_0 = ip_0; // @[Timer.scala 218:23]
  assign scale_io_regs_cfg_read_ip_1 = ip_1; // @[Timer.scala 218:23]
  assign scale_io_regs_cfg_read_ip_2 = ip_2; // @[Timer.scala 218:23]
  assign scale_io_regs_cfg_read_ip_3 = ip_3; // @[Timer.scala 218:23]
  assign scale_io_regs_cfg_read_gang_0 = gang_0; // @[Timer.scala 219:25]
  assign scale_io_regs_cfg_read_gang_1 = gang_1; // @[Timer.scala 219:25]
  assign scale_io_regs_cfg_read_gang_2 = gang_2; // @[Timer.scala 219:25]
  assign scale_io_regs_cfg_read_gang_3 = gang_3; // @[Timer.scala 219:25]
  assign scale_io_regs_cfg_read_extra_0 = extra_0; // @[Timer.scala 220:26]
  assign scale_io_regs_cfg_read_extra_1 = extra_1; // @[Timer.scala 220:26]
  assign scale_io_regs_cfg_read_extra_2 = extra_2; // @[Timer.scala 220:26]
  assign scale_io_regs_cfg_read_extra_3 = extra_3; // @[Timer.scala 220:26]
  assign scale_io_regs_cfg_read_center_0 = center_0; // @[Timer.scala 221:27]
  assign scale_io_regs_cfg_read_center_1 = center_1; // @[Timer.scala 221:27]
  assign scale_io_regs_cfg_read_center_2 = center_2; // @[Timer.scala 221:27]
  assign scale_io_regs_cfg_read_center_3 = center_3; // @[Timer.scala 221:27]
  assign scale_io_regs_cfg_read_running = oneShot; // @[Timer.scala 222:42]
  assign scale_io_regs_cfg_read_countAlways = countAlways; // @[Timer.scala 223:32]
  assign scale_io_regs_cfg_read_deglitch = ip_doSticky_x1_deglitch_r; // @[PWM.scala 36:119]
  assign scale_io_regs_cfg_read_zerocmp = zerocmp; // @[Timer.scala 225:28]
  assign scale_io_regs_cfg_read_sticky = ip_doSticky_x1_sticky_r; // @[Timer.scala 226:36]
  assign scale_io_regs_cfg_read_scale = scale; // @[Timer.scala 227:26]
  assign scale_io_regs_countLo_read = {large_,small_}; // @[Cat.scala 31:58]
  assign scale_io_regs_s_read = _s_T[15:0]; // @[Timer.scala 209:37]
  assign scale_io_regs_cmp_0_read = cmp_0; // @[Timer.scala 232:53]
  assign scale_io_regs_cmp_1_read = cmp_1; // @[Timer.scala 232:53]
  assign scale_io_regs_cmp_2_read = cmp_2; // @[Timer.scala 232:53]
  assign scale_io_regs_cmp_3_read = cmp_3; // @[Timer.scala 232:53]
  assign scale_io_ip_0 = ip_0; // @[Timer.scala 235:9]
  assign scale_io_ip_1 = ip_1; // @[Timer.scala 235:9]
  assign scale_io_ip_2 = ip_2; // @[Timer.scala 235:9]
  assign scale_io_ip_3 = ip_3; // @[Timer.scala 235:9]
  assign scale_io_gpio_0 = _T_10[0]; // @[PWM.scala 62:30]
  assign scale_io_gpio_1 = _T_10[1]; // @[PWM.scala 62:30]
  assign scale_io_gpio_2 = _T_10[2]; // @[PWM.scala 62:30]
  assign scale_io_gpio_3 = _T_10[3]; // @[PWM.scala 62:30]
  always @(posedge clock) begin
    if (scale_io_regs_cfg_write_scale) begin // @[Reg.scala 17:18]
      scale <= scale_io_regs_cfg_write__scale; // @[Reg.scala 17:22]
    end
    if (scale_io_regs_cmp_0_write_valid) begin // @[Reg.scala 17:18]
      cmp_0 <= scale_io_regs_cmp_0_write_bits; // @[Reg.scala 17:22]
    end
    if (scale_io_regs_cmp_1_write_valid) begin // @[Reg.scala 17:18]
      cmp_1 <= scale_io_regs_cmp_1_write_bits; // @[Reg.scala 17:22]
    end
    if (scale_io_regs_cmp_2_write_valid) begin // @[Reg.scala 17:18]
      cmp_2 <= scale_io_regs_cmp_2_write_bits; // @[Reg.scala 17:22]
    end
    if (scale_io_regs_cmp_3_write_valid) begin // @[Reg.scala 17:18]
      cmp_3 <= scale_io_regs_cmp_3_write_bits; // @[Reg.scala 17:22]
    end
    if (reset) begin // @[Counters.scala 45:37]
      small_ <= 5'h0; // @[Counters.scala 45:37]
    end else begin
      small_ <= _GEN_14[4:0];
    end
    if (reset) begin // @[Reg.scala 28:20]
      countAlways <= 1'h0; // @[Reg.scala 28:20]
    end else if (scale_io_regs_cfg_write_countAlways) begin // @[Reg.scala 29:18]
      countAlways <= scale_io_regs_cfg_write__countAlways; // @[Reg.scala 29:22]
    end
    if (reset) begin // @[Reg.scala 28:20]
      oneShot <= 1'h0; // @[Reg.scala 28:20]
    end else if (_io_regs_cfg_read_running_oneShot_T_3) begin // @[Reg.scala 29:18]
      oneShot <= _io_regs_cfg_read_running_oneShot_T_1; // @[Reg.scala 29:22]
    end
    if (reset) begin // @[Counters.scala 50:27]
      large_ <= 26'h0; // @[Counters.scala 50:27]
    end else begin
      large_ <= _GEN_15[25:0];
    end
    if (_elapsed_center_T_3) begin // @[Reg.scala 17:18]
      center_0 <= scale_io_regs_cfg_write__center_0; // @[Reg.scala 17:22]
    end
    if (_elapsed_center_T_3) begin // @[Reg.scala 17:18]
      center_1 <= scale_io_regs_cfg_write__center_1; // @[Reg.scala 17:22]
    end
    if (_elapsed_center_T_3) begin // @[Reg.scala 17:18]
      center_2 <= scale_io_regs_cfg_write__center_2; // @[Reg.scala 17:22]
    end
    if (_elapsed_center_T_3) begin // @[Reg.scala 17:18]
      center_3 <= scale_io_regs_cfg_write__center_3; // @[Reg.scala 17:22]
    end
    if (scale_io_regs_cfg_write_zerocmp) begin // @[Reg.scala 17:18]
      zerocmp <= scale_io_regs_cfg_write__zerocmp; // @[Reg.scala 17:22]
    end
    if (scale_io_regs_cfg_write_deglitch) begin // @[Reg.scala 17:18]
      ip_doSticky_x1_deglitch_r <= scale_io_regs_cfg_write__deglitch; // @[Reg.scala 17:22]
    end
    if (scale_io_regs_cfg_write_sticky) begin // @[Reg.scala 17:18]
      ip_doSticky_x1_sticky_r <= scale_io_regs_cfg_write__sticky; // @[Reg.scala 17:22]
    end
    ip_doSticky <= ip_doSticky_x1_deglitch_r & ~countReset | ip_doSticky_x1_sticky_r; // @[PWM.scala 39:57]
    if (_ip_T_27) begin // @[PWM.scala 43:50]
      ip_0 <= scale_io_regs_cfg_write__ip_0; // @[PWM.scala 43:56]
    end else begin
      ip_0 <= _ip_T_20; // @[PWM.scala 42:9]
    end
    if (_ip_T_27) begin // @[PWM.scala 43:50]
      ip_1 <= scale_io_regs_cfg_write__ip_1; // @[PWM.scala 43:56]
    end else begin
      ip_1 <= _ip_T_21; // @[PWM.scala 42:9]
    end
    if (_ip_T_27) begin // @[PWM.scala 43:50]
      ip_2 <= scale_io_regs_cfg_write__ip_2; // @[PWM.scala 43:56]
    end else begin
      ip_2 <= _ip_T_22; // @[PWM.scala 42:9]
    end
    if (_ip_T_27) begin // @[PWM.scala 43:50]
      ip_3 <= scale_io_regs_cfg_write__ip_3; // @[PWM.scala 43:56]
    end else begin
      ip_3 <= _ip_T_23; // @[PWM.scala 42:9]
    end
    if (_gang_T_3) begin // @[Reg.scala 17:18]
      gang_0 <= scale_io_regs_cfg_write__gang_0; // @[Reg.scala 17:22]
    end
    if (_gang_T_3) begin // @[Reg.scala 17:18]
      gang_1 <= scale_io_regs_cfg_write__gang_1; // @[Reg.scala 17:22]
    end
    if (_gang_T_3) begin // @[Reg.scala 17:18]
      gang_2 <= scale_io_regs_cfg_write__gang_2; // @[Reg.scala 17:22]
    end
    if (_gang_T_3) begin // @[Reg.scala 17:18]
      gang_3 <= scale_io_regs_cfg_write__gang_3; // @[Reg.scala 17:22]
    end
    if (reset) begin // @[Reg.scala 28:20]
      extra_0 <= 1'h0; // @[Reg.scala 28:20]
    end else if (_extra_T_3) begin // @[Reg.scala 29:18]
      extra_0 <= scale_io_regs_cfg_write__extra_0; // @[Reg.scala 29:22]
    end
    if (reset) begin // @[Reg.scala 28:20]
      extra_1 <= 1'h0; // @[Reg.scala 28:20]
    end else if (_extra_T_3) begin // @[Reg.scala 29:18]
      extra_1 <= scale_io_regs_cfg_write__extra_1; // @[Reg.scala 29:22]
    end
    if (reset) begin // @[Reg.scala 28:20]
      extra_2 <= 1'h0; // @[Reg.scala 28:20]
    end else if (_extra_T_3) begin // @[Reg.scala 29:18]
      extra_2 <= scale_io_regs_cfg_write__extra_2; // @[Reg.scala 29:22]
    end
    if (reset) begin // @[Reg.scala 28:20]
      extra_3 <= 1'h0; // @[Reg.scala 28:20]
    end else if (_extra_T_3) begin // @[Reg.scala 29:18]
      extra_3 <= scale_io_regs_cfg_write__extra_3; // @[Reg.scala 29:22]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  scale = _RAND_0[3:0];
  _RAND_1 = {1{`RANDOM}};
  cmp_0 = _RAND_1[15:0];
  _RAND_2 = {1{`RANDOM}};
  cmp_1 = _RAND_2[15:0];
  _RAND_3 = {1{`RANDOM}};
  cmp_2 = _RAND_3[15:0];
  _RAND_4 = {1{`RANDOM}};
  cmp_3 = _RAND_4[15:0];
  _RAND_5 = {1{`RANDOM}};
  small_ = _RAND_5[4:0];
  _RAND_6 = {1{`RANDOM}};
  countAlways = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  oneShot = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  large_ = _RAND_8[25:0];
  _RAND_9 = {1{`RANDOM}};
  center_0 = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  center_1 = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  center_2 = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  center_3 = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  zerocmp = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  ip_doSticky_x1_deglitch_r = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  ip_doSticky_x1_sticky_r = _RAND_15[0:0];
  _RAND_16 = {1{`RANDOM}};
  ip_doSticky = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  ip_0 = _RAND_17[0:0];
  _RAND_18 = {1{`RANDOM}};
  ip_1 = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  ip_2 = _RAND_19[0:0];
  _RAND_20 = {1{`RANDOM}};
  ip_3 = _RAND_20[0:0];
  _RAND_21 = {1{`RANDOM}};
  gang_0 = _RAND_21[0:0];
  _RAND_22 = {1{`RANDOM}};
  gang_1 = _RAND_22[0:0];
  _RAND_23 = {1{`RANDOM}};
  gang_2 = _RAND_23[0:0];
  _RAND_24 = {1{`RANDOM}};
  gang_3 = _RAND_24[0:0];
  _RAND_25 = {1{`RANDOM}};
  extra_0 = _RAND_25[0:0];
  _RAND_26 = {1{`RANDOM}};
  extra_1 = _RAND_26[0:0];
  _RAND_27 = {1{`RANDOM}};
  extra_2 = _RAND_27[0:0];
  _RAND_28 = {1{`RANDOM}};
  extra_3 = _RAND_28[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLPWM(
  input         clock,
  input         reset,
  output        auto_int_xing_out_sync_0,
  output        auto_int_xing_out_sync_1,
  output        auto_int_xing_out_sync_2,
  output        auto_int_xing_out_sync_3,
  output        auto_control_xing_in_a_ready,
  input         auto_control_xing_in_a_valid,
  input  [2:0]  auto_control_xing_in_a_bits_opcode,
  input  [2:0]  auto_control_xing_in_a_bits_param,
  input  [1:0]  auto_control_xing_in_a_bits_size,
  input  [6:0]  auto_control_xing_in_a_bits_source,
  input  [28:0] auto_control_xing_in_a_bits_address,
  input  [3:0]  auto_control_xing_in_a_bits_mask,
  input  [31:0] auto_control_xing_in_a_bits_data,
  input         auto_control_xing_in_a_bits_corrupt,
  input         auto_control_xing_in_d_ready,
  output        auto_control_xing_in_d_valid,
  output [2:0]  auto_control_xing_in_d_bits_opcode,
  output [1:0]  auto_control_xing_in_d_bits_size,
  output [6:0]  auto_control_xing_in_d_bits_source,
  output [31:0] auto_control_xing_in_d_bits_data,
  output        auto_io_out_gpio_0,
  output        auto_io_out_gpio_1,
  output        auto_io_out_gpio_2,
  output        auto_io_out_gpio_3
);
  wire  buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
  wire [28:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
  wire [28:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
  wire  intsource_clock; // @[Crossing.scala 26:31]
  wire  intsource_reset; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_0; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_1; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_2; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_3; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_0; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_1; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_2; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_3; // @[Crossing.scala 26:31]
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  pwm_clock; // @[PWM.scala 95:21]
  wire  pwm_reset; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__ip_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__ip_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__ip_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__ip_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__gang_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__gang_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__gang_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__gang_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__extra_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__extra_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__extra_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__extra_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__center_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__center_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__center_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__center_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__running; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__countAlways; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__deglitch; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__zerocmp; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__sticky; // @[PWM.scala 95:21]
  wire [3:0] pwm_scale_io_regs_cfg_write__scale; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_ip_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_ip_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_ip_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_ip_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_gang_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_gang_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_gang_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_gang_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_extra_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_extra_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_extra_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_extra_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_center_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_center_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_center_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_center_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_running; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_countAlways; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_deglitch; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_zerocmp; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_sticky; // @[PWM.scala 95:21]
  wire [3:0] pwm_scale_io_regs_cfg_read_scale; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_ip_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_ip_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_ip_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_ip_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_gang_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_gang_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_gang_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_gang_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_extra_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_extra_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_extra_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_extra_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_center_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_center_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_center_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_center_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_running; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_countAlways; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_deglitch; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_zerocmp; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_sticky; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_scale; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_countLo_write_valid; // @[PWM.scala 95:21]
  wire [30:0] pwm_scale_io_regs_countLo_write_bits; // @[PWM.scala 95:21]
  wire [30:0] pwm_scale_io_regs_countLo_read; // @[PWM.scala 95:21]
  wire [15:0] pwm_scale_io_regs_s_read; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cmp_0_write_valid; // @[PWM.scala 95:21]
  wire [15:0] pwm_scale_io_regs_cmp_0_write_bits; // @[PWM.scala 95:21]
  wire [15:0] pwm_scale_io_regs_cmp_0_read; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cmp_1_write_valid; // @[PWM.scala 95:21]
  wire [15:0] pwm_scale_io_regs_cmp_1_write_bits; // @[PWM.scala 95:21]
  wire [15:0] pwm_scale_io_regs_cmp_1_read; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cmp_2_write_valid; // @[PWM.scala 95:21]
  wire [15:0] pwm_scale_io_regs_cmp_2_write_bits; // @[PWM.scala 95:21]
  wire [15:0] pwm_scale_io_regs_cmp_2_read; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cmp_3_write_valid; // @[PWM.scala 95:21]
  wire [15:0] pwm_scale_io_regs_cmp_3_write_bits; // @[PWM.scala 95:21]
  wire [15:0] pwm_scale_io_regs_cmp_3_read; // @[PWM.scala 95:21]
  wire  pwm_scale_io_ip_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_ip_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_ip_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_ip_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_gpio_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_gpio_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_gpio_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_gpio_3; // @[PWM.scala 95:21]
  wire [2:0] bundleIn_0_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  in_bits_read = bundleIn_0_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 72:36]
  wire [28:0] bundleIn_0_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [9:0] in_bits_index = bundleIn_0_a_bits_address[11:2]; // @[RegisterRouter.scala 71:18 73:19]
  wire [9:0] out_findex = in_bits_index & 10'h3f0; // @[RegisterRouter.scala 83:24]
  wire  _out_T = out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [3:0] bundleIn_0_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [7:0] _out_frontMask_T_5 = bundleIn_0_a_bits_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_frontMask_T_7 = bundleIn_0_a_bits_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_frontMask_T_9 = bundleIn_0_a_bits_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_frontMask_T_11 = bundleIn_0_a_bits_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [31:0] out_frontMask = {_out_frontMask_T_11,_out_frontMask_T_9,_out_frontMask_T_7,_out_frontMask_T_5}; // @[Cat.scala 31:58]
  wire  out_wimask = &out_frontMask[3:0]; // @[RegisterRouter.scala 83:24]
  wire  bundleIn_0_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  bundleIn_0_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [3:0] out_oindex = {in_bits_index[3],in_bits_index[2],in_bits_index[1],in_bits_index[0]}; // @[Cat.scala 31:58]
  wire [15:0] _out_frontSel_T = 16'h1 << out_oindex; // @[OneHot.scala 57:35]
  wire  out_frontSel_0 = _out_frontSel_T[0]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_0 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_0 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [31:0] bundleIn_0_a_bits_data = buffer_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [3:0] _out_T_29 = pwm_scale_io_regs_cfg_read_scale; // @[RegisterRouter.scala 83:24]
  wire [4:0] out_prepend = {1'h0,_out_T_29}; // @[Cat.scala 31:58]
  wire [7:0] _out_T_38 = {{3'd0}, out_prepend}; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_2 = &out_frontMask[8]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_3 = &out_frontMask[9]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_4 = &out_frontMask[10]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_6 = &out_frontMask[12]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_7 = &out_frontMask[13]; // @[RegisterRouter.scala 83:24]
  wire [14:0] out_prepend_7 = {1'h0,pwm_scale_io_regs_cfg_read_running,pwm_scale_io_regs_cfg_read_countAlways,1'h0,
    pwm_scale_io_regs_cfg_read_deglitch,pwm_scale_io_regs_cfg_read_zerocmp,pwm_scale_io_regs_cfg_read_sticky,_out_T_38}; // @[Cat.scala 31:58]
  wire [15:0] _out_T_111 = {{1'd0}, out_prepend_7}; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_9 = &out_frontMask[16]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_10 = &out_frontMask[17]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_11 = &out_frontMask[18]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_12 = &out_frontMask[19]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_13 = &out_frontMask[20]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_14 = &out_frontMask[21]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_15 = &out_frontMask[22]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_16 = &out_frontMask[23]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_17 = &out_frontMask[24]; // @[RegisterRouter.scala 83:24]
  wire [24:0] out_prepend_16 = {pwm_scale_io_regs_cfg_read_gang_0,pwm_scale_io_regs_cfg_read_extra_3,
    pwm_scale_io_regs_cfg_read_extra_2,pwm_scale_io_regs_cfg_read_extra_1,pwm_scale_io_regs_cfg_read_extra_0,
    pwm_scale_io_regs_cfg_read_center_3,pwm_scale_io_regs_cfg_read_center_2,pwm_scale_io_regs_cfg_read_center_1,
    pwm_scale_io_regs_cfg_read_center_0,_out_T_111}; // @[Cat.scala 31:58]
  wire  out_wimask_18 = &out_frontMask[25]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_19 = &out_frontMask[26]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_20 = &out_frontMask[27]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_21 = &out_frontMask[28]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_22 = &out_frontMask[29]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_23 = &out_frontMask[30]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_24 = &out_frontMask[31]; // @[RegisterRouter.scala 83:24]
  wire [31:0] out_prepend_23 = {pwm_scale_io_regs_cfg_read_ip_3,pwm_scale_io_regs_cfg_read_ip_2,
    pwm_scale_io_regs_cfg_read_ip_1,pwm_scale_io_regs_cfg_read_ip_0,pwm_scale_io_regs_cfg_read_gang_3,
    pwm_scale_io_regs_cfg_read_gang_2,pwm_scale_io_regs_cfg_read_gang_1,out_prepend_16}; // @[Cat.scala 31:58]
  wire  out_wimask_25 = &out_frontMask[15:0]; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_10 = _out_frontSel_T[10]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_25 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_10 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_T_298 = pwm_scale_io_regs_cmp_2_read; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_9 = _out_frontSel_T[9]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_27 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_9 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_T_318 = pwm_scale_io_regs_cmp_1_read; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_28 = &out_frontMask[30:0]; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_2 = _out_frontSel_T[2]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_28 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_2 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [30:0] _out_T_329 = pwm_scale_io_regs_countLo_read; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_11 = _out_frontSel_T[11]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_31 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_11 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_T_358 = pwm_scale_io_regs_cmp_3_read; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_8 = _out_frontSel_T[8]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_32 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_8 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_T_369 = pwm_scale_io_regs_cmp_0_read; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_T_378 = pwm_scale_io_regs_s_read; // @[RegisterRouter.scala 83:24]
  wire  _GEN_66 = 4'h2 == out_oindex ? _out_T : 4'h1 == out_oindex | _out_T; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_67 = 4'h3 == out_oindex ? _out_T : _GEN_66; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_68 = 4'h4 == out_oindex ? _out_T : _GEN_67; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_70 = 4'h6 == out_oindex ? _out_T : 4'h5 == out_oindex | _GEN_68; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_71 = 4'h7 == out_oindex ? _out_T : _GEN_70; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_72 = 4'h8 == out_oindex ? _out_T : _GEN_71; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_73 = 4'h9 == out_oindex ? _out_T : _GEN_72; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_74 = 4'ha == out_oindex ? _out_T : _GEN_73; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_75 = 4'hb == out_oindex ? _out_T : _GEN_74; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_79 = 4'hf == out_oindex | (4'he == out_oindex | (4'hd == out_oindex | (4'hc == out_oindex | _GEN_75))); // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_81 = 4'h1 == out_oindex ? 32'h0 : out_prepend_23; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_2 = {{1'd0}, _out_T_329}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_82 = 4'h2 == out_oindex ? _out_out_bits_data_WIRE_1_2 : _GEN_81; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_83 = 4'h3 == out_oindex ? 32'h0 : _GEN_82; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_4 = {{16'd0}, _out_T_378}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_84 = 4'h4 == out_oindex ? _out_out_bits_data_WIRE_1_4 : _GEN_83; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_85 = 4'h5 == out_oindex ? 32'h0 : _GEN_84; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_86 = 4'h6 == out_oindex ? 32'h0 : _GEN_85; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_87 = 4'h7 == out_oindex ? 32'h1 : _GEN_86; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_8 = {{16'd0}, _out_T_369}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_88 = 4'h8 == out_oindex ? _out_out_bits_data_WIRE_1_8 : _GEN_87; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_9 = {{16'd0}, _out_T_318}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_89 = 4'h9 == out_oindex ? _out_out_bits_data_WIRE_1_9 : _GEN_88; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_10 = {{16'd0}, _out_T_298}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_90 = 4'ha == out_oindex ? _out_out_bits_data_WIRE_1_10 : _GEN_89; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_11 = {{16'd0}, _out_T_358}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_91 = 4'hb == out_oindex ? _out_out_bits_data_WIRE_1_11 : _GEN_90; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_92 = 4'hc == out_oindex ? 32'h0 : _GEN_91; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_93 = 4'hd == out_oindex ? 32'h0 : _GEN_92; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_94 = 4'he == out_oindex ? 32'h0 : _GEN_93; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_95 = 4'hf == out_oindex ? 32'h0 : _GEN_94; // @[MuxLiteral.scala 48:{10,10}]
  TLBuffer_13 buffer ( // @[Buffer.scala 68:28]
    .auto_in_a_ready(buffer_auto_in_a_ready),
    .auto_in_a_valid(buffer_auto_in_a_valid),
    .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
    .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
    .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
    .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
    .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
    .auto_in_a_bits_data(buffer_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
    .auto_in_d_ready(buffer_auto_in_d_ready),
    .auto_in_d_valid(buffer_auto_in_d_valid),
    .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
    .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
    .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
    .auto_out_a_ready(buffer_auto_out_a_ready),
    .auto_out_a_valid(buffer_auto_out_a_valid),
    .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
    .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
    .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
    .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
    .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
    .auto_out_a_bits_data(buffer_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
    .auto_out_d_ready(buffer_auto_out_d_ready),
    .auto_out_d_valid(buffer_auto_out_d_valid),
    .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
    .auto_out_d_bits_source(buffer_auto_out_d_bits_source),
    .auto_out_d_bits_data(buffer_auto_out_d_bits_data)
  );
  IntSyncCrossingSource_18 intsource ( // @[Crossing.scala 26:31]
    .clock(intsource_clock),
    .reset(intsource_reset),
    .auto_in_0(intsource_auto_in_0),
    .auto_in_1(intsource_auto_in_1),
    .auto_in_2(intsource_auto_in_2),
    .auto_in_3(intsource_auto_in_3),
    .auto_out_sync_0(intsource_auto_out_sync_0),
    .auto_out_sync_1(intsource_auto_out_sync_1),
    .auto_out_sync_2(intsource_auto_out_sync_2),
    .auto_out_sync_3(intsource_auto_out_sync_3)
  );
  TLMonitor_67 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  PWMTimer pwm ( // @[PWM.scala 95:21]
    .clock(pwm_clock),
    .reset(pwm_reset),
    .scale_io_regs_cfg_write__ip_0(pwm_scale_io_regs_cfg_write__ip_0),
    .scale_io_regs_cfg_write__ip_1(pwm_scale_io_regs_cfg_write__ip_1),
    .scale_io_regs_cfg_write__ip_2(pwm_scale_io_regs_cfg_write__ip_2),
    .scale_io_regs_cfg_write__ip_3(pwm_scale_io_regs_cfg_write__ip_3),
    .scale_io_regs_cfg_write__gang_0(pwm_scale_io_regs_cfg_write__gang_0),
    .scale_io_regs_cfg_write__gang_1(pwm_scale_io_regs_cfg_write__gang_1),
    .scale_io_regs_cfg_write__gang_2(pwm_scale_io_regs_cfg_write__gang_2),
    .scale_io_regs_cfg_write__gang_3(pwm_scale_io_regs_cfg_write__gang_3),
    .scale_io_regs_cfg_write__extra_0(pwm_scale_io_regs_cfg_write__extra_0),
    .scale_io_regs_cfg_write__extra_1(pwm_scale_io_regs_cfg_write__extra_1),
    .scale_io_regs_cfg_write__extra_2(pwm_scale_io_regs_cfg_write__extra_2),
    .scale_io_regs_cfg_write__extra_3(pwm_scale_io_regs_cfg_write__extra_3),
    .scale_io_regs_cfg_write__center_0(pwm_scale_io_regs_cfg_write__center_0),
    .scale_io_regs_cfg_write__center_1(pwm_scale_io_regs_cfg_write__center_1),
    .scale_io_regs_cfg_write__center_2(pwm_scale_io_regs_cfg_write__center_2),
    .scale_io_regs_cfg_write__center_3(pwm_scale_io_regs_cfg_write__center_3),
    .scale_io_regs_cfg_write__running(pwm_scale_io_regs_cfg_write__running),
    .scale_io_regs_cfg_write__countAlways(pwm_scale_io_regs_cfg_write__countAlways),
    .scale_io_regs_cfg_write__deglitch(pwm_scale_io_regs_cfg_write__deglitch),
    .scale_io_regs_cfg_write__zerocmp(pwm_scale_io_regs_cfg_write__zerocmp),
    .scale_io_regs_cfg_write__sticky(pwm_scale_io_regs_cfg_write__sticky),
    .scale_io_regs_cfg_write__scale(pwm_scale_io_regs_cfg_write__scale),
    .scale_io_regs_cfg_read_ip_0(pwm_scale_io_regs_cfg_read_ip_0),
    .scale_io_regs_cfg_read_ip_1(pwm_scale_io_regs_cfg_read_ip_1),
    .scale_io_regs_cfg_read_ip_2(pwm_scale_io_regs_cfg_read_ip_2),
    .scale_io_regs_cfg_read_ip_3(pwm_scale_io_regs_cfg_read_ip_3),
    .scale_io_regs_cfg_read_gang_0(pwm_scale_io_regs_cfg_read_gang_0),
    .scale_io_regs_cfg_read_gang_1(pwm_scale_io_regs_cfg_read_gang_1),
    .scale_io_regs_cfg_read_gang_2(pwm_scale_io_regs_cfg_read_gang_2),
    .scale_io_regs_cfg_read_gang_3(pwm_scale_io_regs_cfg_read_gang_3),
    .scale_io_regs_cfg_read_extra_0(pwm_scale_io_regs_cfg_read_extra_0),
    .scale_io_regs_cfg_read_extra_1(pwm_scale_io_regs_cfg_read_extra_1),
    .scale_io_regs_cfg_read_extra_2(pwm_scale_io_regs_cfg_read_extra_2),
    .scale_io_regs_cfg_read_extra_3(pwm_scale_io_regs_cfg_read_extra_3),
    .scale_io_regs_cfg_read_center_0(pwm_scale_io_regs_cfg_read_center_0),
    .scale_io_regs_cfg_read_center_1(pwm_scale_io_regs_cfg_read_center_1),
    .scale_io_regs_cfg_read_center_2(pwm_scale_io_regs_cfg_read_center_2),
    .scale_io_regs_cfg_read_center_3(pwm_scale_io_regs_cfg_read_center_3),
    .scale_io_regs_cfg_read_running(pwm_scale_io_regs_cfg_read_running),
    .scale_io_regs_cfg_read_countAlways(pwm_scale_io_regs_cfg_read_countAlways),
    .scale_io_regs_cfg_read_deglitch(pwm_scale_io_regs_cfg_read_deglitch),
    .scale_io_regs_cfg_read_zerocmp(pwm_scale_io_regs_cfg_read_zerocmp),
    .scale_io_regs_cfg_read_sticky(pwm_scale_io_regs_cfg_read_sticky),
    .scale_io_regs_cfg_read_scale(pwm_scale_io_regs_cfg_read_scale),
    .scale_io_regs_cfg_write_ip_0(pwm_scale_io_regs_cfg_write_ip_0),
    .scale_io_regs_cfg_write_ip_1(pwm_scale_io_regs_cfg_write_ip_1),
    .scale_io_regs_cfg_write_ip_2(pwm_scale_io_regs_cfg_write_ip_2),
    .scale_io_regs_cfg_write_ip_3(pwm_scale_io_regs_cfg_write_ip_3),
    .scale_io_regs_cfg_write_gang_0(pwm_scale_io_regs_cfg_write_gang_0),
    .scale_io_regs_cfg_write_gang_1(pwm_scale_io_regs_cfg_write_gang_1),
    .scale_io_regs_cfg_write_gang_2(pwm_scale_io_regs_cfg_write_gang_2),
    .scale_io_regs_cfg_write_gang_3(pwm_scale_io_regs_cfg_write_gang_3),
    .scale_io_regs_cfg_write_extra_0(pwm_scale_io_regs_cfg_write_extra_0),
    .scale_io_regs_cfg_write_extra_1(pwm_scale_io_regs_cfg_write_extra_1),
    .scale_io_regs_cfg_write_extra_2(pwm_scale_io_regs_cfg_write_extra_2),
    .scale_io_regs_cfg_write_extra_3(pwm_scale_io_regs_cfg_write_extra_3),
    .scale_io_regs_cfg_write_center_0(pwm_scale_io_regs_cfg_write_center_0),
    .scale_io_regs_cfg_write_center_1(pwm_scale_io_regs_cfg_write_center_1),
    .scale_io_regs_cfg_write_center_2(pwm_scale_io_regs_cfg_write_center_2),
    .scale_io_regs_cfg_write_center_3(pwm_scale_io_regs_cfg_write_center_3),
    .scale_io_regs_cfg_write_running(pwm_scale_io_regs_cfg_write_running),
    .scale_io_regs_cfg_write_countAlways(pwm_scale_io_regs_cfg_write_countAlways),
    .scale_io_regs_cfg_write_deglitch(pwm_scale_io_regs_cfg_write_deglitch),
    .scale_io_regs_cfg_write_zerocmp(pwm_scale_io_regs_cfg_write_zerocmp),
    .scale_io_regs_cfg_write_sticky(pwm_scale_io_regs_cfg_write_sticky),
    .scale_io_regs_cfg_write_scale(pwm_scale_io_regs_cfg_write_scale),
    .scale_io_regs_countLo_write_valid(pwm_scale_io_regs_countLo_write_valid),
    .scale_io_regs_countLo_write_bits(pwm_scale_io_regs_countLo_write_bits),
    .scale_io_regs_countLo_read(pwm_scale_io_regs_countLo_read),
    .scale_io_regs_s_read(pwm_scale_io_regs_s_read),
    .scale_io_regs_cmp_0_write_valid(pwm_scale_io_regs_cmp_0_write_valid),
    .scale_io_regs_cmp_0_write_bits(pwm_scale_io_regs_cmp_0_write_bits),
    .scale_io_regs_cmp_0_read(pwm_scale_io_regs_cmp_0_read),
    .scale_io_regs_cmp_1_write_valid(pwm_scale_io_regs_cmp_1_write_valid),
    .scale_io_regs_cmp_1_write_bits(pwm_scale_io_regs_cmp_1_write_bits),
    .scale_io_regs_cmp_1_read(pwm_scale_io_regs_cmp_1_read),
    .scale_io_regs_cmp_2_write_valid(pwm_scale_io_regs_cmp_2_write_valid),
    .scale_io_regs_cmp_2_write_bits(pwm_scale_io_regs_cmp_2_write_bits),
    .scale_io_regs_cmp_2_read(pwm_scale_io_regs_cmp_2_read),
    .scale_io_regs_cmp_3_write_valid(pwm_scale_io_regs_cmp_3_write_valid),
    .scale_io_regs_cmp_3_write_bits(pwm_scale_io_regs_cmp_3_write_bits),
    .scale_io_regs_cmp_3_read(pwm_scale_io_regs_cmp_3_read),
    .scale_io_ip_0(pwm_scale_io_ip_0),
    .scale_io_ip_1(pwm_scale_io_ip_1),
    .scale_io_ip_2(pwm_scale_io_ip_2),
    .scale_io_ip_3(pwm_scale_io_ip_3),
    .scale_io_gpio_0(pwm_scale_io_gpio_0),
    .scale_io_gpio_1(pwm_scale_io_gpio_1),
    .scale_io_gpio_2(pwm_scale_io_gpio_2),
    .scale_io_gpio_3(pwm_scale_io_gpio_3)
  );
  assign auto_int_xing_out_sync_0 = intsource_auto_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_1 = intsource_auto_out_sync_1; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_2 = intsource_auto_out_sync_2; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_3 = intsource_auto_out_sync_3; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_in_a_ready = buffer_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_valid = buffer_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_size = buffer_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_source = buffer_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_data = buffer_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_io_out_gpio_0 = pwm_scale_io_gpio_0; // @[Nodes.scala 1207:84 PWM.scala 97:15]
  assign auto_io_out_gpio_1 = pwm_scale_io_gpio_1; // @[Nodes.scala 1207:84 PWM.scala 97:15]
  assign auto_io_out_gpio_2 = pwm_scale_io_gpio_2; // @[Nodes.scala 1207:84 PWM.scala 97:15]
  assign auto_io_out_gpio_3 = pwm_scale_io_gpio_3; // @[Nodes.scala 1207:84 PWM.scala 97:15]
  assign buffer_auto_in_a_valid = auto_control_xing_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_opcode = auto_control_xing_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_param = auto_control_xing_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_size = auto_control_xing_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_source = auto_control_xing_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_address = auto_control_xing_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_mask = auto_control_xing_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_data = auto_control_xing_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_corrupt = auto_control_xing_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_d_ready = auto_control_xing_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_out_a_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign buffer_auto_out_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_data = _GEN_79 ? _GEN_95 : 32'h0; // @[RegisterRouter.scala 83:24]
  assign intsource_clock = clock;
  assign intsource_reset = reset;
  assign intsource_auto_in_0 = pwm_scale_io_ip_0; // @[Nodes.scala 1207:84 PWM.scala 96:16]
  assign intsource_auto_in_1 = pwm_scale_io_ip_1; // @[Nodes.scala 1207:84 PWM.scala 96:16]
  assign intsource_auto_in_2 = pwm_scale_io_ip_2; // @[Nodes.scala 1207:84 PWM.scala 96:16]
  assign intsource_auto_in_3 = pwm_scale_io_ip_3; // @[Nodes.scala 1207:84 PWM.scala 96:16]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_param = buffer_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign monitor_io_in_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign pwm_clock = clock;
  assign pwm_reset = reset;
  assign pwm_scale_io_regs_cfg_write__ip_0 = bundleIn_0_a_bits_data[28]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__ip_1 = bundleIn_0_a_bits_data[29]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__ip_2 = bundleIn_0_a_bits_data[30]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__ip_3 = bundleIn_0_a_bits_data[31]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__gang_0 = bundleIn_0_a_bits_data[24]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__gang_1 = bundleIn_0_a_bits_data[25]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__gang_2 = bundleIn_0_a_bits_data[26]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__gang_3 = bundleIn_0_a_bits_data[27]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__extra_0 = bundleIn_0_a_bits_data[20]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__extra_1 = bundleIn_0_a_bits_data[21]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__extra_2 = bundleIn_0_a_bits_data[22]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__extra_3 = bundleIn_0_a_bits_data[23]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__center_0 = bundleIn_0_a_bits_data[16]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__center_1 = bundleIn_0_a_bits_data[17]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__center_2 = bundleIn_0_a_bits_data[18]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__center_3 = bundleIn_0_a_bits_data[19]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__running = bundleIn_0_a_bits_data[13]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__countAlways = bundleIn_0_a_bits_data[12]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__deglitch = bundleIn_0_a_bits_data[10]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__zerocmp = bundleIn_0_a_bits_data[9]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__sticky = bundleIn_0_a_bits_data[8]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__scale = bundleIn_0_a_bits_data[3:0]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_ip_0 = out_wivalid_0 & out_wimask_21; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_ip_1 = out_wivalid_0 & out_wimask_22; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_ip_2 = out_wivalid_0 & out_wimask_23; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_ip_3 = out_wivalid_0 & out_wimask_24; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_gang_0 = out_wivalid_0 & out_wimask_17; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_gang_1 = out_wivalid_0 & out_wimask_18; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_gang_2 = out_wivalid_0 & out_wimask_19; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_gang_3 = out_wivalid_0 & out_wimask_20; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_extra_0 = out_wivalid_0 & out_wimask_13; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_extra_1 = out_wivalid_0 & out_wimask_14; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_extra_2 = out_wivalid_0 & out_wimask_15; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_extra_3 = out_wivalid_0 & out_wimask_16; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_center_0 = out_wivalid_0 & out_wimask_9; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_center_1 = out_wivalid_0 & out_wimask_10; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_center_2 = out_wivalid_0 & out_wimask_11; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_center_3 = out_wivalid_0 & out_wimask_12; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_running = out_wivalid_0 & out_wimask_7; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_countAlways = out_wivalid_0 & out_wimask_6; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_deglitch = out_wivalid_0 & out_wimask_4; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_zerocmp = out_wivalid_0 & out_wimask_3; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_sticky = out_wivalid_0 & out_wimask_2; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_scale = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_countLo_write_valid = out_wivalid_28 & out_wimask_28; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_countLo_write_bits = bundleIn_0_a_bits_data[30:0]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cmp_0_write_valid = out_wivalid_32 & out_wimask_25; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cmp_0_write_bits = bundleIn_0_a_bits_data[15:0]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cmp_1_write_valid = out_wivalid_27 & out_wimask_25; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cmp_1_write_bits = bundleIn_0_a_bits_data[15:0]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cmp_2_write_valid = out_wivalid_25 & out_wimask_25; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cmp_2_write_bits = bundleIn_0_a_bits_data[15:0]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cmp_3_write_valid = out_wivalid_31 & out_wimask_25; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cmp_3_write_bits = bundleIn_0_a_bits_data[15:0]; // @[RegisterRouter.scala 83:24]
endmodule
module ClockSinkDomain_10(
  output        auto_pwm_0_int_xing_out_sync_0,
  output        auto_pwm_0_int_xing_out_sync_1,
  output        auto_pwm_0_int_xing_out_sync_2,
  output        auto_pwm_0_int_xing_out_sync_3,
  output        auto_pwm_0_control_xing_in_a_ready,
  input         auto_pwm_0_control_xing_in_a_valid,
  input  [2:0]  auto_pwm_0_control_xing_in_a_bits_opcode,
  input  [2:0]  auto_pwm_0_control_xing_in_a_bits_param,
  input  [1:0]  auto_pwm_0_control_xing_in_a_bits_size,
  input  [6:0]  auto_pwm_0_control_xing_in_a_bits_source,
  input  [28:0] auto_pwm_0_control_xing_in_a_bits_address,
  input  [3:0]  auto_pwm_0_control_xing_in_a_bits_mask,
  input  [31:0] auto_pwm_0_control_xing_in_a_bits_data,
  input         auto_pwm_0_control_xing_in_a_bits_corrupt,
  input         auto_pwm_0_control_xing_in_d_ready,
  output        auto_pwm_0_control_xing_in_d_valid,
  output [2:0]  auto_pwm_0_control_xing_in_d_bits_opcode,
  output [1:0]  auto_pwm_0_control_xing_in_d_bits_size,
  output [6:0]  auto_pwm_0_control_xing_in_d_bits_source,
  output [31:0] auto_pwm_0_control_xing_in_d_bits_data,
  output        auto_pwm_0_io_out_gpio_0,
  output        auto_pwm_0_io_out_gpio_1,
  output        auto_pwm_0_io_out_gpio_2,
  output        auto_pwm_0_io_out_gpio_3,
  input         auto_clock_in_clock,
  input         auto_clock_in_reset
);
  wire  pwm_0_clock; // @[PWM.scala 135:49]
  wire  pwm_0_reset; // @[PWM.scala 135:49]
  wire  pwm_0_auto_int_xing_out_sync_0; // @[PWM.scala 135:49]
  wire  pwm_0_auto_int_xing_out_sync_1; // @[PWM.scala 135:49]
  wire  pwm_0_auto_int_xing_out_sync_2; // @[PWM.scala 135:49]
  wire  pwm_0_auto_int_xing_out_sync_3; // @[PWM.scala 135:49]
  wire  pwm_0_auto_control_xing_in_a_ready; // @[PWM.scala 135:49]
  wire  pwm_0_auto_control_xing_in_a_valid; // @[PWM.scala 135:49]
  wire [2:0] pwm_0_auto_control_xing_in_a_bits_opcode; // @[PWM.scala 135:49]
  wire [2:0] pwm_0_auto_control_xing_in_a_bits_param; // @[PWM.scala 135:49]
  wire [1:0] pwm_0_auto_control_xing_in_a_bits_size; // @[PWM.scala 135:49]
  wire [6:0] pwm_0_auto_control_xing_in_a_bits_source; // @[PWM.scala 135:49]
  wire [28:0] pwm_0_auto_control_xing_in_a_bits_address; // @[PWM.scala 135:49]
  wire [3:0] pwm_0_auto_control_xing_in_a_bits_mask; // @[PWM.scala 135:49]
  wire [31:0] pwm_0_auto_control_xing_in_a_bits_data; // @[PWM.scala 135:49]
  wire  pwm_0_auto_control_xing_in_a_bits_corrupt; // @[PWM.scala 135:49]
  wire  pwm_0_auto_control_xing_in_d_ready; // @[PWM.scala 135:49]
  wire  pwm_0_auto_control_xing_in_d_valid; // @[PWM.scala 135:49]
  wire [2:0] pwm_0_auto_control_xing_in_d_bits_opcode; // @[PWM.scala 135:49]
  wire [1:0] pwm_0_auto_control_xing_in_d_bits_size; // @[PWM.scala 135:49]
  wire [6:0] pwm_0_auto_control_xing_in_d_bits_source; // @[PWM.scala 135:49]
  wire [31:0] pwm_0_auto_control_xing_in_d_bits_data; // @[PWM.scala 135:49]
  wire  pwm_0_auto_io_out_gpio_0; // @[PWM.scala 135:49]
  wire  pwm_0_auto_io_out_gpio_1; // @[PWM.scala 135:49]
  wire  pwm_0_auto_io_out_gpio_2; // @[PWM.scala 135:49]
  wire  pwm_0_auto_io_out_gpio_3; // @[PWM.scala 135:49]
  TLPWM pwm_0 ( // @[PWM.scala 135:49]
    .clock(pwm_0_clock),
    .reset(pwm_0_reset),
    .auto_int_xing_out_sync_0(pwm_0_auto_int_xing_out_sync_0),
    .auto_int_xing_out_sync_1(pwm_0_auto_int_xing_out_sync_1),
    .auto_int_xing_out_sync_2(pwm_0_auto_int_xing_out_sync_2),
    .auto_int_xing_out_sync_3(pwm_0_auto_int_xing_out_sync_3),
    .auto_control_xing_in_a_ready(pwm_0_auto_control_xing_in_a_ready),
    .auto_control_xing_in_a_valid(pwm_0_auto_control_xing_in_a_valid),
    .auto_control_xing_in_a_bits_opcode(pwm_0_auto_control_xing_in_a_bits_opcode),
    .auto_control_xing_in_a_bits_param(pwm_0_auto_control_xing_in_a_bits_param),
    .auto_control_xing_in_a_bits_size(pwm_0_auto_control_xing_in_a_bits_size),
    .auto_control_xing_in_a_bits_source(pwm_0_auto_control_xing_in_a_bits_source),
    .auto_control_xing_in_a_bits_address(pwm_0_auto_control_xing_in_a_bits_address),
    .auto_control_xing_in_a_bits_mask(pwm_0_auto_control_xing_in_a_bits_mask),
    .auto_control_xing_in_a_bits_data(pwm_0_auto_control_xing_in_a_bits_data),
    .auto_control_xing_in_a_bits_corrupt(pwm_0_auto_control_xing_in_a_bits_corrupt),
    .auto_control_xing_in_d_ready(pwm_0_auto_control_xing_in_d_ready),
    .auto_control_xing_in_d_valid(pwm_0_auto_control_xing_in_d_valid),
    .auto_control_xing_in_d_bits_opcode(pwm_0_auto_control_xing_in_d_bits_opcode),
    .auto_control_xing_in_d_bits_size(pwm_0_auto_control_xing_in_d_bits_size),
    .auto_control_xing_in_d_bits_source(pwm_0_auto_control_xing_in_d_bits_source),
    .auto_control_xing_in_d_bits_data(pwm_0_auto_control_xing_in_d_bits_data),
    .auto_io_out_gpio_0(pwm_0_auto_io_out_gpio_0),
    .auto_io_out_gpio_1(pwm_0_auto_io_out_gpio_1),
    .auto_io_out_gpio_2(pwm_0_auto_io_out_gpio_2),
    .auto_io_out_gpio_3(pwm_0_auto_io_out_gpio_3)
  );
  assign auto_pwm_0_int_xing_out_sync_0 = pwm_0_auto_int_xing_out_sync_0; // @[LazyModule.scala 311:12]
  assign auto_pwm_0_int_xing_out_sync_1 = pwm_0_auto_int_xing_out_sync_1; // @[LazyModule.scala 311:12]
  assign auto_pwm_0_int_xing_out_sync_2 = pwm_0_auto_int_xing_out_sync_2; // @[LazyModule.scala 311:12]
  assign auto_pwm_0_int_xing_out_sync_3 = pwm_0_auto_int_xing_out_sync_3; // @[LazyModule.scala 311:12]
  assign auto_pwm_0_control_xing_in_a_ready = pwm_0_auto_control_xing_in_a_ready; // @[LazyModule.scala 309:16]
  assign auto_pwm_0_control_xing_in_d_valid = pwm_0_auto_control_xing_in_d_valid; // @[LazyModule.scala 309:16]
  assign auto_pwm_0_control_xing_in_d_bits_opcode = pwm_0_auto_control_xing_in_d_bits_opcode; // @[LazyModule.scala 309:16]
  assign auto_pwm_0_control_xing_in_d_bits_size = pwm_0_auto_control_xing_in_d_bits_size; // @[LazyModule.scala 309:16]
  assign auto_pwm_0_control_xing_in_d_bits_source = pwm_0_auto_control_xing_in_d_bits_source; // @[LazyModule.scala 309:16]
  assign auto_pwm_0_control_xing_in_d_bits_data = pwm_0_auto_control_xing_in_d_bits_data; // @[LazyModule.scala 309:16]
  assign auto_pwm_0_io_out_gpio_0 = pwm_0_auto_io_out_gpio_0; // @[LazyModule.scala 311:12]
  assign auto_pwm_0_io_out_gpio_1 = pwm_0_auto_io_out_gpio_1; // @[LazyModule.scala 311:12]
  assign auto_pwm_0_io_out_gpio_2 = pwm_0_auto_io_out_gpio_2; // @[LazyModule.scala 311:12]
  assign auto_pwm_0_io_out_gpio_3 = pwm_0_auto_io_out_gpio_3; // @[LazyModule.scala 311:12]
  assign pwm_0_clock = auto_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign pwm_0_reset = auto_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign pwm_0_auto_control_xing_in_a_valid = auto_pwm_0_control_xing_in_a_valid; // @[LazyModule.scala 309:16]
  assign pwm_0_auto_control_xing_in_a_bits_opcode = auto_pwm_0_control_xing_in_a_bits_opcode; // @[LazyModule.scala 309:16]
  assign pwm_0_auto_control_xing_in_a_bits_param = auto_pwm_0_control_xing_in_a_bits_param; // @[LazyModule.scala 309:16]
  assign pwm_0_auto_control_xing_in_a_bits_size = auto_pwm_0_control_xing_in_a_bits_size; // @[LazyModule.scala 309:16]
  assign pwm_0_auto_control_xing_in_a_bits_source = auto_pwm_0_control_xing_in_a_bits_source; // @[LazyModule.scala 309:16]
  assign pwm_0_auto_control_xing_in_a_bits_address = auto_pwm_0_control_xing_in_a_bits_address; // @[LazyModule.scala 309:16]
  assign pwm_0_auto_control_xing_in_a_bits_mask = auto_pwm_0_control_xing_in_a_bits_mask; // @[LazyModule.scala 309:16]
  assign pwm_0_auto_control_xing_in_a_bits_data = auto_pwm_0_control_xing_in_a_bits_data; // @[LazyModule.scala 309:16]
  assign pwm_0_auto_control_xing_in_a_bits_corrupt = auto_pwm_0_control_xing_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
  assign pwm_0_auto_control_xing_in_d_ready = auto_pwm_0_control_xing_in_d_ready; // @[LazyModule.scala 309:16]
endmodule
module IntSyncSyncCrossingSink_16(
  input   auto_in_sync_0,
  input   auto_in_sync_1,
  input   auto_in_sync_2,
  input   auto_in_sync_3,
  output  auto_out_0,
  output  auto_out_1,
  output  auto_out_2,
  output  auto_out_3
);
  assign auto_out_0 = auto_in_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_1 = auto_in_sync_1; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_2 = auto_in_sync_2; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_out_3 = auto_in_sync_3; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module TLMonitor_68(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [1:0]  io_in_a_bits_size,
  input  [6:0]  io_in_a_bits_source,
  input  [28:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_size,
  input  [6:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [95:0] _RAND_10;
  reg [383:0] _RAND_11;
  reg [383:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [95:0] _RAND_16;
  reg [383:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T_4 = io_in_a_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire [4:0] _is_aligned_mask_T_1 = 5'h3 << io_in_a_bits_size; // @[package.scala 234:77]
  wire [1:0] is_aligned_mask = ~_is_aligned_mask_T_1[1:0]; // @[package.scala 234:46]
  wire [28:0] _GEN_71 = {{27'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 2'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [28:0] _T_33 = io_in_a_bits_address ^ 29'h10025000; // @[Parameters.scala 137:31]
  wire [29:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
  wire [29:0] _T_36 = $signed(_T_34) & -30'sh1000; // @[Parameters.scala 137:52]
  wire  _T_37 = $signed(_T_36) == 30'sh0; // @[Parameters.scala 137:67]
  wire  _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_74 = _T_73 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_164 = io_in_a_bits_size <= 2'h2; // @[Parameters.scala 92:42]
  wire  _T_172 = _T_164 & _T_37; // @[Parameters.scala 670:56]
  wire  _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_218 = _source_ok_T_4 & _T_172; // @[Monitor.scala 115:71]
  wire  _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_273 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_274 = io_in_a_bits_mask & _T_273; // @[Monitor.scala 127:31]
  wire  _T_275 = _T_274 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_279 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_347 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_355 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_385 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_397 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_10 = io_in_d_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire  _T_401 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_405 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 312:27]
  wire  _T_421 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_449 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_478 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_495 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_513 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [1:0] size; // @[Monitor.scala 386:22]
  reg [6:0] source; // @[Monitor.scala 387:22]
  reg [28:0] address; // @[Monitor.scala 388:22]
  wire  _T_543 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_544 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_548 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_552 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_556 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_560 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] size_1; // @[Monitor.scala 537:22]
  reg [6:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_567 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_568 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_576 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_580 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [95:0] inflight; // @[Monitor.scala 611:27]
  reg [383:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [383:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [8:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [9:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [383:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [383:0] _GEN_73 = {{368'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[383:1]}; // @[Monitor.scala 634:152]
  wire [383:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [383:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
  wire [383:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[383:1]}; // @[Monitor.scala 638:144]
  wire  _T_594 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [127:0] _a_set_wo_ready_T = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_597 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
  wire [8:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [9:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [1026:0] _GEN_1 = {{1023'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [1026:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
  wire [1025:0] _GEN_2 = {{1023'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [1025:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [95:0] _T_599 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_601 = ~_T_599[0]; // @[Monitor.scala 658:17]
  wire [127:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 652:72 653:28]
  wire [1026:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 1027'h0; // @[Monitor.scala 652:72 656:28]
  wire [1025:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 1026'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_605 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_607 = ~_T_401; // @[Monitor.scala 671:74]
  wire  _T_608 = io_in_d_valid & d_first_1 & ~_T_401; // @[Monitor.scala 671:71]
  wire [127:0] _d_clr_wo_ready_T = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [1038:0] _GEN_3 = {{1023'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [1038:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [127:0] _GEN_22 = d_first_done & d_first_1 & _T_607 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 675:91 676:21]
  wire [1038:0] _GEN_23 = d_first_done & d_first_1 & _T_607 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_594 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [95:0] _T_618 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_620 = _T_618[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_625 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_626 = io_in_d_bits_opcode == _GEN_32 | _T_625; // @[Monitor.scala 685:77]
  wire  _T_630 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_637 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_638 = io_in_d_bits_opcode == _GEN_48 | _T_637; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_642 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_652 = _T_605 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_607; // @[Monitor.scala 694:116]
  wire  _T_654 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [95:0] a_set = _GEN_16[95:0];
  wire [95:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [95:0] d_clr = _GEN_22[95:0];
  wire [95:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [95:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [383:0] a_opcodes_set = _GEN_19[383:0];
  wire [383:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [383:0] d_opcodes_clr = _GEN_23[383:0];
  wire [383:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [383:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [383:0] a_sizes_set = _GEN_20[383:0];
  wire [383:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [383:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_663 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [95:0] inflight_1; // @[Monitor.scala 723:35]
  reg [383:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [383:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [383:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
  wire [383:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[383:1]}; // @[Monitor.scala 747:146]
  wire  _T_689 = io_in_d_valid & d_first_2 & _T_401; // @[Monitor.scala 779:71]
  wire [127:0] _GEN_67 = d_first_done & d_first_2 & _T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 783:90 784:21]
  wire [1038:0] _GEN_68 = d_first_done & d_first_2 & _T_401 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 783:90 785:21]
  wire [95:0] _T_697 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_707 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [95:0] d_clr_1 = _GEN_67[95:0];
  wire [95:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [95:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [383:0] d_opcodes_clr_1 = _GEN_68[383:0];
  wire [383:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [383:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_727 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 1'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= 1'h0;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 96'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 384'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 384'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 1'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= 1'h0;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 96'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 384'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= 1'h0;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (d_first_done) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_172 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_172) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_275 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_275) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_309 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_309) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_347 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_347) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_385 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_397 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_397) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_478 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_478 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_495 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_495 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_513 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_513 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_544 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_544) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_548 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_548) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_552 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_552) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_556 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_556) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_560 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_560) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_568 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_568) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_576 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_576) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_580 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_580) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_601 & (_T_597 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_597 & ~reset & ~_T_601) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_620 & (_T_608 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & _T_2 & ~_T_620) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_626 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_626) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_630 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_630) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_638 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_638) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_642 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_642) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_654 & (_T_652 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_652 & _T_2 & ~_T_654) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_663 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_663) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_697[0] & (_T_689 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_689 & _T_2 & ~_T_697[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_707 & (_T_689 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_689 & _T_2 & ~_T_707) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_727 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_727) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[6:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[28:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[6:0];
  _RAND_10 = {3{`RANDOM}};
  inflight = _RAND_10[95:0];
  _RAND_11 = {12{`RANDOM}};
  inflight_opcodes = _RAND_11[383:0];
  _RAND_12 = {12{`RANDOM}};
  inflight_sizes = _RAND_12[383:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {3{`RANDOM}};
  inflight_1 = _RAND_16[95:0];
  _RAND_17 = {12{`RANDOM}};
  inflight_sizes_1 = _RAND_17[383:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLPWM_1(
  input         clock,
  input         reset,
  output        auto_int_xing_out_sync_0,
  output        auto_int_xing_out_sync_1,
  output        auto_int_xing_out_sync_2,
  output        auto_int_xing_out_sync_3,
  output        auto_control_xing_in_a_ready,
  input         auto_control_xing_in_a_valid,
  input  [2:0]  auto_control_xing_in_a_bits_opcode,
  input  [2:0]  auto_control_xing_in_a_bits_param,
  input  [1:0]  auto_control_xing_in_a_bits_size,
  input  [6:0]  auto_control_xing_in_a_bits_source,
  input  [28:0] auto_control_xing_in_a_bits_address,
  input  [3:0]  auto_control_xing_in_a_bits_mask,
  input  [31:0] auto_control_xing_in_a_bits_data,
  input         auto_control_xing_in_a_bits_corrupt,
  input         auto_control_xing_in_d_ready,
  output        auto_control_xing_in_d_valid,
  output [2:0]  auto_control_xing_in_d_bits_opcode,
  output [1:0]  auto_control_xing_in_d_bits_size,
  output [6:0]  auto_control_xing_in_d_bits_source,
  output [31:0] auto_control_xing_in_d_bits_data,
  output        auto_io_out_gpio_0,
  output        auto_io_out_gpio_1,
  output        auto_io_out_gpio_2,
  output        auto_io_out_gpio_3
);
  wire  buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
  wire [28:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
  wire [28:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
  wire  intsource_clock; // @[Crossing.scala 26:31]
  wire  intsource_reset; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_0; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_1; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_2; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_3; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_0; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_1; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_2; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_3; // @[Crossing.scala 26:31]
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  pwm_clock; // @[PWM.scala 95:21]
  wire  pwm_reset; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__ip_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__ip_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__ip_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__ip_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__gang_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__gang_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__gang_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__gang_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__extra_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__extra_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__extra_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__extra_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__center_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__center_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__center_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__center_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__running; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__countAlways; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__deglitch; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__zerocmp; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__sticky; // @[PWM.scala 95:21]
  wire [3:0] pwm_scale_io_regs_cfg_write__scale; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_ip_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_ip_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_ip_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_ip_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_gang_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_gang_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_gang_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_gang_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_extra_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_extra_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_extra_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_extra_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_center_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_center_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_center_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_center_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_running; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_countAlways; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_deglitch; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_zerocmp; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_sticky; // @[PWM.scala 95:21]
  wire [3:0] pwm_scale_io_regs_cfg_read_scale; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_ip_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_ip_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_ip_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_ip_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_gang_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_gang_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_gang_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_gang_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_extra_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_extra_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_extra_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_extra_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_center_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_center_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_center_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_center_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_running; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_countAlways; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_deglitch; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_zerocmp; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_sticky; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_scale; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_countLo_write_valid; // @[PWM.scala 95:21]
  wire [30:0] pwm_scale_io_regs_countLo_write_bits; // @[PWM.scala 95:21]
  wire [30:0] pwm_scale_io_regs_countLo_read; // @[PWM.scala 95:21]
  wire [15:0] pwm_scale_io_regs_s_read; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cmp_0_write_valid; // @[PWM.scala 95:21]
  wire [15:0] pwm_scale_io_regs_cmp_0_write_bits; // @[PWM.scala 95:21]
  wire [15:0] pwm_scale_io_regs_cmp_0_read; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cmp_1_write_valid; // @[PWM.scala 95:21]
  wire [15:0] pwm_scale_io_regs_cmp_1_write_bits; // @[PWM.scala 95:21]
  wire [15:0] pwm_scale_io_regs_cmp_1_read; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cmp_2_write_valid; // @[PWM.scala 95:21]
  wire [15:0] pwm_scale_io_regs_cmp_2_write_bits; // @[PWM.scala 95:21]
  wire [15:0] pwm_scale_io_regs_cmp_2_read; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cmp_3_write_valid; // @[PWM.scala 95:21]
  wire [15:0] pwm_scale_io_regs_cmp_3_write_bits; // @[PWM.scala 95:21]
  wire [15:0] pwm_scale_io_regs_cmp_3_read; // @[PWM.scala 95:21]
  wire  pwm_scale_io_ip_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_ip_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_ip_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_ip_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_gpio_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_gpio_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_gpio_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_gpio_3; // @[PWM.scala 95:21]
  wire [2:0] bundleIn_0_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  in_bits_read = bundleIn_0_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 72:36]
  wire [28:0] bundleIn_0_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [9:0] in_bits_index = bundleIn_0_a_bits_address[11:2]; // @[RegisterRouter.scala 71:18 73:19]
  wire [9:0] out_findex = in_bits_index & 10'h3f0; // @[RegisterRouter.scala 83:24]
  wire  _out_T = out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [3:0] bundleIn_0_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [7:0] _out_frontMask_T_5 = bundleIn_0_a_bits_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_frontMask_T_7 = bundleIn_0_a_bits_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_frontMask_T_9 = bundleIn_0_a_bits_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_frontMask_T_11 = bundleIn_0_a_bits_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [31:0] out_frontMask = {_out_frontMask_T_11,_out_frontMask_T_9,_out_frontMask_T_7,_out_frontMask_T_5}; // @[Cat.scala 31:58]
  wire  out_wimask = &out_frontMask[3:0]; // @[RegisterRouter.scala 83:24]
  wire  bundleIn_0_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  bundleIn_0_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [3:0] out_oindex = {in_bits_index[3],in_bits_index[2],in_bits_index[1],in_bits_index[0]}; // @[Cat.scala 31:58]
  wire [15:0] _out_frontSel_T = 16'h1 << out_oindex; // @[OneHot.scala 57:35]
  wire  out_frontSel_0 = _out_frontSel_T[0]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_0 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_0 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [31:0] bundleIn_0_a_bits_data = buffer_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [3:0] _out_T_29 = pwm_scale_io_regs_cfg_read_scale; // @[RegisterRouter.scala 83:24]
  wire [4:0] out_prepend = {1'h0,_out_T_29}; // @[Cat.scala 31:58]
  wire [7:0] _out_T_38 = {{3'd0}, out_prepend}; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_2 = &out_frontMask[8]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_3 = &out_frontMask[9]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_4 = &out_frontMask[10]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_6 = &out_frontMask[12]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_7 = &out_frontMask[13]; // @[RegisterRouter.scala 83:24]
  wire [14:0] out_prepend_7 = {1'h0,pwm_scale_io_regs_cfg_read_running,pwm_scale_io_regs_cfg_read_countAlways,1'h0,
    pwm_scale_io_regs_cfg_read_deglitch,pwm_scale_io_regs_cfg_read_zerocmp,pwm_scale_io_regs_cfg_read_sticky,_out_T_38}; // @[Cat.scala 31:58]
  wire [15:0] _out_T_111 = {{1'd0}, out_prepend_7}; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_9 = &out_frontMask[16]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_10 = &out_frontMask[17]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_11 = &out_frontMask[18]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_12 = &out_frontMask[19]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_13 = &out_frontMask[20]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_14 = &out_frontMask[21]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_15 = &out_frontMask[22]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_16 = &out_frontMask[23]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_17 = &out_frontMask[24]; // @[RegisterRouter.scala 83:24]
  wire [24:0] out_prepend_16 = {pwm_scale_io_regs_cfg_read_gang_0,pwm_scale_io_regs_cfg_read_extra_3,
    pwm_scale_io_regs_cfg_read_extra_2,pwm_scale_io_regs_cfg_read_extra_1,pwm_scale_io_regs_cfg_read_extra_0,
    pwm_scale_io_regs_cfg_read_center_3,pwm_scale_io_regs_cfg_read_center_2,pwm_scale_io_regs_cfg_read_center_1,
    pwm_scale_io_regs_cfg_read_center_0,_out_T_111}; // @[Cat.scala 31:58]
  wire  out_wimask_18 = &out_frontMask[25]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_19 = &out_frontMask[26]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_20 = &out_frontMask[27]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_21 = &out_frontMask[28]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_22 = &out_frontMask[29]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_23 = &out_frontMask[30]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_24 = &out_frontMask[31]; // @[RegisterRouter.scala 83:24]
  wire [31:0] out_prepend_23 = {pwm_scale_io_regs_cfg_read_ip_3,pwm_scale_io_regs_cfg_read_ip_2,
    pwm_scale_io_regs_cfg_read_ip_1,pwm_scale_io_regs_cfg_read_ip_0,pwm_scale_io_regs_cfg_read_gang_3,
    pwm_scale_io_regs_cfg_read_gang_2,pwm_scale_io_regs_cfg_read_gang_1,out_prepend_16}; // @[Cat.scala 31:58]
  wire  out_wimask_25 = &out_frontMask[15:0]; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_10 = _out_frontSel_T[10]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_25 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_10 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_T_298 = pwm_scale_io_regs_cmp_2_read; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_9 = _out_frontSel_T[9]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_27 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_9 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_T_318 = pwm_scale_io_regs_cmp_1_read; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_28 = &out_frontMask[30:0]; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_2 = _out_frontSel_T[2]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_28 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_2 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [30:0] _out_T_329 = pwm_scale_io_regs_countLo_read; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_11 = _out_frontSel_T[11]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_31 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_11 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_T_358 = pwm_scale_io_regs_cmp_3_read; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_8 = _out_frontSel_T[8]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_32 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_8 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_T_369 = pwm_scale_io_regs_cmp_0_read; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_T_378 = pwm_scale_io_regs_s_read; // @[RegisterRouter.scala 83:24]
  wire  _GEN_66 = 4'h2 == out_oindex ? _out_T : 4'h1 == out_oindex | _out_T; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_67 = 4'h3 == out_oindex ? _out_T : _GEN_66; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_68 = 4'h4 == out_oindex ? _out_T : _GEN_67; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_70 = 4'h6 == out_oindex ? _out_T : 4'h5 == out_oindex | _GEN_68; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_71 = 4'h7 == out_oindex ? _out_T : _GEN_70; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_72 = 4'h8 == out_oindex ? _out_T : _GEN_71; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_73 = 4'h9 == out_oindex ? _out_T : _GEN_72; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_74 = 4'ha == out_oindex ? _out_T : _GEN_73; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_75 = 4'hb == out_oindex ? _out_T : _GEN_74; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_79 = 4'hf == out_oindex | (4'he == out_oindex | (4'hd == out_oindex | (4'hc == out_oindex | _GEN_75))); // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_81 = 4'h1 == out_oindex ? 32'h0 : out_prepend_23; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_2 = {{1'd0}, _out_T_329}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_82 = 4'h2 == out_oindex ? _out_out_bits_data_WIRE_1_2 : _GEN_81; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_83 = 4'h3 == out_oindex ? 32'h0 : _GEN_82; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_4 = {{16'd0}, _out_T_378}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_84 = 4'h4 == out_oindex ? _out_out_bits_data_WIRE_1_4 : _GEN_83; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_85 = 4'h5 == out_oindex ? 32'h0 : _GEN_84; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_86 = 4'h6 == out_oindex ? 32'h0 : _GEN_85; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_87 = 4'h7 == out_oindex ? 32'h1 : _GEN_86; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_8 = {{16'd0}, _out_T_369}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_88 = 4'h8 == out_oindex ? _out_out_bits_data_WIRE_1_8 : _GEN_87; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_9 = {{16'd0}, _out_T_318}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_89 = 4'h9 == out_oindex ? _out_out_bits_data_WIRE_1_9 : _GEN_88; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_10 = {{16'd0}, _out_T_298}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_90 = 4'ha == out_oindex ? _out_out_bits_data_WIRE_1_10 : _GEN_89; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_11 = {{16'd0}, _out_T_358}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_91 = 4'hb == out_oindex ? _out_out_bits_data_WIRE_1_11 : _GEN_90; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_92 = 4'hc == out_oindex ? 32'h0 : _GEN_91; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_93 = 4'hd == out_oindex ? 32'h0 : _GEN_92; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_94 = 4'he == out_oindex ? 32'h0 : _GEN_93; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_95 = 4'hf == out_oindex ? 32'h0 : _GEN_94; // @[MuxLiteral.scala 48:{10,10}]
  TLBuffer_13 buffer ( // @[Buffer.scala 68:28]
    .auto_in_a_ready(buffer_auto_in_a_ready),
    .auto_in_a_valid(buffer_auto_in_a_valid),
    .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
    .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
    .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
    .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
    .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
    .auto_in_a_bits_data(buffer_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
    .auto_in_d_ready(buffer_auto_in_d_ready),
    .auto_in_d_valid(buffer_auto_in_d_valid),
    .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
    .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
    .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
    .auto_out_a_ready(buffer_auto_out_a_ready),
    .auto_out_a_valid(buffer_auto_out_a_valid),
    .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
    .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
    .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
    .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
    .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
    .auto_out_a_bits_data(buffer_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
    .auto_out_d_ready(buffer_auto_out_d_ready),
    .auto_out_d_valid(buffer_auto_out_d_valid),
    .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
    .auto_out_d_bits_source(buffer_auto_out_d_bits_source),
    .auto_out_d_bits_data(buffer_auto_out_d_bits_data)
  );
  IntSyncCrossingSource_18 intsource ( // @[Crossing.scala 26:31]
    .clock(intsource_clock),
    .reset(intsource_reset),
    .auto_in_0(intsource_auto_in_0),
    .auto_in_1(intsource_auto_in_1),
    .auto_in_2(intsource_auto_in_2),
    .auto_in_3(intsource_auto_in_3),
    .auto_out_sync_0(intsource_auto_out_sync_0),
    .auto_out_sync_1(intsource_auto_out_sync_1),
    .auto_out_sync_2(intsource_auto_out_sync_2),
    .auto_out_sync_3(intsource_auto_out_sync_3)
  );
  TLMonitor_68 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  PWMTimer pwm ( // @[PWM.scala 95:21]
    .clock(pwm_clock),
    .reset(pwm_reset),
    .scale_io_regs_cfg_write__ip_0(pwm_scale_io_regs_cfg_write__ip_0),
    .scale_io_regs_cfg_write__ip_1(pwm_scale_io_regs_cfg_write__ip_1),
    .scale_io_regs_cfg_write__ip_2(pwm_scale_io_regs_cfg_write__ip_2),
    .scale_io_regs_cfg_write__ip_3(pwm_scale_io_regs_cfg_write__ip_3),
    .scale_io_regs_cfg_write__gang_0(pwm_scale_io_regs_cfg_write__gang_0),
    .scale_io_regs_cfg_write__gang_1(pwm_scale_io_regs_cfg_write__gang_1),
    .scale_io_regs_cfg_write__gang_2(pwm_scale_io_regs_cfg_write__gang_2),
    .scale_io_regs_cfg_write__gang_3(pwm_scale_io_regs_cfg_write__gang_3),
    .scale_io_regs_cfg_write__extra_0(pwm_scale_io_regs_cfg_write__extra_0),
    .scale_io_regs_cfg_write__extra_1(pwm_scale_io_regs_cfg_write__extra_1),
    .scale_io_regs_cfg_write__extra_2(pwm_scale_io_regs_cfg_write__extra_2),
    .scale_io_regs_cfg_write__extra_3(pwm_scale_io_regs_cfg_write__extra_3),
    .scale_io_regs_cfg_write__center_0(pwm_scale_io_regs_cfg_write__center_0),
    .scale_io_regs_cfg_write__center_1(pwm_scale_io_regs_cfg_write__center_1),
    .scale_io_regs_cfg_write__center_2(pwm_scale_io_regs_cfg_write__center_2),
    .scale_io_regs_cfg_write__center_3(pwm_scale_io_regs_cfg_write__center_3),
    .scale_io_regs_cfg_write__running(pwm_scale_io_regs_cfg_write__running),
    .scale_io_regs_cfg_write__countAlways(pwm_scale_io_regs_cfg_write__countAlways),
    .scale_io_regs_cfg_write__deglitch(pwm_scale_io_regs_cfg_write__deglitch),
    .scale_io_regs_cfg_write__zerocmp(pwm_scale_io_regs_cfg_write__zerocmp),
    .scale_io_regs_cfg_write__sticky(pwm_scale_io_regs_cfg_write__sticky),
    .scale_io_regs_cfg_write__scale(pwm_scale_io_regs_cfg_write__scale),
    .scale_io_regs_cfg_read_ip_0(pwm_scale_io_regs_cfg_read_ip_0),
    .scale_io_regs_cfg_read_ip_1(pwm_scale_io_regs_cfg_read_ip_1),
    .scale_io_regs_cfg_read_ip_2(pwm_scale_io_regs_cfg_read_ip_2),
    .scale_io_regs_cfg_read_ip_3(pwm_scale_io_regs_cfg_read_ip_3),
    .scale_io_regs_cfg_read_gang_0(pwm_scale_io_regs_cfg_read_gang_0),
    .scale_io_regs_cfg_read_gang_1(pwm_scale_io_regs_cfg_read_gang_1),
    .scale_io_regs_cfg_read_gang_2(pwm_scale_io_regs_cfg_read_gang_2),
    .scale_io_regs_cfg_read_gang_3(pwm_scale_io_regs_cfg_read_gang_3),
    .scale_io_regs_cfg_read_extra_0(pwm_scale_io_regs_cfg_read_extra_0),
    .scale_io_regs_cfg_read_extra_1(pwm_scale_io_regs_cfg_read_extra_1),
    .scale_io_regs_cfg_read_extra_2(pwm_scale_io_regs_cfg_read_extra_2),
    .scale_io_regs_cfg_read_extra_3(pwm_scale_io_regs_cfg_read_extra_3),
    .scale_io_regs_cfg_read_center_0(pwm_scale_io_regs_cfg_read_center_0),
    .scale_io_regs_cfg_read_center_1(pwm_scale_io_regs_cfg_read_center_1),
    .scale_io_regs_cfg_read_center_2(pwm_scale_io_regs_cfg_read_center_2),
    .scale_io_regs_cfg_read_center_3(pwm_scale_io_regs_cfg_read_center_3),
    .scale_io_regs_cfg_read_running(pwm_scale_io_regs_cfg_read_running),
    .scale_io_regs_cfg_read_countAlways(pwm_scale_io_regs_cfg_read_countAlways),
    .scale_io_regs_cfg_read_deglitch(pwm_scale_io_regs_cfg_read_deglitch),
    .scale_io_regs_cfg_read_zerocmp(pwm_scale_io_regs_cfg_read_zerocmp),
    .scale_io_regs_cfg_read_sticky(pwm_scale_io_regs_cfg_read_sticky),
    .scale_io_regs_cfg_read_scale(pwm_scale_io_regs_cfg_read_scale),
    .scale_io_regs_cfg_write_ip_0(pwm_scale_io_regs_cfg_write_ip_0),
    .scale_io_regs_cfg_write_ip_1(pwm_scale_io_regs_cfg_write_ip_1),
    .scale_io_regs_cfg_write_ip_2(pwm_scale_io_regs_cfg_write_ip_2),
    .scale_io_regs_cfg_write_ip_3(pwm_scale_io_regs_cfg_write_ip_3),
    .scale_io_regs_cfg_write_gang_0(pwm_scale_io_regs_cfg_write_gang_0),
    .scale_io_regs_cfg_write_gang_1(pwm_scale_io_regs_cfg_write_gang_1),
    .scale_io_regs_cfg_write_gang_2(pwm_scale_io_regs_cfg_write_gang_2),
    .scale_io_regs_cfg_write_gang_3(pwm_scale_io_regs_cfg_write_gang_3),
    .scale_io_regs_cfg_write_extra_0(pwm_scale_io_regs_cfg_write_extra_0),
    .scale_io_regs_cfg_write_extra_1(pwm_scale_io_regs_cfg_write_extra_1),
    .scale_io_regs_cfg_write_extra_2(pwm_scale_io_regs_cfg_write_extra_2),
    .scale_io_regs_cfg_write_extra_3(pwm_scale_io_regs_cfg_write_extra_3),
    .scale_io_regs_cfg_write_center_0(pwm_scale_io_regs_cfg_write_center_0),
    .scale_io_regs_cfg_write_center_1(pwm_scale_io_regs_cfg_write_center_1),
    .scale_io_regs_cfg_write_center_2(pwm_scale_io_regs_cfg_write_center_2),
    .scale_io_regs_cfg_write_center_3(pwm_scale_io_regs_cfg_write_center_3),
    .scale_io_regs_cfg_write_running(pwm_scale_io_regs_cfg_write_running),
    .scale_io_regs_cfg_write_countAlways(pwm_scale_io_regs_cfg_write_countAlways),
    .scale_io_regs_cfg_write_deglitch(pwm_scale_io_regs_cfg_write_deglitch),
    .scale_io_regs_cfg_write_zerocmp(pwm_scale_io_regs_cfg_write_zerocmp),
    .scale_io_regs_cfg_write_sticky(pwm_scale_io_regs_cfg_write_sticky),
    .scale_io_regs_cfg_write_scale(pwm_scale_io_regs_cfg_write_scale),
    .scale_io_regs_countLo_write_valid(pwm_scale_io_regs_countLo_write_valid),
    .scale_io_regs_countLo_write_bits(pwm_scale_io_regs_countLo_write_bits),
    .scale_io_regs_countLo_read(pwm_scale_io_regs_countLo_read),
    .scale_io_regs_s_read(pwm_scale_io_regs_s_read),
    .scale_io_regs_cmp_0_write_valid(pwm_scale_io_regs_cmp_0_write_valid),
    .scale_io_regs_cmp_0_write_bits(pwm_scale_io_regs_cmp_0_write_bits),
    .scale_io_regs_cmp_0_read(pwm_scale_io_regs_cmp_0_read),
    .scale_io_regs_cmp_1_write_valid(pwm_scale_io_regs_cmp_1_write_valid),
    .scale_io_regs_cmp_1_write_bits(pwm_scale_io_regs_cmp_1_write_bits),
    .scale_io_regs_cmp_1_read(pwm_scale_io_regs_cmp_1_read),
    .scale_io_regs_cmp_2_write_valid(pwm_scale_io_regs_cmp_2_write_valid),
    .scale_io_regs_cmp_2_write_bits(pwm_scale_io_regs_cmp_2_write_bits),
    .scale_io_regs_cmp_2_read(pwm_scale_io_regs_cmp_2_read),
    .scale_io_regs_cmp_3_write_valid(pwm_scale_io_regs_cmp_3_write_valid),
    .scale_io_regs_cmp_3_write_bits(pwm_scale_io_regs_cmp_3_write_bits),
    .scale_io_regs_cmp_3_read(pwm_scale_io_regs_cmp_3_read),
    .scale_io_ip_0(pwm_scale_io_ip_0),
    .scale_io_ip_1(pwm_scale_io_ip_1),
    .scale_io_ip_2(pwm_scale_io_ip_2),
    .scale_io_ip_3(pwm_scale_io_ip_3),
    .scale_io_gpio_0(pwm_scale_io_gpio_0),
    .scale_io_gpio_1(pwm_scale_io_gpio_1),
    .scale_io_gpio_2(pwm_scale_io_gpio_2),
    .scale_io_gpio_3(pwm_scale_io_gpio_3)
  );
  assign auto_int_xing_out_sync_0 = intsource_auto_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_1 = intsource_auto_out_sync_1; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_2 = intsource_auto_out_sync_2; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_3 = intsource_auto_out_sync_3; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_in_a_ready = buffer_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_valid = buffer_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_size = buffer_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_source = buffer_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_data = buffer_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_io_out_gpio_0 = pwm_scale_io_gpio_0; // @[Nodes.scala 1207:84 PWM.scala 97:15]
  assign auto_io_out_gpio_1 = pwm_scale_io_gpio_1; // @[Nodes.scala 1207:84 PWM.scala 97:15]
  assign auto_io_out_gpio_2 = pwm_scale_io_gpio_2; // @[Nodes.scala 1207:84 PWM.scala 97:15]
  assign auto_io_out_gpio_3 = pwm_scale_io_gpio_3; // @[Nodes.scala 1207:84 PWM.scala 97:15]
  assign buffer_auto_in_a_valid = auto_control_xing_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_opcode = auto_control_xing_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_param = auto_control_xing_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_size = auto_control_xing_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_source = auto_control_xing_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_address = auto_control_xing_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_mask = auto_control_xing_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_data = auto_control_xing_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_corrupt = auto_control_xing_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_d_ready = auto_control_xing_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_out_a_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign buffer_auto_out_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_data = _GEN_79 ? _GEN_95 : 32'h0; // @[RegisterRouter.scala 83:24]
  assign intsource_clock = clock;
  assign intsource_reset = reset;
  assign intsource_auto_in_0 = pwm_scale_io_ip_0; // @[Nodes.scala 1207:84 PWM.scala 96:16]
  assign intsource_auto_in_1 = pwm_scale_io_ip_1; // @[Nodes.scala 1207:84 PWM.scala 96:16]
  assign intsource_auto_in_2 = pwm_scale_io_ip_2; // @[Nodes.scala 1207:84 PWM.scala 96:16]
  assign intsource_auto_in_3 = pwm_scale_io_ip_3; // @[Nodes.scala 1207:84 PWM.scala 96:16]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_param = buffer_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign monitor_io_in_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign pwm_clock = clock;
  assign pwm_reset = reset;
  assign pwm_scale_io_regs_cfg_write__ip_0 = bundleIn_0_a_bits_data[28]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__ip_1 = bundleIn_0_a_bits_data[29]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__ip_2 = bundleIn_0_a_bits_data[30]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__ip_3 = bundleIn_0_a_bits_data[31]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__gang_0 = bundleIn_0_a_bits_data[24]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__gang_1 = bundleIn_0_a_bits_data[25]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__gang_2 = bundleIn_0_a_bits_data[26]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__gang_3 = bundleIn_0_a_bits_data[27]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__extra_0 = bundleIn_0_a_bits_data[20]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__extra_1 = bundleIn_0_a_bits_data[21]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__extra_2 = bundleIn_0_a_bits_data[22]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__extra_3 = bundleIn_0_a_bits_data[23]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__center_0 = bundleIn_0_a_bits_data[16]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__center_1 = bundleIn_0_a_bits_data[17]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__center_2 = bundleIn_0_a_bits_data[18]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__center_3 = bundleIn_0_a_bits_data[19]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__running = bundleIn_0_a_bits_data[13]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__countAlways = bundleIn_0_a_bits_data[12]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__deglitch = bundleIn_0_a_bits_data[10]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__zerocmp = bundleIn_0_a_bits_data[9]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__sticky = bundleIn_0_a_bits_data[8]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__scale = bundleIn_0_a_bits_data[3:0]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_ip_0 = out_wivalid_0 & out_wimask_21; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_ip_1 = out_wivalid_0 & out_wimask_22; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_ip_2 = out_wivalid_0 & out_wimask_23; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_ip_3 = out_wivalid_0 & out_wimask_24; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_gang_0 = out_wivalid_0 & out_wimask_17; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_gang_1 = out_wivalid_0 & out_wimask_18; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_gang_2 = out_wivalid_0 & out_wimask_19; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_gang_3 = out_wivalid_0 & out_wimask_20; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_extra_0 = out_wivalid_0 & out_wimask_13; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_extra_1 = out_wivalid_0 & out_wimask_14; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_extra_2 = out_wivalid_0 & out_wimask_15; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_extra_3 = out_wivalid_0 & out_wimask_16; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_center_0 = out_wivalid_0 & out_wimask_9; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_center_1 = out_wivalid_0 & out_wimask_10; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_center_2 = out_wivalid_0 & out_wimask_11; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_center_3 = out_wivalid_0 & out_wimask_12; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_running = out_wivalid_0 & out_wimask_7; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_countAlways = out_wivalid_0 & out_wimask_6; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_deglitch = out_wivalid_0 & out_wimask_4; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_zerocmp = out_wivalid_0 & out_wimask_3; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_sticky = out_wivalid_0 & out_wimask_2; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_scale = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_countLo_write_valid = out_wivalid_28 & out_wimask_28; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_countLo_write_bits = bundleIn_0_a_bits_data[30:0]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cmp_0_write_valid = out_wivalid_32 & out_wimask_25; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cmp_0_write_bits = bundleIn_0_a_bits_data[15:0]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cmp_1_write_valid = out_wivalid_27 & out_wimask_25; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cmp_1_write_bits = bundleIn_0_a_bits_data[15:0]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cmp_2_write_valid = out_wivalid_25 & out_wimask_25; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cmp_2_write_bits = bundleIn_0_a_bits_data[15:0]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cmp_3_write_valid = out_wivalid_31 & out_wimask_25; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cmp_3_write_bits = bundleIn_0_a_bits_data[15:0]; // @[RegisterRouter.scala 83:24]
endmodule
module ClockSinkDomain_11(
  output        auto_pwm_1_int_xing_out_sync_0,
  output        auto_pwm_1_int_xing_out_sync_1,
  output        auto_pwm_1_int_xing_out_sync_2,
  output        auto_pwm_1_int_xing_out_sync_3,
  output        auto_pwm_1_control_xing_in_a_ready,
  input         auto_pwm_1_control_xing_in_a_valid,
  input  [2:0]  auto_pwm_1_control_xing_in_a_bits_opcode,
  input  [2:0]  auto_pwm_1_control_xing_in_a_bits_param,
  input  [1:0]  auto_pwm_1_control_xing_in_a_bits_size,
  input  [6:0]  auto_pwm_1_control_xing_in_a_bits_source,
  input  [28:0] auto_pwm_1_control_xing_in_a_bits_address,
  input  [3:0]  auto_pwm_1_control_xing_in_a_bits_mask,
  input  [31:0] auto_pwm_1_control_xing_in_a_bits_data,
  input         auto_pwm_1_control_xing_in_a_bits_corrupt,
  input         auto_pwm_1_control_xing_in_d_ready,
  output        auto_pwm_1_control_xing_in_d_valid,
  output [2:0]  auto_pwm_1_control_xing_in_d_bits_opcode,
  output [1:0]  auto_pwm_1_control_xing_in_d_bits_size,
  output [6:0]  auto_pwm_1_control_xing_in_d_bits_source,
  output [31:0] auto_pwm_1_control_xing_in_d_bits_data,
  output        auto_pwm_1_io_out_gpio_0,
  output        auto_pwm_1_io_out_gpio_1,
  output        auto_pwm_1_io_out_gpio_2,
  output        auto_pwm_1_io_out_gpio_3,
  input         auto_clock_in_clock,
  input         auto_clock_in_reset
);
  wire  pwm_1_clock; // @[PWM.scala 135:49]
  wire  pwm_1_reset; // @[PWM.scala 135:49]
  wire  pwm_1_auto_int_xing_out_sync_0; // @[PWM.scala 135:49]
  wire  pwm_1_auto_int_xing_out_sync_1; // @[PWM.scala 135:49]
  wire  pwm_1_auto_int_xing_out_sync_2; // @[PWM.scala 135:49]
  wire  pwm_1_auto_int_xing_out_sync_3; // @[PWM.scala 135:49]
  wire  pwm_1_auto_control_xing_in_a_ready; // @[PWM.scala 135:49]
  wire  pwm_1_auto_control_xing_in_a_valid; // @[PWM.scala 135:49]
  wire [2:0] pwm_1_auto_control_xing_in_a_bits_opcode; // @[PWM.scala 135:49]
  wire [2:0] pwm_1_auto_control_xing_in_a_bits_param; // @[PWM.scala 135:49]
  wire [1:0] pwm_1_auto_control_xing_in_a_bits_size; // @[PWM.scala 135:49]
  wire [6:0] pwm_1_auto_control_xing_in_a_bits_source; // @[PWM.scala 135:49]
  wire [28:0] pwm_1_auto_control_xing_in_a_bits_address; // @[PWM.scala 135:49]
  wire [3:0] pwm_1_auto_control_xing_in_a_bits_mask; // @[PWM.scala 135:49]
  wire [31:0] pwm_1_auto_control_xing_in_a_bits_data; // @[PWM.scala 135:49]
  wire  pwm_1_auto_control_xing_in_a_bits_corrupt; // @[PWM.scala 135:49]
  wire  pwm_1_auto_control_xing_in_d_ready; // @[PWM.scala 135:49]
  wire  pwm_1_auto_control_xing_in_d_valid; // @[PWM.scala 135:49]
  wire [2:0] pwm_1_auto_control_xing_in_d_bits_opcode; // @[PWM.scala 135:49]
  wire [1:0] pwm_1_auto_control_xing_in_d_bits_size; // @[PWM.scala 135:49]
  wire [6:0] pwm_1_auto_control_xing_in_d_bits_source; // @[PWM.scala 135:49]
  wire [31:0] pwm_1_auto_control_xing_in_d_bits_data; // @[PWM.scala 135:49]
  wire  pwm_1_auto_io_out_gpio_0; // @[PWM.scala 135:49]
  wire  pwm_1_auto_io_out_gpio_1; // @[PWM.scala 135:49]
  wire  pwm_1_auto_io_out_gpio_2; // @[PWM.scala 135:49]
  wire  pwm_1_auto_io_out_gpio_3; // @[PWM.scala 135:49]
  TLPWM_1 pwm_1 ( // @[PWM.scala 135:49]
    .clock(pwm_1_clock),
    .reset(pwm_1_reset),
    .auto_int_xing_out_sync_0(pwm_1_auto_int_xing_out_sync_0),
    .auto_int_xing_out_sync_1(pwm_1_auto_int_xing_out_sync_1),
    .auto_int_xing_out_sync_2(pwm_1_auto_int_xing_out_sync_2),
    .auto_int_xing_out_sync_3(pwm_1_auto_int_xing_out_sync_3),
    .auto_control_xing_in_a_ready(pwm_1_auto_control_xing_in_a_ready),
    .auto_control_xing_in_a_valid(pwm_1_auto_control_xing_in_a_valid),
    .auto_control_xing_in_a_bits_opcode(pwm_1_auto_control_xing_in_a_bits_opcode),
    .auto_control_xing_in_a_bits_param(pwm_1_auto_control_xing_in_a_bits_param),
    .auto_control_xing_in_a_bits_size(pwm_1_auto_control_xing_in_a_bits_size),
    .auto_control_xing_in_a_bits_source(pwm_1_auto_control_xing_in_a_bits_source),
    .auto_control_xing_in_a_bits_address(pwm_1_auto_control_xing_in_a_bits_address),
    .auto_control_xing_in_a_bits_mask(pwm_1_auto_control_xing_in_a_bits_mask),
    .auto_control_xing_in_a_bits_data(pwm_1_auto_control_xing_in_a_bits_data),
    .auto_control_xing_in_a_bits_corrupt(pwm_1_auto_control_xing_in_a_bits_corrupt),
    .auto_control_xing_in_d_ready(pwm_1_auto_control_xing_in_d_ready),
    .auto_control_xing_in_d_valid(pwm_1_auto_control_xing_in_d_valid),
    .auto_control_xing_in_d_bits_opcode(pwm_1_auto_control_xing_in_d_bits_opcode),
    .auto_control_xing_in_d_bits_size(pwm_1_auto_control_xing_in_d_bits_size),
    .auto_control_xing_in_d_bits_source(pwm_1_auto_control_xing_in_d_bits_source),
    .auto_control_xing_in_d_bits_data(pwm_1_auto_control_xing_in_d_bits_data),
    .auto_io_out_gpio_0(pwm_1_auto_io_out_gpio_0),
    .auto_io_out_gpio_1(pwm_1_auto_io_out_gpio_1),
    .auto_io_out_gpio_2(pwm_1_auto_io_out_gpio_2),
    .auto_io_out_gpio_3(pwm_1_auto_io_out_gpio_3)
  );
  assign auto_pwm_1_int_xing_out_sync_0 = pwm_1_auto_int_xing_out_sync_0; // @[LazyModule.scala 311:12]
  assign auto_pwm_1_int_xing_out_sync_1 = pwm_1_auto_int_xing_out_sync_1; // @[LazyModule.scala 311:12]
  assign auto_pwm_1_int_xing_out_sync_2 = pwm_1_auto_int_xing_out_sync_2; // @[LazyModule.scala 311:12]
  assign auto_pwm_1_int_xing_out_sync_3 = pwm_1_auto_int_xing_out_sync_3; // @[LazyModule.scala 311:12]
  assign auto_pwm_1_control_xing_in_a_ready = pwm_1_auto_control_xing_in_a_ready; // @[LazyModule.scala 309:16]
  assign auto_pwm_1_control_xing_in_d_valid = pwm_1_auto_control_xing_in_d_valid; // @[LazyModule.scala 309:16]
  assign auto_pwm_1_control_xing_in_d_bits_opcode = pwm_1_auto_control_xing_in_d_bits_opcode; // @[LazyModule.scala 309:16]
  assign auto_pwm_1_control_xing_in_d_bits_size = pwm_1_auto_control_xing_in_d_bits_size; // @[LazyModule.scala 309:16]
  assign auto_pwm_1_control_xing_in_d_bits_source = pwm_1_auto_control_xing_in_d_bits_source; // @[LazyModule.scala 309:16]
  assign auto_pwm_1_control_xing_in_d_bits_data = pwm_1_auto_control_xing_in_d_bits_data; // @[LazyModule.scala 309:16]
  assign auto_pwm_1_io_out_gpio_0 = pwm_1_auto_io_out_gpio_0; // @[LazyModule.scala 311:12]
  assign auto_pwm_1_io_out_gpio_1 = pwm_1_auto_io_out_gpio_1; // @[LazyModule.scala 311:12]
  assign auto_pwm_1_io_out_gpio_2 = pwm_1_auto_io_out_gpio_2; // @[LazyModule.scala 311:12]
  assign auto_pwm_1_io_out_gpio_3 = pwm_1_auto_io_out_gpio_3; // @[LazyModule.scala 311:12]
  assign pwm_1_clock = auto_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign pwm_1_reset = auto_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign pwm_1_auto_control_xing_in_a_valid = auto_pwm_1_control_xing_in_a_valid; // @[LazyModule.scala 309:16]
  assign pwm_1_auto_control_xing_in_a_bits_opcode = auto_pwm_1_control_xing_in_a_bits_opcode; // @[LazyModule.scala 309:16]
  assign pwm_1_auto_control_xing_in_a_bits_param = auto_pwm_1_control_xing_in_a_bits_param; // @[LazyModule.scala 309:16]
  assign pwm_1_auto_control_xing_in_a_bits_size = auto_pwm_1_control_xing_in_a_bits_size; // @[LazyModule.scala 309:16]
  assign pwm_1_auto_control_xing_in_a_bits_source = auto_pwm_1_control_xing_in_a_bits_source; // @[LazyModule.scala 309:16]
  assign pwm_1_auto_control_xing_in_a_bits_address = auto_pwm_1_control_xing_in_a_bits_address; // @[LazyModule.scala 309:16]
  assign pwm_1_auto_control_xing_in_a_bits_mask = auto_pwm_1_control_xing_in_a_bits_mask; // @[LazyModule.scala 309:16]
  assign pwm_1_auto_control_xing_in_a_bits_data = auto_pwm_1_control_xing_in_a_bits_data; // @[LazyModule.scala 309:16]
  assign pwm_1_auto_control_xing_in_a_bits_corrupt = auto_pwm_1_control_xing_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
  assign pwm_1_auto_control_xing_in_d_ready = auto_pwm_1_control_xing_in_d_ready; // @[LazyModule.scala 309:16]
endmodule
module TLMonitor_69(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [1:0]  io_in_a_bits_size,
  input  [6:0]  io_in_a_bits_source,
  input  [28:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_size,
  input  [6:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [95:0] _RAND_10;
  reg [383:0] _RAND_11;
  reg [383:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [95:0] _RAND_16;
  reg [383:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T_4 = io_in_a_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire [4:0] _is_aligned_mask_T_1 = 5'h3 << io_in_a_bits_size; // @[package.scala 234:77]
  wire [1:0] is_aligned_mask = ~_is_aligned_mask_T_1[1:0]; // @[package.scala 234:46]
  wire [28:0] _GEN_71 = {{27'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 2'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [28:0] _T_33 = io_in_a_bits_address ^ 29'h10035000; // @[Parameters.scala 137:31]
  wire [29:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
  wire [29:0] _T_36 = $signed(_T_34) & -30'sh1000; // @[Parameters.scala 137:52]
  wire  _T_37 = $signed(_T_36) == 30'sh0; // @[Parameters.scala 137:67]
  wire  _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_74 = _T_73 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_164 = io_in_a_bits_size <= 2'h2; // @[Parameters.scala 92:42]
  wire  _T_172 = _T_164 & _T_37; // @[Parameters.scala 670:56]
  wire  _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_218 = _source_ok_T_4 & _T_172; // @[Monitor.scala 115:71]
  wire  _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_273 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_274 = io_in_a_bits_mask & _T_273; // @[Monitor.scala 127:31]
  wire  _T_275 = _T_274 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_279 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_347 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_355 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_385 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_397 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_10 = io_in_d_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire  _T_401 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_405 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 312:27]
  wire  _T_421 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_449 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_478 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_495 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_513 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [1:0] size; // @[Monitor.scala 386:22]
  reg [6:0] source; // @[Monitor.scala 387:22]
  reg [28:0] address; // @[Monitor.scala 388:22]
  wire  _T_543 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_544 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_548 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_552 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_556 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_560 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] size_1; // @[Monitor.scala 537:22]
  reg [6:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_567 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_568 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_576 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_580 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [95:0] inflight; // @[Monitor.scala 611:27]
  reg [383:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [383:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [8:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [9:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [383:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [383:0] _GEN_73 = {{368'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[383:1]}; // @[Monitor.scala 634:152]
  wire [383:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [383:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
  wire [383:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[383:1]}; // @[Monitor.scala 638:144]
  wire  _T_594 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [127:0] _a_set_wo_ready_T = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_597 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
  wire [8:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [9:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [1026:0] _GEN_1 = {{1023'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [1026:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
  wire [1025:0] _GEN_2 = {{1023'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [1025:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [95:0] _T_599 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_601 = ~_T_599[0]; // @[Monitor.scala 658:17]
  wire [127:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 652:72 653:28]
  wire [1026:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 1027'h0; // @[Monitor.scala 652:72 656:28]
  wire [1025:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 1026'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_605 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_607 = ~_T_401; // @[Monitor.scala 671:74]
  wire  _T_608 = io_in_d_valid & d_first_1 & ~_T_401; // @[Monitor.scala 671:71]
  wire [127:0] _d_clr_wo_ready_T = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [1038:0] _GEN_3 = {{1023'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [1038:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [127:0] _GEN_22 = d_first_done & d_first_1 & _T_607 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 675:91 676:21]
  wire [1038:0] _GEN_23 = d_first_done & d_first_1 & _T_607 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_594 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [95:0] _T_618 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_620 = _T_618[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_625 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_626 = io_in_d_bits_opcode == _GEN_32 | _T_625; // @[Monitor.scala 685:77]
  wire  _T_630 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_637 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_638 = io_in_d_bits_opcode == _GEN_48 | _T_637; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_642 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_652 = _T_605 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_607; // @[Monitor.scala 694:116]
  wire  _T_654 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [95:0] a_set = _GEN_16[95:0];
  wire [95:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [95:0] d_clr = _GEN_22[95:0];
  wire [95:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [95:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [383:0] a_opcodes_set = _GEN_19[383:0];
  wire [383:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [383:0] d_opcodes_clr = _GEN_23[383:0];
  wire [383:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [383:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [383:0] a_sizes_set = _GEN_20[383:0];
  wire [383:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [383:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_663 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [95:0] inflight_1; // @[Monitor.scala 723:35]
  reg [383:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [383:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [383:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
  wire [383:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[383:1]}; // @[Monitor.scala 747:146]
  wire  _T_689 = io_in_d_valid & d_first_2 & _T_401; // @[Monitor.scala 779:71]
  wire [127:0] _GEN_67 = d_first_done & d_first_2 & _T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 783:90 784:21]
  wire [1038:0] _GEN_68 = d_first_done & d_first_2 & _T_401 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 783:90 785:21]
  wire [95:0] _T_697 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_707 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [95:0] d_clr_1 = _GEN_67[95:0];
  wire [95:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [95:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [383:0] d_opcodes_clr_1 = _GEN_68[383:0];
  wire [383:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [383:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_727 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 1'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= 1'h0;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 96'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 384'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 384'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 1'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= 1'h0;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 96'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 384'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= 1'h0;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (d_first_done) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_172 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_172) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_275 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_275) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_309 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_309) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_347 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_347) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_385 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_397 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_397) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_478 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_478 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_495 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_495 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_513 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_513 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_544 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_544) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_548 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_548) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_552 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_552) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_556 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_556) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_560 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_560) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_568 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_568) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_576 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_576) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_580 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_580) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_601 & (_T_597 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_597 & ~reset & ~_T_601) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_620 & (_T_608 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & _T_2 & ~_T_620) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_626 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_626) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_630 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_630) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_638 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_638) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_642 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_642) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_654 & (_T_652 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_652 & _T_2 & ~_T_654) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_663 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_663) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_697[0] & (_T_689 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_689 & _T_2 & ~_T_697[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_707 & (_T_689 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_689 & _T_2 & ~_T_707) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_727 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_727) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[6:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[28:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[6:0];
  _RAND_10 = {3{`RANDOM}};
  inflight = _RAND_10[95:0];
  _RAND_11 = {12{`RANDOM}};
  inflight_opcodes = _RAND_11[383:0];
  _RAND_12 = {12{`RANDOM}};
  inflight_sizes = _RAND_12[383:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {3{`RANDOM}};
  inflight_1 = _RAND_16[95:0];
  _RAND_17 = {12{`RANDOM}};
  inflight_sizes_1 = _RAND_17[383:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLPWM_2(
  input         clock,
  input         reset,
  output        auto_int_xing_out_sync_0,
  output        auto_int_xing_out_sync_1,
  output        auto_int_xing_out_sync_2,
  output        auto_int_xing_out_sync_3,
  output        auto_control_xing_in_a_ready,
  input         auto_control_xing_in_a_valid,
  input  [2:0]  auto_control_xing_in_a_bits_opcode,
  input  [2:0]  auto_control_xing_in_a_bits_param,
  input  [1:0]  auto_control_xing_in_a_bits_size,
  input  [6:0]  auto_control_xing_in_a_bits_source,
  input  [28:0] auto_control_xing_in_a_bits_address,
  input  [3:0]  auto_control_xing_in_a_bits_mask,
  input  [31:0] auto_control_xing_in_a_bits_data,
  input         auto_control_xing_in_a_bits_corrupt,
  input         auto_control_xing_in_d_ready,
  output        auto_control_xing_in_d_valid,
  output [2:0]  auto_control_xing_in_d_bits_opcode,
  output [1:0]  auto_control_xing_in_d_bits_size,
  output [6:0]  auto_control_xing_in_d_bits_source,
  output [31:0] auto_control_xing_in_d_bits_data,
  output        auto_io_out_gpio_0,
  output        auto_io_out_gpio_1,
  output        auto_io_out_gpio_2,
  output        auto_io_out_gpio_3
);
  wire  buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
  wire [28:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
  wire [28:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
  wire  intsource_clock; // @[Crossing.scala 26:31]
  wire  intsource_reset; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_0; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_1; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_2; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_3; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_0; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_1; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_2; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_3; // @[Crossing.scala 26:31]
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire  pwm_clock; // @[PWM.scala 95:21]
  wire  pwm_reset; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__ip_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__ip_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__ip_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__ip_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__gang_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__gang_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__gang_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__gang_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__extra_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__extra_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__extra_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__extra_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__center_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__center_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__center_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__center_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__running; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__countAlways; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__deglitch; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__zerocmp; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write__sticky; // @[PWM.scala 95:21]
  wire [3:0] pwm_scale_io_regs_cfg_write__scale; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_ip_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_ip_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_ip_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_ip_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_gang_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_gang_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_gang_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_gang_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_extra_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_extra_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_extra_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_extra_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_center_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_center_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_center_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_center_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_running; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_countAlways; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_deglitch; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_zerocmp; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_read_sticky; // @[PWM.scala 95:21]
  wire [3:0] pwm_scale_io_regs_cfg_read_scale; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_ip_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_ip_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_ip_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_ip_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_gang_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_gang_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_gang_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_gang_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_extra_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_extra_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_extra_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_extra_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_center_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_center_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_center_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_center_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_running; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_countAlways; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_deglitch; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_zerocmp; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_sticky; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cfg_write_scale; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_countLo_write_valid; // @[PWM.scala 95:21]
  wire [30:0] pwm_scale_io_regs_countLo_write_bits; // @[PWM.scala 95:21]
  wire [30:0] pwm_scale_io_regs_countLo_read; // @[PWM.scala 95:21]
  wire [15:0] pwm_scale_io_regs_s_read; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cmp_0_write_valid; // @[PWM.scala 95:21]
  wire [15:0] pwm_scale_io_regs_cmp_0_write_bits; // @[PWM.scala 95:21]
  wire [15:0] pwm_scale_io_regs_cmp_0_read; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cmp_1_write_valid; // @[PWM.scala 95:21]
  wire [15:0] pwm_scale_io_regs_cmp_1_write_bits; // @[PWM.scala 95:21]
  wire [15:0] pwm_scale_io_regs_cmp_1_read; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cmp_2_write_valid; // @[PWM.scala 95:21]
  wire [15:0] pwm_scale_io_regs_cmp_2_write_bits; // @[PWM.scala 95:21]
  wire [15:0] pwm_scale_io_regs_cmp_2_read; // @[PWM.scala 95:21]
  wire  pwm_scale_io_regs_cmp_3_write_valid; // @[PWM.scala 95:21]
  wire [15:0] pwm_scale_io_regs_cmp_3_write_bits; // @[PWM.scala 95:21]
  wire [15:0] pwm_scale_io_regs_cmp_3_read; // @[PWM.scala 95:21]
  wire  pwm_scale_io_ip_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_ip_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_ip_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_ip_3; // @[PWM.scala 95:21]
  wire  pwm_scale_io_gpio_0; // @[PWM.scala 95:21]
  wire  pwm_scale_io_gpio_1; // @[PWM.scala 95:21]
  wire  pwm_scale_io_gpio_2; // @[PWM.scala 95:21]
  wire  pwm_scale_io_gpio_3; // @[PWM.scala 95:21]
  wire [2:0] bundleIn_0_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  in_bits_read = bundleIn_0_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 72:36]
  wire [28:0] bundleIn_0_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [9:0] in_bits_index = bundleIn_0_a_bits_address[11:2]; // @[RegisterRouter.scala 71:18 73:19]
  wire [9:0] out_findex = in_bits_index & 10'h3f0; // @[RegisterRouter.scala 83:24]
  wire  _out_T = out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [3:0] bundleIn_0_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [7:0] _out_frontMask_T_5 = bundleIn_0_a_bits_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_frontMask_T_7 = bundleIn_0_a_bits_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_frontMask_T_9 = bundleIn_0_a_bits_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_frontMask_T_11 = bundleIn_0_a_bits_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [31:0] out_frontMask = {_out_frontMask_T_11,_out_frontMask_T_9,_out_frontMask_T_7,_out_frontMask_T_5}; // @[Cat.scala 31:58]
  wire  out_wimask = &out_frontMask[3:0]; // @[RegisterRouter.scala 83:24]
  wire  bundleIn_0_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  bundleIn_0_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [3:0] out_oindex = {in_bits_index[3],in_bits_index[2],in_bits_index[1],in_bits_index[0]}; // @[Cat.scala 31:58]
  wire [15:0] _out_frontSel_T = 16'h1 << out_oindex; // @[OneHot.scala 57:35]
  wire  out_frontSel_0 = _out_frontSel_T[0]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_0 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_0 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [31:0] bundleIn_0_a_bits_data = buffer_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [3:0] _out_T_29 = pwm_scale_io_regs_cfg_read_scale; // @[RegisterRouter.scala 83:24]
  wire [4:0] out_prepend = {1'h0,_out_T_29}; // @[Cat.scala 31:58]
  wire [7:0] _out_T_38 = {{3'd0}, out_prepend}; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_2 = &out_frontMask[8]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_3 = &out_frontMask[9]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_4 = &out_frontMask[10]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_6 = &out_frontMask[12]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_7 = &out_frontMask[13]; // @[RegisterRouter.scala 83:24]
  wire [14:0] out_prepend_7 = {1'h0,pwm_scale_io_regs_cfg_read_running,pwm_scale_io_regs_cfg_read_countAlways,1'h0,
    pwm_scale_io_regs_cfg_read_deglitch,pwm_scale_io_regs_cfg_read_zerocmp,pwm_scale_io_regs_cfg_read_sticky,_out_T_38}; // @[Cat.scala 31:58]
  wire [15:0] _out_T_111 = {{1'd0}, out_prepend_7}; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_9 = &out_frontMask[16]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_10 = &out_frontMask[17]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_11 = &out_frontMask[18]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_12 = &out_frontMask[19]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_13 = &out_frontMask[20]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_14 = &out_frontMask[21]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_15 = &out_frontMask[22]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_16 = &out_frontMask[23]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_17 = &out_frontMask[24]; // @[RegisterRouter.scala 83:24]
  wire [24:0] out_prepend_16 = {pwm_scale_io_regs_cfg_read_gang_0,pwm_scale_io_regs_cfg_read_extra_3,
    pwm_scale_io_regs_cfg_read_extra_2,pwm_scale_io_regs_cfg_read_extra_1,pwm_scale_io_regs_cfg_read_extra_0,
    pwm_scale_io_regs_cfg_read_center_3,pwm_scale_io_regs_cfg_read_center_2,pwm_scale_io_regs_cfg_read_center_1,
    pwm_scale_io_regs_cfg_read_center_0,_out_T_111}; // @[Cat.scala 31:58]
  wire  out_wimask_18 = &out_frontMask[25]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_19 = &out_frontMask[26]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_20 = &out_frontMask[27]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_21 = &out_frontMask[28]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_22 = &out_frontMask[29]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_23 = &out_frontMask[30]; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_24 = &out_frontMask[31]; // @[RegisterRouter.scala 83:24]
  wire [31:0] out_prepend_23 = {pwm_scale_io_regs_cfg_read_ip_3,pwm_scale_io_regs_cfg_read_ip_2,
    pwm_scale_io_regs_cfg_read_ip_1,pwm_scale_io_regs_cfg_read_ip_0,pwm_scale_io_regs_cfg_read_gang_3,
    pwm_scale_io_regs_cfg_read_gang_2,pwm_scale_io_regs_cfg_read_gang_1,out_prepend_16}; // @[Cat.scala 31:58]
  wire  out_wimask_25 = &out_frontMask[15:0]; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_10 = _out_frontSel_T[10]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_25 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_10 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_T_298 = pwm_scale_io_regs_cmp_2_read; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_9 = _out_frontSel_T[9]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_27 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_9 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_T_318 = pwm_scale_io_regs_cmp_1_read; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_28 = &out_frontMask[30:0]; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_2 = _out_frontSel_T[2]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_28 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_2 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [30:0] _out_T_329 = pwm_scale_io_regs_countLo_read; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_11 = _out_frontSel_T[11]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_31 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_11 & out_findex == 10'h0
    ; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_T_358 = pwm_scale_io_regs_cmp_3_read; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_8 = _out_frontSel_T[8]; // @[RegisterRouter.scala 83:24]
  wire  out_wivalid_32 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_8 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_T_369 = pwm_scale_io_regs_cmp_0_read; // @[RegisterRouter.scala 83:24]
  wire [15:0] _out_T_378 = pwm_scale_io_regs_s_read; // @[RegisterRouter.scala 83:24]
  wire  _GEN_66 = 4'h2 == out_oindex ? _out_T : 4'h1 == out_oindex | _out_T; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_67 = 4'h3 == out_oindex ? _out_T : _GEN_66; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_68 = 4'h4 == out_oindex ? _out_T : _GEN_67; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_70 = 4'h6 == out_oindex ? _out_T : 4'h5 == out_oindex | _GEN_68; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_71 = 4'h7 == out_oindex ? _out_T : _GEN_70; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_72 = 4'h8 == out_oindex ? _out_T : _GEN_71; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_73 = 4'h9 == out_oindex ? _out_T : _GEN_72; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_74 = 4'ha == out_oindex ? _out_T : _GEN_73; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_75 = 4'hb == out_oindex ? _out_T : _GEN_74; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_79 = 4'hf == out_oindex | (4'he == out_oindex | (4'hd == out_oindex | (4'hc == out_oindex | _GEN_75))); // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_81 = 4'h1 == out_oindex ? 32'h0 : out_prepend_23; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_2 = {{1'd0}, _out_T_329}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_82 = 4'h2 == out_oindex ? _out_out_bits_data_WIRE_1_2 : _GEN_81; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_83 = 4'h3 == out_oindex ? 32'h0 : _GEN_82; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_4 = {{16'd0}, _out_T_378}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_84 = 4'h4 == out_oindex ? _out_out_bits_data_WIRE_1_4 : _GEN_83; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_85 = 4'h5 == out_oindex ? 32'h0 : _GEN_84; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_86 = 4'h6 == out_oindex ? 32'h0 : _GEN_85; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_87 = 4'h7 == out_oindex ? 32'h1 : _GEN_86; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_8 = {{16'd0}, _out_T_369}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_88 = 4'h8 == out_oindex ? _out_out_bits_data_WIRE_1_8 : _GEN_87; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_9 = {{16'd0}, _out_T_318}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_89 = 4'h9 == out_oindex ? _out_out_bits_data_WIRE_1_9 : _GEN_88; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_10 = {{16'd0}, _out_T_298}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_90 = 4'ha == out_oindex ? _out_out_bits_data_WIRE_1_10 : _GEN_89; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _out_out_bits_data_WIRE_1_11 = {{16'd0}, _out_T_358}; // @[MuxLiteral.scala 48:{48,48}]
  wire [31:0] _GEN_91 = 4'hb == out_oindex ? _out_out_bits_data_WIRE_1_11 : _GEN_90; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_92 = 4'hc == out_oindex ? 32'h0 : _GEN_91; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_93 = 4'hd == out_oindex ? 32'h0 : _GEN_92; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_94 = 4'he == out_oindex ? 32'h0 : _GEN_93; // @[MuxLiteral.scala 48:{10,10}]
  wire [31:0] _GEN_95 = 4'hf == out_oindex ? 32'h0 : _GEN_94; // @[MuxLiteral.scala 48:{10,10}]
  TLBuffer_13 buffer ( // @[Buffer.scala 68:28]
    .auto_in_a_ready(buffer_auto_in_a_ready),
    .auto_in_a_valid(buffer_auto_in_a_valid),
    .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
    .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
    .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
    .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
    .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
    .auto_in_a_bits_data(buffer_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
    .auto_in_d_ready(buffer_auto_in_d_ready),
    .auto_in_d_valid(buffer_auto_in_d_valid),
    .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
    .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
    .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
    .auto_out_a_ready(buffer_auto_out_a_ready),
    .auto_out_a_valid(buffer_auto_out_a_valid),
    .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
    .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
    .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
    .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
    .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
    .auto_out_a_bits_data(buffer_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
    .auto_out_d_ready(buffer_auto_out_d_ready),
    .auto_out_d_valid(buffer_auto_out_d_valid),
    .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
    .auto_out_d_bits_source(buffer_auto_out_d_bits_source),
    .auto_out_d_bits_data(buffer_auto_out_d_bits_data)
  );
  IntSyncCrossingSource_18 intsource ( // @[Crossing.scala 26:31]
    .clock(intsource_clock),
    .reset(intsource_reset),
    .auto_in_0(intsource_auto_in_0),
    .auto_in_1(intsource_auto_in_1),
    .auto_in_2(intsource_auto_in_2),
    .auto_in_3(intsource_auto_in_3),
    .auto_out_sync_0(intsource_auto_out_sync_0),
    .auto_out_sync_1(intsource_auto_out_sync_1),
    .auto_out_sync_2(intsource_auto_out_sync_2),
    .auto_out_sync_3(intsource_auto_out_sync_3)
  );
  TLMonitor_69 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  PWMTimer pwm ( // @[PWM.scala 95:21]
    .clock(pwm_clock),
    .reset(pwm_reset),
    .scale_io_regs_cfg_write__ip_0(pwm_scale_io_regs_cfg_write__ip_0),
    .scale_io_regs_cfg_write__ip_1(pwm_scale_io_regs_cfg_write__ip_1),
    .scale_io_regs_cfg_write__ip_2(pwm_scale_io_regs_cfg_write__ip_2),
    .scale_io_regs_cfg_write__ip_3(pwm_scale_io_regs_cfg_write__ip_3),
    .scale_io_regs_cfg_write__gang_0(pwm_scale_io_regs_cfg_write__gang_0),
    .scale_io_regs_cfg_write__gang_1(pwm_scale_io_regs_cfg_write__gang_1),
    .scale_io_regs_cfg_write__gang_2(pwm_scale_io_regs_cfg_write__gang_2),
    .scale_io_regs_cfg_write__gang_3(pwm_scale_io_regs_cfg_write__gang_3),
    .scale_io_regs_cfg_write__extra_0(pwm_scale_io_regs_cfg_write__extra_0),
    .scale_io_regs_cfg_write__extra_1(pwm_scale_io_regs_cfg_write__extra_1),
    .scale_io_regs_cfg_write__extra_2(pwm_scale_io_regs_cfg_write__extra_2),
    .scale_io_regs_cfg_write__extra_3(pwm_scale_io_regs_cfg_write__extra_3),
    .scale_io_regs_cfg_write__center_0(pwm_scale_io_regs_cfg_write__center_0),
    .scale_io_regs_cfg_write__center_1(pwm_scale_io_regs_cfg_write__center_1),
    .scale_io_regs_cfg_write__center_2(pwm_scale_io_regs_cfg_write__center_2),
    .scale_io_regs_cfg_write__center_3(pwm_scale_io_regs_cfg_write__center_3),
    .scale_io_regs_cfg_write__running(pwm_scale_io_regs_cfg_write__running),
    .scale_io_regs_cfg_write__countAlways(pwm_scale_io_regs_cfg_write__countAlways),
    .scale_io_regs_cfg_write__deglitch(pwm_scale_io_regs_cfg_write__deglitch),
    .scale_io_regs_cfg_write__zerocmp(pwm_scale_io_regs_cfg_write__zerocmp),
    .scale_io_regs_cfg_write__sticky(pwm_scale_io_regs_cfg_write__sticky),
    .scale_io_regs_cfg_write__scale(pwm_scale_io_regs_cfg_write__scale),
    .scale_io_regs_cfg_read_ip_0(pwm_scale_io_regs_cfg_read_ip_0),
    .scale_io_regs_cfg_read_ip_1(pwm_scale_io_regs_cfg_read_ip_1),
    .scale_io_regs_cfg_read_ip_2(pwm_scale_io_regs_cfg_read_ip_2),
    .scale_io_regs_cfg_read_ip_3(pwm_scale_io_regs_cfg_read_ip_3),
    .scale_io_regs_cfg_read_gang_0(pwm_scale_io_regs_cfg_read_gang_0),
    .scale_io_regs_cfg_read_gang_1(pwm_scale_io_regs_cfg_read_gang_1),
    .scale_io_regs_cfg_read_gang_2(pwm_scale_io_regs_cfg_read_gang_2),
    .scale_io_regs_cfg_read_gang_3(pwm_scale_io_regs_cfg_read_gang_3),
    .scale_io_regs_cfg_read_extra_0(pwm_scale_io_regs_cfg_read_extra_0),
    .scale_io_regs_cfg_read_extra_1(pwm_scale_io_regs_cfg_read_extra_1),
    .scale_io_regs_cfg_read_extra_2(pwm_scale_io_regs_cfg_read_extra_2),
    .scale_io_regs_cfg_read_extra_3(pwm_scale_io_regs_cfg_read_extra_3),
    .scale_io_regs_cfg_read_center_0(pwm_scale_io_regs_cfg_read_center_0),
    .scale_io_regs_cfg_read_center_1(pwm_scale_io_regs_cfg_read_center_1),
    .scale_io_regs_cfg_read_center_2(pwm_scale_io_regs_cfg_read_center_2),
    .scale_io_regs_cfg_read_center_3(pwm_scale_io_regs_cfg_read_center_3),
    .scale_io_regs_cfg_read_running(pwm_scale_io_regs_cfg_read_running),
    .scale_io_regs_cfg_read_countAlways(pwm_scale_io_regs_cfg_read_countAlways),
    .scale_io_regs_cfg_read_deglitch(pwm_scale_io_regs_cfg_read_deglitch),
    .scale_io_regs_cfg_read_zerocmp(pwm_scale_io_regs_cfg_read_zerocmp),
    .scale_io_regs_cfg_read_sticky(pwm_scale_io_regs_cfg_read_sticky),
    .scale_io_regs_cfg_read_scale(pwm_scale_io_regs_cfg_read_scale),
    .scale_io_regs_cfg_write_ip_0(pwm_scale_io_regs_cfg_write_ip_0),
    .scale_io_regs_cfg_write_ip_1(pwm_scale_io_regs_cfg_write_ip_1),
    .scale_io_regs_cfg_write_ip_2(pwm_scale_io_regs_cfg_write_ip_2),
    .scale_io_regs_cfg_write_ip_3(pwm_scale_io_regs_cfg_write_ip_3),
    .scale_io_regs_cfg_write_gang_0(pwm_scale_io_regs_cfg_write_gang_0),
    .scale_io_regs_cfg_write_gang_1(pwm_scale_io_regs_cfg_write_gang_1),
    .scale_io_regs_cfg_write_gang_2(pwm_scale_io_regs_cfg_write_gang_2),
    .scale_io_regs_cfg_write_gang_3(pwm_scale_io_regs_cfg_write_gang_3),
    .scale_io_regs_cfg_write_extra_0(pwm_scale_io_regs_cfg_write_extra_0),
    .scale_io_regs_cfg_write_extra_1(pwm_scale_io_regs_cfg_write_extra_1),
    .scale_io_regs_cfg_write_extra_2(pwm_scale_io_regs_cfg_write_extra_2),
    .scale_io_regs_cfg_write_extra_3(pwm_scale_io_regs_cfg_write_extra_3),
    .scale_io_regs_cfg_write_center_0(pwm_scale_io_regs_cfg_write_center_0),
    .scale_io_regs_cfg_write_center_1(pwm_scale_io_regs_cfg_write_center_1),
    .scale_io_regs_cfg_write_center_2(pwm_scale_io_regs_cfg_write_center_2),
    .scale_io_regs_cfg_write_center_3(pwm_scale_io_regs_cfg_write_center_3),
    .scale_io_regs_cfg_write_running(pwm_scale_io_regs_cfg_write_running),
    .scale_io_regs_cfg_write_countAlways(pwm_scale_io_regs_cfg_write_countAlways),
    .scale_io_regs_cfg_write_deglitch(pwm_scale_io_regs_cfg_write_deglitch),
    .scale_io_regs_cfg_write_zerocmp(pwm_scale_io_regs_cfg_write_zerocmp),
    .scale_io_regs_cfg_write_sticky(pwm_scale_io_regs_cfg_write_sticky),
    .scale_io_regs_cfg_write_scale(pwm_scale_io_regs_cfg_write_scale),
    .scale_io_regs_countLo_write_valid(pwm_scale_io_regs_countLo_write_valid),
    .scale_io_regs_countLo_write_bits(pwm_scale_io_regs_countLo_write_bits),
    .scale_io_regs_countLo_read(pwm_scale_io_regs_countLo_read),
    .scale_io_regs_s_read(pwm_scale_io_regs_s_read),
    .scale_io_regs_cmp_0_write_valid(pwm_scale_io_regs_cmp_0_write_valid),
    .scale_io_regs_cmp_0_write_bits(pwm_scale_io_regs_cmp_0_write_bits),
    .scale_io_regs_cmp_0_read(pwm_scale_io_regs_cmp_0_read),
    .scale_io_regs_cmp_1_write_valid(pwm_scale_io_regs_cmp_1_write_valid),
    .scale_io_regs_cmp_1_write_bits(pwm_scale_io_regs_cmp_1_write_bits),
    .scale_io_regs_cmp_1_read(pwm_scale_io_regs_cmp_1_read),
    .scale_io_regs_cmp_2_write_valid(pwm_scale_io_regs_cmp_2_write_valid),
    .scale_io_regs_cmp_2_write_bits(pwm_scale_io_regs_cmp_2_write_bits),
    .scale_io_regs_cmp_2_read(pwm_scale_io_regs_cmp_2_read),
    .scale_io_regs_cmp_3_write_valid(pwm_scale_io_regs_cmp_3_write_valid),
    .scale_io_regs_cmp_3_write_bits(pwm_scale_io_regs_cmp_3_write_bits),
    .scale_io_regs_cmp_3_read(pwm_scale_io_regs_cmp_3_read),
    .scale_io_ip_0(pwm_scale_io_ip_0),
    .scale_io_ip_1(pwm_scale_io_ip_1),
    .scale_io_ip_2(pwm_scale_io_ip_2),
    .scale_io_ip_3(pwm_scale_io_ip_3),
    .scale_io_gpio_0(pwm_scale_io_gpio_0),
    .scale_io_gpio_1(pwm_scale_io_gpio_1),
    .scale_io_gpio_2(pwm_scale_io_gpio_2),
    .scale_io_gpio_3(pwm_scale_io_gpio_3)
  );
  assign auto_int_xing_out_sync_0 = intsource_auto_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_1 = intsource_auto_out_sync_1; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_2 = intsource_auto_out_sync_2; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_int_xing_out_sync_3 = intsource_auto_out_sync_3; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_in_a_ready = buffer_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_valid = buffer_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_size = buffer_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_source = buffer_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_data = buffer_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_io_out_gpio_0 = pwm_scale_io_gpio_0; // @[Nodes.scala 1207:84 PWM.scala 97:15]
  assign auto_io_out_gpio_1 = pwm_scale_io_gpio_1; // @[Nodes.scala 1207:84 PWM.scala 97:15]
  assign auto_io_out_gpio_2 = pwm_scale_io_gpio_2; // @[Nodes.scala 1207:84 PWM.scala 97:15]
  assign auto_io_out_gpio_3 = pwm_scale_io_gpio_3; // @[Nodes.scala 1207:84 PWM.scala 97:15]
  assign buffer_auto_in_a_valid = auto_control_xing_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_opcode = auto_control_xing_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_param = auto_control_xing_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_size = auto_control_xing_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_source = auto_control_xing_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_address = auto_control_xing_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_mask = auto_control_xing_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_data = auto_control_xing_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_corrupt = auto_control_xing_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_d_ready = auto_control_xing_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_out_a_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign buffer_auto_out_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_data = _GEN_79 ? _GEN_95 : 32'h0; // @[RegisterRouter.scala 83:24]
  assign intsource_clock = clock;
  assign intsource_reset = reset;
  assign intsource_auto_in_0 = pwm_scale_io_ip_0; // @[Nodes.scala 1207:84 PWM.scala 96:16]
  assign intsource_auto_in_1 = pwm_scale_io_ip_1; // @[Nodes.scala 1207:84 PWM.scala 96:16]
  assign intsource_auto_in_2 = pwm_scale_io_ip_2; // @[Nodes.scala 1207:84 PWM.scala 96:16]
  assign intsource_auto_in_3 = pwm_scale_io_ip_3; // @[Nodes.scala 1207:84 PWM.scala 96:16]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_param = buffer_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign monitor_io_in_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign pwm_clock = clock;
  assign pwm_reset = reset;
  assign pwm_scale_io_regs_cfg_write__ip_0 = bundleIn_0_a_bits_data[28]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__ip_1 = bundleIn_0_a_bits_data[29]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__ip_2 = bundleIn_0_a_bits_data[30]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__ip_3 = bundleIn_0_a_bits_data[31]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__gang_0 = bundleIn_0_a_bits_data[24]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__gang_1 = bundleIn_0_a_bits_data[25]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__gang_2 = bundleIn_0_a_bits_data[26]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__gang_3 = bundleIn_0_a_bits_data[27]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__extra_0 = bundleIn_0_a_bits_data[20]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__extra_1 = bundleIn_0_a_bits_data[21]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__extra_2 = bundleIn_0_a_bits_data[22]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__extra_3 = bundleIn_0_a_bits_data[23]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__center_0 = bundleIn_0_a_bits_data[16]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__center_1 = bundleIn_0_a_bits_data[17]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__center_2 = bundleIn_0_a_bits_data[18]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__center_3 = bundleIn_0_a_bits_data[19]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__running = bundleIn_0_a_bits_data[13]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__countAlways = bundleIn_0_a_bits_data[12]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__deglitch = bundleIn_0_a_bits_data[10]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__zerocmp = bundleIn_0_a_bits_data[9]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__sticky = bundleIn_0_a_bits_data[8]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write__scale = bundleIn_0_a_bits_data[3:0]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_ip_0 = out_wivalid_0 & out_wimask_21; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_ip_1 = out_wivalid_0 & out_wimask_22; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_ip_2 = out_wivalid_0 & out_wimask_23; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_ip_3 = out_wivalid_0 & out_wimask_24; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_gang_0 = out_wivalid_0 & out_wimask_17; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_gang_1 = out_wivalid_0 & out_wimask_18; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_gang_2 = out_wivalid_0 & out_wimask_19; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_gang_3 = out_wivalid_0 & out_wimask_20; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_extra_0 = out_wivalid_0 & out_wimask_13; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_extra_1 = out_wivalid_0 & out_wimask_14; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_extra_2 = out_wivalid_0 & out_wimask_15; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_extra_3 = out_wivalid_0 & out_wimask_16; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_center_0 = out_wivalid_0 & out_wimask_9; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_center_1 = out_wivalid_0 & out_wimask_10; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_center_2 = out_wivalid_0 & out_wimask_11; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_center_3 = out_wivalid_0 & out_wimask_12; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_running = out_wivalid_0 & out_wimask_7; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_countAlways = out_wivalid_0 & out_wimask_6; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_deglitch = out_wivalid_0 & out_wimask_4; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_zerocmp = out_wivalid_0 & out_wimask_3; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_sticky = out_wivalid_0 & out_wimask_2; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cfg_write_scale = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_countLo_write_valid = out_wivalid_28 & out_wimask_28; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_countLo_write_bits = bundleIn_0_a_bits_data[30:0]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cmp_0_write_valid = out_wivalid_32 & out_wimask_25; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cmp_0_write_bits = bundleIn_0_a_bits_data[15:0]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cmp_1_write_valid = out_wivalid_27 & out_wimask_25; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cmp_1_write_bits = bundleIn_0_a_bits_data[15:0]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cmp_2_write_valid = out_wivalid_25 & out_wimask_25; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cmp_2_write_bits = bundleIn_0_a_bits_data[15:0]; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cmp_3_write_valid = out_wivalid_31 & out_wimask_25; // @[RegisterRouter.scala 83:24]
  assign pwm_scale_io_regs_cmp_3_write_bits = bundleIn_0_a_bits_data[15:0]; // @[RegisterRouter.scala 83:24]
endmodule
module ClockSinkDomain_12(
  output        auto_pwm_2_int_xing_out_sync_0,
  output        auto_pwm_2_int_xing_out_sync_1,
  output        auto_pwm_2_int_xing_out_sync_2,
  output        auto_pwm_2_int_xing_out_sync_3,
  output        auto_pwm_2_control_xing_in_a_ready,
  input         auto_pwm_2_control_xing_in_a_valid,
  input  [2:0]  auto_pwm_2_control_xing_in_a_bits_opcode,
  input  [2:0]  auto_pwm_2_control_xing_in_a_bits_param,
  input  [1:0]  auto_pwm_2_control_xing_in_a_bits_size,
  input  [6:0]  auto_pwm_2_control_xing_in_a_bits_source,
  input  [28:0] auto_pwm_2_control_xing_in_a_bits_address,
  input  [3:0]  auto_pwm_2_control_xing_in_a_bits_mask,
  input  [31:0] auto_pwm_2_control_xing_in_a_bits_data,
  input         auto_pwm_2_control_xing_in_a_bits_corrupt,
  input         auto_pwm_2_control_xing_in_d_ready,
  output        auto_pwm_2_control_xing_in_d_valid,
  output [2:0]  auto_pwm_2_control_xing_in_d_bits_opcode,
  output [1:0]  auto_pwm_2_control_xing_in_d_bits_size,
  output [6:0]  auto_pwm_2_control_xing_in_d_bits_source,
  output [31:0] auto_pwm_2_control_xing_in_d_bits_data,
  output        auto_pwm_2_io_out_gpio_0,
  output        auto_pwm_2_io_out_gpio_1,
  output        auto_pwm_2_io_out_gpio_2,
  output        auto_pwm_2_io_out_gpio_3,
  input         auto_clock_in_clock,
  input         auto_clock_in_reset
);
  wire  pwm_2_clock; // @[PWM.scala 135:49]
  wire  pwm_2_reset; // @[PWM.scala 135:49]
  wire  pwm_2_auto_int_xing_out_sync_0; // @[PWM.scala 135:49]
  wire  pwm_2_auto_int_xing_out_sync_1; // @[PWM.scala 135:49]
  wire  pwm_2_auto_int_xing_out_sync_2; // @[PWM.scala 135:49]
  wire  pwm_2_auto_int_xing_out_sync_3; // @[PWM.scala 135:49]
  wire  pwm_2_auto_control_xing_in_a_ready; // @[PWM.scala 135:49]
  wire  pwm_2_auto_control_xing_in_a_valid; // @[PWM.scala 135:49]
  wire [2:0] pwm_2_auto_control_xing_in_a_bits_opcode; // @[PWM.scala 135:49]
  wire [2:0] pwm_2_auto_control_xing_in_a_bits_param; // @[PWM.scala 135:49]
  wire [1:0] pwm_2_auto_control_xing_in_a_bits_size; // @[PWM.scala 135:49]
  wire [6:0] pwm_2_auto_control_xing_in_a_bits_source; // @[PWM.scala 135:49]
  wire [28:0] pwm_2_auto_control_xing_in_a_bits_address; // @[PWM.scala 135:49]
  wire [3:0] pwm_2_auto_control_xing_in_a_bits_mask; // @[PWM.scala 135:49]
  wire [31:0] pwm_2_auto_control_xing_in_a_bits_data; // @[PWM.scala 135:49]
  wire  pwm_2_auto_control_xing_in_a_bits_corrupt; // @[PWM.scala 135:49]
  wire  pwm_2_auto_control_xing_in_d_ready; // @[PWM.scala 135:49]
  wire  pwm_2_auto_control_xing_in_d_valid; // @[PWM.scala 135:49]
  wire [2:0] pwm_2_auto_control_xing_in_d_bits_opcode; // @[PWM.scala 135:49]
  wire [1:0] pwm_2_auto_control_xing_in_d_bits_size; // @[PWM.scala 135:49]
  wire [6:0] pwm_2_auto_control_xing_in_d_bits_source; // @[PWM.scala 135:49]
  wire [31:0] pwm_2_auto_control_xing_in_d_bits_data; // @[PWM.scala 135:49]
  wire  pwm_2_auto_io_out_gpio_0; // @[PWM.scala 135:49]
  wire  pwm_2_auto_io_out_gpio_1; // @[PWM.scala 135:49]
  wire  pwm_2_auto_io_out_gpio_2; // @[PWM.scala 135:49]
  wire  pwm_2_auto_io_out_gpio_3; // @[PWM.scala 135:49]
  TLPWM_2 pwm_2 ( // @[PWM.scala 135:49]
    .clock(pwm_2_clock),
    .reset(pwm_2_reset),
    .auto_int_xing_out_sync_0(pwm_2_auto_int_xing_out_sync_0),
    .auto_int_xing_out_sync_1(pwm_2_auto_int_xing_out_sync_1),
    .auto_int_xing_out_sync_2(pwm_2_auto_int_xing_out_sync_2),
    .auto_int_xing_out_sync_3(pwm_2_auto_int_xing_out_sync_3),
    .auto_control_xing_in_a_ready(pwm_2_auto_control_xing_in_a_ready),
    .auto_control_xing_in_a_valid(pwm_2_auto_control_xing_in_a_valid),
    .auto_control_xing_in_a_bits_opcode(pwm_2_auto_control_xing_in_a_bits_opcode),
    .auto_control_xing_in_a_bits_param(pwm_2_auto_control_xing_in_a_bits_param),
    .auto_control_xing_in_a_bits_size(pwm_2_auto_control_xing_in_a_bits_size),
    .auto_control_xing_in_a_bits_source(pwm_2_auto_control_xing_in_a_bits_source),
    .auto_control_xing_in_a_bits_address(pwm_2_auto_control_xing_in_a_bits_address),
    .auto_control_xing_in_a_bits_mask(pwm_2_auto_control_xing_in_a_bits_mask),
    .auto_control_xing_in_a_bits_data(pwm_2_auto_control_xing_in_a_bits_data),
    .auto_control_xing_in_a_bits_corrupt(pwm_2_auto_control_xing_in_a_bits_corrupt),
    .auto_control_xing_in_d_ready(pwm_2_auto_control_xing_in_d_ready),
    .auto_control_xing_in_d_valid(pwm_2_auto_control_xing_in_d_valid),
    .auto_control_xing_in_d_bits_opcode(pwm_2_auto_control_xing_in_d_bits_opcode),
    .auto_control_xing_in_d_bits_size(pwm_2_auto_control_xing_in_d_bits_size),
    .auto_control_xing_in_d_bits_source(pwm_2_auto_control_xing_in_d_bits_source),
    .auto_control_xing_in_d_bits_data(pwm_2_auto_control_xing_in_d_bits_data),
    .auto_io_out_gpio_0(pwm_2_auto_io_out_gpio_0),
    .auto_io_out_gpio_1(pwm_2_auto_io_out_gpio_1),
    .auto_io_out_gpio_2(pwm_2_auto_io_out_gpio_2),
    .auto_io_out_gpio_3(pwm_2_auto_io_out_gpio_3)
  );
  assign auto_pwm_2_int_xing_out_sync_0 = pwm_2_auto_int_xing_out_sync_0; // @[LazyModule.scala 311:12]
  assign auto_pwm_2_int_xing_out_sync_1 = pwm_2_auto_int_xing_out_sync_1; // @[LazyModule.scala 311:12]
  assign auto_pwm_2_int_xing_out_sync_2 = pwm_2_auto_int_xing_out_sync_2; // @[LazyModule.scala 311:12]
  assign auto_pwm_2_int_xing_out_sync_3 = pwm_2_auto_int_xing_out_sync_3; // @[LazyModule.scala 311:12]
  assign auto_pwm_2_control_xing_in_a_ready = pwm_2_auto_control_xing_in_a_ready; // @[LazyModule.scala 309:16]
  assign auto_pwm_2_control_xing_in_d_valid = pwm_2_auto_control_xing_in_d_valid; // @[LazyModule.scala 309:16]
  assign auto_pwm_2_control_xing_in_d_bits_opcode = pwm_2_auto_control_xing_in_d_bits_opcode; // @[LazyModule.scala 309:16]
  assign auto_pwm_2_control_xing_in_d_bits_size = pwm_2_auto_control_xing_in_d_bits_size; // @[LazyModule.scala 309:16]
  assign auto_pwm_2_control_xing_in_d_bits_source = pwm_2_auto_control_xing_in_d_bits_source; // @[LazyModule.scala 309:16]
  assign auto_pwm_2_control_xing_in_d_bits_data = pwm_2_auto_control_xing_in_d_bits_data; // @[LazyModule.scala 309:16]
  assign auto_pwm_2_io_out_gpio_0 = pwm_2_auto_io_out_gpio_0; // @[LazyModule.scala 311:12]
  assign auto_pwm_2_io_out_gpio_1 = pwm_2_auto_io_out_gpio_1; // @[LazyModule.scala 311:12]
  assign auto_pwm_2_io_out_gpio_2 = pwm_2_auto_io_out_gpio_2; // @[LazyModule.scala 311:12]
  assign auto_pwm_2_io_out_gpio_3 = pwm_2_auto_io_out_gpio_3; // @[LazyModule.scala 311:12]
  assign pwm_2_clock = auto_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign pwm_2_reset = auto_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign pwm_2_auto_control_xing_in_a_valid = auto_pwm_2_control_xing_in_a_valid; // @[LazyModule.scala 309:16]
  assign pwm_2_auto_control_xing_in_a_bits_opcode = auto_pwm_2_control_xing_in_a_bits_opcode; // @[LazyModule.scala 309:16]
  assign pwm_2_auto_control_xing_in_a_bits_param = auto_pwm_2_control_xing_in_a_bits_param; // @[LazyModule.scala 309:16]
  assign pwm_2_auto_control_xing_in_a_bits_size = auto_pwm_2_control_xing_in_a_bits_size; // @[LazyModule.scala 309:16]
  assign pwm_2_auto_control_xing_in_a_bits_source = auto_pwm_2_control_xing_in_a_bits_source; // @[LazyModule.scala 309:16]
  assign pwm_2_auto_control_xing_in_a_bits_address = auto_pwm_2_control_xing_in_a_bits_address; // @[LazyModule.scala 309:16]
  assign pwm_2_auto_control_xing_in_a_bits_mask = auto_pwm_2_control_xing_in_a_bits_mask; // @[LazyModule.scala 309:16]
  assign pwm_2_auto_control_xing_in_a_bits_data = auto_pwm_2_control_xing_in_a_bits_data; // @[LazyModule.scala 309:16]
  assign pwm_2_auto_control_xing_in_a_bits_corrupt = auto_pwm_2_control_xing_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
  assign pwm_2_auto_control_xing_in_d_ready = auto_pwm_2_control_xing_in_d_ready; // @[LazyModule.scala 309:16]
endmodule
module TLMonitor_70(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [1:0]  io_in_a_bits_size,
  input  [6:0]  io_in_a_bits_source,
  input  [28:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_size,
  input  [6:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [95:0] _RAND_10;
  reg [383:0] _RAND_11;
  reg [383:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [95:0] _RAND_16;
  reg [383:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T_4 = io_in_a_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire [4:0] _is_aligned_mask_T_1 = 5'h3 << io_in_a_bits_size; // @[package.scala 234:77]
  wire [1:0] is_aligned_mask = ~_is_aligned_mask_T_1[1:0]; // @[package.scala 234:46]
  wire [28:0] _GEN_71 = {{27'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 2'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [28:0] _T_33 = io_in_a_bits_address ^ 29'h10016000; // @[Parameters.scala 137:31]
  wire [29:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
  wire [29:0] _T_36 = $signed(_T_34) & -30'sh1000; // @[Parameters.scala 137:52]
  wire  _T_37 = $signed(_T_36) == 30'sh0; // @[Parameters.scala 137:67]
  wire  _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_74 = _T_73 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_164 = io_in_a_bits_size <= 2'h2; // @[Parameters.scala 92:42]
  wire  _T_172 = _T_164 & _T_37; // @[Parameters.scala 670:56]
  wire  _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_218 = _source_ok_T_4 & _T_172; // @[Monitor.scala 115:71]
  wire  _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_273 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_274 = io_in_a_bits_mask & _T_273; // @[Monitor.scala 127:31]
  wire  _T_275 = _T_274 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_279 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_347 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_355 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_385 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_397 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_10 = io_in_d_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire  _T_401 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_405 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 312:27]
  wire  _T_421 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_449 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_478 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_495 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_513 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [1:0] size; // @[Monitor.scala 386:22]
  reg [6:0] source; // @[Monitor.scala 387:22]
  reg [28:0] address; // @[Monitor.scala 388:22]
  wire  _T_543 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_544 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_548 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_552 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_556 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_560 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] size_1; // @[Monitor.scala 537:22]
  reg [6:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_567 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_568 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_576 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_580 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [95:0] inflight; // @[Monitor.scala 611:27]
  reg [383:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [383:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [8:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [9:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [383:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [383:0] _GEN_73 = {{368'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[383:1]}; // @[Monitor.scala 634:152]
  wire [383:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [383:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
  wire [383:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[383:1]}; // @[Monitor.scala 638:144]
  wire  _T_594 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [127:0] _a_set_wo_ready_T = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_597 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
  wire [8:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [9:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [1026:0] _GEN_1 = {{1023'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [1026:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
  wire [1025:0] _GEN_2 = {{1023'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [1025:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [95:0] _T_599 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_601 = ~_T_599[0]; // @[Monitor.scala 658:17]
  wire [127:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 652:72 653:28]
  wire [1026:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 1027'h0; // @[Monitor.scala 652:72 656:28]
  wire [1025:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 1026'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_605 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_607 = ~_T_401; // @[Monitor.scala 671:74]
  wire  _T_608 = io_in_d_valid & d_first_1 & ~_T_401; // @[Monitor.scala 671:71]
  wire [127:0] _d_clr_wo_ready_T = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [1038:0] _GEN_3 = {{1023'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [1038:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [127:0] _GEN_22 = d_first_done & d_first_1 & _T_607 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 675:91 676:21]
  wire [1038:0] _GEN_23 = d_first_done & d_first_1 & _T_607 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_594 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [95:0] _T_618 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_620 = _T_618[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_625 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_626 = io_in_d_bits_opcode == _GEN_32 | _T_625; // @[Monitor.scala 685:77]
  wire  _T_630 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_637 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_638 = io_in_d_bits_opcode == _GEN_48 | _T_637; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_642 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_652 = _T_605 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_607; // @[Monitor.scala 694:116]
  wire  _T_654 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [95:0] a_set = _GEN_16[95:0];
  wire [95:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [95:0] d_clr = _GEN_22[95:0];
  wire [95:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [95:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [383:0] a_opcodes_set = _GEN_19[383:0];
  wire [383:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [383:0] d_opcodes_clr = _GEN_23[383:0];
  wire [383:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [383:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [383:0] a_sizes_set = _GEN_20[383:0];
  wire [383:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [383:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_663 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [95:0] inflight_1; // @[Monitor.scala 723:35]
  reg [383:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [383:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [383:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
  wire [383:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[383:1]}; // @[Monitor.scala 747:146]
  wire  _T_689 = io_in_d_valid & d_first_2 & _T_401; // @[Monitor.scala 779:71]
  wire [127:0] _GEN_67 = d_first_done & d_first_2 & _T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 783:90 784:21]
  wire [1038:0] _GEN_68 = d_first_done & d_first_2 & _T_401 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 783:90 785:21]
  wire [95:0] _T_697 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_707 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [95:0] d_clr_1 = _GEN_67[95:0];
  wire [95:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [95:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [383:0] d_opcodes_clr_1 = _GEN_68[383:0];
  wire [383:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [383:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_727 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 1'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= 1'h0;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 96'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 384'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 384'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 1'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= 1'h0;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 96'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 384'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= 1'h0;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (d_first_done) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_172 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_172) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_275 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_275) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_309 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_309) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_347 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_347) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_385 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_397 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_397) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_478 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_478 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_495 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_495 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_513 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_513 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_544 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_544) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_548 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_548) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_552 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_552) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_556 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_556) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_560 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_560) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_568 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_568) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_576 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_576) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_580 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_580) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_601 & (_T_597 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_597 & ~reset & ~_T_601) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_620 & (_T_608 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & _T_2 & ~_T_620) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_626 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_626) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_630 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_630) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_638 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_638) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_642 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_642) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_654 & (_T_652 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_652 & _T_2 & ~_T_654) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_663 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_663) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_697[0] & (_T_689 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_689 & _T_2 & ~_T_697[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_707 & (_T_689 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_689 & _T_2 & ~_T_707) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_727 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_727) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[6:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[28:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[6:0];
  _RAND_10 = {3{`RANDOM}};
  inflight = _RAND_10[95:0];
  _RAND_11 = {12{`RANDOM}};
  inflight_opcodes = _RAND_11[383:0];
  _RAND_12 = {12{`RANDOM}};
  inflight_sizes = _RAND_12[383:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {3{`RANDOM}};
  inflight_1 = _RAND_16[95:0];
  _RAND_17 = {12{`RANDOM}};
  inflight_sizes_1 = _RAND_17[383:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLI2C(
  input         clock,
  input         reset,
  output        auto_int_xing_out_sync_0,
  output        auto_control_xing_in_a_ready,
  input         auto_control_xing_in_a_valid,
  input  [2:0]  auto_control_xing_in_a_bits_opcode,
  input  [2:0]  auto_control_xing_in_a_bits_param,
  input  [1:0]  auto_control_xing_in_a_bits_size,
  input  [6:0]  auto_control_xing_in_a_bits_source,
  input  [28:0] auto_control_xing_in_a_bits_address,
  input  [3:0]  auto_control_xing_in_a_bits_mask,
  input  [31:0] auto_control_xing_in_a_bits_data,
  input         auto_control_xing_in_a_bits_corrupt,
  input         auto_control_xing_in_d_ready,
  output        auto_control_xing_in_d_valid,
  output [2:0]  auto_control_xing_in_d_bits_opcode,
  output [1:0]  auto_control_xing_in_d_bits_size,
  output [6:0]  auto_control_xing_in_d_bits_source,
  output [31:0] auto_control_xing_in_d_bits_data,
  input         auto_io_out_scl_in,
  output        auto_io_out_scl_oe,
  input         auto_io_out_sda_in,
  output        auto_io_out_sda_oe
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [31:0] _RAND_33;
  reg [31:0] _RAND_34;
  reg [31:0] _RAND_35;
  reg [31:0] _RAND_36;
  reg [31:0] _RAND_37;
  reg [31:0] _RAND_38;
  reg [31:0] _RAND_39;
  reg [31:0] _RAND_40;
  reg [31:0] _RAND_41;
  reg [31:0] _RAND_42;
  reg [31:0] _RAND_43;
  reg [31:0] _RAND_44;
  reg [31:0] _RAND_45;
  reg [31:0] _RAND_46;
`endif // RANDOMIZE_REG_INIT
  wire  buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
  wire [28:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
  wire [28:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
  wire  intsource_clock; // @[Crossing.scala 26:31]
  wire  intsource_reset; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_0; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_0; // @[Crossing.scala 26:31]
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  reg [7:0] prescaler_hi; // @[I2C.scala 125:25]
  reg [7:0] prescaler_lo; // @[I2C.scala 125:25]
  reg  control_coreEn; // @[I2C.scala 126:25]
  reg  control_intEn; // @[I2C.scala 126:25]
  reg [7:0] transmitData; // @[I2C.scala 127:25]
  reg [7:0] receivedData; // @[I2C.scala 128:25]
  reg  cmd_start; // @[I2C.scala 129:25]
  reg  cmd_stop; // @[I2C.scala 129:25]
  reg  cmd_read; // @[I2C.scala 129:25]
  reg  cmd_write; // @[I2C.scala 129:25]
  reg  cmd_ack; // @[I2C.scala 129:25]
  reg  cmd_irqAck; // @[I2C.scala 129:25]
  reg  status_receivedAck; // @[I2C.scala 130:25]
  reg  status_busy; // @[I2C.scala 130:25]
  reg  status_arbLost; // @[I2C.scala 130:25]
  reg  status_transferInProgress; // @[I2C.scala 130:25]
  reg  status_irqFlag; // @[I2C.scala 130:25]
  reg [13:0] filterCnt; // @[I2C.scala 139:22]
  wire  _T = ~control_coreEn; // @[I2C.scala 140:10]
  wire  _T_2 = ~(|filterCnt); // @[I2C.scala 142:16]
  wire [15:0] _filterCnt_T = {prescaler_hi,prescaler_lo}; // @[Cat.scala 31:58]
  wire [13:0] _filterCnt_T_3 = filterCnt - 14'h1; // @[I2C.scala 145:28]
  reg [2:0] fSCL; // @[I2C.scala 148:22]
  reg [2:0] fSDA; // @[I2C.scala 149:22]
  wire [3:0] _fSCL_T = {fSCL,auto_io_out_scl_in}; // @[Cat.scala 31:58]
  wire [3:0] _fSDA_T = {fSDA,auto_io_out_sda_in}; // @[Cat.scala 31:58]
  wire [3:0] _GEN_2 = _T_2 ? _fSCL_T : {{1'd0}, fSCL}; // @[I2C.scala 150:27 151:10 148:22]
  wire [3:0] _GEN_3 = _T_2 ? _fSDA_T : {{1'd0}, fSDA}; // @[I2C.scala 150:27 152:10 149:22]
  wire  _sSCL_x29_T_3 = fSCL[0] & fSCL[1]; // @[Misc.scala 166:48]
  wire  _sSCL_x29_T_4 = fSCL[0] & fSCL[2]; // @[Misc.scala 166:48]
  wire  _sSCL_x29_T_6 = fSCL[1] & fSCL[2]; // @[Misc.scala 166:48]
  wire  sSCL_x29 = _sSCL_x29_T_3 | _sSCL_x29_T_4 | _sSCL_x29_T_6; // @[Misc.scala 167:22]
  reg  sSCL; // @[I2C.scala 155:22]
  wire  _sSDA_x32_T_3 = fSDA[0] & fSDA[1]; // @[Misc.scala 166:48]
  wire  _sSDA_x32_T_4 = fSDA[0] & fSDA[2]; // @[Misc.scala 166:48]
  wire  _sSDA_x32_T_6 = fSDA[1] & fSDA[2]; // @[Misc.scala 166:48]
  wire  sSDA_x32 = _sSDA_x32_T_3 | _sSDA_x32_T_4 | _sSDA_x32_T_6; // @[Misc.scala 167:22]
  reg  sSDA; // @[I2C.scala 156:22]
  reg  dSCL; // @[I2C.scala 158:22]
  reg  dSDA; // @[I2C.scala 159:22]
  reg  dSCLOen; // @[I2C.scala 161:22]
  wire  _startCond_x44_T = ~sSDA; // @[I2C.scala 165:46]
  wire  startCond_x44 = ~sSDA & dSDA & sSCL; // @[I2C.scala 165:61]
  reg  startCond; // @[I2C.scala 165:22]
  wire  stopCond_x47 = sSDA & ~dSDA & sSCL; // @[I2C.scala 166:61]
  reg  stopCond; // @[I2C.scala 166:22]
  wire  _sclSync_T = ~sSCL; // @[I2C.scala 170:27]
  reg  sclOen; // @[I2C.scala 193:23]
  wire  bundleOut_0_scl_oe = ~sclOen; // @[I2C.scala 194:18]
  wire  sclSync = dSCL & ~sSCL & bundleOut_0_scl_oe; // @[I2C.scala 170:33]
  reg  slaveWait; // @[I2C.scala 174:22]
  reg  clkEn; // @[I2C.scala 177:22]
  reg [15:0] cnt; // @[I2C.scala 178:22]
  wire  _T_9 = ~(|cnt) | _T | sclSync; // @[I2C.scala 181:39]
  wire [15:0] _cnt_T_2 = cnt - 16'h1; // @[I2C.scala 189:18]
  reg  sdaOen; // @[I2C.scala 196:23]
  reg  sdaChk; // @[I2C.scala 199:23]
  reg  transmitBit; // @[I2C.scala 201:24]
  reg  receivedBit; // @[I2C.scala 202:24]
  reg [3:0] bitCmd; // @[I2C.scala 207:24]
  reg  bitCmdStop; // @[I2C.scala 208:24]
  reg  bitCmdAck; // @[I2C.scala 212:24]
  reg [4:0] bitState; // @[I2C.scala 219:24]
  wire  arbLost_x83 = sdaChk & _startCond_x44_T & sdaOen | bitState != 5'h0 & stopCond & ~bitCmdStop; // @[I2C.scala 221:76]
  reg  arbLost; // @[I2C.scala 221:24]
  wire [4:0] _GEN_10 = 4'h8 == bitCmd ? 5'ha : bitState; // @[I2C.scala 219:24 237:27 241:43]
  wire [4:0] _GEN_11 = 4'h4 == bitCmd ? 5'he : _GEN_10; // @[I2C.scala 237:27 240:43]
  wire [4:0] _GEN_12 = 4'h2 == bitCmd ? 5'h6 : _GEN_11; // @[I2C.scala 237:27 239:43]
  wire [4:0] _GEN_13 = 4'h1 == bitCmd ? 5'h1 : _GEN_12; // @[I2C.scala 237:27 238:43]
  wire [4:0] _GEN_14 = 5'h11 == bitState ? 5'h0 : bitState; // @[I2C.scala 235:25 349:21 219:24]
  wire  _GEN_16 = 5'h11 == bitState ? 1'h0 : sclOen; // @[I2C.scala 235:25 351:21 193:23]
  wire  _GEN_17 = 5'h11 == bitState ? transmitBit : sdaOen; // @[I2C.scala 235:25 352:21 196:23]
  wire  _GEN_18 = 5'h11 == bitState ? 1'h0 : sdaChk; // @[I2C.scala 235:25 353:21 199:23]
  wire [4:0] _GEN_19 = 5'h10 == bitState ? 5'h11 : _GEN_14; // @[I2C.scala 235:25 343:21]
  wire  _GEN_20 = 5'h10 == bitState | _GEN_16; // @[I2C.scala 235:25 344:21]
  wire  _GEN_21 = 5'h10 == bitState ? transmitBit : _GEN_17; // @[I2C.scala 235:25 345:21]
  wire  _GEN_22 = 5'h10 == bitState | _GEN_18; // @[I2C.scala 235:25 346:21]
  wire  _GEN_23 = 5'h10 == bitState ? 1'h0 : 5'h11 == bitState; // @[I2C.scala 232:15 235:25]
  wire [4:0] _GEN_24 = 5'hf == bitState ? 5'h10 : _GEN_19; // @[I2C.scala 235:25 337:21]
  wire  _GEN_25 = 5'hf == bitState | _GEN_20; // @[I2C.scala 235:25 338:21]
  wire  _GEN_26 = 5'hf == bitState ? transmitBit : _GEN_21; // @[I2C.scala 235:25 339:21]
  wire  _GEN_27 = 5'hf == bitState ? 1'h0 : _GEN_22; // @[I2C.scala 235:25 340:21]
  wire  _GEN_28 = 5'hf == bitState ? 1'h0 : _GEN_23; // @[I2C.scala 232:15 235:25]
  wire [4:0] _GEN_29 = 5'he == bitState ? 5'hf : _GEN_24; // @[I2C.scala 235:25 331:21]
  wire  _GEN_30 = 5'he == bitState ? 1'h0 : _GEN_25; // @[I2C.scala 235:25 332:21]
  wire  _GEN_31 = 5'he == bitState ? transmitBit : _GEN_26; // @[I2C.scala 235:25 333:21]
  wire  _GEN_32 = 5'he == bitState ? 1'h0 : _GEN_27; // @[I2C.scala 235:25 334:21]
  wire  _GEN_33 = 5'he == bitState ? 1'h0 : _GEN_28; // @[I2C.scala 232:15 235:25]
  wire [4:0] _GEN_34 = 5'hd == bitState ? 5'h0 : _GEN_29; // @[I2C.scala 235:25 323:21]
  wire  _GEN_35 = 5'hd == bitState | _GEN_33; // @[I2C.scala 235:25 324:21]
  wire  _GEN_36 = 5'hd == bitState ? 1'h0 : _GEN_30; // @[I2C.scala 235:25 325:21]
  wire  _GEN_37 = 5'hd == bitState | _GEN_31; // @[I2C.scala 235:25 326:21]
  wire  _GEN_38 = 5'hd == bitState ? 1'h0 : _GEN_32; // @[I2C.scala 235:25 327:21]
  wire [4:0] _GEN_39 = 5'hc == bitState ? 5'hd : _GEN_34; // @[I2C.scala 235:25 317:21]
  wire  _GEN_40 = 5'hc == bitState | _GEN_36; // @[I2C.scala 235:25 318:21]
  wire  _GEN_41 = 5'hc == bitState | _GEN_37; // @[I2C.scala 235:25 319:21]
  wire  _GEN_42 = 5'hc == bitState ? 1'h0 : _GEN_38; // @[I2C.scala 235:25 320:21]
  wire  _GEN_43 = 5'hc == bitState ? 1'h0 : _GEN_35; // @[I2C.scala 232:15 235:25]
  wire [4:0] _GEN_44 = 5'hb == bitState ? 5'hc : _GEN_39; // @[I2C.scala 235:25 311:21]
  wire  _GEN_45 = 5'hb == bitState | _GEN_40; // @[I2C.scala 235:25 312:21]
  wire  _GEN_46 = 5'hb == bitState | _GEN_41; // @[I2C.scala 235:25 313:21]
  wire  _GEN_47 = 5'hb == bitState ? 1'h0 : _GEN_42; // @[I2C.scala 235:25 314:21]
  wire  _GEN_48 = 5'hb == bitState ? 1'h0 : _GEN_43; // @[I2C.scala 232:15 235:25]
  wire [4:0] _GEN_49 = 5'ha == bitState ? 5'hb : _GEN_44; // @[I2C.scala 235:25 305:21]
  wire  _GEN_50 = 5'ha == bitState ? 1'h0 : _GEN_45; // @[I2C.scala 235:25 306:21]
  wire  _GEN_51 = 5'ha == bitState | _GEN_46; // @[I2C.scala 235:25 307:21]
  wire  _GEN_52 = 5'ha == bitState ? 1'h0 : _GEN_47; // @[I2C.scala 235:25 308:21]
  wire  _GEN_53 = 5'ha == bitState ? 1'h0 : _GEN_48; // @[I2C.scala 232:15 235:25]
  wire [4:0] _GEN_54 = 5'h9 == bitState ? 5'h0 : _GEN_49; // @[I2C.scala 235:25 297:21]
  wire  _GEN_55 = 5'h9 == bitState | _GEN_53; // @[I2C.scala 235:25 298:21]
  wire  _GEN_56 = 5'h9 == bitState | _GEN_50; // @[I2C.scala 235:25 299:21]
  wire  _GEN_57 = 5'h9 == bitState | _GEN_51; // @[I2C.scala 235:25 300:21]
  wire  _GEN_58 = 5'h9 == bitState ? 1'h0 : _GEN_52; // @[I2C.scala 235:25 301:21]
  wire [4:0] _GEN_59 = 5'h8 == bitState ? 5'h9 : _GEN_54; // @[I2C.scala 235:25 291:21]
  wire  _GEN_60 = 5'h8 == bitState | _GEN_56; // @[I2C.scala 235:25 292:21]
  wire  _GEN_61 = 5'h8 == bitState ? 1'h0 : _GEN_57; // @[I2C.scala 235:25 293:21]
  wire  _GEN_62 = 5'h8 == bitState ? 1'h0 : _GEN_58; // @[I2C.scala 235:25 294:21]
  wire  _GEN_63 = 5'h8 == bitState ? 1'h0 : _GEN_55; // @[I2C.scala 232:15 235:25]
  wire [4:0] _GEN_64 = 5'h7 == bitState ? 5'h8 : _GEN_59; // @[I2C.scala 235:25 285:21]
  wire  _GEN_65 = 5'h7 == bitState | _GEN_60; // @[I2C.scala 235:25 286:21]
  wire  _GEN_66 = 5'h7 == bitState ? 1'h0 : _GEN_61; // @[I2C.scala 235:25 287:21]
  wire  _GEN_67 = 5'h7 == bitState ? 1'h0 : _GEN_62; // @[I2C.scala 235:25 288:21]
  wire  _GEN_68 = 5'h7 == bitState ? 1'h0 : _GEN_63; // @[I2C.scala 232:15 235:25]
  wire [4:0] _GEN_69 = 5'h6 == bitState ? 5'h7 : _GEN_64; // @[I2C.scala 235:25 279:21]
  wire  _GEN_70 = 5'h6 == bitState ? 1'h0 : _GEN_65; // @[I2C.scala 235:25 280:21]
  wire  _GEN_71 = 5'h6 == bitState ? 1'h0 : _GEN_66; // @[I2C.scala 235:25 281:21]
  wire  _GEN_72 = 5'h6 == bitState ? 1'h0 : _GEN_67; // @[I2C.scala 235:25 282:21]
  wire  _GEN_73 = 5'h6 == bitState ? 1'h0 : _GEN_68; // @[I2C.scala 232:15 235:25]
  wire [4:0] _GEN_74 = 5'h5 == bitState ? 5'h0 : _GEN_69; // @[I2C.scala 235:25 271:21]
  wire  _GEN_75 = 5'h5 == bitState | _GEN_73; // @[I2C.scala 235:25 272:21]
  wire  _GEN_76 = 5'h5 == bitState ? 1'h0 : _GEN_70; // @[I2C.scala 235:25 273:21]
  wire  _GEN_77 = 5'h5 == bitState ? 1'h0 : _GEN_71; // @[I2C.scala 235:25 274:21]
  wire  _GEN_78 = 5'h5 == bitState ? 1'h0 : _GEN_72; // @[I2C.scala 235:25 275:21]
  wire [4:0] _GEN_79 = 5'h4 == bitState ? 5'h5 : _GEN_74; // @[I2C.scala 235:25 265:21]
  wire  _GEN_80 = 5'h4 == bitState | _GEN_76; // @[I2C.scala 235:25 266:21]
  wire  _GEN_81 = 5'h4 == bitState ? 1'h0 : _GEN_77; // @[I2C.scala 235:25 267:21]
  wire  _GEN_82 = 5'h4 == bitState ? 1'h0 : _GEN_78; // @[I2C.scala 235:25 268:21]
  wire  _GEN_83 = 5'h4 == bitState ? 1'h0 : _GEN_75; // @[I2C.scala 232:15 235:25]
  wire [4:0] _GEN_84 = 5'h3 == bitState ? 5'h4 : _GEN_79; // @[I2C.scala 235:25 259:21]
  wire  _GEN_85 = 5'h3 == bitState | _GEN_80; // @[I2C.scala 235:25 260:21]
  wire  _GEN_86 = 5'h3 == bitState ? 1'h0 : _GEN_81; // @[I2C.scala 235:25 261:21]
  wire  _GEN_87 = 5'h3 == bitState ? 1'h0 : _GEN_82; // @[I2C.scala 235:25 262:21]
  wire  _GEN_88 = 5'h3 == bitState ? 1'h0 : _GEN_83; // @[I2C.scala 232:15 235:25]
  wire [4:0] _GEN_89 = 5'h2 == bitState ? 5'h3 : _GEN_84; // @[I2C.scala 235:25 253:21]
  wire  _GEN_90 = 5'h2 == bitState | _GEN_85; // @[I2C.scala 235:25 254:21]
  wire  _GEN_91 = 5'h2 == bitState | _GEN_86; // @[I2C.scala 235:25 255:21]
  wire  _GEN_92 = 5'h2 == bitState ? 1'h0 : _GEN_87; // @[I2C.scala 235:25 256:21]
  wire  _GEN_93 = 5'h2 == bitState ? 1'h0 : _GEN_88; // @[I2C.scala 232:15 235:25]
  wire [4:0] _GEN_94 = 5'h1 == bitState ? 5'h2 : _GEN_89; // @[I2C.scala 235:25 247:21]
  wire  _GEN_95 = 5'h1 == bitState ? sclOen : _GEN_90; // @[I2C.scala 235:25 248:21]
  wire  _GEN_96 = 5'h1 == bitState | _GEN_91; // @[I2C.scala 235:25 249:21]
  wire  _GEN_97 = 5'h1 == bitState ? 1'h0 : _GEN_92; // @[I2C.scala 235:25 250:21]
  wire  _GEN_98 = 5'h1 == bitState ? 1'h0 : _GEN_93; // @[I2C.scala 232:15 235:25]
  wire  _GEN_101 = 5'h0 == bitState ? sclOen : _GEN_95; // @[I2C.scala 193:23 235:25]
  wire  _GEN_102 = 5'h0 == bitState ? sdaOen : _GEN_96; // @[I2C.scala 196:23 235:25]
  wire  _GEN_103 = 5'h0 == bitState ? 1'h0 : _GEN_98; // @[I2C.scala 232:15 235:25]
  wire  _GEN_106 = clkEn ? _GEN_101 : sclOen; // @[I2C.scala 234:18 193:23]
  wire  _GEN_107 = clkEn ? _GEN_102 : sdaOen; // @[I2C.scala 234:18 196:23]
  wire  _GEN_108 = clkEn & _GEN_103; // @[I2C.scala 232:15 234:18]
  wire  _GEN_111 = arbLost | _GEN_106; // @[I2C.scala 224:18 227:15]
  wire  _GEN_112 = arbLost | _GEN_107; // @[I2C.scala 224:18 228:15]
  reg  load; // @[I2C.scala 361:24]
  reg  shift; // @[I2C.scala 362:24]
  reg  cmdAck; // @[I2C.scala 363:24]
  reg  receivedAck; // @[I2C.scala 364:24]
  wire  _go_T = cmd_read | cmd_write; // @[I2C.scala 365:31]
  wire  go = (cmd_read | cmd_write | cmd_stop) & ~cmdAck; // @[I2C.scala 365:55]
  reg [2:0] bitCnt; // @[I2C.scala 367:24]
  wire [2:0] _bitCnt_T_1 = bitCnt - 3'h1; // @[I2C.scala 372:22]
  wire  bitCntDone = ~(|bitCnt); // @[I2C.scala 374:21]
  wire [8:0] _receivedData_T = {receivedData,receivedBit}; // @[Cat.scala 31:58]
  wire [8:0] _GEN_116 = shift ? _receivedData_T : {{1'd0}, receivedData}; // @[I2C.scala 380:21 381:18 128:25]
  wire [8:0] _GEN_117 = load ? {{1'd0}, transmitData} : _GEN_116; // @[I2C.scala 377:15 378:18]
  reg [2:0] byteState; // @[I2C.scala 385:24]
  wire [2:0] _GEN_118 = cmd_write ? 3'h3 : 3'h5; // @[I2C.scala 413:33 414:23 418:23]
  wire [2:0] _GEN_119 = cmd_write ? 3'h4 : 3'h2; // @[I2C.scala 413:33 415:23 419:23]
  wire [2:0] _GEN_120 = cmd_read ? 3'h2 : _GEN_118; // @[I2C.scala 409:32 410:23]
  wire [3:0] _GEN_121 = cmd_read ? 4'h8 : {{1'd0}, _GEN_119}; // @[I2C.scala 409:32 411:23]
  wire [2:0] _GEN_122 = cmd_start ? 3'h1 : _GEN_120; // @[I2C.scala 405:28 406:23]
  wire [3:0] _GEN_123 = cmd_start ? 4'h1 : _GEN_121; // @[I2C.scala 405:28 407:23]
  wire [2:0] _GEN_127 = cmd_read ? 3'h2 : 3'h3; // @[I2C.scala 427:27 428:23 432:23]
  wire [3:0] _GEN_128 = cmd_read ? 4'h8 : 4'h4; // @[I2C.scala 427:27 429:23 433:23]
  wire [2:0] _GEN_129 = bitCmdAck ? _GEN_127 : byteState; // @[I2C.scala 385:24 426:26]
  wire [3:0] _GEN_130 = bitCmdAck ? _GEN_128 : bitCmd; // @[I2C.scala 207:24 426:26]
  wire [2:0] _GEN_132 = bitCntDone ? 3'h4 : 3'h3; // @[I2C.scala 441:29 442:23 446:23]
  wire [3:0] _GEN_133 = bitCntDone ? 4'h8 : 4'h4; // @[I2C.scala 441:29 443:23 447:23]
  wire  _GEN_134 = bitCntDone ? 1'h0 : 1'h1; // @[I2C.scala 398:17 441:29 448:23]
  wire [2:0] _GEN_135 = bitCmdAck ? _GEN_132 : byteState; // @[I2C.scala 385:24 440:26]
  wire [3:0] _GEN_136 = bitCmdAck ? _GEN_133 : bitCmd; // @[I2C.scala 207:24 440:26]
  wire  _GEN_137 = bitCmdAck & _GEN_134; // @[I2C.scala 398:17 440:26]
  wire [2:0] _GEN_138 = bitCntDone ? 3'h4 : 3'h2; // @[I2C.scala 454:29 455:23 459:23]
  wire [3:0] _GEN_139 = bitCntDone ? 4'h4 : 4'h8; // @[I2C.scala 454:29 456:23 460:23]
  wire [2:0] _GEN_140 = bitCmdAck ? _GEN_138 : byteState; // @[I2C.scala 385:24 453:26]
  wire [3:0] _GEN_141 = bitCmdAck ? _GEN_139 : bitCmd; // @[I2C.scala 207:24 453:26]
  wire  _GEN_142 = bitCmdAck ? cmd_ack : receivedData[7]; // @[I2C.scala 397:17 453:26 464:23]
  wire [2:0] _GEN_143 = cmd_stop ? 3'h5 : 3'h0; // @[I2C.scala 469:27 470:23 474:23]
  wire [1:0] _GEN_144 = cmd_stop ? 2'h2 : 2'h0; // @[I2C.scala 469:27 471:23 475:23]
  wire  _GEN_145 = cmd_stop ? 1'h0 : 1'h1; // @[I2C.scala 400:17 469:27 478:23]
  wire [2:0] _GEN_146 = bitCmdAck ? _GEN_143 : byteState; // @[I2C.scala 385:24 468:26]
  wire [3:0] _GEN_147 = bitCmdAck ? {{2'd0}, _GEN_144} : bitCmd; // @[I2C.scala 207:24 468:26]
  wire  _GEN_148 = bitCmdAck & _GEN_145; // @[I2C.scala 400:17 468:26]
  wire  _GEN_149 = bitCmdAck ? receivedBit : receivedAck; // @[I2C.scala 468:26 482:23 364:24]
  wire  _GEN_150 = bitCmdAck | cmd_ack; // @[I2C.scala 468:26 484:23 487:23]
  wire [2:0] _GEN_151 = bitCmdAck ? 3'h0 : byteState; // @[I2C.scala 491:26 492:21 385:24]
  wire [3:0] _GEN_152 = bitCmdAck ? 4'h0 : bitCmd; // @[I2C.scala 491:26 493:21 207:24]
  wire [2:0] _GEN_153 = 3'h5 == byteState ? _GEN_151 : byteState; // @[I2C.scala 385:24 402:24]
  wire [3:0] _GEN_154 = 3'h5 == byteState ? _GEN_152 : bitCmd; // @[I2C.scala 207:24 402:24]
  wire  _GEN_155 = 3'h5 == byteState & bitCmdAck; // @[I2C.scala 400:17 402:24]
  wire [2:0] _GEN_156 = 3'h4 == byteState ? _GEN_146 : _GEN_153; // @[I2C.scala 402:24]
  wire [3:0] _GEN_157 = 3'h4 == byteState ? _GEN_147 : _GEN_154; // @[I2C.scala 402:24]
  wire  _GEN_158 = 3'h4 == byteState ? _GEN_148 : _GEN_155; // @[I2C.scala 402:24]
  wire  _GEN_159 = 3'h4 == byteState ? _GEN_149 : receivedAck; // @[I2C.scala 364:24 402:24]
  wire  _GEN_160 = 3'h4 == byteState ? _GEN_150 : receivedData[7]; // @[I2C.scala 397:17 402:24]
  wire [2:0] _GEN_161 = 3'h2 == byteState ? _GEN_140 : _GEN_156; // @[I2C.scala 402:24]
  wire [3:0] _GEN_162 = 3'h2 == byteState ? _GEN_141 : _GEN_157; // @[I2C.scala 402:24]
  wire  _GEN_163 = 3'h2 == byteState & bitCmdAck; // @[I2C.scala 398:17 402:24]
  wire  _GEN_164 = 3'h2 == byteState ? _GEN_142 : _GEN_160; // @[I2C.scala 402:24]
  wire  _GEN_165 = 3'h2 == byteState ? 1'h0 : _GEN_158; // @[I2C.scala 400:17 402:24]
  wire  _GEN_166 = 3'h2 == byteState ? receivedAck : _GEN_159; // @[I2C.scala 364:24 402:24]
  wire [2:0] _GEN_167 = 3'h3 == byteState ? _GEN_135 : _GEN_161; // @[I2C.scala 402:24]
  wire [3:0] _GEN_168 = 3'h3 == byteState ? _GEN_136 : _GEN_162; // @[I2C.scala 402:24]
  wire  _GEN_169 = 3'h3 == byteState ? _GEN_137 : _GEN_163; // @[I2C.scala 402:24]
  wire  _GEN_170 = 3'h3 == byteState ? receivedData[7] : _GEN_164; // @[I2C.scala 397:17 402:24]
  wire  _GEN_171 = 3'h3 == byteState ? 1'h0 : _GEN_165; // @[I2C.scala 400:17 402:24]
  wire  _GEN_172 = 3'h3 == byteState ? receivedAck : _GEN_166; // @[I2C.scala 364:24 402:24]
  wire  _GEN_175 = 3'h1 == byteState & bitCmdAck; // @[I2C.scala 399:17 402:24]
  wire  bundleIn_0_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [2:0] bundleIn_0_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  in_bits_read = bundleIn_0_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 72:36]
  wire [28:0] bundleIn_0_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [9:0] in_bits_index = bundleIn_0_a_bits_address[11:2]; // @[RegisterRouter.scala 71:18 73:19]
  wire [2:0] out_iindex = {in_bits_index[2],in_bits_index[1],in_bits_index[0]}; // @[Cat.scala 31:58]
  wire [9:0] out_findex = in_bits_index & 10'h3f8; // @[RegisterRouter.scala 83:24]
  wire  _out_T_8 = out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  bundleIn_0_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [7:0] _out_backSel_T = 8'h1 << out_iindex; // @[OneHot.scala 57:35]
  wire  out_backSel_4 = _out_backSel_T[4]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_6 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_backSel_4 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [3:0] bundleIn_0_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [7:0] _out_backMask_T_11 = bundleIn_0_a_bits_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_backMask_T_9 = bundleIn_0_a_bits_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_backMask_T_7 = bundleIn_0_a_bits_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_backMask_T_5 = bundleIn_0_a_bits_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [31:0] out_backMask = {_out_backMask_T_11,_out_backMask_T_9,_out_backMask_T_7,_out_backMask_T_5}; // @[Cat.scala 31:58]
  wire  out_womask_6 = &out_backMask[7:0]; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala 83:24]
  wire [31:0] bundleIn_0_a_bits_data = buffer_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [7:0] _nextCmd_T = {cmd_start,cmd_stop,cmd_read,cmd_write,cmd_ack,2'h0,cmd_irqAck}; // @[I2C.scala 508:18]
  wire [7:0] _nextCmd_T_1 = _nextCmd_T & 8'hfe; // @[I2C.scala 508:25]
  wire [7:0] nextCmd = out_f_woready_6 ? bundleIn_0_a_bits_data[7:0] : _nextCmd_T_1; // @[I2C.scala 508:11 564:77 566:74]
  wire  _T_40 = cmdAck | arbLost; // @[I2C.scala 511:16]
  wire  _GEN_198 = startCond | status_busy; // @[I2C.scala 130:25 522:25 523:29]
  wire  _GEN_200 = cmd_start ? 1'h0 : status_arbLost; // @[I2C.scala 130:25 529:25 530:29]
  wire  _GEN_201 = arbLost | _GEN_200; // @[I2C.scala 526:18 527:29]
  reg  statusReadReady; // @[I2C.scala 536:28]
  wire  _GEN_202 = ~statusReadReady | statusReadReady; // @[I2C.scala 540:32 541:21 536:28]
  wire  _GEN_203 = _T_40 ? 1'h0 : _GEN_202; // @[I2C.scala 537:28 538:21]
  wire  out_rimask = |out_backMask[7:0]; // @[RegisterRouter.scala 83:24]
  wire  out_rofireMux_out_4 = statusReadReady | ~out_rimask; // @[RegisterRouter.scala 83:24]
  wire  _out_rofireMux_T_21 = out_rofireMux_out_4 | ~(out_findex == 10'h0); // @[RegisterRouter.scala 83:24]
  wire  _GEN_232 = 3'h4 == out_iindex ? _out_rofireMux_T_21 : 1'h1; // @[MuxLiteral.scala 48:{10,10}]
  wire  out_rofireMux = 3'h7 == out_iindex | (3'h6 == out_iindex | (3'h5 == out_iindex | _GEN_232)); // @[MuxLiteral.scala 48:{10,10}]
  wire  out_oready = in_bits_read ? out_rofireMux : 1'h1; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_0 = _out_backSel_T[0]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_0 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_0 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready = out_woready_0 & out_womask_6; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_1 = _out_backSel_T[1]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_1 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_1 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_1 = out_woready_1 & out_womask_6; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_2 = _out_backSel_T[2]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_2 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_2 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_3 = &out_backMask[6]; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_3 = out_woready_2 & out_wimask_3; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_4 = &out_backMask[7]; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_4 = out_woready_2 & out_wimask_4; // @[RegisterRouter.scala 83:24]
  wire [7:0] out_prepend_1 = {control_coreEn,control_intEn,6'h0}; // @[Cat.scala 31:58]
  wire  out_frontSel_3 = _out_backSel_T[3]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_5 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_3 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_5 = out_woready_5 & out_womask_6; // @[RegisterRouter.scala 83:24]
  wire [7:0] out_f_data = {status_receivedAck,status_busy,status_arbLost,3'h0,status_transferInProgress,status_irqFlag}; // @[I2C.scala 561:89]
  wire  _GEN_210 = out_f_woready_6 ? 1'h0 : _GEN_203; // @[I2C.scala 564:77 565:82]
  wire  _GEN_245 = 3'h1 == out_iindex ? _out_T_8 : _out_T_8; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_246 = 3'h2 == out_iindex ? _out_T_8 : _GEN_245; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_247 = 3'h3 == out_iindex ? _out_T_8 : _GEN_246; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_248 = 3'h4 == out_iindex ? _out_T_8 : _GEN_247; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_251 = 3'h7 == out_iindex | (3'h6 == out_iindex | (3'h5 == out_iindex | _GEN_248)); // @[MuxLiteral.scala 48:{10,10}]
  wire [7:0] _GEN_253 = 3'h1 == out_iindex ? prescaler_hi : prescaler_lo; // @[MuxLiteral.scala 48:{10,10}]
  wire [7:0] _GEN_254 = 3'h2 == out_iindex ? out_prepend_1 : _GEN_253; // @[MuxLiteral.scala 48:{10,10}]
  wire [7:0] _GEN_255 = 3'h3 == out_iindex ? receivedData : _GEN_254; // @[MuxLiteral.scala 48:{10,10}]
  wire [7:0] _GEN_256 = 3'h4 == out_iindex ? out_f_data : _GEN_255; // @[MuxLiteral.scala 48:{10,10}]
  wire [7:0] _GEN_257 = 3'h5 == out_iindex ? 8'h0 : _GEN_256; // @[MuxLiteral.scala 48:{10,10}]
  wire [7:0] _GEN_258 = 3'h6 == out_iindex ? 8'h0 : _GEN_257; // @[MuxLiteral.scala 48:{10,10}]
  wire [7:0] _GEN_259 = 3'h7 == out_iindex ? 8'h0 : _GEN_258; // @[MuxLiteral.scala 48:{10,10}]
  wire [7:0] _out_out_bits_data_T_4 = _GEN_251 ? _GEN_259 : 8'h0; // @[RegisterRouter.scala 83:24]
  TLBuffer_13 buffer ( // @[Buffer.scala 68:28]
    .auto_in_a_ready(buffer_auto_in_a_ready),
    .auto_in_a_valid(buffer_auto_in_a_valid),
    .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
    .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
    .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
    .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
    .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
    .auto_in_a_bits_data(buffer_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
    .auto_in_d_ready(buffer_auto_in_d_ready),
    .auto_in_d_valid(buffer_auto_in_d_valid),
    .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
    .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
    .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
    .auto_out_a_ready(buffer_auto_out_a_ready),
    .auto_out_a_valid(buffer_auto_out_a_valid),
    .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
    .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
    .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
    .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
    .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
    .auto_out_a_bits_data(buffer_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
    .auto_out_d_ready(buffer_auto_out_d_ready),
    .auto_out_d_valid(buffer_auto_out_d_valid),
    .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
    .auto_out_d_bits_source(buffer_auto_out_d_bits_source),
    .auto_out_d_bits_data(buffer_auto_out_d_bits_data)
  );
  IntSyncCrossingSource_1 intsource ( // @[Crossing.scala 26:31]
    .clock(intsource_clock),
    .reset(intsource_reset),
    .auto_in_0(intsource_auto_in_0),
    .auto_out_sync_0(intsource_auto_out_sync_0)
  );
  TLMonitor_70 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  assign auto_int_xing_out_sync_0 = intsource_auto_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_in_a_ready = buffer_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_valid = buffer_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_size = buffer_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_source = buffer_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_data = buffer_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_io_out_scl_oe = ~sclOen; // @[I2C.scala 194:18]
  assign auto_io_out_sda_oe = ~sdaOen; // @[I2C.scala 197:18]
  assign buffer_auto_in_a_valid = auto_control_xing_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_opcode = auto_control_xing_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_param = auto_control_xing_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_size = auto_control_xing_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_source = auto_control_xing_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_address = auto_control_xing_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_mask = auto_control_xing_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_data = auto_control_xing_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_corrupt = auto_control_xing_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_d_ready = auto_control_xing_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_out_a_ready = bundleIn_0_d_ready & out_oready; // @[RegisterRouter.scala 83:24]
  assign buffer_auto_out_d_valid = bundleIn_0_a_valid & out_oready; // @[RegisterRouter.scala 83:24]
  assign buffer_auto_out_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign buffer_auto_out_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_data = {{24'd0}, _out_out_bits_data_T_4}; // @[RegisterRouter.scala 83:{24,24}]
  assign intsource_clock = clock;
  assign intsource_reset = reset;
  assign intsource_auto_in_0 = status_irqFlag & control_intEn; // @[I2C.scala 578:35]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = bundleIn_0_d_ready & out_oready; // @[RegisterRouter.scala 83:24]
  assign monitor_io_in_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_param = buffer_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_valid = bundleIn_0_a_valid & out_oready; // @[RegisterRouter.scala 83:24]
  assign monitor_io_in_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign monitor_io_in_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  always @(posedge clock) begin
    if (reset) begin // @[I2C.scala 125:25]
      prescaler_hi <= 8'hff; // @[I2C.scala 125:25]
    end else if (out_f_woready_1) begin // @[RegField.scala 74:88]
      prescaler_hi <= bundleIn_0_a_bits_data[7:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[I2C.scala 125:25]
      prescaler_lo <= 8'hff; // @[I2C.scala 125:25]
    end else if (out_f_woready) begin // @[RegField.scala 74:88]
      prescaler_lo <= bundleIn_0_a_bits_data[7:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[I2C.scala 126:25]
      control_coreEn <= 1'h0; // @[I2C.scala 126:25]
    end else if (out_f_woready_4) begin // @[RegField.scala 74:88]
      control_coreEn <= bundleIn_0_a_bits_data[7]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[I2C.scala 126:25]
      control_intEn <= 1'h0; // @[I2C.scala 126:25]
    end else if (out_f_woready_3) begin // @[RegField.scala 74:88]
      control_intEn <= bundleIn_0_a_bits_data[6]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[I2C.scala 127:25]
      transmitData <= 8'h0; // @[I2C.scala 127:25]
    end else if (out_f_woready_5) begin // @[RegField.scala 74:88]
      transmitData <= bundleIn_0_a_bits_data[7:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[I2C.scala 128:25]
      receivedData <= 8'h0; // @[I2C.scala 128:25]
    end else begin
      receivedData <= _GEN_117[7:0];
    end
    if (reset) begin // @[I2C.scala 129:25]
      cmd_start <= 1'h0; // @[I2C.scala 129:25]
    end else if (cmdAck | arbLost) begin // @[I2C.scala 511:28]
      cmd_start <= 1'h0; // @[I2C.scala 512:15]
    end else begin
      cmd_start <= nextCmd[7]; // @[I2C.scala 507:7]
    end
    if (reset) begin // @[I2C.scala 129:25]
      cmd_stop <= 1'h0; // @[I2C.scala 129:25]
    end else if (cmdAck | arbLost) begin // @[I2C.scala 511:28]
      cmd_stop <= 1'h0; // @[I2C.scala 513:15]
    end else begin
      cmd_stop <= nextCmd[6]; // @[I2C.scala 507:7]
    end
    if (reset) begin // @[I2C.scala 129:25]
      cmd_read <= 1'h0; // @[I2C.scala 129:25]
    end else if (cmdAck | arbLost) begin // @[I2C.scala 511:28]
      cmd_read <= 1'h0; // @[I2C.scala 514:15]
    end else begin
      cmd_read <= nextCmd[5]; // @[I2C.scala 507:7]
    end
    if (reset) begin // @[I2C.scala 129:25]
      cmd_write <= 1'h0; // @[I2C.scala 129:25]
    end else if (cmdAck | arbLost) begin // @[I2C.scala 511:28]
      cmd_write <= 1'h0; // @[I2C.scala 515:15]
    end else begin
      cmd_write <= nextCmd[4]; // @[I2C.scala 507:7]
    end
    if (reset) begin // @[I2C.scala 129:25]
      cmd_ack <= 1'h0; // @[I2C.scala 129:25]
    end else begin
      cmd_ack <= nextCmd[3]; // @[I2C.scala 507:7]
    end
    if (reset) begin // @[I2C.scala 129:25]
      cmd_irqAck <= 1'h0; // @[I2C.scala 129:25]
    end else begin
      cmd_irqAck <= nextCmd[0]; // @[I2C.scala 507:7]
    end
    if (reset) begin // @[I2C.scala 130:25]
      status_receivedAck <= 1'h0; // @[I2C.scala 130:25]
    end else begin
      status_receivedAck <= receivedAck; // @[I2C.scala 518:22]
    end
    if (reset) begin // @[I2C.scala 130:25]
      status_busy <= 1'h0; // @[I2C.scala 130:25]
    end else if (stopCond) begin // @[I2C.scala 519:19]
      status_busy <= 1'h0; // @[I2C.scala 520:29]
    end else begin
      status_busy <= _GEN_198;
    end
    if (reset) begin // @[I2C.scala 130:25]
      status_arbLost <= 1'h0; // @[I2C.scala 130:25]
    end else begin
      status_arbLost <= _GEN_201;
    end
    if (reset) begin // @[I2C.scala 130:25]
      status_transferInProgress <= 1'h0; // @[I2C.scala 130:25]
    end else begin
      status_transferInProgress <= _go_T; // @[I2C.scala 532:29]
    end
    if (reset) begin // @[I2C.scala 130:25]
      status_irqFlag <= 1'h0; // @[I2C.scala 130:25]
    end else begin
      status_irqFlag <= (_T_40 | status_irqFlag) & ~cmd_irqAck; // @[I2C.scala 533:29]
    end
    if (reset) begin // @[I2C.scala 139:22]
      filterCnt <= 14'h0; // @[I2C.scala 139:22]
    end else if (~control_coreEn) begin // @[I2C.scala 140:28]
      filterCnt <= 14'h0; // @[I2C.scala 141:15]
    end else if (~(|filterCnt)) begin // @[I2C.scala 142:34]
      filterCnt <= _filterCnt_T[15:2]; // @[I2C.scala 143:15]
    end else begin
      filterCnt <= _filterCnt_T_3; // @[I2C.scala 145:15]
    end
    if (reset) begin // @[I2C.scala 148:22]
      fSCL <= 3'h7; // @[I2C.scala 148:22]
    end else begin
      fSCL <= _GEN_2[2:0];
    end
    if (reset) begin // @[I2C.scala 149:22]
      fSDA <= 3'h7; // @[I2C.scala 149:22]
    end else begin
      fSDA <= _GEN_3[2:0];
    end
    sSCL <= reset | sSCL_x29; // @[I2C.scala 155:{22,22,22}]
    sSDA <= reset | sSDA_x32; // @[I2C.scala 156:{22,22,22}]
    dSCL <= reset | sSCL; // @[I2C.scala 158:{22,22,22}]
    dSDA <= reset | sSDA; // @[I2C.scala 159:{22,22,22}]
    dSCLOen <= ~sclOen; // @[I2C.scala 194:18]
    if (reset) begin // @[I2C.scala 165:22]
      startCond <= 1'h0; // @[I2C.scala 165:22]
    end else begin
      startCond <= startCond_x44; // @[I2C.scala 165:22]
    end
    if (reset) begin // @[I2C.scala 166:22]
      stopCond <= 1'h0; // @[I2C.scala 166:22]
    end else begin
      stopCond <= stopCond_x47; // @[I2C.scala 166:22]
    end
    sclOen <= reset | _GEN_111; // @[I2C.scala 193:{23,23}]
    if (reset) begin // @[I2C.scala 174:22]
      slaveWait <= 1'h0; // @[I2C.scala 174:22]
    end else begin
      slaveWait <= bundleOut_0_scl_oe & ~dSCLOen & _sclSync_T | slaveWait & _sclSync_T; // @[I2C.scala 175:13]
    end
    clkEn <= reset | _T_9; // @[I2C.scala 177:{22,22}]
    if (reset) begin // @[I2C.scala 178:22]
      cnt <= 16'h0; // @[I2C.scala 178:22]
    end else if (~(|cnt) | _T | sclSync) begin // @[I2C.scala 181:52]
      cnt <= _filterCnt_T; // @[I2C.scala 182:11]
    end else if (!(slaveWait)) begin // @[I2C.scala 185:25]
      cnt <= _cnt_T_2; // @[I2C.scala 189:11]
    end
    sdaOen <= reset | _GEN_112; // @[I2C.scala 196:{23,23}]
    if (reset) begin // @[I2C.scala 199:23]
      sdaChk <= 1'h0; // @[I2C.scala 199:23]
    end else if (arbLost) begin // @[I2C.scala 224:18]
      sdaChk <= 1'h0; // @[I2C.scala 229:15]
    end else if (clkEn) begin // @[I2C.scala 234:18]
      if (5'h0 == bitState) begin // @[I2C.scala 235:25]
        sdaChk <= 1'h0; // @[I2C.scala 243:18]
      end else begin
        sdaChk <= _GEN_97;
      end
    end
    if (reset) begin // @[I2C.scala 201:24]
      transmitBit <= 1'h0; // @[I2C.scala 201:24]
    end else if (arbLost) begin // @[I2C.scala 387:18]
      transmitBit <= 1'h0; // @[I2C.scala 389:17]
    end else if (3'h0 == byteState) begin // @[I2C.scala 402:24]
      transmitBit <= receivedData[7]; // @[I2C.scala 397:17]
    end else if (3'h1 == byteState) begin // @[I2C.scala 402:24]
      transmitBit <= receivedData[7]; // @[I2C.scala 397:17]
    end else begin
      transmitBit <= _GEN_170;
    end
    if (sSCL & ~dSCL) begin // @[I2C.scala 203:24]
      receivedBit <= sSDA; // @[I2C.scala 204:17]
    end
    if (reset) begin // @[I2C.scala 207:24]
      bitCmd <= 4'h0; // @[I2C.scala 207:24]
    end else if (arbLost) begin // @[I2C.scala 387:18]
      bitCmd <= 4'h0; // @[I2C.scala 388:17]
    end else if (3'h0 == byteState) begin // @[I2C.scala 402:24]
      if (go) begin // @[I2C.scala 404:19]
        bitCmd <= _GEN_123;
      end
    end else if (3'h1 == byteState) begin // @[I2C.scala 402:24]
      bitCmd <= _GEN_130;
    end else begin
      bitCmd <= _GEN_168;
    end
    if (reset) begin // @[I2C.scala 208:24]
      bitCmdStop <= 1'h0; // @[I2C.scala 208:24]
    end else if (clkEn) begin // @[I2C.scala 209:16]
      bitCmdStop <= bitCmd == 4'h2; // @[I2C.scala 210:16]
    end
    if (reset) begin // @[I2C.scala 212:24]
      bitCmdAck <= 1'h0; // @[I2C.scala 212:24]
    end else if (arbLost) begin // @[I2C.scala 224:18]
      bitCmdAck <= 1'h0; // @[I2C.scala 226:15]
    end else begin
      bitCmdAck <= _GEN_108;
    end
    if (reset) begin // @[I2C.scala 219:24]
      bitState <= 5'h0; // @[I2C.scala 219:24]
    end else if (arbLost) begin // @[I2C.scala 224:18]
      bitState <= 5'h0; // @[I2C.scala 225:15]
    end else if (clkEn) begin // @[I2C.scala 234:18]
      if (5'h0 == bitState) begin // @[I2C.scala 235:25]
        bitState <= _GEN_13;
      end else begin
        bitState <= _GEN_94;
      end
    end
    if (reset) begin // @[I2C.scala 221:24]
      arbLost <= 1'h0; // @[I2C.scala 221:24]
    end else begin
      arbLost <= arbLost_x83; // @[I2C.scala 221:24]
    end
    if (reset) begin // @[I2C.scala 361:24]
      load <= 1'h0; // @[I2C.scala 361:24]
    end else if (arbLost) begin // @[I2C.scala 387:18]
      load <= 1'h0; // @[I2C.scala 391:17]
    end else if (3'h0 == byteState) begin // @[I2C.scala 402:24]
      load <= go;
    end else begin
      load <= _GEN_175;
    end
    if (reset) begin // @[I2C.scala 362:24]
      shift <= 1'h0; // @[I2C.scala 362:24]
    end else if (arbLost) begin // @[I2C.scala 387:18]
      shift <= 1'h0; // @[I2C.scala 390:17]
    end else if (3'h0 == byteState) begin // @[I2C.scala 402:24]
      shift <= 1'h0; // @[I2C.scala 398:17]
    end else if (3'h1 == byteState) begin // @[I2C.scala 402:24]
      shift <= 1'h0; // @[I2C.scala 398:17]
    end else begin
      shift <= _GEN_169;
    end
    if (reset) begin // @[I2C.scala 363:24]
      cmdAck <= 1'h0; // @[I2C.scala 363:24]
    end else if (arbLost) begin // @[I2C.scala 387:18]
      cmdAck <= 1'h0; // @[I2C.scala 392:17]
    end else if (3'h0 == byteState) begin // @[I2C.scala 402:24]
      cmdAck <= 1'h0; // @[I2C.scala 400:17]
    end else if (3'h1 == byteState) begin // @[I2C.scala 402:24]
      cmdAck <= 1'h0; // @[I2C.scala 400:17]
    end else begin
      cmdAck <= _GEN_171;
    end
    if (reset) begin // @[I2C.scala 364:24]
      receivedAck <= 1'h0; // @[I2C.scala 364:24]
    end else if (arbLost) begin // @[I2C.scala 387:18]
      receivedAck <= 1'h0; // @[I2C.scala 394:17]
    end else if (!(3'h0 == byteState)) begin // @[I2C.scala 402:24]
      if (!(3'h1 == byteState)) begin // @[I2C.scala 402:24]
        receivedAck <= _GEN_172;
      end
    end
    if (reset) begin // @[I2C.scala 367:24]
      bitCnt <= 3'h0; // @[I2C.scala 367:24]
    end else if (load) begin // @[I2C.scala 368:15]
      bitCnt <= 3'h7; // @[I2C.scala 369:12]
    end else if (shift) begin // @[I2C.scala 371:21]
      bitCnt <= _bitCnt_T_1; // @[I2C.scala 372:12]
    end
    if (reset) begin // @[I2C.scala 385:24]
      byteState <= 3'h0; // @[I2C.scala 385:24]
    end else if (arbLost) begin // @[I2C.scala 387:18]
      byteState <= 3'h0; // @[I2C.scala 393:17]
    end else if (3'h0 == byteState) begin // @[I2C.scala 402:24]
      if (go) begin // @[I2C.scala 404:19]
        byteState <= _GEN_122;
      end
    end else if (3'h1 == byteState) begin // @[I2C.scala 402:24]
      byteState <= _GEN_129;
    end else begin
      byteState <= _GEN_167;
    end
    statusReadReady <= reset | _GEN_210; // @[I2C.scala 536:{28,28}]
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  prescaler_hi = _RAND_0[7:0];
  _RAND_1 = {1{`RANDOM}};
  prescaler_lo = _RAND_1[7:0];
  _RAND_2 = {1{`RANDOM}};
  control_coreEn = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  control_intEn = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  transmitData = _RAND_4[7:0];
  _RAND_5 = {1{`RANDOM}};
  receivedData = _RAND_5[7:0];
  _RAND_6 = {1{`RANDOM}};
  cmd_start = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  cmd_stop = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  cmd_read = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  cmd_write = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  cmd_ack = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  cmd_irqAck = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  status_receivedAck = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  status_busy = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  status_arbLost = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  status_transferInProgress = _RAND_15[0:0];
  _RAND_16 = {1{`RANDOM}};
  status_irqFlag = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  filterCnt = _RAND_17[13:0];
  _RAND_18 = {1{`RANDOM}};
  fSCL = _RAND_18[2:0];
  _RAND_19 = {1{`RANDOM}};
  fSDA = _RAND_19[2:0];
  _RAND_20 = {1{`RANDOM}};
  sSCL = _RAND_20[0:0];
  _RAND_21 = {1{`RANDOM}};
  sSDA = _RAND_21[0:0];
  _RAND_22 = {1{`RANDOM}};
  dSCL = _RAND_22[0:0];
  _RAND_23 = {1{`RANDOM}};
  dSDA = _RAND_23[0:0];
  _RAND_24 = {1{`RANDOM}};
  dSCLOen = _RAND_24[0:0];
  _RAND_25 = {1{`RANDOM}};
  startCond = _RAND_25[0:0];
  _RAND_26 = {1{`RANDOM}};
  stopCond = _RAND_26[0:0];
  _RAND_27 = {1{`RANDOM}};
  sclOen = _RAND_27[0:0];
  _RAND_28 = {1{`RANDOM}};
  slaveWait = _RAND_28[0:0];
  _RAND_29 = {1{`RANDOM}};
  clkEn = _RAND_29[0:0];
  _RAND_30 = {1{`RANDOM}};
  cnt = _RAND_30[15:0];
  _RAND_31 = {1{`RANDOM}};
  sdaOen = _RAND_31[0:0];
  _RAND_32 = {1{`RANDOM}};
  sdaChk = _RAND_32[0:0];
  _RAND_33 = {1{`RANDOM}};
  transmitBit = _RAND_33[0:0];
  _RAND_34 = {1{`RANDOM}};
  receivedBit = _RAND_34[0:0];
  _RAND_35 = {1{`RANDOM}};
  bitCmd = _RAND_35[3:0];
  _RAND_36 = {1{`RANDOM}};
  bitCmdStop = _RAND_36[0:0];
  _RAND_37 = {1{`RANDOM}};
  bitCmdAck = _RAND_37[0:0];
  _RAND_38 = {1{`RANDOM}};
  bitState = _RAND_38[4:0];
  _RAND_39 = {1{`RANDOM}};
  arbLost = _RAND_39[0:0];
  _RAND_40 = {1{`RANDOM}};
  load = _RAND_40[0:0];
  _RAND_41 = {1{`RANDOM}};
  shift = _RAND_41[0:0];
  _RAND_42 = {1{`RANDOM}};
  cmdAck = _RAND_42[0:0];
  _RAND_43 = {1{`RANDOM}};
  receivedAck = _RAND_43[0:0];
  _RAND_44 = {1{`RANDOM}};
  bitCnt = _RAND_44[2:0];
  _RAND_45 = {1{`RANDOM}};
  byteState = _RAND_45[2:0];
  _RAND_46 = {1{`RANDOM}};
  statusReadReady = _RAND_46[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ClockSinkDomain_13(
  output        auto_i2c_0_int_xing_out_sync_0,
  output        auto_i2c_0_control_xing_in_a_ready,
  input         auto_i2c_0_control_xing_in_a_valid,
  input  [2:0]  auto_i2c_0_control_xing_in_a_bits_opcode,
  input  [2:0]  auto_i2c_0_control_xing_in_a_bits_param,
  input  [1:0]  auto_i2c_0_control_xing_in_a_bits_size,
  input  [6:0]  auto_i2c_0_control_xing_in_a_bits_source,
  input  [28:0] auto_i2c_0_control_xing_in_a_bits_address,
  input  [3:0]  auto_i2c_0_control_xing_in_a_bits_mask,
  input  [31:0] auto_i2c_0_control_xing_in_a_bits_data,
  input         auto_i2c_0_control_xing_in_a_bits_corrupt,
  input         auto_i2c_0_control_xing_in_d_ready,
  output        auto_i2c_0_control_xing_in_d_valid,
  output [2:0]  auto_i2c_0_control_xing_in_d_bits_opcode,
  output [1:0]  auto_i2c_0_control_xing_in_d_bits_size,
  output [6:0]  auto_i2c_0_control_xing_in_d_bits_source,
  output [31:0] auto_i2c_0_control_xing_in_d_bits_data,
  input         auto_i2c_0_io_out_scl_in,
  output        auto_i2c_0_io_out_scl_oe,
  input         auto_i2c_0_io_out_sda_in,
  output        auto_i2c_0_io_out_sda_oe,
  input         auto_clock_in_clock,
  input         auto_clock_in_reset
);
  wire  i2c_0_clock; // @[I2C.scala 597:49]
  wire  i2c_0_reset; // @[I2C.scala 597:49]
  wire  i2c_0_auto_int_xing_out_sync_0; // @[I2C.scala 597:49]
  wire  i2c_0_auto_control_xing_in_a_ready; // @[I2C.scala 597:49]
  wire  i2c_0_auto_control_xing_in_a_valid; // @[I2C.scala 597:49]
  wire [2:0] i2c_0_auto_control_xing_in_a_bits_opcode; // @[I2C.scala 597:49]
  wire [2:0] i2c_0_auto_control_xing_in_a_bits_param; // @[I2C.scala 597:49]
  wire [1:0] i2c_0_auto_control_xing_in_a_bits_size; // @[I2C.scala 597:49]
  wire [6:0] i2c_0_auto_control_xing_in_a_bits_source; // @[I2C.scala 597:49]
  wire [28:0] i2c_0_auto_control_xing_in_a_bits_address; // @[I2C.scala 597:49]
  wire [3:0] i2c_0_auto_control_xing_in_a_bits_mask; // @[I2C.scala 597:49]
  wire [31:0] i2c_0_auto_control_xing_in_a_bits_data; // @[I2C.scala 597:49]
  wire  i2c_0_auto_control_xing_in_a_bits_corrupt; // @[I2C.scala 597:49]
  wire  i2c_0_auto_control_xing_in_d_ready; // @[I2C.scala 597:49]
  wire  i2c_0_auto_control_xing_in_d_valid; // @[I2C.scala 597:49]
  wire [2:0] i2c_0_auto_control_xing_in_d_bits_opcode; // @[I2C.scala 597:49]
  wire [1:0] i2c_0_auto_control_xing_in_d_bits_size; // @[I2C.scala 597:49]
  wire [6:0] i2c_0_auto_control_xing_in_d_bits_source; // @[I2C.scala 597:49]
  wire [31:0] i2c_0_auto_control_xing_in_d_bits_data; // @[I2C.scala 597:49]
  wire  i2c_0_auto_io_out_scl_in; // @[I2C.scala 597:49]
  wire  i2c_0_auto_io_out_scl_oe; // @[I2C.scala 597:49]
  wire  i2c_0_auto_io_out_sda_in; // @[I2C.scala 597:49]
  wire  i2c_0_auto_io_out_sda_oe; // @[I2C.scala 597:49]
  TLI2C i2c_0 ( // @[I2C.scala 597:49]
    .clock(i2c_0_clock),
    .reset(i2c_0_reset),
    .auto_int_xing_out_sync_0(i2c_0_auto_int_xing_out_sync_0),
    .auto_control_xing_in_a_ready(i2c_0_auto_control_xing_in_a_ready),
    .auto_control_xing_in_a_valid(i2c_0_auto_control_xing_in_a_valid),
    .auto_control_xing_in_a_bits_opcode(i2c_0_auto_control_xing_in_a_bits_opcode),
    .auto_control_xing_in_a_bits_param(i2c_0_auto_control_xing_in_a_bits_param),
    .auto_control_xing_in_a_bits_size(i2c_0_auto_control_xing_in_a_bits_size),
    .auto_control_xing_in_a_bits_source(i2c_0_auto_control_xing_in_a_bits_source),
    .auto_control_xing_in_a_bits_address(i2c_0_auto_control_xing_in_a_bits_address),
    .auto_control_xing_in_a_bits_mask(i2c_0_auto_control_xing_in_a_bits_mask),
    .auto_control_xing_in_a_bits_data(i2c_0_auto_control_xing_in_a_bits_data),
    .auto_control_xing_in_a_bits_corrupt(i2c_0_auto_control_xing_in_a_bits_corrupt),
    .auto_control_xing_in_d_ready(i2c_0_auto_control_xing_in_d_ready),
    .auto_control_xing_in_d_valid(i2c_0_auto_control_xing_in_d_valid),
    .auto_control_xing_in_d_bits_opcode(i2c_0_auto_control_xing_in_d_bits_opcode),
    .auto_control_xing_in_d_bits_size(i2c_0_auto_control_xing_in_d_bits_size),
    .auto_control_xing_in_d_bits_source(i2c_0_auto_control_xing_in_d_bits_source),
    .auto_control_xing_in_d_bits_data(i2c_0_auto_control_xing_in_d_bits_data),
    .auto_io_out_scl_in(i2c_0_auto_io_out_scl_in),
    .auto_io_out_scl_oe(i2c_0_auto_io_out_scl_oe),
    .auto_io_out_sda_in(i2c_0_auto_io_out_sda_in),
    .auto_io_out_sda_oe(i2c_0_auto_io_out_sda_oe)
  );
  assign auto_i2c_0_int_xing_out_sync_0 = i2c_0_auto_int_xing_out_sync_0; // @[LazyModule.scala 311:12]
  assign auto_i2c_0_control_xing_in_a_ready = i2c_0_auto_control_xing_in_a_ready; // @[LazyModule.scala 309:16]
  assign auto_i2c_0_control_xing_in_d_valid = i2c_0_auto_control_xing_in_d_valid; // @[LazyModule.scala 309:16]
  assign auto_i2c_0_control_xing_in_d_bits_opcode = i2c_0_auto_control_xing_in_d_bits_opcode; // @[LazyModule.scala 309:16]
  assign auto_i2c_0_control_xing_in_d_bits_size = i2c_0_auto_control_xing_in_d_bits_size; // @[LazyModule.scala 309:16]
  assign auto_i2c_0_control_xing_in_d_bits_source = i2c_0_auto_control_xing_in_d_bits_source; // @[LazyModule.scala 309:16]
  assign auto_i2c_0_control_xing_in_d_bits_data = i2c_0_auto_control_xing_in_d_bits_data; // @[LazyModule.scala 309:16]
  assign auto_i2c_0_io_out_scl_oe = i2c_0_auto_io_out_scl_oe; // @[LazyModule.scala 311:12]
  assign auto_i2c_0_io_out_sda_oe = i2c_0_auto_io_out_sda_oe; // @[LazyModule.scala 311:12]
  assign i2c_0_clock = auto_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign i2c_0_reset = auto_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign i2c_0_auto_control_xing_in_a_valid = auto_i2c_0_control_xing_in_a_valid; // @[LazyModule.scala 309:16]
  assign i2c_0_auto_control_xing_in_a_bits_opcode = auto_i2c_0_control_xing_in_a_bits_opcode; // @[LazyModule.scala 309:16]
  assign i2c_0_auto_control_xing_in_a_bits_param = auto_i2c_0_control_xing_in_a_bits_param; // @[LazyModule.scala 309:16]
  assign i2c_0_auto_control_xing_in_a_bits_size = auto_i2c_0_control_xing_in_a_bits_size; // @[LazyModule.scala 309:16]
  assign i2c_0_auto_control_xing_in_a_bits_source = auto_i2c_0_control_xing_in_a_bits_source; // @[LazyModule.scala 309:16]
  assign i2c_0_auto_control_xing_in_a_bits_address = auto_i2c_0_control_xing_in_a_bits_address; // @[LazyModule.scala 309:16]
  assign i2c_0_auto_control_xing_in_a_bits_mask = auto_i2c_0_control_xing_in_a_bits_mask; // @[LazyModule.scala 309:16]
  assign i2c_0_auto_control_xing_in_a_bits_data = auto_i2c_0_control_xing_in_a_bits_data; // @[LazyModule.scala 309:16]
  assign i2c_0_auto_control_xing_in_a_bits_corrupt = auto_i2c_0_control_xing_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
  assign i2c_0_auto_control_xing_in_d_ready = auto_i2c_0_control_xing_in_d_ready; // @[LazyModule.scala 309:16]
  assign i2c_0_auto_io_out_scl_in = auto_i2c_0_io_out_scl_in; // @[LazyModule.scala 311:12]
  assign i2c_0_auto_io_out_sda_in = auto_i2c_0_io_out_sda_in; // @[LazyModule.scala 311:12]
endmodule
module TLMonitor_71(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [1:0]  io_in_a_bits_size,
  input  [6:0]  io_in_a_bits_source,
  input  [28:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [2:0]  io_in_d_bits_opcode,
  input  [1:0]  io_in_d_bits_size,
  input  [6:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [95:0] _RAND_10;
  reg [383:0] _RAND_11;
  reg [383:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [95:0] _RAND_16;
  reg [383:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T_4 = io_in_a_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire [4:0] _is_aligned_mask_T_1 = 5'h3 << io_in_a_bits_size; // @[package.scala 234:77]
  wire [1:0] is_aligned_mask = ~_is_aligned_mask_T_1[1:0]; // @[package.scala 234:46]
  wire [28:0] _GEN_71 = {{27'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [28:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 2'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [28:0] _T_33 = io_in_a_bits_address ^ 29'h10026000; // @[Parameters.scala 137:31]
  wire [29:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
  wire [29:0] _T_36 = $signed(_T_34) & -30'sh1000; // @[Parameters.scala 137:52]
  wire  _T_37 = $signed(_T_36) == 30'sh0; // @[Parameters.scala 137:67]
  wire  _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_74 = _T_73 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_164 = io_in_a_bits_size <= 2'h2; // @[Parameters.scala 92:42]
  wire  _T_172 = _T_164 & _T_37; // @[Parameters.scala 670:56]
  wire  _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_218 = _source_ok_T_4 & _T_172; // @[Monitor.scala 115:71]
  wire  _T_236 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_273 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_274 = io_in_a_bits_mask & _T_273; // @[Monitor.scala 127:31]
  wire  _T_275 = _T_274 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_279 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_309 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_317 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_347 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_355 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_385 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _T_397 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 42:24]
  wire  _source_ok_T_10 = io_in_d_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire  _T_401 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 310:25]
  wire  _T_405 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 312:27]
  wire  _T_421 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 318:25]
  wire  _T_449 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 328:25]
  wire  _T_478 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 338:25]
  wire  _T_495 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 346:25]
  wire  _T_513 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 354:25]
  wire  a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [1:0] size; // @[Monitor.scala 386:22]
  reg [6:0] source; // @[Monitor.scala 387:22]
  reg [28:0] address; // @[Monitor.scala 388:22]
  wire  _T_543 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_544 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_548 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_552 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_556 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_560 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode_1; // @[Monitor.scala 535:22]
  reg [1:0] size_1; // @[Monitor.scala 537:22]
  reg [6:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_567 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_568 = io_in_d_bits_opcode == opcode_1; // @[Monitor.scala 542:29]
  wire  _T_576 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_580 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [95:0] inflight; // @[Monitor.scala 611:27]
  reg [383:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [383:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [8:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [9:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [383:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [383:0] _GEN_73 = {{368'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[383:1]}; // @[Monitor.scala 634:152]
  wire [383:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [383:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
  wire [383:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[383:1]}; // @[Monitor.scala 638:144]
  wire  _T_594 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [127:0] _a_set_wo_ready_T = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_597 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
  wire [8:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [9:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [1026:0] _GEN_1 = {{1023'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [1026:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
  wire [1025:0] _GEN_2 = {{1023'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [1025:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [95:0] _T_599 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_601 = ~_T_599[0]; // @[Monitor.scala 658:17]
  wire [127:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 652:72 653:28]
  wire [1026:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 1027'h0; // @[Monitor.scala 652:72 656:28]
  wire [1025:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 1026'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_605 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire  _T_607 = ~_T_401; // @[Monitor.scala 671:74]
  wire  _T_608 = io_in_d_valid & d_first_1 & ~_T_401; // @[Monitor.scala 671:71]
  wire [127:0] _d_clr_wo_ready_T = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [1038:0] _GEN_3 = {{1023'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [1038:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [127:0] _GEN_22 = d_first_done & d_first_1 & _T_607 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 675:91 676:21]
  wire [1038:0] _GEN_23 = d_first_done & d_first_1 & _T_607 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_594 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [95:0] _T_618 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_620 = _T_618[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_625 = io_in_d_bits_opcode == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_626 = io_in_d_bits_opcode == _GEN_32 | _T_625; // @[Monitor.scala 685:77]
  wire  _T_630 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_637 = io_in_d_bits_opcode == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_638 = io_in_d_bits_opcode == _GEN_48 | _T_637; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_642 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_652 = _T_605 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2 & _T_607; // @[Monitor.scala 694:116]
  wire  _T_654 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [95:0] a_set = _GEN_16[95:0];
  wire [95:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [95:0] d_clr = _GEN_22[95:0];
  wire [95:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [95:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [383:0] a_opcodes_set = _GEN_19[383:0];
  wire [383:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [383:0] d_opcodes_clr = _GEN_23[383:0];
  wire [383:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [383:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [383:0] a_sizes_set = _GEN_20[383:0];
  wire [383:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [383:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_663 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  reg [95:0] inflight_1; // @[Monitor.scala 723:35]
  reg [383:0] inflight_sizes_1; // @[Monitor.scala 725:35]
  reg  d_first_counter_2; // @[Edges.scala 228:27]
  wire  d_first_counter1_2 = d_first_counter_2 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_2 = ~d_first_counter_2; // @[Edges.scala 230:25]
  wire [383:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _a_opcode_lookup_T; // @[Monitor.scala 747:42]
  wire [383:0] _c_size_lookup_T_6 = _c_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 747:93]
  wire [383:0] _c_size_lookup_T_7 = {{1'd0}, _c_size_lookup_T_6[383:1]}; // @[Monitor.scala 747:146]
  wire  _T_689 = io_in_d_valid & d_first_2 & _T_401; // @[Monitor.scala 779:71]
  wire [127:0] _GEN_67 = d_first_done & d_first_2 & _T_401 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 783:90 784:21]
  wire [1038:0] _GEN_68 = d_first_done & d_first_2 & _T_401 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 783:90 785:21]
  wire [95:0] _T_697 = inflight_1 >> io_in_d_bits_source; // @[Monitor.scala 791:25]
  wire [3:0] c_size_lookup = _c_size_lookup_T_7[3:0];
  wire  _T_707 = _GEN_82 == c_size_lookup; // @[Monitor.scala 795:36]
  wire [95:0] d_clr_1 = _GEN_67[95:0];
  wire [95:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala 809:46]
  wire [95:0] _inflight_T_5 = inflight_1 & _inflight_T_4; // @[Monitor.scala 809:44]
  wire [383:0] d_opcodes_clr_1 = _GEN_68[383:0];
  wire [383:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala 810:62]
  wire [383:0] _inflight_sizes_T_5 = inflight_sizes_1 & _inflight_opcodes_T_4; // @[Monitor.scala 811:56]
  reg [31:0] watchdog_1; // @[Monitor.scala 813:27]
  wire  _T_727 = ~(|inflight_1) | plusarg_reader_1_out == 32'h0 | watchdog_1 < plusarg_reader_1_out; // @[Monitor.scala 816:47]
  wire [31:0] _watchdog_T_3 = watchdog_1 + 32'h1; // @[Monitor.scala 818:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 1'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= 1'h0;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      opcode_1 <= io_in_d_bits_opcode; // @[Monitor.scala 550:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 96'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 384'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 384'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 1'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= 1'h0;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    if (reset) begin // @[Monitor.scala 723:35]
      inflight_1 <= 96'h0; // @[Monitor.scala 723:35]
    end else begin
      inflight_1 <= _inflight_T_5; // @[Monitor.scala 809:22]
    end
    if (reset) begin // @[Monitor.scala 725:35]
      inflight_sizes_1 <= 384'h0; // @[Monitor.scala 725:35]
    end else begin
      inflight_sizes_1 <= _inflight_sizes_T_5; // @[Monitor.scala 811:22]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_2 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_2) begin // @[Edges.scala 235:21]
        d_first_counter_2 <= 1'h0;
      end else begin
        d_first_counter_2 <= d_first_counter1_2;
      end
    end
    if (reset) begin // @[Monitor.scala 813:27]
      watchdog_1 <= 32'h0; // @[Monitor.scala 813:27]
    end else if (d_first_done) begin // @[Monitor.scala 819:47]
      watchdog_1 <= 32'h0; // @[Monitor.scala 819:58]
    end else begin
      watchdog_1 <= _watchdog_T_3; // @[Monitor.scala 818:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_172 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_172) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_218 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_218) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_275 & (io_in_a_valid & _T_236 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_236 & ~reset & ~_T_275) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_309 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_309) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_279 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_279 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_347 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_347) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_317 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_317 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_385 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_385) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_355 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_355 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_397 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_T_397) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel has invalid opcode (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_401 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_401 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_421 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_421 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel Grant smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_405 & (io_in_d_valid & _T_449 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_449 & _T_2 & ~_T_405) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel GrantData smaller than a beat (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_478 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_478 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_495 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_495 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_513 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_513 & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_544 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_544) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_548 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_548) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_552 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_552) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_556 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_556) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_560 & (_T_543 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_543 & ~reset & ~_T_560) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_568 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_568) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_576 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_576) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_580 & (_T_567 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_567 & _T_2 & ~_T_580) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_601 & (_T_597 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_597 & ~reset & ~_T_601) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_620 & (_T_608 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & _T_2 & ~_T_620) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_626 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_626) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_630 & (_T_608 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & same_cycle_resp & _T_2 & ~_T_630) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_638 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_638) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_642 & (_T_608 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_608 & ~same_cycle_resp & _T_2 & ~_T_642) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_654 & (_T_652 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_652 & _T_2 & ~_T_654) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_663 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_663) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_697[0] & (_T_689 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_689 & _T_2 & ~_T_697[0]) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_707 & (_T_689 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_689 & _T_2 & ~_T_707) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_727 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_727) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:14)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[6:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[28:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  opcode_1 = _RAND_7[2:0];
  _RAND_8 = {1{`RANDOM}};
  size_1 = _RAND_8[1:0];
  _RAND_9 = {1{`RANDOM}};
  source_1 = _RAND_9[6:0];
  _RAND_10 = {3{`RANDOM}};
  inflight = _RAND_10[95:0];
  _RAND_11 = {12{`RANDOM}};
  inflight_opcodes = _RAND_11[383:0];
  _RAND_12 = {12{`RANDOM}};
  inflight_sizes = _RAND_12[383:0];
  _RAND_13 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  watchdog = _RAND_15[31:0];
  _RAND_16 = {3{`RANDOM}};
  inflight_1 = _RAND_16[95:0];
  _RAND_17 = {12{`RANDOM}};
  inflight_sizes_1 = _RAND_17[383:0];
  _RAND_18 = {1{`RANDOM}};
  d_first_counter_2 = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  watchdog_1 = _RAND_19[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLI2C_1(
  input         clock,
  input         reset,
  output        auto_int_xing_out_sync_0,
  output        auto_control_xing_in_a_ready,
  input         auto_control_xing_in_a_valid,
  input  [2:0]  auto_control_xing_in_a_bits_opcode,
  input  [2:0]  auto_control_xing_in_a_bits_param,
  input  [1:0]  auto_control_xing_in_a_bits_size,
  input  [6:0]  auto_control_xing_in_a_bits_source,
  input  [28:0] auto_control_xing_in_a_bits_address,
  input  [3:0]  auto_control_xing_in_a_bits_mask,
  input  [31:0] auto_control_xing_in_a_bits_data,
  input         auto_control_xing_in_a_bits_corrupt,
  input         auto_control_xing_in_d_ready,
  output        auto_control_xing_in_d_valid,
  output [2:0]  auto_control_xing_in_d_bits_opcode,
  output [1:0]  auto_control_xing_in_d_bits_size,
  output [6:0]  auto_control_xing_in_d_bits_source,
  output [31:0] auto_control_xing_in_d_bits_data,
  input         auto_io_out_scl_in,
  output        auto_io_out_scl_oe,
  input         auto_io_out_sda_in,
  output        auto_io_out_sda_oe
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [31:0] _RAND_33;
  reg [31:0] _RAND_34;
  reg [31:0] _RAND_35;
  reg [31:0] _RAND_36;
  reg [31:0] _RAND_37;
  reg [31:0] _RAND_38;
  reg [31:0] _RAND_39;
  reg [31:0] _RAND_40;
  reg [31:0] _RAND_41;
  reg [31:0] _RAND_42;
  reg [31:0] _RAND_43;
  reg [31:0] _RAND_44;
  reg [31:0] _RAND_45;
  reg [31:0] _RAND_46;
`endif // RANDOMIZE_REG_INIT
  wire  buffer_auto_in_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 68:28]
  wire [28:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_in_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 68:28]
  wire [28:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 68:28]
  wire [3:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_ready; // @[Buffer.scala 68:28]
  wire  buffer_auto_out_d_valid; // @[Buffer.scala 68:28]
  wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 68:28]
  wire [1:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 68:28]
  wire [6:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 68:28]
  wire [31:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 68:28]
  wire  intsource_clock; // @[Crossing.scala 26:31]
  wire  intsource_reset; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_0; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_0; // @[Crossing.scala 26:31]
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [28:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_d_bits_opcode; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  reg [7:0] prescaler_hi; // @[I2C.scala 125:25]
  reg [7:0] prescaler_lo; // @[I2C.scala 125:25]
  reg  control_coreEn; // @[I2C.scala 126:25]
  reg  control_intEn; // @[I2C.scala 126:25]
  reg [7:0] transmitData; // @[I2C.scala 127:25]
  reg [7:0] receivedData; // @[I2C.scala 128:25]
  reg  cmd_start; // @[I2C.scala 129:25]
  reg  cmd_stop; // @[I2C.scala 129:25]
  reg  cmd_read; // @[I2C.scala 129:25]
  reg  cmd_write; // @[I2C.scala 129:25]
  reg  cmd_ack; // @[I2C.scala 129:25]
  reg  cmd_irqAck; // @[I2C.scala 129:25]
  reg  status_receivedAck; // @[I2C.scala 130:25]
  reg  status_busy; // @[I2C.scala 130:25]
  reg  status_arbLost; // @[I2C.scala 130:25]
  reg  status_transferInProgress; // @[I2C.scala 130:25]
  reg  status_irqFlag; // @[I2C.scala 130:25]
  reg [13:0] filterCnt; // @[I2C.scala 139:22]
  wire  _T = ~control_coreEn; // @[I2C.scala 140:10]
  wire  _T_2 = ~(|filterCnt); // @[I2C.scala 142:16]
  wire [15:0] _filterCnt_T = {prescaler_hi,prescaler_lo}; // @[Cat.scala 31:58]
  wire [13:0] _filterCnt_T_3 = filterCnt - 14'h1; // @[I2C.scala 145:28]
  reg [2:0] fSCL; // @[I2C.scala 148:22]
  reg [2:0] fSDA; // @[I2C.scala 149:22]
  wire [3:0] _fSCL_T = {fSCL,auto_io_out_scl_in}; // @[Cat.scala 31:58]
  wire [3:0] _fSDA_T = {fSDA,auto_io_out_sda_in}; // @[Cat.scala 31:58]
  wire [3:0] _GEN_2 = _T_2 ? _fSCL_T : {{1'd0}, fSCL}; // @[I2C.scala 150:27 151:10 148:22]
  wire [3:0] _GEN_3 = _T_2 ? _fSDA_T : {{1'd0}, fSDA}; // @[I2C.scala 150:27 152:10 149:22]
  wire  _sSCL_x29_T_3 = fSCL[0] & fSCL[1]; // @[Misc.scala 166:48]
  wire  _sSCL_x29_T_4 = fSCL[0] & fSCL[2]; // @[Misc.scala 166:48]
  wire  _sSCL_x29_T_6 = fSCL[1] & fSCL[2]; // @[Misc.scala 166:48]
  wire  sSCL_x29 = _sSCL_x29_T_3 | _sSCL_x29_T_4 | _sSCL_x29_T_6; // @[Misc.scala 167:22]
  reg  sSCL; // @[I2C.scala 155:22]
  wire  _sSDA_x32_T_3 = fSDA[0] & fSDA[1]; // @[Misc.scala 166:48]
  wire  _sSDA_x32_T_4 = fSDA[0] & fSDA[2]; // @[Misc.scala 166:48]
  wire  _sSDA_x32_T_6 = fSDA[1] & fSDA[2]; // @[Misc.scala 166:48]
  wire  sSDA_x32 = _sSDA_x32_T_3 | _sSDA_x32_T_4 | _sSDA_x32_T_6; // @[Misc.scala 167:22]
  reg  sSDA; // @[I2C.scala 156:22]
  reg  dSCL; // @[I2C.scala 158:22]
  reg  dSDA; // @[I2C.scala 159:22]
  reg  dSCLOen; // @[I2C.scala 161:22]
  wire  _startCond_x44_T = ~sSDA; // @[I2C.scala 165:46]
  wire  startCond_x44 = ~sSDA & dSDA & sSCL; // @[I2C.scala 165:61]
  reg  startCond; // @[I2C.scala 165:22]
  wire  stopCond_x47 = sSDA & ~dSDA & sSCL; // @[I2C.scala 166:61]
  reg  stopCond; // @[I2C.scala 166:22]
  wire  _sclSync_T = ~sSCL; // @[I2C.scala 170:27]
  reg  sclOen; // @[I2C.scala 193:23]
  wire  bundleOut_0_scl_oe = ~sclOen; // @[I2C.scala 194:18]
  wire  sclSync = dSCL & ~sSCL & bundleOut_0_scl_oe; // @[I2C.scala 170:33]
  reg  slaveWait; // @[I2C.scala 174:22]
  reg  clkEn; // @[I2C.scala 177:22]
  reg [15:0] cnt; // @[I2C.scala 178:22]
  wire  _T_9 = ~(|cnt) | _T | sclSync; // @[I2C.scala 181:39]
  wire [15:0] _cnt_T_2 = cnt - 16'h1; // @[I2C.scala 189:18]
  reg  sdaOen; // @[I2C.scala 196:23]
  reg  sdaChk; // @[I2C.scala 199:23]
  reg  transmitBit; // @[I2C.scala 201:24]
  reg  receivedBit; // @[I2C.scala 202:24]
  reg [3:0] bitCmd; // @[I2C.scala 207:24]
  reg  bitCmdStop; // @[I2C.scala 208:24]
  reg  bitCmdAck; // @[I2C.scala 212:24]
  reg [4:0] bitState; // @[I2C.scala 219:24]
  wire  arbLost_x83 = sdaChk & _startCond_x44_T & sdaOen | bitState != 5'h0 & stopCond & ~bitCmdStop; // @[I2C.scala 221:76]
  reg  arbLost; // @[I2C.scala 221:24]
  wire [4:0] _GEN_10 = 4'h8 == bitCmd ? 5'ha : bitState; // @[I2C.scala 219:24 237:27 241:43]
  wire [4:0] _GEN_11 = 4'h4 == bitCmd ? 5'he : _GEN_10; // @[I2C.scala 237:27 240:43]
  wire [4:0] _GEN_12 = 4'h2 == bitCmd ? 5'h6 : _GEN_11; // @[I2C.scala 237:27 239:43]
  wire [4:0] _GEN_13 = 4'h1 == bitCmd ? 5'h1 : _GEN_12; // @[I2C.scala 237:27 238:43]
  wire [4:0] _GEN_14 = 5'h11 == bitState ? 5'h0 : bitState; // @[I2C.scala 235:25 349:21 219:24]
  wire  _GEN_16 = 5'h11 == bitState ? 1'h0 : sclOen; // @[I2C.scala 235:25 351:21 193:23]
  wire  _GEN_17 = 5'h11 == bitState ? transmitBit : sdaOen; // @[I2C.scala 235:25 352:21 196:23]
  wire  _GEN_18 = 5'h11 == bitState ? 1'h0 : sdaChk; // @[I2C.scala 235:25 353:21 199:23]
  wire [4:0] _GEN_19 = 5'h10 == bitState ? 5'h11 : _GEN_14; // @[I2C.scala 235:25 343:21]
  wire  _GEN_20 = 5'h10 == bitState | _GEN_16; // @[I2C.scala 235:25 344:21]
  wire  _GEN_21 = 5'h10 == bitState ? transmitBit : _GEN_17; // @[I2C.scala 235:25 345:21]
  wire  _GEN_22 = 5'h10 == bitState | _GEN_18; // @[I2C.scala 235:25 346:21]
  wire  _GEN_23 = 5'h10 == bitState ? 1'h0 : 5'h11 == bitState; // @[I2C.scala 232:15 235:25]
  wire [4:0] _GEN_24 = 5'hf == bitState ? 5'h10 : _GEN_19; // @[I2C.scala 235:25 337:21]
  wire  _GEN_25 = 5'hf == bitState | _GEN_20; // @[I2C.scala 235:25 338:21]
  wire  _GEN_26 = 5'hf == bitState ? transmitBit : _GEN_21; // @[I2C.scala 235:25 339:21]
  wire  _GEN_27 = 5'hf == bitState ? 1'h0 : _GEN_22; // @[I2C.scala 235:25 340:21]
  wire  _GEN_28 = 5'hf == bitState ? 1'h0 : _GEN_23; // @[I2C.scala 232:15 235:25]
  wire [4:0] _GEN_29 = 5'he == bitState ? 5'hf : _GEN_24; // @[I2C.scala 235:25 331:21]
  wire  _GEN_30 = 5'he == bitState ? 1'h0 : _GEN_25; // @[I2C.scala 235:25 332:21]
  wire  _GEN_31 = 5'he == bitState ? transmitBit : _GEN_26; // @[I2C.scala 235:25 333:21]
  wire  _GEN_32 = 5'he == bitState ? 1'h0 : _GEN_27; // @[I2C.scala 235:25 334:21]
  wire  _GEN_33 = 5'he == bitState ? 1'h0 : _GEN_28; // @[I2C.scala 232:15 235:25]
  wire [4:0] _GEN_34 = 5'hd == bitState ? 5'h0 : _GEN_29; // @[I2C.scala 235:25 323:21]
  wire  _GEN_35 = 5'hd == bitState | _GEN_33; // @[I2C.scala 235:25 324:21]
  wire  _GEN_36 = 5'hd == bitState ? 1'h0 : _GEN_30; // @[I2C.scala 235:25 325:21]
  wire  _GEN_37 = 5'hd == bitState | _GEN_31; // @[I2C.scala 235:25 326:21]
  wire  _GEN_38 = 5'hd == bitState ? 1'h0 : _GEN_32; // @[I2C.scala 235:25 327:21]
  wire [4:0] _GEN_39 = 5'hc == bitState ? 5'hd : _GEN_34; // @[I2C.scala 235:25 317:21]
  wire  _GEN_40 = 5'hc == bitState | _GEN_36; // @[I2C.scala 235:25 318:21]
  wire  _GEN_41 = 5'hc == bitState | _GEN_37; // @[I2C.scala 235:25 319:21]
  wire  _GEN_42 = 5'hc == bitState ? 1'h0 : _GEN_38; // @[I2C.scala 235:25 320:21]
  wire  _GEN_43 = 5'hc == bitState ? 1'h0 : _GEN_35; // @[I2C.scala 232:15 235:25]
  wire [4:0] _GEN_44 = 5'hb == bitState ? 5'hc : _GEN_39; // @[I2C.scala 235:25 311:21]
  wire  _GEN_45 = 5'hb == bitState | _GEN_40; // @[I2C.scala 235:25 312:21]
  wire  _GEN_46 = 5'hb == bitState | _GEN_41; // @[I2C.scala 235:25 313:21]
  wire  _GEN_47 = 5'hb == bitState ? 1'h0 : _GEN_42; // @[I2C.scala 235:25 314:21]
  wire  _GEN_48 = 5'hb == bitState ? 1'h0 : _GEN_43; // @[I2C.scala 232:15 235:25]
  wire [4:0] _GEN_49 = 5'ha == bitState ? 5'hb : _GEN_44; // @[I2C.scala 235:25 305:21]
  wire  _GEN_50 = 5'ha == bitState ? 1'h0 : _GEN_45; // @[I2C.scala 235:25 306:21]
  wire  _GEN_51 = 5'ha == bitState | _GEN_46; // @[I2C.scala 235:25 307:21]
  wire  _GEN_52 = 5'ha == bitState ? 1'h0 : _GEN_47; // @[I2C.scala 235:25 308:21]
  wire  _GEN_53 = 5'ha == bitState ? 1'h0 : _GEN_48; // @[I2C.scala 232:15 235:25]
  wire [4:0] _GEN_54 = 5'h9 == bitState ? 5'h0 : _GEN_49; // @[I2C.scala 235:25 297:21]
  wire  _GEN_55 = 5'h9 == bitState | _GEN_53; // @[I2C.scala 235:25 298:21]
  wire  _GEN_56 = 5'h9 == bitState | _GEN_50; // @[I2C.scala 235:25 299:21]
  wire  _GEN_57 = 5'h9 == bitState | _GEN_51; // @[I2C.scala 235:25 300:21]
  wire  _GEN_58 = 5'h9 == bitState ? 1'h0 : _GEN_52; // @[I2C.scala 235:25 301:21]
  wire [4:0] _GEN_59 = 5'h8 == bitState ? 5'h9 : _GEN_54; // @[I2C.scala 235:25 291:21]
  wire  _GEN_60 = 5'h8 == bitState | _GEN_56; // @[I2C.scala 235:25 292:21]
  wire  _GEN_61 = 5'h8 == bitState ? 1'h0 : _GEN_57; // @[I2C.scala 235:25 293:21]
  wire  _GEN_62 = 5'h8 == bitState ? 1'h0 : _GEN_58; // @[I2C.scala 235:25 294:21]
  wire  _GEN_63 = 5'h8 == bitState ? 1'h0 : _GEN_55; // @[I2C.scala 232:15 235:25]
  wire [4:0] _GEN_64 = 5'h7 == bitState ? 5'h8 : _GEN_59; // @[I2C.scala 235:25 285:21]
  wire  _GEN_65 = 5'h7 == bitState | _GEN_60; // @[I2C.scala 235:25 286:21]
  wire  _GEN_66 = 5'h7 == bitState ? 1'h0 : _GEN_61; // @[I2C.scala 235:25 287:21]
  wire  _GEN_67 = 5'h7 == bitState ? 1'h0 : _GEN_62; // @[I2C.scala 235:25 288:21]
  wire  _GEN_68 = 5'h7 == bitState ? 1'h0 : _GEN_63; // @[I2C.scala 232:15 235:25]
  wire [4:0] _GEN_69 = 5'h6 == bitState ? 5'h7 : _GEN_64; // @[I2C.scala 235:25 279:21]
  wire  _GEN_70 = 5'h6 == bitState ? 1'h0 : _GEN_65; // @[I2C.scala 235:25 280:21]
  wire  _GEN_71 = 5'h6 == bitState ? 1'h0 : _GEN_66; // @[I2C.scala 235:25 281:21]
  wire  _GEN_72 = 5'h6 == bitState ? 1'h0 : _GEN_67; // @[I2C.scala 235:25 282:21]
  wire  _GEN_73 = 5'h6 == bitState ? 1'h0 : _GEN_68; // @[I2C.scala 232:15 235:25]
  wire [4:0] _GEN_74 = 5'h5 == bitState ? 5'h0 : _GEN_69; // @[I2C.scala 235:25 271:21]
  wire  _GEN_75 = 5'h5 == bitState | _GEN_73; // @[I2C.scala 235:25 272:21]
  wire  _GEN_76 = 5'h5 == bitState ? 1'h0 : _GEN_70; // @[I2C.scala 235:25 273:21]
  wire  _GEN_77 = 5'h5 == bitState ? 1'h0 : _GEN_71; // @[I2C.scala 235:25 274:21]
  wire  _GEN_78 = 5'h5 == bitState ? 1'h0 : _GEN_72; // @[I2C.scala 235:25 275:21]
  wire [4:0] _GEN_79 = 5'h4 == bitState ? 5'h5 : _GEN_74; // @[I2C.scala 235:25 265:21]
  wire  _GEN_80 = 5'h4 == bitState | _GEN_76; // @[I2C.scala 235:25 266:21]
  wire  _GEN_81 = 5'h4 == bitState ? 1'h0 : _GEN_77; // @[I2C.scala 235:25 267:21]
  wire  _GEN_82 = 5'h4 == bitState ? 1'h0 : _GEN_78; // @[I2C.scala 235:25 268:21]
  wire  _GEN_83 = 5'h4 == bitState ? 1'h0 : _GEN_75; // @[I2C.scala 232:15 235:25]
  wire [4:0] _GEN_84 = 5'h3 == bitState ? 5'h4 : _GEN_79; // @[I2C.scala 235:25 259:21]
  wire  _GEN_85 = 5'h3 == bitState | _GEN_80; // @[I2C.scala 235:25 260:21]
  wire  _GEN_86 = 5'h3 == bitState ? 1'h0 : _GEN_81; // @[I2C.scala 235:25 261:21]
  wire  _GEN_87 = 5'h3 == bitState ? 1'h0 : _GEN_82; // @[I2C.scala 235:25 262:21]
  wire  _GEN_88 = 5'h3 == bitState ? 1'h0 : _GEN_83; // @[I2C.scala 232:15 235:25]
  wire [4:0] _GEN_89 = 5'h2 == bitState ? 5'h3 : _GEN_84; // @[I2C.scala 235:25 253:21]
  wire  _GEN_90 = 5'h2 == bitState | _GEN_85; // @[I2C.scala 235:25 254:21]
  wire  _GEN_91 = 5'h2 == bitState | _GEN_86; // @[I2C.scala 235:25 255:21]
  wire  _GEN_92 = 5'h2 == bitState ? 1'h0 : _GEN_87; // @[I2C.scala 235:25 256:21]
  wire  _GEN_93 = 5'h2 == bitState ? 1'h0 : _GEN_88; // @[I2C.scala 232:15 235:25]
  wire [4:0] _GEN_94 = 5'h1 == bitState ? 5'h2 : _GEN_89; // @[I2C.scala 235:25 247:21]
  wire  _GEN_95 = 5'h1 == bitState ? sclOen : _GEN_90; // @[I2C.scala 235:25 248:21]
  wire  _GEN_96 = 5'h1 == bitState | _GEN_91; // @[I2C.scala 235:25 249:21]
  wire  _GEN_97 = 5'h1 == bitState ? 1'h0 : _GEN_92; // @[I2C.scala 235:25 250:21]
  wire  _GEN_98 = 5'h1 == bitState ? 1'h0 : _GEN_93; // @[I2C.scala 232:15 235:25]
  wire  _GEN_101 = 5'h0 == bitState ? sclOen : _GEN_95; // @[I2C.scala 193:23 235:25]
  wire  _GEN_102 = 5'h0 == bitState ? sdaOen : _GEN_96; // @[I2C.scala 196:23 235:25]
  wire  _GEN_103 = 5'h0 == bitState ? 1'h0 : _GEN_98; // @[I2C.scala 232:15 235:25]
  wire  _GEN_106 = clkEn ? _GEN_101 : sclOen; // @[I2C.scala 234:18 193:23]
  wire  _GEN_107 = clkEn ? _GEN_102 : sdaOen; // @[I2C.scala 234:18 196:23]
  wire  _GEN_108 = clkEn & _GEN_103; // @[I2C.scala 232:15 234:18]
  wire  _GEN_111 = arbLost | _GEN_106; // @[I2C.scala 224:18 227:15]
  wire  _GEN_112 = arbLost | _GEN_107; // @[I2C.scala 224:18 228:15]
  reg  load; // @[I2C.scala 361:24]
  reg  shift; // @[I2C.scala 362:24]
  reg  cmdAck; // @[I2C.scala 363:24]
  reg  receivedAck; // @[I2C.scala 364:24]
  wire  _go_T = cmd_read | cmd_write; // @[I2C.scala 365:31]
  wire  go = (cmd_read | cmd_write | cmd_stop) & ~cmdAck; // @[I2C.scala 365:55]
  reg [2:0] bitCnt; // @[I2C.scala 367:24]
  wire [2:0] _bitCnt_T_1 = bitCnt - 3'h1; // @[I2C.scala 372:22]
  wire  bitCntDone = ~(|bitCnt); // @[I2C.scala 374:21]
  wire [8:0] _receivedData_T = {receivedData,receivedBit}; // @[Cat.scala 31:58]
  wire [8:0] _GEN_116 = shift ? _receivedData_T : {{1'd0}, receivedData}; // @[I2C.scala 380:21 381:18 128:25]
  wire [8:0] _GEN_117 = load ? {{1'd0}, transmitData} : _GEN_116; // @[I2C.scala 377:15 378:18]
  reg [2:0] byteState; // @[I2C.scala 385:24]
  wire [2:0] _GEN_118 = cmd_write ? 3'h3 : 3'h5; // @[I2C.scala 413:33 414:23 418:23]
  wire [2:0] _GEN_119 = cmd_write ? 3'h4 : 3'h2; // @[I2C.scala 413:33 415:23 419:23]
  wire [2:0] _GEN_120 = cmd_read ? 3'h2 : _GEN_118; // @[I2C.scala 409:32 410:23]
  wire [3:0] _GEN_121 = cmd_read ? 4'h8 : {{1'd0}, _GEN_119}; // @[I2C.scala 409:32 411:23]
  wire [2:0] _GEN_122 = cmd_start ? 3'h1 : _GEN_120; // @[I2C.scala 405:28 406:23]
  wire [3:0] _GEN_123 = cmd_start ? 4'h1 : _GEN_121; // @[I2C.scala 405:28 407:23]
  wire [2:0] _GEN_127 = cmd_read ? 3'h2 : 3'h3; // @[I2C.scala 427:27 428:23 432:23]
  wire [3:0] _GEN_128 = cmd_read ? 4'h8 : 4'h4; // @[I2C.scala 427:27 429:23 433:23]
  wire [2:0] _GEN_129 = bitCmdAck ? _GEN_127 : byteState; // @[I2C.scala 385:24 426:26]
  wire [3:0] _GEN_130 = bitCmdAck ? _GEN_128 : bitCmd; // @[I2C.scala 207:24 426:26]
  wire [2:0] _GEN_132 = bitCntDone ? 3'h4 : 3'h3; // @[I2C.scala 441:29 442:23 446:23]
  wire [3:0] _GEN_133 = bitCntDone ? 4'h8 : 4'h4; // @[I2C.scala 441:29 443:23 447:23]
  wire  _GEN_134 = bitCntDone ? 1'h0 : 1'h1; // @[I2C.scala 398:17 441:29 448:23]
  wire [2:0] _GEN_135 = bitCmdAck ? _GEN_132 : byteState; // @[I2C.scala 385:24 440:26]
  wire [3:0] _GEN_136 = bitCmdAck ? _GEN_133 : bitCmd; // @[I2C.scala 207:24 440:26]
  wire  _GEN_137 = bitCmdAck & _GEN_134; // @[I2C.scala 398:17 440:26]
  wire [2:0] _GEN_138 = bitCntDone ? 3'h4 : 3'h2; // @[I2C.scala 454:29 455:23 459:23]
  wire [3:0] _GEN_139 = bitCntDone ? 4'h4 : 4'h8; // @[I2C.scala 454:29 456:23 460:23]
  wire [2:0] _GEN_140 = bitCmdAck ? _GEN_138 : byteState; // @[I2C.scala 385:24 453:26]
  wire [3:0] _GEN_141 = bitCmdAck ? _GEN_139 : bitCmd; // @[I2C.scala 207:24 453:26]
  wire  _GEN_142 = bitCmdAck ? cmd_ack : receivedData[7]; // @[I2C.scala 397:17 453:26 464:23]
  wire [2:0] _GEN_143 = cmd_stop ? 3'h5 : 3'h0; // @[I2C.scala 469:27 470:23 474:23]
  wire [1:0] _GEN_144 = cmd_stop ? 2'h2 : 2'h0; // @[I2C.scala 469:27 471:23 475:23]
  wire  _GEN_145 = cmd_stop ? 1'h0 : 1'h1; // @[I2C.scala 400:17 469:27 478:23]
  wire [2:0] _GEN_146 = bitCmdAck ? _GEN_143 : byteState; // @[I2C.scala 385:24 468:26]
  wire [3:0] _GEN_147 = bitCmdAck ? {{2'd0}, _GEN_144} : bitCmd; // @[I2C.scala 207:24 468:26]
  wire  _GEN_148 = bitCmdAck & _GEN_145; // @[I2C.scala 400:17 468:26]
  wire  _GEN_149 = bitCmdAck ? receivedBit : receivedAck; // @[I2C.scala 468:26 482:23 364:24]
  wire  _GEN_150 = bitCmdAck | cmd_ack; // @[I2C.scala 468:26 484:23 487:23]
  wire [2:0] _GEN_151 = bitCmdAck ? 3'h0 : byteState; // @[I2C.scala 491:26 492:21 385:24]
  wire [3:0] _GEN_152 = bitCmdAck ? 4'h0 : bitCmd; // @[I2C.scala 491:26 493:21 207:24]
  wire [2:0] _GEN_153 = 3'h5 == byteState ? _GEN_151 : byteState; // @[I2C.scala 385:24 402:24]
  wire [3:0] _GEN_154 = 3'h5 == byteState ? _GEN_152 : bitCmd; // @[I2C.scala 207:24 402:24]
  wire  _GEN_155 = 3'h5 == byteState & bitCmdAck; // @[I2C.scala 400:17 402:24]
  wire [2:0] _GEN_156 = 3'h4 == byteState ? _GEN_146 : _GEN_153; // @[I2C.scala 402:24]
  wire [3:0] _GEN_157 = 3'h4 == byteState ? _GEN_147 : _GEN_154; // @[I2C.scala 402:24]
  wire  _GEN_158 = 3'h4 == byteState ? _GEN_148 : _GEN_155; // @[I2C.scala 402:24]
  wire  _GEN_159 = 3'h4 == byteState ? _GEN_149 : receivedAck; // @[I2C.scala 364:24 402:24]
  wire  _GEN_160 = 3'h4 == byteState ? _GEN_150 : receivedData[7]; // @[I2C.scala 397:17 402:24]
  wire [2:0] _GEN_161 = 3'h2 == byteState ? _GEN_140 : _GEN_156; // @[I2C.scala 402:24]
  wire [3:0] _GEN_162 = 3'h2 == byteState ? _GEN_141 : _GEN_157; // @[I2C.scala 402:24]
  wire  _GEN_163 = 3'h2 == byteState & bitCmdAck; // @[I2C.scala 398:17 402:24]
  wire  _GEN_164 = 3'h2 == byteState ? _GEN_142 : _GEN_160; // @[I2C.scala 402:24]
  wire  _GEN_165 = 3'h2 == byteState ? 1'h0 : _GEN_158; // @[I2C.scala 400:17 402:24]
  wire  _GEN_166 = 3'h2 == byteState ? receivedAck : _GEN_159; // @[I2C.scala 364:24 402:24]
  wire [2:0] _GEN_167 = 3'h3 == byteState ? _GEN_135 : _GEN_161; // @[I2C.scala 402:24]
  wire [3:0] _GEN_168 = 3'h3 == byteState ? _GEN_136 : _GEN_162; // @[I2C.scala 402:24]
  wire  _GEN_169 = 3'h3 == byteState ? _GEN_137 : _GEN_163; // @[I2C.scala 402:24]
  wire  _GEN_170 = 3'h3 == byteState ? receivedData[7] : _GEN_164; // @[I2C.scala 397:17 402:24]
  wire  _GEN_171 = 3'h3 == byteState ? 1'h0 : _GEN_165; // @[I2C.scala 400:17 402:24]
  wire  _GEN_172 = 3'h3 == byteState ? receivedAck : _GEN_166; // @[I2C.scala 364:24 402:24]
  wire  _GEN_175 = 3'h1 == byteState & bitCmdAck; // @[I2C.scala 399:17 402:24]
  wire  bundleIn_0_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [2:0] bundleIn_0_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire  in_bits_read = bundleIn_0_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 72:36]
  wire [28:0] bundleIn_0_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [9:0] in_bits_index = bundleIn_0_a_bits_address[11:2]; // @[RegisterRouter.scala 71:18 73:19]
  wire [2:0] out_iindex = {in_bits_index[2],in_bits_index[1],in_bits_index[0]}; // @[Cat.scala 31:58]
  wire [9:0] out_findex = in_bits_index & 10'h3f8; // @[RegisterRouter.scala 83:24]
  wire  _out_T_8 = out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  bundleIn_0_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [7:0] _out_backSel_T = 8'h1 << out_iindex; // @[OneHot.scala 57:35]
  wire  out_backSel_4 = _out_backSel_T[4]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_6 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_backSel_4 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire [3:0] bundleIn_0_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [7:0] _out_backMask_T_11 = bundleIn_0_a_bits_mask[3] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_backMask_T_9 = bundleIn_0_a_bits_mask[2] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_backMask_T_7 = bundleIn_0_a_bits_mask[1] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [7:0] _out_backMask_T_5 = bundleIn_0_a_bits_mask[0] ? 8'hff : 8'h0; // @[Bitwise.scala 74:12]
  wire [31:0] out_backMask = {_out_backMask_T_11,_out_backMask_T_9,_out_backMask_T_7,_out_backMask_T_5}; // @[Cat.scala 31:58]
  wire  out_womask_6 = &out_backMask[7:0]; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala 83:24]
  wire [31:0] bundleIn_0_a_bits_data = buffer_auto_out_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  wire [7:0] _nextCmd_T = {cmd_start,cmd_stop,cmd_read,cmd_write,cmd_ack,2'h0,cmd_irqAck}; // @[I2C.scala 508:18]
  wire [7:0] _nextCmd_T_1 = _nextCmd_T & 8'hfe; // @[I2C.scala 508:25]
  wire [7:0] nextCmd = out_f_woready_6 ? bundleIn_0_a_bits_data[7:0] : _nextCmd_T_1; // @[I2C.scala 508:11 564:77 566:74]
  wire  _T_40 = cmdAck | arbLost; // @[I2C.scala 511:16]
  wire  _GEN_198 = startCond | status_busy; // @[I2C.scala 130:25 522:25 523:29]
  wire  _GEN_200 = cmd_start ? 1'h0 : status_arbLost; // @[I2C.scala 130:25 529:25 530:29]
  wire  _GEN_201 = arbLost | _GEN_200; // @[I2C.scala 526:18 527:29]
  reg  statusReadReady; // @[I2C.scala 536:28]
  wire  _GEN_202 = ~statusReadReady | statusReadReady; // @[I2C.scala 540:32 541:21 536:28]
  wire  _GEN_203 = _T_40 ? 1'h0 : _GEN_202; // @[I2C.scala 537:28 538:21]
  wire  out_rimask = |out_backMask[7:0]; // @[RegisterRouter.scala 83:24]
  wire  out_rofireMux_out_4 = statusReadReady | ~out_rimask; // @[RegisterRouter.scala 83:24]
  wire  _out_rofireMux_T_21 = out_rofireMux_out_4 | ~(out_findex == 10'h0); // @[RegisterRouter.scala 83:24]
  wire  _GEN_232 = 3'h4 == out_iindex ? _out_rofireMux_T_21 : 1'h1; // @[MuxLiteral.scala 48:{10,10}]
  wire  out_rofireMux = 3'h7 == out_iindex | (3'h6 == out_iindex | (3'h5 == out_iindex | _GEN_232)); // @[MuxLiteral.scala 48:{10,10}]
  wire  out_oready = in_bits_read ? out_rofireMux : 1'h1; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_0 = _out_backSel_T[0]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_0 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_0 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready = out_woready_0 & out_womask_6; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_1 = _out_backSel_T[1]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_1 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_1 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_1 = out_woready_1 & out_womask_6; // @[RegisterRouter.scala 83:24]
  wire  out_frontSel_2 = _out_backSel_T[2]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_2 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_2 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_3 = &out_backMask[6]; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_3 = out_woready_2 & out_wimask_3; // @[RegisterRouter.scala 83:24]
  wire  out_wimask_4 = &out_backMask[7]; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_4 = out_woready_2 & out_wimask_4; // @[RegisterRouter.scala 83:24]
  wire [7:0] out_prepend_1 = {control_coreEn,control_intEn,6'h0}; // @[Cat.scala 31:58]
  wire  out_frontSel_3 = _out_backSel_T[3]; // @[RegisterRouter.scala 83:24]
  wire  out_woready_5 = bundleIn_0_a_valid & bundleIn_0_d_ready & ~in_bits_read & out_frontSel_3 & out_findex == 10'h0; // @[RegisterRouter.scala 83:24]
  wire  out_f_woready_5 = out_woready_5 & out_womask_6; // @[RegisterRouter.scala 83:24]
  wire [7:0] out_f_data = {status_receivedAck,status_busy,status_arbLost,3'h0,status_transferInProgress,status_irqFlag}; // @[I2C.scala 561:89]
  wire  _GEN_210 = out_f_woready_6 ? 1'h0 : _GEN_203; // @[I2C.scala 564:77 565:82]
  wire  _GEN_245 = 3'h1 == out_iindex ? _out_T_8 : _out_T_8; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_246 = 3'h2 == out_iindex ? _out_T_8 : _GEN_245; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_247 = 3'h3 == out_iindex ? _out_T_8 : _GEN_246; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_248 = 3'h4 == out_iindex ? _out_T_8 : _GEN_247; // @[MuxLiteral.scala 48:{10,10}]
  wire  _GEN_251 = 3'h7 == out_iindex | (3'h6 == out_iindex | (3'h5 == out_iindex | _GEN_248)); // @[MuxLiteral.scala 48:{10,10}]
  wire [7:0] _GEN_253 = 3'h1 == out_iindex ? prescaler_hi : prescaler_lo; // @[MuxLiteral.scala 48:{10,10}]
  wire [7:0] _GEN_254 = 3'h2 == out_iindex ? out_prepend_1 : _GEN_253; // @[MuxLiteral.scala 48:{10,10}]
  wire [7:0] _GEN_255 = 3'h3 == out_iindex ? receivedData : _GEN_254; // @[MuxLiteral.scala 48:{10,10}]
  wire [7:0] _GEN_256 = 3'h4 == out_iindex ? out_f_data : _GEN_255; // @[MuxLiteral.scala 48:{10,10}]
  wire [7:0] _GEN_257 = 3'h5 == out_iindex ? 8'h0 : _GEN_256; // @[MuxLiteral.scala 48:{10,10}]
  wire [7:0] _GEN_258 = 3'h6 == out_iindex ? 8'h0 : _GEN_257; // @[MuxLiteral.scala 48:{10,10}]
  wire [7:0] _GEN_259 = 3'h7 == out_iindex ? 8'h0 : _GEN_258; // @[MuxLiteral.scala 48:{10,10}]
  wire [7:0] _out_out_bits_data_T_4 = _GEN_251 ? _GEN_259 : 8'h0; // @[RegisterRouter.scala 83:24]
  TLBuffer_13 buffer ( // @[Buffer.scala 68:28]
    .auto_in_a_ready(buffer_auto_in_a_ready),
    .auto_in_a_valid(buffer_auto_in_a_valid),
    .auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(buffer_auto_in_a_bits_param),
    .auto_in_a_bits_size(buffer_auto_in_a_bits_size),
    .auto_in_a_bits_source(buffer_auto_in_a_bits_source),
    .auto_in_a_bits_address(buffer_auto_in_a_bits_address),
    .auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
    .auto_in_a_bits_data(buffer_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
    .auto_in_d_ready(buffer_auto_in_d_ready),
    .auto_in_d_valid(buffer_auto_in_d_valid),
    .auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(buffer_auto_in_d_bits_size),
    .auto_in_d_bits_source(buffer_auto_in_d_bits_source),
    .auto_in_d_bits_data(buffer_auto_in_d_bits_data),
    .auto_out_a_ready(buffer_auto_out_a_ready),
    .auto_out_a_valid(buffer_auto_out_a_valid),
    .auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
    .auto_out_a_bits_param(buffer_auto_out_a_bits_param),
    .auto_out_a_bits_size(buffer_auto_out_a_bits_size),
    .auto_out_a_bits_source(buffer_auto_out_a_bits_source),
    .auto_out_a_bits_address(buffer_auto_out_a_bits_address),
    .auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
    .auto_out_a_bits_data(buffer_auto_out_a_bits_data),
    .auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
    .auto_out_d_ready(buffer_auto_out_d_ready),
    .auto_out_d_valid(buffer_auto_out_d_valid),
    .auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
    .auto_out_d_bits_size(buffer_auto_out_d_bits_size),
    .auto_out_d_bits_source(buffer_auto_out_d_bits_source),
    .auto_out_d_bits_data(buffer_auto_out_d_bits_data)
  );
  IntSyncCrossingSource_1 intsource ( // @[Crossing.scala 26:31]
    .clock(intsource_clock),
    .reset(intsource_reset),
    .auto_in_0(intsource_auto_in_0),
    .auto_out_sync_0(intsource_auto_out_sync_0)
  );
  TLMonitor_71 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_opcode(monitor_io_in_d_bits_opcode),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  assign auto_int_xing_out_sync_0 = intsource_auto_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign auto_control_xing_in_a_ready = buffer_auto_in_a_ready; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_valid = buffer_auto_in_d_valid; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_size = buffer_auto_in_d_bits_size; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_source = buffer_auto_in_d_bits_source; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_control_xing_in_d_bits_data = buffer_auto_in_d_bits_data; // @[Nodes.scala 1207:84 LazyModule.scala 298:16]
  assign auto_io_out_scl_oe = ~sclOen; // @[I2C.scala 194:18]
  assign auto_io_out_sda_oe = ~sdaOen; // @[I2C.scala 197:18]
  assign buffer_auto_in_a_valid = auto_control_xing_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_opcode = auto_control_xing_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_param = auto_control_xing_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_size = auto_control_xing_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_source = auto_control_xing_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_address = auto_control_xing_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_mask = auto_control_xing_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_data = auto_control_xing_in_a_bits_data; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_a_bits_corrupt = auto_control_xing_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_in_d_ready = auto_control_xing_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign buffer_auto_out_a_ready = bundleIn_0_d_ready & out_oready; // @[RegisterRouter.scala 83:24]
  assign buffer_auto_out_d_valid = bundleIn_0_a_valid & out_oready; // @[RegisterRouter.scala 83:24]
  assign buffer_auto_out_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign buffer_auto_out_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign buffer_auto_out_d_bits_data = {{24'd0}, _out_out_bits_data_T_4}; // @[RegisterRouter.scala 83:{24,24}]
  assign intsource_clock = clock;
  assign intsource_reset = reset;
  assign intsource_auto_in_0 = status_irqFlag & control_intEn; // @[I2C.scala 578:35]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = bundleIn_0_d_ready & out_oready; // @[RegisterRouter.scala 83:24]
  assign monitor_io_in_a_valid = buffer_auto_out_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_param = buffer_auto_out_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_address = buffer_auto_out_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_ready = buffer_auto_out_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_valid = bundleIn_0_a_valid & out_oready; // @[RegisterRouter.scala 83:24]
  assign monitor_io_in_d_bits_opcode = {{2'd0}, in_bits_read}; // @[Nodes.scala 1210:84 RegisterRouter.scala 98:19]
  assign monitor_io_in_d_bits_size = buffer_auto_out_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign monitor_io_in_d_bits_source = buffer_auto_out_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  always @(posedge clock) begin
    if (reset) begin // @[I2C.scala 125:25]
      prescaler_hi <= 8'hff; // @[I2C.scala 125:25]
    end else if (out_f_woready_1) begin // @[RegField.scala 74:88]
      prescaler_hi <= bundleIn_0_a_bits_data[7:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[I2C.scala 125:25]
      prescaler_lo <= 8'hff; // @[I2C.scala 125:25]
    end else if (out_f_woready) begin // @[RegField.scala 74:88]
      prescaler_lo <= bundleIn_0_a_bits_data[7:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[I2C.scala 126:25]
      control_coreEn <= 1'h0; // @[I2C.scala 126:25]
    end else if (out_f_woready_4) begin // @[RegField.scala 74:88]
      control_coreEn <= bundleIn_0_a_bits_data[7]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[I2C.scala 126:25]
      control_intEn <= 1'h0; // @[I2C.scala 126:25]
    end else if (out_f_woready_3) begin // @[RegField.scala 74:88]
      control_intEn <= bundleIn_0_a_bits_data[6]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[I2C.scala 127:25]
      transmitData <= 8'h0; // @[I2C.scala 127:25]
    end else if (out_f_woready_5) begin // @[RegField.scala 74:88]
      transmitData <= bundleIn_0_a_bits_data[7:0]; // @[RegField.scala 74:92]
    end
    if (reset) begin // @[I2C.scala 128:25]
      receivedData <= 8'h0; // @[I2C.scala 128:25]
    end else begin
      receivedData <= _GEN_117[7:0];
    end
    if (reset) begin // @[I2C.scala 129:25]
      cmd_start <= 1'h0; // @[I2C.scala 129:25]
    end else if (cmdAck | arbLost) begin // @[I2C.scala 511:28]
      cmd_start <= 1'h0; // @[I2C.scala 512:15]
    end else begin
      cmd_start <= nextCmd[7]; // @[I2C.scala 507:7]
    end
    if (reset) begin // @[I2C.scala 129:25]
      cmd_stop <= 1'h0; // @[I2C.scala 129:25]
    end else if (cmdAck | arbLost) begin // @[I2C.scala 511:28]
      cmd_stop <= 1'h0; // @[I2C.scala 513:15]
    end else begin
      cmd_stop <= nextCmd[6]; // @[I2C.scala 507:7]
    end
    if (reset) begin // @[I2C.scala 129:25]
      cmd_read <= 1'h0; // @[I2C.scala 129:25]
    end else if (cmdAck | arbLost) begin // @[I2C.scala 511:28]
      cmd_read <= 1'h0; // @[I2C.scala 514:15]
    end else begin
      cmd_read <= nextCmd[5]; // @[I2C.scala 507:7]
    end
    if (reset) begin // @[I2C.scala 129:25]
      cmd_write <= 1'h0; // @[I2C.scala 129:25]
    end else if (cmdAck | arbLost) begin // @[I2C.scala 511:28]
      cmd_write <= 1'h0; // @[I2C.scala 515:15]
    end else begin
      cmd_write <= nextCmd[4]; // @[I2C.scala 507:7]
    end
    if (reset) begin // @[I2C.scala 129:25]
      cmd_ack <= 1'h0; // @[I2C.scala 129:25]
    end else begin
      cmd_ack <= nextCmd[3]; // @[I2C.scala 507:7]
    end
    if (reset) begin // @[I2C.scala 129:25]
      cmd_irqAck <= 1'h0; // @[I2C.scala 129:25]
    end else begin
      cmd_irqAck <= nextCmd[0]; // @[I2C.scala 507:7]
    end
    if (reset) begin // @[I2C.scala 130:25]
      status_receivedAck <= 1'h0; // @[I2C.scala 130:25]
    end else begin
      status_receivedAck <= receivedAck; // @[I2C.scala 518:22]
    end
    if (reset) begin // @[I2C.scala 130:25]
      status_busy <= 1'h0; // @[I2C.scala 130:25]
    end else if (stopCond) begin // @[I2C.scala 519:19]
      status_busy <= 1'h0; // @[I2C.scala 520:29]
    end else begin
      status_busy <= _GEN_198;
    end
    if (reset) begin // @[I2C.scala 130:25]
      status_arbLost <= 1'h0; // @[I2C.scala 130:25]
    end else begin
      status_arbLost <= _GEN_201;
    end
    if (reset) begin // @[I2C.scala 130:25]
      status_transferInProgress <= 1'h0; // @[I2C.scala 130:25]
    end else begin
      status_transferInProgress <= _go_T; // @[I2C.scala 532:29]
    end
    if (reset) begin // @[I2C.scala 130:25]
      status_irqFlag <= 1'h0; // @[I2C.scala 130:25]
    end else begin
      status_irqFlag <= (_T_40 | status_irqFlag) & ~cmd_irqAck; // @[I2C.scala 533:29]
    end
    if (reset) begin // @[I2C.scala 139:22]
      filterCnt <= 14'h0; // @[I2C.scala 139:22]
    end else if (~control_coreEn) begin // @[I2C.scala 140:28]
      filterCnt <= 14'h0; // @[I2C.scala 141:15]
    end else if (~(|filterCnt)) begin // @[I2C.scala 142:34]
      filterCnt <= _filterCnt_T[15:2]; // @[I2C.scala 143:15]
    end else begin
      filterCnt <= _filterCnt_T_3; // @[I2C.scala 145:15]
    end
    if (reset) begin // @[I2C.scala 148:22]
      fSCL <= 3'h7; // @[I2C.scala 148:22]
    end else begin
      fSCL <= _GEN_2[2:0];
    end
    if (reset) begin // @[I2C.scala 149:22]
      fSDA <= 3'h7; // @[I2C.scala 149:22]
    end else begin
      fSDA <= _GEN_3[2:0];
    end
    sSCL <= reset | sSCL_x29; // @[I2C.scala 155:{22,22,22}]
    sSDA <= reset | sSDA_x32; // @[I2C.scala 156:{22,22,22}]
    dSCL <= reset | sSCL; // @[I2C.scala 158:{22,22,22}]
    dSDA <= reset | sSDA; // @[I2C.scala 159:{22,22,22}]
    dSCLOen <= ~sclOen; // @[I2C.scala 194:18]
    if (reset) begin // @[I2C.scala 165:22]
      startCond <= 1'h0; // @[I2C.scala 165:22]
    end else begin
      startCond <= startCond_x44; // @[I2C.scala 165:22]
    end
    if (reset) begin // @[I2C.scala 166:22]
      stopCond <= 1'h0; // @[I2C.scala 166:22]
    end else begin
      stopCond <= stopCond_x47; // @[I2C.scala 166:22]
    end
    sclOen <= reset | _GEN_111; // @[I2C.scala 193:{23,23}]
    if (reset) begin // @[I2C.scala 174:22]
      slaveWait <= 1'h0; // @[I2C.scala 174:22]
    end else begin
      slaveWait <= bundleOut_0_scl_oe & ~dSCLOen & _sclSync_T | slaveWait & _sclSync_T; // @[I2C.scala 175:13]
    end
    clkEn <= reset | _T_9; // @[I2C.scala 177:{22,22}]
    if (reset) begin // @[I2C.scala 178:22]
      cnt <= 16'h0; // @[I2C.scala 178:22]
    end else if (~(|cnt) | _T | sclSync) begin // @[I2C.scala 181:52]
      cnt <= _filterCnt_T; // @[I2C.scala 182:11]
    end else if (!(slaveWait)) begin // @[I2C.scala 185:25]
      cnt <= _cnt_T_2; // @[I2C.scala 189:11]
    end
    sdaOen <= reset | _GEN_112; // @[I2C.scala 196:{23,23}]
    if (reset) begin // @[I2C.scala 199:23]
      sdaChk <= 1'h0; // @[I2C.scala 199:23]
    end else if (arbLost) begin // @[I2C.scala 224:18]
      sdaChk <= 1'h0; // @[I2C.scala 229:15]
    end else if (clkEn) begin // @[I2C.scala 234:18]
      if (5'h0 == bitState) begin // @[I2C.scala 235:25]
        sdaChk <= 1'h0; // @[I2C.scala 243:18]
      end else begin
        sdaChk <= _GEN_97;
      end
    end
    if (reset) begin // @[I2C.scala 201:24]
      transmitBit <= 1'h0; // @[I2C.scala 201:24]
    end else if (arbLost) begin // @[I2C.scala 387:18]
      transmitBit <= 1'h0; // @[I2C.scala 389:17]
    end else if (3'h0 == byteState) begin // @[I2C.scala 402:24]
      transmitBit <= receivedData[7]; // @[I2C.scala 397:17]
    end else if (3'h1 == byteState) begin // @[I2C.scala 402:24]
      transmitBit <= receivedData[7]; // @[I2C.scala 397:17]
    end else begin
      transmitBit <= _GEN_170;
    end
    if (sSCL & ~dSCL) begin // @[I2C.scala 203:24]
      receivedBit <= sSDA; // @[I2C.scala 204:17]
    end
    if (reset) begin // @[I2C.scala 207:24]
      bitCmd <= 4'h0; // @[I2C.scala 207:24]
    end else if (arbLost) begin // @[I2C.scala 387:18]
      bitCmd <= 4'h0; // @[I2C.scala 388:17]
    end else if (3'h0 == byteState) begin // @[I2C.scala 402:24]
      if (go) begin // @[I2C.scala 404:19]
        bitCmd <= _GEN_123;
      end
    end else if (3'h1 == byteState) begin // @[I2C.scala 402:24]
      bitCmd <= _GEN_130;
    end else begin
      bitCmd <= _GEN_168;
    end
    if (reset) begin // @[I2C.scala 208:24]
      bitCmdStop <= 1'h0; // @[I2C.scala 208:24]
    end else if (clkEn) begin // @[I2C.scala 209:16]
      bitCmdStop <= bitCmd == 4'h2; // @[I2C.scala 210:16]
    end
    if (reset) begin // @[I2C.scala 212:24]
      bitCmdAck <= 1'h0; // @[I2C.scala 212:24]
    end else if (arbLost) begin // @[I2C.scala 224:18]
      bitCmdAck <= 1'h0; // @[I2C.scala 226:15]
    end else begin
      bitCmdAck <= _GEN_108;
    end
    if (reset) begin // @[I2C.scala 219:24]
      bitState <= 5'h0; // @[I2C.scala 219:24]
    end else if (arbLost) begin // @[I2C.scala 224:18]
      bitState <= 5'h0; // @[I2C.scala 225:15]
    end else if (clkEn) begin // @[I2C.scala 234:18]
      if (5'h0 == bitState) begin // @[I2C.scala 235:25]
        bitState <= _GEN_13;
      end else begin
        bitState <= _GEN_94;
      end
    end
    if (reset) begin // @[I2C.scala 221:24]
      arbLost <= 1'h0; // @[I2C.scala 221:24]
    end else begin
      arbLost <= arbLost_x83; // @[I2C.scala 221:24]
    end
    if (reset) begin // @[I2C.scala 361:24]
      load <= 1'h0; // @[I2C.scala 361:24]
    end else if (arbLost) begin // @[I2C.scala 387:18]
      load <= 1'h0; // @[I2C.scala 391:17]
    end else if (3'h0 == byteState) begin // @[I2C.scala 402:24]
      load <= go;
    end else begin
      load <= _GEN_175;
    end
    if (reset) begin // @[I2C.scala 362:24]
      shift <= 1'h0; // @[I2C.scala 362:24]
    end else if (arbLost) begin // @[I2C.scala 387:18]
      shift <= 1'h0; // @[I2C.scala 390:17]
    end else if (3'h0 == byteState) begin // @[I2C.scala 402:24]
      shift <= 1'h0; // @[I2C.scala 398:17]
    end else if (3'h1 == byteState) begin // @[I2C.scala 402:24]
      shift <= 1'h0; // @[I2C.scala 398:17]
    end else begin
      shift <= _GEN_169;
    end
    if (reset) begin // @[I2C.scala 363:24]
      cmdAck <= 1'h0; // @[I2C.scala 363:24]
    end else if (arbLost) begin // @[I2C.scala 387:18]
      cmdAck <= 1'h0; // @[I2C.scala 392:17]
    end else if (3'h0 == byteState) begin // @[I2C.scala 402:24]
      cmdAck <= 1'h0; // @[I2C.scala 400:17]
    end else if (3'h1 == byteState) begin // @[I2C.scala 402:24]
      cmdAck <= 1'h0; // @[I2C.scala 400:17]
    end else begin
      cmdAck <= _GEN_171;
    end
    if (reset) begin // @[I2C.scala 364:24]
      receivedAck <= 1'h0; // @[I2C.scala 364:24]
    end else if (arbLost) begin // @[I2C.scala 387:18]
      receivedAck <= 1'h0; // @[I2C.scala 394:17]
    end else if (!(3'h0 == byteState)) begin // @[I2C.scala 402:24]
      if (!(3'h1 == byteState)) begin // @[I2C.scala 402:24]
        receivedAck <= _GEN_172;
      end
    end
    if (reset) begin // @[I2C.scala 367:24]
      bitCnt <= 3'h0; // @[I2C.scala 367:24]
    end else if (load) begin // @[I2C.scala 368:15]
      bitCnt <= 3'h7; // @[I2C.scala 369:12]
    end else if (shift) begin // @[I2C.scala 371:21]
      bitCnt <= _bitCnt_T_1; // @[I2C.scala 372:12]
    end
    if (reset) begin // @[I2C.scala 385:24]
      byteState <= 3'h0; // @[I2C.scala 385:24]
    end else if (arbLost) begin // @[I2C.scala 387:18]
      byteState <= 3'h0; // @[I2C.scala 393:17]
    end else if (3'h0 == byteState) begin // @[I2C.scala 402:24]
      if (go) begin // @[I2C.scala 404:19]
        byteState <= _GEN_122;
      end
    end else if (3'h1 == byteState) begin // @[I2C.scala 402:24]
      byteState <= _GEN_129;
    end else begin
      byteState <= _GEN_167;
    end
    statusReadReady <= reset | _GEN_210; // @[I2C.scala 536:{28,28}]
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  prescaler_hi = _RAND_0[7:0];
  _RAND_1 = {1{`RANDOM}};
  prescaler_lo = _RAND_1[7:0];
  _RAND_2 = {1{`RANDOM}};
  control_coreEn = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  control_intEn = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  transmitData = _RAND_4[7:0];
  _RAND_5 = {1{`RANDOM}};
  receivedData = _RAND_5[7:0];
  _RAND_6 = {1{`RANDOM}};
  cmd_start = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  cmd_stop = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  cmd_read = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  cmd_write = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  cmd_ack = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  cmd_irqAck = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  status_receivedAck = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  status_busy = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  status_arbLost = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  status_transferInProgress = _RAND_15[0:0];
  _RAND_16 = {1{`RANDOM}};
  status_irqFlag = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  filterCnt = _RAND_17[13:0];
  _RAND_18 = {1{`RANDOM}};
  fSCL = _RAND_18[2:0];
  _RAND_19 = {1{`RANDOM}};
  fSDA = _RAND_19[2:0];
  _RAND_20 = {1{`RANDOM}};
  sSCL = _RAND_20[0:0];
  _RAND_21 = {1{`RANDOM}};
  sSDA = _RAND_21[0:0];
  _RAND_22 = {1{`RANDOM}};
  dSCL = _RAND_22[0:0];
  _RAND_23 = {1{`RANDOM}};
  dSDA = _RAND_23[0:0];
  _RAND_24 = {1{`RANDOM}};
  dSCLOen = _RAND_24[0:0];
  _RAND_25 = {1{`RANDOM}};
  startCond = _RAND_25[0:0];
  _RAND_26 = {1{`RANDOM}};
  stopCond = _RAND_26[0:0];
  _RAND_27 = {1{`RANDOM}};
  sclOen = _RAND_27[0:0];
  _RAND_28 = {1{`RANDOM}};
  slaveWait = _RAND_28[0:0];
  _RAND_29 = {1{`RANDOM}};
  clkEn = _RAND_29[0:0];
  _RAND_30 = {1{`RANDOM}};
  cnt = _RAND_30[15:0];
  _RAND_31 = {1{`RANDOM}};
  sdaOen = _RAND_31[0:0];
  _RAND_32 = {1{`RANDOM}};
  sdaChk = _RAND_32[0:0];
  _RAND_33 = {1{`RANDOM}};
  transmitBit = _RAND_33[0:0];
  _RAND_34 = {1{`RANDOM}};
  receivedBit = _RAND_34[0:0];
  _RAND_35 = {1{`RANDOM}};
  bitCmd = _RAND_35[3:0];
  _RAND_36 = {1{`RANDOM}};
  bitCmdStop = _RAND_36[0:0];
  _RAND_37 = {1{`RANDOM}};
  bitCmdAck = _RAND_37[0:0];
  _RAND_38 = {1{`RANDOM}};
  bitState = _RAND_38[4:0];
  _RAND_39 = {1{`RANDOM}};
  arbLost = _RAND_39[0:0];
  _RAND_40 = {1{`RANDOM}};
  load = _RAND_40[0:0];
  _RAND_41 = {1{`RANDOM}};
  shift = _RAND_41[0:0];
  _RAND_42 = {1{`RANDOM}};
  cmdAck = _RAND_42[0:0];
  _RAND_43 = {1{`RANDOM}};
  receivedAck = _RAND_43[0:0];
  _RAND_44 = {1{`RANDOM}};
  bitCnt = _RAND_44[2:0];
  _RAND_45 = {1{`RANDOM}};
  byteState = _RAND_45[2:0];
  _RAND_46 = {1{`RANDOM}};
  statusReadReady = _RAND_46[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ClockSinkDomain_14(
  output        auto_i2c_1_int_xing_out_sync_0,
  output        auto_i2c_1_control_xing_in_a_ready,
  input         auto_i2c_1_control_xing_in_a_valid,
  input  [2:0]  auto_i2c_1_control_xing_in_a_bits_opcode,
  input  [2:0]  auto_i2c_1_control_xing_in_a_bits_param,
  input  [1:0]  auto_i2c_1_control_xing_in_a_bits_size,
  input  [6:0]  auto_i2c_1_control_xing_in_a_bits_source,
  input  [28:0] auto_i2c_1_control_xing_in_a_bits_address,
  input  [3:0]  auto_i2c_1_control_xing_in_a_bits_mask,
  input  [31:0] auto_i2c_1_control_xing_in_a_bits_data,
  input         auto_i2c_1_control_xing_in_a_bits_corrupt,
  input         auto_i2c_1_control_xing_in_d_ready,
  output        auto_i2c_1_control_xing_in_d_valid,
  output [2:0]  auto_i2c_1_control_xing_in_d_bits_opcode,
  output [1:0]  auto_i2c_1_control_xing_in_d_bits_size,
  output [6:0]  auto_i2c_1_control_xing_in_d_bits_source,
  output [31:0] auto_i2c_1_control_xing_in_d_bits_data,
  input         auto_i2c_1_io_out_scl_in,
  output        auto_i2c_1_io_out_scl_oe,
  input         auto_i2c_1_io_out_sda_in,
  output        auto_i2c_1_io_out_sda_oe,
  input         auto_clock_in_clock,
  input         auto_clock_in_reset
);
  wire  i2c_1_clock; // @[I2C.scala 597:49]
  wire  i2c_1_reset; // @[I2C.scala 597:49]
  wire  i2c_1_auto_int_xing_out_sync_0; // @[I2C.scala 597:49]
  wire  i2c_1_auto_control_xing_in_a_ready; // @[I2C.scala 597:49]
  wire  i2c_1_auto_control_xing_in_a_valid; // @[I2C.scala 597:49]
  wire [2:0] i2c_1_auto_control_xing_in_a_bits_opcode; // @[I2C.scala 597:49]
  wire [2:0] i2c_1_auto_control_xing_in_a_bits_param; // @[I2C.scala 597:49]
  wire [1:0] i2c_1_auto_control_xing_in_a_bits_size; // @[I2C.scala 597:49]
  wire [6:0] i2c_1_auto_control_xing_in_a_bits_source; // @[I2C.scala 597:49]
  wire [28:0] i2c_1_auto_control_xing_in_a_bits_address; // @[I2C.scala 597:49]
  wire [3:0] i2c_1_auto_control_xing_in_a_bits_mask; // @[I2C.scala 597:49]
  wire [31:0] i2c_1_auto_control_xing_in_a_bits_data; // @[I2C.scala 597:49]
  wire  i2c_1_auto_control_xing_in_a_bits_corrupt; // @[I2C.scala 597:49]
  wire  i2c_1_auto_control_xing_in_d_ready; // @[I2C.scala 597:49]
  wire  i2c_1_auto_control_xing_in_d_valid; // @[I2C.scala 597:49]
  wire [2:0] i2c_1_auto_control_xing_in_d_bits_opcode; // @[I2C.scala 597:49]
  wire [1:0] i2c_1_auto_control_xing_in_d_bits_size; // @[I2C.scala 597:49]
  wire [6:0] i2c_1_auto_control_xing_in_d_bits_source; // @[I2C.scala 597:49]
  wire [31:0] i2c_1_auto_control_xing_in_d_bits_data; // @[I2C.scala 597:49]
  wire  i2c_1_auto_io_out_scl_in; // @[I2C.scala 597:49]
  wire  i2c_1_auto_io_out_scl_oe; // @[I2C.scala 597:49]
  wire  i2c_1_auto_io_out_sda_in; // @[I2C.scala 597:49]
  wire  i2c_1_auto_io_out_sda_oe; // @[I2C.scala 597:49]
  TLI2C_1 i2c_1 ( // @[I2C.scala 597:49]
    .clock(i2c_1_clock),
    .reset(i2c_1_reset),
    .auto_int_xing_out_sync_0(i2c_1_auto_int_xing_out_sync_0),
    .auto_control_xing_in_a_ready(i2c_1_auto_control_xing_in_a_ready),
    .auto_control_xing_in_a_valid(i2c_1_auto_control_xing_in_a_valid),
    .auto_control_xing_in_a_bits_opcode(i2c_1_auto_control_xing_in_a_bits_opcode),
    .auto_control_xing_in_a_bits_param(i2c_1_auto_control_xing_in_a_bits_param),
    .auto_control_xing_in_a_bits_size(i2c_1_auto_control_xing_in_a_bits_size),
    .auto_control_xing_in_a_bits_source(i2c_1_auto_control_xing_in_a_bits_source),
    .auto_control_xing_in_a_bits_address(i2c_1_auto_control_xing_in_a_bits_address),
    .auto_control_xing_in_a_bits_mask(i2c_1_auto_control_xing_in_a_bits_mask),
    .auto_control_xing_in_a_bits_data(i2c_1_auto_control_xing_in_a_bits_data),
    .auto_control_xing_in_a_bits_corrupt(i2c_1_auto_control_xing_in_a_bits_corrupt),
    .auto_control_xing_in_d_ready(i2c_1_auto_control_xing_in_d_ready),
    .auto_control_xing_in_d_valid(i2c_1_auto_control_xing_in_d_valid),
    .auto_control_xing_in_d_bits_opcode(i2c_1_auto_control_xing_in_d_bits_opcode),
    .auto_control_xing_in_d_bits_size(i2c_1_auto_control_xing_in_d_bits_size),
    .auto_control_xing_in_d_bits_source(i2c_1_auto_control_xing_in_d_bits_source),
    .auto_control_xing_in_d_bits_data(i2c_1_auto_control_xing_in_d_bits_data),
    .auto_io_out_scl_in(i2c_1_auto_io_out_scl_in),
    .auto_io_out_scl_oe(i2c_1_auto_io_out_scl_oe),
    .auto_io_out_sda_in(i2c_1_auto_io_out_sda_in),
    .auto_io_out_sda_oe(i2c_1_auto_io_out_sda_oe)
  );
  assign auto_i2c_1_int_xing_out_sync_0 = i2c_1_auto_int_xing_out_sync_0; // @[LazyModule.scala 311:12]
  assign auto_i2c_1_control_xing_in_a_ready = i2c_1_auto_control_xing_in_a_ready; // @[LazyModule.scala 309:16]
  assign auto_i2c_1_control_xing_in_d_valid = i2c_1_auto_control_xing_in_d_valid; // @[LazyModule.scala 309:16]
  assign auto_i2c_1_control_xing_in_d_bits_opcode = i2c_1_auto_control_xing_in_d_bits_opcode; // @[LazyModule.scala 309:16]
  assign auto_i2c_1_control_xing_in_d_bits_size = i2c_1_auto_control_xing_in_d_bits_size; // @[LazyModule.scala 309:16]
  assign auto_i2c_1_control_xing_in_d_bits_source = i2c_1_auto_control_xing_in_d_bits_source; // @[LazyModule.scala 309:16]
  assign auto_i2c_1_control_xing_in_d_bits_data = i2c_1_auto_control_xing_in_d_bits_data; // @[LazyModule.scala 309:16]
  assign auto_i2c_1_io_out_scl_oe = i2c_1_auto_io_out_scl_oe; // @[LazyModule.scala 311:12]
  assign auto_i2c_1_io_out_sda_oe = i2c_1_auto_io_out_sda_oe; // @[LazyModule.scala 311:12]
  assign i2c_1_clock = auto_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign i2c_1_reset = auto_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign i2c_1_auto_control_xing_in_a_valid = auto_i2c_1_control_xing_in_a_valid; // @[LazyModule.scala 309:16]
  assign i2c_1_auto_control_xing_in_a_bits_opcode = auto_i2c_1_control_xing_in_a_bits_opcode; // @[LazyModule.scala 309:16]
  assign i2c_1_auto_control_xing_in_a_bits_param = auto_i2c_1_control_xing_in_a_bits_param; // @[LazyModule.scala 309:16]
  assign i2c_1_auto_control_xing_in_a_bits_size = auto_i2c_1_control_xing_in_a_bits_size; // @[LazyModule.scala 309:16]
  assign i2c_1_auto_control_xing_in_a_bits_source = auto_i2c_1_control_xing_in_a_bits_source; // @[LazyModule.scala 309:16]
  assign i2c_1_auto_control_xing_in_a_bits_address = auto_i2c_1_control_xing_in_a_bits_address; // @[LazyModule.scala 309:16]
  assign i2c_1_auto_control_xing_in_a_bits_mask = auto_i2c_1_control_xing_in_a_bits_mask; // @[LazyModule.scala 309:16]
  assign i2c_1_auto_control_xing_in_a_bits_data = auto_i2c_1_control_xing_in_a_bits_data; // @[LazyModule.scala 309:16]
  assign i2c_1_auto_control_xing_in_a_bits_corrupt = auto_i2c_1_control_xing_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
  assign i2c_1_auto_control_xing_in_d_ready = auto_i2c_1_control_xing_in_d_ready; // @[LazyModule.scala 309:16]
  assign i2c_1_auto_io_out_scl_in = auto_i2c_1_io_out_scl_in; // @[LazyModule.scala 311:12]
  assign i2c_1_auto_io_out_sda_in = auto_i2c_1_io_out_sda_in; // @[LazyModule.scala 311:12]
endmodule
module TLMonitor_72(
  input         clock,
  input         reset,
  input         io_in_a_ready,
  input         io_in_a_valid,
  input  [2:0]  io_in_a_bits_opcode,
  input  [2:0]  io_in_a_bits_param,
  input  [1:0]  io_in_a_bits_size,
  input  [6:0]  io_in_a_bits_source,
  input  [16:0] io_in_a_bits_address,
  input  [3:0]  io_in_a_bits_mask,
  input         io_in_a_bits_corrupt,
  input         io_in_d_ready,
  input         io_in_d_valid,
  input  [1:0]  io_in_d_bits_size,
  input  [6:0]  io_in_d_bits_source
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [95:0] _RAND_9;
  reg [383:0] _RAND_10;
  reg [383:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] plusarg_reader_out; // @[PlusArg.scala 80:11]
  wire [31:0] plusarg_reader_1_out; // @[PlusArg.scala 80:11]
  wire  _T_2 = ~reset; // @[Monitor.scala 42:11]
  wire  _source_ok_T_4 = io_in_a_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire [4:0] _is_aligned_mask_T_1 = 5'h3 << io_in_a_bits_size; // @[package.scala 234:77]
  wire [1:0] is_aligned_mask = ~_is_aligned_mask_T_1[1:0]; // @[package.scala 234:46]
  wire [16:0] _GEN_71 = {{15'd0}, is_aligned_mask}; // @[Edges.scala 20:16]
  wire [16:0] _is_aligned_T = io_in_a_bits_address & _GEN_71; // @[Edges.scala 20:16]
  wire  is_aligned = _is_aligned_T == 17'h0; // @[Edges.scala 20:24]
  wire  mask_sizeOH_shiftAmount = io_in_a_bits_size[0]; // @[OneHot.scala 63:49]
  wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala 64:12]
  wire [1:0] mask_sizeOH = _mask_sizeOH_T_1 | 2'h1; // @[Misc.scala 201:81]
  wire  _mask_T = io_in_a_bits_size >= 2'h2; // @[Misc.scala 205:21]
  wire  mask_size = mask_sizeOH[1]; // @[Misc.scala 208:26]
  wire  mask_bit = io_in_a_bits_address[1]; // @[Misc.scala 209:26]
  wire  mask_nbit = ~mask_bit; // @[Misc.scala 210:20]
  wire  mask_acc = _mask_T | mask_size & mask_nbit; // @[Misc.scala 214:29]
  wire  mask_acc_1 = _mask_T | mask_size & mask_bit; // @[Misc.scala 214:29]
  wire  mask_size_1 = mask_sizeOH[0]; // @[Misc.scala 208:26]
  wire  mask_bit_1 = io_in_a_bits_address[0]; // @[Misc.scala 209:26]
  wire  mask_nbit_1 = ~mask_bit_1; // @[Misc.scala 210:20]
  wire  mask_eq_2 = mask_nbit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_2 = mask_acc | mask_size_1 & mask_eq_2; // @[Misc.scala 214:29]
  wire  mask_eq_3 = mask_nbit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_3 = mask_acc | mask_size_1 & mask_eq_3; // @[Misc.scala 214:29]
  wire  mask_eq_4 = mask_bit & mask_nbit_1; // @[Misc.scala 213:27]
  wire  mask_acc_4 = mask_acc_1 | mask_size_1 & mask_eq_4; // @[Misc.scala 214:29]
  wire  mask_eq_5 = mask_bit & mask_bit_1; // @[Misc.scala 213:27]
  wire  mask_acc_5 = mask_acc_1 | mask_size_1 & mask_eq_5; // @[Misc.scala 214:29]
  wire [3:0] mask = {mask_acc_5,mask_acc_4,mask_acc_3,mask_acc_2}; // @[Cat.scala 31:58]
  wire  _T_10 = ~_source_ok_T_4; // @[Monitor.scala 63:7]
  wire  _T_20 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 81:25]
  wire [16:0] _T_33 = io_in_a_bits_address ^ 17'h10000; // @[Parameters.scala 137:31]
  wire [17:0] _T_34 = {1'b0,$signed(_T_33)}; // @[Parameters.scala 137:49]
  wire [17:0] _T_36 = $signed(_T_34) & -18'sh10000; // @[Parameters.scala 137:52]
  wire  _T_37 = $signed(_T_36) == 18'sh0; // @[Parameters.scala 137:67]
  wire  _T_69 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 108:27]
  wire [3:0] _T_73 = ~io_in_a_bits_mask; // @[Monitor.scala 88:18]
  wire  _T_74 = _T_73 == 4'h0; // @[Monitor.scala 88:31]
  wire  _T_78 = ~io_in_a_bits_corrupt; // @[Monitor.scala 89:18]
  wire  _T_82 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 92:25]
  wire  _T_135 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 99:31]
  wire  _T_148 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 104:25]
  wire  _T_164 = io_in_a_bits_size <= 2'h2; // @[Parameters.scala 92:42]
  wire  _T_172 = _T_164 & _T_37; // @[Parameters.scala 670:56]
  wire  _T_183 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 109:31]
  wire  _T_187 = io_in_a_bits_mask == mask; // @[Monitor.scala 110:30]
  wire  _T_195 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 114:25]
  wire  _T_233 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 122:25]
  wire [3:0] _T_267 = ~mask; // @[Monitor.scala 127:33]
  wire [3:0] _T_268 = io_in_a_bits_mask & _T_267; // @[Monitor.scala 127:31]
  wire  _T_269 = _T_268 == 4'h0; // @[Monitor.scala 127:40]
  wire  _T_273 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 130:25]
  wire  _T_303 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 138:33]
  wire  _T_311 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 138:25]
  wire  _T_341 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 145:30]
  wire  _T_349 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 146:25]
  wire  _T_379 = io_in_a_bits_param <= 3'h1; // @[Bundles.scala 158:28]
  wire  _source_ok_T_10 = io_in_d_bits_source <= 7'h5f; // @[Parameters.scala 57:20]
  wire  a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala 50:35]
  reg  a_first_counter; // @[Edges.scala 228:27]
  wire  a_first_counter1 = a_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  a_first = ~a_first_counter; // @[Edges.scala 230:25]
  reg [2:0] opcode; // @[Monitor.scala 384:22]
  reg [2:0] param; // @[Monitor.scala 385:22]
  reg [1:0] size; // @[Monitor.scala 386:22]
  reg [6:0] source; // @[Monitor.scala 387:22]
  reg [16:0] address; // @[Monitor.scala 388:22]
  wire  _T_537 = io_in_a_valid & ~a_first; // @[Monitor.scala 389:19]
  wire  _T_538 = io_in_a_bits_opcode == opcode; // @[Monitor.scala 390:32]
  wire  _T_542 = io_in_a_bits_param == param; // @[Monitor.scala 391:32]
  wire  _T_546 = io_in_a_bits_size == size; // @[Monitor.scala 392:32]
  wire  _T_550 = io_in_a_bits_source == source; // @[Monitor.scala 393:32]
  wire  _T_554 = io_in_a_bits_address == address; // @[Monitor.scala 394:32]
  wire  d_first_done = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala 50:35]
  reg  d_first_counter; // @[Edges.scala 228:27]
  wire  d_first_counter1 = d_first_counter - 1'h1; // @[Edges.scala 229:28]
  wire  d_first = ~d_first_counter; // @[Edges.scala 230:25]
  reg [1:0] size_1; // @[Monitor.scala 537:22]
  reg [6:0] source_1; // @[Monitor.scala 538:22]
  wire  _T_561 = io_in_d_valid & ~d_first; // @[Monitor.scala 541:19]
  wire  _T_570 = io_in_d_bits_size == size_1; // @[Monitor.scala 544:29]
  wire  _T_574 = io_in_d_bits_source == source_1; // @[Monitor.scala 545:29]
  reg [95:0] inflight; // @[Monitor.scala 611:27]
  reg [383:0] inflight_opcodes; // @[Monitor.scala 613:35]
  reg [383:0] inflight_sizes; // @[Monitor.scala 615:33]
  reg  a_first_counter_1; // @[Edges.scala 228:27]
  wire  a_first_counter1_1 = a_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  a_first_1 = ~a_first_counter_1; // @[Edges.scala 230:25]
  reg  d_first_counter_1; // @[Edges.scala 228:27]
  wire  d_first_counter1_1 = d_first_counter_1 - 1'h1; // @[Edges.scala 229:28]
  wire  d_first_1 = ~d_first_counter_1; // @[Edges.scala 230:25]
  wire [8:0] _GEN_72 = {io_in_d_bits_source, 2'h0}; // @[Monitor.scala 634:69]
  wire [9:0] _a_opcode_lookup_T = {{1'd0}, _GEN_72}; // @[Monitor.scala 634:69]
  wire [383:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala 634:44]
  wire [15:0] _a_opcode_lookup_T_5 = 16'h10 - 16'h1; // @[Monitor.scala 609:57]
  wire [383:0] _GEN_73 = {{368'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & _GEN_73; // @[Monitor.scala 634:97]
  wire [383:0] _a_opcode_lookup_T_7 = {{1'd0}, _a_opcode_lookup_T_6[383:1]}; // @[Monitor.scala 634:152]
  wire [383:0] _a_size_lookup_T_1 = inflight_sizes >> _a_opcode_lookup_T; // @[Monitor.scala 638:40]
  wire [383:0] _a_size_lookup_T_6 = _a_size_lookup_T_1 & _GEN_73; // @[Monitor.scala 638:91]
  wire [383:0] _a_size_lookup_T_7 = {{1'd0}, _a_size_lookup_T_6[383:1]}; // @[Monitor.scala 638:144]
  wire  _T_588 = io_in_a_valid & a_first_1; // @[Monitor.scala 648:26]
  wire [127:0] _a_set_wo_ready_T = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 57:35]
  wire  _T_591 = a_first_done & a_first_1; // @[Monitor.scala 652:27]
  wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode, 1'h0}; // @[Monitor.scala 654:53]
  wire [3:0] _a_opcodes_set_interm_T_1 = _a_opcodes_set_interm_T | 4'h1; // @[Monitor.scala 654:61]
  wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size, 1'h0}; // @[Monitor.scala 655:51]
  wire [2:0] _a_sizes_set_interm_T_1 = _a_sizes_set_interm_T | 3'h1; // @[Monitor.scala 655:59]
  wire [8:0] _GEN_78 = {io_in_a_bits_source, 2'h0}; // @[Monitor.scala 656:79]
  wire [9:0] _a_opcodes_set_T = {{1'd0}, _GEN_78}; // @[Monitor.scala 656:79]
  wire [3:0] a_opcodes_set_interm = a_first_done & a_first_1 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala 652:72 654:28]
  wire [1026:0] _GEN_1 = {{1023'd0}, a_opcodes_set_interm}; // @[Monitor.scala 656:54]
  wire [1026:0] _a_opcodes_set_T_1 = _GEN_1 << _a_opcodes_set_T; // @[Monitor.scala 656:54]
  wire [2:0] a_sizes_set_interm = a_first_done & a_first_1 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala 652:72 655:28]
  wire [1025:0] _GEN_2 = {{1023'd0}, a_sizes_set_interm}; // @[Monitor.scala 657:52]
  wire [1025:0] _a_sizes_set_T_1 = _GEN_2 << _a_opcodes_set_T; // @[Monitor.scala 657:52]
  wire [95:0] _T_593 = inflight >> io_in_a_bits_source; // @[Monitor.scala 658:26]
  wire  _T_595 = ~_T_593[0]; // @[Monitor.scala 658:17]
  wire [127:0] _GEN_16 = a_first_done & a_first_1 ? _a_set_wo_ready_T : 128'h0; // @[Monitor.scala 652:72 653:28]
  wire [1026:0] _GEN_19 = a_first_done & a_first_1 ? _a_opcodes_set_T_1 : 1027'h0; // @[Monitor.scala 652:72 656:28]
  wire [1025:0] _GEN_20 = a_first_done & a_first_1 ? _a_sizes_set_T_1 : 1026'h0; // @[Monitor.scala 652:72 657:28]
  wire  _T_599 = io_in_d_valid & d_first_1; // @[Monitor.scala 671:26]
  wire [127:0] _d_clr_wo_ready_T = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 57:35]
  wire [1038:0] _GEN_3 = {{1023'd0}, _a_opcode_lookup_T_5}; // @[Monitor.scala 677:76]
  wire [1038:0] _d_opcodes_clr_T_5 = _GEN_3 << _a_opcode_lookup_T; // @[Monitor.scala 677:76]
  wire [127:0] _GEN_22 = d_first_done & d_first_1 ? _d_clr_wo_ready_T : 128'h0; // @[Monitor.scala 675:91 676:21]
  wire [1038:0] _GEN_23 = d_first_done & d_first_1 ? _d_opcodes_clr_T_5 : 1039'h0; // @[Monitor.scala 675:91 677:21]
  wire  _same_cycle_resp_T_2 = io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:113]
  wire  same_cycle_resp = _T_588 & io_in_a_bits_source == io_in_d_bits_source; // @[Monitor.scala 681:88]
  wire [95:0] _T_612 = inflight >> io_in_d_bits_source; // @[Monitor.scala 682:25]
  wire  _T_614 = _T_612[0] | same_cycle_resp; // @[Monitor.scala 682:49]
  wire [2:0] _GEN_27 = 3'h2 == io_in_a_bits_opcode ? 3'h1 : 3'h0; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_28 = 3'h3 == io_in_a_bits_opcode ? 3'h1 : _GEN_27; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_29 = 3'h4 == io_in_a_bits_opcode ? 3'h1 : _GEN_28; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_30 = 3'h5 == io_in_a_bits_opcode ? 3'h2 : _GEN_29; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_31 = 3'h6 == io_in_a_bits_opcode ? 3'h4 : _GEN_30; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_32 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_31; // @[Monitor.scala 685:{38,38}]
  wire [2:0] _GEN_39 = 3'h6 == io_in_a_bits_opcode ? 3'h5 : _GEN_30; // @[Monitor.scala 686:{39,39}]
  wire [2:0] _GEN_40 = 3'h7 == io_in_a_bits_opcode ? 3'h4 : _GEN_39; // @[Monitor.scala 686:{39,39}]
  wire  _T_619 = 3'h1 == _GEN_40; // @[Monitor.scala 686:39]
  wire  _T_620 = 3'h1 == _GEN_32 | _T_619; // @[Monitor.scala 685:77]
  wire  _T_624 = io_in_a_bits_size == io_in_d_bits_size; // @[Monitor.scala 687:36]
  wire [3:0] a_opcode_lookup = _a_opcode_lookup_T_7[3:0];
  wire [2:0] _GEN_43 = 3'h2 == a_opcode_lookup[2:0] ? 3'h1 : 3'h0; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_44 = 3'h3 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_43; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_45 = 3'h4 == a_opcode_lookup[2:0] ? 3'h1 : _GEN_44; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_46 = 3'h5 == a_opcode_lookup[2:0] ? 3'h2 : _GEN_45; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_47 = 3'h6 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_46; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_48 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_47; // @[Monitor.scala 689:{38,38}]
  wire [2:0] _GEN_55 = 3'h6 == a_opcode_lookup[2:0] ? 3'h5 : _GEN_46; // @[Monitor.scala 690:{38,38}]
  wire [2:0] _GEN_56 = 3'h7 == a_opcode_lookup[2:0] ? 3'h4 : _GEN_55; // @[Monitor.scala 690:{38,38}]
  wire  _T_631 = 3'h1 == _GEN_56; // @[Monitor.scala 690:38]
  wire  _T_632 = 3'h1 == _GEN_48 | _T_631; // @[Monitor.scala 689:72]
  wire [3:0] a_size_lookup = _a_size_lookup_T_7[3:0];
  wire [3:0] _GEN_82 = {{2'd0}, io_in_d_bits_size}; // @[Monitor.scala 691:36]
  wire  _T_636 = _GEN_82 == a_size_lookup; // @[Monitor.scala 691:36]
  wire  _T_644 = _T_599 & a_first_1 & io_in_a_valid & _same_cycle_resp_T_2; // @[Monitor.scala 694:65]
  wire  _T_648 = ~io_in_d_ready | io_in_a_ready; // @[Monitor.scala 695:32]
  wire [95:0] a_set = _GEN_16[95:0];
  wire [95:0] _inflight_T = inflight | a_set; // @[Monitor.scala 702:27]
  wire [95:0] d_clr = _GEN_22[95:0];
  wire [95:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala 702:38]
  wire [95:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala 702:36]
  wire [383:0] a_opcodes_set = _GEN_19[383:0];
  wire [383:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala 703:43]
  wire [383:0] d_opcodes_clr = _GEN_23[383:0];
  wire [383:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala 703:62]
  wire [383:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala 703:60]
  wire [383:0] a_sizes_set = _GEN_20[383:0];
  wire [383:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala 704:39]
  wire [383:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_opcodes_T_1; // @[Monitor.scala 704:54]
  reg [31:0] watchdog; // @[Monitor.scala 706:27]
  wire  _T_657 = ~(|inflight) | plusarg_reader_out == 32'h0 | watchdog < plusarg_reader_out; // @[Monitor.scala 709:47]
  wire [31:0] _watchdog_T_1 = watchdog + 32'h1; // @[Monitor.scala 711:26]
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_out)
  );
  plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0), .WIDTH(32)) plusarg_reader_1 ( // @[PlusArg.scala 80:11]
    .out(plusarg_reader_1_out)
  );
  always @(posedge clock) begin
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first) begin // @[Edges.scala 235:21]
        a_first_counter <= 1'h0;
      end else begin
        a_first_counter <= a_first_counter1;
      end
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      opcode <= io_in_a_bits_opcode; // @[Monitor.scala 397:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      param <= io_in_a_bits_param; // @[Monitor.scala 398:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      size <= io_in_a_bits_size; // @[Monitor.scala 399:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      source <= io_in_a_bits_source; // @[Monitor.scala 400:15]
    end
    if (a_first_done & a_first) begin // @[Monitor.scala 396:32]
      address <= io_in_a_bits_address; // @[Monitor.scala 401:15]
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first) begin // @[Edges.scala 235:21]
        d_first_counter <= 1'h0;
      end else begin
        d_first_counter <= d_first_counter1;
      end
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      size_1 <= io_in_d_bits_size; // @[Monitor.scala 552:15]
    end
    if (d_first_done & d_first) begin // @[Monitor.scala 549:32]
      source_1 <= io_in_d_bits_source; // @[Monitor.scala 553:15]
    end
    if (reset) begin // @[Monitor.scala 611:27]
      inflight <= 96'h0; // @[Monitor.scala 611:27]
    end else begin
      inflight <= _inflight_T_2; // @[Monitor.scala 702:14]
    end
    if (reset) begin // @[Monitor.scala 613:35]
      inflight_opcodes <= 384'h0; // @[Monitor.scala 613:35]
    end else begin
      inflight_opcodes <= _inflight_opcodes_T_2; // @[Monitor.scala 703:22]
    end
    if (reset) begin // @[Monitor.scala 615:33]
      inflight_sizes <= 384'h0; // @[Monitor.scala 615:33]
    end else begin
      inflight_sizes <= _inflight_sizes_T_2; // @[Monitor.scala 704:20]
    end
    if (reset) begin // @[Edges.scala 228:27]
      a_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (a_first_done) begin // @[Edges.scala 234:17]
      if (a_first_1) begin // @[Edges.scala 235:21]
        a_first_counter_1 <= 1'h0;
      end else begin
        a_first_counter_1 <= a_first_counter1_1;
      end
    end
    if (reset) begin // @[Edges.scala 228:27]
      d_first_counter_1 <= 1'h0; // @[Edges.scala 228:27]
    end else if (d_first_done) begin // @[Edges.scala 234:17]
      if (d_first_1) begin // @[Edges.scala 235:21]
        d_first_counter_1 <= 1'h0;
      end else begin
        d_first_counter_1 <= d_first_counter1_1;
      end
    end
    if (reset) begin // @[Monitor.scala 706:27]
      watchdog <= 32'h0; // @[Monitor.scala 706:27]
    end else if (a_first_done | d_first_done) begin // @[Monitor.scala 712:47]
      watchdog <= 32'h0; // @[Monitor.scala 712:58]
    end else begin
      watchdog <= _watchdog_T_1; // @[Monitor.scala 711:14]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_20 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_20 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_mask_T & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_mask_T) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_69 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_69) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_135 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_135) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_74 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_74) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_82 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_82 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_172 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_172) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid source ID (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get address not aligned to size (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get carries invalid param (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get contains invalid mask (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_148 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_148 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Get is corrupt (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull address not aligned to size (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull carries invalid param (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_195 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_195 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutFull contains invalid mask (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_233 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_233 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_233 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_233 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_233 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_233 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_183 & (io_in_a_valid & _T_233 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_233 & ~reset & ~_T_183) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial carries invalid param (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_269 & (io_in_a_valid & _T_233 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_233 & ~reset & ~_T_269) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_273 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_273 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_273 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_273 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_273 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_273 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_303 & (io_in_a_valid & _T_273 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_273 & ~reset & ~_T_303) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_273 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_273 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_311 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_311 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_311 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_311 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid source ID (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_311 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_311 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical address not aligned to size (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_341 & (io_in_a_valid & _T_311 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_311 & ~reset & ~_T_341) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_311 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_311 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Logical contains invalid mask (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (io_in_a_valid & _T_349 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_349 & ~reset) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (_T_10 & (io_in_a_valid & _T_349 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_349 & ~reset & _T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid source ID (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~is_aligned & (io_in_a_valid & _T_349 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_349 & ~reset & ~is_aligned) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint address not aligned to size (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_379 & (io_in_a_valid & _T_349 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_349 & ~reset & ~_T_379) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_187 & (io_in_a_valid & _T_349 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_349 & ~reset & ~_T_187) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint contains invalid mask (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_78 & (io_in_a_valid & _T_349 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_a_valid & _T_349 & ~reset & ~_T_78) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel Hint is corrupt (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_source_ok_T_10 & (io_in_d_valid & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (io_in_d_valid & _T_2 & ~_source_ok_T_10) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BootROM.scala:84:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_538 & (_T_537 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_537 & ~reset & ~_T_538) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_542 & (_T_537 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_537 & ~reset & ~_T_542) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel param changed within multibeat operation (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_546 & (_T_537 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_537 & ~reset & ~_T_546) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel size changed within multibeat operation (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_550 & (_T_537 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_537 & ~reset & ~_T_550) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel source changed within multibeat operation (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_554 & (_T_537 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_537 & ~reset & ~_T_554) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel address changed with multibeat operation (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_570 & (_T_561 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_561 & _T_2 & ~_T_570) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel size changed within multibeat operation (connected at BootROM.scala:84:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_574 & (_T_561 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_561 & _T_2 & ~_T_574) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel source changed within multibeat operation (connected at BootROM.scala:84:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_595 & (_T_591 & ~reset)) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_591 & ~reset & ~_T_595) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'A' channel re-used a source ID (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_614 & (_T_599 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_599 & _T_2 & ~_T_614) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BootROM.scala:84:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_620 & (_T_599 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_599 & same_cycle_resp & _T_2 & ~_T_620) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at BootROM.scala:84:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_624 & (_T_599 & same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_599 & same_cycle_resp & _T_2 & ~_T_624) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at BootROM.scala:84:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_632 & (_T_599 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_599 & ~same_cycle_resp & _T_2 & ~_T_632) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper opcode response (connected at BootROM.scala:84:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_636 & (_T_599 & ~same_cycle_resp & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_599 & ~same_cycle_resp & _T_2 & ~_T_636) begin
          $fwrite(32'h80000002,
            "Assertion failed: 'D' channel contains improper response size (connected at BootROM.scala:84:18)\n    at Monitor.scala:49 assert(cond, message)\n"
            ); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_648 & (_T_644 & _T_2)) begin
          $fatal; // @[Monitor.scala 49:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_644 & _T_2 & ~_T_648) begin
          $fwrite(32'h80000002,"Assertion failed: ready check\n    at Monitor.scala:49 assert(cond, message)\n"); // @[Monitor.scala 49:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_657 & ~reset) begin
          $fatal; // @[Monitor.scala 42:11]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_657) begin
          $fwrite(32'h80000002,
            "Assertion failed: TileLink timeout expired (connected at BootROM.scala:84:18)\n    at Monitor.scala:42 assert(cond, message)\n"
            ); // @[Monitor.scala 42:11]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  a_first_counter = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  opcode = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  param = _RAND_2[2:0];
  _RAND_3 = {1{`RANDOM}};
  size = _RAND_3[1:0];
  _RAND_4 = {1{`RANDOM}};
  source = _RAND_4[6:0];
  _RAND_5 = {1{`RANDOM}};
  address = _RAND_5[16:0];
  _RAND_6 = {1{`RANDOM}};
  d_first_counter = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  size_1 = _RAND_7[1:0];
  _RAND_8 = {1{`RANDOM}};
  source_1 = _RAND_8[6:0];
  _RAND_9 = {3{`RANDOM}};
  inflight = _RAND_9[95:0];
  _RAND_10 = {12{`RANDOM}};
  inflight_opcodes = _RAND_10[383:0];
  _RAND_11 = {12{`RANDOM}};
  inflight_sizes = _RAND_11[383:0];
  _RAND_12 = {1{`RANDOM}};
  a_first_counter_1 = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  d_first_counter_1 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  watchdog = _RAND_14[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module TLROM(
  input         clock,
  input         reset,
  output        auto_in_a_ready,
  input         auto_in_a_valid,
  input  [2:0]  auto_in_a_bits_opcode,
  input  [2:0]  auto_in_a_bits_param,
  input  [1:0]  auto_in_a_bits_size,
  input  [6:0]  auto_in_a_bits_source,
  input  [16:0] auto_in_a_bits_address,
  input  [3:0]  auto_in_a_bits_mask,
  input         auto_in_a_bits_corrupt,
  input         auto_in_d_ready,
  output        auto_in_d_valid,
  output [1:0]  auto_in_d_bits_size,
  output [6:0]  auto_in_d_bits_source,
  output [31:0] auto_in_d_bits_data
);
  wire  monitor_clock; // @[Nodes.scala 24:25]
  wire  monitor_reset; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_valid; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_opcode; // @[Nodes.scala 24:25]
  wire [2:0] monitor_io_in_a_bits_param; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_a_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_io_in_a_bits_source; // @[Nodes.scala 24:25]
  wire [16:0] monitor_io_in_a_bits_address; // @[Nodes.scala 24:25]
  wire [3:0] monitor_io_in_a_bits_mask; // @[Nodes.scala 24:25]
  wire  monitor_io_in_a_bits_corrupt; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_ready; // @[Nodes.scala 24:25]
  wire  monitor_io_in_d_valid; // @[Nodes.scala 24:25]
  wire [1:0] monitor_io_in_d_bits_size; // @[Nodes.scala 24:25]
  wire [6:0] monitor_io_in_d_bits_source; // @[Nodes.scala 24:25]
  wire [10:0] index = auto_in_a_bits_address[12:2]; // @[BootROM.scala 49:34]
  wire [2:0] high = auto_in_a_bits_address[15:13]; // @[BootROM.scala 50:68]
  wire [31:0] _GEN_1 = 11'h1 == index ? 32'h0 : 32'h6f; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2 = 11'h2 == index ? 32'h0 : _GEN_1; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_3 = 11'h3 == index ? 32'h0 : _GEN_2; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_4 = 11'h4 == index ? 32'h0 : _GEN_3; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_5 = 11'h5 == index ? 32'h0 : _GEN_4; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_6 = 11'h6 == index ? 32'h0 : _GEN_5; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_7 = 11'h7 == index ? 32'h0 : _GEN_6; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_8 = 11'h8 == index ? 32'h0 : _GEN_7; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_9 = 11'h9 == index ? 32'h0 : _GEN_8; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_10 = 11'ha == index ? 32'h0 : _GEN_9; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_11 = 11'hb == index ? 32'h0 : _GEN_10; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_12 = 11'hc == index ? 32'h0 : _GEN_11; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_13 = 11'hd == index ? 32'h0 : _GEN_12; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_14 = 11'he == index ? 32'h0 : _GEN_13; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_15 = 11'hf == index ? 32'h0 : _GEN_14; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_16 = 11'h10 == index ? 32'h8002137 : _GEN_15; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_17 = 11'h11 == index ? 32'hff010113 : _GEN_16; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_18 = 11'h12 == index ? 32'h1fff0097 : _GEN_17; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_19 = 11'h13 == index ? 32'hfb8080e7 : _GEN_18; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_20 = 11'h14 == index ? 32'h6f : _GEN_19; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_21 = 11'h15 == index ? 32'hedfe0dd0 : _GEN_20; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_22 = 11'h16 == index ? 32'ha5130000 : _GEN_21; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_23 = 11'h17 == index ? 32'h38000000 : _GEN_22; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_24 = 11'h18 == index ? 32'h44110000 : _GEN_23; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_25 = 11'h19 == index ? 32'h28000000 : _GEN_24; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_26 = 11'h1a == index ? 32'h11000000 : _GEN_25; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_27 = 11'h1b == index ? 32'h10000000 : _GEN_26; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_28 = 11'h1c == index ? 32'h0 : _GEN_27; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_29 = 11'h1d == index ? 32'h61020000 : _GEN_28; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_30 = 11'h1e == index ? 32'hc110000 : _GEN_29; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_31 = 11'h1f == index ? 32'h0 : _GEN_30; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_32 = 11'h20 == index ? 32'h0 : _GEN_31; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_33 = 11'h21 == index ? 32'h0 : _GEN_32; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_34 = 11'h22 == index ? 32'h0 : _GEN_33; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_35 = 11'h23 == index ? 32'h1000000 : _GEN_34; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_36 = 11'h24 == index ? 32'h0 : _GEN_35; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_37 = 11'h25 == index ? 32'h3000000 : _GEN_36; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_38 = 11'h26 == index ? 32'h4000000 : _GEN_37; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_39 = 11'h27 == index ? 32'h0 : _GEN_38; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_40 = 11'h28 == index ? 32'h1000000 : _GEN_39; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_41 = 11'h29 == index ? 32'h3000000 : _GEN_40; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_42 = 11'h2a == index ? 32'h4000000 : _GEN_41; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_43 = 11'h2b == index ? 32'hf000000 : _GEN_42; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_44 = 11'h2c == index ? 32'h1000000 : _GEN_43; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_45 = 11'h2d == index ? 32'h3000000 : _GEN_44; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_46 = 11'h2e == index ? 32'h21000000 : _GEN_45; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_47 = 11'h2f == index ? 32'h1b000000 : _GEN_46; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_48 = 11'h30 == index ? 32'h65657266 : _GEN_47; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_49 = 11'h31 == index ? 32'h70696863 : _GEN_48; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_50 = 11'h32 == index ? 32'h6f722c73 : _GEN_49; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_51 = 11'h33 == index ? 32'h74656b63 : _GEN_50; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_52 = 11'h34 == index ? 32'h70696863 : _GEN_51; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_53 = 11'h35 == index ? 32'h6b6e752d : _GEN_52; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_54 = 11'h36 == index ? 32'h6e776f6e : _GEN_53; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_55 = 11'h37 == index ? 32'h7665642d : _GEN_54; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_56 = 11'h38 == index ? 32'h0 : _GEN_55; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_57 = 11'h39 == index ? 32'h3000000 : _GEN_56; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_58 = 11'h3a == index ? 32'h1d000000 : _GEN_57; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_59 = 11'h3b == index ? 32'h26000000 : _GEN_58; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_60 = 11'h3c == index ? 32'h65657266 : _GEN_59; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_61 = 11'h3d == index ? 32'h70696863 : _GEN_60; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_62 = 11'h3e == index ? 32'h6f722c73 : _GEN_61; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_63 = 11'h3f == index ? 32'h74656b63 : _GEN_62; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_64 = 11'h40 == index ? 32'h70696863 : _GEN_63; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_65 = 11'h41 == index ? 32'h6b6e752d : _GEN_64; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_66 = 11'h42 == index ? 32'h6e776f6e : _GEN_65; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_67 = 11'h43 == index ? 32'h0 : _GEN_66; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_68 = 11'h44 == index ? 32'h1000000 : _GEN_67; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_69 = 11'h45 == index ? 32'h61696c61 : _GEN_68; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_70 = 11'h46 == index ? 32'h736573 : _GEN_69; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_71 = 11'h47 == index ? 32'h3000000 : _GEN_70; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_72 = 11'h48 == index ? 32'h15000000 : _GEN_71; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_73 = 11'h49 == index ? 32'h2c000000 : _GEN_72; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_74 = 11'h4a == index ? 32'h636f732f : _GEN_73; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_75 = 11'h4b == index ? 32'h7265732f : _GEN_74; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_76 = 11'h4c == index ? 32'h406c6169 : _GEN_75; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_77 = 11'h4d == index ? 32'h31303031 : _GEN_76; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_78 = 11'h4e == index ? 32'h30303033 : _GEN_77; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_79 = 11'h4f == index ? 32'h0 : _GEN_78; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_80 = 11'h50 == index ? 32'h3000000 : _GEN_79; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_81 = 11'h51 == index ? 32'h15000000 : _GEN_80; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_82 = 11'h52 == index ? 32'h34000000 : _GEN_81; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_83 = 11'h53 == index ? 32'h636f732f : _GEN_82; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_84 = 11'h54 == index ? 32'h7265732f : _GEN_83; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_85 = 11'h55 == index ? 32'h406c6169 : _GEN_84; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_86 = 11'h56 == index ? 32'h32303031 : _GEN_85; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_87 = 11'h57 == index ? 32'h30303033 : _GEN_86; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_88 = 11'h58 == index ? 32'h0 : _GEN_87; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_89 = 11'h59 == index ? 32'h3000000 : _GEN_88; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_90 = 11'h5a == index ? 32'h15000000 : _GEN_89; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_91 = 11'h5b == index ? 32'h3c000000 : _GEN_90; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_92 = 11'h5c == index ? 32'h636f732f : _GEN_91; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_93 = 11'h5d == index ? 32'h7265732f : _GEN_92; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_94 = 11'h5e == index ? 32'h406c6169 : _GEN_93; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_95 = 11'h5f == index ? 32'h33303031 : _GEN_94; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_96 = 11'h60 == index ? 32'h30303033 : _GEN_95; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_97 = 11'h61 == index ? 32'h0 : _GEN_96; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_98 = 11'h62 == index ? 32'h3000000 : _GEN_97; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_99 = 11'h63 == index ? 32'h15000000 : _GEN_98; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_100 = 11'h64 == index ? 32'h44000000 : _GEN_99; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_101 = 11'h65 == index ? 32'h636f732f : _GEN_100; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_102 = 11'h66 == index ? 32'h7265732f : _GEN_101; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_103 = 11'h67 == index ? 32'h406c6169 : _GEN_102; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_104 = 11'h68 == index ? 32'h34303031 : _GEN_103; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_105 = 11'h69 == index ? 32'h30303033 : _GEN_104; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_106 = 11'h6a == index ? 32'h0 : _GEN_105; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_107 = 11'h6b == index ? 32'h3000000 : _GEN_106; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_108 = 11'h6c == index ? 32'h15000000 : _GEN_107; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_109 = 11'h6d == index ? 32'h4c000000 : _GEN_108; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_110 = 11'h6e == index ? 32'h636f732f : _GEN_109; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_111 = 11'h6f == index ? 32'h7265732f : _GEN_110; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_112 = 11'h70 == index ? 32'h406c6169 : _GEN_111; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_113 = 11'h71 == index ? 32'h35303031 : _GEN_112; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_114 = 11'h72 == index ? 32'h30303033 : _GEN_113; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_115 = 11'h73 == index ? 32'h0 : _GEN_114; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_116 = 11'h74 == index ? 32'h2000000 : _GEN_115; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_117 = 11'h75 == index ? 32'h1000000 : _GEN_116; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_118 = 11'h76 == index ? 32'h73757063 : _GEN_117; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_119 = 11'h77 == index ? 32'h0 : _GEN_118; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_120 = 11'h78 == index ? 32'h3000000 : _GEN_119; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_121 = 11'h79 == index ? 32'h4000000 : _GEN_120; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_122 = 11'h7a == index ? 32'h0 : _GEN_121; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_123 = 11'h7b == index ? 32'h1000000 : _GEN_122; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_124 = 11'h7c == index ? 32'h3000000 : _GEN_123; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_125 = 11'h7d == index ? 32'h4000000 : _GEN_124; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_126 = 11'h7e == index ? 32'hf000000 : _GEN_125; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_127 = 11'h7f == index ? 32'h0 : _GEN_126; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_128 = 11'h80 == index ? 32'h3000000 : _GEN_127; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_129 = 11'h81 == index ? 32'h4000000 : _GEN_128; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_130 = 11'h82 == index ? 32'h54000000 : _GEN_129; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_131 = 11'h83 == index ? 32'h800000 : _GEN_130; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_132 = 11'h84 == index ? 32'h1000000 : _GEN_131; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_133 = 11'h85 == index ? 32'h40757063 : _GEN_132; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_134 = 11'h86 == index ? 32'h30 : _GEN_133; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_135 = 11'h87 == index ? 32'h3000000 : _GEN_134; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_136 = 11'h88 == index ? 32'h4000000 : _GEN_135; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_137 = 11'h89 == index ? 32'h67000000 : _GEN_136; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_138 = 11'h8a == index ? 32'h0 : _GEN_137; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_139 = 11'h8b == index ? 32'h3000000 : _GEN_138; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_140 = 11'h8c == index ? 32'h15000000 : _GEN_139; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_141 = 11'h8d == index ? 32'h1b000000 : _GEN_140; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_142 = 11'h8e == index ? 32'h69666973 : _GEN_141; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_143 = 11'h8f == index ? 32'h722c6576 : _GEN_142; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_144 = 11'h90 == index ? 32'h656b636f : _GEN_143; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_145 = 11'h91 == index ? 32'h72003074 : _GEN_144; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_146 = 11'h92 == index ? 32'h76637369 : _GEN_145; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_147 = 11'h93 == index ? 32'h0 : _GEN_146; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_148 = 11'h94 == index ? 32'h3000000 : _GEN_147; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_149 = 11'h95 == index ? 32'h4000000 : _GEN_148; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_150 = 11'h96 == index ? 32'h77000000 : _GEN_149; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_151 = 11'h97 == index ? 32'h40000000 : _GEN_150; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_152 = 11'h98 == index ? 32'h3000000 : _GEN_151; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_153 = 11'h99 == index ? 32'h4000000 : _GEN_152; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_154 = 11'h9a == index ? 32'h8a000000 : _GEN_153; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_155 = 11'h9b == index ? 32'h40000000 : _GEN_154; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_156 = 11'h9c == index ? 32'h3000000 : _GEN_155; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_157 = 11'h9d == index ? 32'h4000000 : _GEN_156; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_158 = 11'h9e == index ? 32'h97000000 : _GEN_157; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_159 = 11'h9f == index ? 32'h200000 : _GEN_158; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_160 = 11'ha0 == index ? 32'h3000000 : _GEN_159; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_161 = 11'ha1 == index ? 32'h4000000 : _GEN_160; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_162 = 11'ha2 == index ? 32'ha4000000 : _GEN_161; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_163 = 11'ha3 == index ? 32'h757063 : _GEN_162; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_164 = 11'ha4 == index ? 32'h3000000 : _GEN_163; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_165 = 11'ha5 == index ? 32'h4000000 : _GEN_164; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_166 = 11'ha6 == index ? 32'hb0000000 : _GEN_165; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_167 = 11'ha7 == index ? 32'h2000000 : _GEN_166; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_168 = 11'ha8 == index ? 32'h3000000 : _GEN_167; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_169 = 11'ha9 == index ? 32'h4000000 : _GEN_168; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_170 = 11'haa == index ? 32'hcf000000 : _GEN_169; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_171 = 11'hab == index ? 32'h40000000 : _GEN_170; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_172 = 11'hac == index ? 32'h3000000 : _GEN_171; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_173 = 11'had == index ? 32'h4000000 : _GEN_172; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_174 = 11'hae == index ? 32'he2000000 : _GEN_173; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_175 = 11'haf == index ? 32'h80000000 : _GEN_174; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_176 = 11'hb0 == index ? 32'h3000000 : _GEN_175; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_177 = 11'hb1 == index ? 32'h4000000 : _GEN_176; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_178 = 11'hb2 == index ? 32'hef000000 : _GEN_177; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_179 = 11'hb3 == index ? 32'h400000 : _GEN_178; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_180 = 11'hb4 == index ? 32'h3000000 : _GEN_179; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_181 = 11'hb5 == index ? 32'h4000000 : _GEN_180; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_182 = 11'hb6 == index ? 32'hfc000000 : _GEN_181; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_183 = 11'hb7 == index ? 32'h1000000 : _GEN_182; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_184 = 11'hb8 == index ? 32'h3000000 : _GEN_183; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_185 = 11'hb9 == index ? 32'h4000000 : _GEN_184; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_186 = 11'hba == index ? 32'hd010000 : _GEN_185; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_187 = 11'hbb == index ? 32'h0 : _GEN_186; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_188 = 11'hbc == index ? 32'h3000000 : _GEN_187; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_189 = 11'hbd == index ? 32'h9000000 : _GEN_188; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_190 = 11'hbe == index ? 32'h11010000 : _GEN_189; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_191 = 11'hbf == index ? 32'h32337672 : _GEN_190; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_192 = 11'hc0 == index ? 32'h63616d69 : _GEN_191; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_193 = 11'hc1 == index ? 32'h0 : _GEN_192; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_194 = 11'hc2 == index ? 32'h3000000 : _GEN_193; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_195 = 11'hc3 == index ? 32'h4000000 : _GEN_194; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_196 = 11'hc4 == index ? 32'h1b010000 : _GEN_195; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_197 = 11'hc5 == index ? 32'h4000000 : _GEN_196; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_198 = 11'hc6 == index ? 32'h3000000 : _GEN_197; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_199 = 11'hc7 == index ? 32'h4000000 : _GEN_198; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_200 = 11'hc8 == index ? 32'h30010000 : _GEN_199; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_201 = 11'hc9 == index ? 32'h8000000 : _GEN_200; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_202 = 11'hca == index ? 32'h3000000 : _GEN_201; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_203 = 11'hcb == index ? 32'h4000000 : _GEN_202; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_204 = 11'hcc == index ? 32'h41010000 : _GEN_203; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_205 = 11'hcd == index ? 32'h2000000 : _GEN_204; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_206 = 11'hce == index ? 32'h3000000 : _GEN_205; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_207 = 11'hcf == index ? 32'h5000000 : _GEN_206; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_208 = 11'hd0 == index ? 32'h4d010000 : _GEN_207; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_209 = 11'hd1 == index ? 32'h79616b6f : _GEN_208; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_210 = 11'hd2 == index ? 32'h0 : _GEN_209; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_211 = 11'hd3 == index ? 32'h3000000 : _GEN_210; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_212 = 11'hd4 == index ? 32'h4000000 : _GEN_211; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_213 = 11'hd5 == index ? 32'h54000000 : _GEN_212; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_214 = 11'hd6 == index ? 32'h800000 : _GEN_213; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_215 = 11'hd7 == index ? 32'h1000000 : _GEN_214; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_216 = 11'hd8 == index ? 32'h65746e69 : _GEN_215; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_217 = 11'hd9 == index ? 32'h70757272 : _GEN_216; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_218 = 11'hda == index ? 32'h6f632d74 : _GEN_217; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_219 = 11'hdb == index ? 32'h6f72746e : _GEN_218; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_220 = 11'hdc == index ? 32'h72656c6c : _GEN_219; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_221 = 11'hdd == index ? 32'h0 : _GEN_220; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_222 = 11'hde == index ? 32'h3000000 : _GEN_221; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_223 = 11'hdf == index ? 32'h4000000 : _GEN_222; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_224 = 11'he0 == index ? 32'h54010000 : _GEN_223; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_225 = 11'he1 == index ? 32'h1000000 : _GEN_224; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_226 = 11'he2 == index ? 32'h3000000 : _GEN_225; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_227 = 11'he3 == index ? 32'hf000000 : _GEN_226; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_228 = 11'he4 == index ? 32'h1b000000 : _GEN_227; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_229 = 11'he5 == index ? 32'h63736972 : _GEN_228; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_230 = 11'he6 == index ? 32'h70632c76 : _GEN_229; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_231 = 11'he7 == index ? 32'h6e692d75 : _GEN_230; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_232 = 11'he8 == index ? 32'h6374 : _GEN_231; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_233 = 11'he9 == index ? 32'h3000000 : _GEN_232; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_234 = 11'hea == index ? 32'h0 : _GEN_233; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_235 = 11'heb == index ? 32'h65010000 : _GEN_234; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_236 = 11'hec == index ? 32'h3000000 : _GEN_235; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_237 = 11'hed == index ? 32'h4000000 : _GEN_236; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_238 = 11'hee == index ? 32'h7a010000 : _GEN_237; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_239 = 11'hef == index ? 32'h4000000 : _GEN_238; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_240 = 11'hf0 == index ? 32'h2000000 : _GEN_239; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_241 = 11'hf1 == index ? 32'h2000000 : _GEN_240; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_242 = 11'hf2 == index ? 32'h2000000 : _GEN_241; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_243 = 11'hf3 == index ? 32'h1000000 : _GEN_242; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_244 = 11'hf4 == index ? 32'h636f73 : _GEN_243; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_245 = 11'hf5 == index ? 32'h3000000 : _GEN_244; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_246 = 11'hf6 == index ? 32'h4000000 : _GEN_245; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_247 = 11'hf7 == index ? 32'h0 : _GEN_246; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_248 = 11'hf8 == index ? 32'h1000000 : _GEN_247; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_249 = 11'hf9 == index ? 32'h3000000 : _GEN_248; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_250 = 11'hfa == index ? 32'h4000000 : _GEN_249; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_251 = 11'hfb == index ? 32'hf000000 : _GEN_250; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_252 = 11'hfc == index ? 32'h1000000 : _GEN_251; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_253 = 11'hfd == index ? 32'h3000000 : _GEN_252; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_254 = 11'hfe == index ? 32'h2c000000 : _GEN_253; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_255 = 11'hff == index ? 32'h1b000000 : _GEN_254; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_256 = 11'h100 == index ? 32'h65657266 : _GEN_255; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_257 = 11'h101 == index ? 32'h70696863 : _GEN_256; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_258 = 11'h102 == index ? 32'h6f722c73 : _GEN_257; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_259 = 11'h103 == index ? 32'h74656b63 : _GEN_258; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_260 = 11'h104 == index ? 32'h70696863 : _GEN_259; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_261 = 11'h105 == index ? 32'h6b6e752d : _GEN_260; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_262 = 11'h106 == index ? 32'h6e776f6e : _GEN_261; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_263 = 11'h107 == index ? 32'h636f732d : _GEN_262; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_264 = 11'h108 == index ? 32'h6d697300 : _GEN_263; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_265 = 11'h109 == index ? 32'h2d656c70 : _GEN_264; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_266 = 11'h10a == index ? 32'h737562 : _GEN_265; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_267 = 11'h10b == index ? 32'h3000000 : _GEN_266; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_268 = 11'h10c == index ? 32'h0 : _GEN_267; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_269 = 11'h10d == index ? 32'h82010000 : _GEN_268; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_270 = 11'h10e == index ? 32'h1000000 : _GEN_269; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_271 = 11'h10f == index ? 32'h406e6f61 : _GEN_270; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_272 = 11'h110 == index ? 32'h30303031 : _GEN_271; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_273 = 11'h111 == index ? 32'h30303030 : _GEN_272; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_274 = 11'h112 == index ? 32'h0 : _GEN_273; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_275 = 11'h113 == index ? 32'h3000000 : _GEN_274; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_276 = 11'h114 == index ? 32'hc000000 : _GEN_275; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_277 = 11'h115 == index ? 32'h1b000000 : _GEN_276; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_278 = 11'h116 == index ? 32'h69666973 : _GEN_277; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_279 = 11'h117 == index ? 32'h612c6576 : _GEN_278; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_280 = 11'h118 == index ? 32'h306e6f : _GEN_279; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_281 = 11'h119 == index ? 32'h3000000 : _GEN_280; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_282 = 11'h11a == index ? 32'h4000000 : _GEN_281; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_283 = 11'h11b == index ? 32'h89010000 : _GEN_282; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_284 = 11'h11c == index ? 32'h3000000 : _GEN_283; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_285 = 11'h11d == index ? 32'h3000000 : _GEN_284; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_286 = 11'h11e == index ? 32'h8000000 : _GEN_285; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_287 = 11'h11f == index ? 32'h9a010000 : _GEN_286; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_288 = 11'h120 == index ? 32'h1000000 : _GEN_287; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_289 = 11'h121 == index ? 32'h2000000 : _GEN_288; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_290 = 11'h122 == index ? 32'h3000000 : _GEN_289; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_291 = 11'h123 == index ? 32'h8000000 : _GEN_290; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_292 = 11'h124 == index ? 32'hd010000 : _GEN_291; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_293 = 11'h125 == index ? 32'h10 : _GEN_292; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_294 = 11'h126 == index ? 32'h100000 : _GEN_293; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_295 = 11'h127 == index ? 32'h3000000 : _GEN_294; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_296 = 11'h128 == index ? 32'h8000000 : _GEN_295; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_297 = 11'h129 == index ? 32'ha5010000 : _GEN_296; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_298 = 11'h12a == index ? 32'h746e6f63 : _GEN_297; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_299 = 11'h12b == index ? 32'h6c6f72 : _GEN_298; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_300 = 11'h12c == index ? 32'h2000000 : _GEN_299; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_301 = 11'h12d == index ? 32'h1000000 : _GEN_300; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_302 = 11'h12e == index ? 32'h6e696c63 : _GEN_301; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_303 = 11'h12f == index ? 32'h30324074 : _GEN_302; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_304 = 11'h130 == index ? 32'h30303030 : _GEN_303; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_305 = 11'h131 == index ? 32'h30 : _GEN_304; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_306 = 11'h132 == index ? 32'h3000000 : _GEN_305; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_307 = 11'h133 == index ? 32'hd000000 : _GEN_306; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_308 = 11'h134 == index ? 32'h1b000000 : _GEN_307; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_309 = 11'h135 == index ? 32'h63736972 : _GEN_308; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_310 = 11'h136 == index ? 32'h6c632c76 : _GEN_309; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_311 = 11'h137 == index ? 32'h30746e69 : _GEN_310; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_312 = 11'h138 == index ? 32'h0 : _GEN_311; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_313 = 11'h139 == index ? 32'h3000000 : _GEN_312; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_314 = 11'h13a == index ? 32'h10000000 : _GEN_313; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_315 = 11'h13b == index ? 32'haf010000 : _GEN_314; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_316 = 11'h13c == index ? 32'h4000000 : _GEN_315; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_317 = 11'h13d == index ? 32'h3000000 : _GEN_316; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_318 = 11'h13e == index ? 32'h4000000 : _GEN_317; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_319 = 11'h13f == index ? 32'h7000000 : _GEN_318; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_320 = 11'h140 == index ? 32'h3000000 : _GEN_319; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_321 = 11'h141 == index ? 32'h8000000 : _GEN_320; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_322 = 11'h142 == index ? 32'hd010000 : _GEN_321; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_323 = 11'h143 == index ? 32'h2 : _GEN_322; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_324 = 11'h144 == index ? 32'h100 : _GEN_323; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_325 = 11'h145 == index ? 32'h3000000 : _GEN_324; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_326 = 11'h146 == index ? 32'h8000000 : _GEN_325; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_327 = 11'h147 == index ? 32'ha5010000 : _GEN_326; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_328 = 11'h148 == index ? 32'h746e6f63 : _GEN_327; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_329 = 11'h149 == index ? 32'h6c6f72 : _GEN_328; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_330 = 11'h14a == index ? 32'h2000000 : _GEN_329; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_331 = 11'h14b == index ? 32'h1000000 : _GEN_330; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_332 = 11'h14c == index ? 32'h75626564 : _GEN_331; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_333 = 11'h14d == index ? 32'h6f632d67 : _GEN_332; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_334 = 11'h14e == index ? 32'h6f72746e : _GEN_333; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_335 = 11'h14f == index ? 32'h72656c6c : _GEN_334; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_336 = 11'h150 == index ? 32'h3040 : _GEN_335; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_337 = 11'h151 == index ? 32'h3000000 : _GEN_336; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_338 = 11'h152 == index ? 32'h21000000 : _GEN_337; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_339 = 11'h153 == index ? 32'h1b000000 : _GEN_338; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_340 = 11'h154 == index ? 32'h69666973 : _GEN_339; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_341 = 11'h155 == index ? 32'h642c6576 : _GEN_340; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_342 = 11'h156 == index ? 32'h67756265 : _GEN_341; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_343 = 11'h157 == index ? 32'h3331302d : _GEN_342; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_344 = 11'h158 == index ? 32'h73697200 : _GEN_343; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_345 = 11'h159 == index ? 32'h642c7663 : _GEN_344; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_346 = 11'h15a == index ? 32'h67756265 : _GEN_345; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_347 = 11'h15b == index ? 32'h3331302d : _GEN_346; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_348 = 11'h15c == index ? 32'h0 : _GEN_347; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_349 = 11'h15d == index ? 32'h3000000 : _GEN_348; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_350 = 11'h15e == index ? 32'h5000000 : _GEN_349; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_351 = 11'h15f == index ? 32'hc3010000 : _GEN_350; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_352 = 11'h160 == index ? 32'h6761746a : _GEN_351; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_353 = 11'h161 == index ? 32'h0 : _GEN_352; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_354 = 11'h162 == index ? 32'h3000000 : _GEN_353; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_355 = 11'h163 == index ? 32'h8000000 : _GEN_354; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_356 = 11'h164 == index ? 32'haf010000 : _GEN_355; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_357 = 11'h165 == index ? 32'h4000000 : _GEN_356; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_358 = 11'h166 == index ? 32'hffff0000 : _GEN_357; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_359 = 11'h167 == index ? 32'h3000000 : _GEN_358; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_360 = 11'h168 == index ? 32'h8000000 : _GEN_359; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_361 = 11'h169 == index ? 32'hd010000 : _GEN_360; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_362 = 11'h16a == index ? 32'h0 : _GEN_361; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_363 = 11'h16b == index ? 32'h100000 : _GEN_362; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_364 = 11'h16c == index ? 32'h3000000 : _GEN_363; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_365 = 11'h16d == index ? 32'h8000000 : _GEN_364; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_366 = 11'h16e == index ? 32'ha5010000 : _GEN_365; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_367 = 11'h16f == index ? 32'h746e6f63 : _GEN_366; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_368 = 11'h170 == index ? 32'h6c6f72 : _GEN_367; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_369 = 11'h171 == index ? 32'h2000000 : _GEN_368; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_370 = 11'h172 == index ? 32'h1000000 : _GEN_369; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_371 = 11'h173 == index ? 32'h6f727265 : _GEN_370; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_372 = 11'h174 == index ? 32'h65642d72 : _GEN_371; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_373 = 11'h175 == index ? 32'h65636976 : _GEN_372; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_374 = 11'h176 == index ? 32'h30303340 : _GEN_373; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_375 = 11'h177 == index ? 32'h30 : _GEN_374; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_376 = 11'h178 == index ? 32'h3000000 : _GEN_375; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_377 = 11'h179 == index ? 32'he000000 : _GEN_376; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_378 = 11'h17a == index ? 32'h1b000000 : _GEN_377; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_379 = 11'h17b == index ? 32'h69666973 : _GEN_378; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_380 = 11'h17c == index ? 32'h652c6576 : _GEN_379; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_381 = 11'h17d == index ? 32'h726f7272 : _GEN_380; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_382 = 11'h17e == index ? 32'h30 : _GEN_381; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_383 = 11'h17f == index ? 32'h3000000 : _GEN_382; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_384 = 11'h180 == index ? 32'h8000000 : _GEN_383; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_385 = 11'h181 == index ? 32'hd010000 : _GEN_384; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_386 = 11'h182 == index ? 32'h300000 : _GEN_385; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_387 = 11'h183 == index ? 32'h100000 : _GEN_386; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_388 = 11'h184 == index ? 32'h2000000 : _GEN_387; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_389 = 11'h185 == index ? 32'h1000000 : _GEN_388; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_390 = 11'h186 == index ? 32'h6f697067 : _GEN_389; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_391 = 11'h187 == index ? 32'h30303140 : _GEN_390; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_392 = 11'h188 == index ? 32'h30303231 : _GEN_391; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_393 = 11'h189 == index ? 32'h30 : _GEN_392; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_394 = 11'h18a == index ? 32'h3000000 : _GEN_393; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_395 = 11'h18b == index ? 32'h4000000 : _GEN_394; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_396 = 11'h18c == index ? 32'hd0010000 : _GEN_395; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_397 = 11'h18d == index ? 32'h2000000 : _GEN_396; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_398 = 11'h18e == index ? 32'h3000000 : _GEN_397; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_399 = 11'h18f == index ? 32'h4000000 : _GEN_398; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_400 = 11'h190 == index ? 32'h54010000 : _GEN_399; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_401 = 11'h191 == index ? 32'h2000000 : _GEN_400; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_402 = 11'h192 == index ? 32'h3000000 : _GEN_401; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_403 = 11'h193 == index ? 32'h4000000 : _GEN_402; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_404 = 11'h194 == index ? 32'hdc010000 : _GEN_403; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_405 = 11'h195 == index ? 32'h5000000 : _GEN_404; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_406 = 11'h196 == index ? 32'h3000000 : _GEN_405; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_407 = 11'h197 == index ? 32'h1a000000 : _GEN_406; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_408 = 11'h198 == index ? 32'h1b000000 : _GEN_407; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_409 = 11'h199 == index ? 32'h69666973 : _GEN_408; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_410 = 11'h19a == index ? 32'h672c6576 : _GEN_409; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_411 = 11'h19b == index ? 32'h306f6970 : _GEN_410; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_412 = 11'h19c == index ? 32'h66697300 : _GEN_411; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_413 = 11'h19d == index ? 32'h2c657669 : _GEN_412; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_414 = 11'h19e == index ? 32'h6f697067 : _GEN_413; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_415 = 11'h19f == index ? 32'h31 : _GEN_414; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_416 = 11'h1a0 == index ? 32'h3000000 : _GEN_415; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_417 = 11'h1a1 == index ? 32'h0 : _GEN_416; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_418 = 11'h1a2 == index ? 32'he3010000 : _GEN_417; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_419 = 11'h1a3 == index ? 32'h3000000 : _GEN_418; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_420 = 11'h1a4 == index ? 32'h0 : _GEN_419; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_421 = 11'h1a5 == index ? 32'h65010000 : _GEN_420; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_422 = 11'h1a6 == index ? 32'h3000000 : _GEN_421; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_423 = 11'h1a7 == index ? 32'h4000000 : _GEN_422; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_424 = 11'h1a8 == index ? 32'h89010000 : _GEN_423; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_425 = 11'h1a9 == index ? 32'h3000000 : _GEN_424; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_426 = 11'h1aa == index ? 32'h3000000 : _GEN_425; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_427 = 11'h1ab == index ? 32'h80000000 : _GEN_426; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_428 = 11'h1ac == index ? 32'h9a010000 : _GEN_427; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_429 = 11'h1ad == index ? 32'hb000000 : _GEN_428; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_430 = 11'h1ae == index ? 32'hc000000 : _GEN_429; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_431 = 11'h1af == index ? 32'hd000000 : _GEN_430; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_432 = 11'h1b0 == index ? 32'he000000 : _GEN_431; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_433 = 11'h1b1 == index ? 32'hf000000 : _GEN_432; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_434 = 11'h1b2 == index ? 32'h10000000 : _GEN_433; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_435 = 11'h1b3 == index ? 32'h11000000 : _GEN_434; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_436 = 11'h1b4 == index ? 32'h12000000 : _GEN_435; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_437 = 11'h1b5 == index ? 32'h13000000 : _GEN_436; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_438 = 11'h1b6 == index ? 32'h14000000 : _GEN_437; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_439 = 11'h1b7 == index ? 32'h15000000 : _GEN_438; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_440 = 11'h1b8 == index ? 32'h16000000 : _GEN_439; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_441 = 11'h1b9 == index ? 32'h17000000 : _GEN_440; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_442 = 11'h1ba == index ? 32'h18000000 : _GEN_441; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_443 = 11'h1bb == index ? 32'h19000000 : _GEN_442; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_444 = 11'h1bc == index ? 32'h1a000000 : _GEN_443; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_445 = 11'h1bd == index ? 32'h1b000000 : _GEN_444; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_446 = 11'h1be == index ? 32'h1c000000 : _GEN_445; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_447 = 11'h1bf == index ? 32'h1d000000 : _GEN_446; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_448 = 11'h1c0 == index ? 32'h1e000000 : _GEN_447; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_449 = 11'h1c1 == index ? 32'h1f000000 : _GEN_448; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_450 = 11'h1c2 == index ? 32'h20000000 : _GEN_449; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_451 = 11'h1c3 == index ? 32'h21000000 : _GEN_450; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_452 = 11'h1c4 == index ? 32'h22000000 : _GEN_451; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_453 = 11'h1c5 == index ? 32'h23000000 : _GEN_452; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_454 = 11'h1c6 == index ? 32'h24000000 : _GEN_453; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_455 = 11'h1c7 == index ? 32'h25000000 : _GEN_454; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_456 = 11'h1c8 == index ? 32'h26000000 : _GEN_455; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_457 = 11'h1c9 == index ? 32'h27000000 : _GEN_456; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_458 = 11'h1ca == index ? 32'h28000000 : _GEN_457; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_459 = 11'h1cb == index ? 32'h29000000 : _GEN_458; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_460 = 11'h1cc == index ? 32'h2a000000 : _GEN_459; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_461 = 11'h1cd == index ? 32'h3000000 : _GEN_460; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_462 = 11'h1ce == index ? 32'h8000000 : _GEN_461; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_463 = 11'h1cf == index ? 32'hd010000 : _GEN_462; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_464 = 11'h1d0 == index ? 32'h200110 : _GEN_463; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_465 = 11'h1d1 == index ? 32'h100000 : _GEN_464; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_466 = 11'h1d2 == index ? 32'h3000000 : _GEN_465; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_467 = 11'h1d3 == index ? 32'h8000000 : _GEN_466; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_468 = 11'h1d4 == index ? 32'ha5010000 : _GEN_467; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_469 = 11'h1d5 == index ? 32'h746e6f63 : _GEN_468; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_470 = 11'h1d6 == index ? 32'h6c6f72 : _GEN_469; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_471 = 11'h1d7 == index ? 32'h2000000 : _GEN_470; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_472 = 11'h1d8 == index ? 32'h1000000 : _GEN_471; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_473 = 11'h1d9 == index ? 32'h40633269 : _GEN_472; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_474 = 11'h1da == index ? 32'h31303031 : _GEN_473; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_475 = 11'h1db == index ? 32'h30303036 : _GEN_474; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_476 = 11'h1dc == index ? 32'h0 : _GEN_475; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_477 = 11'h1dd == index ? 32'h3000000 : _GEN_476; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_478 = 11'h1de == index ? 32'h4000000 : _GEN_477; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_479 = 11'h1df == index ? 32'hdc010000 : _GEN_478; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_480 = 11'h1e0 == index ? 32'h5000000 : _GEN_479; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_481 = 11'h1e1 == index ? 32'h3000000 : _GEN_480; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_482 = 11'h1e2 == index ? 32'hc000000 : _GEN_481; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_483 = 11'h1e3 == index ? 32'h1b000000 : _GEN_482; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_484 = 11'h1e4 == index ? 32'h69666973 : _GEN_483; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_485 = 11'h1e5 == index ? 32'h692c6576 : _GEN_484; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_486 = 11'h1e6 == index ? 32'h306332 : _GEN_485; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_487 = 11'h1e7 == index ? 32'h3000000 : _GEN_486; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_488 = 11'h1e8 == index ? 32'h4000000 : _GEN_487; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_489 = 11'h1e9 == index ? 32'h89010000 : _GEN_488; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_490 = 11'h1ea == index ? 32'h3000000 : _GEN_489; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_491 = 11'h1eb == index ? 32'h3000000 : _GEN_490; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_492 = 11'h1ec == index ? 32'h4000000 : _GEN_491; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_493 = 11'h1ed == index ? 32'h9a010000 : _GEN_492; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_494 = 11'h1ee == index ? 32'h37000000 : _GEN_493; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_495 = 11'h1ef == index ? 32'h3000000 : _GEN_494; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_496 = 11'h1f0 == index ? 32'h8000000 : _GEN_495; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_497 = 11'h1f1 == index ? 32'hd010000 : _GEN_496; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_498 = 11'h1f2 == index ? 32'h600110 : _GEN_497; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_499 = 11'h1f3 == index ? 32'h100000 : _GEN_498; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_500 = 11'h1f4 == index ? 32'h3000000 : _GEN_499; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_501 = 11'h1f5 == index ? 32'h8000000 : _GEN_500; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_502 = 11'h1f6 == index ? 32'ha5010000 : _GEN_501; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_503 = 11'h1f7 == index ? 32'h746e6f63 : _GEN_502; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_504 = 11'h1f8 == index ? 32'h6c6f72 : _GEN_503; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_505 = 11'h1f9 == index ? 32'h2000000 : _GEN_504; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_506 = 11'h1fa == index ? 32'h1000000 : _GEN_505; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_507 = 11'h1fb == index ? 32'h40633269 : _GEN_506; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_508 = 11'h1fc == index ? 32'h32303031 : _GEN_507; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_509 = 11'h1fd == index ? 32'h30303036 : _GEN_508; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_510 = 11'h1fe == index ? 32'h0 : _GEN_509; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_511 = 11'h1ff == index ? 32'h3000000 : _GEN_510; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_512 = 11'h200 == index ? 32'h4000000 : _GEN_511; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_513 = 11'h201 == index ? 32'hdc010000 : _GEN_512; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_514 = 11'h202 == index ? 32'h5000000 : _GEN_513; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_515 = 11'h203 == index ? 32'h3000000 : _GEN_514; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_516 = 11'h204 == index ? 32'hc000000 : _GEN_515; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_517 = 11'h205 == index ? 32'h1b000000 : _GEN_516; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_518 = 11'h206 == index ? 32'h69666973 : _GEN_517; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_519 = 11'h207 == index ? 32'h692c6576 : _GEN_518; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_520 = 11'h208 == index ? 32'h306332 : _GEN_519; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_521 = 11'h209 == index ? 32'h3000000 : _GEN_520; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_522 = 11'h20a == index ? 32'h4000000 : _GEN_521; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_523 = 11'h20b == index ? 32'h89010000 : _GEN_522; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_524 = 11'h20c == index ? 32'h3000000 : _GEN_523; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_525 = 11'h20d == index ? 32'h3000000 : _GEN_524; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_526 = 11'h20e == index ? 32'h4000000 : _GEN_525; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_527 = 11'h20f == index ? 32'h9a010000 : _GEN_526; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_528 = 11'h210 == index ? 32'h38000000 : _GEN_527; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_529 = 11'h211 == index ? 32'h3000000 : _GEN_528; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_530 = 11'h212 == index ? 32'h8000000 : _GEN_529; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_531 = 11'h213 == index ? 32'hd010000 : _GEN_530; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_532 = 11'h214 == index ? 32'h600210 : _GEN_531; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_533 = 11'h215 == index ? 32'h100000 : _GEN_532; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_534 = 11'h216 == index ? 32'h3000000 : _GEN_533; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_535 = 11'h217 == index ? 32'h8000000 : _GEN_534; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_536 = 11'h218 == index ? 32'ha5010000 : _GEN_535; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_537 = 11'h219 == index ? 32'h746e6f63 : _GEN_536; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_538 = 11'h21a == index ? 32'h6c6f72 : _GEN_537; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_539 = 11'h21b == index ? 32'h2000000 : _GEN_538; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_540 = 11'h21c == index ? 32'h1000000 : _GEN_539; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_541 = 11'h21d == index ? 32'h65746e69 : _GEN_540; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_542 = 11'h21e == index ? 32'h70757272 : _GEN_541; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_543 = 11'h21f == index ? 32'h6f632d74 : _GEN_542; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_544 = 11'h220 == index ? 32'h6f72746e : _GEN_543; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_545 = 11'h221 == index ? 32'h72656c6c : _GEN_544; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_546 = 11'h222 == index ? 32'h30306340 : _GEN_545; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_547 = 11'h223 == index ? 32'h30303030 : _GEN_546; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_548 = 11'h224 == index ? 32'h0 : _GEN_547; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_549 = 11'h225 == index ? 32'h3000000 : _GEN_548; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_550 = 11'h226 == index ? 32'h4000000 : _GEN_549; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_551 = 11'h227 == index ? 32'h54010000 : _GEN_550; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_552 = 11'h228 == index ? 32'h1000000 : _GEN_551; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_553 = 11'h229 == index ? 32'h3000000 : _GEN_552; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_554 = 11'h22a == index ? 32'hc000000 : _GEN_553; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_555 = 11'h22b == index ? 32'h1b000000 : _GEN_554; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_556 = 11'h22c == index ? 32'h63736972 : _GEN_555; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_557 = 11'h22d == index ? 32'h6c702c76 : _GEN_556; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_558 = 11'h22e == index ? 32'h306369 : _GEN_557; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_559 = 11'h22f == index ? 32'h3000000 : _GEN_558; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_560 = 11'h230 == index ? 32'h0 : _GEN_559; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_561 = 11'h231 == index ? 32'h65010000 : _GEN_560; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_562 = 11'h232 == index ? 32'h3000000 : _GEN_561; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_563 = 11'h233 == index ? 32'h10000000 : _GEN_562; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_564 = 11'h234 == index ? 32'haf010000 : _GEN_563; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_565 = 11'h235 == index ? 32'h4000000 : _GEN_564; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_566 = 11'h236 == index ? 32'hb000000 : _GEN_565; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_567 = 11'h237 == index ? 32'h4000000 : _GEN_566; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_568 = 11'h238 == index ? 32'h9000000 : _GEN_567; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_569 = 11'h239 == index ? 32'h3000000 : _GEN_568; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_570 = 11'h23a == index ? 32'h8000000 : _GEN_569; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_571 = 11'h23b == index ? 32'hd010000 : _GEN_570; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_572 = 11'h23c == index ? 32'hc : _GEN_571; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_573 = 11'h23d == index ? 32'h4 : _GEN_572; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_574 = 11'h23e == index ? 32'h3000000 : _GEN_573; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_575 = 11'h23f == index ? 32'h8000000 : _GEN_574; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_576 = 11'h240 == index ? 32'ha5010000 : _GEN_575; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_577 = 11'h241 == index ? 32'h746e6f63 : _GEN_576; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_578 = 11'h242 == index ? 32'h6c6f72 : _GEN_577; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_579 = 11'h243 == index ? 32'h3000000 : _GEN_578; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_580 = 11'h244 == index ? 32'h4000000 : _GEN_579; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_581 = 11'h245 == index ? 32'hf3010000 : _GEN_580; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_582 = 11'h246 == index ? 32'h7000000 : _GEN_581; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_583 = 11'h247 == index ? 32'h3000000 : _GEN_582; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_584 = 11'h248 == index ? 32'h4000000 : _GEN_583; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_585 = 11'h249 == index ? 32'h6020000 : _GEN_584; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_586 = 11'h24a == index ? 32'h38000000 : _GEN_585; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_587 = 11'h24b == index ? 32'h3000000 : _GEN_586; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_588 = 11'h24c == index ? 32'h4000000 : _GEN_587; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_589 = 11'h24d == index ? 32'h7a010000 : _GEN_588; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_590 = 11'h24e == index ? 32'h3000000 : _GEN_589; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_591 = 11'h24f == index ? 32'h2000000 : _GEN_590; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_592 = 11'h250 == index ? 32'h1000000 : _GEN_591; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_593 = 11'h251 == index ? 32'h6d697469 : _GEN_592; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_594 = 11'h252 == index ? 32'h30303840 : _GEN_593; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_595 = 11'h253 == index ? 32'h30303030 : _GEN_594; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_596 = 11'h254 == index ? 32'h0 : _GEN_595; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_597 = 11'h255 == index ? 32'h3000000 : _GEN_596; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_598 = 11'h256 == index ? 32'hd000000 : _GEN_597; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_599 = 11'h257 == index ? 32'h1b000000 : _GEN_598; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_600 = 11'h258 == index ? 32'h69666973 : _GEN_599; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_601 = 11'h259 == index ? 32'h692c6576 : _GEN_600; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_602 = 11'h25a == index ? 32'h306d6974 : _GEN_601; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_603 = 11'h25b == index ? 32'h0 : _GEN_602; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_604 = 11'h25c == index ? 32'h3000000 : _GEN_603; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_605 = 11'h25d == index ? 32'h10000000 : _GEN_604; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_606 = 11'h25e == index ? 32'hd010000 : _GEN_605; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_607 = 11'h25f == index ? 32'h8 : _GEN_606; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_608 = 11'h260 == index ? 32'h200000 : _GEN_607; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_609 = 11'h261 == index ? 32'h200008 : _GEN_608; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_610 = 11'h262 == index ? 32'h200000 : _GEN_609; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_611 = 11'h263 == index ? 32'h3000000 : _GEN_610; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_612 = 11'h264 == index ? 32'hc000000 : _GEN_611; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_613 = 11'h265 == index ? 32'ha5010000 : _GEN_612; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_614 = 11'h266 == index ? 32'h6d656d : _GEN_613; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_615 = 11'h267 == index ? 32'h746e6f63 : _GEN_614; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_616 = 11'h268 == index ? 32'h6c6f72 : _GEN_615; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_617 = 11'h269 == index ? 32'h3000000 : _GEN_616; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_618 = 11'h26a == index ? 32'h4000000 : _GEN_617; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_619 = 11'h26b == index ? 32'h7a010000 : _GEN_618; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_620 = 11'h26c == index ? 32'h2000000 : _GEN_619; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_621 = 11'h26d == index ? 32'h2000000 : _GEN_620; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_622 = 11'h26e == index ? 32'h1000000 : _GEN_621; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_623 = 11'h26f == index ? 32'h406d7770 : _GEN_622; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_624 = 11'h270 == index ? 32'h31303031 : _GEN_623; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_625 = 11'h271 == index ? 32'h30303035 : _GEN_624; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_626 = 11'h272 == index ? 32'h0 : _GEN_625; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_627 = 11'h273 == index ? 32'h3000000 : _GEN_626; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_628 = 11'h274 == index ? 32'h4000000 : _GEN_627; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_629 = 11'h275 == index ? 32'hdc010000 : _GEN_628; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_630 = 11'h276 == index ? 32'h5000000 : _GEN_629; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_631 = 11'h277 == index ? 32'h3000000 : _GEN_630; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_632 = 11'h278 == index ? 32'hc000000 : _GEN_631; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_633 = 11'h279 == index ? 32'h1b000000 : _GEN_632; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_634 = 11'h27a == index ? 32'h69666973 : _GEN_633; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_635 = 11'h27b == index ? 32'h702c6576 : _GEN_634; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_636 = 11'h27c == index ? 32'h306d77 : _GEN_635; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_637 = 11'h27d == index ? 32'h3000000 : _GEN_636; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_638 = 11'h27e == index ? 32'h4000000 : _GEN_637; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_639 = 11'h27f == index ? 32'h89010000 : _GEN_638; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_640 = 11'h280 == index ? 32'h3000000 : _GEN_639; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_641 = 11'h281 == index ? 32'h3000000 : _GEN_640; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_642 = 11'h282 == index ? 32'h10000000 : _GEN_641; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_643 = 11'h283 == index ? 32'h9a010000 : _GEN_642; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_644 = 11'h284 == index ? 32'h2b000000 : _GEN_643; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_645 = 11'h285 == index ? 32'h2c000000 : _GEN_644; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_646 = 11'h286 == index ? 32'h2d000000 : _GEN_645; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_647 = 11'h287 == index ? 32'h2e000000 : _GEN_646; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_648 = 11'h288 == index ? 32'h3000000 : _GEN_647; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_649 = 11'h289 == index ? 32'h8000000 : _GEN_648; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_650 = 11'h28a == index ? 32'hd010000 : _GEN_649; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_651 = 11'h28b == index ? 32'h500110 : _GEN_650; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_652 = 11'h28c == index ? 32'h100000 : _GEN_651; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_653 = 11'h28d == index ? 32'h3000000 : _GEN_652; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_654 = 11'h28e == index ? 32'h8000000 : _GEN_653; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_655 = 11'h28f == index ? 32'ha5010000 : _GEN_654; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_656 = 11'h290 == index ? 32'h746e6f63 : _GEN_655; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_657 = 11'h291 == index ? 32'h6c6f72 : _GEN_656; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_658 = 11'h292 == index ? 32'h3000000 : _GEN_657; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_659 = 11'h293 == index ? 32'h4000000 : _GEN_658; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_660 = 11'h294 == index ? 32'h11020000 : _GEN_659; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_661 = 11'h295 == index ? 32'h10000000 : _GEN_660; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_662 = 11'h296 == index ? 32'h3000000 : _GEN_661; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_663 = 11'h297 == index ? 32'h4000000 : _GEN_662; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_664 = 11'h298 == index ? 32'h2d020000 : _GEN_663; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_665 = 11'h299 == index ? 32'h4000000 : _GEN_664; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_666 = 11'h29a == index ? 32'h2000000 : _GEN_665; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_667 = 11'h29b == index ? 32'h1000000 : _GEN_666; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_668 = 11'h29c == index ? 32'h406d7770 : _GEN_667; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_669 = 11'h29d == index ? 32'h32303031 : _GEN_668; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_670 = 11'h29e == index ? 32'h30303035 : _GEN_669; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_671 = 11'h29f == index ? 32'h0 : _GEN_670; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_672 = 11'h2a0 == index ? 32'h3000000 : _GEN_671; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_673 = 11'h2a1 == index ? 32'h4000000 : _GEN_672; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_674 = 11'h2a2 == index ? 32'hdc010000 : _GEN_673; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_675 = 11'h2a3 == index ? 32'h5000000 : _GEN_674; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_676 = 11'h2a4 == index ? 32'h3000000 : _GEN_675; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_677 = 11'h2a5 == index ? 32'hc000000 : _GEN_676; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_678 = 11'h2a6 == index ? 32'h1b000000 : _GEN_677; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_679 = 11'h2a7 == index ? 32'h69666973 : _GEN_678; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_680 = 11'h2a8 == index ? 32'h702c6576 : _GEN_679; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_681 = 11'h2a9 == index ? 32'h306d77 : _GEN_680; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_682 = 11'h2aa == index ? 32'h3000000 : _GEN_681; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_683 = 11'h2ab == index ? 32'h4000000 : _GEN_682; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_684 = 11'h2ac == index ? 32'h89010000 : _GEN_683; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_685 = 11'h2ad == index ? 32'h3000000 : _GEN_684; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_686 = 11'h2ae == index ? 32'h3000000 : _GEN_685; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_687 = 11'h2af == index ? 32'h10000000 : _GEN_686; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_688 = 11'h2b0 == index ? 32'h9a010000 : _GEN_687; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_689 = 11'h2b1 == index ? 32'h2f000000 : _GEN_688; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_690 = 11'h2b2 == index ? 32'h30000000 : _GEN_689; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_691 = 11'h2b3 == index ? 32'h31000000 : _GEN_690; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_692 = 11'h2b4 == index ? 32'h32000000 : _GEN_691; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_693 = 11'h2b5 == index ? 32'h3000000 : _GEN_692; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_694 = 11'h2b6 == index ? 32'h8000000 : _GEN_693; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_695 = 11'h2b7 == index ? 32'hd010000 : _GEN_694; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_696 = 11'h2b8 == index ? 32'h500210 : _GEN_695; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_697 = 11'h2b9 == index ? 32'h100000 : _GEN_696; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_698 = 11'h2ba == index ? 32'h3000000 : _GEN_697; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_699 = 11'h2bb == index ? 32'h8000000 : _GEN_698; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_700 = 11'h2bc == index ? 32'ha5010000 : _GEN_699; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_701 = 11'h2bd == index ? 32'h746e6f63 : _GEN_700; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_702 = 11'h2be == index ? 32'h6c6f72 : _GEN_701; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_703 = 11'h2bf == index ? 32'h3000000 : _GEN_702; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_704 = 11'h2c0 == index ? 32'h4000000 : _GEN_703; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_705 = 11'h2c1 == index ? 32'h11020000 : _GEN_704; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_706 = 11'h2c2 == index ? 32'h10000000 : _GEN_705; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_707 = 11'h2c3 == index ? 32'h3000000 : _GEN_706; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_708 = 11'h2c4 == index ? 32'h4000000 : _GEN_707; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_709 = 11'h2c5 == index ? 32'h2d020000 : _GEN_708; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_710 = 11'h2c6 == index ? 32'h4000000 : _GEN_709; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_711 = 11'h2c7 == index ? 32'h2000000 : _GEN_710; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_712 = 11'h2c8 == index ? 32'h1000000 : _GEN_711; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_713 = 11'h2c9 == index ? 32'h406d7770 : _GEN_712; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_714 = 11'h2ca == index ? 32'h33303031 : _GEN_713; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_715 = 11'h2cb == index ? 32'h30303035 : _GEN_714; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_716 = 11'h2cc == index ? 32'h0 : _GEN_715; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_717 = 11'h2cd == index ? 32'h3000000 : _GEN_716; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_718 = 11'h2ce == index ? 32'h4000000 : _GEN_717; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_719 = 11'h2cf == index ? 32'hdc010000 : _GEN_718; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_720 = 11'h2d0 == index ? 32'h5000000 : _GEN_719; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_721 = 11'h2d1 == index ? 32'h3000000 : _GEN_720; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_722 = 11'h2d2 == index ? 32'hc000000 : _GEN_721; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_723 = 11'h2d3 == index ? 32'h1b000000 : _GEN_722; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_724 = 11'h2d4 == index ? 32'h69666973 : _GEN_723; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_725 = 11'h2d5 == index ? 32'h702c6576 : _GEN_724; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_726 = 11'h2d6 == index ? 32'h306d77 : _GEN_725; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_727 = 11'h2d7 == index ? 32'h3000000 : _GEN_726; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_728 = 11'h2d8 == index ? 32'h4000000 : _GEN_727; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_729 = 11'h2d9 == index ? 32'h89010000 : _GEN_728; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_730 = 11'h2da == index ? 32'h3000000 : _GEN_729; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_731 = 11'h2db == index ? 32'h3000000 : _GEN_730; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_732 = 11'h2dc == index ? 32'h10000000 : _GEN_731; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_733 = 11'h2dd == index ? 32'h9a010000 : _GEN_732; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_734 = 11'h2de == index ? 32'h33000000 : _GEN_733; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_735 = 11'h2df == index ? 32'h34000000 : _GEN_734; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_736 = 11'h2e0 == index ? 32'h35000000 : _GEN_735; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_737 = 11'h2e1 == index ? 32'h36000000 : _GEN_736; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_738 = 11'h2e2 == index ? 32'h3000000 : _GEN_737; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_739 = 11'h2e3 == index ? 32'h8000000 : _GEN_738; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_740 = 11'h2e4 == index ? 32'hd010000 : _GEN_739; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_741 = 11'h2e5 == index ? 32'h500310 : _GEN_740; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_742 = 11'h2e6 == index ? 32'h100000 : _GEN_741; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_743 = 11'h2e7 == index ? 32'h3000000 : _GEN_742; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_744 = 11'h2e8 == index ? 32'h8000000 : _GEN_743; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_745 = 11'h2e9 == index ? 32'ha5010000 : _GEN_744; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_746 = 11'h2ea == index ? 32'h746e6f63 : _GEN_745; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_747 = 11'h2eb == index ? 32'h6c6f72 : _GEN_746; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_748 = 11'h2ec == index ? 32'h3000000 : _GEN_747; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_749 = 11'h2ed == index ? 32'h4000000 : _GEN_748; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_750 = 11'h2ee == index ? 32'h11020000 : _GEN_749; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_751 = 11'h2ef == index ? 32'h10000000 : _GEN_750; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_752 = 11'h2f0 == index ? 32'h3000000 : _GEN_751; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_753 = 11'h2f1 == index ? 32'h4000000 : _GEN_752; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_754 = 11'h2f2 == index ? 32'h2d020000 : _GEN_753; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_755 = 11'h2f3 == index ? 32'h4000000 : _GEN_754; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_756 = 11'h2f4 == index ? 32'h2000000 : _GEN_755; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_757 = 11'h2f5 == index ? 32'h1000000 : _GEN_756; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_758 = 11'h2f6 == index ? 32'h406d6f72 : _GEN_757; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_759 = 11'h2f7 == index ? 32'h30303031 : _GEN_758; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_760 = 11'h2f8 == index ? 32'h30 : _GEN_759; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_761 = 11'h2f9 == index ? 32'h3000000 : _GEN_760; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_762 = 11'h2fa == index ? 32'hc000000 : _GEN_761; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_763 = 11'h2fb == index ? 32'h1b000000 : _GEN_762; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_764 = 11'h2fc == index ? 32'h69666973 : _GEN_763; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_765 = 11'h2fd == index ? 32'h722c6576 : _GEN_764; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_766 = 11'h2fe == index ? 32'h306d6f : _GEN_765; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_767 = 11'h2ff == index ? 32'h3000000 : _GEN_766; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_768 = 11'h300 == index ? 32'h8000000 : _GEN_767; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_769 = 11'h301 == index ? 32'hd010000 : _GEN_768; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_770 = 11'h302 == index ? 32'h100 : _GEN_769; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_771 = 11'h303 == index ? 32'h100 : _GEN_770; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_772 = 11'h304 == index ? 32'h3000000 : _GEN_771; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_773 = 11'h305 == index ? 32'h4000000 : _GEN_772; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_774 = 11'h306 == index ? 32'ha5010000 : _GEN_773; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_775 = 11'h307 == index ? 32'h6d656d : _GEN_774; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_776 = 11'h308 == index ? 32'h2000000 : _GEN_775; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_777 = 11'h309 == index ? 32'h1000000 : _GEN_776; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_778 = 11'h30a == index ? 32'h69726573 : _GEN_777; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_779 = 11'h30b == index ? 32'h31406c61 : _GEN_778; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_780 = 11'h30c == index ? 32'h33313030 : _GEN_779; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_781 = 11'h30d == index ? 32'h303030 : _GEN_780; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_782 = 11'h30e == index ? 32'h3000000 : _GEN_781; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_783 = 11'h30f == index ? 32'h4000000 : _GEN_782; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_784 = 11'h310 == index ? 32'hdc010000 : _GEN_783; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_785 = 11'h311 == index ? 32'h5000000 : _GEN_784; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_786 = 11'h312 == index ? 32'h3000000 : _GEN_785; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_787 = 11'h313 == index ? 32'hd000000 : _GEN_786; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_788 = 11'h314 == index ? 32'h1b000000 : _GEN_787; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_789 = 11'h315 == index ? 32'h69666973 : _GEN_788; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_790 = 11'h316 == index ? 32'h752c6576 : _GEN_789; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_791 = 11'h317 == index ? 32'h30747261 : _GEN_790; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_792 = 11'h318 == index ? 32'h0 : _GEN_791; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_793 = 11'h319 == index ? 32'h3000000 : _GEN_792; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_794 = 11'h31a == index ? 32'h4000000 : _GEN_793; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_795 = 11'h31b == index ? 32'h89010000 : _GEN_794; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_796 = 11'h31c == index ? 32'h3000000 : _GEN_795; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_797 = 11'h31d == index ? 32'h3000000 : _GEN_796; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_798 = 11'h31e == index ? 32'h4000000 : _GEN_797; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_799 = 11'h31f == index ? 32'h9a010000 : _GEN_798; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_800 = 11'h320 == index ? 32'h3000000 : _GEN_799; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_801 = 11'h321 == index ? 32'h3000000 : _GEN_800; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_802 = 11'h322 == index ? 32'h8000000 : _GEN_801; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_803 = 11'h323 == index ? 32'hd010000 : _GEN_802; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_804 = 11'h324 == index ? 32'h300110 : _GEN_803; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_805 = 11'h325 == index ? 32'h100000 : _GEN_804; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_806 = 11'h326 == index ? 32'h3000000 : _GEN_805; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_807 = 11'h327 == index ? 32'h8000000 : _GEN_806; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_808 = 11'h328 == index ? 32'ha5010000 : _GEN_807; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_809 = 11'h329 == index ? 32'h746e6f63 : _GEN_808; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_810 = 11'h32a == index ? 32'h6c6f72 : _GEN_809; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_811 = 11'h32b == index ? 32'h2000000 : _GEN_810; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_812 = 11'h32c == index ? 32'h1000000 : _GEN_811; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_813 = 11'h32d == index ? 32'h69726573 : _GEN_812; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_814 = 11'h32e == index ? 32'h31406c61 : _GEN_813; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_815 = 11'h32f == index ? 32'h33323030 : _GEN_814; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_816 = 11'h330 == index ? 32'h303030 : _GEN_815; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_817 = 11'h331 == index ? 32'h3000000 : _GEN_816; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_818 = 11'h332 == index ? 32'h4000000 : _GEN_817; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_819 = 11'h333 == index ? 32'hdc010000 : _GEN_818; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_820 = 11'h334 == index ? 32'h5000000 : _GEN_819; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_821 = 11'h335 == index ? 32'h3000000 : _GEN_820; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_822 = 11'h336 == index ? 32'hd000000 : _GEN_821; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_823 = 11'h337 == index ? 32'h1b000000 : _GEN_822; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_824 = 11'h338 == index ? 32'h69666973 : _GEN_823; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_825 = 11'h339 == index ? 32'h752c6576 : _GEN_824; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_826 = 11'h33a == index ? 32'h30747261 : _GEN_825; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_827 = 11'h33b == index ? 32'h0 : _GEN_826; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_828 = 11'h33c == index ? 32'h3000000 : _GEN_827; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_829 = 11'h33d == index ? 32'h4000000 : _GEN_828; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_830 = 11'h33e == index ? 32'h89010000 : _GEN_829; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_831 = 11'h33f == index ? 32'h3000000 : _GEN_830; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_832 = 11'h340 == index ? 32'h3000000 : _GEN_831; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_833 = 11'h341 == index ? 32'h4000000 : _GEN_832; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_834 = 11'h342 == index ? 32'h9a010000 : _GEN_833; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_835 = 11'h343 == index ? 32'h4000000 : _GEN_834; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_836 = 11'h344 == index ? 32'h3000000 : _GEN_835; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_837 = 11'h345 == index ? 32'h8000000 : _GEN_836; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_838 = 11'h346 == index ? 32'hd010000 : _GEN_837; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_839 = 11'h347 == index ? 32'h300210 : _GEN_838; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_840 = 11'h348 == index ? 32'h100000 : _GEN_839; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_841 = 11'h349 == index ? 32'h3000000 : _GEN_840; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_842 = 11'h34a == index ? 32'h8000000 : _GEN_841; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_843 = 11'h34b == index ? 32'ha5010000 : _GEN_842; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_844 = 11'h34c == index ? 32'h746e6f63 : _GEN_843; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_845 = 11'h34d == index ? 32'h6c6f72 : _GEN_844; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_846 = 11'h34e == index ? 32'h2000000 : _GEN_845; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_847 = 11'h34f == index ? 32'h1000000 : _GEN_846; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_848 = 11'h350 == index ? 32'h69726573 : _GEN_847; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_849 = 11'h351 == index ? 32'h31406c61 : _GEN_848; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_850 = 11'h352 == index ? 32'h33333030 : _GEN_849; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_851 = 11'h353 == index ? 32'h303030 : _GEN_850; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_852 = 11'h354 == index ? 32'h3000000 : _GEN_851; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_853 = 11'h355 == index ? 32'h4000000 : _GEN_852; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_854 = 11'h356 == index ? 32'hdc010000 : _GEN_853; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_855 = 11'h357 == index ? 32'h5000000 : _GEN_854; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_856 = 11'h358 == index ? 32'h3000000 : _GEN_855; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_857 = 11'h359 == index ? 32'hd000000 : _GEN_856; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_858 = 11'h35a == index ? 32'h1b000000 : _GEN_857; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_859 = 11'h35b == index ? 32'h69666973 : _GEN_858; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_860 = 11'h35c == index ? 32'h752c6576 : _GEN_859; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_861 = 11'h35d == index ? 32'h30747261 : _GEN_860; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_862 = 11'h35e == index ? 32'h0 : _GEN_861; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_863 = 11'h35f == index ? 32'h3000000 : _GEN_862; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_864 = 11'h360 == index ? 32'h4000000 : _GEN_863; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_865 = 11'h361 == index ? 32'h89010000 : _GEN_864; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_866 = 11'h362 == index ? 32'h3000000 : _GEN_865; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_867 = 11'h363 == index ? 32'h3000000 : _GEN_866; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_868 = 11'h364 == index ? 32'h4000000 : _GEN_867; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_869 = 11'h365 == index ? 32'h9a010000 : _GEN_868; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_870 = 11'h366 == index ? 32'h5000000 : _GEN_869; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_871 = 11'h367 == index ? 32'h3000000 : _GEN_870; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_872 = 11'h368 == index ? 32'h8000000 : _GEN_871; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_873 = 11'h369 == index ? 32'hd010000 : _GEN_872; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_874 = 11'h36a == index ? 32'h300310 : _GEN_873; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_875 = 11'h36b == index ? 32'h100000 : _GEN_874; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_876 = 11'h36c == index ? 32'h3000000 : _GEN_875; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_877 = 11'h36d == index ? 32'h8000000 : _GEN_876; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_878 = 11'h36e == index ? 32'ha5010000 : _GEN_877; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_879 = 11'h36f == index ? 32'h746e6f63 : _GEN_878; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_880 = 11'h370 == index ? 32'h6c6f72 : _GEN_879; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_881 = 11'h371 == index ? 32'h2000000 : _GEN_880; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_882 = 11'h372 == index ? 32'h1000000 : _GEN_881; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_883 = 11'h373 == index ? 32'h69726573 : _GEN_882; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_884 = 11'h374 == index ? 32'h31406c61 : _GEN_883; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_885 = 11'h375 == index ? 32'h33343030 : _GEN_884; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_886 = 11'h376 == index ? 32'h303030 : _GEN_885; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_887 = 11'h377 == index ? 32'h3000000 : _GEN_886; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_888 = 11'h378 == index ? 32'h4000000 : _GEN_887; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_889 = 11'h379 == index ? 32'hdc010000 : _GEN_888; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_890 = 11'h37a == index ? 32'h5000000 : _GEN_889; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_891 = 11'h37b == index ? 32'h3000000 : _GEN_890; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_892 = 11'h37c == index ? 32'hd000000 : _GEN_891; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_893 = 11'h37d == index ? 32'h1b000000 : _GEN_892; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_894 = 11'h37e == index ? 32'h69666973 : _GEN_893; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_895 = 11'h37f == index ? 32'h752c6576 : _GEN_894; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_896 = 11'h380 == index ? 32'h30747261 : _GEN_895; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_897 = 11'h381 == index ? 32'h0 : _GEN_896; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_898 = 11'h382 == index ? 32'h3000000 : _GEN_897; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_899 = 11'h383 == index ? 32'h4000000 : _GEN_898; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_900 = 11'h384 == index ? 32'h89010000 : _GEN_899; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_901 = 11'h385 == index ? 32'h3000000 : _GEN_900; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_902 = 11'h386 == index ? 32'h3000000 : _GEN_901; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_903 = 11'h387 == index ? 32'h4000000 : _GEN_902; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_904 = 11'h388 == index ? 32'h9a010000 : _GEN_903; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_905 = 11'h389 == index ? 32'h6000000 : _GEN_904; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_906 = 11'h38a == index ? 32'h3000000 : _GEN_905; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_907 = 11'h38b == index ? 32'h8000000 : _GEN_906; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_908 = 11'h38c == index ? 32'hd010000 : _GEN_907; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_909 = 11'h38d == index ? 32'h300410 : _GEN_908; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_910 = 11'h38e == index ? 32'h100000 : _GEN_909; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_911 = 11'h38f == index ? 32'h3000000 : _GEN_910; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_912 = 11'h390 == index ? 32'h8000000 : _GEN_911; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_913 = 11'h391 == index ? 32'ha5010000 : _GEN_912; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_914 = 11'h392 == index ? 32'h746e6f63 : _GEN_913; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_915 = 11'h393 == index ? 32'h6c6f72 : _GEN_914; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_916 = 11'h394 == index ? 32'h2000000 : _GEN_915; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_917 = 11'h395 == index ? 32'h1000000 : _GEN_916; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_918 = 11'h396 == index ? 32'h69726573 : _GEN_917; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_919 = 11'h397 == index ? 32'h31406c61 : _GEN_918; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_920 = 11'h398 == index ? 32'h33353030 : _GEN_919; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_921 = 11'h399 == index ? 32'h303030 : _GEN_920; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_922 = 11'h39a == index ? 32'h3000000 : _GEN_921; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_923 = 11'h39b == index ? 32'h4000000 : _GEN_922; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_924 = 11'h39c == index ? 32'hdc010000 : _GEN_923; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_925 = 11'h39d == index ? 32'h5000000 : _GEN_924; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_926 = 11'h39e == index ? 32'h3000000 : _GEN_925; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_927 = 11'h39f == index ? 32'hd000000 : _GEN_926; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_928 = 11'h3a0 == index ? 32'h1b000000 : _GEN_927; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_929 = 11'h3a1 == index ? 32'h69666973 : _GEN_928; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_930 = 11'h3a2 == index ? 32'h752c6576 : _GEN_929; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_931 = 11'h3a3 == index ? 32'h30747261 : _GEN_930; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_932 = 11'h3a4 == index ? 32'h0 : _GEN_931; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_933 = 11'h3a5 == index ? 32'h3000000 : _GEN_932; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_934 = 11'h3a6 == index ? 32'h4000000 : _GEN_933; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_935 = 11'h3a7 == index ? 32'h89010000 : _GEN_934; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_936 = 11'h3a8 == index ? 32'h3000000 : _GEN_935; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_937 = 11'h3a9 == index ? 32'h3000000 : _GEN_936; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_938 = 11'h3aa == index ? 32'h4000000 : _GEN_937; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_939 = 11'h3ab == index ? 32'h9a010000 : _GEN_938; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_940 = 11'h3ac == index ? 32'h7000000 : _GEN_939; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_941 = 11'h3ad == index ? 32'h3000000 : _GEN_940; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_942 = 11'h3ae == index ? 32'h8000000 : _GEN_941; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_943 = 11'h3af == index ? 32'hd010000 : _GEN_942; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_944 = 11'h3b0 == index ? 32'h300510 : _GEN_943; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_945 = 11'h3b1 == index ? 32'h100000 : _GEN_944; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_946 = 11'h3b2 == index ? 32'h3000000 : _GEN_945; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_947 = 11'h3b3 == index ? 32'h8000000 : _GEN_946; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_948 = 11'h3b4 == index ? 32'ha5010000 : _GEN_947; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_949 = 11'h3b5 == index ? 32'h746e6f63 : _GEN_948; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_950 = 11'h3b6 == index ? 32'h6c6f72 : _GEN_949; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_951 = 11'h3b7 == index ? 32'h2000000 : _GEN_950; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_952 = 11'h3b8 == index ? 32'h1000000 : _GEN_951; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_953 = 11'h3b9 == index ? 32'h40697073 : _GEN_952; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_954 = 11'h3ba == index ? 32'h31303031 : _GEN_953; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_955 = 11'h3bb == index ? 32'h30303034 : _GEN_954; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_956 = 11'h3bc == index ? 32'h0 : _GEN_955; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_957 = 11'h3bd == index ? 32'h3000000 : _GEN_956; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_958 = 11'h3be == index ? 32'h4000000 : _GEN_957; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_959 = 11'h3bf == index ? 32'h0 : _GEN_958; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_960 = 11'h3c0 == index ? 32'h1000000 : _GEN_959; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_961 = 11'h3c1 == index ? 32'h3000000 : _GEN_960; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_962 = 11'h3c2 == index ? 32'h4000000 : _GEN_961; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_963 = 11'h3c3 == index ? 32'hf000000 : _GEN_962; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_964 = 11'h3c4 == index ? 32'h0 : _GEN_963; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_965 = 11'h3c5 == index ? 32'h3000000 : _GEN_964; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_966 = 11'h3c6 == index ? 32'h4000000 : _GEN_965; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_967 = 11'h3c7 == index ? 32'hdc010000 : _GEN_966; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_968 = 11'h3c8 == index ? 32'h5000000 : _GEN_967; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_969 = 11'h3c9 == index ? 32'h3000000 : _GEN_968; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_970 = 11'h3ca == index ? 32'hc000000 : _GEN_969; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_971 = 11'h3cb == index ? 32'h1b000000 : _GEN_970; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_972 = 11'h3cc == index ? 32'h69666973 : _GEN_971; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_973 = 11'h3cd == index ? 32'h732c6576 : _GEN_972; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_974 = 11'h3ce == index ? 32'h306970 : _GEN_973; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_975 = 11'h3cf == index ? 32'h3000000 : _GEN_974; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_976 = 11'h3d0 == index ? 32'h4000000 : _GEN_975; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_977 = 11'h3d1 == index ? 32'h89010000 : _GEN_976; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_978 = 11'h3d2 == index ? 32'h3000000 : _GEN_977; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_979 = 11'h3d3 == index ? 32'h3000000 : _GEN_978; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_980 = 11'h3d4 == index ? 32'h4000000 : _GEN_979; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_981 = 11'h3d5 == index ? 32'h9a010000 : _GEN_980; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_982 = 11'h3d6 == index ? 32'h8000000 : _GEN_981; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_983 = 11'h3d7 == index ? 32'h3000000 : _GEN_982; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_984 = 11'h3d8 == index ? 32'h10000000 : _GEN_983; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_985 = 11'h3d9 == index ? 32'hd010000 : _GEN_984; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_986 = 11'h3da == index ? 32'h400110 : _GEN_985; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_987 = 11'h3db == index ? 32'h100000 : _GEN_986; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_988 = 11'h3dc == index ? 32'h20 : _GEN_987; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_989 = 11'h3dd == index ? 32'h20 : _GEN_988; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_990 = 11'h3de == index ? 32'h3000000 : _GEN_989; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_991 = 11'h3df == index ? 32'hc000000 : _GEN_990; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_992 = 11'h3e0 == index ? 32'ha5010000 : _GEN_991; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_993 = 11'h3e1 == index ? 32'h746e6f63 : _GEN_992; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_994 = 11'h3e2 == index ? 32'h6c6f72 : _GEN_993; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_995 = 11'h3e3 == index ? 32'h6d656d : _GEN_994; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_996 = 11'h3e4 == index ? 32'h2000000 : _GEN_995; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_997 = 11'h3e5 == index ? 32'h1000000 : _GEN_996; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_998 = 11'h3e6 == index ? 32'h40697073 : _GEN_997; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_999 = 11'h3e7 == index ? 32'h32303031 : _GEN_998; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1000 = 11'h3e8 == index ? 32'h30303034 : _GEN_999; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1001 = 11'h3e9 == index ? 32'h0 : _GEN_1000; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1002 = 11'h3ea == index ? 32'h3000000 : _GEN_1001; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1003 = 11'h3eb == index ? 32'h4000000 : _GEN_1002; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1004 = 11'h3ec == index ? 32'h0 : _GEN_1003; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1005 = 11'h3ed == index ? 32'h1000000 : _GEN_1004; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1006 = 11'h3ee == index ? 32'h3000000 : _GEN_1005; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1007 = 11'h3ef == index ? 32'h4000000 : _GEN_1006; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1008 = 11'h3f0 == index ? 32'hf000000 : _GEN_1007; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1009 = 11'h3f1 == index ? 32'h0 : _GEN_1008; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1010 = 11'h3f2 == index ? 32'h3000000 : _GEN_1009; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1011 = 11'h3f3 == index ? 32'h4000000 : _GEN_1010; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1012 = 11'h3f4 == index ? 32'hdc010000 : _GEN_1011; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1013 = 11'h3f5 == index ? 32'h5000000 : _GEN_1012; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1014 = 11'h3f6 == index ? 32'h3000000 : _GEN_1013; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1015 = 11'h3f7 == index ? 32'hc000000 : _GEN_1014; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1016 = 11'h3f8 == index ? 32'h1b000000 : _GEN_1015; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1017 = 11'h3f9 == index ? 32'h69666973 : _GEN_1016; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1018 = 11'h3fa == index ? 32'h732c6576 : _GEN_1017; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1019 = 11'h3fb == index ? 32'h306970 : _GEN_1018; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1020 = 11'h3fc == index ? 32'h3000000 : _GEN_1019; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1021 = 11'h3fd == index ? 32'h4000000 : _GEN_1020; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1022 = 11'h3fe == index ? 32'h89010000 : _GEN_1021; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1023 = 11'h3ff == index ? 32'h3000000 : _GEN_1022; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1024 = 11'h400 == index ? 32'h3000000 : _GEN_1023; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1025 = 11'h401 == index ? 32'h4000000 : _GEN_1024; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1026 = 11'h402 == index ? 32'h9a010000 : _GEN_1025; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1027 = 11'h403 == index ? 32'ha000000 : _GEN_1026; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1028 = 11'h404 == index ? 32'h3000000 : _GEN_1027; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1029 = 11'h405 == index ? 32'h8000000 : _GEN_1028; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1030 = 11'h406 == index ? 32'hd010000 : _GEN_1029; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1031 = 11'h407 == index ? 32'h400210 : _GEN_1030; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1032 = 11'h408 == index ? 32'h100000 : _GEN_1031; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1033 = 11'h409 == index ? 32'h3000000 : _GEN_1032; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1034 = 11'h40a == index ? 32'h8000000 : _GEN_1033; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1035 = 11'h40b == index ? 32'ha5010000 : _GEN_1034; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1036 = 11'h40c == index ? 32'h746e6f63 : _GEN_1035; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1037 = 11'h40d == index ? 32'h6c6f72 : _GEN_1036; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1038 = 11'h40e == index ? 32'h2000000 : _GEN_1037; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1039 = 11'h40f == index ? 32'h1000000 : _GEN_1038; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1040 = 11'h410 == index ? 32'h40697073 : _GEN_1039; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1041 = 11'h411 == index ? 32'h33303031 : _GEN_1040; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1042 = 11'h412 == index ? 32'h30303034 : _GEN_1041; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1043 = 11'h413 == index ? 32'h0 : _GEN_1042; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1044 = 11'h414 == index ? 32'h3000000 : _GEN_1043; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1045 = 11'h415 == index ? 32'h4000000 : _GEN_1044; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1046 = 11'h416 == index ? 32'h0 : _GEN_1045; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1047 = 11'h417 == index ? 32'h1000000 : _GEN_1046; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1048 = 11'h418 == index ? 32'h3000000 : _GEN_1047; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1049 = 11'h419 == index ? 32'h4000000 : _GEN_1048; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1050 = 11'h41a == index ? 32'hf000000 : _GEN_1049; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1051 = 11'h41b == index ? 32'h0 : _GEN_1050; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1052 = 11'h41c == index ? 32'h3000000 : _GEN_1051; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1053 = 11'h41d == index ? 32'h4000000 : _GEN_1052; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1054 = 11'h41e == index ? 32'hdc010000 : _GEN_1053; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1055 = 11'h41f == index ? 32'h5000000 : _GEN_1054; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1056 = 11'h420 == index ? 32'h3000000 : _GEN_1055; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1057 = 11'h421 == index ? 32'hc000000 : _GEN_1056; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1058 = 11'h422 == index ? 32'h1b000000 : _GEN_1057; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1059 = 11'h423 == index ? 32'h69666973 : _GEN_1058; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1060 = 11'h424 == index ? 32'h732c6576 : _GEN_1059; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1061 = 11'h425 == index ? 32'h306970 : _GEN_1060; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1062 = 11'h426 == index ? 32'h3000000 : _GEN_1061; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1063 = 11'h427 == index ? 32'h4000000 : _GEN_1062; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1064 = 11'h428 == index ? 32'h89010000 : _GEN_1063; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1065 = 11'h429 == index ? 32'h3000000 : _GEN_1064; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1066 = 11'h42a == index ? 32'h3000000 : _GEN_1065; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1067 = 11'h42b == index ? 32'h4000000 : _GEN_1066; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1068 = 11'h42c == index ? 32'h9a010000 : _GEN_1067; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1069 = 11'h42d == index ? 32'h9000000 : _GEN_1068; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1070 = 11'h42e == index ? 32'h3000000 : _GEN_1069; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1071 = 11'h42f == index ? 32'h10000000 : _GEN_1070; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1072 = 11'h430 == index ? 32'hd010000 : _GEN_1071; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1073 = 11'h431 == index ? 32'h400310 : _GEN_1072; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1074 = 11'h432 == index ? 32'h100000 : _GEN_1073; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1075 = 11'h433 == index ? 32'h40 : _GEN_1074; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1076 = 11'h434 == index ? 32'h20 : _GEN_1075; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1077 = 11'h435 == index ? 32'h3000000 : _GEN_1076; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1078 = 11'h436 == index ? 32'hc000000 : _GEN_1077; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1079 = 11'h437 == index ? 32'ha5010000 : _GEN_1078; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1080 = 11'h438 == index ? 32'h746e6f63 : _GEN_1079; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1081 = 11'h439 == index ? 32'h6c6f72 : _GEN_1080; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1082 = 11'h43a == index ? 32'h6d656d : _GEN_1081; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1083 = 11'h43b == index ? 32'h3000000 : _GEN_1082; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1084 = 11'h43c == index ? 32'h4000000 : _GEN_1083; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1085 = 11'h43d == index ? 32'h7a010000 : _GEN_1084; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1086 = 11'h43e == index ? 32'h1000000 : _GEN_1085; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1087 = 11'h43f == index ? 32'h2000000 : _GEN_1086; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1088 = 11'h440 == index ? 32'h1000000 : _GEN_1087; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1089 = 11'h441 == index ? 32'h73627573 : _GEN_1088; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1090 = 11'h442 == index ? 32'h65747379 : _GEN_1089; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1091 = 11'h443 == index ? 32'h62705f6d : _GEN_1090; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1092 = 11'h444 == index ? 32'h635f7375 : _GEN_1091; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1093 = 11'h445 == index ? 32'h6b636f6c : _GEN_1092; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1094 = 11'h446 == index ? 32'h0 : _GEN_1093; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1095 = 11'h447 == index ? 32'h3000000 : _GEN_1094; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1096 = 11'h448 == index ? 32'h4000000 : _GEN_1095; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1097 = 11'h449 == index ? 32'h41020000 : _GEN_1096; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1098 = 11'h44a == index ? 32'h0 : _GEN_1097; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1099 = 11'h44b == index ? 32'h3000000 : _GEN_1098; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1100 = 11'h44c == index ? 32'h4000000 : _GEN_1099; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1101 = 11'h44d == index ? 32'h67000000 : _GEN_1100; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1102 = 11'h44e == index ? 32'he1f505 : _GEN_1101; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1103 = 11'h44f == index ? 32'h3000000 : _GEN_1102; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1104 = 11'h450 == index ? 32'h15000000 : _GEN_1103; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1105 = 11'h451 == index ? 32'h4e020000 : _GEN_1104; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1106 = 11'h452 == index ? 32'h73627573 : _GEN_1105; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1107 = 11'h453 == index ? 32'h65747379 : _GEN_1106; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1108 = 11'h454 == index ? 32'h62705f6d : _GEN_1107; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1109 = 11'h455 == index ? 32'h635f7375 : _GEN_1108; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1110 = 11'h456 == index ? 32'h6b636f6c : _GEN_1109; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1111 = 11'h457 == index ? 32'h0 : _GEN_1110; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1112 = 11'h458 == index ? 32'h3000000 : _GEN_1111; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1113 = 11'h459 == index ? 32'hc000000 : _GEN_1112; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1114 = 11'h45a == index ? 32'h1b000000 : _GEN_1113; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1115 = 11'h45b == index ? 32'h65786966 : _GEN_1114; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1116 = 11'h45c == index ? 32'h6c632d64 : _GEN_1115; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1117 = 11'h45d == index ? 32'h6b636f : _GEN_1116; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1118 = 11'h45e == index ? 32'h3000000 : _GEN_1117; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1119 = 11'h45f == index ? 32'h4000000 : _GEN_1118; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1120 = 11'h460 == index ? 32'h7a010000 : _GEN_1119; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1121 = 11'h461 == index ? 32'h5000000 : _GEN_1120; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1122 = 11'h462 == index ? 32'h2000000 : _GEN_1121; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1123 = 11'h463 == index ? 32'h2000000 : _GEN_1122; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1124 = 11'h464 == index ? 32'h2000000 : _GEN_1123; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1125 = 11'h465 == index ? 32'h9000000 : _GEN_1124; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1126 = 11'h466 == index ? 32'h64646123 : _GEN_1125; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1127 = 11'h467 == index ? 32'h73736572 : _GEN_1126; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1128 = 11'h468 == index ? 32'h6c65632d : _GEN_1127; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1129 = 11'h469 == index ? 32'h2300736c : _GEN_1128; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1130 = 11'h46a == index ? 32'h657a6973 : _GEN_1129; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1131 = 11'h46b == index ? 32'h6c65632d : _GEN_1130; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1132 = 11'h46c == index ? 32'h6300736c : _GEN_1131; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1133 = 11'h46d == index ? 32'h61706d6f : _GEN_1132; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1134 = 11'h46e == index ? 32'h6c626974 : _GEN_1133; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1135 = 11'h46f == index ? 32'h6f6d0065 : _GEN_1134; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1136 = 11'h470 == index ? 32'h6c6564 : _GEN_1135; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1137 = 11'h471 == index ? 32'h69726573 : _GEN_1136; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1138 = 11'h472 == index ? 32'h306c61 : _GEN_1137; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1139 = 11'h473 == index ? 32'h69726573 : _GEN_1138; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1140 = 11'h474 == index ? 32'h316c61 : _GEN_1139; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1141 = 11'h475 == index ? 32'h69726573 : _GEN_1140; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1142 = 11'h476 == index ? 32'h326c61 : _GEN_1141; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1143 = 11'h477 == index ? 32'h69726573 : _GEN_1142; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1144 = 11'h478 == index ? 32'h336c61 : _GEN_1143; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1145 = 11'h479 == index ? 32'h69726573 : _GEN_1144; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1146 = 11'h47a == index ? 32'h346c61 : _GEN_1145; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1147 = 11'h47b == index ? 32'h656d6974 : _GEN_1146; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1148 = 11'h47c == index ? 32'h65736162 : _GEN_1147; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1149 = 11'h47d == index ? 32'h6572662d : _GEN_1148; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1150 = 11'h47e == index ? 32'h6e657571 : _GEN_1149; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1151 = 11'h47f == index ? 32'h63007963 : _GEN_1150; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1152 = 11'h480 == index ? 32'h6b636f6c : _GEN_1151; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1153 = 11'h481 == index ? 32'h6572662d : _GEN_1152; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1154 = 11'h482 == index ? 32'h6e657571 : _GEN_1153; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1155 = 11'h483 == index ? 32'h64007963 : _GEN_1154; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1156 = 11'h484 == index ? 32'h6361632d : _GEN_1155; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1157 = 11'h485 == index ? 32'h622d6568 : _GEN_1156; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1158 = 11'h486 == index ? 32'h6b636f6c : _GEN_1157; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1159 = 11'h487 == index ? 32'h7a69732d : _GEN_1158; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1160 = 11'h488 == index ? 32'h2d640065 : _GEN_1159; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1161 = 11'h489 == index ? 32'h68636163 : _GEN_1160; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1162 = 11'h48a == index ? 32'h65732d65 : _GEN_1161; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1163 = 11'h48b == index ? 32'h64007374 : _GEN_1162; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1164 = 11'h48c == index ? 32'h6361632d : _GEN_1163; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1165 = 11'h48d == index ? 32'h732d6568 : _GEN_1164; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1166 = 11'h48e == index ? 32'h657a69 : _GEN_1165; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1167 = 11'h48f == index ? 32'h69766564 : _GEN_1166; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1168 = 11'h490 == index ? 32'h745f6563 : _GEN_1167; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1169 = 11'h491 == index ? 32'h657079 : _GEN_1168; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1170 = 11'h492 == index ? 32'h64726168 : _GEN_1169; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1171 = 11'h493 == index ? 32'h65726177 : _GEN_1170; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1172 = 11'h494 == index ? 32'h6578652d : _GEN_1171; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1173 = 11'h495 == index ? 32'h72622d63 : _GEN_1172; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1174 = 11'h496 == index ? 32'h706b6165 : _GEN_1173; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1175 = 11'h497 == index ? 32'h746e696f : _GEN_1174; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1176 = 11'h498 == index ? 32'h756f632d : _GEN_1175; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1177 = 11'h499 == index ? 32'h6900746e : _GEN_1176; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1178 = 11'h49a == index ? 32'h6361632d : _GEN_1177; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1179 = 11'h49b == index ? 32'h622d6568 : _GEN_1178; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1180 = 11'h49c == index ? 32'h6b636f6c : _GEN_1179; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1181 = 11'h49d == index ? 32'h7a69732d : _GEN_1180; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1182 = 11'h49e == index ? 32'h2d690065 : _GEN_1181; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1183 = 11'h49f == index ? 32'h68636163 : _GEN_1182; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1184 = 11'h4a0 == index ? 32'h65732d65 : _GEN_1183; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1185 = 11'h4a1 == index ? 32'h69007374 : _GEN_1184; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1186 = 11'h4a2 == index ? 32'h6361632d : _GEN_1185; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1187 = 11'h4a3 == index ? 32'h732d6568 : _GEN_1186; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1188 = 11'h4a4 == index ? 32'h657a69 : _GEN_1187; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1189 = 11'h4a5 == index ? 32'h7478656e : _GEN_1188; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1190 = 11'h4a6 == index ? 32'h76656c2d : _GEN_1189; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1191 = 11'h4a7 == index ? 32'h632d6c65 : _GEN_1190; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1192 = 11'h4a8 == index ? 32'h65686361 : _GEN_1191; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1193 = 11'h4a9 == index ? 32'h67657200 : _GEN_1192; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1194 = 11'h4aa == index ? 32'h73697200 : _GEN_1193; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1195 = 11'h4ab == index ? 32'h692c7663 : _GEN_1194; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1196 = 11'h4ac == index ? 32'h72006173 : _GEN_1195; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1197 = 11'h4ad == index ? 32'h76637369 : _GEN_1196; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1198 = 11'h4ae == index ? 32'h706d702c : _GEN_1197; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1199 = 11'h4af == index ? 32'h6e617267 : _GEN_1198; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1200 = 11'h4b0 == index ? 32'h72616c75 : _GEN_1199; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1201 = 11'h4b1 == index ? 32'h797469 : _GEN_1200; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1202 = 11'h4b2 == index ? 32'h63736972 : _GEN_1201; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1203 = 11'h4b3 == index ? 32'h6d702c76 : _GEN_1202; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1204 = 11'h4b4 == index ? 32'h67657270 : _GEN_1203; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1205 = 11'h4b5 == index ? 32'h736e6f69 : _GEN_1204; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1206 = 11'h4b6 == index ? 32'h66697300 : _GEN_1205; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1207 = 11'h4b7 == index ? 32'h2c657669 : _GEN_1206; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1208 = 11'h4b8 == index ? 32'h6d697469 : _GEN_1207; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1209 = 11'h4b9 == index ? 32'h61747300 : _GEN_1208; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1210 = 11'h4ba == index ? 32'h737574 : _GEN_1209; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1211 = 11'h4bb == index ? 32'h746e6923 : _GEN_1210; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1212 = 11'h4bc == index ? 32'h75727265 : _GEN_1211; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1213 = 11'h4bd == index ? 32'h632d7470 : _GEN_1212; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1214 = 11'h4be == index ? 32'h736c6c65 : _GEN_1213; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1215 = 11'h4bf == index ? 32'h746e6900 : _GEN_1214; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1216 = 11'h4c0 == index ? 32'h75727265 : _GEN_1215; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1217 = 11'h4c1 == index ? 32'h632d7470 : _GEN_1216; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1218 = 11'h4c2 == index ? 32'h72746e6f : _GEN_1217; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1219 = 11'h4c3 == index ? 32'h656c6c6f : _GEN_1218; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1220 = 11'h4c4 == index ? 32'h68700072 : _GEN_1219; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1221 = 11'h4c5 == index ? 32'h6c646e61 : _GEN_1220; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1222 = 11'h4c6 == index ? 32'h61720065 : _GEN_1221; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1223 = 11'h4c7 == index ? 32'h7365676e : _GEN_1222; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1224 = 11'h4c8 == index ? 32'h746e6900 : _GEN_1223; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1225 = 11'h4c9 == index ? 32'h75727265 : _GEN_1224; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1226 = 11'h4ca == index ? 32'h702d7470 : _GEN_1225; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1227 = 11'h4cb == index ? 32'h6e657261 : _GEN_1226; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1228 = 11'h4cc == index ? 32'h6e690074 : _GEN_1227; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1229 = 11'h4cd == index ? 32'h72726574 : _GEN_1228; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1230 = 11'h4ce == index ? 32'h73747075 : _GEN_1229; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1231 = 11'h4cf == index ? 32'h67657200 : _GEN_1230; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1232 = 11'h4d0 == index ? 32'h6d616e2d : _GEN_1231; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1233 = 11'h4d1 == index ? 32'h69007365 : _GEN_1232; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1234 = 11'h4d2 == index ? 32'h7265746e : _GEN_1233; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1235 = 11'h4d3 == index ? 32'h74707572 : _GEN_1234; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1236 = 11'h4d4 == index ? 32'h78652d73 : _GEN_1235; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1237 = 11'h4d5 == index ? 32'h646e6574 : _GEN_1236; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1238 = 11'h4d6 == index ? 32'h64006465 : _GEN_1237; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1239 = 11'h4d7 == index ? 32'h67756265 : _GEN_1238; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1240 = 11'h4d8 == index ? 32'h7474612d : _GEN_1239; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1241 = 11'h4d9 == index ? 32'h686361 : _GEN_1240; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1242 = 11'h4da == index ? 32'h69706723 : _GEN_1241; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1243 = 11'h4db == index ? 32'h65632d6f : _GEN_1242; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1244 = 11'h4dc == index ? 32'h736c6c : _GEN_1243; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1245 = 11'h4dd == index ? 32'h636f6c63 : _GEN_1244; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1246 = 11'h4de == index ? 32'h6700736b : _GEN_1245; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1247 = 11'h4df == index ? 32'h2d6f6970 : _GEN_1246; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1248 = 11'h4e0 == index ? 32'h746e6f63 : _GEN_1247; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1249 = 11'h4e1 == index ? 32'h6c6c6f72 : _GEN_1248; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1250 = 11'h4e2 == index ? 32'h72007265 : _GEN_1249; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1251 = 11'h4e3 == index ? 32'h76637369 : _GEN_1250; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1252 = 11'h4e4 == index ? 32'h78616d2c : _GEN_1251; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1253 = 11'h4e5 == index ? 32'h6972702d : _GEN_1252; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1254 = 11'h4e6 == index ? 32'h7469726f : _GEN_1253; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1255 = 11'h4e7 == index ? 32'h69720079 : _GEN_1254; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1256 = 11'h4e8 == index ? 32'h2c766373 : _GEN_1255; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1257 = 11'h4e9 == index ? 32'h7665646e : _GEN_1256; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1258 = 11'h4ea == index ? 32'h66697300 : _GEN_1257; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1259 = 11'h4eb == index ? 32'h2c657669 : _GEN_1258; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1260 = 11'h4ec == index ? 32'h706d6f63 : _GEN_1259; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1261 = 11'h4ed == index ? 32'h74617261 : _GEN_1260; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1262 = 11'h4ee == index ? 32'h772d726f : _GEN_1261; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1263 = 11'h4ef == index ? 32'h68746469 : _GEN_1262; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1264 = 11'h4f0 == index ? 32'h73746962 : _GEN_1263; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1265 = 11'h4f1 == index ? 32'h66697300 : _GEN_1264; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1266 = 11'h4f2 == index ? 32'h2c657669 : _GEN_1265; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1267 = 11'h4f3 == index ? 32'h6d6f636e : _GEN_1266; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1268 = 11'h4f4 == index ? 32'h61726170 : _GEN_1267; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1269 = 11'h4f5 == index ? 32'h73726f74 : _GEN_1268; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1270 = 11'h4f6 == index ? 32'h6c632300 : _GEN_1269; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1271 = 11'h4f7 == index ? 32'h2d6b636f : _GEN_1270; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1272 = 11'h4f8 == index ? 32'h6c6c6563 : _GEN_1271; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1273 = 11'h4f9 == index ? 32'h6c630073 : _GEN_1272; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1274 = 11'h4fa == index ? 32'h2d6b636f : _GEN_1273; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1275 = 11'h4fb == index ? 32'h7074756f : _GEN_1274; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1276 = 11'h4fc == index ? 32'h6e2d7475 : _GEN_1275; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1277 = 11'h4fd == index ? 32'h73656d61 : _GEN_1276; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1278 = 11'h4fe == index ? 32'h0 : _GEN_1277; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1279 = 11'h4ff == index ? 32'h0 : _GEN_1278; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1280 = 11'h500 == index ? 32'h0 : _GEN_1279; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1281 = 11'h501 == index ? 32'h0 : _GEN_1280; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1282 = 11'h502 == index ? 32'h0 : _GEN_1281; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1283 = 11'h503 == index ? 32'h0 : _GEN_1282; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1284 = 11'h504 == index ? 32'h0 : _GEN_1283; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1285 = 11'h505 == index ? 32'h0 : _GEN_1284; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1286 = 11'h506 == index ? 32'h0 : _GEN_1285; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1287 = 11'h507 == index ? 32'h0 : _GEN_1286; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1288 = 11'h508 == index ? 32'h0 : _GEN_1287; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1289 = 11'h509 == index ? 32'h0 : _GEN_1288; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1290 = 11'h50a == index ? 32'h0 : _GEN_1289; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1291 = 11'h50b == index ? 32'h0 : _GEN_1290; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1292 = 11'h50c == index ? 32'h0 : _GEN_1291; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1293 = 11'h50d == index ? 32'h0 : _GEN_1292; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1294 = 11'h50e == index ? 32'h0 : _GEN_1293; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1295 = 11'h50f == index ? 32'h0 : _GEN_1294; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1296 = 11'h510 == index ? 32'h0 : _GEN_1295; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1297 = 11'h511 == index ? 32'h0 : _GEN_1296; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1298 = 11'h512 == index ? 32'h0 : _GEN_1297; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1299 = 11'h513 == index ? 32'h0 : _GEN_1298; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1300 = 11'h514 == index ? 32'h0 : _GEN_1299; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1301 = 11'h515 == index ? 32'h0 : _GEN_1300; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1302 = 11'h516 == index ? 32'h0 : _GEN_1301; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1303 = 11'h517 == index ? 32'h0 : _GEN_1302; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1304 = 11'h518 == index ? 32'h0 : _GEN_1303; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1305 = 11'h519 == index ? 32'h0 : _GEN_1304; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1306 = 11'h51a == index ? 32'h0 : _GEN_1305; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1307 = 11'h51b == index ? 32'h0 : _GEN_1306; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1308 = 11'h51c == index ? 32'h0 : _GEN_1307; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1309 = 11'h51d == index ? 32'h0 : _GEN_1308; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1310 = 11'h51e == index ? 32'h0 : _GEN_1309; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1311 = 11'h51f == index ? 32'h0 : _GEN_1310; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1312 = 11'h520 == index ? 32'h0 : _GEN_1311; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1313 = 11'h521 == index ? 32'h0 : _GEN_1312; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1314 = 11'h522 == index ? 32'h0 : _GEN_1313; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1315 = 11'h523 == index ? 32'h0 : _GEN_1314; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1316 = 11'h524 == index ? 32'h0 : _GEN_1315; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1317 = 11'h525 == index ? 32'h0 : _GEN_1316; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1318 = 11'h526 == index ? 32'h0 : _GEN_1317; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1319 = 11'h527 == index ? 32'h0 : _GEN_1318; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1320 = 11'h528 == index ? 32'h0 : _GEN_1319; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1321 = 11'h529 == index ? 32'h0 : _GEN_1320; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1322 = 11'h52a == index ? 32'h0 : _GEN_1321; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1323 = 11'h52b == index ? 32'h0 : _GEN_1322; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1324 = 11'h52c == index ? 32'h0 : _GEN_1323; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1325 = 11'h52d == index ? 32'h0 : _GEN_1324; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1326 = 11'h52e == index ? 32'h0 : _GEN_1325; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1327 = 11'h52f == index ? 32'h0 : _GEN_1326; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1328 = 11'h530 == index ? 32'h0 : _GEN_1327; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1329 = 11'h531 == index ? 32'h0 : _GEN_1328; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1330 = 11'h532 == index ? 32'h0 : _GEN_1329; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1331 = 11'h533 == index ? 32'h0 : _GEN_1330; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1332 = 11'h534 == index ? 32'h0 : _GEN_1331; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1333 = 11'h535 == index ? 32'h0 : _GEN_1332; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1334 = 11'h536 == index ? 32'h0 : _GEN_1333; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1335 = 11'h537 == index ? 32'h0 : _GEN_1334; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1336 = 11'h538 == index ? 32'h0 : _GEN_1335; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1337 = 11'h539 == index ? 32'h0 : _GEN_1336; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1338 = 11'h53a == index ? 32'h0 : _GEN_1337; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1339 = 11'h53b == index ? 32'h0 : _GEN_1338; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1340 = 11'h53c == index ? 32'h0 : _GEN_1339; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1341 = 11'h53d == index ? 32'h0 : _GEN_1340; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1342 = 11'h53e == index ? 32'h0 : _GEN_1341; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1343 = 11'h53f == index ? 32'h0 : _GEN_1342; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1344 = 11'h540 == index ? 32'h0 : _GEN_1343; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1345 = 11'h541 == index ? 32'h0 : _GEN_1344; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1346 = 11'h542 == index ? 32'h0 : _GEN_1345; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1347 = 11'h543 == index ? 32'h0 : _GEN_1346; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1348 = 11'h544 == index ? 32'h0 : _GEN_1347; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1349 = 11'h545 == index ? 32'h0 : _GEN_1348; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1350 = 11'h546 == index ? 32'h0 : _GEN_1349; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1351 = 11'h547 == index ? 32'h0 : _GEN_1350; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1352 = 11'h548 == index ? 32'h0 : _GEN_1351; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1353 = 11'h549 == index ? 32'h0 : _GEN_1352; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1354 = 11'h54a == index ? 32'h0 : _GEN_1353; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1355 = 11'h54b == index ? 32'h0 : _GEN_1354; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1356 = 11'h54c == index ? 32'h0 : _GEN_1355; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1357 = 11'h54d == index ? 32'h0 : _GEN_1356; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1358 = 11'h54e == index ? 32'h0 : _GEN_1357; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1359 = 11'h54f == index ? 32'h0 : _GEN_1358; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1360 = 11'h550 == index ? 32'h0 : _GEN_1359; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1361 = 11'h551 == index ? 32'h0 : _GEN_1360; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1362 = 11'h552 == index ? 32'h0 : _GEN_1361; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1363 = 11'h553 == index ? 32'h0 : _GEN_1362; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1364 = 11'h554 == index ? 32'h0 : _GEN_1363; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1365 = 11'h555 == index ? 32'h0 : _GEN_1364; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1366 = 11'h556 == index ? 32'h0 : _GEN_1365; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1367 = 11'h557 == index ? 32'h0 : _GEN_1366; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1368 = 11'h558 == index ? 32'h0 : _GEN_1367; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1369 = 11'h559 == index ? 32'h0 : _GEN_1368; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1370 = 11'h55a == index ? 32'h0 : _GEN_1369; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1371 = 11'h55b == index ? 32'h0 : _GEN_1370; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1372 = 11'h55c == index ? 32'h0 : _GEN_1371; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1373 = 11'h55d == index ? 32'h0 : _GEN_1372; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1374 = 11'h55e == index ? 32'h0 : _GEN_1373; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1375 = 11'h55f == index ? 32'h0 : _GEN_1374; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1376 = 11'h560 == index ? 32'h0 : _GEN_1375; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1377 = 11'h561 == index ? 32'h0 : _GEN_1376; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1378 = 11'h562 == index ? 32'h0 : _GEN_1377; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1379 = 11'h563 == index ? 32'h0 : _GEN_1378; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1380 = 11'h564 == index ? 32'h0 : _GEN_1379; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1381 = 11'h565 == index ? 32'h0 : _GEN_1380; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1382 = 11'h566 == index ? 32'h0 : _GEN_1381; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1383 = 11'h567 == index ? 32'h0 : _GEN_1382; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1384 = 11'h568 == index ? 32'h0 : _GEN_1383; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1385 = 11'h569 == index ? 32'h0 : _GEN_1384; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1386 = 11'h56a == index ? 32'h0 : _GEN_1385; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1387 = 11'h56b == index ? 32'h0 : _GEN_1386; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1388 = 11'h56c == index ? 32'h0 : _GEN_1387; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1389 = 11'h56d == index ? 32'h0 : _GEN_1388; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1390 = 11'h56e == index ? 32'h0 : _GEN_1389; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1391 = 11'h56f == index ? 32'h0 : _GEN_1390; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1392 = 11'h570 == index ? 32'h0 : _GEN_1391; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1393 = 11'h571 == index ? 32'h0 : _GEN_1392; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1394 = 11'h572 == index ? 32'h0 : _GEN_1393; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1395 = 11'h573 == index ? 32'h0 : _GEN_1394; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1396 = 11'h574 == index ? 32'h0 : _GEN_1395; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1397 = 11'h575 == index ? 32'h0 : _GEN_1396; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1398 = 11'h576 == index ? 32'h0 : _GEN_1397; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1399 = 11'h577 == index ? 32'h0 : _GEN_1398; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1400 = 11'h578 == index ? 32'h0 : _GEN_1399; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1401 = 11'h579 == index ? 32'h0 : _GEN_1400; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1402 = 11'h57a == index ? 32'h0 : _GEN_1401; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1403 = 11'h57b == index ? 32'h0 : _GEN_1402; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1404 = 11'h57c == index ? 32'h0 : _GEN_1403; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1405 = 11'h57d == index ? 32'h0 : _GEN_1404; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1406 = 11'h57e == index ? 32'h0 : _GEN_1405; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1407 = 11'h57f == index ? 32'h0 : _GEN_1406; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1408 = 11'h580 == index ? 32'h0 : _GEN_1407; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1409 = 11'h581 == index ? 32'h0 : _GEN_1408; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1410 = 11'h582 == index ? 32'h0 : _GEN_1409; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1411 = 11'h583 == index ? 32'h0 : _GEN_1410; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1412 = 11'h584 == index ? 32'h0 : _GEN_1411; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1413 = 11'h585 == index ? 32'h0 : _GEN_1412; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1414 = 11'h586 == index ? 32'h0 : _GEN_1413; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1415 = 11'h587 == index ? 32'h0 : _GEN_1414; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1416 = 11'h588 == index ? 32'h0 : _GEN_1415; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1417 = 11'h589 == index ? 32'h0 : _GEN_1416; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1418 = 11'h58a == index ? 32'h0 : _GEN_1417; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1419 = 11'h58b == index ? 32'h0 : _GEN_1418; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1420 = 11'h58c == index ? 32'h0 : _GEN_1419; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1421 = 11'h58d == index ? 32'h0 : _GEN_1420; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1422 = 11'h58e == index ? 32'h0 : _GEN_1421; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1423 = 11'h58f == index ? 32'h0 : _GEN_1422; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1424 = 11'h590 == index ? 32'h0 : _GEN_1423; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1425 = 11'h591 == index ? 32'h0 : _GEN_1424; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1426 = 11'h592 == index ? 32'h0 : _GEN_1425; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1427 = 11'h593 == index ? 32'h0 : _GEN_1426; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1428 = 11'h594 == index ? 32'h0 : _GEN_1427; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1429 = 11'h595 == index ? 32'h0 : _GEN_1428; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1430 = 11'h596 == index ? 32'h0 : _GEN_1429; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1431 = 11'h597 == index ? 32'h0 : _GEN_1430; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1432 = 11'h598 == index ? 32'h0 : _GEN_1431; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1433 = 11'h599 == index ? 32'h0 : _GEN_1432; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1434 = 11'h59a == index ? 32'h0 : _GEN_1433; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1435 = 11'h59b == index ? 32'h0 : _GEN_1434; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1436 = 11'h59c == index ? 32'h0 : _GEN_1435; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1437 = 11'h59d == index ? 32'h0 : _GEN_1436; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1438 = 11'h59e == index ? 32'h0 : _GEN_1437; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1439 = 11'h59f == index ? 32'h0 : _GEN_1438; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1440 = 11'h5a0 == index ? 32'h0 : _GEN_1439; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1441 = 11'h5a1 == index ? 32'h0 : _GEN_1440; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1442 = 11'h5a2 == index ? 32'h0 : _GEN_1441; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1443 = 11'h5a3 == index ? 32'h0 : _GEN_1442; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1444 = 11'h5a4 == index ? 32'h0 : _GEN_1443; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1445 = 11'h5a5 == index ? 32'h0 : _GEN_1444; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1446 = 11'h5a6 == index ? 32'h0 : _GEN_1445; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1447 = 11'h5a7 == index ? 32'h0 : _GEN_1446; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1448 = 11'h5a8 == index ? 32'h0 : _GEN_1447; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1449 = 11'h5a9 == index ? 32'h0 : _GEN_1448; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1450 = 11'h5aa == index ? 32'h0 : _GEN_1449; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1451 = 11'h5ab == index ? 32'h0 : _GEN_1450; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1452 = 11'h5ac == index ? 32'h0 : _GEN_1451; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1453 = 11'h5ad == index ? 32'h0 : _GEN_1452; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1454 = 11'h5ae == index ? 32'h0 : _GEN_1453; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1455 = 11'h5af == index ? 32'h0 : _GEN_1454; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1456 = 11'h5b0 == index ? 32'h0 : _GEN_1455; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1457 = 11'h5b1 == index ? 32'h0 : _GEN_1456; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1458 = 11'h5b2 == index ? 32'h0 : _GEN_1457; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1459 = 11'h5b3 == index ? 32'h0 : _GEN_1458; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1460 = 11'h5b4 == index ? 32'h0 : _GEN_1459; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1461 = 11'h5b5 == index ? 32'h0 : _GEN_1460; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1462 = 11'h5b6 == index ? 32'h0 : _GEN_1461; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1463 = 11'h5b7 == index ? 32'h0 : _GEN_1462; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1464 = 11'h5b8 == index ? 32'h0 : _GEN_1463; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1465 = 11'h5b9 == index ? 32'h0 : _GEN_1464; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1466 = 11'h5ba == index ? 32'h0 : _GEN_1465; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1467 = 11'h5bb == index ? 32'h0 : _GEN_1466; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1468 = 11'h5bc == index ? 32'h0 : _GEN_1467; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1469 = 11'h5bd == index ? 32'h0 : _GEN_1468; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1470 = 11'h5be == index ? 32'h0 : _GEN_1469; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1471 = 11'h5bf == index ? 32'h0 : _GEN_1470; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1472 = 11'h5c0 == index ? 32'h0 : _GEN_1471; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1473 = 11'h5c1 == index ? 32'h0 : _GEN_1472; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1474 = 11'h5c2 == index ? 32'h0 : _GEN_1473; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1475 = 11'h5c3 == index ? 32'h0 : _GEN_1474; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1476 = 11'h5c4 == index ? 32'h0 : _GEN_1475; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1477 = 11'h5c5 == index ? 32'h0 : _GEN_1476; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1478 = 11'h5c6 == index ? 32'h0 : _GEN_1477; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1479 = 11'h5c7 == index ? 32'h0 : _GEN_1478; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1480 = 11'h5c8 == index ? 32'h0 : _GEN_1479; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1481 = 11'h5c9 == index ? 32'h0 : _GEN_1480; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1482 = 11'h5ca == index ? 32'h0 : _GEN_1481; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1483 = 11'h5cb == index ? 32'h0 : _GEN_1482; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1484 = 11'h5cc == index ? 32'h0 : _GEN_1483; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1485 = 11'h5cd == index ? 32'h0 : _GEN_1484; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1486 = 11'h5ce == index ? 32'h0 : _GEN_1485; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1487 = 11'h5cf == index ? 32'h0 : _GEN_1486; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1488 = 11'h5d0 == index ? 32'h0 : _GEN_1487; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1489 = 11'h5d1 == index ? 32'h0 : _GEN_1488; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1490 = 11'h5d2 == index ? 32'h0 : _GEN_1489; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1491 = 11'h5d3 == index ? 32'h0 : _GEN_1490; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1492 = 11'h5d4 == index ? 32'h0 : _GEN_1491; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1493 = 11'h5d5 == index ? 32'h0 : _GEN_1492; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1494 = 11'h5d6 == index ? 32'h0 : _GEN_1493; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1495 = 11'h5d7 == index ? 32'h0 : _GEN_1494; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1496 = 11'h5d8 == index ? 32'h0 : _GEN_1495; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1497 = 11'h5d9 == index ? 32'h0 : _GEN_1496; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1498 = 11'h5da == index ? 32'h0 : _GEN_1497; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1499 = 11'h5db == index ? 32'h0 : _GEN_1498; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1500 = 11'h5dc == index ? 32'h0 : _GEN_1499; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1501 = 11'h5dd == index ? 32'h0 : _GEN_1500; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1502 = 11'h5de == index ? 32'h0 : _GEN_1501; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1503 = 11'h5df == index ? 32'h0 : _GEN_1502; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1504 = 11'h5e0 == index ? 32'h0 : _GEN_1503; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1505 = 11'h5e1 == index ? 32'h0 : _GEN_1504; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1506 = 11'h5e2 == index ? 32'h0 : _GEN_1505; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1507 = 11'h5e3 == index ? 32'h0 : _GEN_1506; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1508 = 11'h5e4 == index ? 32'h0 : _GEN_1507; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1509 = 11'h5e5 == index ? 32'h0 : _GEN_1508; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1510 = 11'h5e6 == index ? 32'h0 : _GEN_1509; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1511 = 11'h5e7 == index ? 32'h0 : _GEN_1510; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1512 = 11'h5e8 == index ? 32'h0 : _GEN_1511; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1513 = 11'h5e9 == index ? 32'h0 : _GEN_1512; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1514 = 11'h5ea == index ? 32'h0 : _GEN_1513; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1515 = 11'h5eb == index ? 32'h0 : _GEN_1514; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1516 = 11'h5ec == index ? 32'h0 : _GEN_1515; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1517 = 11'h5ed == index ? 32'h0 : _GEN_1516; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1518 = 11'h5ee == index ? 32'h0 : _GEN_1517; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1519 = 11'h5ef == index ? 32'h0 : _GEN_1518; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1520 = 11'h5f0 == index ? 32'h0 : _GEN_1519; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1521 = 11'h5f1 == index ? 32'h0 : _GEN_1520; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1522 = 11'h5f2 == index ? 32'h0 : _GEN_1521; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1523 = 11'h5f3 == index ? 32'h0 : _GEN_1522; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1524 = 11'h5f4 == index ? 32'h0 : _GEN_1523; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1525 = 11'h5f5 == index ? 32'h0 : _GEN_1524; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1526 = 11'h5f6 == index ? 32'h0 : _GEN_1525; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1527 = 11'h5f7 == index ? 32'h0 : _GEN_1526; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1528 = 11'h5f8 == index ? 32'h0 : _GEN_1527; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1529 = 11'h5f9 == index ? 32'h0 : _GEN_1528; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1530 = 11'h5fa == index ? 32'h0 : _GEN_1529; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1531 = 11'h5fb == index ? 32'h0 : _GEN_1530; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1532 = 11'h5fc == index ? 32'h0 : _GEN_1531; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1533 = 11'h5fd == index ? 32'h0 : _GEN_1532; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1534 = 11'h5fe == index ? 32'h0 : _GEN_1533; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1535 = 11'h5ff == index ? 32'h0 : _GEN_1534; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1536 = 11'h600 == index ? 32'h0 : _GEN_1535; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1537 = 11'h601 == index ? 32'h0 : _GEN_1536; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1538 = 11'h602 == index ? 32'h0 : _GEN_1537; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1539 = 11'h603 == index ? 32'h0 : _GEN_1538; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1540 = 11'h604 == index ? 32'h0 : _GEN_1539; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1541 = 11'h605 == index ? 32'h0 : _GEN_1540; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1542 = 11'h606 == index ? 32'h0 : _GEN_1541; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1543 = 11'h607 == index ? 32'h0 : _GEN_1542; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1544 = 11'h608 == index ? 32'h0 : _GEN_1543; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1545 = 11'h609 == index ? 32'h0 : _GEN_1544; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1546 = 11'h60a == index ? 32'h0 : _GEN_1545; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1547 = 11'h60b == index ? 32'h0 : _GEN_1546; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1548 = 11'h60c == index ? 32'h0 : _GEN_1547; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1549 = 11'h60d == index ? 32'h0 : _GEN_1548; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1550 = 11'h60e == index ? 32'h0 : _GEN_1549; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1551 = 11'h60f == index ? 32'h0 : _GEN_1550; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1552 = 11'h610 == index ? 32'h0 : _GEN_1551; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1553 = 11'h611 == index ? 32'h0 : _GEN_1552; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1554 = 11'h612 == index ? 32'h0 : _GEN_1553; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1555 = 11'h613 == index ? 32'h0 : _GEN_1554; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1556 = 11'h614 == index ? 32'h0 : _GEN_1555; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1557 = 11'h615 == index ? 32'h0 : _GEN_1556; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1558 = 11'h616 == index ? 32'h0 : _GEN_1557; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1559 = 11'h617 == index ? 32'h0 : _GEN_1558; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1560 = 11'h618 == index ? 32'h0 : _GEN_1559; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1561 = 11'h619 == index ? 32'h0 : _GEN_1560; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1562 = 11'h61a == index ? 32'h0 : _GEN_1561; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1563 = 11'h61b == index ? 32'h0 : _GEN_1562; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1564 = 11'h61c == index ? 32'h0 : _GEN_1563; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1565 = 11'h61d == index ? 32'h0 : _GEN_1564; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1566 = 11'h61e == index ? 32'h0 : _GEN_1565; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1567 = 11'h61f == index ? 32'h0 : _GEN_1566; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1568 = 11'h620 == index ? 32'h0 : _GEN_1567; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1569 = 11'h621 == index ? 32'h0 : _GEN_1568; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1570 = 11'h622 == index ? 32'h0 : _GEN_1569; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1571 = 11'h623 == index ? 32'h0 : _GEN_1570; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1572 = 11'h624 == index ? 32'h0 : _GEN_1571; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1573 = 11'h625 == index ? 32'h0 : _GEN_1572; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1574 = 11'h626 == index ? 32'h0 : _GEN_1573; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1575 = 11'h627 == index ? 32'h0 : _GEN_1574; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1576 = 11'h628 == index ? 32'h0 : _GEN_1575; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1577 = 11'h629 == index ? 32'h0 : _GEN_1576; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1578 = 11'h62a == index ? 32'h0 : _GEN_1577; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1579 = 11'h62b == index ? 32'h0 : _GEN_1578; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1580 = 11'h62c == index ? 32'h0 : _GEN_1579; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1581 = 11'h62d == index ? 32'h0 : _GEN_1580; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1582 = 11'h62e == index ? 32'h0 : _GEN_1581; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1583 = 11'h62f == index ? 32'h0 : _GEN_1582; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1584 = 11'h630 == index ? 32'h0 : _GEN_1583; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1585 = 11'h631 == index ? 32'h0 : _GEN_1584; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1586 = 11'h632 == index ? 32'h0 : _GEN_1585; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1587 = 11'h633 == index ? 32'h0 : _GEN_1586; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1588 = 11'h634 == index ? 32'h0 : _GEN_1587; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1589 = 11'h635 == index ? 32'h0 : _GEN_1588; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1590 = 11'h636 == index ? 32'h0 : _GEN_1589; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1591 = 11'h637 == index ? 32'h0 : _GEN_1590; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1592 = 11'h638 == index ? 32'h0 : _GEN_1591; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1593 = 11'h639 == index ? 32'h0 : _GEN_1592; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1594 = 11'h63a == index ? 32'h0 : _GEN_1593; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1595 = 11'h63b == index ? 32'h0 : _GEN_1594; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1596 = 11'h63c == index ? 32'h0 : _GEN_1595; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1597 = 11'h63d == index ? 32'h0 : _GEN_1596; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1598 = 11'h63e == index ? 32'h0 : _GEN_1597; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1599 = 11'h63f == index ? 32'h0 : _GEN_1598; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1600 = 11'h640 == index ? 32'h0 : _GEN_1599; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1601 = 11'h641 == index ? 32'h0 : _GEN_1600; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1602 = 11'h642 == index ? 32'h0 : _GEN_1601; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1603 = 11'h643 == index ? 32'h0 : _GEN_1602; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1604 = 11'h644 == index ? 32'h0 : _GEN_1603; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1605 = 11'h645 == index ? 32'h0 : _GEN_1604; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1606 = 11'h646 == index ? 32'h0 : _GEN_1605; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1607 = 11'h647 == index ? 32'h0 : _GEN_1606; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1608 = 11'h648 == index ? 32'h0 : _GEN_1607; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1609 = 11'h649 == index ? 32'h0 : _GEN_1608; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1610 = 11'h64a == index ? 32'h0 : _GEN_1609; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1611 = 11'h64b == index ? 32'h0 : _GEN_1610; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1612 = 11'h64c == index ? 32'h0 : _GEN_1611; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1613 = 11'h64d == index ? 32'h0 : _GEN_1612; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1614 = 11'h64e == index ? 32'h0 : _GEN_1613; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1615 = 11'h64f == index ? 32'h0 : _GEN_1614; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1616 = 11'h650 == index ? 32'h0 : _GEN_1615; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1617 = 11'h651 == index ? 32'h0 : _GEN_1616; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1618 = 11'h652 == index ? 32'h0 : _GEN_1617; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1619 = 11'h653 == index ? 32'h0 : _GEN_1618; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1620 = 11'h654 == index ? 32'h0 : _GEN_1619; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1621 = 11'h655 == index ? 32'h0 : _GEN_1620; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1622 = 11'h656 == index ? 32'h0 : _GEN_1621; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1623 = 11'h657 == index ? 32'h0 : _GEN_1622; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1624 = 11'h658 == index ? 32'h0 : _GEN_1623; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1625 = 11'h659 == index ? 32'h0 : _GEN_1624; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1626 = 11'h65a == index ? 32'h0 : _GEN_1625; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1627 = 11'h65b == index ? 32'h0 : _GEN_1626; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1628 = 11'h65c == index ? 32'h0 : _GEN_1627; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1629 = 11'h65d == index ? 32'h0 : _GEN_1628; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1630 = 11'h65e == index ? 32'h0 : _GEN_1629; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1631 = 11'h65f == index ? 32'h0 : _GEN_1630; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1632 = 11'h660 == index ? 32'h0 : _GEN_1631; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1633 = 11'h661 == index ? 32'h0 : _GEN_1632; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1634 = 11'h662 == index ? 32'h0 : _GEN_1633; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1635 = 11'h663 == index ? 32'h0 : _GEN_1634; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1636 = 11'h664 == index ? 32'h0 : _GEN_1635; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1637 = 11'h665 == index ? 32'h0 : _GEN_1636; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1638 = 11'h666 == index ? 32'h0 : _GEN_1637; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1639 = 11'h667 == index ? 32'h0 : _GEN_1638; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1640 = 11'h668 == index ? 32'h0 : _GEN_1639; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1641 = 11'h669 == index ? 32'h0 : _GEN_1640; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1642 = 11'h66a == index ? 32'h0 : _GEN_1641; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1643 = 11'h66b == index ? 32'h0 : _GEN_1642; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1644 = 11'h66c == index ? 32'h0 : _GEN_1643; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1645 = 11'h66d == index ? 32'h0 : _GEN_1644; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1646 = 11'h66e == index ? 32'h0 : _GEN_1645; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1647 = 11'h66f == index ? 32'h0 : _GEN_1646; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1648 = 11'h670 == index ? 32'h0 : _GEN_1647; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1649 = 11'h671 == index ? 32'h0 : _GEN_1648; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1650 = 11'h672 == index ? 32'h0 : _GEN_1649; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1651 = 11'h673 == index ? 32'h0 : _GEN_1650; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1652 = 11'h674 == index ? 32'h0 : _GEN_1651; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1653 = 11'h675 == index ? 32'h0 : _GEN_1652; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1654 = 11'h676 == index ? 32'h0 : _GEN_1653; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1655 = 11'h677 == index ? 32'h0 : _GEN_1654; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1656 = 11'h678 == index ? 32'h0 : _GEN_1655; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1657 = 11'h679 == index ? 32'h0 : _GEN_1656; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1658 = 11'h67a == index ? 32'h0 : _GEN_1657; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1659 = 11'h67b == index ? 32'h0 : _GEN_1658; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1660 = 11'h67c == index ? 32'h0 : _GEN_1659; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1661 = 11'h67d == index ? 32'h0 : _GEN_1660; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1662 = 11'h67e == index ? 32'h0 : _GEN_1661; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1663 = 11'h67f == index ? 32'h0 : _GEN_1662; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1664 = 11'h680 == index ? 32'h0 : _GEN_1663; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1665 = 11'h681 == index ? 32'h0 : _GEN_1664; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1666 = 11'h682 == index ? 32'h0 : _GEN_1665; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1667 = 11'h683 == index ? 32'h0 : _GEN_1666; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1668 = 11'h684 == index ? 32'h0 : _GEN_1667; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1669 = 11'h685 == index ? 32'h0 : _GEN_1668; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1670 = 11'h686 == index ? 32'h0 : _GEN_1669; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1671 = 11'h687 == index ? 32'h0 : _GEN_1670; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1672 = 11'h688 == index ? 32'h0 : _GEN_1671; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1673 = 11'h689 == index ? 32'h0 : _GEN_1672; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1674 = 11'h68a == index ? 32'h0 : _GEN_1673; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1675 = 11'h68b == index ? 32'h0 : _GEN_1674; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1676 = 11'h68c == index ? 32'h0 : _GEN_1675; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1677 = 11'h68d == index ? 32'h0 : _GEN_1676; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1678 = 11'h68e == index ? 32'h0 : _GEN_1677; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1679 = 11'h68f == index ? 32'h0 : _GEN_1678; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1680 = 11'h690 == index ? 32'h0 : _GEN_1679; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1681 = 11'h691 == index ? 32'h0 : _GEN_1680; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1682 = 11'h692 == index ? 32'h0 : _GEN_1681; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1683 = 11'h693 == index ? 32'h0 : _GEN_1682; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1684 = 11'h694 == index ? 32'h0 : _GEN_1683; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1685 = 11'h695 == index ? 32'h0 : _GEN_1684; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1686 = 11'h696 == index ? 32'h0 : _GEN_1685; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1687 = 11'h697 == index ? 32'h0 : _GEN_1686; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1688 = 11'h698 == index ? 32'h0 : _GEN_1687; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1689 = 11'h699 == index ? 32'h0 : _GEN_1688; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1690 = 11'h69a == index ? 32'h0 : _GEN_1689; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1691 = 11'h69b == index ? 32'h0 : _GEN_1690; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1692 = 11'h69c == index ? 32'h0 : _GEN_1691; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1693 = 11'h69d == index ? 32'h0 : _GEN_1692; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1694 = 11'h69e == index ? 32'h0 : _GEN_1693; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1695 = 11'h69f == index ? 32'h0 : _GEN_1694; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1696 = 11'h6a0 == index ? 32'h0 : _GEN_1695; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1697 = 11'h6a1 == index ? 32'h0 : _GEN_1696; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1698 = 11'h6a2 == index ? 32'h0 : _GEN_1697; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1699 = 11'h6a3 == index ? 32'h0 : _GEN_1698; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1700 = 11'h6a4 == index ? 32'h0 : _GEN_1699; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1701 = 11'h6a5 == index ? 32'h0 : _GEN_1700; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1702 = 11'h6a6 == index ? 32'h0 : _GEN_1701; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1703 = 11'h6a7 == index ? 32'h0 : _GEN_1702; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1704 = 11'h6a8 == index ? 32'h0 : _GEN_1703; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1705 = 11'h6a9 == index ? 32'h0 : _GEN_1704; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1706 = 11'h6aa == index ? 32'h0 : _GEN_1705; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1707 = 11'h6ab == index ? 32'h0 : _GEN_1706; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1708 = 11'h6ac == index ? 32'h0 : _GEN_1707; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1709 = 11'h6ad == index ? 32'h0 : _GEN_1708; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1710 = 11'h6ae == index ? 32'h0 : _GEN_1709; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1711 = 11'h6af == index ? 32'h0 : _GEN_1710; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1712 = 11'h6b0 == index ? 32'h0 : _GEN_1711; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1713 = 11'h6b1 == index ? 32'h0 : _GEN_1712; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1714 = 11'h6b2 == index ? 32'h0 : _GEN_1713; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1715 = 11'h6b3 == index ? 32'h0 : _GEN_1714; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1716 = 11'h6b4 == index ? 32'h0 : _GEN_1715; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1717 = 11'h6b5 == index ? 32'h0 : _GEN_1716; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1718 = 11'h6b6 == index ? 32'h0 : _GEN_1717; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1719 = 11'h6b7 == index ? 32'h0 : _GEN_1718; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1720 = 11'h6b8 == index ? 32'h0 : _GEN_1719; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1721 = 11'h6b9 == index ? 32'h0 : _GEN_1720; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1722 = 11'h6ba == index ? 32'h0 : _GEN_1721; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1723 = 11'h6bb == index ? 32'h0 : _GEN_1722; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1724 = 11'h6bc == index ? 32'h0 : _GEN_1723; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1725 = 11'h6bd == index ? 32'h0 : _GEN_1724; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1726 = 11'h6be == index ? 32'h0 : _GEN_1725; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1727 = 11'h6bf == index ? 32'h0 : _GEN_1726; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1728 = 11'h6c0 == index ? 32'h0 : _GEN_1727; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1729 = 11'h6c1 == index ? 32'h0 : _GEN_1728; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1730 = 11'h6c2 == index ? 32'h0 : _GEN_1729; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1731 = 11'h6c3 == index ? 32'h0 : _GEN_1730; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1732 = 11'h6c4 == index ? 32'h0 : _GEN_1731; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1733 = 11'h6c5 == index ? 32'h0 : _GEN_1732; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1734 = 11'h6c6 == index ? 32'h0 : _GEN_1733; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1735 = 11'h6c7 == index ? 32'h0 : _GEN_1734; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1736 = 11'h6c8 == index ? 32'h0 : _GEN_1735; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1737 = 11'h6c9 == index ? 32'h0 : _GEN_1736; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1738 = 11'h6ca == index ? 32'h0 : _GEN_1737; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1739 = 11'h6cb == index ? 32'h0 : _GEN_1738; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1740 = 11'h6cc == index ? 32'h0 : _GEN_1739; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1741 = 11'h6cd == index ? 32'h0 : _GEN_1740; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1742 = 11'h6ce == index ? 32'h0 : _GEN_1741; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1743 = 11'h6cf == index ? 32'h0 : _GEN_1742; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1744 = 11'h6d0 == index ? 32'h0 : _GEN_1743; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1745 = 11'h6d1 == index ? 32'h0 : _GEN_1744; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1746 = 11'h6d2 == index ? 32'h0 : _GEN_1745; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1747 = 11'h6d3 == index ? 32'h0 : _GEN_1746; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1748 = 11'h6d4 == index ? 32'h0 : _GEN_1747; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1749 = 11'h6d5 == index ? 32'h0 : _GEN_1748; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1750 = 11'h6d6 == index ? 32'h0 : _GEN_1749; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1751 = 11'h6d7 == index ? 32'h0 : _GEN_1750; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1752 = 11'h6d8 == index ? 32'h0 : _GEN_1751; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1753 = 11'h6d9 == index ? 32'h0 : _GEN_1752; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1754 = 11'h6da == index ? 32'h0 : _GEN_1753; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1755 = 11'h6db == index ? 32'h0 : _GEN_1754; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1756 = 11'h6dc == index ? 32'h0 : _GEN_1755; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1757 = 11'h6dd == index ? 32'h0 : _GEN_1756; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1758 = 11'h6de == index ? 32'h0 : _GEN_1757; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1759 = 11'h6df == index ? 32'h0 : _GEN_1758; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1760 = 11'h6e0 == index ? 32'h0 : _GEN_1759; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1761 = 11'h6e1 == index ? 32'h0 : _GEN_1760; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1762 = 11'h6e2 == index ? 32'h0 : _GEN_1761; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1763 = 11'h6e3 == index ? 32'h0 : _GEN_1762; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1764 = 11'h6e4 == index ? 32'h0 : _GEN_1763; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1765 = 11'h6e5 == index ? 32'h0 : _GEN_1764; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1766 = 11'h6e6 == index ? 32'h0 : _GEN_1765; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1767 = 11'h6e7 == index ? 32'h0 : _GEN_1766; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1768 = 11'h6e8 == index ? 32'h0 : _GEN_1767; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1769 = 11'h6e9 == index ? 32'h0 : _GEN_1768; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1770 = 11'h6ea == index ? 32'h0 : _GEN_1769; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1771 = 11'h6eb == index ? 32'h0 : _GEN_1770; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1772 = 11'h6ec == index ? 32'h0 : _GEN_1771; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1773 = 11'h6ed == index ? 32'h0 : _GEN_1772; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1774 = 11'h6ee == index ? 32'h0 : _GEN_1773; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1775 = 11'h6ef == index ? 32'h0 : _GEN_1774; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1776 = 11'h6f0 == index ? 32'h0 : _GEN_1775; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1777 = 11'h6f1 == index ? 32'h0 : _GEN_1776; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1778 = 11'h6f2 == index ? 32'h0 : _GEN_1777; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1779 = 11'h6f3 == index ? 32'h0 : _GEN_1778; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1780 = 11'h6f4 == index ? 32'h0 : _GEN_1779; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1781 = 11'h6f5 == index ? 32'h0 : _GEN_1780; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1782 = 11'h6f6 == index ? 32'h0 : _GEN_1781; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1783 = 11'h6f7 == index ? 32'h0 : _GEN_1782; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1784 = 11'h6f8 == index ? 32'h0 : _GEN_1783; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1785 = 11'h6f9 == index ? 32'h0 : _GEN_1784; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1786 = 11'h6fa == index ? 32'h0 : _GEN_1785; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1787 = 11'h6fb == index ? 32'h0 : _GEN_1786; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1788 = 11'h6fc == index ? 32'h0 : _GEN_1787; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1789 = 11'h6fd == index ? 32'h0 : _GEN_1788; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1790 = 11'h6fe == index ? 32'h0 : _GEN_1789; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1791 = 11'h6ff == index ? 32'h0 : _GEN_1790; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1792 = 11'h700 == index ? 32'h0 : _GEN_1791; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1793 = 11'h701 == index ? 32'h0 : _GEN_1792; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1794 = 11'h702 == index ? 32'h0 : _GEN_1793; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1795 = 11'h703 == index ? 32'h0 : _GEN_1794; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1796 = 11'h704 == index ? 32'h0 : _GEN_1795; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1797 = 11'h705 == index ? 32'h0 : _GEN_1796; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1798 = 11'h706 == index ? 32'h0 : _GEN_1797; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1799 = 11'h707 == index ? 32'h0 : _GEN_1798; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1800 = 11'h708 == index ? 32'h0 : _GEN_1799; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1801 = 11'h709 == index ? 32'h0 : _GEN_1800; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1802 = 11'h70a == index ? 32'h0 : _GEN_1801; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1803 = 11'h70b == index ? 32'h0 : _GEN_1802; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1804 = 11'h70c == index ? 32'h0 : _GEN_1803; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1805 = 11'h70d == index ? 32'h0 : _GEN_1804; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1806 = 11'h70e == index ? 32'h0 : _GEN_1805; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1807 = 11'h70f == index ? 32'h0 : _GEN_1806; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1808 = 11'h710 == index ? 32'h0 : _GEN_1807; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1809 = 11'h711 == index ? 32'h0 : _GEN_1808; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1810 = 11'h712 == index ? 32'h0 : _GEN_1809; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1811 = 11'h713 == index ? 32'h0 : _GEN_1810; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1812 = 11'h714 == index ? 32'h0 : _GEN_1811; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1813 = 11'h715 == index ? 32'h0 : _GEN_1812; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1814 = 11'h716 == index ? 32'h0 : _GEN_1813; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1815 = 11'h717 == index ? 32'h0 : _GEN_1814; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1816 = 11'h718 == index ? 32'h0 : _GEN_1815; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1817 = 11'h719 == index ? 32'h0 : _GEN_1816; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1818 = 11'h71a == index ? 32'h0 : _GEN_1817; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1819 = 11'h71b == index ? 32'h0 : _GEN_1818; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1820 = 11'h71c == index ? 32'h0 : _GEN_1819; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1821 = 11'h71d == index ? 32'h0 : _GEN_1820; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1822 = 11'h71e == index ? 32'h0 : _GEN_1821; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1823 = 11'h71f == index ? 32'h0 : _GEN_1822; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1824 = 11'h720 == index ? 32'h0 : _GEN_1823; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1825 = 11'h721 == index ? 32'h0 : _GEN_1824; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1826 = 11'h722 == index ? 32'h0 : _GEN_1825; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1827 = 11'h723 == index ? 32'h0 : _GEN_1826; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1828 = 11'h724 == index ? 32'h0 : _GEN_1827; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1829 = 11'h725 == index ? 32'h0 : _GEN_1828; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1830 = 11'h726 == index ? 32'h0 : _GEN_1829; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1831 = 11'h727 == index ? 32'h0 : _GEN_1830; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1832 = 11'h728 == index ? 32'h0 : _GEN_1831; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1833 = 11'h729 == index ? 32'h0 : _GEN_1832; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1834 = 11'h72a == index ? 32'h0 : _GEN_1833; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1835 = 11'h72b == index ? 32'h0 : _GEN_1834; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1836 = 11'h72c == index ? 32'h0 : _GEN_1835; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1837 = 11'h72d == index ? 32'h0 : _GEN_1836; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1838 = 11'h72e == index ? 32'h0 : _GEN_1837; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1839 = 11'h72f == index ? 32'h0 : _GEN_1838; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1840 = 11'h730 == index ? 32'h0 : _GEN_1839; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1841 = 11'h731 == index ? 32'h0 : _GEN_1840; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1842 = 11'h732 == index ? 32'h0 : _GEN_1841; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1843 = 11'h733 == index ? 32'h0 : _GEN_1842; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1844 = 11'h734 == index ? 32'h0 : _GEN_1843; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1845 = 11'h735 == index ? 32'h0 : _GEN_1844; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1846 = 11'h736 == index ? 32'h0 : _GEN_1845; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1847 = 11'h737 == index ? 32'h0 : _GEN_1846; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1848 = 11'h738 == index ? 32'h0 : _GEN_1847; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1849 = 11'h739 == index ? 32'h0 : _GEN_1848; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1850 = 11'h73a == index ? 32'h0 : _GEN_1849; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1851 = 11'h73b == index ? 32'h0 : _GEN_1850; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1852 = 11'h73c == index ? 32'h0 : _GEN_1851; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1853 = 11'h73d == index ? 32'h0 : _GEN_1852; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1854 = 11'h73e == index ? 32'h0 : _GEN_1853; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1855 = 11'h73f == index ? 32'h0 : _GEN_1854; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1856 = 11'h740 == index ? 32'h0 : _GEN_1855; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1857 = 11'h741 == index ? 32'h0 : _GEN_1856; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1858 = 11'h742 == index ? 32'h0 : _GEN_1857; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1859 = 11'h743 == index ? 32'h0 : _GEN_1858; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1860 = 11'h744 == index ? 32'h0 : _GEN_1859; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1861 = 11'h745 == index ? 32'h0 : _GEN_1860; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1862 = 11'h746 == index ? 32'h0 : _GEN_1861; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1863 = 11'h747 == index ? 32'h0 : _GEN_1862; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1864 = 11'h748 == index ? 32'h0 : _GEN_1863; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1865 = 11'h749 == index ? 32'h0 : _GEN_1864; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1866 = 11'h74a == index ? 32'h0 : _GEN_1865; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1867 = 11'h74b == index ? 32'h0 : _GEN_1866; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1868 = 11'h74c == index ? 32'h0 : _GEN_1867; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1869 = 11'h74d == index ? 32'h0 : _GEN_1868; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1870 = 11'h74e == index ? 32'h0 : _GEN_1869; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1871 = 11'h74f == index ? 32'h0 : _GEN_1870; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1872 = 11'h750 == index ? 32'h0 : _GEN_1871; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1873 = 11'h751 == index ? 32'h0 : _GEN_1872; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1874 = 11'h752 == index ? 32'h0 : _GEN_1873; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1875 = 11'h753 == index ? 32'h0 : _GEN_1874; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1876 = 11'h754 == index ? 32'h0 : _GEN_1875; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1877 = 11'h755 == index ? 32'h0 : _GEN_1876; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1878 = 11'h756 == index ? 32'h0 : _GEN_1877; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1879 = 11'h757 == index ? 32'h0 : _GEN_1878; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1880 = 11'h758 == index ? 32'h0 : _GEN_1879; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1881 = 11'h759 == index ? 32'h0 : _GEN_1880; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1882 = 11'h75a == index ? 32'h0 : _GEN_1881; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1883 = 11'h75b == index ? 32'h0 : _GEN_1882; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1884 = 11'h75c == index ? 32'h0 : _GEN_1883; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1885 = 11'h75d == index ? 32'h0 : _GEN_1884; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1886 = 11'h75e == index ? 32'h0 : _GEN_1885; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1887 = 11'h75f == index ? 32'h0 : _GEN_1886; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1888 = 11'h760 == index ? 32'h0 : _GEN_1887; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1889 = 11'h761 == index ? 32'h0 : _GEN_1888; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1890 = 11'h762 == index ? 32'h0 : _GEN_1889; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1891 = 11'h763 == index ? 32'h0 : _GEN_1890; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1892 = 11'h764 == index ? 32'h0 : _GEN_1891; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1893 = 11'h765 == index ? 32'h0 : _GEN_1892; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1894 = 11'h766 == index ? 32'h0 : _GEN_1893; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1895 = 11'h767 == index ? 32'h0 : _GEN_1894; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1896 = 11'h768 == index ? 32'h0 : _GEN_1895; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1897 = 11'h769 == index ? 32'h0 : _GEN_1896; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1898 = 11'h76a == index ? 32'h0 : _GEN_1897; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1899 = 11'h76b == index ? 32'h0 : _GEN_1898; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1900 = 11'h76c == index ? 32'h0 : _GEN_1899; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1901 = 11'h76d == index ? 32'h0 : _GEN_1900; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1902 = 11'h76e == index ? 32'h0 : _GEN_1901; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1903 = 11'h76f == index ? 32'h0 : _GEN_1902; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1904 = 11'h770 == index ? 32'h0 : _GEN_1903; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1905 = 11'h771 == index ? 32'h0 : _GEN_1904; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1906 = 11'h772 == index ? 32'h0 : _GEN_1905; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1907 = 11'h773 == index ? 32'h0 : _GEN_1906; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1908 = 11'h774 == index ? 32'h0 : _GEN_1907; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1909 = 11'h775 == index ? 32'h0 : _GEN_1908; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1910 = 11'h776 == index ? 32'h0 : _GEN_1909; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1911 = 11'h777 == index ? 32'h0 : _GEN_1910; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1912 = 11'h778 == index ? 32'h0 : _GEN_1911; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1913 = 11'h779 == index ? 32'h0 : _GEN_1912; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1914 = 11'h77a == index ? 32'h0 : _GEN_1913; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1915 = 11'h77b == index ? 32'h0 : _GEN_1914; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1916 = 11'h77c == index ? 32'h0 : _GEN_1915; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1917 = 11'h77d == index ? 32'h0 : _GEN_1916; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1918 = 11'h77e == index ? 32'h0 : _GEN_1917; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1919 = 11'h77f == index ? 32'h0 : _GEN_1918; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1920 = 11'h780 == index ? 32'h0 : _GEN_1919; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1921 = 11'h781 == index ? 32'h0 : _GEN_1920; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1922 = 11'h782 == index ? 32'h0 : _GEN_1921; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1923 = 11'h783 == index ? 32'h0 : _GEN_1922; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1924 = 11'h784 == index ? 32'h0 : _GEN_1923; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1925 = 11'h785 == index ? 32'h0 : _GEN_1924; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1926 = 11'h786 == index ? 32'h0 : _GEN_1925; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1927 = 11'h787 == index ? 32'h0 : _GEN_1926; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1928 = 11'h788 == index ? 32'h0 : _GEN_1927; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1929 = 11'h789 == index ? 32'h0 : _GEN_1928; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1930 = 11'h78a == index ? 32'h0 : _GEN_1929; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1931 = 11'h78b == index ? 32'h0 : _GEN_1930; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1932 = 11'h78c == index ? 32'h0 : _GEN_1931; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1933 = 11'h78d == index ? 32'h0 : _GEN_1932; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1934 = 11'h78e == index ? 32'h0 : _GEN_1933; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1935 = 11'h78f == index ? 32'h0 : _GEN_1934; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1936 = 11'h790 == index ? 32'h0 : _GEN_1935; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1937 = 11'h791 == index ? 32'h0 : _GEN_1936; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1938 = 11'h792 == index ? 32'h0 : _GEN_1937; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1939 = 11'h793 == index ? 32'h0 : _GEN_1938; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1940 = 11'h794 == index ? 32'h0 : _GEN_1939; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1941 = 11'h795 == index ? 32'h0 : _GEN_1940; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1942 = 11'h796 == index ? 32'h0 : _GEN_1941; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1943 = 11'h797 == index ? 32'h0 : _GEN_1942; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1944 = 11'h798 == index ? 32'h0 : _GEN_1943; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1945 = 11'h799 == index ? 32'h0 : _GEN_1944; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1946 = 11'h79a == index ? 32'h0 : _GEN_1945; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1947 = 11'h79b == index ? 32'h0 : _GEN_1946; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1948 = 11'h79c == index ? 32'h0 : _GEN_1947; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1949 = 11'h79d == index ? 32'h0 : _GEN_1948; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1950 = 11'h79e == index ? 32'h0 : _GEN_1949; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1951 = 11'h79f == index ? 32'h0 : _GEN_1950; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1952 = 11'h7a0 == index ? 32'h0 : _GEN_1951; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1953 = 11'h7a1 == index ? 32'h0 : _GEN_1952; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1954 = 11'h7a2 == index ? 32'h0 : _GEN_1953; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1955 = 11'h7a3 == index ? 32'h0 : _GEN_1954; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1956 = 11'h7a4 == index ? 32'h0 : _GEN_1955; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1957 = 11'h7a5 == index ? 32'h0 : _GEN_1956; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1958 = 11'h7a6 == index ? 32'h0 : _GEN_1957; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1959 = 11'h7a7 == index ? 32'h0 : _GEN_1958; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1960 = 11'h7a8 == index ? 32'h0 : _GEN_1959; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1961 = 11'h7a9 == index ? 32'h0 : _GEN_1960; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1962 = 11'h7aa == index ? 32'h0 : _GEN_1961; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1963 = 11'h7ab == index ? 32'h0 : _GEN_1962; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1964 = 11'h7ac == index ? 32'h0 : _GEN_1963; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1965 = 11'h7ad == index ? 32'h0 : _GEN_1964; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1966 = 11'h7ae == index ? 32'h0 : _GEN_1965; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1967 = 11'h7af == index ? 32'h0 : _GEN_1966; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1968 = 11'h7b0 == index ? 32'h0 : _GEN_1967; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1969 = 11'h7b1 == index ? 32'h0 : _GEN_1968; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1970 = 11'h7b2 == index ? 32'h0 : _GEN_1969; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1971 = 11'h7b3 == index ? 32'h0 : _GEN_1970; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1972 = 11'h7b4 == index ? 32'h0 : _GEN_1971; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1973 = 11'h7b5 == index ? 32'h0 : _GEN_1972; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1974 = 11'h7b6 == index ? 32'h0 : _GEN_1973; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1975 = 11'h7b7 == index ? 32'h0 : _GEN_1974; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1976 = 11'h7b8 == index ? 32'h0 : _GEN_1975; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1977 = 11'h7b9 == index ? 32'h0 : _GEN_1976; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1978 = 11'h7ba == index ? 32'h0 : _GEN_1977; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1979 = 11'h7bb == index ? 32'h0 : _GEN_1978; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1980 = 11'h7bc == index ? 32'h0 : _GEN_1979; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1981 = 11'h7bd == index ? 32'h0 : _GEN_1980; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1982 = 11'h7be == index ? 32'h0 : _GEN_1981; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1983 = 11'h7bf == index ? 32'h0 : _GEN_1982; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1984 = 11'h7c0 == index ? 32'h0 : _GEN_1983; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1985 = 11'h7c1 == index ? 32'h0 : _GEN_1984; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1986 = 11'h7c2 == index ? 32'h0 : _GEN_1985; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1987 = 11'h7c3 == index ? 32'h0 : _GEN_1986; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1988 = 11'h7c4 == index ? 32'h0 : _GEN_1987; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1989 = 11'h7c5 == index ? 32'h0 : _GEN_1988; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1990 = 11'h7c6 == index ? 32'h0 : _GEN_1989; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1991 = 11'h7c7 == index ? 32'h0 : _GEN_1990; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1992 = 11'h7c8 == index ? 32'h0 : _GEN_1991; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1993 = 11'h7c9 == index ? 32'h0 : _GEN_1992; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1994 = 11'h7ca == index ? 32'h0 : _GEN_1993; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1995 = 11'h7cb == index ? 32'h0 : _GEN_1994; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1996 = 11'h7cc == index ? 32'h0 : _GEN_1995; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1997 = 11'h7cd == index ? 32'h0 : _GEN_1996; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1998 = 11'h7ce == index ? 32'h0 : _GEN_1997; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_1999 = 11'h7cf == index ? 32'h0 : _GEN_1998; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2000 = 11'h7d0 == index ? 32'h0 : _GEN_1999; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2001 = 11'h7d1 == index ? 32'h0 : _GEN_2000; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2002 = 11'h7d2 == index ? 32'h0 : _GEN_2001; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2003 = 11'h7d3 == index ? 32'h0 : _GEN_2002; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2004 = 11'h7d4 == index ? 32'h0 : _GEN_2003; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2005 = 11'h7d5 == index ? 32'h0 : _GEN_2004; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2006 = 11'h7d6 == index ? 32'h0 : _GEN_2005; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2007 = 11'h7d7 == index ? 32'h0 : _GEN_2006; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2008 = 11'h7d8 == index ? 32'h0 : _GEN_2007; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2009 = 11'h7d9 == index ? 32'h0 : _GEN_2008; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2010 = 11'h7da == index ? 32'h0 : _GEN_2009; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2011 = 11'h7db == index ? 32'h0 : _GEN_2010; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2012 = 11'h7dc == index ? 32'h0 : _GEN_2011; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2013 = 11'h7dd == index ? 32'h0 : _GEN_2012; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2014 = 11'h7de == index ? 32'h0 : _GEN_2013; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2015 = 11'h7df == index ? 32'h0 : _GEN_2014; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2016 = 11'h7e0 == index ? 32'h0 : _GEN_2015; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2017 = 11'h7e1 == index ? 32'h0 : _GEN_2016; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2018 = 11'h7e2 == index ? 32'h0 : _GEN_2017; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2019 = 11'h7e3 == index ? 32'h0 : _GEN_2018; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2020 = 11'h7e4 == index ? 32'h0 : _GEN_2019; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2021 = 11'h7e5 == index ? 32'h0 : _GEN_2020; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2022 = 11'h7e6 == index ? 32'h0 : _GEN_2021; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2023 = 11'h7e7 == index ? 32'h0 : _GEN_2022; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2024 = 11'h7e8 == index ? 32'h0 : _GEN_2023; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2025 = 11'h7e9 == index ? 32'h0 : _GEN_2024; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2026 = 11'h7ea == index ? 32'h0 : _GEN_2025; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2027 = 11'h7eb == index ? 32'h0 : _GEN_2026; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2028 = 11'h7ec == index ? 32'h0 : _GEN_2027; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2029 = 11'h7ed == index ? 32'h0 : _GEN_2028; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2030 = 11'h7ee == index ? 32'h0 : _GEN_2029; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2031 = 11'h7ef == index ? 32'h0 : _GEN_2030; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2032 = 11'h7f0 == index ? 32'h0 : _GEN_2031; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2033 = 11'h7f1 == index ? 32'h0 : _GEN_2032; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2034 = 11'h7f2 == index ? 32'h0 : _GEN_2033; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2035 = 11'h7f3 == index ? 32'h0 : _GEN_2034; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2036 = 11'h7f4 == index ? 32'h0 : _GEN_2035; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2037 = 11'h7f5 == index ? 32'h0 : _GEN_2036; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2038 = 11'h7f6 == index ? 32'h0 : _GEN_2037; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2039 = 11'h7f7 == index ? 32'h0 : _GEN_2038; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2040 = 11'h7f8 == index ? 32'h0 : _GEN_2039; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2041 = 11'h7f9 == index ? 32'h0 : _GEN_2040; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2042 = 11'h7fa == index ? 32'h0 : _GEN_2041; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2043 = 11'h7fb == index ? 32'h0 : _GEN_2042; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2044 = 11'h7fc == index ? 32'h0 : _GEN_2043; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2045 = 11'h7fd == index ? 32'h0 : _GEN_2044; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2046 = 11'h7fe == index ? 32'h0 : _GEN_2045; // @[BootROM.scala 51:{47,47}]
  wire [31:0] _GEN_2047 = 11'h7ff == index ? 32'h0 : _GEN_2046; // @[BootROM.scala 51:{47,47}]
  TLMonitor_72 monitor ( // @[Nodes.scala 24:25]
    .clock(monitor_clock),
    .reset(monitor_reset),
    .io_in_a_ready(monitor_io_in_a_ready),
    .io_in_a_valid(monitor_io_in_a_valid),
    .io_in_a_bits_opcode(monitor_io_in_a_bits_opcode),
    .io_in_a_bits_param(monitor_io_in_a_bits_param),
    .io_in_a_bits_size(monitor_io_in_a_bits_size),
    .io_in_a_bits_source(monitor_io_in_a_bits_source),
    .io_in_a_bits_address(monitor_io_in_a_bits_address),
    .io_in_a_bits_mask(monitor_io_in_a_bits_mask),
    .io_in_a_bits_corrupt(monitor_io_in_a_bits_corrupt),
    .io_in_d_ready(monitor_io_in_d_ready),
    .io_in_d_valid(monitor_io_in_d_valid),
    .io_in_d_bits_size(monitor_io_in_d_bits_size),
    .io_in_d_bits_source(monitor_io_in_d_bits_source)
  );
  assign auto_in_a_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_in_d_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_in_d_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_in_d_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign auto_in_d_bits_data = |high ? 32'h0 : _GEN_2047; // @[BootROM.scala 51:47]
  assign monitor_clock = clock;
  assign monitor_reset = reset;
  assign monitor_io_in_a_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_valid = auto_in_a_valid; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_bits_size = auto_in_a_bits_size; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign monitor_io_in_d_bits_source = auto_in_a_bits_source; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
module ClockSinkDomain_15(
  output        auto_bootrom_in_a_ready,
  input         auto_bootrom_in_a_valid,
  input  [2:0]  auto_bootrom_in_a_bits_opcode,
  input  [2:0]  auto_bootrom_in_a_bits_param,
  input  [1:0]  auto_bootrom_in_a_bits_size,
  input  [6:0]  auto_bootrom_in_a_bits_source,
  input  [16:0] auto_bootrom_in_a_bits_address,
  input  [3:0]  auto_bootrom_in_a_bits_mask,
  input         auto_bootrom_in_a_bits_corrupt,
  input         auto_bootrom_in_d_ready,
  output        auto_bootrom_in_d_valid,
  output [1:0]  auto_bootrom_in_d_bits_size,
  output [6:0]  auto_bootrom_in_d_bits_source,
  output [31:0] auto_bootrom_in_d_bits_data,
  input         auto_clock_in_clock,
  input         auto_clock_in_reset
);
  wire  bootrom_clock; // @[BootROM.scala 81:17]
  wire  bootrom_reset; // @[BootROM.scala 81:17]
  wire  bootrom_auto_in_a_ready; // @[BootROM.scala 81:17]
  wire  bootrom_auto_in_a_valid; // @[BootROM.scala 81:17]
  wire [2:0] bootrom_auto_in_a_bits_opcode; // @[BootROM.scala 81:17]
  wire [2:0] bootrom_auto_in_a_bits_param; // @[BootROM.scala 81:17]
  wire [1:0] bootrom_auto_in_a_bits_size; // @[BootROM.scala 81:17]
  wire [6:0] bootrom_auto_in_a_bits_source; // @[BootROM.scala 81:17]
  wire [16:0] bootrom_auto_in_a_bits_address; // @[BootROM.scala 81:17]
  wire [3:0] bootrom_auto_in_a_bits_mask; // @[BootROM.scala 81:17]
  wire  bootrom_auto_in_a_bits_corrupt; // @[BootROM.scala 81:17]
  wire  bootrom_auto_in_d_ready; // @[BootROM.scala 81:17]
  wire  bootrom_auto_in_d_valid; // @[BootROM.scala 81:17]
  wire [1:0] bootrom_auto_in_d_bits_size; // @[BootROM.scala 81:17]
  wire [6:0] bootrom_auto_in_d_bits_source; // @[BootROM.scala 81:17]
  wire [31:0] bootrom_auto_in_d_bits_data; // @[BootROM.scala 81:17]
  TLROM bootrom ( // @[BootROM.scala 81:17]
    .clock(bootrom_clock),
    .reset(bootrom_reset),
    .auto_in_a_ready(bootrom_auto_in_a_ready),
    .auto_in_a_valid(bootrom_auto_in_a_valid),
    .auto_in_a_bits_opcode(bootrom_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(bootrom_auto_in_a_bits_param),
    .auto_in_a_bits_size(bootrom_auto_in_a_bits_size),
    .auto_in_a_bits_source(bootrom_auto_in_a_bits_source),
    .auto_in_a_bits_address(bootrom_auto_in_a_bits_address),
    .auto_in_a_bits_mask(bootrom_auto_in_a_bits_mask),
    .auto_in_a_bits_corrupt(bootrom_auto_in_a_bits_corrupt),
    .auto_in_d_ready(bootrom_auto_in_d_ready),
    .auto_in_d_valid(bootrom_auto_in_d_valid),
    .auto_in_d_bits_size(bootrom_auto_in_d_bits_size),
    .auto_in_d_bits_source(bootrom_auto_in_d_bits_source),
    .auto_in_d_bits_data(bootrom_auto_in_d_bits_data)
  );
  assign auto_bootrom_in_a_ready = bootrom_auto_in_a_ready; // @[LazyModule.scala 309:16]
  assign auto_bootrom_in_d_valid = bootrom_auto_in_d_valid; // @[LazyModule.scala 309:16]
  assign auto_bootrom_in_d_bits_size = bootrom_auto_in_d_bits_size; // @[LazyModule.scala 309:16]
  assign auto_bootrom_in_d_bits_source = bootrom_auto_in_d_bits_source; // @[LazyModule.scala 309:16]
  assign auto_bootrom_in_d_bits_data = bootrom_auto_in_d_bits_data; // @[LazyModule.scala 309:16]
  assign bootrom_clock = auto_clock_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bootrom_reset = auto_clock_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
  assign bootrom_auto_in_a_valid = auto_bootrom_in_a_valid; // @[LazyModule.scala 309:16]
  assign bootrom_auto_in_a_bits_opcode = auto_bootrom_in_a_bits_opcode; // @[LazyModule.scala 309:16]
  assign bootrom_auto_in_a_bits_param = auto_bootrom_in_a_bits_param; // @[LazyModule.scala 309:16]
  assign bootrom_auto_in_a_bits_size = auto_bootrom_in_a_bits_size; // @[LazyModule.scala 309:16]
  assign bootrom_auto_in_a_bits_source = auto_bootrom_in_a_bits_source; // @[LazyModule.scala 309:16]
  assign bootrom_auto_in_a_bits_address = auto_bootrom_in_a_bits_address; // @[LazyModule.scala 309:16]
  assign bootrom_auto_in_a_bits_mask = auto_bootrom_in_a_bits_mask; // @[LazyModule.scala 309:16]
  assign bootrom_auto_in_a_bits_corrupt = auto_bootrom_in_a_bits_corrupt; // @[LazyModule.scala 309:16]
  assign bootrom_auto_in_d_ready = auto_bootrom_in_d_ready; // @[LazyModule.scala 309:16]
endmodule
module CaptureUpdateChain(
  input        clock,
  input        reset,
  input        io_chainIn_shift,
  input        io_chainIn_data,
  input        io_chainIn_capture,
  input        io_chainIn_update,
  output       io_chainOut_data,
  input  [1:0] io_capture_bits_dmiStatus,
  output       io_update_valid,
  output       io_update_bits_dmireset
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
`endif // RANDOMIZE_REG_INIT
  reg  regs_0; // @[JtagShifter.scala 154:39]
  reg  regs_1; // @[JtagShifter.scala 154:39]
  reg  regs_2; // @[JtagShifter.scala 154:39]
  reg  regs_3; // @[JtagShifter.scala 154:39]
  reg  regs_4; // @[JtagShifter.scala 154:39]
  reg  regs_5; // @[JtagShifter.scala 154:39]
  reg  regs_6; // @[JtagShifter.scala 154:39]
  reg  regs_7; // @[JtagShifter.scala 154:39]
  reg  regs_8; // @[JtagShifter.scala 154:39]
  reg  regs_9; // @[JtagShifter.scala 154:39]
  reg  regs_10; // @[JtagShifter.scala 154:39]
  reg  regs_11; // @[JtagShifter.scala 154:39]
  reg  regs_12; // @[JtagShifter.scala 154:39]
  reg  regs_13; // @[JtagShifter.scala 154:39]
  reg  regs_14; // @[JtagShifter.scala 154:39]
  reg  regs_15; // @[JtagShifter.scala 154:39]
  reg  regs_16; // @[JtagShifter.scala 154:39]
  reg  regs_17; // @[JtagShifter.scala 154:39]
  reg  regs_18; // @[JtagShifter.scala 154:39]
  reg  regs_19; // @[JtagShifter.scala 154:39]
  reg  regs_20; // @[JtagShifter.scala 154:39]
  reg  regs_21; // @[JtagShifter.scala 154:39]
  reg  regs_22; // @[JtagShifter.scala 154:39]
  reg  regs_23; // @[JtagShifter.scala 154:39]
  reg  regs_24; // @[JtagShifter.scala 154:39]
  reg  regs_25; // @[JtagShifter.scala 154:39]
  reg  regs_26; // @[JtagShifter.scala 154:39]
  reg  regs_27; // @[JtagShifter.scala 154:39]
  reg  regs_28; // @[JtagShifter.scala 154:39]
  reg  regs_29; // @[JtagShifter.scala 154:39]
  reg  regs_30; // @[JtagShifter.scala 154:39]
  reg  regs_31; // @[JtagShifter.scala 154:39]
  wire [7:0] updateBits_lo_lo = {regs_7,regs_6,regs_5,regs_4,regs_3,regs_2,regs_1,regs_0}; // @[Cat.scala 31:58]
  wire [15:0] updateBits_lo = {regs_15,regs_14,regs_13,regs_12,regs_11,regs_10,regs_9,regs_8,updateBits_lo_lo}; // @[Cat.scala 31:58]
  wire [7:0] updateBits_hi_lo = {regs_23,regs_22,regs_21,regs_20,regs_19,regs_18,regs_17,regs_16}; // @[Cat.scala 31:58]
  wire [31:0] updateBits = {regs_31,regs_30,regs_29,regs_28,regs_27,regs_26,regs_25,regs_24,updateBits_hi_lo,
    updateBits_lo}; // @[Cat.scala 31:58]
  wire [31:0] captureBits = {20'h5,io_capture_bits_dmiStatus,6'h7,4'h1}; // @[JtagShifter.scala 161:43]
  wire  _T_1 = ~(io_chainIn_capture & io_chainIn_update); // @[JtagShifter.scala 183:10]
  wire  _T_4 = _T_1 & ~(io_chainIn_capture & io_chainIn_shift); // @[JtagShifter.scala 184:7]
  wire  _T_7 = _T_4 & ~(io_chainIn_update & io_chainIn_shift); // @[JtagShifter.scala 185:7]
  assign io_chainOut_data = regs_0; // @[JtagShifter.scala 156:20]
  assign io_update_valid = io_chainIn_capture ? 1'h0 : io_chainIn_update; // @[JtagShifter.scala 166:29 170:21]
  assign io_update_bits_dmireset = updateBits[16]; // @[JtagShifter.scala 159:40]
  always @(posedge clock) begin
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_0 <= captureBits[0]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_0 <= regs_1; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_1 <= captureBits[1]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_1 <= regs_2; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_2 <= captureBits[2]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_2 <= regs_3; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_3 <= captureBits[3]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_3 <= regs_4; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_4 <= captureBits[4]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_4 <= regs_5; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_5 <= captureBits[5]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_5 <= regs_6; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_6 <= captureBits[6]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_6 <= regs_7; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_7 <= captureBits[7]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_7 <= regs_8; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_8 <= captureBits[8]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_8 <= regs_9; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_9 <= captureBits[9]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_9 <= regs_10; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_10 <= captureBits[10]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_10 <= regs_11; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_11 <= captureBits[11]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_11 <= regs_12; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_12 <= captureBits[12]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_12 <= regs_13; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_13 <= captureBits[13]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_13 <= regs_14; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_14 <= captureBits[14]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_14 <= regs_15; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_15 <= captureBits[15]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_15 <= regs_16; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_16 <= captureBits[16]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_16 <= regs_17; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_17 <= captureBits[17]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_17 <= regs_18; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_18 <= captureBits[18]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_18 <= regs_19; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_19 <= captureBits[19]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_19 <= regs_20; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_20 <= captureBits[20]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_20 <= regs_21; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_21 <= captureBits[21]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_21 <= regs_22; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_22 <= captureBits[22]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_22 <= regs_23; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_23 <= captureBits[23]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_23 <= regs_24; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_24 <= captureBits[24]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_24 <= regs_25; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_25 <= captureBits[25]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_25 <= regs_26; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_26 <= captureBits[26]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_26 <= regs_27; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_27 <= captureBits[27]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_27 <= regs_28; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_28 <= captureBits[28]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_28 <= regs_29; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_29 <= captureBits[29]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_29 <= regs_30; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_30 <= captureBits[30]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_30 <= regs_31; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_31 <= captureBits[31]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_31 <= io_chainIn_data; // @[JtagShifter.scala 175:15]
      end
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_7 & ~reset) begin
          $fatal; // @[JtagShifter.scala 183:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_7) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at JtagShifter.scala:183 assert(!(io.chainIn.capture && io.chainIn.update)\n"); // @[JtagShifter.scala 183:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  regs_0 = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  regs_1 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  regs_2 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  regs_3 = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  regs_4 = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  regs_5 = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  regs_6 = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  regs_7 = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  regs_8 = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  regs_9 = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  regs_10 = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  regs_11 = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  regs_12 = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  regs_13 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  regs_14 = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  regs_15 = _RAND_15[0:0];
  _RAND_16 = {1{`RANDOM}};
  regs_16 = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  regs_17 = _RAND_17[0:0];
  _RAND_18 = {1{`RANDOM}};
  regs_18 = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  regs_19 = _RAND_19[0:0];
  _RAND_20 = {1{`RANDOM}};
  regs_20 = _RAND_20[0:0];
  _RAND_21 = {1{`RANDOM}};
  regs_21 = _RAND_21[0:0];
  _RAND_22 = {1{`RANDOM}};
  regs_22 = _RAND_22[0:0];
  _RAND_23 = {1{`RANDOM}};
  regs_23 = _RAND_23[0:0];
  _RAND_24 = {1{`RANDOM}};
  regs_24 = _RAND_24[0:0];
  _RAND_25 = {1{`RANDOM}};
  regs_25 = _RAND_25[0:0];
  _RAND_26 = {1{`RANDOM}};
  regs_26 = _RAND_26[0:0];
  _RAND_27 = {1{`RANDOM}};
  regs_27 = _RAND_27[0:0];
  _RAND_28 = {1{`RANDOM}};
  regs_28 = _RAND_28[0:0];
  _RAND_29 = {1{`RANDOM}};
  regs_29 = _RAND_29[0:0];
  _RAND_30 = {1{`RANDOM}};
  regs_30 = _RAND_30[0:0];
  _RAND_31 = {1{`RANDOM}};
  regs_31 = _RAND_31[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module CaptureUpdateChain_1(
  input         clock,
  input         reset,
  input         io_chainIn_shift,
  input         io_chainIn_data,
  input         io_chainIn_capture,
  input         io_chainIn_update,
  output        io_chainOut_data,
  input  [6:0]  io_capture_bits_addr,
  input  [31:0] io_capture_bits_data,
  input  [1:0]  io_capture_bits_resp,
  output        io_capture_capture,
  output        io_update_valid,
  output [6:0]  io_update_bits_addr,
  output [31:0] io_update_bits_data,
  output [1:0]  io_update_bits_op
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [31:0] _RAND_33;
  reg [31:0] _RAND_34;
  reg [31:0] _RAND_35;
  reg [31:0] _RAND_36;
  reg [31:0] _RAND_37;
  reg [31:0] _RAND_38;
  reg [31:0] _RAND_39;
  reg [31:0] _RAND_40;
`endif // RANDOMIZE_REG_INIT
  reg  regs_0; // @[JtagShifter.scala 154:39]
  reg  regs_1; // @[JtagShifter.scala 154:39]
  reg  regs_2; // @[JtagShifter.scala 154:39]
  reg  regs_3; // @[JtagShifter.scala 154:39]
  reg  regs_4; // @[JtagShifter.scala 154:39]
  reg  regs_5; // @[JtagShifter.scala 154:39]
  reg  regs_6; // @[JtagShifter.scala 154:39]
  reg  regs_7; // @[JtagShifter.scala 154:39]
  reg  regs_8; // @[JtagShifter.scala 154:39]
  reg  regs_9; // @[JtagShifter.scala 154:39]
  reg  regs_10; // @[JtagShifter.scala 154:39]
  reg  regs_11; // @[JtagShifter.scala 154:39]
  reg  regs_12; // @[JtagShifter.scala 154:39]
  reg  regs_13; // @[JtagShifter.scala 154:39]
  reg  regs_14; // @[JtagShifter.scala 154:39]
  reg  regs_15; // @[JtagShifter.scala 154:39]
  reg  regs_16; // @[JtagShifter.scala 154:39]
  reg  regs_17; // @[JtagShifter.scala 154:39]
  reg  regs_18; // @[JtagShifter.scala 154:39]
  reg  regs_19; // @[JtagShifter.scala 154:39]
  reg  regs_20; // @[JtagShifter.scala 154:39]
  reg  regs_21; // @[JtagShifter.scala 154:39]
  reg  regs_22; // @[JtagShifter.scala 154:39]
  reg  regs_23; // @[JtagShifter.scala 154:39]
  reg  regs_24; // @[JtagShifter.scala 154:39]
  reg  regs_25; // @[JtagShifter.scala 154:39]
  reg  regs_26; // @[JtagShifter.scala 154:39]
  reg  regs_27; // @[JtagShifter.scala 154:39]
  reg  regs_28; // @[JtagShifter.scala 154:39]
  reg  regs_29; // @[JtagShifter.scala 154:39]
  reg  regs_30; // @[JtagShifter.scala 154:39]
  reg  regs_31; // @[JtagShifter.scala 154:39]
  reg  regs_32; // @[JtagShifter.scala 154:39]
  reg  regs_33; // @[JtagShifter.scala 154:39]
  reg  regs_34; // @[JtagShifter.scala 154:39]
  reg  regs_35; // @[JtagShifter.scala 154:39]
  reg  regs_36; // @[JtagShifter.scala 154:39]
  reg  regs_37; // @[JtagShifter.scala 154:39]
  reg  regs_38; // @[JtagShifter.scala 154:39]
  reg  regs_39; // @[JtagShifter.scala 154:39]
  reg  regs_40; // @[JtagShifter.scala 154:39]
  wire [9:0] updateBits_lo_lo = {regs_9,regs_8,regs_7,regs_6,regs_5,regs_4,regs_3,regs_2,regs_1,regs_0}; // @[Cat.scala 31:58]
  wire [9:0] updateBits_lo_hi = {regs_19,regs_18,regs_17,regs_16,regs_15,regs_14,regs_13,regs_12,regs_11,regs_10}; // @[Cat.scala 31:58]
  wire [9:0] updateBits_hi_lo = {regs_29,regs_28,regs_27,regs_26,regs_25,regs_24,regs_23,regs_22,regs_21,regs_20}; // @[Cat.scala 31:58]
  wire [4:0] updateBits_hi_hi_lo = {regs_34,regs_33,regs_32,regs_31,regs_30}; // @[Cat.scala 31:58]
  wire [40:0] updateBits = {regs_40,regs_39,regs_38,regs_37,regs_36,regs_35,updateBits_hi_hi_lo,updateBits_hi_lo,
    updateBits_lo_hi,updateBits_lo_lo}; // @[Cat.scala 31:58]
  wire [40:0] captureBits = {io_capture_bits_addr,io_capture_bits_data,io_capture_bits_resp}; // @[JtagShifter.scala 161:43]
  wire  _T_1 = ~(io_chainIn_capture & io_chainIn_update); // @[JtagShifter.scala 183:10]
  wire  _T_4 = _T_1 & ~(io_chainIn_capture & io_chainIn_shift); // @[JtagShifter.scala 184:7]
  wire  _T_7 = _T_4 & ~(io_chainIn_update & io_chainIn_shift); // @[JtagShifter.scala 185:7]
  assign io_chainOut_data = regs_0; // @[JtagShifter.scala 156:20]
  assign io_capture_capture = io_chainIn_capture; // @[JtagShifter.scala 166:29 169:24]
  assign io_update_valid = io_chainIn_capture ? 1'h0 : io_chainIn_update; // @[JtagShifter.scala 166:29 170:21]
  assign io_update_bits_addr = updateBits[40:34]; // @[JtagShifter.scala 159:40]
  assign io_update_bits_data = updateBits[33:2]; // @[JtagShifter.scala 159:40]
  assign io_update_bits_op = updateBits[1:0]; // @[JtagShifter.scala 159:40]
  always @(posedge clock) begin
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_0 <= captureBits[0]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_0 <= regs_1; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_1 <= captureBits[1]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_1 <= regs_2; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_2 <= captureBits[2]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_2 <= regs_3; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_3 <= captureBits[3]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_3 <= regs_4; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_4 <= captureBits[4]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_4 <= regs_5; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_5 <= captureBits[5]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_5 <= regs_6; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_6 <= captureBits[6]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_6 <= regs_7; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_7 <= captureBits[7]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_7 <= regs_8; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_8 <= captureBits[8]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_8 <= regs_9; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_9 <= captureBits[9]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_9 <= regs_10; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_10 <= captureBits[10]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_10 <= regs_11; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_11 <= captureBits[11]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_11 <= regs_12; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_12 <= captureBits[12]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_12 <= regs_13; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_13 <= captureBits[13]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_13 <= regs_14; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_14 <= captureBits[14]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_14 <= regs_15; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_15 <= captureBits[15]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_15 <= regs_16; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_16 <= captureBits[16]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_16 <= regs_17; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_17 <= captureBits[17]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_17 <= regs_18; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_18 <= captureBits[18]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_18 <= regs_19; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_19 <= captureBits[19]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_19 <= regs_20; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_20 <= captureBits[20]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_20 <= regs_21; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_21 <= captureBits[21]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_21 <= regs_22; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_22 <= captureBits[22]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_22 <= regs_23; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_23 <= captureBits[23]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_23 <= regs_24; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_24 <= captureBits[24]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_24 <= regs_25; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_25 <= captureBits[25]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_25 <= regs_26; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_26 <= captureBits[26]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_26 <= regs_27; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_27 <= captureBits[27]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_27 <= regs_28; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_28 <= captureBits[28]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_28 <= regs_29; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_29 <= captureBits[29]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_29 <= regs_30; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_30 <= captureBits[30]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_30 <= regs_31; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_31 <= captureBits[31]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_31 <= regs_32; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_32 <= captureBits[32]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_32 <= regs_33; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_33 <= captureBits[33]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_33 <= regs_34; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_34 <= captureBits[34]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_34 <= regs_35; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_35 <= captureBits[35]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_35 <= regs_36; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_36 <= captureBits[36]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_36 <= regs_37; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_37 <= captureBits[37]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_37 <= regs_38; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_38 <= captureBits[38]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_38 <= regs_39; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_39 <= captureBits[39]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_39 <= regs_40; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_40 <= captureBits[40]; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_40 <= io_chainIn_data; // @[JtagShifter.scala 175:15]
      end
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_7 & ~reset) begin
          $fatal; // @[JtagShifter.scala 183:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_7) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at JtagShifter.scala:183 assert(!(io.chainIn.capture && io.chainIn.update)\n"); // @[JtagShifter.scala 183:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  regs_0 = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  regs_1 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  regs_2 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  regs_3 = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  regs_4 = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  regs_5 = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  regs_6 = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  regs_7 = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  regs_8 = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  regs_9 = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  regs_10 = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  regs_11 = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  regs_12 = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  regs_13 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  regs_14 = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  regs_15 = _RAND_15[0:0];
  _RAND_16 = {1{`RANDOM}};
  regs_16 = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  regs_17 = _RAND_17[0:0];
  _RAND_18 = {1{`RANDOM}};
  regs_18 = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  regs_19 = _RAND_19[0:0];
  _RAND_20 = {1{`RANDOM}};
  regs_20 = _RAND_20[0:0];
  _RAND_21 = {1{`RANDOM}};
  regs_21 = _RAND_21[0:0];
  _RAND_22 = {1{`RANDOM}};
  regs_22 = _RAND_22[0:0];
  _RAND_23 = {1{`RANDOM}};
  regs_23 = _RAND_23[0:0];
  _RAND_24 = {1{`RANDOM}};
  regs_24 = _RAND_24[0:0];
  _RAND_25 = {1{`RANDOM}};
  regs_25 = _RAND_25[0:0];
  _RAND_26 = {1{`RANDOM}};
  regs_26 = _RAND_26[0:0];
  _RAND_27 = {1{`RANDOM}};
  regs_27 = _RAND_27[0:0];
  _RAND_28 = {1{`RANDOM}};
  regs_28 = _RAND_28[0:0];
  _RAND_29 = {1{`RANDOM}};
  regs_29 = _RAND_29[0:0];
  _RAND_30 = {1{`RANDOM}};
  regs_30 = _RAND_30[0:0];
  _RAND_31 = {1{`RANDOM}};
  regs_31 = _RAND_31[0:0];
  _RAND_32 = {1{`RANDOM}};
  regs_32 = _RAND_32[0:0];
  _RAND_33 = {1{`RANDOM}};
  regs_33 = _RAND_33[0:0];
  _RAND_34 = {1{`RANDOM}};
  regs_34 = _RAND_34[0:0];
  _RAND_35 = {1{`RANDOM}};
  regs_35 = _RAND_35[0:0];
  _RAND_36 = {1{`RANDOM}};
  regs_36 = _RAND_36[0:0];
  _RAND_37 = {1{`RANDOM}};
  regs_37 = _RAND_37[0:0];
  _RAND_38 = {1{`RANDOM}};
  regs_38 = _RAND_38[0:0];
  _RAND_39 = {1{`RANDOM}};
  regs_39 = _RAND_39[0:0];
  _RAND_40 = {1{`RANDOM}};
  regs_40 = _RAND_40[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module CaptureChain(
  input   clock,
  input   reset,
  input   io_chainIn_shift,
  input   io_chainIn_data,
  input   io_chainIn_capture,
  input   io_chainIn_update,
  output  io_chainOut_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
`endif // RANDOMIZE_REG_INIT
  reg  regs_0; // @[JtagShifter.scala 101:39]
  reg  regs_1; // @[JtagShifter.scala 101:39]
  reg  regs_2; // @[JtagShifter.scala 101:39]
  reg  regs_3; // @[JtagShifter.scala 101:39]
  reg  regs_4; // @[JtagShifter.scala 101:39]
  reg  regs_5; // @[JtagShifter.scala 101:39]
  reg  regs_6; // @[JtagShifter.scala 101:39]
  reg  regs_7; // @[JtagShifter.scala 101:39]
  reg  regs_8; // @[JtagShifter.scala 101:39]
  reg  regs_9; // @[JtagShifter.scala 101:39]
  reg  regs_10; // @[JtagShifter.scala 101:39]
  reg  regs_11; // @[JtagShifter.scala 101:39]
  reg  regs_12; // @[JtagShifter.scala 101:39]
  reg  regs_13; // @[JtagShifter.scala 101:39]
  reg  regs_14; // @[JtagShifter.scala 101:39]
  reg  regs_15; // @[JtagShifter.scala 101:39]
  reg  regs_16; // @[JtagShifter.scala 101:39]
  reg  regs_17; // @[JtagShifter.scala 101:39]
  reg  regs_18; // @[JtagShifter.scala 101:39]
  reg  regs_19; // @[JtagShifter.scala 101:39]
  reg  regs_20; // @[JtagShifter.scala 101:39]
  reg  regs_21; // @[JtagShifter.scala 101:39]
  reg  regs_22; // @[JtagShifter.scala 101:39]
  reg  regs_23; // @[JtagShifter.scala 101:39]
  reg  regs_24; // @[JtagShifter.scala 101:39]
  reg  regs_25; // @[JtagShifter.scala 101:39]
  reg  regs_26; // @[JtagShifter.scala 101:39]
  reg  regs_27; // @[JtagShifter.scala 101:39]
  reg  regs_28; // @[JtagShifter.scala 101:39]
  reg  regs_29; // @[JtagShifter.scala 101:39]
  reg  regs_30; // @[JtagShifter.scala 101:39]
  reg  regs_31; // @[JtagShifter.scala 101:39]
  wire  _GEN_1 = io_chainIn_shift ? regs_1 : regs_0; // @[JtagShifter.scala 110:34 112:37 101:39]
  wire  _GEN_2 = io_chainIn_shift ? regs_2 : regs_1; // @[JtagShifter.scala 110:34 112:37 101:39]
  wire  _GEN_5 = io_chainIn_shift ? regs_5 : regs_4; // @[JtagShifter.scala 110:34 112:37 101:39]
  wire  _GEN_9 = io_chainIn_shift ? regs_9 : regs_8; // @[JtagShifter.scala 110:34 112:37 101:39]
  wire  _GEN_12 = io_chainIn_shift ? regs_12 : regs_11; // @[JtagShifter.scala 110:34 112:37 101:39]
  wire  _T_1 = ~(io_chainIn_capture & io_chainIn_update); // @[JtagShifter.scala 117:10]
  wire  _T_4 = _T_1 & ~(io_chainIn_capture & io_chainIn_shift); // @[JtagShifter.scala 118:7]
  wire  _T_7 = _T_4 & ~(io_chainIn_update & io_chainIn_shift); // @[JtagShifter.scala 119:7]
  assign io_chainOut_data = regs_0; // @[JtagShifter.scala 103:20]
  always @(posedge clock) begin
    regs_0 <= io_chainIn_capture | _GEN_1; // @[JtagShifter.scala 107:29 108:35]
    regs_1 <= io_chainIn_capture | _GEN_2; // @[JtagShifter.scala 107:29 108:35]
    if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
      regs_2 <= 1'h0; // @[JtagShifter.scala 108:35]
    end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
      regs_2 <= regs_3; // @[JtagShifter.scala 112:37]
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
      regs_3 <= 1'h0; // @[JtagShifter.scala 108:35]
    end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
      regs_3 <= regs_4; // @[JtagShifter.scala 112:37]
    end
    regs_4 <= io_chainIn_capture | _GEN_5; // @[JtagShifter.scala 107:29 108:35]
    if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
      regs_5 <= 1'h0; // @[JtagShifter.scala 108:35]
    end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
      regs_5 <= regs_6; // @[JtagShifter.scala 112:37]
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
      regs_6 <= 1'h0; // @[JtagShifter.scala 108:35]
    end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
      regs_6 <= regs_7; // @[JtagShifter.scala 112:37]
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
      regs_7 <= 1'h0; // @[JtagShifter.scala 108:35]
    end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
      regs_7 <= regs_8; // @[JtagShifter.scala 112:37]
    end
    regs_8 <= io_chainIn_capture | _GEN_9; // @[JtagShifter.scala 107:29 108:35]
    if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
      regs_9 <= 1'h0; // @[JtagShifter.scala 108:35]
    end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
      regs_9 <= regs_10; // @[JtagShifter.scala 112:37]
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
      regs_10 <= 1'h0; // @[JtagShifter.scala 108:35]
    end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
      regs_10 <= regs_11; // @[JtagShifter.scala 112:37]
    end
    regs_11 <= io_chainIn_capture | _GEN_12; // @[JtagShifter.scala 107:29 108:35]
    if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
      regs_12 <= 1'h0; // @[JtagShifter.scala 108:35]
    end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
      regs_12 <= regs_13; // @[JtagShifter.scala 112:37]
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
      regs_13 <= 1'h0; // @[JtagShifter.scala 108:35]
    end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
      regs_13 <= regs_14; // @[JtagShifter.scala 112:37]
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
      regs_14 <= 1'h0; // @[JtagShifter.scala 108:35]
    end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
      regs_14 <= regs_15; // @[JtagShifter.scala 112:37]
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
      regs_15 <= 1'h0; // @[JtagShifter.scala 108:35]
    end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
      regs_15 <= regs_16; // @[JtagShifter.scala 112:37]
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
      regs_16 <= 1'h0; // @[JtagShifter.scala 108:35]
    end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
      regs_16 <= regs_17; // @[JtagShifter.scala 112:37]
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
      regs_17 <= 1'h0; // @[JtagShifter.scala 108:35]
    end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
      regs_17 <= regs_18; // @[JtagShifter.scala 112:37]
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
      regs_18 <= 1'h0; // @[JtagShifter.scala 108:35]
    end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
      regs_18 <= regs_19; // @[JtagShifter.scala 112:37]
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
      regs_19 <= 1'h0; // @[JtagShifter.scala 108:35]
    end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
      regs_19 <= regs_20; // @[JtagShifter.scala 112:37]
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
      regs_20 <= 1'h0; // @[JtagShifter.scala 108:35]
    end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
      regs_20 <= regs_21; // @[JtagShifter.scala 112:37]
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
      regs_21 <= 1'h0; // @[JtagShifter.scala 108:35]
    end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
      regs_21 <= regs_22; // @[JtagShifter.scala 112:37]
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
      regs_22 <= 1'h0; // @[JtagShifter.scala 108:35]
    end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
      regs_22 <= regs_23; // @[JtagShifter.scala 112:37]
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
      regs_23 <= 1'h0; // @[JtagShifter.scala 108:35]
    end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
      regs_23 <= regs_24; // @[JtagShifter.scala 112:37]
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
      regs_24 <= 1'h0; // @[JtagShifter.scala 108:35]
    end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
      regs_24 <= regs_25; // @[JtagShifter.scala 112:37]
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
      regs_25 <= 1'h0; // @[JtagShifter.scala 108:35]
    end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
      regs_25 <= regs_26; // @[JtagShifter.scala 112:37]
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
      regs_26 <= 1'h0; // @[JtagShifter.scala 108:35]
    end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
      regs_26 <= regs_27; // @[JtagShifter.scala 112:37]
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
      regs_27 <= 1'h0; // @[JtagShifter.scala 108:35]
    end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
      regs_27 <= regs_28; // @[JtagShifter.scala 112:37]
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
      regs_28 <= 1'h0; // @[JtagShifter.scala 108:35]
    end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
      regs_28 <= regs_29; // @[JtagShifter.scala 112:37]
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
      regs_29 <= 1'h0; // @[JtagShifter.scala 108:35]
    end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
      regs_29 <= regs_30; // @[JtagShifter.scala 112:37]
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
      regs_30 <= 1'h0; // @[JtagShifter.scala 108:35]
    end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
      regs_30 <= regs_31; // @[JtagShifter.scala 112:37]
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 107:29]
      regs_31 <= 1'h0; // @[JtagShifter.scala 108:35]
    end else if (io_chainIn_shift) begin // @[JtagShifter.scala 110:34]
      regs_31 <= io_chainIn_data; // @[JtagShifter.scala 111:15]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_7 & ~reset) begin
          $fatal; // @[JtagShifter.scala 117:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_7) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at JtagShifter.scala:117 assert(!(io.chainIn.capture && io.chainIn.update)\n"); // @[JtagShifter.scala 117:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  regs_0 = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  regs_1 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  regs_2 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  regs_3 = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  regs_4 = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  regs_5 = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  regs_6 = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  regs_7 = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  regs_8 = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  regs_9 = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  regs_10 = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  regs_11 = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  regs_12 = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  regs_13 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  regs_14 = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  regs_15 = _RAND_15[0:0];
  _RAND_16 = {1{`RANDOM}};
  regs_16 = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  regs_17 = _RAND_17[0:0];
  _RAND_18 = {1{`RANDOM}};
  regs_18 = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  regs_19 = _RAND_19[0:0];
  _RAND_20 = {1{`RANDOM}};
  regs_20 = _RAND_20[0:0];
  _RAND_21 = {1{`RANDOM}};
  regs_21 = _RAND_21[0:0];
  _RAND_22 = {1{`RANDOM}};
  regs_22 = _RAND_22[0:0];
  _RAND_23 = {1{`RANDOM}};
  regs_23 = _RAND_23[0:0];
  _RAND_24 = {1{`RANDOM}};
  regs_24 = _RAND_24[0:0];
  _RAND_25 = {1{`RANDOM}};
  regs_25 = _RAND_25[0:0];
  _RAND_26 = {1{`RANDOM}};
  regs_26 = _RAND_26[0:0];
  _RAND_27 = {1{`RANDOM}};
  regs_27 = _RAND_27[0:0];
  _RAND_28 = {1{`RANDOM}};
  regs_28 = _RAND_28[0:0];
  _RAND_29 = {1{`RANDOM}};
  regs_29 = _RAND_29[0:0];
  _RAND_30 = {1{`RANDOM}};
  regs_30 = _RAND_30[0:0];
  _RAND_31 = {1{`RANDOM}};
  regs_31 = _RAND_31[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module JtagStateMachine(
  input        clock,
  input        reset,
  input        io_tms,
  output [3:0] io_currState
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg [3:0] currState; // @[JtagStateMachine.scala 78:26]
  wire [3:0] _nextState_T_1 = io_tms ? 4'h7 : 4'hc; // @[JtagStateMachine.scala 85:23]
  wire [3:0] _nextState_T_3 = io_tms ? 4'h1 : 4'h2; // @[JtagStateMachine.scala 91:23]
  wire [3:0] _nextState_T_5 = io_tms ? 4'h5 : 4'h3; // @[JtagStateMachine.scala 97:23]
  wire [3:0] _nextState_T_6 = io_tms ? 4'h0 : 4'h3; // @[JtagStateMachine.scala 100:23]
  wire [3:0] _nextState_T_7 = io_tms ? 4'h5 : 4'h2; // @[JtagStateMachine.scala 103:23]
  wire [3:0] _nextState_T_9 = io_tms ? 4'hf : 4'he; // @[JtagStateMachine.scala 109:23]
  wire [3:0] _nextState_T_10 = io_tms ? 4'h9 : 4'ha; // @[JtagStateMachine.scala 112:23]
  wire [3:0] _nextState_T_12 = io_tms ? 4'hd : 4'hb; // @[JtagStateMachine.scala 118:23]
  wire [3:0] _nextState_T_13 = io_tms ? 4'h8 : 4'hb; // @[JtagStateMachine.scala 121:23]
  wire [3:0] _nextState_T_14 = io_tms ? 4'hd : 4'ha; // @[JtagStateMachine.scala 124:23]
  wire [3:0] _GEN_0 = 4'hd == currState ? _nextState_T_1 : 4'hf; // @[JtagStateMachine.scala 127:17 80:22]
  wire [3:0] _GEN_1 = 4'h8 == currState ? _nextState_T_14 : _GEN_0; // @[JtagStateMachine.scala 124:17 80:22]
  wire [3:0] _GEN_2 = 4'hb == currState ? _nextState_T_13 : _GEN_1; // @[JtagStateMachine.scala 121:17 80:22]
  wire [3:0] _GEN_3 = 4'h9 == currState ? _nextState_T_12 : _GEN_2; // @[JtagStateMachine.scala 118:17 80:22]
  wire [3:0] _GEN_4 = 4'ha == currState ? _nextState_T_10 : _GEN_3; // @[JtagStateMachine.scala 115:17 80:22]
  wire [3:0] _GEN_5 = 4'he == currState ? _nextState_T_10 : _GEN_4; // @[JtagStateMachine.scala 112:17 80:22]
  wire [3:0] _GEN_6 = 4'h4 == currState ? _nextState_T_9 : _GEN_5; // @[JtagStateMachine.scala 109:17 80:22]
  wire [3:0] _GEN_7 = 4'h5 == currState ? _nextState_T_1 : _GEN_6; // @[JtagStateMachine.scala 106:17 80:22]
  wire [3:0] _GEN_8 = 4'h0 == currState ? _nextState_T_7 : _GEN_7; // @[JtagStateMachine.scala 103:17 80:22]
  wire [3:0] _GEN_9 = 4'h3 == currState ? _nextState_T_6 : _GEN_8; // @[JtagStateMachine.scala 100:17 80:22]
  wire [3:0] _GEN_10 = 4'h1 == currState ? _nextState_T_5 : _GEN_9; // @[JtagStateMachine.scala 80:22 97:17]
  wire [3:0] _GEN_11 = 4'h2 == currState ? _nextState_T_3 : _GEN_10; // @[JtagStateMachine.scala 80:22 94:17]
  assign io_currState = currState; // @[JtagStateMachine.scala 131:16]
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[JtagStateMachine.scala 80:22]
      currState <= 4'hf; // @[JtagStateMachine.scala 82:23]
    end else if (4'hf == currState) begin // @[JtagStateMachine.scala 80:22]
      if (io_tms) begin // @[JtagStateMachine.scala 85:23]
        currState <= 4'hf;
      end else begin
        currState <= 4'hc;
      end
    end else if (4'hc == currState) begin // @[JtagStateMachine.scala 80:22]
      if (io_tms) begin // @[JtagStateMachine.scala 88:23]
        currState <= 4'h7;
      end else begin
        currState <= 4'hc;
      end
    end else if (4'h7 == currState) begin // @[JtagStateMachine.scala 80:22]
      if (io_tms) begin // @[JtagStateMachine.scala 91:17]
        currState <= 4'h4;
      end else begin
        currState <= 4'h6;
      end
    end else if (4'h6 == currState) begin
      currState <= _nextState_T_3;
    end else begin
      currState <= _GEN_11;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  currState = _RAND_0[3:0];
`endif // RANDOMIZE_REG_INIT
  if (reset) begin
    currState = 4'hf;
  end
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module CaptureUpdateChain_2(
  input        clock,
  input        reset,
  input        io_chainIn_shift,
  input        io_chainIn_data,
  input        io_chainIn_capture,
  input        io_chainIn_update,
  output       io_chainOut_data,
  output [4:0] io_update_bits
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
  reg  regs_0; // @[JtagShifter.scala 154:39]
  reg  regs_1; // @[JtagShifter.scala 154:39]
  reg  regs_2; // @[JtagShifter.scala 154:39]
  reg  regs_3; // @[JtagShifter.scala 154:39]
  reg  regs_4; // @[JtagShifter.scala 154:39]
  wire [1:0] updateBits_lo = {regs_1,regs_0}; // @[Cat.scala 31:58]
  wire [2:0] updateBits_hi = {regs_4,regs_3,regs_2}; // @[Cat.scala 31:58]
  wire  _GEN_1 = io_chainIn_shift ? regs_1 : regs_0; // @[JtagShifter.scala 174:34 176:37 154:39]
  wire  _GEN_9 = io_chainIn_update ? regs_0 : _GEN_1; // @[JtagShifter.scala 171:35 154:39]
  wire  _T_1 = ~(io_chainIn_capture & io_chainIn_update); // @[JtagShifter.scala 183:10]
  wire  _T_4 = _T_1 & ~(io_chainIn_capture & io_chainIn_shift); // @[JtagShifter.scala 184:7]
  wire  _T_7 = _T_4 & ~(io_chainIn_update & io_chainIn_shift); // @[JtagShifter.scala 185:7]
  assign io_chainOut_data = regs_0; // @[JtagShifter.scala 156:20]
  assign io_update_bits = {updateBits_hi,updateBits_lo}; // @[Cat.scala 31:58]
  always @(posedge clock) begin
    regs_0 <= io_chainIn_capture | _GEN_9; // @[JtagShifter.scala 166:29 167:59]
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_1 <= 1'h0; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_1 <= regs_2; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_2 <= 1'h0; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_2 <= regs_3; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_3 <= 1'h0; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_3 <= regs_4; // @[JtagShifter.scala 176:37]
      end
    end
    if (io_chainIn_capture) begin // @[JtagShifter.scala 166:29]
      regs_4 <= 1'h0; // @[JtagShifter.scala 167:59]
    end else if (!(io_chainIn_update)) begin // @[JtagShifter.scala 171:35]
      if (io_chainIn_shift) begin // @[JtagShifter.scala 174:34]
        regs_4 <= io_chainIn_data; // @[JtagShifter.scala 175:15]
      end
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_7 & ~reset) begin
          $fatal; // @[JtagShifter.scala 183:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_7) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at JtagShifter.scala:183 assert(!(io.chainIn.capture && io.chainIn.update)\n"); // @[JtagShifter.scala 183:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  regs_0 = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  regs_1 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  regs_2 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  regs_3 = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  regs_4 = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module JtagTapController(
  input        clock,
  input        reset,
  input        io_jtag_TMS,
  input        io_jtag_TDI,
  output       io_jtag_TDO_data,
  output       io_jtag_TDO_driven,
  input        io_control_jtag_reset,
  output [4:0] io_output_instruction,
  output       io_output_tapIsInTestLogicReset,
  output       io_dataChainOut_shift,
  output       io_dataChainOut_data,
  output       io_dataChainOut_capture,
  output       io_dataChainOut_update,
  input        io_dataChainIn_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
  wire  stateMachine_clock; // @[JtagTap.scala 82:30]
  wire  stateMachine_reset; // @[JtagTap.scala 82:30]
  wire  stateMachine_io_tms; // @[JtagTap.scala 82:30]
  wire [3:0] stateMachine_io_currState; // @[JtagTap.scala 82:30]
  wire  irChain_clock; // @[JtagTap.scala 102:23]
  wire  irChain_reset; // @[JtagTap.scala 102:23]
  wire  irChain_io_chainIn_shift; // @[JtagTap.scala 102:23]
  wire  irChain_io_chainIn_data; // @[JtagTap.scala 102:23]
  wire  irChain_io_chainIn_capture; // @[JtagTap.scala 102:23]
  wire  irChain_io_chainIn_update; // @[JtagTap.scala 102:23]
  wire  irChain_io_chainOut_data; // @[JtagTap.scala 102:23]
  wire [4:0] irChain_io_update_bits; // @[JtagTap.scala 102:23]
  wire  clock_falling = ~clock; // @[JtagTap.scala 67:48]
  reg  tdoReg; // @[JtagTap.scala 89:30]
  reg  tdoeReg; // @[JtagTap.scala 90:30]
  wire [3:0] currState = stateMachine_io_currState; // @[JtagTap.scala 75:23 85:15]
  wire  _irChain_io_chainIn_shift_T = currState == 4'ha; // @[JtagTap.scala 104:41]
  wire  _irChain_io_chainIn_update_T = currState == 4'hd; // @[JtagTap.scala 107:42]
  reg [4:0] activeInstruction; // @[JtagTap.scala 111:36]
  wire  tapIsInTestLogicReset = currState == 4'hf; // @[JtagTap.scala 120:38]
  wire  _io_dataChainOut_shift_T = currState == 4'h2; // @[JtagTap.scala 126:38]
  wire  _GEN_2 = irChain_io_chainOut_data; // @[JtagTap.scala 137:51 138:9]
  JtagStateMachine stateMachine ( // @[JtagTap.scala 82:30]
    .clock(stateMachine_clock),
    .reset(stateMachine_reset),
    .io_tms(stateMachine_io_tms),
    .io_currState(stateMachine_io_currState)
  );
  CaptureUpdateChain_2 irChain ( // @[JtagTap.scala 102:23]
    .clock(irChain_clock),
    .reset(irChain_reset),
    .io_chainIn_shift(irChain_io_chainIn_shift),
    .io_chainIn_data(irChain_io_chainIn_data),
    .io_chainIn_capture(irChain_io_chainIn_capture),
    .io_chainIn_update(irChain_io_chainIn_update),
    .io_chainOut_data(irChain_io_chainOut_data),
    .io_update_bits(irChain_io_update_bits)
  );
  assign io_jtag_TDO_data = tdoReg; // @[JtagTap.scala 91:26]
  assign io_jtag_TDO_driven = tdoeReg; // @[JtagTap.scala 92:26]
  assign io_output_instruction = activeInstruction; // @[JtagTap.scala 117:27]
  assign io_output_tapIsInTestLogicReset = currState == 4'hf; // @[JtagTap.scala 120:38]
  assign io_dataChainOut_shift = currState == 4'h2; // @[JtagTap.scala 126:38]
  assign io_dataChainOut_data = io_jtag_TDI; // @[JtagTap.scala 127:24]
  assign io_dataChainOut_capture = currState == 4'h6; // @[JtagTap.scala 128:40]
  assign io_dataChainOut_update = currState == 4'h5; // @[JtagTap.scala 129:39]
  assign stateMachine_clock = clock;
  assign stateMachine_reset = io_control_jtag_reset;
  assign stateMachine_io_tms = io_jtag_TMS; // @[JtagTap.scala 84:25]
  assign irChain_clock = clock;
  assign irChain_reset = reset;
  assign irChain_io_chainIn_shift = currState == 4'ha; // @[JtagTap.scala 104:41]
  assign irChain_io_chainIn_data = io_jtag_TDI; // @[JtagTap.scala 105:27]
  assign irChain_io_chainIn_capture = currState == 4'he; // @[JtagTap.scala 106:43]
  assign irChain_io_chainIn_update = currState == 4'hd; // @[JtagTap.scala 107:42]
  always @(posedge clock_falling or posedge io_control_jtag_reset) begin
    if (io_control_jtag_reset) begin // @[JtagTap.scala 134:44]
      tdoReg <= 1'h0; // @[JtagTap.scala 135:9]
    end else if (_io_dataChainOut_shift_T) begin
      tdoReg <= io_dataChainIn_data;
    end else begin
      tdoReg <= _GEN_2;
    end
  end
  always @(posedge clock_falling or posedge io_control_jtag_reset) begin
    if (io_control_jtag_reset) begin // @[JtagTap.scala 134:44]
      tdoeReg <= 1'h0; // @[JtagTap.scala 136:16]
    end else begin
      tdoeReg <= _io_dataChainOut_shift_T | _irChain_io_chainIn_shift_T;
    end
  end
  always @(posedge clock_falling or posedge io_control_jtag_reset) begin
    if (io_control_jtag_reset) begin // @[JtagTap.scala 112:34]
      activeInstruction <= 5'h1; // @[JtagTap.scala 113:25]
    end else if (tapIsInTestLogicReset) begin // @[JtagTap.scala 114:53]
      activeInstruction <= 5'h1; // @[JtagTap.scala 115:25]
    end else if (_irChain_io_chainIn_update_T) begin // @[JtagTap.scala 111:36]
      activeInstruction <= irChain_io_update_bits;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  tdoReg = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  tdoeReg = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  activeInstruction = _RAND_2[4:0];
`endif // RANDOMIZE_REG_INIT
  if (io_control_jtag_reset) begin
    tdoReg = 1'h0;
  end
  if (io_control_jtag_reset) begin
    tdoeReg = 1'h0;
  end
  if (io_control_jtag_reset) begin
    activeInstruction = 5'h1;
  end
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module JtagBypassChain(
  input   clock,
  input   reset,
  input   io_chainIn_shift,
  input   io_chainIn_data,
  input   io_chainIn_capture,
  input   io_chainIn_update,
  output  io_chainOut_data
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg  reg_; // @[JtagShifter.scala 61:16]
  wire  _T_1 = ~(io_chainIn_capture & io_chainIn_update); // @[JtagShifter.scala 72:10]
  wire  _T_4 = _T_1 & ~(io_chainIn_capture & io_chainIn_shift); // @[JtagShifter.scala 73:7]
  wire  _T_7 = _T_4 & ~(io_chainIn_update & io_chainIn_shift); // @[JtagShifter.scala 74:7]
  assign io_chainOut_data = reg_; // @[JtagShifter.scala 63:20]
  always @(posedge clock) begin
    if (io_chainIn_capture) begin // @[JtagShifter.scala 67:29]
      reg_ <= 1'h0; // @[JtagShifter.scala 68:9]
    end else if (io_chainIn_shift) begin // @[JtagShifter.scala 69:34]
      reg_ <= io_chainIn_data; // @[JtagShifter.scala 70:9]
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~_T_7 & ~reset) begin
          $fatal; // @[JtagShifter.scala 72:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~reset & ~_T_7) begin
          $fwrite(32'h80000002,
            "Assertion failed\n    at JtagShifter.scala:72 assert(!(io.chainIn.capture && io.chainIn.update)\n"); // @[JtagShifter.scala 72:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  reg_ = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module DebugTransportModuleJTAG(
  input         io_jtag_clock,
  input         io_jtag_reset,
  input         io_dmi_req_ready,
  output        io_dmi_req_valid,
  output [6:0]  io_dmi_req_bits_addr,
  output [31:0] io_dmi_req_bits_data,
  output [1:0]  io_dmi_req_bits_op,
  output        io_dmi_resp_ready,
  input         io_dmi_resp_valid,
  input  [31:0] io_dmi_resp_bits_data,
  input  [1:0]  io_dmi_resp_bits_resp,
  input         io_jtag_TMS,
  input         io_jtag_TDI,
  output        io_jtag_TDO_data,
  output        io_jtag_TDO_driven
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
`endif // RANDOMIZE_REG_INIT
  wire  dtmInfoChain_clock; // @[DebugTransport.scala 128:29]
  wire  dtmInfoChain_reset; // @[DebugTransport.scala 128:29]
  wire  dtmInfoChain_io_chainIn_shift; // @[DebugTransport.scala 128:29]
  wire  dtmInfoChain_io_chainIn_data; // @[DebugTransport.scala 128:29]
  wire  dtmInfoChain_io_chainIn_capture; // @[DebugTransport.scala 128:29]
  wire  dtmInfoChain_io_chainIn_update; // @[DebugTransport.scala 128:29]
  wire  dtmInfoChain_io_chainOut_data; // @[DebugTransport.scala 128:29]
  wire [1:0] dtmInfoChain_io_capture_bits_dmiStatus; // @[DebugTransport.scala 128:29]
  wire  dtmInfoChain_io_update_valid; // @[DebugTransport.scala 128:29]
  wire  dtmInfoChain_io_update_bits_dmireset; // @[DebugTransport.scala 128:29]
  wire  dmiAccessChain_clock; // @[DebugTransport.scala 134:31]
  wire  dmiAccessChain_reset; // @[DebugTransport.scala 134:31]
  wire  dmiAccessChain_io_chainIn_shift; // @[DebugTransport.scala 134:31]
  wire  dmiAccessChain_io_chainIn_data; // @[DebugTransport.scala 134:31]
  wire  dmiAccessChain_io_chainIn_capture; // @[DebugTransport.scala 134:31]
  wire  dmiAccessChain_io_chainIn_update; // @[DebugTransport.scala 134:31]
  wire  dmiAccessChain_io_chainOut_data; // @[DebugTransport.scala 134:31]
  wire [6:0] dmiAccessChain_io_capture_bits_addr; // @[DebugTransport.scala 134:31]
  wire [31:0] dmiAccessChain_io_capture_bits_data; // @[DebugTransport.scala 134:31]
  wire [1:0] dmiAccessChain_io_capture_bits_resp; // @[DebugTransport.scala 134:31]
  wire  dmiAccessChain_io_capture_capture; // @[DebugTransport.scala 134:31]
  wire  dmiAccessChain_io_update_valid; // @[DebugTransport.scala 134:31]
  wire [6:0] dmiAccessChain_io_update_bits_addr; // @[DebugTransport.scala 134:31]
  wire [31:0] dmiAccessChain_io_update_bits_data; // @[DebugTransport.scala 134:31]
  wire [1:0] dmiAccessChain_io_update_bits_op; // @[DebugTransport.scala 134:31]
  wire  tapIO_idcodeChain_clock; // @[JtagTap.scala 181:33]
  wire  tapIO_idcodeChain_reset; // @[JtagTap.scala 181:33]
  wire  tapIO_idcodeChain_io_chainIn_shift; // @[JtagTap.scala 181:33]
  wire  tapIO_idcodeChain_io_chainIn_data; // @[JtagTap.scala 181:33]
  wire  tapIO_idcodeChain_io_chainIn_capture; // @[JtagTap.scala 181:33]
  wire  tapIO_idcodeChain_io_chainIn_update; // @[JtagTap.scala 181:33]
  wire  tapIO_idcodeChain_io_chainOut_data; // @[JtagTap.scala 181:33]
  wire  tapIO_controllerInternal_clock; // @[JtagTap.scala 199:36]
  wire  tapIO_controllerInternal_reset; // @[JtagTap.scala 199:36]
  wire  tapIO_controllerInternal_io_jtag_TMS; // @[JtagTap.scala 199:36]
  wire  tapIO_controllerInternal_io_jtag_TDI; // @[JtagTap.scala 199:36]
  wire  tapIO_controllerInternal_io_jtag_TDO_data; // @[JtagTap.scala 199:36]
  wire  tapIO_controllerInternal_io_jtag_TDO_driven; // @[JtagTap.scala 199:36]
  wire  tapIO_controllerInternal_io_control_jtag_reset; // @[JtagTap.scala 199:36]
  wire [4:0] tapIO_controllerInternal_io_output_instruction; // @[JtagTap.scala 199:36]
  wire  tapIO_controllerInternal_io_output_tapIsInTestLogicReset; // @[JtagTap.scala 199:36]
  wire  tapIO_controllerInternal_io_dataChainOut_shift; // @[JtagTap.scala 199:36]
  wire  tapIO_controllerInternal_io_dataChainOut_data; // @[JtagTap.scala 199:36]
  wire  tapIO_controllerInternal_io_dataChainOut_capture; // @[JtagTap.scala 199:36]
  wire  tapIO_controllerInternal_io_dataChainOut_update; // @[JtagTap.scala 199:36]
  wire  tapIO_controllerInternal_io_dataChainIn_data; // @[JtagTap.scala 199:36]
  wire  tapIO_bypassChain_clock; // @[JtagTap.scala 207:29]
  wire  tapIO_bypassChain_reset; // @[JtagTap.scala 207:29]
  wire  tapIO_bypassChain_io_chainIn_shift; // @[JtagTap.scala 207:29]
  wire  tapIO_bypassChain_io_chainIn_data; // @[JtagTap.scala 207:29]
  wire  tapIO_bypassChain_io_chainIn_capture; // @[JtagTap.scala 207:29]
  wire  tapIO_bypassChain_io_chainIn_update; // @[JtagTap.scala 207:29]
  wire  tapIO_bypassChain_io_chainOut_data; // @[JtagTap.scala 207:29]
  reg  busyReg; // @[DebugTransport.scala 96:24]
  reg  stickyBusyReg; // @[DebugTransport.scala 97:30]
  reg  stickyNonzeroRespReg; // @[DebugTransport.scala 98:37]
  reg  downgradeOpReg; // @[DebugTransport.scala 100:31]
  reg [6:0] dmiReqReg_addr; // @[DebugTransport.scala 110:23]
  reg [31:0] dmiReqReg_data; // @[DebugTransport.scala 110:23]
  reg [1:0] dmiReqReg_op; // @[DebugTransport.scala 110:23]
  reg  dmiReqValidReg; // @[DebugTransport.scala 111:31]
  wire  _dmiStatus_T = stickyNonzeroRespReg | stickyBusyReg; // @[DebugTransport.scala 118:63]
  wire  _GEN_0 = io_dmi_req_valid | busyReg; // @[DebugTransport.scala 143:27 144:13 96:24]
  wire  _T_1 = io_dmi_resp_ready & io_dmi_resp_valid; // @[Decoupled.scala 50:35]
  wire  busy = busyReg & ~io_dmi_resp_valid | stickyBusyReg; // @[DebugTransport.scala 155:42]
  wire  _downgradeOpReg_T = ~busy; // @[DebugTransport.scala 164:24]
  wire  nonzeroResp = stickyNonzeroRespReg | io_dmi_resp_valid & io_dmi_resp_bits_resp != 2'h0; // @[DebugTransport.scala 178:39]
  wire  _GEN_4 = dmiAccessChain_io_capture_capture ? busy : stickyBusyReg; // @[DebugTransport.scala 163:44 165:19 97:30]
  wire  _GEN_5 = dmiAccessChain_io_capture_capture ? nonzeroResp : stickyNonzeroRespReg; // @[DebugTransport.scala 163:44 166:26 98:37]
  wire [6:0] _dmiAccessChain_io_capture_bits_T_addr = io_dmi_resp_valid ? dmiReqReg_addr : 7'h0; // @[DebugTransport.scala 197:60]
  wire [31:0] _dmiAccessChain_io_capture_bits_T_data = io_dmi_resp_valid ? io_dmi_resp_bits_data : 32'h0; // @[DebugTransport.scala 197:60]
  wire [1:0] _dmiAccessChain_io_capture_bits_T_resp = io_dmi_resp_valid ? io_dmi_resp_bits_resp : 2'h0; // @[DebugTransport.scala 197:60]
  wire  _T_4 = io_dmi_req_ready & io_dmi_req_valid; // @[Decoupled.scala 50:35]
  wire  _GEN_14 = downgradeOpReg | dmiAccessChain_io_update_bits_op == 2'h0 ? 1'h0 : 1'h1; // @[DebugTransport.scala 208:97 216:24]
  wire  _GEN_19 = stickyBusyReg ? 1'h0 : _GEN_14; // @[DebugTransport.scala 206:26]
  wire  dmiReqValidCheck = dmiAccessChain_io_update_valid & _GEN_19; // @[DebugTransport.scala 205:41]
  wire  _T_8 = ~io_jtag_reset; // @[DebugTransport.scala 203:9]
  wire  _GEN_13 = downgradeOpReg | dmiAccessChain_io_update_bits_op == 2'h0 ? dmiReqValidReg : 1'h1; // @[DebugTransport.scala 111:31 208:97 215:22]
  wire  _io_dmi_resp_ready_T = dmiReqReg_op == 2'h2; // @[DebugTransport.scala 225:18]
  wire  _io_dmi_resp_ready_T_2 = dmiAccessChain_io_capture_capture & _downgradeOpReg_T; // @[DebugTransport.scala 229:41]
  wire [31:0] _GEN_1 = 32'h913 % 32'h2; // @[JtagTap.scala 184:18]
  wire [1:0] _tapIO_T = _GEN_1[1:0]; // @[JtagTap.scala 184:18]
  wire [11:0] _tapIO_T_8 = 12'h800 - 12'h1; // @[JtagTap.scala 185:41]
  wire [30:0] _GEN_59 = {{19'd0}, _tapIO_T_8}; // @[JtagTap.scala 185:26]
  wire [30:0] _tapIO_T_9 = 31'h489 & _GEN_59; // @[JtagTap.scala 185:26]
  wire  tapIO_icodeSelects_0 = tapIO_controllerInternal_io_output_instruction == 5'h1; // @[JtagTap.scala 223:82]
  wire  tapIO_icodeSelects_0_1 = tapIO_controllerInternal_io_output_instruction == 5'h10; // @[JtagTap.scala 223:82]
  wire  tapIO_icodeSelects_0_2 = tapIO_controllerInternal_io_output_instruction == 5'h11; // @[JtagTap.scala 223:82]
  wire  _GEN_28 = tapIO_icodeSelects_0_2 ? dmiAccessChain_io_chainOut_data : tapIO_bypassChain_io_chainOut_data; // @[JtagTap.scala 233:28 234:43 240:41]
  wire  _GEN_32 = tapIO_icodeSelects_0_1 ? dtmInfoChain_io_chainOut_data : _GEN_28; // @[JtagTap.scala 233:28 234:43]
  wire  tapIO_output_tapIsInTestLogicReset = tapIO_controllerInternal_io_output_tapIsInTestLogicReset; // @[JtagTap.scala 174:26 256:23]
  CaptureUpdateChain dtmInfoChain ( // @[DebugTransport.scala 128:29]
    .clock(dtmInfoChain_clock),
    .reset(dtmInfoChain_reset),
    .io_chainIn_shift(dtmInfoChain_io_chainIn_shift),
    .io_chainIn_data(dtmInfoChain_io_chainIn_data),
    .io_chainIn_capture(dtmInfoChain_io_chainIn_capture),
    .io_chainIn_update(dtmInfoChain_io_chainIn_update),
    .io_chainOut_data(dtmInfoChain_io_chainOut_data),
    .io_capture_bits_dmiStatus(dtmInfoChain_io_capture_bits_dmiStatus),
    .io_update_valid(dtmInfoChain_io_update_valid),
    .io_update_bits_dmireset(dtmInfoChain_io_update_bits_dmireset)
  );
  CaptureUpdateChain_1 dmiAccessChain ( // @[DebugTransport.scala 134:31]
    .clock(dmiAccessChain_clock),
    .reset(dmiAccessChain_reset),
    .io_chainIn_shift(dmiAccessChain_io_chainIn_shift),
    .io_chainIn_data(dmiAccessChain_io_chainIn_data),
    .io_chainIn_capture(dmiAccessChain_io_chainIn_capture),
    .io_chainIn_update(dmiAccessChain_io_chainIn_update),
    .io_chainOut_data(dmiAccessChain_io_chainOut_data),
    .io_capture_bits_addr(dmiAccessChain_io_capture_bits_addr),
    .io_capture_bits_data(dmiAccessChain_io_capture_bits_data),
    .io_capture_bits_resp(dmiAccessChain_io_capture_bits_resp),
    .io_capture_capture(dmiAccessChain_io_capture_capture),
    .io_update_valid(dmiAccessChain_io_update_valid),
    .io_update_bits_addr(dmiAccessChain_io_update_bits_addr),
    .io_update_bits_data(dmiAccessChain_io_update_bits_data),
    .io_update_bits_op(dmiAccessChain_io_update_bits_op)
  );
  CaptureChain tapIO_idcodeChain ( // @[JtagTap.scala 181:33]
    .clock(tapIO_idcodeChain_clock),
    .reset(tapIO_idcodeChain_reset),
    .io_chainIn_shift(tapIO_idcodeChain_io_chainIn_shift),
    .io_chainIn_data(tapIO_idcodeChain_io_chainIn_data),
    .io_chainIn_capture(tapIO_idcodeChain_io_chainIn_capture),
    .io_chainIn_update(tapIO_idcodeChain_io_chainIn_update),
    .io_chainOut_data(tapIO_idcodeChain_io_chainOut_data)
  );
  JtagTapController tapIO_controllerInternal ( // @[JtagTap.scala 199:36]
    .clock(tapIO_controllerInternal_clock),
    .reset(tapIO_controllerInternal_reset),
    .io_jtag_TMS(tapIO_controllerInternal_io_jtag_TMS),
    .io_jtag_TDI(tapIO_controllerInternal_io_jtag_TDI),
    .io_jtag_TDO_data(tapIO_controllerInternal_io_jtag_TDO_data),
    .io_jtag_TDO_driven(tapIO_controllerInternal_io_jtag_TDO_driven),
    .io_control_jtag_reset(tapIO_controllerInternal_io_control_jtag_reset),
    .io_output_instruction(tapIO_controllerInternal_io_output_instruction),
    .io_output_tapIsInTestLogicReset(tapIO_controllerInternal_io_output_tapIsInTestLogicReset),
    .io_dataChainOut_shift(tapIO_controllerInternal_io_dataChainOut_shift),
    .io_dataChainOut_data(tapIO_controllerInternal_io_dataChainOut_data),
    .io_dataChainOut_capture(tapIO_controllerInternal_io_dataChainOut_capture),
    .io_dataChainOut_update(tapIO_controllerInternal_io_dataChainOut_update),
    .io_dataChainIn_data(tapIO_controllerInternal_io_dataChainIn_data)
  );
  JtagBypassChain tapIO_bypassChain ( // @[JtagTap.scala 207:29]
    .clock(tapIO_bypassChain_clock),
    .reset(tapIO_bypassChain_reset),
    .io_chainIn_shift(tapIO_bypassChain_io_chainIn_shift),
    .io_chainIn_data(tapIO_bypassChain_io_chainIn_data),
    .io_chainIn_capture(tapIO_bypassChain_io_chainIn_capture),
    .io_chainIn_update(tapIO_bypassChain_io_chainIn_update),
    .io_chainOut_data(tapIO_bypassChain_io_chainOut_data)
  );
  assign io_dmi_req_valid = dmiReqValidReg; // @[DebugTransport.scala 241:20]
  assign io_dmi_req_bits_addr = dmiReqReg_addr; // @[DebugTransport.scala 244:19]
  assign io_dmi_req_bits_data = dmiReqReg_data; // @[DebugTransport.scala 244:19]
  assign io_dmi_req_bits_op = dmiReqReg_op; // @[DebugTransport.scala 244:19]
  assign io_dmi_resp_ready = _io_dmi_resp_ready_T ? io_dmi_resp_valid : _io_dmi_resp_ready_T_2; // @[DebugTransport.scala 224:27]
  assign io_jtag_TDO_data = tapIO_controllerInternal_io_jtag_TDO_data; // @[JtagTap.scala 174:26 254:21]
  assign io_jtag_TDO_driven = tapIO_controllerInternal_io_jtag_TDO_driven; // @[JtagTap.scala 174:26 254:21]
  assign dtmInfoChain_clock = io_jtag_clock;
  assign dtmInfoChain_reset = io_jtag_reset; // @[DebugTransport.scala 89:50]
  assign dtmInfoChain_io_chainIn_shift = tapIO_icodeSelects_0_1 & tapIO_controllerInternal_io_dataChainOut_shift; // @[JtagTap.scala 245:21 246:26 248:26]
  assign dtmInfoChain_io_chainIn_data = tapIO_icodeSelects_0_1 & tapIO_controllerInternal_io_dataChainOut_data; // @[JtagTap.scala 245:21 246:26 248:26]
  assign dtmInfoChain_io_chainIn_capture = tapIO_icodeSelects_0_1 & tapIO_controllerInternal_io_dataChainOut_capture; // @[JtagTap.scala 245:21 246:26 248:26]
  assign dtmInfoChain_io_chainIn_update = tapIO_icodeSelects_0_1 & tapIO_controllerInternal_io_dataChainOut_update; // @[JtagTap.scala 245:21 246:26 248:26]
  assign dtmInfoChain_io_capture_bits_dmiStatus = {stickyNonzeroRespReg,_dmiStatus_T}; // @[Cat.scala 31:58]
  assign dmiAccessChain_clock = io_jtag_clock;
  assign dmiAccessChain_reset = io_jtag_reset; // @[DebugTransport.scala 89:50]
  assign dmiAccessChain_io_chainIn_shift = tapIO_icodeSelects_0_2 & tapIO_controllerInternal_io_dataChainOut_shift; // @[JtagTap.scala 245:21 246:26 248:26]
  assign dmiAccessChain_io_chainIn_data = tapIO_icodeSelects_0_2 & tapIO_controllerInternal_io_dataChainOut_data; // @[JtagTap.scala 245:21 246:26 248:26]
  assign dmiAccessChain_io_chainIn_capture = tapIO_icodeSelects_0_2 & tapIO_controllerInternal_io_dataChainOut_capture; // @[JtagTap.scala 245:21 246:26 248:26]
  assign dmiAccessChain_io_chainIn_update = tapIO_icodeSelects_0_2 & tapIO_controllerInternal_io_dataChainOut_update; // @[JtagTap.scala 245:21 246:26 248:26]
  assign dmiAccessChain_io_capture_bits_addr = busy ? 7'h0 : _dmiAccessChain_io_capture_bits_T_addr; // @[DebugTransport.scala 197:40]
  assign dmiAccessChain_io_capture_bits_data = busy ? 32'h0 : _dmiAccessChain_io_capture_bits_T_data; // @[DebugTransport.scala 197:40]
  assign dmiAccessChain_io_capture_bits_resp = busy ? 2'h3 : _dmiAccessChain_io_capture_bits_T_resp; // @[DebugTransport.scala 197:40]
  assign tapIO_idcodeChain_clock = io_jtag_clock;
  assign tapIO_idcodeChain_reset = io_jtag_reset; // @[DebugTransport.scala 89:50]
  assign tapIO_idcodeChain_io_chainIn_shift = tapIO_icodeSelects_0 & tapIO_controllerInternal_io_dataChainOut_shift; // @[JtagTap.scala 245:21 246:26 248:26]
  assign tapIO_idcodeChain_io_chainIn_data = tapIO_icodeSelects_0 & tapIO_controllerInternal_io_dataChainOut_data; // @[JtagTap.scala 245:21 246:26 248:26]
  assign tapIO_idcodeChain_io_chainIn_capture = tapIO_icodeSelects_0 & tapIO_controllerInternal_io_dataChainOut_capture; // @[JtagTap.scala 245:21 246:26 248:26]
  assign tapIO_idcodeChain_io_chainIn_update = tapIO_icodeSelects_0 & tapIO_controllerInternal_io_dataChainOut_update; // @[JtagTap.scala 245:21 246:26 248:26]
  assign tapIO_controllerInternal_clock = io_jtag_clock;
  assign tapIO_controllerInternal_reset = io_jtag_reset; // @[DebugTransport.scala 89:50]
  assign tapIO_controllerInternal_io_jtag_TMS = io_jtag_TMS; // @[JtagTap.scala 174:26 DebugTransport.scala 262:14]
  assign tapIO_controllerInternal_io_jtag_TDI = io_jtag_TDI; // @[JtagTap.scala 174:26 DebugTransport.scala 262:14]
  assign tapIO_controllerInternal_io_control_jtag_reset = io_jtag_reset; // @[DebugTransport.scala 264:45]
  assign tapIO_controllerInternal_io_dataChainIn_data = tapIO_icodeSelects_0 ? tapIO_idcodeChain_io_chainOut_data :
    _GEN_32; // @[JtagTap.scala 233:28 234:43]
  assign tapIO_bypassChain_clock = io_jtag_clock;
  assign tapIO_bypassChain_reset = io_jtag_reset; // @[DebugTransport.scala 89:50]
  assign tapIO_bypassChain_io_chainIn_shift = tapIO_controllerInternal_io_dataChainOut_shift; // @[JtagTap.scala 210:28]
  assign tapIO_bypassChain_io_chainIn_data = tapIO_controllerInternal_io_dataChainOut_data; // @[JtagTap.scala 210:28]
  assign tapIO_bypassChain_io_chainIn_capture = tapIO_controllerInternal_io_dataChainOut_capture; // @[JtagTap.scala 210:28]
  assign tapIO_bypassChain_io_chainIn_update = tapIO_controllerInternal_io_dataChainOut_update; // @[JtagTap.scala 210:28]
  always @(posedge io_jtag_clock) begin
    if (dmiAccessChain_io_update_valid) begin // @[DebugTransport.scala 205:41]
      if (!(stickyBusyReg)) begin // @[DebugTransport.scala 206:26]
        if (downgradeOpReg | dmiAccessChain_io_update_bits_op == 2'h0) begin // @[DebugTransport.scala 208:97]
          dmiReqReg_addr <= 7'h0; // @[DebugTransport.scala 210:22]
        end else begin
          dmiReqReg_addr <= dmiAccessChain_io_update_bits_addr; // @[DebugTransport.scala 214:17]
        end
      end
    end
    if (dmiAccessChain_io_update_valid) begin // @[DebugTransport.scala 205:41]
      if (!(stickyBusyReg)) begin // @[DebugTransport.scala 206:26]
        if (downgradeOpReg | dmiAccessChain_io_update_bits_op == 2'h0) begin // @[DebugTransport.scala 208:97]
          dmiReqReg_data <= 32'h0; // @[DebugTransport.scala 211:22]
        end else begin
          dmiReqReg_data <= dmiAccessChain_io_update_bits_data; // @[DebugTransport.scala 214:17]
        end
      end
    end
    if (dmiAccessChain_io_update_valid) begin // @[DebugTransport.scala 205:41]
      if (!(stickyBusyReg)) begin // @[DebugTransport.scala 206:26]
        if (downgradeOpReg | dmiAccessChain_io_update_bits_op == 2'h0) begin // @[DebugTransport.scala 208:97]
          dmiReqReg_op <= 2'h0; // @[DebugTransport.scala 212:22]
        end else begin
          dmiReqReg_op <= dmiAccessChain_io_update_bits_op; // @[DebugTransport.scala 214:17]
        end
      end
    end
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(~(dmiReqValidCheck & _T_4)) & ~io_jtag_reset) begin
          $fatal; // @[DebugTransport.scala 203:9]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (~io_jtag_reset & ~(~(dmiReqValidCheck & _T_4))) begin
          $fwrite(32'h80000002,
            "Assertion failed: Conflicting updates for dmiReqValidReg, should not happen.\n    at DebugTransport.scala:203 assert(!(dmiReqValidCheck && io.dmi.req.fire()), \"Conflicting updates for dmiReqValidReg, should not happen.\");\n"
            ); // @[DebugTransport.scala 203:9]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_tapIO_T == 2'h1) & _T_8) begin
          $fatal; // @[JtagTap.scala 184:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_8 & ~(_tapIO_T == 2'h1)) begin
          $fwrite(32'h80000002,
            "Assertion failed: LSB must be set in IDCODE, see 12.1.1d\n    at JtagTap.scala:184 assert(i %% 2.U === 1.U, \"LSB must be set in IDCODE, see 12.1.1d\")\n"
            ); // @[JtagTap.scala 184:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef STOP_COND
      if (`STOP_COND) begin
    `endif
        if (~(_tapIO_T_9 != 31'h7f) & _T_8) begin
          $fatal; // @[JtagTap.scala 185:15]
        end
    `ifdef STOP_COND
      end
    `endif
    `endif // SYNTHESIS
    `ifndef SYNTHESIS
    `ifdef PRINTF_COND
      if (`PRINTF_COND) begin
    `endif
        if (_T_8 & ~(_tapIO_T_9 != 31'h7f)) begin
          $fwrite(32'h80000002,
            "Assertion failed: IDCODE must not have 0b00001111111 as manufacturer identity, see 12.2.1b\n    at JtagTap.scala:185 assert(((i >> 1) & ((1.U << 11) - 1.U)) =/= JtagIdcode.dummyMfrId.U,\n"
            ); // @[JtagTap.scala 185:15]
        end
    `ifdef PRINTF_COND
      end
    `endif
    `endif // SYNTHESIS
  end
  always @(posedge io_jtag_clock or posedge io_jtag_reset) begin
    if (io_jtag_reset) begin // @[DebugTransport.scala 269:45]
      busyReg <= 1'h0; // @[DebugTransport.scala 270:13]
    end else if (tapIO_output_tapIsInTestLogicReset) begin // @[DebugTransport.scala 146:29]
      busyReg <= 1'h0; // @[DebugTransport.scala 147:13]
    end else if (_T_1) begin
      busyReg <= 1'h0;
    end else begin
      busyReg <= _GEN_0;
    end
  end
  always @(posedge io_jtag_clock or posedge io_jtag_reset) begin
    if (io_jtag_reset) begin // @[DebugTransport.scala 269:45]
      stickyBusyReg <= 1'h0; // @[DebugTransport.scala 271:19]
    end else if (tapIO_output_tapIsInTestLogicReset) begin // @[DebugTransport.scala 168:39]
      stickyBusyReg <= 1'h0; // @[DebugTransport.scala 169:49 171:21]
    end else if (dtmInfoChain_io_update_valid) begin
      if (dtmInfoChain_io_update_bits_dmireset) begin
        stickyBusyReg <= 1'h0;
      end else begin
        stickyBusyReg <= _GEN_4;
      end
    end else begin
      stickyBusyReg <= _GEN_4;
    end
  end
  always @(posedge io_jtag_clock or posedge io_jtag_reset) begin
    if (io_jtag_reset) begin // @[DebugTransport.scala 269:45]
      stickyNonzeroRespReg <= 1'h0; // @[DebugTransport.scala 272:26]
    end else if (tapIO_output_tapIsInTestLogicReset) begin // @[DebugTransport.scala 168:39]
      stickyNonzeroRespReg <= 1'h0; // @[DebugTransport.scala 169:49 170:28]
    end else if (dtmInfoChain_io_update_valid) begin
      if (dtmInfoChain_io_update_bits_dmireset) begin
        stickyNonzeroRespReg <= 1'h0;
      end else begin
        stickyNonzeroRespReg <= _GEN_5;
      end
    end else begin
      stickyNonzeroRespReg <= _GEN_5;
    end
  end
  always @(posedge io_jtag_clock or posedge io_jtag_reset) begin
    if (io_jtag_reset) begin // @[DebugTransport.scala 269:45]
      downgradeOpReg <= 1'h0; // @[DebugTransport.scala 273:20]
    end else if (tapIO_output_tapIsInTestLogicReset) begin // @[DebugTransport.scala 163:44]
      downgradeOpReg <= 1'h0; // @[DebugTransport.scala 164:20]
    end else if (dmiAccessChain_io_capture_capture) begin // @[DebugTransport.scala 160:41]
      downgradeOpReg <= ~busy & nonzeroResp; // @[DebugTransport.scala 161:20]
    end else if (dmiAccessChain_io_update_valid) begin // @[DebugTransport.scala 100:31]
      downgradeOpReg <= 1'h0;
    end
  end
  always @(posedge io_jtag_clock or posedge io_jtag_reset) begin
    if (io_jtag_reset) begin // @[DebugTransport.scala 269:45]
      dmiReqValidReg <= 1'h0; // @[DebugTransport.scala 274:20]
    end else if (tapIO_output_tapIsInTestLogicReset) begin // @[DebugTransport.scala 220:28]
      dmiReqValidReg <= 1'h0; // @[DebugTransport.scala 221:20]
    end else if (_T_4) begin // @[DebugTransport.scala 205:41]
      dmiReqValidReg <= 1'h0; // @[DebugTransport.scala 206:26 111:31]
    end else if (dmiAccessChain_io_update_valid) begin // @[DebugTransport.scala 111:31]
      if (!(stickyBusyReg)) begin
        dmiReqValidReg <= _GEN_13;
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  busyReg = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  stickyBusyReg = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  stickyNonzeroRespReg = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  downgradeOpReg = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  dmiReqReg_addr = _RAND_4[6:0];
  _RAND_5 = {1{`RANDOM}};
  dmiReqReg_data = _RAND_5[31:0];
  _RAND_6 = {1{`RANDOM}};
  dmiReqReg_op = _RAND_6[1:0];
  _RAND_7 = {1{`RANDOM}};
  dmiReqValidReg = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
  if (io_jtag_reset) begin
    busyReg = 1'h0;
  end
  if (io_jtag_reset) begin
    stickyBusyReg = 1'h0;
  end
  if (io_jtag_reset) begin
    stickyNonzeroRespReg = 1'h0;
  end
  if (io_jtag_reset) begin
    downgradeOpReg = 1'h0;
  end
  if (io_jtag_reset) begin
    dmiReqValidReg = 1'h0;
  end
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module MarmotCaravelSystem(
  input   clock,
  input   reset,
  input   debug_clock,
  input   debug_systemjtag_jtag_TCK,
  input   debug_systemjtag_jtag_TMS,
  input   debug_systemjtag_jtag_TDI,
  output  debug_systemjtag_jtag_TDO_data,
  output  debug_systemjtag_jtag_TDO_driven,
  input   debug_systemjtag_reset,
  output  uart_0_txd,
  input   uart_0_rxd,
  output  uart_1_txd,
  input   uart_1_rxd,
  output  uart_2_txd,
  input   uart_2_rxd,
  output  uart_3_txd,
  input   uart_3_rxd,
  output  uart_4_txd,
  input   uart_4_rxd,
  output  spi_0_sck,
  input   spi_0_dq_0_i,
  output  spi_0_dq_0_o,
  output  spi_0_dq_0_oe,
  input   spi_0_dq_1_i,
  output  spi_0_dq_1_o,
  output  spi_0_dq_1_oe,
  input   spi_0_dq_2_i,
  output  spi_0_dq_2_o,
  output  spi_0_dq_2_oe,
  input   spi_0_dq_3_i,
  output  spi_0_dq_3_o,
  output  spi_0_dq_3_oe,
  output  spi_0_cs_0,
  output  spi_0_cs_1,
  input   gpio_0_pins_0_i_ival,
  output  gpio_0_pins_0_o_oval,
  output  gpio_0_pins_0_o_oe,
  output  gpio_0_pins_0_o_ie,
  input   gpio_0_pins_1_i_ival,
  output  gpio_0_pins_1_o_oval,
  output  gpio_0_pins_1_o_oe,
  output  gpio_0_pins_1_o_ie,
  input   gpio_0_pins_2_i_ival,
  output  gpio_0_pins_2_o_oval,
  output  gpio_0_pins_2_o_oe,
  output  gpio_0_pins_2_o_ie,
  input   gpio_0_pins_3_i_ival,
  output  gpio_0_pins_3_o_oval,
  output  gpio_0_pins_3_o_oe,
  output  gpio_0_pins_3_o_ie,
  input   gpio_0_pins_4_i_ival,
  output  gpio_0_pins_4_o_oval,
  output  gpio_0_pins_4_o_oe,
  output  gpio_0_pins_4_o_ie,
  input   gpio_0_pins_5_i_ival,
  output  gpio_0_pins_5_o_oval,
  output  gpio_0_pins_5_o_oe,
  output  gpio_0_pins_5_o_ie,
  input   gpio_0_pins_6_i_ival,
  output  gpio_0_pins_6_o_oval,
  output  gpio_0_pins_6_o_oe,
  input   gpio_0_pins_7_i_ival,
  output  gpio_0_pins_7_o_oval,
  output  gpio_0_pins_7_o_oe,
  input   gpio_0_pins_8_i_ival,
  output  gpio_0_pins_8_o_oval,
  output  gpio_0_pins_8_o_oe,
  input   gpio_0_pins_9_i_ival,
  output  gpio_0_pins_9_o_oval,
  output  gpio_0_pins_9_o_oe,
  input   gpio_0_pins_10_i_ival,
  output  gpio_0_pins_10_o_oval,
  output  gpio_0_pins_10_o_oe,
  input   gpio_0_pins_11_i_ival,
  output  gpio_0_pins_11_o_oval,
  output  gpio_0_pins_11_o_oe,
  input   gpio_0_pins_12_i_ival,
  output  gpio_0_pins_12_o_oval,
  output  gpio_0_pins_12_o_oe,
  output  gpio_0_pins_12_o_ie,
  input   gpio_0_pins_13_i_ival,
  output  gpio_0_pins_13_o_oval,
  output  gpio_0_pins_13_o_oe,
  output  gpio_0_pins_13_o_ie,
  input   gpio_0_pins_14_i_ival,
  output  gpio_0_pins_14_o_oval,
  output  gpio_0_pins_14_o_oe,
  output  gpio_0_pins_14_o_ie,
  input   gpio_0_pins_15_i_ival,
  output  gpio_0_pins_15_o_oval,
  output  gpio_0_pins_15_o_oe,
  output  gpio_0_pins_15_o_ie,
  input   gpio_0_pins_16_i_ival,
  output  gpio_0_pins_16_o_oval,
  output  gpio_0_pins_16_o_oe,
  output  gpio_0_pins_16_o_ie,
  input   gpio_0_pins_17_i_ival,
  output  gpio_0_pins_17_o_oval,
  output  gpio_0_pins_17_o_oe,
  output  gpio_0_pins_17_o_ie,
  input   gpio_0_pins_18_i_ival,
  output  gpio_0_pins_18_o_oval,
  output  gpio_0_pins_18_o_oe,
  output  gpio_0_pins_18_o_ie,
  input   gpio_0_pins_19_i_ival,
  output  gpio_0_pins_19_o_oval,
  output  gpio_0_pins_19_o_oe,
  output  gpio_0_pins_19_o_ie,
  input   gpio_0_pins_20_i_ival,
  output  gpio_0_pins_20_o_oval,
  output  gpio_0_pins_20_o_oe,
  output  gpio_0_pins_20_o_ie,
  input   gpio_0_pins_21_i_ival,
  output  gpio_0_pins_21_o_oval,
  output  gpio_0_pins_21_o_oe,
  output  gpio_0_pins_21_o_ie,
  input   gpio_0_pins_22_i_ival,
  output  gpio_0_pins_22_o_oval,
  output  gpio_0_pins_22_o_oe,
  output  gpio_0_pins_22_o_ie,
  input   gpio_0_pins_23_i_ival,
  output  gpio_0_pins_23_o_oval,
  output  gpio_0_pins_23_o_oe,
  output  gpio_0_pins_23_o_ie,
  input   gpio_0_pins_24_i_ival,
  output  gpio_0_pins_24_o_oval,
  output  gpio_0_pins_24_o_oe,
  output  gpio_0_pins_24_o_ie,
  input   gpio_0_pins_25_i_ival,
  output  gpio_0_pins_25_o_oval,
  output  gpio_0_pins_25_o_oe,
  input   gpio_0_pins_26_i_ival,
  output  gpio_0_pins_26_o_oval,
  output  gpio_0_pins_26_o_oe,
  input   gpio_0_pins_27_i_ival,
  output  gpio_0_pins_27_o_oval,
  output  gpio_0_pins_27_o_oe,
  input   gpio_0_pins_28_i_ival,
  output  gpio_0_pins_28_o_oval,
  output  gpio_0_pins_28_o_oe,
  input   gpio_0_pins_29_i_ival,
  output  gpio_0_pins_29_o_oval,
  output  gpio_0_pins_29_o_oe,
  input   gpio_0_pins_30_i_ival,
  output  gpio_0_pins_30_o_oval,
  output  gpio_0_pins_30_o_oe,
  input   gpio_0_pins_31_i_ival,
  output  gpio_0_pins_31_o_oval,
  output  gpio_0_pins_31_o_oe,
  input   iof_0_iof_0_0_o_oval,
  input   iof_0_iof_0_1_o_oval,
  output  iof_0_iof_0_2_i_ival,
  input   iof_0_iof_0_2_o_oval,
  input   iof_0_iof_0_2_o_oe,
  input   iof_0_iof_0_2_o_ie,
  output  iof_0_iof_0_3_i_ival,
  input   iof_0_iof_0_3_o_oval,
  input   iof_0_iof_0_3_o_oe,
  input   iof_0_iof_0_3_o_ie,
  output  iof_0_iof_0_4_i_ival,
  input   iof_0_iof_0_4_o_oval,
  input   iof_0_iof_0_4_o_oe,
  input   iof_0_iof_0_4_o_ie,
  output  iof_0_iof_0_5_i_ival,
  input   iof_0_iof_0_5_o_oval,
  input   iof_0_iof_0_5_o_oe,
  input   iof_0_iof_0_5_o_ie,
  output  iof_0_iof_0_12_i_ival,
  input   iof_0_iof_0_12_o_oe,
  output  iof_0_iof_0_13_i_ival,
  input   iof_0_iof_0_13_o_oe,
  output  iof_0_iof_0_14_i_ival,
  input   iof_0_iof_0_14_o_oe,
  output  iof_0_iof_0_15_i_ival,
  input   iof_0_iof_0_15_o_oe,
  output  iof_0_iof_0_16_i_ival,
  input   iof_0_iof_0_17_o_oval,
  output  iof_0_iof_0_18_i_ival,
  input   iof_0_iof_0_19_o_oval,
  output  iof_0_iof_0_20_i_ival,
  input   iof_0_iof_0_21_o_oval,
  output  iof_0_iof_0_22_i_ival,
  input   iof_0_iof_0_23_o_oval,
  input   iof_0_iof_0_24_o_oval,
  input   iof_0_iof_1_12_o_oval,
  input   iof_0_iof_1_13_o_oval,
  input   iof_0_iof_1_14_o_oval,
  input   iof_0_iof_1_15_o_oval,
  input   iof_0_iof_1_16_o_oval,
  input   iof_0_iof_1_17_o_oval,
  input   iof_0_iof_1_18_o_oval,
  input   iof_0_iof_1_19_o_oval,
  input   iof_0_iof_1_20_o_oval,
  input   iof_0_iof_1_21_o_oval,
  input   iof_0_iof_1_22_o_oval,
  input   iof_0_iof_1_23_o_oval,
  output  pwm_0_gpio_0,
  output  pwm_0_gpio_1,
  output  pwm_0_gpio_2,
  output  pwm_0_gpio_3,
  output  pwm_1_gpio_0,
  output  pwm_1_gpio_1,
  output  pwm_1_gpio_2,
  output  pwm_1_gpio_3,
  output  pwm_2_gpio_0,
  output  pwm_2_gpio_1,
  output  pwm_2_gpio_2,
  output  pwm_2_gpio_3,
  output  qspi_0_sck,
  input   qspi_0_dq_0_i,
  output  qspi_0_dq_0_o,
  output  qspi_0_dq_0_oe,
  input   qspi_0_dq_1_i,
  output  qspi_0_dq_1_o,
  output  qspi_0_dq_1_oe,
  input   qspi_0_dq_2_i,
  output  qspi_0_dq_2_o,
  output  qspi_0_dq_2_oe,
  input   qspi_0_dq_3_i,
  output  qspi_0_dq_3_o,
  output  qspi_0_dq_3_oe,
  output  qspi_0_cs_0,
  output  qspi_ram_0_sck,
  input   qspi_ram_0_dq_0_i,
  output  qspi_ram_0_dq_0_o,
  output  qspi_ram_0_dq_0_oe,
  input   qspi_ram_0_dq_1_i,
  output  qspi_ram_0_dq_1_o,
  output  qspi_ram_0_dq_1_oe,
  input   qspi_ram_0_dq_2_i,
  output  qspi_ram_0_dq_2_o,
  output  qspi_ram_0_dq_2_oe,
  input   qspi_ram_0_dq_3_i,
  output  qspi_ram_0_dq_3_o,
  output  qspi_ram_0_dq_3_oe,
  output  qspi_ram_0_cs_0,
  input   aon_pins_erst_n_i_ival,
  input   aon_pins_lfextclk_i_ival,
  output  aon_rsts_corerst,
  input   i2c_0_scl_in,
  output  i2c_0_scl_oe,
  input   i2c_0_sda_in,
  output  i2c_0_sda_oe,
  input   i2c_1_scl_in,
  output  i2c_1_scl_oe,
  input   i2c_1_sda_in,
  output  i2c_1_sda_oe
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
  wire  ibus_auto_int_bus_int_in_14_0; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_13_0; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_12_0; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_12_1; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_12_2; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_12_3; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_11_0; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_11_1; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_11_2; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_11_3; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_10_0; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_10_1; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_10_2; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_10_3; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_9_0; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_9_1; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_9_2; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_9_3; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_9_4; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_9_5; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_9_6; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_9_7; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_9_8; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_9_9; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_9_10; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_9_11; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_9_12; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_9_13; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_9_14; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_9_15; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_9_16; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_9_17; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_9_18; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_9_19; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_9_20; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_9_21; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_9_22; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_9_23; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_9_24; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_9_25; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_9_26; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_9_27; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_9_28; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_9_29; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_9_30; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_9_31; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_8_0; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_7_0; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_6_0; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_5_0; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_4_0; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_3_0; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_2_0; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_1_0; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_0_0; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_in_0_1; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_0; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_1; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_2; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_3; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_4; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_5; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_6; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_7; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_8; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_9; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_10; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_11; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_12; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_13; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_14; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_15; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_16; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_17; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_18; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_19; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_20; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_21; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_22; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_23; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_24; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_25; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_26; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_27; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_28; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_29; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_30; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_31; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_32; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_33; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_34; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_35; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_36; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_37; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_38; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_39; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_40; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_41; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_42; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_43; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_44; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_45; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_46; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_47; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_48; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_49; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_50; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_51; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_52; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_53; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_54; // @[BaseSubsystem.scala 50:24]
  wire  ibus_auto_int_bus_int_out_55; // @[BaseSubsystem.scala 50:24]
  wire  dummyClockGroupSourceNode_clock; // @[ClockGroup.scala 79:81]
  wire  dummyClockGroupSourceNode_reset; // @[ClockGroup.scala 79:81]
  wire  dummyClockGroupSourceNode_auto_out_member_subsystem_sbus_5_clock; // @[ClockGroup.scala 79:81]
  wire  dummyClockGroupSourceNode_auto_out_member_subsystem_sbus_5_reset; // @[ClockGroup.scala 79:81]
  wire  dummyClockGroupSourceNode_auto_out_member_subsystem_sbus_4_clock; // @[ClockGroup.scala 79:81]
  wire  dummyClockGroupSourceNode_auto_out_member_subsystem_sbus_4_reset; // @[ClockGroup.scala 79:81]
  wire  dummyClockGroupSourceNode_auto_out_member_subsystem_sbus_3_clock; // @[ClockGroup.scala 79:81]
  wire  dummyClockGroupSourceNode_auto_out_member_subsystem_sbus_3_reset; // @[ClockGroup.scala 79:81]
  wire  dummyClockGroupSourceNode_auto_out_member_subsystem_sbus_2_clock; // @[ClockGroup.scala 79:81]
  wire  dummyClockGroupSourceNode_auto_out_member_subsystem_sbus_2_reset; // @[ClockGroup.scala 79:81]
  wire  dummyClockGroupSourceNode_auto_out_member_subsystem_sbus_1_clock; // @[ClockGroup.scala 79:81]
  wire  dummyClockGroupSourceNode_auto_out_member_subsystem_sbus_1_reset; // @[ClockGroup.scala 79:81]
  wire  dummyClockGroupSourceNode_auto_out_member_subsystem_sbus_0_clock; // @[ClockGroup.scala 79:81]
  wire  dummyClockGroupSourceNode_auto_out_member_subsystem_sbus_0_reset; // @[ClockGroup.scala 79:81]
  wire  subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_ready; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_valid; // @[SystemBus.scala 24:26]
  wire [2:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_opcode; // @[SystemBus.scala 24:26]
  wire [2:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_param; // @[SystemBus.scala 24:26]
  wire [3:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_size; // @[SystemBus.scala 24:26]
  wire [1:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_source; // @[SystemBus.scala 24:26]
  wire [30:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_address; // @[SystemBus.scala 24:26]
  wire [3:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_mask; // @[SystemBus.scala 24:26]
  wire [31:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_data; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_corrupt; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_b_ready; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_b_valid; // @[SystemBus.scala 24:26]
  wire [1:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_b_bits_param; // @[SystemBus.scala 24:26]
  wire [30:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_b_bits_address; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_c_ready; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_c_valid; // @[SystemBus.scala 24:26]
  wire [2:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_opcode; // @[SystemBus.scala 24:26]
  wire [2:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_param; // @[SystemBus.scala 24:26]
  wire [3:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_size; // @[SystemBus.scala 24:26]
  wire [1:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_source; // @[SystemBus.scala 24:26]
  wire [30:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_address; // @[SystemBus.scala 24:26]
  wire [31:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_data; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_corrupt; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_ready; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_valid; // @[SystemBus.scala 24:26]
  wire [2:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_opcode; // @[SystemBus.scala 24:26]
  wire [1:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_param; // @[SystemBus.scala 24:26]
  wire [3:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_size; // @[SystemBus.scala 24:26]
  wire [1:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_source; // @[SystemBus.scala 24:26]
  wire [1:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_sink; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_denied; // @[SystemBus.scala 24:26]
  wire [31:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_data; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_corrupt; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_e_valid; // @[SystemBus.scala 24:26]
  wire [1:0] subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_e_bits_sink; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_ready; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_valid; // @[SystemBus.scala 24:26]
  wire [2:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_opcode; // @[SystemBus.scala 24:26]
  wire [2:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_param; // @[SystemBus.scala 24:26]
  wire [2:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_size; // @[SystemBus.scala 24:26]
  wire [1:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_source; // @[SystemBus.scala 24:26]
  wire [30:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_address; // @[SystemBus.scala 24:26]
  wire [3:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_mask; // @[SystemBus.scala 24:26]
  wire [31:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_data; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_corrupt; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_b_ready; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_b_valid; // @[SystemBus.scala 24:26]
  wire [1:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_b_bits_param; // @[SystemBus.scala 24:26]
  wire [30:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_b_bits_address; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_ready; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_valid; // @[SystemBus.scala 24:26]
  wire [2:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_opcode; // @[SystemBus.scala 24:26]
  wire [2:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_param; // @[SystemBus.scala 24:26]
  wire [2:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_size; // @[SystemBus.scala 24:26]
  wire [1:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_source; // @[SystemBus.scala 24:26]
  wire [30:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_address; // @[SystemBus.scala 24:26]
  wire [31:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_data; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_corrupt; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_d_ready; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_d_valid; // @[SystemBus.scala 24:26]
  wire [2:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_opcode; // @[SystemBus.scala 24:26]
  wire [1:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_param; // @[SystemBus.scala 24:26]
  wire [2:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_size; // @[SystemBus.scala 24:26]
  wire [1:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_source; // @[SystemBus.scala 24:26]
  wire [1:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_sink; // @[SystemBus.scala 24:26]
  wire [31:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_data; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_e_valid; // @[SystemBus.scala 24:26]
  wire [1:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_e_bits_sink; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_ready; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_valid; // @[SystemBus.scala 24:26]
  wire [2:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_opcode; // @[SystemBus.scala 24:26]
  wire [2:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_param; // @[SystemBus.scala 24:26]
  wire [3:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_size; // @[SystemBus.scala 24:26]
  wire [1:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_source; // @[SystemBus.scala 24:26]
  wire [29:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_address; // @[SystemBus.scala 24:26]
  wire [3:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_mask; // @[SystemBus.scala 24:26]
  wire [31:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_data; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_corrupt; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_ready; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_valid; // @[SystemBus.scala 24:26]
  wire [2:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_opcode; // @[SystemBus.scala 24:26]
  wire [1:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_param; // @[SystemBus.scala 24:26]
  wire [3:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_size; // @[SystemBus.scala 24:26]
  wire [1:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_source; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_sink; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_denied; // @[SystemBus.scala 24:26]
  wire [31:0] subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_data; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_corrupt; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_fixedClockNode_out_1_clock; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_fixedClockNode_out_1_reset; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_5_clock; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_5_reset; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_4_clock; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_4_reset; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_3_clock; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_3_reset; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_2_clock; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_2_reset; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_1_clock; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_1_reset; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_0_clock; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_0_reset; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_subsystem_sbus_clock_groups_out_2_member_subsystem_l2_1_clock; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_subsystem_sbus_clock_groups_out_2_member_subsystem_l2_1_reset; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_subsystem_sbus_clock_groups_out_2_member_subsystem_l2_0_clock; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_subsystem_sbus_clock_groups_out_2_member_subsystem_l2_0_reset; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_subsystem_sbus_clock_groups_out_1_member_subsystem_fbus_0_clock; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_subsystem_sbus_clock_groups_out_1_member_subsystem_fbus_0_reset; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_subsystem_sbus_clock_groups_out_0_member_subsystem_cbus_1_clock; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_subsystem_sbus_clock_groups_out_0_member_subsystem_cbus_1_reset; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_subsystem_sbus_clock_groups_out_0_member_subsystem_cbus_0_clock; // @[SystemBus.scala 24:26]
  wire  subsystem_sbus_auto_subsystem_sbus_clock_groups_out_0_member_subsystem_cbus_0_reset; // @[SystemBus.scala 24:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_a_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_a_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_param; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_source; // @[PeripheryBus.scala 31:26]
  wire [28:0] subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_address; // @[PeripheryBus.scala 31:26]
  wire [3:0] subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_d_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_d_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_d_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_d_bits_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_d_bits_source; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_d_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_a_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_a_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_param; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_source; // @[PeripheryBus.scala 31:26]
  wire [28:0] subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_address; // @[PeripheryBus.scala 31:26]
  wire [3:0] subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_d_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_d_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_d_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_d_bits_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_d_bits_source; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_d_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_a_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_a_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_param; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_source; // @[PeripheryBus.scala 31:26]
  wire [28:0] subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_address; // @[PeripheryBus.scala 31:26]
  wire [3:0] subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_d_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_d_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_d_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_d_bits_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_d_bits_source; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_d_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_a_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_a_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_param; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_source; // @[PeripheryBus.scala 31:26]
  wire [28:0] subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_address; // @[PeripheryBus.scala 31:26]
  wire [3:0] subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_d_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_d_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_d_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_d_bits_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_d_bits_source; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_d_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_a_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_a_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_param; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_source; // @[PeripheryBus.scala 31:26]
  wire [28:0] subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_address; // @[PeripheryBus.scala 31:26]
  wire [3:0] subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_d_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_d_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_d_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_d_bits_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_d_bits_source; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_d_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_param; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_source; // @[PeripheryBus.scala 31:26]
  wire [28:0] subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_address; // @[PeripheryBus.scala 31:26]
  wire [3:0] subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_d_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_d_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_source; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_a_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_a_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_param; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_source; // @[PeripheryBus.scala 31:26]
  wire [28:0] subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_address; // @[PeripheryBus.scala 31:26]
  wire [3:0] subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_d_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_d_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_d_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_d_bits_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_d_bits_source; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_d_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_param; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_source; // @[PeripheryBus.scala 31:26]
  wire [28:0] subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_address; // @[PeripheryBus.scala 31:26]
  wire [3:0] subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_d_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_d_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_d_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_d_bits_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_d_bits_source; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_d_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_param; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_size; // @[PeripheryBus.scala 31:26]
  wire [8:0] subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_source; // @[PeripheryBus.scala 31:26]
  wire [29:0] subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_address; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_d_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_d_valid; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_d_bits_size; // @[PeripheryBus.scala 31:26]
  wire [8:0] subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_d_bits_source; // @[PeripheryBus.scala 31:26]
  wire [7:0] subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_d_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_param; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_source; // @[PeripheryBus.scala 31:26]
  wire [28:0] subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_address; // @[PeripheryBus.scala 31:26]
  wire [3:0] subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_d_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_d_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_source; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_a_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_a_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_param; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_source; // @[PeripheryBus.scala 31:26]
  wire [28:0] subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_address; // @[PeripheryBus.scala 31:26]
  wire [3:0] subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_d_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_d_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_d_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_d_bits_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_d_bits_source; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_d_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_a_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_a_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_param; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_source; // @[PeripheryBus.scala 31:26]
  wire [28:0] subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_address; // @[PeripheryBus.scala 31:26]
  wire [3:0] subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_d_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_d_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_d_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_d_bits_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_d_bits_source; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_d_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_a_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_a_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_param; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_source; // @[PeripheryBus.scala 31:26]
  wire [28:0] subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_address; // @[PeripheryBus.scala 31:26]
  wire [3:0] subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_d_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_d_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_d_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_d_bits_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_d_bits_source; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_d_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_param; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_source; // @[PeripheryBus.scala 31:26]
  wire [28:0] subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_address; // @[PeripheryBus.scala 31:26]
  wire [3:0] subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_d_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_d_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_source; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source; // @[PeripheryBus.scala 31:26]
  wire [28:0] subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address; // @[PeripheryBus.scala 31:26]
  wire [3:0] subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_fixedClockNode_out_13_clock; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_fixedClockNode_out_13_reset; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_fixedClockNode_out_12_clock; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_fixedClockNode_out_12_reset; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_fixedClockNode_out_11_clock; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_fixedClockNode_out_11_reset; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_fixedClockNode_out_10_clock; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_fixedClockNode_out_10_reset; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_fixedClockNode_out_9_clock; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_fixedClockNode_out_9_reset; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_fixedClockNode_out_8_clock; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_fixedClockNode_out_8_reset; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_fixedClockNode_out_7_clock; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_fixedClockNode_out_7_reset; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_fixedClockNode_out_6_clock; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_fixedClockNode_out_6_reset; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_fixedClockNode_out_5_clock; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_fixedClockNode_out_5_reset; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_fixedClockNode_out_4_clock; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_fixedClockNode_out_4_reset; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_fixedClockNode_out_3_clock; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_fixedClockNode_out_3_reset; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_fixedClockNode_out_2_clock; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_fixedClockNode_out_2_reset; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_fixedClockNode_out_1_clock; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_fixedClockNode_out_1_reset; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_fixedClockNode_out_0_clock; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_fixedClockNode_out_0_reset; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_subsystem_pbus_clock_groups_in_member_subsystem_pbus_0_clock; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_subsystem_pbus_clock_groups_in_member_subsystem_pbus_0_reset; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_bus_xing_in_a_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_bus_xing_in_a_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_bus_xing_in_a_bits_param; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_bus_xing_in_a_bits_size; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_pbus_auto_bus_xing_in_a_bits_source; // @[PeripheryBus.scala 31:26]
  wire [29:0] subsystem_pbus_auto_bus_xing_in_a_bits_address; // @[PeripheryBus.scala 31:26]
  wire [3:0] subsystem_pbus_auto_bus_xing_in_a_bits_mask; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_pbus_auto_bus_xing_in_a_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_bus_xing_in_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_bus_xing_in_d_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_pbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_pbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_pbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_pbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_pbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala 31:26]
  wire  subsystem_fbus_auto_subsystem_fbus_clock_groups_in_member_subsystem_fbus_0_clock; // @[FrontBus.scala 22:26]
  wire  subsystem_fbus_auto_subsystem_fbus_clock_groups_in_member_subsystem_fbus_0_reset; // @[FrontBus.scala 22:26]
  wire  subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_param; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_source; // @[PeripheryBus.scala 31:26]
  wire [16:0] subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_address; // @[PeripheryBus.scala 31:26]
  wire [3:0] subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_d_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_d_valid; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_d_bits_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_d_bits_source; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_d_bits_data; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_cbus_auto_coupler_to_aon_asource_out_a_mem_0_opcode; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_cbus_auto_coupler_to_aon_asource_out_a_mem_0_param; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_cbus_auto_coupler_to_aon_asource_out_a_mem_0_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_cbus_auto_coupler_to_aon_asource_out_a_mem_0_source; // @[PeripheryBus.scala 31:26]
  wire [28:0] subsystem_cbus_auto_coupler_to_aon_asource_out_a_mem_0_address; // @[PeripheryBus.scala 31:26]
  wire [3:0] subsystem_cbus_auto_coupler_to_aon_asource_out_a_mem_0_mask; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_cbus_auto_coupler_to_aon_asource_out_a_mem_0_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_aon_asource_out_a_mem_0_corrupt; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_aon_asource_out_a_ridx; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_aon_asource_out_a_widx; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_aon_asource_out_a_safe_ridx_valid; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_aon_asource_out_a_safe_widx_valid; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_aon_asource_out_a_safe_source_reset_n; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_aon_asource_out_a_safe_sink_reset_n; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_cbus_auto_coupler_to_aon_asource_out_d_mem_0_opcode; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_cbus_auto_coupler_to_aon_asource_out_d_mem_0_param; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_cbus_auto_coupler_to_aon_asource_out_d_mem_0_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_cbus_auto_coupler_to_aon_asource_out_d_mem_0_source; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_aon_asource_out_d_mem_0_sink; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_aon_asource_out_d_mem_0_denied; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_cbus_auto_coupler_to_aon_asource_out_d_mem_0_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_aon_asource_out_d_mem_0_corrupt; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_aon_asource_out_d_ridx; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_aon_asource_out_d_widx; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_aon_asource_out_d_safe_ridx_valid; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_aon_asource_out_d_safe_widx_valid; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_aon_asource_out_d_safe_source_reset_n; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_aon_asource_out_d_safe_sink_reset_n; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_param; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_size; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_source; // @[PeripheryBus.scala 31:26]
  wire [27:0] subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_address; // @[PeripheryBus.scala 31:26]
  wire [3:0] subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_param; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_size; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_source; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_sink; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_denied; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_corrupt; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_param; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_source; // @[PeripheryBus.scala 31:26]
  wire [11:0] subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_address; // @[PeripheryBus.scala 31:26]
  wire [3:0] subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_bits_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_bits_source; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_param; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_source; // @[PeripheryBus.scala 31:26]
  wire [25:0] subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_address; // @[PeripheryBus.scala 31:26]
  wire [3:0] subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_bits_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_bits_source; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_param; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_source; // @[PeripheryBus.scala 31:26]
  wire [27:0] subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_address; // @[PeripheryBus.scala 31:26]
  wire [3:0] subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_bits_size; // @[PeripheryBus.scala 31:26]
  wire [6:0] subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_bits_source; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_param; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_size; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_source; // @[PeripheryBus.scala 31:26]
  wire [29:0] subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_address; // @[PeripheryBus.scala 31:26]
  wire [3:0] subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_mask; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_param; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_size; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_source; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_sink; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_denied; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_corrupt; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_fixedClockNode_out_2_clock; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_fixedClockNode_out_2_reset; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_fixedClockNode_out_0_clock; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_fixedClockNode_out_0_reset; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_1_clock; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_1_reset; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_0_clock; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_0_reset; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_subsystem_cbus_clock_groups_out_member_subsystem_pbus_0_clock; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_subsystem_cbus_clock_groups_out_member_subsystem_pbus_0_reset; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_bus_xing_in_a_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_cbus_auto_bus_xing_in_a_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_cbus_auto_bus_xing_in_a_bits_param; // @[PeripheryBus.scala 31:26]
  wire [3:0] subsystem_cbus_auto_bus_xing_in_a_bits_size; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_cbus_auto_bus_xing_in_a_bits_source; // @[PeripheryBus.scala 31:26]
  wire [29:0] subsystem_cbus_auto_bus_xing_in_a_bits_address; // @[PeripheryBus.scala 31:26]
  wire [3:0] subsystem_cbus_auto_bus_xing_in_a_bits_mask; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_cbus_auto_bus_xing_in_a_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_bus_xing_in_a_bits_corrupt; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_bus_xing_in_d_ready; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala 31:26]
  wire [2:0] subsystem_cbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_cbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala 31:26]
  wire [3:0] subsystem_cbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala 31:26]
  wire [1:0] subsystem_cbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala 31:26]
  wire [31:0] subsystem_cbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_clock; // @[PeripheryBus.scala 31:26]
  wire  subsystem_cbus_reset; // @[PeripheryBus.scala 31:26]
  wire  subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_ready; // @[MemoryBus.scala 25:26]
  wire  subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_valid; // @[MemoryBus.scala 25:26]
  wire [2:0] subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_opcode; // @[MemoryBus.scala 25:26]
  wire [2:0] subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_param; // @[MemoryBus.scala 25:26]
  wire  subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_size; // @[MemoryBus.scala 25:26]
  wire [10:0] subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_source; // @[MemoryBus.scala 25:26]
  wire [30:0] subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_address; // @[MemoryBus.scala 25:26]
  wire  subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_mask; // @[MemoryBus.scala 25:26]
  wire [7:0] subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_data; // @[MemoryBus.scala 25:26]
  wire  subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_corrupt; // @[MemoryBus.scala 25:26]
  wire  subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_d_ready; // @[MemoryBus.scala 25:26]
  wire  subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_d_valid; // @[MemoryBus.scala 25:26]
  wire [2:0] subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_d_bits_opcode; // @[MemoryBus.scala 25:26]
  wire  subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_d_bits_size; // @[MemoryBus.scala 25:26]
  wire [10:0] subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_d_bits_source; // @[MemoryBus.scala 25:26]
  wire [7:0] subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_d_bits_data; // @[MemoryBus.scala 25:26]
  wire  subsystem_mbus_auto_subsystem_mbus_clock_groups_in_member_subsystem_mbus_0_clock; // @[MemoryBus.scala 25:26]
  wire  subsystem_mbus_auto_subsystem_mbus_clock_groups_in_member_subsystem_mbus_0_reset; // @[MemoryBus.scala 25:26]
  wire  subsystem_mbus_auto_bus_xing_in_a_ready; // @[MemoryBus.scala 25:26]
  wire  subsystem_mbus_auto_bus_xing_in_a_valid; // @[MemoryBus.scala 25:26]
  wire [2:0] subsystem_mbus_auto_bus_xing_in_a_bits_opcode; // @[MemoryBus.scala 25:26]
  wire [2:0] subsystem_mbus_auto_bus_xing_in_a_bits_param; // @[MemoryBus.scala 25:26]
  wire [2:0] subsystem_mbus_auto_bus_xing_in_a_bits_size; // @[MemoryBus.scala 25:26]
  wire [3:0] subsystem_mbus_auto_bus_xing_in_a_bits_source; // @[MemoryBus.scala 25:26]
  wire [30:0] subsystem_mbus_auto_bus_xing_in_a_bits_address; // @[MemoryBus.scala 25:26]
  wire [3:0] subsystem_mbus_auto_bus_xing_in_a_bits_mask; // @[MemoryBus.scala 25:26]
  wire [31:0] subsystem_mbus_auto_bus_xing_in_a_bits_data; // @[MemoryBus.scala 25:26]
  wire  subsystem_mbus_auto_bus_xing_in_d_ready; // @[MemoryBus.scala 25:26]
  wire  subsystem_mbus_auto_bus_xing_in_d_valid; // @[MemoryBus.scala 25:26]
  wire [2:0] subsystem_mbus_auto_bus_xing_in_d_bits_opcode; // @[MemoryBus.scala 25:26]
  wire [2:0] subsystem_mbus_auto_bus_xing_in_d_bits_size; // @[MemoryBus.scala 25:26]
  wire [3:0] subsystem_mbus_auto_bus_xing_in_d_bits_source; // @[MemoryBus.scala 25:26]
  wire [31:0] subsystem_mbus_auto_bus_xing_in_d_bits_data; // @[MemoryBus.scala 25:26]
  wire  subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_ready; // @[BankedL2Params.scala 47:31]
  wire  subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_valid; // @[BankedL2Params.scala 47:31]
  wire [2:0] subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_opcode; // @[BankedL2Params.scala 47:31]
  wire [2:0] subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_param; // @[BankedL2Params.scala 47:31]
  wire [2:0] subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_size; // @[BankedL2Params.scala 47:31]
  wire [3:0] subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_source; // @[BankedL2Params.scala 47:31]
  wire [30:0] subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_address; // @[BankedL2Params.scala 47:31]
  wire [3:0] subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_mask; // @[BankedL2Params.scala 47:31]
  wire [31:0] subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_data; // @[BankedL2Params.scala 47:31]
  wire  subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_ready; // @[BankedL2Params.scala 47:31]
  wire  subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_valid; // @[BankedL2Params.scala 47:31]
  wire [2:0] subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_bits_opcode; // @[BankedL2Params.scala 47:31]
  wire [2:0] subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_bits_size; // @[BankedL2Params.scala 47:31]
  wire [3:0] subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_bits_source; // @[BankedL2Params.scala 47:31]
  wire [31:0] subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_bits_data; // @[BankedL2Params.scala 47:31]
  wire  subsystem_l2_wrapper_auto_coherent_jbar_in_a_ready; // @[BankedL2Params.scala 47:31]
  wire  subsystem_l2_wrapper_auto_coherent_jbar_in_a_valid; // @[BankedL2Params.scala 47:31]
  wire [2:0] subsystem_l2_wrapper_auto_coherent_jbar_in_a_bits_opcode; // @[BankedL2Params.scala 47:31]
  wire [2:0] subsystem_l2_wrapper_auto_coherent_jbar_in_a_bits_param; // @[BankedL2Params.scala 47:31]
  wire [2:0] subsystem_l2_wrapper_auto_coherent_jbar_in_a_bits_size; // @[BankedL2Params.scala 47:31]
  wire [1:0] subsystem_l2_wrapper_auto_coherent_jbar_in_a_bits_source; // @[BankedL2Params.scala 47:31]
  wire [30:0] subsystem_l2_wrapper_auto_coherent_jbar_in_a_bits_address; // @[BankedL2Params.scala 47:31]
  wire [3:0] subsystem_l2_wrapper_auto_coherent_jbar_in_a_bits_mask; // @[BankedL2Params.scala 47:31]
  wire [31:0] subsystem_l2_wrapper_auto_coherent_jbar_in_a_bits_data; // @[BankedL2Params.scala 47:31]
  wire  subsystem_l2_wrapper_auto_coherent_jbar_in_a_bits_corrupt; // @[BankedL2Params.scala 47:31]
  wire  subsystem_l2_wrapper_auto_coherent_jbar_in_b_ready; // @[BankedL2Params.scala 47:31]
  wire  subsystem_l2_wrapper_auto_coherent_jbar_in_b_valid; // @[BankedL2Params.scala 47:31]
  wire [1:0] subsystem_l2_wrapper_auto_coherent_jbar_in_b_bits_param; // @[BankedL2Params.scala 47:31]
  wire [30:0] subsystem_l2_wrapper_auto_coherent_jbar_in_b_bits_address; // @[BankedL2Params.scala 47:31]
  wire  subsystem_l2_wrapper_auto_coherent_jbar_in_c_ready; // @[BankedL2Params.scala 47:31]
  wire  subsystem_l2_wrapper_auto_coherent_jbar_in_c_valid; // @[BankedL2Params.scala 47:31]
  wire [2:0] subsystem_l2_wrapper_auto_coherent_jbar_in_c_bits_opcode; // @[BankedL2Params.scala 47:31]
  wire [2:0] subsystem_l2_wrapper_auto_coherent_jbar_in_c_bits_param; // @[BankedL2Params.scala 47:31]
  wire [2:0] subsystem_l2_wrapper_auto_coherent_jbar_in_c_bits_size; // @[BankedL2Params.scala 47:31]
  wire [1:0] subsystem_l2_wrapper_auto_coherent_jbar_in_c_bits_source; // @[BankedL2Params.scala 47:31]
  wire [30:0] subsystem_l2_wrapper_auto_coherent_jbar_in_c_bits_address; // @[BankedL2Params.scala 47:31]
  wire [31:0] subsystem_l2_wrapper_auto_coherent_jbar_in_c_bits_data; // @[BankedL2Params.scala 47:31]
  wire  subsystem_l2_wrapper_auto_coherent_jbar_in_c_bits_corrupt; // @[BankedL2Params.scala 47:31]
  wire  subsystem_l2_wrapper_auto_coherent_jbar_in_d_ready; // @[BankedL2Params.scala 47:31]
  wire  subsystem_l2_wrapper_auto_coherent_jbar_in_d_valid; // @[BankedL2Params.scala 47:31]
  wire [2:0] subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_opcode; // @[BankedL2Params.scala 47:31]
  wire [1:0] subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_param; // @[BankedL2Params.scala 47:31]
  wire [2:0] subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_size; // @[BankedL2Params.scala 47:31]
  wire [1:0] subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_source; // @[BankedL2Params.scala 47:31]
  wire [1:0] subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_sink; // @[BankedL2Params.scala 47:31]
  wire [31:0] subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_data; // @[BankedL2Params.scala 47:31]
  wire  subsystem_l2_wrapper_auto_coherent_jbar_in_e_valid; // @[BankedL2Params.scala 47:31]
  wire [1:0] subsystem_l2_wrapper_auto_coherent_jbar_in_e_bits_sink; // @[BankedL2Params.scala 47:31]
  wire  subsystem_l2_wrapper_auto_subsystem_l2_clock_groups_in_member_subsystem_l2_1_clock; // @[BankedL2Params.scala 47:31]
  wire  subsystem_l2_wrapper_auto_subsystem_l2_clock_groups_in_member_subsystem_l2_1_reset; // @[BankedL2Params.scala 47:31]
  wire  subsystem_l2_wrapper_auto_subsystem_l2_clock_groups_in_member_subsystem_l2_0_clock; // @[BankedL2Params.scala 47:31]
  wire  subsystem_l2_wrapper_auto_subsystem_l2_clock_groups_in_member_subsystem_l2_0_reset; // @[BankedL2Params.scala 47:31]
  wire  subsystem_l2_wrapper_auto_subsystem_l2_clock_groups_out_member_subsystem_mbus_0_clock; // @[BankedL2Params.scala 47:31]
  wire  subsystem_l2_wrapper_auto_subsystem_l2_clock_groups_out_member_subsystem_mbus_0_reset; // @[BankedL2Params.scala 47:31]
  wire  tile_prci_domain_auto_intsink_in_sync_0; // @[HasTiles.scala 252:38]
  wire  tile_prci_domain_auto_tile_reset_domain_tile_hartid_in; // @[HasTiles.scala 252:38]
  wire  tile_prci_domain_auto_int_out_clock_xing_out_2_sync_0; // @[HasTiles.scala 252:38]
  wire  tile_prci_domain_auto_int_out_clock_xing_out_1_sync_0; // @[HasTiles.scala 252:38]
  wire  tile_prci_domain_auto_int_out_clock_xing_out_0_sync_0; // @[HasTiles.scala 252:38]
  wire  tile_prci_domain_auto_int_in_clock_xing_in_2_sync_0; // @[HasTiles.scala 252:38]
  wire  tile_prci_domain_auto_int_in_clock_xing_in_1_sync_0; // @[HasTiles.scala 252:38]
  wire  tile_prci_domain_auto_int_in_clock_xing_in_0_sync_0; // @[HasTiles.scala 252:38]
  wire  tile_prci_domain_auto_int_in_clock_xing_in_0_sync_1; // @[HasTiles.scala 252:38]
  wire  tile_prci_domain_auto_tl_slave_clock_xing_in_a_ready; // @[HasTiles.scala 252:38]
  wire  tile_prci_domain_auto_tl_slave_clock_xing_in_a_valid; // @[HasTiles.scala 252:38]
  wire [2:0] tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_opcode; // @[HasTiles.scala 252:38]
  wire [2:0] tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_param; // @[HasTiles.scala 252:38]
  wire [2:0] tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_size; // @[HasTiles.scala 252:38]
  wire [1:0] tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_source; // @[HasTiles.scala 252:38]
  wire [27:0] tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_address; // @[HasTiles.scala 252:38]
  wire [3:0] tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_mask; // @[HasTiles.scala 252:38]
  wire [31:0] tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_data; // @[HasTiles.scala 252:38]
  wire  tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_corrupt; // @[HasTiles.scala 252:38]
  wire  tile_prci_domain_auto_tl_slave_clock_xing_in_d_ready; // @[HasTiles.scala 252:38]
  wire  tile_prci_domain_auto_tl_slave_clock_xing_in_d_valid; // @[HasTiles.scala 252:38]
  wire [2:0] tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_opcode; // @[HasTiles.scala 252:38]
  wire [1:0] tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_param; // @[HasTiles.scala 252:38]
  wire [2:0] tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_size; // @[HasTiles.scala 252:38]
  wire [1:0] tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_source; // @[HasTiles.scala 252:38]
  wire  tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_sink; // @[HasTiles.scala 252:38]
  wire  tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_denied; // @[HasTiles.scala 252:38]
  wire [31:0] tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_data; // @[HasTiles.scala 252:38]
  wire  tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_corrupt; // @[HasTiles.scala 252:38]
  wire  tile_prci_domain_auto_tl_master_clock_xing_out_a_ready; // @[HasTiles.scala 252:38]
  wire  tile_prci_domain_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala 252:38]
  wire [2:0] tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala 252:38]
  wire [2:0] tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala 252:38]
  wire [3:0] tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala 252:38]
  wire [1:0] tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala 252:38]
  wire [30:0] tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala 252:38]
  wire [3:0] tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala 252:38]
  wire [31:0] tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala 252:38]
  wire  tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala 252:38]
  wire  tile_prci_domain_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala 252:38]
  wire  tile_prci_domain_auto_tl_master_clock_xing_out_b_valid; // @[HasTiles.scala 252:38]
  wire [1:0] tile_prci_domain_auto_tl_master_clock_xing_out_b_bits_param; // @[HasTiles.scala 252:38]
  wire [30:0] tile_prci_domain_auto_tl_master_clock_xing_out_b_bits_address; // @[HasTiles.scala 252:38]
  wire  tile_prci_domain_auto_tl_master_clock_xing_out_c_ready; // @[HasTiles.scala 252:38]
  wire  tile_prci_domain_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala 252:38]
  wire [2:0] tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala 252:38]
  wire [2:0] tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala 252:38]
  wire [3:0] tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala 252:38]
  wire [1:0] tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala 252:38]
  wire [30:0] tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala 252:38]
  wire [31:0] tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala 252:38]
  wire  tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala 252:38]
  wire  tile_prci_domain_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala 252:38]
  wire  tile_prci_domain_auto_tl_master_clock_xing_out_d_valid; // @[HasTiles.scala 252:38]
  wire [2:0] tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_opcode; // @[HasTiles.scala 252:38]
  wire [1:0] tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_param; // @[HasTiles.scala 252:38]
  wire [3:0] tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_size; // @[HasTiles.scala 252:38]
  wire [1:0] tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_source; // @[HasTiles.scala 252:38]
  wire [1:0] tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_sink; // @[HasTiles.scala 252:38]
  wire  tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_denied; // @[HasTiles.scala 252:38]
  wire [31:0] tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_data; // @[HasTiles.scala 252:38]
  wire  tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_corrupt; // @[HasTiles.scala 252:38]
  wire  tile_prci_domain_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala 252:38]
  wire [1:0] tile_prci_domain_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala 252:38]
  wire  tile_prci_domain_auto_tap_clock_in_clock; // @[HasTiles.scala 252:38]
  wire  tile_prci_domain_auto_tap_clock_in_reset; // @[HasTiles.scala 252:38]
  wire  plicDomainWrapper_auto_plic_int_in_0; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_1; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_2; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_3; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_4; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_5; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_6; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_7; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_8; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_9; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_10; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_11; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_12; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_13; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_14; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_15; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_16; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_17; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_18; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_19; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_20; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_21; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_22; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_23; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_24; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_25; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_26; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_27; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_28; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_29; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_30; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_31; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_32; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_33; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_34; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_35; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_36; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_37; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_38; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_39; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_40; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_41; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_42; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_43; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_44; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_45; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_46; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_47; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_48; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_49; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_50; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_51; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_52; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_53; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_54; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_in_55; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_out_1_0; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_int_out_0_0; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_in_a_ready; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_in_a_valid; // @[Plic.scala 359:39]
  wire [2:0] plicDomainWrapper_auto_plic_in_a_bits_opcode; // @[Plic.scala 359:39]
  wire [2:0] plicDomainWrapper_auto_plic_in_a_bits_param; // @[Plic.scala 359:39]
  wire [1:0] plicDomainWrapper_auto_plic_in_a_bits_size; // @[Plic.scala 359:39]
  wire [6:0] plicDomainWrapper_auto_plic_in_a_bits_source; // @[Plic.scala 359:39]
  wire [27:0] plicDomainWrapper_auto_plic_in_a_bits_address; // @[Plic.scala 359:39]
  wire [3:0] plicDomainWrapper_auto_plic_in_a_bits_mask; // @[Plic.scala 359:39]
  wire [31:0] plicDomainWrapper_auto_plic_in_a_bits_data; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_in_a_bits_corrupt; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_in_d_ready; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_plic_in_d_valid; // @[Plic.scala 359:39]
  wire [2:0] plicDomainWrapper_auto_plic_in_d_bits_opcode; // @[Plic.scala 359:39]
  wire [1:0] plicDomainWrapper_auto_plic_in_d_bits_size; // @[Plic.scala 359:39]
  wire [6:0] plicDomainWrapper_auto_plic_in_d_bits_source; // @[Plic.scala 359:39]
  wire [31:0] plicDomainWrapper_auto_plic_in_d_bits_data; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_clock_in_clock; // @[Plic.scala 359:39]
  wire  plicDomainWrapper_auto_clock_in_reset; // @[Plic.scala 359:39]
  wire  clint_clock; // @[CLINT.scala 109:27]
  wire  clint_reset; // @[CLINT.scala 109:27]
  wire  clint_auto_int_out_0; // @[CLINT.scala 109:27]
  wire  clint_auto_int_out_1; // @[CLINT.scala 109:27]
  wire  clint_auto_in_a_ready; // @[CLINT.scala 109:27]
  wire  clint_auto_in_a_valid; // @[CLINT.scala 109:27]
  wire [2:0] clint_auto_in_a_bits_opcode; // @[CLINT.scala 109:27]
  wire [2:0] clint_auto_in_a_bits_param; // @[CLINT.scala 109:27]
  wire [1:0] clint_auto_in_a_bits_size; // @[CLINT.scala 109:27]
  wire [6:0] clint_auto_in_a_bits_source; // @[CLINT.scala 109:27]
  wire [25:0] clint_auto_in_a_bits_address; // @[CLINT.scala 109:27]
  wire [3:0] clint_auto_in_a_bits_mask; // @[CLINT.scala 109:27]
  wire [31:0] clint_auto_in_a_bits_data; // @[CLINT.scala 109:27]
  wire  clint_auto_in_a_bits_corrupt; // @[CLINT.scala 109:27]
  wire  clint_auto_in_d_ready; // @[CLINT.scala 109:27]
  wire  clint_auto_in_d_valid; // @[CLINT.scala 109:27]
  wire [2:0] clint_auto_in_d_bits_opcode; // @[CLINT.scala 109:27]
  wire [1:0] clint_auto_in_d_bits_size; // @[CLINT.scala 109:27]
  wire [6:0] clint_auto_in_d_bits_source; // @[CLINT.scala 109:27]
  wire [31:0] clint_auto_in_d_bits_data; // @[CLINT.scala 109:27]
  wire  clint_io_rtcTick; // @[CLINT.scala 109:27]
  wire  debug_1_auto_dmInner_dmInner_tl_in_a_ready; // @[Periphery.scala 84:27]
  wire  debug_1_auto_dmInner_dmInner_tl_in_a_valid; // @[Periphery.scala 84:27]
  wire [2:0] debug_1_auto_dmInner_dmInner_tl_in_a_bits_opcode; // @[Periphery.scala 84:27]
  wire [2:0] debug_1_auto_dmInner_dmInner_tl_in_a_bits_param; // @[Periphery.scala 84:27]
  wire [1:0] debug_1_auto_dmInner_dmInner_tl_in_a_bits_size; // @[Periphery.scala 84:27]
  wire [6:0] debug_1_auto_dmInner_dmInner_tl_in_a_bits_source; // @[Periphery.scala 84:27]
  wire [11:0] debug_1_auto_dmInner_dmInner_tl_in_a_bits_address; // @[Periphery.scala 84:27]
  wire [3:0] debug_1_auto_dmInner_dmInner_tl_in_a_bits_mask; // @[Periphery.scala 84:27]
  wire [31:0] debug_1_auto_dmInner_dmInner_tl_in_a_bits_data; // @[Periphery.scala 84:27]
  wire  debug_1_auto_dmInner_dmInner_tl_in_a_bits_corrupt; // @[Periphery.scala 84:27]
  wire  debug_1_auto_dmInner_dmInner_tl_in_d_ready; // @[Periphery.scala 84:27]
  wire  debug_1_auto_dmInner_dmInner_tl_in_d_valid; // @[Periphery.scala 84:27]
  wire [2:0] debug_1_auto_dmInner_dmInner_tl_in_d_bits_opcode; // @[Periphery.scala 84:27]
  wire [1:0] debug_1_auto_dmInner_dmInner_tl_in_d_bits_size; // @[Periphery.scala 84:27]
  wire [6:0] debug_1_auto_dmInner_dmInner_tl_in_d_bits_source; // @[Periphery.scala 84:27]
  wire [31:0] debug_1_auto_dmInner_dmInner_tl_in_d_bits_data; // @[Periphery.scala 84:27]
  wire  debug_1_auto_dmOuter_intsource_out_sync_0; // @[Periphery.scala 84:27]
  wire  debug_1_io_debug_clock; // @[Periphery.scala 84:27]
  wire  debug_1_io_ctrl_ndreset; // @[Periphery.scala 84:27]
  wire  debug_1_io_dmi_dmi_req_ready; // @[Periphery.scala 84:27]
  wire  debug_1_io_dmi_dmi_req_valid; // @[Periphery.scala 84:27]
  wire [6:0] debug_1_io_dmi_dmi_req_bits_addr; // @[Periphery.scala 84:27]
  wire [31:0] debug_1_io_dmi_dmi_req_bits_data; // @[Periphery.scala 84:27]
  wire [1:0] debug_1_io_dmi_dmi_req_bits_op; // @[Periphery.scala 84:27]
  wire  debug_1_io_dmi_dmi_resp_ready; // @[Periphery.scala 84:27]
  wire  debug_1_io_dmi_dmi_resp_valid; // @[Periphery.scala 84:27]
  wire [31:0] debug_1_io_dmi_dmi_resp_bits_data; // @[Periphery.scala 84:27]
  wire [1:0] debug_1_io_dmi_dmi_resp_bits_resp; // @[Periphery.scala 84:27]
  wire  debug_1_io_dmi_dmiClock; // @[Periphery.scala 84:27]
  wire  debug_1_io_dmi_dmiReset; // @[Periphery.scala 84:27]
  wire  tileHartIdNexusNode_auto_out; // @[HasTiles.scala 159:39]
  wire  intsource_clock; // @[Crossing.scala 26:31]
  wire  intsource_reset; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_0; // @[Crossing.scala 26:31]
  wire  intsource_auto_in_1; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_0; // @[Crossing.scala 26:31]
  wire  intsource_auto_out_sync_1; // @[Crossing.scala 26:31]
  wire  intsource_1_clock; // @[Crossing.scala 26:31]
  wire  intsource_1_reset; // @[Crossing.scala 26:31]
  wire  intsource_1_auto_in_0; // @[Crossing.scala 26:31]
  wire  intsource_1_auto_out_sync_0; // @[Crossing.scala 26:31]
  wire  intsource_2_clock; // @[Crossing.scala 26:31]
  wire  intsource_2_reset; // @[Crossing.scala 26:31]
  wire  intsource_2_auto_in_0; // @[Crossing.scala 26:31]
  wire  intsource_2_auto_out_sync_0; // @[Crossing.scala 26:31]
  wire  intsink_1_auto_in_sync_0; // @[Crossing.scala 94:29]
  wire  intsink_1_auto_out_0; // @[Crossing.scala 94:29]
  wire  intsink_2_auto_in_sync_0; // @[Crossing.scala 94:29]
  wire  intsink_2_auto_out_0; // @[Crossing.scala 94:29]
  wire  intsink_3_auto_in_sync_0; // @[Crossing.scala 94:29]
  wire  intsink_3_auto_out_0; // @[Crossing.scala 94:29]
  wire  aon_1_auto_intsource_out_sync_0; // @[MockAONPeriphery.scala 21:23]
  wire  aon_1_auto_intsource_out_sync_1; // @[MockAONPeriphery.scala 21:23]
  wire [2:0] aon_1_auto_isolation_in_a_mem_0_opcode; // @[MockAONPeriphery.scala 21:23]
  wire [2:0] aon_1_auto_isolation_in_a_mem_0_param; // @[MockAONPeriphery.scala 21:23]
  wire [1:0] aon_1_auto_isolation_in_a_mem_0_size; // @[MockAONPeriphery.scala 21:23]
  wire [6:0] aon_1_auto_isolation_in_a_mem_0_source; // @[MockAONPeriphery.scala 21:23]
  wire [28:0] aon_1_auto_isolation_in_a_mem_0_address; // @[MockAONPeriphery.scala 21:23]
  wire [3:0] aon_1_auto_isolation_in_a_mem_0_mask; // @[MockAONPeriphery.scala 21:23]
  wire [31:0] aon_1_auto_isolation_in_a_mem_0_data; // @[MockAONPeriphery.scala 21:23]
  wire  aon_1_auto_isolation_in_a_mem_0_corrupt; // @[MockAONPeriphery.scala 21:23]
  wire  aon_1_auto_isolation_in_a_ridx; // @[MockAONPeriphery.scala 21:23]
  wire  aon_1_auto_isolation_in_a_widx; // @[MockAONPeriphery.scala 21:23]
  wire  aon_1_auto_isolation_in_a_safe_ridx_valid; // @[MockAONPeriphery.scala 21:23]
  wire  aon_1_auto_isolation_in_a_safe_widx_valid; // @[MockAONPeriphery.scala 21:23]
  wire  aon_1_auto_isolation_in_a_safe_source_reset_n; // @[MockAONPeriphery.scala 21:23]
  wire  aon_1_auto_isolation_in_a_safe_sink_reset_n; // @[MockAONPeriphery.scala 21:23]
  wire [2:0] aon_1_auto_isolation_in_d_mem_0_opcode; // @[MockAONPeriphery.scala 21:23]
  wire [1:0] aon_1_auto_isolation_in_d_mem_0_param; // @[MockAONPeriphery.scala 21:23]
  wire [1:0] aon_1_auto_isolation_in_d_mem_0_size; // @[MockAONPeriphery.scala 21:23]
  wire [6:0] aon_1_auto_isolation_in_d_mem_0_source; // @[MockAONPeriphery.scala 21:23]
  wire  aon_1_auto_isolation_in_d_mem_0_sink; // @[MockAONPeriphery.scala 21:23]
  wire  aon_1_auto_isolation_in_d_mem_0_denied; // @[MockAONPeriphery.scala 21:23]
  wire [31:0] aon_1_auto_isolation_in_d_mem_0_data; // @[MockAONPeriphery.scala 21:23]
  wire  aon_1_auto_isolation_in_d_mem_0_corrupt; // @[MockAONPeriphery.scala 21:23]
  wire  aon_1_auto_isolation_in_d_ridx; // @[MockAONPeriphery.scala 21:23]
  wire  aon_1_auto_isolation_in_d_widx; // @[MockAONPeriphery.scala 21:23]
  wire  aon_1_auto_isolation_in_d_safe_ridx_valid; // @[MockAONPeriphery.scala 21:23]
  wire  aon_1_auto_isolation_in_d_safe_widx_valid; // @[MockAONPeriphery.scala 21:23]
  wire  aon_1_auto_isolation_in_d_safe_source_reset_n; // @[MockAONPeriphery.scala 21:23]
  wire  aon_1_auto_isolation_in_d_safe_sink_reset_n; // @[MockAONPeriphery.scala 21:23]
  wire  aon_1_io_pins_erst_n_i_ival; // @[MockAONPeriphery.scala 21:23]
  wire  aon_1_io_pins_lfextclk_i_ival; // @[MockAONPeriphery.scala 21:23]
  wire  aon_1_io_rsts_corerst; // @[MockAONPeriphery.scala 21:23]
  wire  aon_1_io_rtc; // @[MockAONPeriphery.scala 21:23]
  wire  aon_1_io_ndreset; // @[MockAONPeriphery.scala 21:23]
  wire  intsink_4_clock; // @[Crossing.scala 74:29]
  wire  intsink_4_auto_in_sync_0; // @[Crossing.scala 74:29]
  wire  intsink_4_auto_in_sync_1; // @[Crossing.scala 74:29]
  wire  intsink_4_auto_out_0; // @[Crossing.scala 74:29]
  wire  intsink_4_auto_out_1; // @[Crossing.scala 74:29]
  wire  uartClockDomainWrapper_auto_uart_0_int_xing_out_sync_0; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_auto_uart_0_control_xing_in_a_valid; // @[UART.scala 242:44]
  wire [2:0] uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_opcode; // @[UART.scala 242:44]
  wire [2:0] uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_param; // @[UART.scala 242:44]
  wire [1:0] uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_size; // @[UART.scala 242:44]
  wire [6:0] uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_source; // @[UART.scala 242:44]
  wire [28:0] uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_address; // @[UART.scala 242:44]
  wire [3:0] uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_mask; // @[UART.scala 242:44]
  wire [31:0] uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_data; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_corrupt; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_auto_uart_0_control_xing_in_d_ready; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid; // @[UART.scala 242:44]
  wire [2:0] uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode; // @[UART.scala 242:44]
  wire [1:0] uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size; // @[UART.scala 242:44]
  wire [6:0] uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source; // @[UART.scala 242:44]
  wire [31:0] uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_auto_uart_0_io_out_txd; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_auto_uart_0_io_out_rxd; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_auto_clock_in_clock; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_auto_clock_in_reset; // @[UART.scala 242:44]
  wire  intsink_5_auto_in_sync_0; // @[Crossing.scala 94:29]
  wire  intsink_5_auto_out_0; // @[Crossing.scala 94:29]
  wire  uartClockDomainWrapper_1_auto_uart_1_int_xing_out_sync_0; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_ready; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_valid; // @[UART.scala 242:44]
  wire [2:0] uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_opcode; // @[UART.scala 242:44]
  wire [2:0] uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_param; // @[UART.scala 242:44]
  wire [1:0] uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_size; // @[UART.scala 242:44]
  wire [6:0] uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_source; // @[UART.scala 242:44]
  wire [28:0] uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_address; // @[UART.scala 242:44]
  wire [3:0] uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_mask; // @[UART.scala 242:44]
  wire [31:0] uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_data; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_corrupt; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_1_auto_uart_1_control_xing_in_d_ready; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_1_auto_uart_1_control_xing_in_d_valid; // @[UART.scala 242:44]
  wire [2:0] uartClockDomainWrapper_1_auto_uart_1_control_xing_in_d_bits_opcode; // @[UART.scala 242:44]
  wire [1:0] uartClockDomainWrapper_1_auto_uart_1_control_xing_in_d_bits_size; // @[UART.scala 242:44]
  wire [6:0] uartClockDomainWrapper_1_auto_uart_1_control_xing_in_d_bits_source; // @[UART.scala 242:44]
  wire [31:0] uartClockDomainWrapper_1_auto_uart_1_control_xing_in_d_bits_data; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_1_auto_uart_1_io_out_txd; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_1_auto_uart_1_io_out_rxd; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_1_auto_clock_in_clock; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_1_auto_clock_in_reset; // @[UART.scala 242:44]
  wire  intsink_6_auto_in_sync_0; // @[Crossing.scala 94:29]
  wire  intsink_6_auto_out_0; // @[Crossing.scala 94:29]
  wire  uartClockDomainWrapper_2_auto_uart_2_int_xing_out_sync_0; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_2_auto_uart_2_control_xing_in_a_ready; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_2_auto_uart_2_control_xing_in_a_valid; // @[UART.scala 242:44]
  wire [2:0] uartClockDomainWrapper_2_auto_uart_2_control_xing_in_a_bits_opcode; // @[UART.scala 242:44]
  wire [2:0] uartClockDomainWrapper_2_auto_uart_2_control_xing_in_a_bits_param; // @[UART.scala 242:44]
  wire [1:0] uartClockDomainWrapper_2_auto_uart_2_control_xing_in_a_bits_size; // @[UART.scala 242:44]
  wire [6:0] uartClockDomainWrapper_2_auto_uart_2_control_xing_in_a_bits_source; // @[UART.scala 242:44]
  wire [28:0] uartClockDomainWrapper_2_auto_uart_2_control_xing_in_a_bits_address; // @[UART.scala 242:44]
  wire [3:0] uartClockDomainWrapper_2_auto_uart_2_control_xing_in_a_bits_mask; // @[UART.scala 242:44]
  wire [31:0] uartClockDomainWrapper_2_auto_uart_2_control_xing_in_a_bits_data; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_2_auto_uart_2_control_xing_in_a_bits_corrupt; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_2_auto_uart_2_control_xing_in_d_ready; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_2_auto_uart_2_control_xing_in_d_valid; // @[UART.scala 242:44]
  wire [2:0] uartClockDomainWrapper_2_auto_uart_2_control_xing_in_d_bits_opcode; // @[UART.scala 242:44]
  wire [1:0] uartClockDomainWrapper_2_auto_uart_2_control_xing_in_d_bits_size; // @[UART.scala 242:44]
  wire [6:0] uartClockDomainWrapper_2_auto_uart_2_control_xing_in_d_bits_source; // @[UART.scala 242:44]
  wire [31:0] uartClockDomainWrapper_2_auto_uart_2_control_xing_in_d_bits_data; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_2_auto_uart_2_io_out_txd; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_2_auto_uart_2_io_out_rxd; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_2_auto_clock_in_clock; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_2_auto_clock_in_reset; // @[UART.scala 242:44]
  wire  intsink_7_auto_in_sync_0; // @[Crossing.scala 94:29]
  wire  intsink_7_auto_out_0; // @[Crossing.scala 94:29]
  wire  uartClockDomainWrapper_3_auto_uart_3_int_xing_out_sync_0; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_3_auto_uart_3_control_xing_in_a_ready; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_3_auto_uart_3_control_xing_in_a_valid; // @[UART.scala 242:44]
  wire [2:0] uartClockDomainWrapper_3_auto_uart_3_control_xing_in_a_bits_opcode; // @[UART.scala 242:44]
  wire [2:0] uartClockDomainWrapper_3_auto_uart_3_control_xing_in_a_bits_param; // @[UART.scala 242:44]
  wire [1:0] uartClockDomainWrapper_3_auto_uart_3_control_xing_in_a_bits_size; // @[UART.scala 242:44]
  wire [6:0] uartClockDomainWrapper_3_auto_uart_3_control_xing_in_a_bits_source; // @[UART.scala 242:44]
  wire [28:0] uartClockDomainWrapper_3_auto_uart_3_control_xing_in_a_bits_address; // @[UART.scala 242:44]
  wire [3:0] uartClockDomainWrapper_3_auto_uart_3_control_xing_in_a_bits_mask; // @[UART.scala 242:44]
  wire [31:0] uartClockDomainWrapper_3_auto_uart_3_control_xing_in_a_bits_data; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_3_auto_uart_3_control_xing_in_a_bits_corrupt; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_3_auto_uart_3_control_xing_in_d_ready; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_3_auto_uart_3_control_xing_in_d_valid; // @[UART.scala 242:44]
  wire [2:0] uartClockDomainWrapper_3_auto_uart_3_control_xing_in_d_bits_opcode; // @[UART.scala 242:44]
  wire [1:0] uartClockDomainWrapper_3_auto_uart_3_control_xing_in_d_bits_size; // @[UART.scala 242:44]
  wire [6:0] uartClockDomainWrapper_3_auto_uart_3_control_xing_in_d_bits_source; // @[UART.scala 242:44]
  wire [31:0] uartClockDomainWrapper_3_auto_uart_3_control_xing_in_d_bits_data; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_3_auto_uart_3_io_out_txd; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_3_auto_uart_3_io_out_rxd; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_3_auto_clock_in_clock; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_3_auto_clock_in_reset; // @[UART.scala 242:44]
  wire  intsink_8_auto_in_sync_0; // @[Crossing.scala 94:29]
  wire  intsink_8_auto_out_0; // @[Crossing.scala 94:29]
  wire  uartClockDomainWrapper_4_auto_uart_4_int_xing_out_sync_0; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_4_auto_uart_4_control_xing_in_a_ready; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_4_auto_uart_4_control_xing_in_a_valid; // @[UART.scala 242:44]
  wire [2:0] uartClockDomainWrapper_4_auto_uart_4_control_xing_in_a_bits_opcode; // @[UART.scala 242:44]
  wire [2:0] uartClockDomainWrapper_4_auto_uart_4_control_xing_in_a_bits_param; // @[UART.scala 242:44]
  wire [1:0] uartClockDomainWrapper_4_auto_uart_4_control_xing_in_a_bits_size; // @[UART.scala 242:44]
  wire [6:0] uartClockDomainWrapper_4_auto_uart_4_control_xing_in_a_bits_source; // @[UART.scala 242:44]
  wire [28:0] uartClockDomainWrapper_4_auto_uart_4_control_xing_in_a_bits_address; // @[UART.scala 242:44]
  wire [3:0] uartClockDomainWrapper_4_auto_uart_4_control_xing_in_a_bits_mask; // @[UART.scala 242:44]
  wire [31:0] uartClockDomainWrapper_4_auto_uart_4_control_xing_in_a_bits_data; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_4_auto_uart_4_control_xing_in_a_bits_corrupt; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_4_auto_uart_4_control_xing_in_d_ready; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_4_auto_uart_4_control_xing_in_d_valid; // @[UART.scala 242:44]
  wire [2:0] uartClockDomainWrapper_4_auto_uart_4_control_xing_in_d_bits_opcode; // @[UART.scala 242:44]
  wire [1:0] uartClockDomainWrapper_4_auto_uart_4_control_xing_in_d_bits_size; // @[UART.scala 242:44]
  wire [6:0] uartClockDomainWrapper_4_auto_uart_4_control_xing_in_d_bits_source; // @[UART.scala 242:44]
  wire [31:0] uartClockDomainWrapper_4_auto_uart_4_control_xing_in_d_bits_data; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_4_auto_uart_4_io_out_txd; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_4_auto_uart_4_io_out_rxd; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_4_auto_clock_in_clock; // @[UART.scala 242:44]
  wire  uartClockDomainWrapper_4_auto_clock_in_reset; // @[UART.scala 242:44]
  wire  intsink_9_auto_in_sync_0; // @[Crossing.scala 94:29]
  wire  intsink_9_auto_out_0; // @[Crossing.scala 94:29]
  wire  qspiClockDomainWrapper_auto_qspi_0_int_xing_out_sync_0; // @[SPI.scala 92:44]
  wire  qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_ready; // @[SPI.scala 92:44]
  wire  qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_valid; // @[SPI.scala 92:44]
  wire [2:0] qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_opcode; // @[SPI.scala 92:44]
  wire [2:0] qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_param; // @[SPI.scala 92:44]
  wire  qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_size; // @[SPI.scala 92:44]
  wire [8:0] qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_source; // @[SPI.scala 92:44]
  wire [29:0] qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_address; // @[SPI.scala 92:44]
  wire  qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_mask; // @[SPI.scala 92:44]
  wire  qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_corrupt; // @[SPI.scala 92:44]
  wire  qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_d_ready; // @[SPI.scala 92:44]
  wire  qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_d_valid; // @[SPI.scala 92:44]
  wire  qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_d_bits_size; // @[SPI.scala 92:44]
  wire [8:0] qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_d_bits_source; // @[SPI.scala 92:44]
  wire [7:0] qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_d_bits_data; // @[SPI.scala 92:44]
  wire  qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_ready; // @[SPI.scala 92:44]
  wire  qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_valid; // @[SPI.scala 92:44]
  wire [2:0] qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_opcode; // @[SPI.scala 92:44]
  wire [2:0] qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_param; // @[SPI.scala 92:44]
  wire [1:0] qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_size; // @[SPI.scala 92:44]
  wire [6:0] qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_source; // @[SPI.scala 92:44]
  wire [28:0] qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_address; // @[SPI.scala 92:44]
  wire [3:0] qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_mask; // @[SPI.scala 92:44]
  wire [31:0] qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_data; // @[SPI.scala 92:44]
  wire  qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_corrupt; // @[SPI.scala 92:44]
  wire  qspiClockDomainWrapper_auto_qspi_0_control_xing_in_d_ready; // @[SPI.scala 92:44]
  wire  qspiClockDomainWrapper_auto_qspi_0_control_xing_in_d_valid; // @[SPI.scala 92:44]
  wire [2:0] qspiClockDomainWrapper_auto_qspi_0_control_xing_in_d_bits_opcode; // @[SPI.scala 92:44]
  wire [1:0] qspiClockDomainWrapper_auto_qspi_0_control_xing_in_d_bits_size; // @[SPI.scala 92:44]
  wire [6:0] qspiClockDomainWrapper_auto_qspi_0_control_xing_in_d_bits_source; // @[SPI.scala 92:44]
  wire [31:0] qspiClockDomainWrapper_auto_qspi_0_control_xing_in_d_bits_data; // @[SPI.scala 92:44]
  wire  qspiClockDomainWrapper_auto_qspi_0_io_out_sck; // @[SPI.scala 92:44]
  wire  qspiClockDomainWrapper_auto_qspi_0_io_out_dq_0_i; // @[SPI.scala 92:44]
  wire  qspiClockDomainWrapper_auto_qspi_0_io_out_dq_0_o; // @[SPI.scala 92:44]
  wire  qspiClockDomainWrapper_auto_qspi_0_io_out_dq_0_oe; // @[SPI.scala 92:44]
  wire  qspiClockDomainWrapper_auto_qspi_0_io_out_dq_1_i; // @[SPI.scala 92:44]
  wire  qspiClockDomainWrapper_auto_qspi_0_io_out_dq_1_o; // @[SPI.scala 92:44]
  wire  qspiClockDomainWrapper_auto_qspi_0_io_out_dq_1_oe; // @[SPI.scala 92:44]
  wire  qspiClockDomainWrapper_auto_qspi_0_io_out_dq_2_i; // @[SPI.scala 92:44]
  wire  qspiClockDomainWrapper_auto_qspi_0_io_out_dq_2_o; // @[SPI.scala 92:44]
  wire  qspiClockDomainWrapper_auto_qspi_0_io_out_dq_2_oe; // @[SPI.scala 92:44]
  wire  qspiClockDomainWrapper_auto_qspi_0_io_out_dq_3_i; // @[SPI.scala 92:44]
  wire  qspiClockDomainWrapper_auto_qspi_0_io_out_dq_3_o; // @[SPI.scala 92:44]
  wire  qspiClockDomainWrapper_auto_qspi_0_io_out_dq_3_oe; // @[SPI.scala 92:44]
  wire  qspiClockDomainWrapper_auto_qspi_0_io_out_cs_0; // @[SPI.scala 92:44]
  wire  qspiClockDomainWrapper_auto_clock_in_clock; // @[SPI.scala 92:44]
  wire  qspiClockDomainWrapper_auto_clock_in_reset; // @[SPI.scala 92:44]
  wire  intsink_10_auto_in_sync_0; // @[Crossing.scala 94:29]
  wire  intsink_10_auto_out_0; // @[Crossing.scala 94:29]
  wire  qspiClockDomainWrapper_1_auto_qspi_ram_0_int_xing_out_sync_0; // @[SPI.scala 39:44]
  wire  qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_a_ready; // @[SPI.scala 39:44]
  wire  qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_a_valid; // @[SPI.scala 39:44]
  wire [2:0] qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_a_bits_opcode; // @[SPI.scala 39:44]
  wire [2:0] qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_a_bits_param; // @[SPI.scala 39:44]
  wire  qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_a_bits_size; // @[SPI.scala 39:44]
  wire [10:0] qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_a_bits_source; // @[SPI.scala 39:44]
  wire [30:0] qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_a_bits_address; // @[SPI.scala 39:44]
  wire  qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_a_bits_mask; // @[SPI.scala 39:44]
  wire [7:0] qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_a_bits_data; // @[SPI.scala 39:44]
  wire  qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_a_bits_corrupt; // @[SPI.scala 39:44]
  wire  qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_d_ready; // @[SPI.scala 39:44]
  wire  qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_d_valid; // @[SPI.scala 39:44]
  wire [2:0] qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_d_bits_opcode; // @[SPI.scala 39:44]
  wire  qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_d_bits_size; // @[SPI.scala 39:44]
  wire [10:0] qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_d_bits_source; // @[SPI.scala 39:44]
  wire [7:0] qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_d_bits_data; // @[SPI.scala 39:44]
  wire  qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_a_ready; // @[SPI.scala 39:44]
  wire  qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_a_valid; // @[SPI.scala 39:44]
  wire [2:0] qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_a_bits_opcode; // @[SPI.scala 39:44]
  wire [2:0] qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_a_bits_param; // @[SPI.scala 39:44]
  wire [1:0] qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_a_bits_size; // @[SPI.scala 39:44]
  wire [6:0] qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_a_bits_source; // @[SPI.scala 39:44]
  wire [28:0] qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_a_bits_address; // @[SPI.scala 39:44]
  wire [3:0] qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_a_bits_mask; // @[SPI.scala 39:44]
  wire [31:0] qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_a_bits_data; // @[SPI.scala 39:44]
  wire  qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_a_bits_corrupt; // @[SPI.scala 39:44]
  wire  qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_d_ready; // @[SPI.scala 39:44]
  wire  qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_d_valid; // @[SPI.scala 39:44]
  wire [2:0] qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_d_bits_opcode; // @[SPI.scala 39:44]
  wire [1:0] qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_d_bits_size; // @[SPI.scala 39:44]
  wire [6:0] qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_d_bits_source; // @[SPI.scala 39:44]
  wire [31:0] qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_d_bits_data; // @[SPI.scala 39:44]
  wire  qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_sck; // @[SPI.scala 39:44]
  wire  qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_dq_0_i; // @[SPI.scala 39:44]
  wire  qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_dq_0_o; // @[SPI.scala 39:44]
  wire  qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_dq_0_oe; // @[SPI.scala 39:44]
  wire  qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_dq_1_i; // @[SPI.scala 39:44]
  wire  qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_dq_1_o; // @[SPI.scala 39:44]
  wire  qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_dq_1_oe; // @[SPI.scala 39:44]
  wire  qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_dq_2_i; // @[SPI.scala 39:44]
  wire  qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_dq_2_o; // @[SPI.scala 39:44]
  wire  qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_dq_2_oe; // @[SPI.scala 39:44]
  wire  qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_dq_3_i; // @[SPI.scala 39:44]
  wire  qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_dq_3_o; // @[SPI.scala 39:44]
  wire  qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_dq_3_oe; // @[SPI.scala 39:44]
  wire  qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_cs_0; // @[SPI.scala 39:44]
  wire  qspiClockDomainWrapper_1_auto_clock_in_clock; // @[SPI.scala 39:44]
  wire  qspiClockDomainWrapper_1_auto_clock_in_reset; // @[SPI.scala 39:44]
  wire  intsink_11_auto_in_sync_0; // @[Crossing.scala 94:29]
  wire  intsink_11_auto_out_0; // @[Crossing.scala 94:29]
  wire  spiClockDomainWrapper_auto_spi_0_int_xing_out_sync_0; // @[SPI.scala 35:43]
  wire  spiClockDomainWrapper_auto_spi_0_control_xing_in_a_ready; // @[SPI.scala 35:43]
  wire  spiClockDomainWrapper_auto_spi_0_control_xing_in_a_valid; // @[SPI.scala 35:43]
  wire [2:0] spiClockDomainWrapper_auto_spi_0_control_xing_in_a_bits_opcode; // @[SPI.scala 35:43]
  wire [2:0] spiClockDomainWrapper_auto_spi_0_control_xing_in_a_bits_param; // @[SPI.scala 35:43]
  wire [1:0] spiClockDomainWrapper_auto_spi_0_control_xing_in_a_bits_size; // @[SPI.scala 35:43]
  wire [6:0] spiClockDomainWrapper_auto_spi_0_control_xing_in_a_bits_source; // @[SPI.scala 35:43]
  wire [28:0] spiClockDomainWrapper_auto_spi_0_control_xing_in_a_bits_address; // @[SPI.scala 35:43]
  wire [3:0] spiClockDomainWrapper_auto_spi_0_control_xing_in_a_bits_mask; // @[SPI.scala 35:43]
  wire [31:0] spiClockDomainWrapper_auto_spi_0_control_xing_in_a_bits_data; // @[SPI.scala 35:43]
  wire  spiClockDomainWrapper_auto_spi_0_control_xing_in_a_bits_corrupt; // @[SPI.scala 35:43]
  wire  spiClockDomainWrapper_auto_spi_0_control_xing_in_d_ready; // @[SPI.scala 35:43]
  wire  spiClockDomainWrapper_auto_spi_0_control_xing_in_d_valid; // @[SPI.scala 35:43]
  wire [2:0] spiClockDomainWrapper_auto_spi_0_control_xing_in_d_bits_opcode; // @[SPI.scala 35:43]
  wire [1:0] spiClockDomainWrapper_auto_spi_0_control_xing_in_d_bits_size; // @[SPI.scala 35:43]
  wire [6:0] spiClockDomainWrapper_auto_spi_0_control_xing_in_d_bits_source; // @[SPI.scala 35:43]
  wire [31:0] spiClockDomainWrapper_auto_spi_0_control_xing_in_d_bits_data; // @[SPI.scala 35:43]
  wire  spiClockDomainWrapper_auto_spi_0_io_out_sck; // @[SPI.scala 35:43]
  wire  spiClockDomainWrapper_auto_spi_0_io_out_dq_0_i; // @[SPI.scala 35:43]
  wire  spiClockDomainWrapper_auto_spi_0_io_out_dq_0_o; // @[SPI.scala 35:43]
  wire  spiClockDomainWrapper_auto_spi_0_io_out_dq_0_oe; // @[SPI.scala 35:43]
  wire  spiClockDomainWrapper_auto_spi_0_io_out_dq_1_i; // @[SPI.scala 35:43]
  wire  spiClockDomainWrapper_auto_spi_0_io_out_dq_1_o; // @[SPI.scala 35:43]
  wire  spiClockDomainWrapper_auto_spi_0_io_out_dq_1_oe; // @[SPI.scala 35:43]
  wire  spiClockDomainWrapper_auto_spi_0_io_out_dq_2_i; // @[SPI.scala 35:43]
  wire  spiClockDomainWrapper_auto_spi_0_io_out_dq_2_o; // @[SPI.scala 35:43]
  wire  spiClockDomainWrapper_auto_spi_0_io_out_dq_2_oe; // @[SPI.scala 35:43]
  wire  spiClockDomainWrapper_auto_spi_0_io_out_dq_3_i; // @[SPI.scala 35:43]
  wire  spiClockDomainWrapper_auto_spi_0_io_out_dq_3_o; // @[SPI.scala 35:43]
  wire  spiClockDomainWrapper_auto_spi_0_io_out_dq_3_oe; // @[SPI.scala 35:43]
  wire  spiClockDomainWrapper_auto_spi_0_io_out_cs_0; // @[SPI.scala 35:43]
  wire  spiClockDomainWrapper_auto_spi_0_io_out_cs_1; // @[SPI.scala 35:43]
  wire  spiClockDomainWrapper_auto_clock_in_clock; // @[SPI.scala 35:43]
  wire  spiClockDomainWrapper_auto_clock_in_reset; // @[SPI.scala 35:43]
  wire  intsink_12_auto_in_sync_0; // @[Crossing.scala 94:29]
  wire  intsink_12_auto_out_0; // @[Crossing.scala 94:29]
  wire  gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_0; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_1; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_2; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_3; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_4; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_5; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_6; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_7; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_8; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_9; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_10; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_11; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_12; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_13; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_14; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_15; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_16; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_17; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_18; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_19; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_20; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_21; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_22; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_23; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_24; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_25; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_26; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_27; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_28; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_29; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_30; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_31; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_ready; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_valid; // @[GPIO.scala 281:44]
  wire [2:0] gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_opcode; // @[GPIO.scala 281:44]
  wire [2:0] gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_param; // @[GPIO.scala 281:44]
  wire [1:0] gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_size; // @[GPIO.scala 281:44]
  wire [6:0] gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_source; // @[GPIO.scala 281:44]
  wire [28:0] gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_address; // @[GPIO.scala 281:44]
  wire [3:0] gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_mask; // @[GPIO.scala 281:44]
  wire [31:0] gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_data; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_corrupt; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_control_xing_in_d_ready; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_control_xing_in_d_valid; // @[GPIO.scala 281:44]
  wire [2:0] gpioClockDomainWrapper_auto_gpio_0_control_xing_in_d_bits_opcode; // @[GPIO.scala 281:44]
  wire [1:0] gpioClockDomainWrapper_auto_gpio_0_control_xing_in_d_bits_size; // @[GPIO.scala 281:44]
  wire [6:0] gpioClockDomainWrapper_auto_gpio_0_control_xing_in_d_bits_source; // @[GPIO.scala 281:44]
  wire [31:0] gpioClockDomainWrapper_auto_gpio_0_control_xing_in_d_bits_data; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_0_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_1_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_2_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_2_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_2_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_2_o_ie; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_3_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_3_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_3_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_3_o_ie; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_4_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_4_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_4_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_4_o_ie; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_5_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_5_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_5_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_5_o_ie; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_12_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_12_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_13_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_13_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_14_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_14_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_15_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_15_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_16_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_17_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_18_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_19_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_20_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_21_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_22_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_23_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_24_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_1_12_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_1_13_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_1_14_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_1_15_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_1_16_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_1_17_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_1_18_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_1_19_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_1_20_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_1_21_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_1_22_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_1_23_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_0_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_0_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_0_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_0_o_ie; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_1_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_1_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_1_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_1_o_ie; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_2_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_2_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_2_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_2_o_ie; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_3_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_3_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_3_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_3_o_ie; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_4_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_4_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_4_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_4_o_ie; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_5_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_5_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_5_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_5_o_ie; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_6_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_6_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_6_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_7_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_7_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_7_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_8_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_8_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_8_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_9_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_9_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_9_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_10_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_10_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_10_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_11_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_11_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_11_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_12_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_12_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_12_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_12_o_ie; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_13_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_13_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_13_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_13_o_ie; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_14_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_14_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_14_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_14_o_ie; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_15_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_15_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_15_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_15_o_ie; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_16_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_16_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_16_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_16_o_ie; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_17_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_17_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_17_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_17_o_ie; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_18_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_18_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_18_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_18_o_ie; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_19_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_19_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_19_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_19_o_ie; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_20_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_20_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_20_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_20_o_ie; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_21_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_21_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_21_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_21_o_ie; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_22_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_22_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_22_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_22_o_ie; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_23_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_23_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_23_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_23_o_ie; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_24_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_24_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_24_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_24_o_ie; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_25_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_25_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_25_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_26_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_26_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_26_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_27_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_27_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_27_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_28_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_28_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_28_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_29_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_29_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_29_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_30_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_30_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_30_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_31_i_ival; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_31_o_oval; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_gpio_0_io_out_pins_31_o_oe; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_clock_in_clock; // @[GPIO.scala 281:44]
  wire  gpioClockDomainWrapper_auto_clock_in_reset; // @[GPIO.scala 281:44]
  wire  intsink_13_auto_in_sync_0; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_in_sync_1; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_in_sync_2; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_in_sync_3; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_in_sync_4; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_in_sync_5; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_in_sync_6; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_in_sync_7; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_in_sync_8; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_in_sync_9; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_in_sync_10; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_in_sync_11; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_in_sync_12; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_in_sync_13; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_in_sync_14; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_in_sync_15; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_in_sync_16; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_in_sync_17; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_in_sync_18; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_in_sync_19; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_in_sync_20; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_in_sync_21; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_in_sync_22; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_in_sync_23; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_in_sync_24; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_in_sync_25; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_in_sync_26; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_in_sync_27; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_in_sync_28; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_in_sync_29; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_in_sync_30; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_in_sync_31; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_out_0; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_out_1; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_out_2; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_out_3; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_out_4; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_out_5; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_out_6; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_out_7; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_out_8; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_out_9; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_out_10; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_out_11; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_out_12; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_out_13; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_out_14; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_out_15; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_out_16; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_out_17; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_out_18; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_out_19; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_out_20; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_out_21; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_out_22; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_out_23; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_out_24; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_out_25; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_out_26; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_out_27; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_out_28; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_out_29; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_out_30; // @[Crossing.scala 94:29]
  wire  intsink_13_auto_out_31; // @[Crossing.scala 94:29]
  wire  pwmClockDomainWrapper_auto_pwm_0_int_xing_out_sync_0; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_auto_pwm_0_int_xing_out_sync_1; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_auto_pwm_0_int_xing_out_sync_2; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_auto_pwm_0_int_xing_out_sync_3; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_auto_pwm_0_control_xing_in_a_ready; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_auto_pwm_0_control_xing_in_a_valid; // @[PWM.scala 134:43]
  wire [2:0] pwmClockDomainWrapper_auto_pwm_0_control_xing_in_a_bits_opcode; // @[PWM.scala 134:43]
  wire [2:0] pwmClockDomainWrapper_auto_pwm_0_control_xing_in_a_bits_param; // @[PWM.scala 134:43]
  wire [1:0] pwmClockDomainWrapper_auto_pwm_0_control_xing_in_a_bits_size; // @[PWM.scala 134:43]
  wire [6:0] pwmClockDomainWrapper_auto_pwm_0_control_xing_in_a_bits_source; // @[PWM.scala 134:43]
  wire [28:0] pwmClockDomainWrapper_auto_pwm_0_control_xing_in_a_bits_address; // @[PWM.scala 134:43]
  wire [3:0] pwmClockDomainWrapper_auto_pwm_0_control_xing_in_a_bits_mask; // @[PWM.scala 134:43]
  wire [31:0] pwmClockDomainWrapper_auto_pwm_0_control_xing_in_a_bits_data; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_auto_pwm_0_control_xing_in_a_bits_corrupt; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_auto_pwm_0_control_xing_in_d_ready; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_auto_pwm_0_control_xing_in_d_valid; // @[PWM.scala 134:43]
  wire [2:0] pwmClockDomainWrapper_auto_pwm_0_control_xing_in_d_bits_opcode; // @[PWM.scala 134:43]
  wire [1:0] pwmClockDomainWrapper_auto_pwm_0_control_xing_in_d_bits_size; // @[PWM.scala 134:43]
  wire [6:0] pwmClockDomainWrapper_auto_pwm_0_control_xing_in_d_bits_source; // @[PWM.scala 134:43]
  wire [31:0] pwmClockDomainWrapper_auto_pwm_0_control_xing_in_d_bits_data; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_auto_pwm_0_io_out_gpio_0; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_auto_pwm_0_io_out_gpio_1; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_auto_pwm_0_io_out_gpio_2; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_auto_pwm_0_io_out_gpio_3; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_auto_clock_in_clock; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_auto_clock_in_reset; // @[PWM.scala 134:43]
  wire  intsink_14_auto_in_sync_0; // @[Crossing.scala 94:29]
  wire  intsink_14_auto_in_sync_1; // @[Crossing.scala 94:29]
  wire  intsink_14_auto_in_sync_2; // @[Crossing.scala 94:29]
  wire  intsink_14_auto_in_sync_3; // @[Crossing.scala 94:29]
  wire  intsink_14_auto_out_0; // @[Crossing.scala 94:29]
  wire  intsink_14_auto_out_1; // @[Crossing.scala 94:29]
  wire  intsink_14_auto_out_2; // @[Crossing.scala 94:29]
  wire  intsink_14_auto_out_3; // @[Crossing.scala 94:29]
  wire  pwmClockDomainWrapper_1_auto_pwm_1_int_xing_out_sync_0; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_1_auto_pwm_1_int_xing_out_sync_1; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_1_auto_pwm_1_int_xing_out_sync_2; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_1_auto_pwm_1_int_xing_out_sync_3; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_a_ready; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_a_valid; // @[PWM.scala 134:43]
  wire [2:0] pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_a_bits_opcode; // @[PWM.scala 134:43]
  wire [2:0] pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_a_bits_param; // @[PWM.scala 134:43]
  wire [1:0] pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_a_bits_size; // @[PWM.scala 134:43]
  wire [6:0] pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_a_bits_source; // @[PWM.scala 134:43]
  wire [28:0] pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_a_bits_address; // @[PWM.scala 134:43]
  wire [3:0] pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_a_bits_mask; // @[PWM.scala 134:43]
  wire [31:0] pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_a_bits_data; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_a_bits_corrupt; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_d_ready; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_d_valid; // @[PWM.scala 134:43]
  wire [2:0] pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_d_bits_opcode; // @[PWM.scala 134:43]
  wire [1:0] pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_d_bits_size; // @[PWM.scala 134:43]
  wire [6:0] pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_d_bits_source; // @[PWM.scala 134:43]
  wire [31:0] pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_d_bits_data; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_1_auto_pwm_1_io_out_gpio_0; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_1_auto_pwm_1_io_out_gpio_1; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_1_auto_pwm_1_io_out_gpio_2; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_1_auto_pwm_1_io_out_gpio_3; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_1_auto_clock_in_clock; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_1_auto_clock_in_reset; // @[PWM.scala 134:43]
  wire  intsink_15_auto_in_sync_0; // @[Crossing.scala 94:29]
  wire  intsink_15_auto_in_sync_1; // @[Crossing.scala 94:29]
  wire  intsink_15_auto_in_sync_2; // @[Crossing.scala 94:29]
  wire  intsink_15_auto_in_sync_3; // @[Crossing.scala 94:29]
  wire  intsink_15_auto_out_0; // @[Crossing.scala 94:29]
  wire  intsink_15_auto_out_1; // @[Crossing.scala 94:29]
  wire  intsink_15_auto_out_2; // @[Crossing.scala 94:29]
  wire  intsink_15_auto_out_3; // @[Crossing.scala 94:29]
  wire  pwmClockDomainWrapper_2_auto_pwm_2_int_xing_out_sync_0; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_2_auto_pwm_2_int_xing_out_sync_1; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_2_auto_pwm_2_int_xing_out_sync_2; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_2_auto_pwm_2_int_xing_out_sync_3; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_a_ready; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_a_valid; // @[PWM.scala 134:43]
  wire [2:0] pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_a_bits_opcode; // @[PWM.scala 134:43]
  wire [2:0] pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_a_bits_param; // @[PWM.scala 134:43]
  wire [1:0] pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_a_bits_size; // @[PWM.scala 134:43]
  wire [6:0] pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_a_bits_source; // @[PWM.scala 134:43]
  wire [28:0] pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_a_bits_address; // @[PWM.scala 134:43]
  wire [3:0] pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_a_bits_mask; // @[PWM.scala 134:43]
  wire [31:0] pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_a_bits_data; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_a_bits_corrupt; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_d_ready; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_d_valid; // @[PWM.scala 134:43]
  wire [2:0] pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_d_bits_opcode; // @[PWM.scala 134:43]
  wire [1:0] pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_d_bits_size; // @[PWM.scala 134:43]
  wire [6:0] pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_d_bits_source; // @[PWM.scala 134:43]
  wire [31:0] pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_d_bits_data; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_2_auto_pwm_2_io_out_gpio_0; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_2_auto_pwm_2_io_out_gpio_1; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_2_auto_pwm_2_io_out_gpio_2; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_2_auto_pwm_2_io_out_gpio_3; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_2_auto_clock_in_clock; // @[PWM.scala 134:43]
  wire  pwmClockDomainWrapper_2_auto_clock_in_reset; // @[PWM.scala 134:43]
  wire  intsink_16_auto_in_sync_0; // @[Crossing.scala 94:29]
  wire  intsink_16_auto_in_sync_1; // @[Crossing.scala 94:29]
  wire  intsink_16_auto_in_sync_2; // @[Crossing.scala 94:29]
  wire  intsink_16_auto_in_sync_3; // @[Crossing.scala 94:29]
  wire  intsink_16_auto_out_0; // @[Crossing.scala 94:29]
  wire  intsink_16_auto_out_1; // @[Crossing.scala 94:29]
  wire  intsink_16_auto_out_2; // @[Crossing.scala 94:29]
  wire  intsink_16_auto_out_3; // @[Crossing.scala 94:29]
  wire  i2cClockDomainWrapper_auto_i2c_0_int_xing_out_sync_0; // @[I2C.scala 596:43]
  wire  i2cClockDomainWrapper_auto_i2c_0_control_xing_in_a_ready; // @[I2C.scala 596:43]
  wire  i2cClockDomainWrapper_auto_i2c_0_control_xing_in_a_valid; // @[I2C.scala 596:43]
  wire [2:0] i2cClockDomainWrapper_auto_i2c_0_control_xing_in_a_bits_opcode; // @[I2C.scala 596:43]
  wire [2:0] i2cClockDomainWrapper_auto_i2c_0_control_xing_in_a_bits_param; // @[I2C.scala 596:43]
  wire [1:0] i2cClockDomainWrapper_auto_i2c_0_control_xing_in_a_bits_size; // @[I2C.scala 596:43]
  wire [6:0] i2cClockDomainWrapper_auto_i2c_0_control_xing_in_a_bits_source; // @[I2C.scala 596:43]
  wire [28:0] i2cClockDomainWrapper_auto_i2c_0_control_xing_in_a_bits_address; // @[I2C.scala 596:43]
  wire [3:0] i2cClockDomainWrapper_auto_i2c_0_control_xing_in_a_bits_mask; // @[I2C.scala 596:43]
  wire [31:0] i2cClockDomainWrapper_auto_i2c_0_control_xing_in_a_bits_data; // @[I2C.scala 596:43]
  wire  i2cClockDomainWrapper_auto_i2c_0_control_xing_in_a_bits_corrupt; // @[I2C.scala 596:43]
  wire  i2cClockDomainWrapper_auto_i2c_0_control_xing_in_d_ready; // @[I2C.scala 596:43]
  wire  i2cClockDomainWrapper_auto_i2c_0_control_xing_in_d_valid; // @[I2C.scala 596:43]
  wire [2:0] i2cClockDomainWrapper_auto_i2c_0_control_xing_in_d_bits_opcode; // @[I2C.scala 596:43]
  wire [1:0] i2cClockDomainWrapper_auto_i2c_0_control_xing_in_d_bits_size; // @[I2C.scala 596:43]
  wire [6:0] i2cClockDomainWrapper_auto_i2c_0_control_xing_in_d_bits_source; // @[I2C.scala 596:43]
  wire [31:0] i2cClockDomainWrapper_auto_i2c_0_control_xing_in_d_bits_data; // @[I2C.scala 596:43]
  wire  i2cClockDomainWrapper_auto_i2c_0_io_out_scl_in; // @[I2C.scala 596:43]
  wire  i2cClockDomainWrapper_auto_i2c_0_io_out_scl_oe; // @[I2C.scala 596:43]
  wire  i2cClockDomainWrapper_auto_i2c_0_io_out_sda_in; // @[I2C.scala 596:43]
  wire  i2cClockDomainWrapper_auto_i2c_0_io_out_sda_oe; // @[I2C.scala 596:43]
  wire  i2cClockDomainWrapper_auto_clock_in_clock; // @[I2C.scala 596:43]
  wire  i2cClockDomainWrapper_auto_clock_in_reset; // @[I2C.scala 596:43]
  wire  intsink_17_auto_in_sync_0; // @[Crossing.scala 94:29]
  wire  intsink_17_auto_out_0; // @[Crossing.scala 94:29]
  wire  i2cClockDomainWrapper_1_auto_i2c_1_int_xing_out_sync_0; // @[I2C.scala 596:43]
  wire  i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_a_ready; // @[I2C.scala 596:43]
  wire  i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_a_valid; // @[I2C.scala 596:43]
  wire [2:0] i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_a_bits_opcode; // @[I2C.scala 596:43]
  wire [2:0] i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_a_bits_param; // @[I2C.scala 596:43]
  wire [1:0] i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_a_bits_size; // @[I2C.scala 596:43]
  wire [6:0] i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_a_bits_source; // @[I2C.scala 596:43]
  wire [28:0] i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_a_bits_address; // @[I2C.scala 596:43]
  wire [3:0] i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_a_bits_mask; // @[I2C.scala 596:43]
  wire [31:0] i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_a_bits_data; // @[I2C.scala 596:43]
  wire  i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_a_bits_corrupt; // @[I2C.scala 596:43]
  wire  i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_d_ready; // @[I2C.scala 596:43]
  wire  i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_d_valid; // @[I2C.scala 596:43]
  wire [2:0] i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_d_bits_opcode; // @[I2C.scala 596:43]
  wire [1:0] i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_d_bits_size; // @[I2C.scala 596:43]
  wire [6:0] i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_d_bits_source; // @[I2C.scala 596:43]
  wire [31:0] i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_d_bits_data; // @[I2C.scala 596:43]
  wire  i2cClockDomainWrapper_1_auto_i2c_1_io_out_scl_in; // @[I2C.scala 596:43]
  wire  i2cClockDomainWrapper_1_auto_i2c_1_io_out_scl_oe; // @[I2C.scala 596:43]
  wire  i2cClockDomainWrapper_1_auto_i2c_1_io_out_sda_in; // @[I2C.scala 596:43]
  wire  i2cClockDomainWrapper_1_auto_i2c_1_io_out_sda_oe; // @[I2C.scala 596:43]
  wire  i2cClockDomainWrapper_1_auto_clock_in_clock; // @[I2C.scala 596:43]
  wire  i2cClockDomainWrapper_1_auto_clock_in_reset; // @[I2C.scala 596:43]
  wire  intsink_18_auto_in_sync_0; // @[Crossing.scala 94:29]
  wire  intsink_18_auto_out_0; // @[Crossing.scala 94:29]
  wire  bootROMDomainWrapper_auto_bootrom_in_a_ready; // @[BootROM.scala 70:42]
  wire  bootROMDomainWrapper_auto_bootrom_in_a_valid; // @[BootROM.scala 70:42]
  wire [2:0] bootROMDomainWrapper_auto_bootrom_in_a_bits_opcode; // @[BootROM.scala 70:42]
  wire [2:0] bootROMDomainWrapper_auto_bootrom_in_a_bits_param; // @[BootROM.scala 70:42]
  wire [1:0] bootROMDomainWrapper_auto_bootrom_in_a_bits_size; // @[BootROM.scala 70:42]
  wire [6:0] bootROMDomainWrapper_auto_bootrom_in_a_bits_source; // @[BootROM.scala 70:42]
  wire [16:0] bootROMDomainWrapper_auto_bootrom_in_a_bits_address; // @[BootROM.scala 70:42]
  wire [3:0] bootROMDomainWrapper_auto_bootrom_in_a_bits_mask; // @[BootROM.scala 70:42]
  wire  bootROMDomainWrapper_auto_bootrom_in_a_bits_corrupt; // @[BootROM.scala 70:42]
  wire  bootROMDomainWrapper_auto_bootrom_in_d_ready; // @[BootROM.scala 70:42]
  wire  bootROMDomainWrapper_auto_bootrom_in_d_valid; // @[BootROM.scala 70:42]
  wire [1:0] bootROMDomainWrapper_auto_bootrom_in_d_bits_size; // @[BootROM.scala 70:42]
  wire [6:0] bootROMDomainWrapper_auto_bootrom_in_d_bits_source; // @[BootROM.scala 70:42]
  wire [31:0] bootROMDomainWrapper_auto_bootrom_in_d_bits_data; // @[BootROM.scala 70:42]
  wire  bootROMDomainWrapper_auto_clock_in_clock; // @[BootROM.scala 70:42]
  wire  bootROMDomainWrapper_auto_clock_in_reset; // @[BootROM.scala 70:42]
  wire  dtm_io_jtag_clock; // @[Periphery.scala 161:21]
  wire  dtm_io_jtag_reset; // @[Periphery.scala 161:21]
  wire  dtm_io_dmi_req_ready; // @[Periphery.scala 161:21]
  wire  dtm_io_dmi_req_valid; // @[Periphery.scala 161:21]
  wire [6:0] dtm_io_dmi_req_bits_addr; // @[Periphery.scala 161:21]
  wire [31:0] dtm_io_dmi_req_bits_data; // @[Periphery.scala 161:21]
  wire [1:0] dtm_io_dmi_req_bits_op; // @[Periphery.scala 161:21]
  wire  dtm_io_dmi_resp_ready; // @[Periphery.scala 161:21]
  wire  dtm_io_dmi_resp_valid; // @[Periphery.scala 161:21]
  wire [31:0] dtm_io_dmi_resp_bits_data; // @[Periphery.scala 161:21]
  wire [1:0] dtm_io_dmi_resp_bits_resp; // @[Periphery.scala 161:21]
  wire  dtm_io_jtag_TMS; // @[Periphery.scala 161:21]
  wire  dtm_io_jtag_TDI; // @[Periphery.scala 161:21]
  wire  dtm_io_jtag_TDO_data; // @[Periphery.scala 161:21]
  wire  dtm_io_jtag_TDO_driven; // @[Periphery.scala 161:21]
  wire  rtc_sync_rtc_clock; // @[ShiftReg.scala 45:23]
  wire  rtc_sync_rtc_io_d; // @[ShiftReg.scala 45:23]
  wire  rtc_sync_rtc_io_q; // @[ShiftReg.scala 45:23]
  reg  rtc_last; // @[MockAONPeriphery.scala 46:21]
  wire  rtc_sync = rtc_sync_rtc_io_q; // @[ShiftReg.scala 48:{24,24}]
  wire  rtc_tick_x2 = rtc_sync & ~rtc_last; // @[MockAONPeriphery.scala 47:57]
  reg  rtc_tick; // @[MockAONPeriphery.scala 47:21]
  InterruptBusWrapper ibus ( // @[BaseSubsystem.scala 50:24]
    .auto_int_bus_int_in_14_0(ibus_auto_int_bus_int_in_14_0),
    .auto_int_bus_int_in_13_0(ibus_auto_int_bus_int_in_13_0),
    .auto_int_bus_int_in_12_0(ibus_auto_int_bus_int_in_12_0),
    .auto_int_bus_int_in_12_1(ibus_auto_int_bus_int_in_12_1),
    .auto_int_bus_int_in_12_2(ibus_auto_int_bus_int_in_12_2),
    .auto_int_bus_int_in_12_3(ibus_auto_int_bus_int_in_12_3),
    .auto_int_bus_int_in_11_0(ibus_auto_int_bus_int_in_11_0),
    .auto_int_bus_int_in_11_1(ibus_auto_int_bus_int_in_11_1),
    .auto_int_bus_int_in_11_2(ibus_auto_int_bus_int_in_11_2),
    .auto_int_bus_int_in_11_3(ibus_auto_int_bus_int_in_11_3),
    .auto_int_bus_int_in_10_0(ibus_auto_int_bus_int_in_10_0),
    .auto_int_bus_int_in_10_1(ibus_auto_int_bus_int_in_10_1),
    .auto_int_bus_int_in_10_2(ibus_auto_int_bus_int_in_10_2),
    .auto_int_bus_int_in_10_3(ibus_auto_int_bus_int_in_10_3),
    .auto_int_bus_int_in_9_0(ibus_auto_int_bus_int_in_9_0),
    .auto_int_bus_int_in_9_1(ibus_auto_int_bus_int_in_9_1),
    .auto_int_bus_int_in_9_2(ibus_auto_int_bus_int_in_9_2),
    .auto_int_bus_int_in_9_3(ibus_auto_int_bus_int_in_9_3),
    .auto_int_bus_int_in_9_4(ibus_auto_int_bus_int_in_9_4),
    .auto_int_bus_int_in_9_5(ibus_auto_int_bus_int_in_9_5),
    .auto_int_bus_int_in_9_6(ibus_auto_int_bus_int_in_9_6),
    .auto_int_bus_int_in_9_7(ibus_auto_int_bus_int_in_9_7),
    .auto_int_bus_int_in_9_8(ibus_auto_int_bus_int_in_9_8),
    .auto_int_bus_int_in_9_9(ibus_auto_int_bus_int_in_9_9),
    .auto_int_bus_int_in_9_10(ibus_auto_int_bus_int_in_9_10),
    .auto_int_bus_int_in_9_11(ibus_auto_int_bus_int_in_9_11),
    .auto_int_bus_int_in_9_12(ibus_auto_int_bus_int_in_9_12),
    .auto_int_bus_int_in_9_13(ibus_auto_int_bus_int_in_9_13),
    .auto_int_bus_int_in_9_14(ibus_auto_int_bus_int_in_9_14),
    .auto_int_bus_int_in_9_15(ibus_auto_int_bus_int_in_9_15),
    .auto_int_bus_int_in_9_16(ibus_auto_int_bus_int_in_9_16),
    .auto_int_bus_int_in_9_17(ibus_auto_int_bus_int_in_9_17),
    .auto_int_bus_int_in_9_18(ibus_auto_int_bus_int_in_9_18),
    .auto_int_bus_int_in_9_19(ibus_auto_int_bus_int_in_9_19),
    .auto_int_bus_int_in_9_20(ibus_auto_int_bus_int_in_9_20),
    .auto_int_bus_int_in_9_21(ibus_auto_int_bus_int_in_9_21),
    .auto_int_bus_int_in_9_22(ibus_auto_int_bus_int_in_9_22),
    .auto_int_bus_int_in_9_23(ibus_auto_int_bus_int_in_9_23),
    .auto_int_bus_int_in_9_24(ibus_auto_int_bus_int_in_9_24),
    .auto_int_bus_int_in_9_25(ibus_auto_int_bus_int_in_9_25),
    .auto_int_bus_int_in_9_26(ibus_auto_int_bus_int_in_9_26),
    .auto_int_bus_int_in_9_27(ibus_auto_int_bus_int_in_9_27),
    .auto_int_bus_int_in_9_28(ibus_auto_int_bus_int_in_9_28),
    .auto_int_bus_int_in_9_29(ibus_auto_int_bus_int_in_9_29),
    .auto_int_bus_int_in_9_30(ibus_auto_int_bus_int_in_9_30),
    .auto_int_bus_int_in_9_31(ibus_auto_int_bus_int_in_9_31),
    .auto_int_bus_int_in_8_0(ibus_auto_int_bus_int_in_8_0),
    .auto_int_bus_int_in_7_0(ibus_auto_int_bus_int_in_7_0),
    .auto_int_bus_int_in_6_0(ibus_auto_int_bus_int_in_6_0),
    .auto_int_bus_int_in_5_0(ibus_auto_int_bus_int_in_5_0),
    .auto_int_bus_int_in_4_0(ibus_auto_int_bus_int_in_4_0),
    .auto_int_bus_int_in_3_0(ibus_auto_int_bus_int_in_3_0),
    .auto_int_bus_int_in_2_0(ibus_auto_int_bus_int_in_2_0),
    .auto_int_bus_int_in_1_0(ibus_auto_int_bus_int_in_1_0),
    .auto_int_bus_int_in_0_0(ibus_auto_int_bus_int_in_0_0),
    .auto_int_bus_int_in_0_1(ibus_auto_int_bus_int_in_0_1),
    .auto_int_bus_int_out_0(ibus_auto_int_bus_int_out_0),
    .auto_int_bus_int_out_1(ibus_auto_int_bus_int_out_1),
    .auto_int_bus_int_out_2(ibus_auto_int_bus_int_out_2),
    .auto_int_bus_int_out_3(ibus_auto_int_bus_int_out_3),
    .auto_int_bus_int_out_4(ibus_auto_int_bus_int_out_4),
    .auto_int_bus_int_out_5(ibus_auto_int_bus_int_out_5),
    .auto_int_bus_int_out_6(ibus_auto_int_bus_int_out_6),
    .auto_int_bus_int_out_7(ibus_auto_int_bus_int_out_7),
    .auto_int_bus_int_out_8(ibus_auto_int_bus_int_out_8),
    .auto_int_bus_int_out_9(ibus_auto_int_bus_int_out_9),
    .auto_int_bus_int_out_10(ibus_auto_int_bus_int_out_10),
    .auto_int_bus_int_out_11(ibus_auto_int_bus_int_out_11),
    .auto_int_bus_int_out_12(ibus_auto_int_bus_int_out_12),
    .auto_int_bus_int_out_13(ibus_auto_int_bus_int_out_13),
    .auto_int_bus_int_out_14(ibus_auto_int_bus_int_out_14),
    .auto_int_bus_int_out_15(ibus_auto_int_bus_int_out_15),
    .auto_int_bus_int_out_16(ibus_auto_int_bus_int_out_16),
    .auto_int_bus_int_out_17(ibus_auto_int_bus_int_out_17),
    .auto_int_bus_int_out_18(ibus_auto_int_bus_int_out_18),
    .auto_int_bus_int_out_19(ibus_auto_int_bus_int_out_19),
    .auto_int_bus_int_out_20(ibus_auto_int_bus_int_out_20),
    .auto_int_bus_int_out_21(ibus_auto_int_bus_int_out_21),
    .auto_int_bus_int_out_22(ibus_auto_int_bus_int_out_22),
    .auto_int_bus_int_out_23(ibus_auto_int_bus_int_out_23),
    .auto_int_bus_int_out_24(ibus_auto_int_bus_int_out_24),
    .auto_int_bus_int_out_25(ibus_auto_int_bus_int_out_25),
    .auto_int_bus_int_out_26(ibus_auto_int_bus_int_out_26),
    .auto_int_bus_int_out_27(ibus_auto_int_bus_int_out_27),
    .auto_int_bus_int_out_28(ibus_auto_int_bus_int_out_28),
    .auto_int_bus_int_out_29(ibus_auto_int_bus_int_out_29),
    .auto_int_bus_int_out_30(ibus_auto_int_bus_int_out_30),
    .auto_int_bus_int_out_31(ibus_auto_int_bus_int_out_31),
    .auto_int_bus_int_out_32(ibus_auto_int_bus_int_out_32),
    .auto_int_bus_int_out_33(ibus_auto_int_bus_int_out_33),
    .auto_int_bus_int_out_34(ibus_auto_int_bus_int_out_34),
    .auto_int_bus_int_out_35(ibus_auto_int_bus_int_out_35),
    .auto_int_bus_int_out_36(ibus_auto_int_bus_int_out_36),
    .auto_int_bus_int_out_37(ibus_auto_int_bus_int_out_37),
    .auto_int_bus_int_out_38(ibus_auto_int_bus_int_out_38),
    .auto_int_bus_int_out_39(ibus_auto_int_bus_int_out_39),
    .auto_int_bus_int_out_40(ibus_auto_int_bus_int_out_40),
    .auto_int_bus_int_out_41(ibus_auto_int_bus_int_out_41),
    .auto_int_bus_int_out_42(ibus_auto_int_bus_int_out_42),
    .auto_int_bus_int_out_43(ibus_auto_int_bus_int_out_43),
    .auto_int_bus_int_out_44(ibus_auto_int_bus_int_out_44),
    .auto_int_bus_int_out_45(ibus_auto_int_bus_int_out_45),
    .auto_int_bus_int_out_46(ibus_auto_int_bus_int_out_46),
    .auto_int_bus_int_out_47(ibus_auto_int_bus_int_out_47),
    .auto_int_bus_int_out_48(ibus_auto_int_bus_int_out_48),
    .auto_int_bus_int_out_49(ibus_auto_int_bus_int_out_49),
    .auto_int_bus_int_out_50(ibus_auto_int_bus_int_out_50),
    .auto_int_bus_int_out_51(ibus_auto_int_bus_int_out_51),
    .auto_int_bus_int_out_52(ibus_auto_int_bus_int_out_52),
    .auto_int_bus_int_out_53(ibus_auto_int_bus_int_out_53),
    .auto_int_bus_int_out_54(ibus_auto_int_bus_int_out_54),
    .auto_int_bus_int_out_55(ibus_auto_int_bus_int_out_55)
  );
  SimpleClockGroupSource dummyClockGroupSourceNode ( // @[ClockGroup.scala 79:81]
    .clock(dummyClockGroupSourceNode_clock),
    .reset(dummyClockGroupSourceNode_reset),
    .auto_out_member_subsystem_sbus_5_clock(dummyClockGroupSourceNode_auto_out_member_subsystem_sbus_5_clock),
    .auto_out_member_subsystem_sbus_5_reset(dummyClockGroupSourceNode_auto_out_member_subsystem_sbus_5_reset),
    .auto_out_member_subsystem_sbus_4_clock(dummyClockGroupSourceNode_auto_out_member_subsystem_sbus_4_clock),
    .auto_out_member_subsystem_sbus_4_reset(dummyClockGroupSourceNode_auto_out_member_subsystem_sbus_4_reset),
    .auto_out_member_subsystem_sbus_3_clock(dummyClockGroupSourceNode_auto_out_member_subsystem_sbus_3_clock),
    .auto_out_member_subsystem_sbus_3_reset(dummyClockGroupSourceNode_auto_out_member_subsystem_sbus_3_reset),
    .auto_out_member_subsystem_sbus_2_clock(dummyClockGroupSourceNode_auto_out_member_subsystem_sbus_2_clock),
    .auto_out_member_subsystem_sbus_2_reset(dummyClockGroupSourceNode_auto_out_member_subsystem_sbus_2_reset),
    .auto_out_member_subsystem_sbus_1_clock(dummyClockGroupSourceNode_auto_out_member_subsystem_sbus_1_clock),
    .auto_out_member_subsystem_sbus_1_reset(dummyClockGroupSourceNode_auto_out_member_subsystem_sbus_1_reset),
    .auto_out_member_subsystem_sbus_0_clock(dummyClockGroupSourceNode_auto_out_member_subsystem_sbus_0_clock),
    .auto_out_member_subsystem_sbus_0_reset(dummyClockGroupSourceNode_auto_out_member_subsystem_sbus_0_reset)
  );
  SystemBus subsystem_sbus ( // @[SystemBus.scala 24:26]
    .auto_coupler_from_tile_tl_master_clock_xing_in_a_ready(
      subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_ready),
    .auto_coupler_from_tile_tl_master_clock_xing_in_a_valid(
      subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_valid),
    .auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_opcode(
      subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_opcode),
    .auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_param(
      subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_param),
    .auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_size(
      subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_size),
    .auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_source(
      subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_source),
    .auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_address(
      subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_address),
    .auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_mask(
      subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_mask),
    .auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_data(
      subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_data),
    .auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_corrupt(
      subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_corrupt),
    .auto_coupler_from_tile_tl_master_clock_xing_in_b_ready(
      subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_b_ready),
    .auto_coupler_from_tile_tl_master_clock_xing_in_b_valid(
      subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_b_valid),
    .auto_coupler_from_tile_tl_master_clock_xing_in_b_bits_param(
      subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_b_bits_param),
    .auto_coupler_from_tile_tl_master_clock_xing_in_b_bits_address(
      subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_b_bits_address),
    .auto_coupler_from_tile_tl_master_clock_xing_in_c_ready(
      subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_c_ready),
    .auto_coupler_from_tile_tl_master_clock_xing_in_c_valid(
      subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_c_valid),
    .auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_opcode(
      subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_opcode),
    .auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_param(
      subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_param),
    .auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_size(
      subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_size),
    .auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_source(
      subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_source),
    .auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_address(
      subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_address),
    .auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_data(
      subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_data),
    .auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_corrupt(
      subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_corrupt),
    .auto_coupler_from_tile_tl_master_clock_xing_in_d_ready(
      subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_ready),
    .auto_coupler_from_tile_tl_master_clock_xing_in_d_valid(
      subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_valid),
    .auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_opcode(
      subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_opcode),
    .auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_param(
      subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_param),
    .auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_size(
      subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_size),
    .auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_source(
      subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_source),
    .auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_sink(
      subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_sink),
    .auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_denied(
      subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_denied),
    .auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_data(
      subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_data),
    .auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_corrupt(
      subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_corrupt),
    .auto_coupler_from_tile_tl_master_clock_xing_in_e_valid(
      subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_e_valid),
    .auto_coupler_from_tile_tl_master_clock_xing_in_e_bits_sink(
      subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_e_bits_sink),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_a_ready(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_ready),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_a_valid(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_valid),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_opcode(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_opcode),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_param(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_param),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_size(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_size),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_source(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_source),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_address(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_address),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_mask(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_mask),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_data(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_data),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_corrupt(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_corrupt),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_b_ready(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_b_ready),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_b_valid(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_b_valid),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_b_bits_param(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_b_bits_param),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_b_bits_address(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_b_bits_address),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_c_ready(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_ready),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_c_valid(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_valid),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_opcode(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_opcode),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_param(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_param),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_size(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_size),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_source(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_source),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_address(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_address),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_data(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_data),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_corrupt(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_corrupt),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_d_ready(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_d_ready),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_d_valid(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_d_valid),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_opcode(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_opcode),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_param(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_param),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_size(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_size),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_source(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_source),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_sink(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_sink),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_data(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_data),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_e_valid(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_e_valid),
    .auto_coupler_to_bus_named_subsystem_l2_widget_out_e_bits_sink(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_e_bits_sink),
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_ready(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_ready),
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_valid(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_valid),
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_opcode(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_opcode),
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_param(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_param),
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_size(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_size),
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_source(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_source),
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_address(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_address),
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_mask(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_mask),
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_data(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_data),
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_corrupt(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_corrupt),
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_ready(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_ready),
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_valid(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_valid),
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_opcode(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_opcode),
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_param(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_param),
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_size(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_size),
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_source(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_source),
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_sink(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_sink),
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_denied(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_denied),
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_data(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_data),
    .auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_corrupt(
      subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_corrupt),
    .auto_fixedClockNode_out_1_clock(subsystem_sbus_auto_fixedClockNode_out_1_clock),
    .auto_fixedClockNode_out_1_reset(subsystem_sbus_auto_fixedClockNode_out_1_reset),
    .auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_5_clock(
      subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_5_clock),
    .auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_5_reset(
      subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_5_reset),
    .auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_4_clock(
      subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_4_clock),
    .auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_4_reset(
      subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_4_reset),
    .auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_3_clock(
      subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_3_clock),
    .auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_3_reset(
      subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_3_reset),
    .auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_2_clock(
      subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_2_clock),
    .auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_2_reset(
      subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_2_reset),
    .auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_1_clock(
      subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_1_clock),
    .auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_1_reset(
      subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_1_reset),
    .auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_0_clock(
      subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_0_clock),
    .auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_0_reset(
      subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_0_reset),
    .auto_subsystem_sbus_clock_groups_out_2_member_subsystem_l2_1_clock(
      subsystem_sbus_auto_subsystem_sbus_clock_groups_out_2_member_subsystem_l2_1_clock),
    .auto_subsystem_sbus_clock_groups_out_2_member_subsystem_l2_1_reset(
      subsystem_sbus_auto_subsystem_sbus_clock_groups_out_2_member_subsystem_l2_1_reset),
    .auto_subsystem_sbus_clock_groups_out_2_member_subsystem_l2_0_clock(
      subsystem_sbus_auto_subsystem_sbus_clock_groups_out_2_member_subsystem_l2_0_clock),
    .auto_subsystem_sbus_clock_groups_out_2_member_subsystem_l2_0_reset(
      subsystem_sbus_auto_subsystem_sbus_clock_groups_out_2_member_subsystem_l2_0_reset),
    .auto_subsystem_sbus_clock_groups_out_1_member_subsystem_fbus_0_clock(
      subsystem_sbus_auto_subsystem_sbus_clock_groups_out_1_member_subsystem_fbus_0_clock),
    .auto_subsystem_sbus_clock_groups_out_1_member_subsystem_fbus_0_reset(
      subsystem_sbus_auto_subsystem_sbus_clock_groups_out_1_member_subsystem_fbus_0_reset),
    .auto_subsystem_sbus_clock_groups_out_0_member_subsystem_cbus_1_clock(
      subsystem_sbus_auto_subsystem_sbus_clock_groups_out_0_member_subsystem_cbus_1_clock),
    .auto_subsystem_sbus_clock_groups_out_0_member_subsystem_cbus_1_reset(
      subsystem_sbus_auto_subsystem_sbus_clock_groups_out_0_member_subsystem_cbus_1_reset),
    .auto_subsystem_sbus_clock_groups_out_0_member_subsystem_cbus_0_clock(
      subsystem_sbus_auto_subsystem_sbus_clock_groups_out_0_member_subsystem_cbus_0_clock),
    .auto_subsystem_sbus_clock_groups_out_0_member_subsystem_cbus_0_reset(
      subsystem_sbus_auto_subsystem_sbus_clock_groups_out_0_member_subsystem_cbus_0_reset)
  );
  PeripheryBus subsystem_pbus ( // @[PeripheryBus.scala 31:26]
    .auto_coupler_to_device_named_i2c_1_control_xing_out_a_ready(
      subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_a_ready),
    .auto_coupler_to_device_named_i2c_1_control_xing_out_a_valid(
      subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_a_valid),
    .auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_opcode(
      subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_opcode),
    .auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_param(
      subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_param),
    .auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_size(
      subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_size),
    .auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_source(
      subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_source),
    .auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_address(
      subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_address),
    .auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_mask(
      subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_mask),
    .auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_data(
      subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_data),
    .auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_corrupt(
      subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_corrupt),
    .auto_coupler_to_device_named_i2c_1_control_xing_out_d_ready(
      subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_d_ready),
    .auto_coupler_to_device_named_i2c_1_control_xing_out_d_valid(
      subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_d_valid),
    .auto_coupler_to_device_named_i2c_1_control_xing_out_d_bits_opcode(
      subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_d_bits_opcode),
    .auto_coupler_to_device_named_i2c_1_control_xing_out_d_bits_size(
      subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_d_bits_size),
    .auto_coupler_to_device_named_i2c_1_control_xing_out_d_bits_source(
      subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_d_bits_source),
    .auto_coupler_to_device_named_i2c_1_control_xing_out_d_bits_data(
      subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_d_bits_data),
    .auto_coupler_to_device_named_i2c_0_control_xing_out_a_ready(
      subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_a_ready),
    .auto_coupler_to_device_named_i2c_0_control_xing_out_a_valid(
      subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_a_valid),
    .auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_opcode(
      subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_opcode),
    .auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_param(
      subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_param),
    .auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_size(
      subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_size),
    .auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_source(
      subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_source),
    .auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_address(
      subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_address),
    .auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_mask(
      subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_mask),
    .auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_data(
      subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_data),
    .auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_corrupt(
      subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_corrupt),
    .auto_coupler_to_device_named_i2c_0_control_xing_out_d_ready(
      subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_d_ready),
    .auto_coupler_to_device_named_i2c_0_control_xing_out_d_valid(
      subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_d_valid),
    .auto_coupler_to_device_named_i2c_0_control_xing_out_d_bits_opcode(
      subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_d_bits_opcode),
    .auto_coupler_to_device_named_i2c_0_control_xing_out_d_bits_size(
      subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_d_bits_size),
    .auto_coupler_to_device_named_i2c_0_control_xing_out_d_bits_source(
      subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_d_bits_source),
    .auto_coupler_to_device_named_i2c_0_control_xing_out_d_bits_data(
      subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_d_bits_data),
    .auto_coupler_to_device_named_pwm_2_control_xing_out_a_ready(
      subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_a_ready),
    .auto_coupler_to_device_named_pwm_2_control_xing_out_a_valid(
      subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_a_valid),
    .auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_opcode(
      subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_opcode),
    .auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_param(
      subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_param),
    .auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_size(
      subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_size),
    .auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_source(
      subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_source),
    .auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_address(
      subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_address),
    .auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_mask(
      subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_mask),
    .auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_data(
      subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_data),
    .auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_corrupt(
      subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_corrupt),
    .auto_coupler_to_device_named_pwm_2_control_xing_out_d_ready(
      subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_d_ready),
    .auto_coupler_to_device_named_pwm_2_control_xing_out_d_valid(
      subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_d_valid),
    .auto_coupler_to_device_named_pwm_2_control_xing_out_d_bits_opcode(
      subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_d_bits_opcode),
    .auto_coupler_to_device_named_pwm_2_control_xing_out_d_bits_size(
      subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_d_bits_size),
    .auto_coupler_to_device_named_pwm_2_control_xing_out_d_bits_source(
      subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_d_bits_source),
    .auto_coupler_to_device_named_pwm_2_control_xing_out_d_bits_data(
      subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_d_bits_data),
    .auto_coupler_to_device_named_pwm_1_control_xing_out_a_ready(
      subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_a_ready),
    .auto_coupler_to_device_named_pwm_1_control_xing_out_a_valid(
      subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_a_valid),
    .auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_opcode(
      subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_opcode),
    .auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_param(
      subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_param),
    .auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_size(
      subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_size),
    .auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_source(
      subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_source),
    .auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_address(
      subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_address),
    .auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_mask(
      subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_mask),
    .auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_data(
      subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_data),
    .auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_corrupt(
      subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_corrupt),
    .auto_coupler_to_device_named_pwm_1_control_xing_out_d_ready(
      subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_d_ready),
    .auto_coupler_to_device_named_pwm_1_control_xing_out_d_valid(
      subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_d_valid),
    .auto_coupler_to_device_named_pwm_1_control_xing_out_d_bits_opcode(
      subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_d_bits_opcode),
    .auto_coupler_to_device_named_pwm_1_control_xing_out_d_bits_size(
      subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_d_bits_size),
    .auto_coupler_to_device_named_pwm_1_control_xing_out_d_bits_source(
      subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_d_bits_source),
    .auto_coupler_to_device_named_pwm_1_control_xing_out_d_bits_data(
      subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_d_bits_data),
    .auto_coupler_to_device_named_pwm_0_control_xing_out_a_ready(
      subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_a_ready),
    .auto_coupler_to_device_named_pwm_0_control_xing_out_a_valid(
      subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_a_valid),
    .auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_opcode(
      subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_opcode),
    .auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_param(
      subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_param),
    .auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_size(
      subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_size),
    .auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_source(
      subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_source),
    .auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_address(
      subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_address),
    .auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_mask(
      subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_mask),
    .auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_data(
      subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_data),
    .auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_corrupt(
      subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_corrupt),
    .auto_coupler_to_device_named_pwm_0_control_xing_out_d_ready(
      subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_d_ready),
    .auto_coupler_to_device_named_pwm_0_control_xing_out_d_valid(
      subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_d_valid),
    .auto_coupler_to_device_named_pwm_0_control_xing_out_d_bits_opcode(
      subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_d_bits_opcode),
    .auto_coupler_to_device_named_pwm_0_control_xing_out_d_bits_size(
      subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_d_bits_size),
    .auto_coupler_to_device_named_pwm_0_control_xing_out_d_bits_source(
      subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_d_bits_source),
    .auto_coupler_to_device_named_pwm_0_control_xing_out_d_bits_data(
      subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_d_bits_data),
    .auto_coupler_to_device_named_gpio_0_control_xing_out_a_ready(
      subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_ready),
    .auto_coupler_to_device_named_gpio_0_control_xing_out_a_valid(
      subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_valid),
    .auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_opcode(
      subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_opcode),
    .auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_param(
      subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_param),
    .auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_size(
      subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_size),
    .auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_source(
      subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_source),
    .auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_address(
      subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_address),
    .auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_mask(
      subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_mask),
    .auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_data(
      subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_data),
    .auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_corrupt(
      subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_corrupt),
    .auto_coupler_to_device_named_gpio_0_control_xing_out_d_ready(
      subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_d_ready),
    .auto_coupler_to_device_named_gpio_0_control_xing_out_d_valid(
      subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_d_valid),
    .auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_opcode(
      subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_opcode),
    .auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_size(
      subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_size),
    .auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_source(
      subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_source),
    .auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_data(
      subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_data),
    .auto_coupler_to_device_named_spi_0_control_xing_out_a_ready(
      subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_a_ready),
    .auto_coupler_to_device_named_spi_0_control_xing_out_a_valid(
      subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_a_valid),
    .auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_opcode(
      subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_opcode),
    .auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_param(
      subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_param),
    .auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_size(
      subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_size),
    .auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_source(
      subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_source),
    .auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_address(
      subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_address),
    .auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_mask(
      subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_mask),
    .auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_data(
      subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_data),
    .auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_corrupt(
      subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_corrupt),
    .auto_coupler_to_device_named_spi_0_control_xing_out_d_ready(
      subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_d_ready),
    .auto_coupler_to_device_named_spi_0_control_xing_out_d_valid(
      subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_d_valid),
    .auto_coupler_to_device_named_spi_0_control_xing_out_d_bits_opcode(
      subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_d_bits_opcode),
    .auto_coupler_to_device_named_spi_0_control_xing_out_d_bits_size(
      subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_d_bits_size),
    .auto_coupler_to_device_named_spi_0_control_xing_out_d_bits_source(
      subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_d_bits_source),
    .auto_coupler_to_device_named_spi_0_control_xing_out_d_bits_data(
      subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_d_bits_data),
    .auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_ready(
      subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_ready),
    .auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_valid(
      subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_valid),
    .auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_opcode(
      subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_opcode),
    .auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_param(
      subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_param),
    .auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_size(
      subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_size),
    .auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_source(
      subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_source),
    .auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_address(
      subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_address),
    .auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_mask(
      subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_mask),
    .auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_data(
      subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_data),
    .auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_corrupt(
      subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_corrupt),
    .auto_coupler_to_device_named_qspi_ram_0_control_xing_out_d_ready(
      subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_d_ready),
    .auto_coupler_to_device_named_qspi_ram_0_control_xing_out_d_valid(
      subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_d_valid),
    .auto_coupler_to_device_named_qspi_ram_0_control_xing_out_d_bits_opcode(
      subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_d_bits_opcode),
    .auto_coupler_to_device_named_qspi_ram_0_control_xing_out_d_bits_size(
      subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_d_bits_size),
    .auto_coupler_to_device_named_qspi_ram_0_control_xing_out_d_bits_source(
      subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_d_bits_source),
    .auto_coupler_to_device_named_qspi_ram_0_control_xing_out_d_bits_data(
      subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_d_bits_data),
    .auto_coupler_to_device_named_qspi_0_mem_xing_out_a_ready(
      subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_ready),
    .auto_coupler_to_device_named_qspi_0_mem_xing_out_a_valid(
      subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_valid),
    .auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_opcode(
      subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_opcode),
    .auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_param(
      subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_param),
    .auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_size(
      subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_size),
    .auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_source(
      subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_source),
    .auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_address(
      subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_address),
    .auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_mask(
      subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_mask),
    .auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_corrupt(
      subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_corrupt),
    .auto_coupler_to_device_named_qspi_0_mem_xing_out_d_ready(
      subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_d_ready),
    .auto_coupler_to_device_named_qspi_0_mem_xing_out_d_valid(
      subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_d_valid),
    .auto_coupler_to_device_named_qspi_0_mem_xing_out_d_bits_size(
      subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_d_bits_size),
    .auto_coupler_to_device_named_qspi_0_mem_xing_out_d_bits_source(
      subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_d_bits_source),
    .auto_coupler_to_device_named_qspi_0_mem_xing_out_d_bits_data(
      subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_d_bits_data),
    .auto_coupler_to_device_named_qspi_0_control_xing_out_a_ready(
      subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_ready),
    .auto_coupler_to_device_named_qspi_0_control_xing_out_a_valid(
      subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_valid),
    .auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_opcode(
      subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_opcode),
    .auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_param(
      subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_param),
    .auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_size(
      subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_size),
    .auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_source(
      subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_source),
    .auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_address(
      subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_address),
    .auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_mask(
      subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_mask),
    .auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_data(
      subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_data),
    .auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_corrupt(
      subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_corrupt),
    .auto_coupler_to_device_named_qspi_0_control_xing_out_d_ready(
      subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_d_ready),
    .auto_coupler_to_device_named_qspi_0_control_xing_out_d_valid(
      subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_d_valid),
    .auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_opcode(
      subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_opcode),
    .auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_size(
      subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_size),
    .auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_source(
      subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_source),
    .auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_data(
      subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_data),
    .auto_coupler_to_device_named_uart_4_control_xing_out_a_ready(
      subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_a_ready),
    .auto_coupler_to_device_named_uart_4_control_xing_out_a_valid(
      subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_a_valid),
    .auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_opcode(
      subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_opcode),
    .auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_param(
      subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_param),
    .auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_size(
      subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_size),
    .auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_source(
      subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_source),
    .auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_address(
      subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_address),
    .auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_mask(
      subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_mask),
    .auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_data(
      subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_data),
    .auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_corrupt(
      subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_corrupt),
    .auto_coupler_to_device_named_uart_4_control_xing_out_d_ready(
      subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_d_ready),
    .auto_coupler_to_device_named_uart_4_control_xing_out_d_valid(
      subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_d_valid),
    .auto_coupler_to_device_named_uart_4_control_xing_out_d_bits_opcode(
      subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_d_bits_opcode),
    .auto_coupler_to_device_named_uart_4_control_xing_out_d_bits_size(
      subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_d_bits_size),
    .auto_coupler_to_device_named_uart_4_control_xing_out_d_bits_source(
      subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_d_bits_source),
    .auto_coupler_to_device_named_uart_4_control_xing_out_d_bits_data(
      subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_d_bits_data),
    .auto_coupler_to_device_named_uart_3_control_xing_out_a_ready(
      subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_a_ready),
    .auto_coupler_to_device_named_uart_3_control_xing_out_a_valid(
      subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_a_valid),
    .auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_opcode(
      subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_opcode),
    .auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_param(
      subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_param),
    .auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_size(
      subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_size),
    .auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_source(
      subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_source),
    .auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_address(
      subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_address),
    .auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_mask(
      subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_mask),
    .auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_data(
      subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_data),
    .auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_corrupt(
      subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_corrupt),
    .auto_coupler_to_device_named_uart_3_control_xing_out_d_ready(
      subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_d_ready),
    .auto_coupler_to_device_named_uart_3_control_xing_out_d_valid(
      subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_d_valid),
    .auto_coupler_to_device_named_uart_3_control_xing_out_d_bits_opcode(
      subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_d_bits_opcode),
    .auto_coupler_to_device_named_uart_3_control_xing_out_d_bits_size(
      subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_d_bits_size),
    .auto_coupler_to_device_named_uart_3_control_xing_out_d_bits_source(
      subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_d_bits_source),
    .auto_coupler_to_device_named_uart_3_control_xing_out_d_bits_data(
      subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_d_bits_data),
    .auto_coupler_to_device_named_uart_2_control_xing_out_a_ready(
      subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_a_ready),
    .auto_coupler_to_device_named_uart_2_control_xing_out_a_valid(
      subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_a_valid),
    .auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_opcode(
      subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_opcode),
    .auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_param(
      subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_param),
    .auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_size(
      subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_size),
    .auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_source(
      subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_source),
    .auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_address(
      subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_address),
    .auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_mask(
      subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_mask),
    .auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_data(
      subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_data),
    .auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_corrupt(
      subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_corrupt),
    .auto_coupler_to_device_named_uart_2_control_xing_out_d_ready(
      subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_d_ready),
    .auto_coupler_to_device_named_uart_2_control_xing_out_d_valid(
      subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_d_valid),
    .auto_coupler_to_device_named_uart_2_control_xing_out_d_bits_opcode(
      subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_d_bits_opcode),
    .auto_coupler_to_device_named_uart_2_control_xing_out_d_bits_size(
      subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_d_bits_size),
    .auto_coupler_to_device_named_uart_2_control_xing_out_d_bits_source(
      subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_d_bits_source),
    .auto_coupler_to_device_named_uart_2_control_xing_out_d_bits_data(
      subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_d_bits_data),
    .auto_coupler_to_device_named_uart_1_control_xing_out_a_ready(
      subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_ready),
    .auto_coupler_to_device_named_uart_1_control_xing_out_a_valid(
      subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_valid),
    .auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_opcode(
      subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_opcode),
    .auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_param(
      subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_param),
    .auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_size(
      subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_size),
    .auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_source(
      subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_source),
    .auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_address(
      subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_address),
    .auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_mask(
      subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_mask),
    .auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_data(
      subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_data),
    .auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_corrupt(
      subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_corrupt),
    .auto_coupler_to_device_named_uart_1_control_xing_out_d_ready(
      subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_d_ready),
    .auto_coupler_to_device_named_uart_1_control_xing_out_d_valid(
      subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_d_valid),
    .auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_opcode(
      subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_opcode),
    .auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_size(
      subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_size),
    .auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_source(
      subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_source),
    .auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_data(
      subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_data),
    .auto_coupler_to_device_named_uart_0_control_xing_out_a_ready(
      subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_ready),
    .auto_coupler_to_device_named_uart_0_control_xing_out_a_valid(
      subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid),
    .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode(
      subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode),
    .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param(
      subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param),
    .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size(
      subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size),
    .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source(
      subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source),
    .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address(
      subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address),
    .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask(
      subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask),
    .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data(
      subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data),
    .auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt(
      subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt),
    .auto_coupler_to_device_named_uart_0_control_xing_out_d_ready(
      subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready),
    .auto_coupler_to_device_named_uart_0_control_xing_out_d_valid(
      subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_valid),
    .auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode(
      subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode),
    .auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size(
      subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size),
    .auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source(
      subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source),
    .auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data(
      subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data),
    .auto_fixedClockNode_out_13_clock(subsystem_pbus_auto_fixedClockNode_out_13_clock),
    .auto_fixedClockNode_out_13_reset(subsystem_pbus_auto_fixedClockNode_out_13_reset),
    .auto_fixedClockNode_out_12_clock(subsystem_pbus_auto_fixedClockNode_out_12_clock),
    .auto_fixedClockNode_out_12_reset(subsystem_pbus_auto_fixedClockNode_out_12_reset),
    .auto_fixedClockNode_out_11_clock(subsystem_pbus_auto_fixedClockNode_out_11_clock),
    .auto_fixedClockNode_out_11_reset(subsystem_pbus_auto_fixedClockNode_out_11_reset),
    .auto_fixedClockNode_out_10_clock(subsystem_pbus_auto_fixedClockNode_out_10_clock),
    .auto_fixedClockNode_out_10_reset(subsystem_pbus_auto_fixedClockNode_out_10_reset),
    .auto_fixedClockNode_out_9_clock(subsystem_pbus_auto_fixedClockNode_out_9_clock),
    .auto_fixedClockNode_out_9_reset(subsystem_pbus_auto_fixedClockNode_out_9_reset),
    .auto_fixedClockNode_out_8_clock(subsystem_pbus_auto_fixedClockNode_out_8_clock),
    .auto_fixedClockNode_out_8_reset(subsystem_pbus_auto_fixedClockNode_out_8_reset),
    .auto_fixedClockNode_out_7_clock(subsystem_pbus_auto_fixedClockNode_out_7_clock),
    .auto_fixedClockNode_out_7_reset(subsystem_pbus_auto_fixedClockNode_out_7_reset),
    .auto_fixedClockNode_out_6_clock(subsystem_pbus_auto_fixedClockNode_out_6_clock),
    .auto_fixedClockNode_out_6_reset(subsystem_pbus_auto_fixedClockNode_out_6_reset),
    .auto_fixedClockNode_out_5_clock(subsystem_pbus_auto_fixedClockNode_out_5_clock),
    .auto_fixedClockNode_out_5_reset(subsystem_pbus_auto_fixedClockNode_out_5_reset),
    .auto_fixedClockNode_out_4_clock(subsystem_pbus_auto_fixedClockNode_out_4_clock),
    .auto_fixedClockNode_out_4_reset(subsystem_pbus_auto_fixedClockNode_out_4_reset),
    .auto_fixedClockNode_out_3_clock(subsystem_pbus_auto_fixedClockNode_out_3_clock),
    .auto_fixedClockNode_out_3_reset(subsystem_pbus_auto_fixedClockNode_out_3_reset),
    .auto_fixedClockNode_out_2_clock(subsystem_pbus_auto_fixedClockNode_out_2_clock),
    .auto_fixedClockNode_out_2_reset(subsystem_pbus_auto_fixedClockNode_out_2_reset),
    .auto_fixedClockNode_out_1_clock(subsystem_pbus_auto_fixedClockNode_out_1_clock),
    .auto_fixedClockNode_out_1_reset(subsystem_pbus_auto_fixedClockNode_out_1_reset),
    .auto_fixedClockNode_out_0_clock(subsystem_pbus_auto_fixedClockNode_out_0_clock),
    .auto_fixedClockNode_out_0_reset(subsystem_pbus_auto_fixedClockNode_out_0_reset),
    .auto_subsystem_pbus_clock_groups_in_member_subsystem_pbus_0_clock(
      subsystem_pbus_auto_subsystem_pbus_clock_groups_in_member_subsystem_pbus_0_clock),
    .auto_subsystem_pbus_clock_groups_in_member_subsystem_pbus_0_reset(
      subsystem_pbus_auto_subsystem_pbus_clock_groups_in_member_subsystem_pbus_0_reset),
    .auto_bus_xing_in_a_ready(subsystem_pbus_auto_bus_xing_in_a_ready),
    .auto_bus_xing_in_a_valid(subsystem_pbus_auto_bus_xing_in_a_valid),
    .auto_bus_xing_in_a_bits_opcode(subsystem_pbus_auto_bus_xing_in_a_bits_opcode),
    .auto_bus_xing_in_a_bits_param(subsystem_pbus_auto_bus_xing_in_a_bits_param),
    .auto_bus_xing_in_a_bits_size(subsystem_pbus_auto_bus_xing_in_a_bits_size),
    .auto_bus_xing_in_a_bits_source(subsystem_pbus_auto_bus_xing_in_a_bits_source),
    .auto_bus_xing_in_a_bits_address(subsystem_pbus_auto_bus_xing_in_a_bits_address),
    .auto_bus_xing_in_a_bits_mask(subsystem_pbus_auto_bus_xing_in_a_bits_mask),
    .auto_bus_xing_in_a_bits_data(subsystem_pbus_auto_bus_xing_in_a_bits_data),
    .auto_bus_xing_in_a_bits_corrupt(subsystem_pbus_auto_bus_xing_in_a_bits_corrupt),
    .auto_bus_xing_in_d_ready(subsystem_pbus_auto_bus_xing_in_d_ready),
    .auto_bus_xing_in_d_valid(subsystem_pbus_auto_bus_xing_in_d_valid),
    .auto_bus_xing_in_d_bits_opcode(subsystem_pbus_auto_bus_xing_in_d_bits_opcode),
    .auto_bus_xing_in_d_bits_param(subsystem_pbus_auto_bus_xing_in_d_bits_param),
    .auto_bus_xing_in_d_bits_size(subsystem_pbus_auto_bus_xing_in_d_bits_size),
    .auto_bus_xing_in_d_bits_source(subsystem_pbus_auto_bus_xing_in_d_bits_source),
    .auto_bus_xing_in_d_bits_sink(subsystem_pbus_auto_bus_xing_in_d_bits_sink),
    .auto_bus_xing_in_d_bits_denied(subsystem_pbus_auto_bus_xing_in_d_bits_denied),
    .auto_bus_xing_in_d_bits_data(subsystem_pbus_auto_bus_xing_in_d_bits_data),
    .auto_bus_xing_in_d_bits_corrupt(subsystem_pbus_auto_bus_xing_in_d_bits_corrupt)
  );
  FrontBus subsystem_fbus ( // @[FrontBus.scala 22:26]
    .auto_subsystem_fbus_clock_groups_in_member_subsystem_fbus_0_clock(
      subsystem_fbus_auto_subsystem_fbus_clock_groups_in_member_subsystem_fbus_0_clock),
    .auto_subsystem_fbus_clock_groups_in_member_subsystem_fbus_0_reset(
      subsystem_fbus_auto_subsystem_fbus_clock_groups_in_member_subsystem_fbus_0_reset)
  );
  PeripheryBus_1 subsystem_cbus ( // @[PeripheryBus.scala 31:26]
    .auto_coupler_to_bootrom_fragmenter_out_a_ready(subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_ready),
    .auto_coupler_to_bootrom_fragmenter_out_a_valid(subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_valid),
    .auto_coupler_to_bootrom_fragmenter_out_a_bits_opcode(
      subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_opcode),
    .auto_coupler_to_bootrom_fragmenter_out_a_bits_param(
      subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_param),
    .auto_coupler_to_bootrom_fragmenter_out_a_bits_size(
      subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_size),
    .auto_coupler_to_bootrom_fragmenter_out_a_bits_source(
      subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_source),
    .auto_coupler_to_bootrom_fragmenter_out_a_bits_address(
      subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_address),
    .auto_coupler_to_bootrom_fragmenter_out_a_bits_mask(
      subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_mask),
    .auto_coupler_to_bootrom_fragmenter_out_a_bits_corrupt(
      subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_corrupt),
    .auto_coupler_to_bootrom_fragmenter_out_d_ready(subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_d_ready),
    .auto_coupler_to_bootrom_fragmenter_out_d_valid(subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_d_valid),
    .auto_coupler_to_bootrom_fragmenter_out_d_bits_size(
      subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_d_bits_size),
    .auto_coupler_to_bootrom_fragmenter_out_d_bits_source(
      subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_d_bits_source),
    .auto_coupler_to_bootrom_fragmenter_out_d_bits_data(
      subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_d_bits_data),
    .auto_coupler_to_aon_asource_out_a_mem_0_opcode(subsystem_cbus_auto_coupler_to_aon_asource_out_a_mem_0_opcode),
    .auto_coupler_to_aon_asource_out_a_mem_0_param(subsystem_cbus_auto_coupler_to_aon_asource_out_a_mem_0_param),
    .auto_coupler_to_aon_asource_out_a_mem_0_size(subsystem_cbus_auto_coupler_to_aon_asource_out_a_mem_0_size),
    .auto_coupler_to_aon_asource_out_a_mem_0_source(subsystem_cbus_auto_coupler_to_aon_asource_out_a_mem_0_source),
    .auto_coupler_to_aon_asource_out_a_mem_0_address(subsystem_cbus_auto_coupler_to_aon_asource_out_a_mem_0_address),
    .auto_coupler_to_aon_asource_out_a_mem_0_mask(subsystem_cbus_auto_coupler_to_aon_asource_out_a_mem_0_mask),
    .auto_coupler_to_aon_asource_out_a_mem_0_data(subsystem_cbus_auto_coupler_to_aon_asource_out_a_mem_0_data),
    .auto_coupler_to_aon_asource_out_a_mem_0_corrupt(subsystem_cbus_auto_coupler_to_aon_asource_out_a_mem_0_corrupt),
    .auto_coupler_to_aon_asource_out_a_ridx(subsystem_cbus_auto_coupler_to_aon_asource_out_a_ridx),
    .auto_coupler_to_aon_asource_out_a_widx(subsystem_cbus_auto_coupler_to_aon_asource_out_a_widx),
    .auto_coupler_to_aon_asource_out_a_safe_ridx_valid(subsystem_cbus_auto_coupler_to_aon_asource_out_a_safe_ridx_valid)
      ,
    .auto_coupler_to_aon_asource_out_a_safe_widx_valid(subsystem_cbus_auto_coupler_to_aon_asource_out_a_safe_widx_valid)
      ,
    .auto_coupler_to_aon_asource_out_a_safe_source_reset_n(
      subsystem_cbus_auto_coupler_to_aon_asource_out_a_safe_source_reset_n),
    .auto_coupler_to_aon_asource_out_a_safe_sink_reset_n(
      subsystem_cbus_auto_coupler_to_aon_asource_out_a_safe_sink_reset_n),
    .auto_coupler_to_aon_asource_out_d_mem_0_opcode(subsystem_cbus_auto_coupler_to_aon_asource_out_d_mem_0_opcode),
    .auto_coupler_to_aon_asource_out_d_mem_0_param(subsystem_cbus_auto_coupler_to_aon_asource_out_d_mem_0_param),
    .auto_coupler_to_aon_asource_out_d_mem_0_size(subsystem_cbus_auto_coupler_to_aon_asource_out_d_mem_0_size),
    .auto_coupler_to_aon_asource_out_d_mem_0_source(subsystem_cbus_auto_coupler_to_aon_asource_out_d_mem_0_source),
    .auto_coupler_to_aon_asource_out_d_mem_0_sink(subsystem_cbus_auto_coupler_to_aon_asource_out_d_mem_0_sink),
    .auto_coupler_to_aon_asource_out_d_mem_0_denied(subsystem_cbus_auto_coupler_to_aon_asource_out_d_mem_0_denied),
    .auto_coupler_to_aon_asource_out_d_mem_0_data(subsystem_cbus_auto_coupler_to_aon_asource_out_d_mem_0_data),
    .auto_coupler_to_aon_asource_out_d_mem_0_corrupt(subsystem_cbus_auto_coupler_to_aon_asource_out_d_mem_0_corrupt),
    .auto_coupler_to_aon_asource_out_d_ridx(subsystem_cbus_auto_coupler_to_aon_asource_out_d_ridx),
    .auto_coupler_to_aon_asource_out_d_widx(subsystem_cbus_auto_coupler_to_aon_asource_out_d_widx),
    .auto_coupler_to_aon_asource_out_d_safe_ridx_valid(subsystem_cbus_auto_coupler_to_aon_asource_out_d_safe_ridx_valid)
      ,
    .auto_coupler_to_aon_asource_out_d_safe_widx_valid(subsystem_cbus_auto_coupler_to_aon_asource_out_d_safe_widx_valid)
      ,
    .auto_coupler_to_aon_asource_out_d_safe_source_reset_n(
      subsystem_cbus_auto_coupler_to_aon_asource_out_d_safe_source_reset_n),
    .auto_coupler_to_aon_asource_out_d_safe_sink_reset_n(
      subsystem_cbus_auto_coupler_to_aon_asource_out_d_safe_sink_reset_n),
    .auto_coupler_to_tile_tl_slave_clock_xing_out_a_ready(
      subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_ready),
    .auto_coupler_to_tile_tl_slave_clock_xing_out_a_valid(
      subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_valid),
    .auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_opcode(
      subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_opcode),
    .auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_param(
      subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_param),
    .auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_size(
      subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_size),
    .auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_source(
      subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_source),
    .auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_address(
      subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_address),
    .auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_mask(
      subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_mask),
    .auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_data(
      subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_data),
    .auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_corrupt(
      subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_corrupt),
    .auto_coupler_to_tile_tl_slave_clock_xing_out_d_ready(
      subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_ready),
    .auto_coupler_to_tile_tl_slave_clock_xing_out_d_valid(
      subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_valid),
    .auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_opcode(
      subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_opcode),
    .auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_param(
      subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_param),
    .auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_size(
      subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_size),
    .auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_source(
      subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_source),
    .auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_sink(
      subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_sink),
    .auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_denied(
      subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_denied),
    .auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_data(
      subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_data),
    .auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_corrupt(
      subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_corrupt),
    .auto_coupler_to_debug_fragmenter_out_a_ready(subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_ready),
    .auto_coupler_to_debug_fragmenter_out_a_valid(subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_valid),
    .auto_coupler_to_debug_fragmenter_out_a_bits_opcode(
      subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_opcode),
    .auto_coupler_to_debug_fragmenter_out_a_bits_param(subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_param)
      ,
    .auto_coupler_to_debug_fragmenter_out_a_bits_size(subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_size),
    .auto_coupler_to_debug_fragmenter_out_a_bits_source(
      subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_source),
    .auto_coupler_to_debug_fragmenter_out_a_bits_address(
      subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_address),
    .auto_coupler_to_debug_fragmenter_out_a_bits_mask(subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_mask),
    .auto_coupler_to_debug_fragmenter_out_a_bits_data(subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_data),
    .auto_coupler_to_debug_fragmenter_out_a_bits_corrupt(
      subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_corrupt),
    .auto_coupler_to_debug_fragmenter_out_d_ready(subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_ready),
    .auto_coupler_to_debug_fragmenter_out_d_valid(subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_valid),
    .auto_coupler_to_debug_fragmenter_out_d_bits_opcode(
      subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_bits_opcode),
    .auto_coupler_to_debug_fragmenter_out_d_bits_size(subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_bits_size),
    .auto_coupler_to_debug_fragmenter_out_d_bits_source(
      subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_bits_source),
    .auto_coupler_to_debug_fragmenter_out_d_bits_data(subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_bits_data),
    .auto_coupler_to_clint_fragmenter_out_a_ready(subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_ready),
    .auto_coupler_to_clint_fragmenter_out_a_valid(subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_valid),
    .auto_coupler_to_clint_fragmenter_out_a_bits_opcode(
      subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_opcode),
    .auto_coupler_to_clint_fragmenter_out_a_bits_param(subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_param)
      ,
    .auto_coupler_to_clint_fragmenter_out_a_bits_size(subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_size),
    .auto_coupler_to_clint_fragmenter_out_a_bits_source(
      subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_source),
    .auto_coupler_to_clint_fragmenter_out_a_bits_address(
      subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_address),
    .auto_coupler_to_clint_fragmenter_out_a_bits_mask(subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_mask),
    .auto_coupler_to_clint_fragmenter_out_a_bits_data(subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_data),
    .auto_coupler_to_clint_fragmenter_out_a_bits_corrupt(
      subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_corrupt),
    .auto_coupler_to_clint_fragmenter_out_d_ready(subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_ready),
    .auto_coupler_to_clint_fragmenter_out_d_valid(subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_valid),
    .auto_coupler_to_clint_fragmenter_out_d_bits_opcode(
      subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_bits_opcode),
    .auto_coupler_to_clint_fragmenter_out_d_bits_size(subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_bits_size),
    .auto_coupler_to_clint_fragmenter_out_d_bits_source(
      subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_bits_source),
    .auto_coupler_to_clint_fragmenter_out_d_bits_data(subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_bits_data),
    .auto_coupler_to_plic_fragmenter_out_a_ready(subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_ready),
    .auto_coupler_to_plic_fragmenter_out_a_valid(subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_valid),
    .auto_coupler_to_plic_fragmenter_out_a_bits_opcode(subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_opcode)
      ,
    .auto_coupler_to_plic_fragmenter_out_a_bits_param(subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_param),
    .auto_coupler_to_plic_fragmenter_out_a_bits_size(subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_size),
    .auto_coupler_to_plic_fragmenter_out_a_bits_source(subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_source)
      ,
    .auto_coupler_to_plic_fragmenter_out_a_bits_address(
      subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_address),
    .auto_coupler_to_plic_fragmenter_out_a_bits_mask(subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_mask),
    .auto_coupler_to_plic_fragmenter_out_a_bits_data(subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_data),
    .auto_coupler_to_plic_fragmenter_out_a_bits_corrupt(
      subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_corrupt),
    .auto_coupler_to_plic_fragmenter_out_d_ready(subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_ready),
    .auto_coupler_to_plic_fragmenter_out_d_valid(subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_valid),
    .auto_coupler_to_plic_fragmenter_out_d_bits_opcode(subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_bits_opcode)
      ,
    .auto_coupler_to_plic_fragmenter_out_d_bits_size(subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_bits_size),
    .auto_coupler_to_plic_fragmenter_out_d_bits_source(subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_bits_source)
      ,
    .auto_coupler_to_plic_fragmenter_out_d_bits_data(subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_bits_data),
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_ready(
      subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_ready),
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_valid(
      subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_valid),
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_opcode(
      subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_opcode),
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_param(
      subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_param),
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_size(
      subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_size),
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_source(
      subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_source),
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_address(
      subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_address),
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_mask(
      subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_mask),
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_data(
      subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_data),
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_corrupt(
      subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_corrupt),
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_ready(
      subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_ready),
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_valid(
      subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_valid),
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_opcode(
      subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_opcode),
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_param(
      subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_param),
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_size(
      subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_size),
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_source(
      subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_source),
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_sink(
      subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_sink),
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_denied(
      subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_denied),
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_data(
      subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_data),
    .auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_corrupt(
      subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_corrupt),
    .auto_fixedClockNode_out_2_clock(subsystem_cbus_auto_fixedClockNode_out_2_clock),
    .auto_fixedClockNode_out_2_reset(subsystem_cbus_auto_fixedClockNode_out_2_reset),
    .auto_fixedClockNode_out_0_clock(subsystem_cbus_auto_fixedClockNode_out_0_clock),
    .auto_fixedClockNode_out_0_reset(subsystem_cbus_auto_fixedClockNode_out_0_reset),
    .auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_1_clock(
      subsystem_cbus_auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_1_clock),
    .auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_1_reset(
      subsystem_cbus_auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_1_reset),
    .auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_0_clock(
      subsystem_cbus_auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_0_clock),
    .auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_0_reset(
      subsystem_cbus_auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_0_reset),
    .auto_subsystem_cbus_clock_groups_out_member_subsystem_pbus_0_clock(
      subsystem_cbus_auto_subsystem_cbus_clock_groups_out_member_subsystem_pbus_0_clock),
    .auto_subsystem_cbus_clock_groups_out_member_subsystem_pbus_0_reset(
      subsystem_cbus_auto_subsystem_cbus_clock_groups_out_member_subsystem_pbus_0_reset),
    .auto_bus_xing_in_a_ready(subsystem_cbus_auto_bus_xing_in_a_ready),
    .auto_bus_xing_in_a_valid(subsystem_cbus_auto_bus_xing_in_a_valid),
    .auto_bus_xing_in_a_bits_opcode(subsystem_cbus_auto_bus_xing_in_a_bits_opcode),
    .auto_bus_xing_in_a_bits_param(subsystem_cbus_auto_bus_xing_in_a_bits_param),
    .auto_bus_xing_in_a_bits_size(subsystem_cbus_auto_bus_xing_in_a_bits_size),
    .auto_bus_xing_in_a_bits_source(subsystem_cbus_auto_bus_xing_in_a_bits_source),
    .auto_bus_xing_in_a_bits_address(subsystem_cbus_auto_bus_xing_in_a_bits_address),
    .auto_bus_xing_in_a_bits_mask(subsystem_cbus_auto_bus_xing_in_a_bits_mask),
    .auto_bus_xing_in_a_bits_data(subsystem_cbus_auto_bus_xing_in_a_bits_data),
    .auto_bus_xing_in_a_bits_corrupt(subsystem_cbus_auto_bus_xing_in_a_bits_corrupt),
    .auto_bus_xing_in_d_ready(subsystem_cbus_auto_bus_xing_in_d_ready),
    .auto_bus_xing_in_d_valid(subsystem_cbus_auto_bus_xing_in_d_valid),
    .auto_bus_xing_in_d_bits_opcode(subsystem_cbus_auto_bus_xing_in_d_bits_opcode),
    .auto_bus_xing_in_d_bits_param(subsystem_cbus_auto_bus_xing_in_d_bits_param),
    .auto_bus_xing_in_d_bits_size(subsystem_cbus_auto_bus_xing_in_d_bits_size),
    .auto_bus_xing_in_d_bits_source(subsystem_cbus_auto_bus_xing_in_d_bits_source),
    .auto_bus_xing_in_d_bits_sink(subsystem_cbus_auto_bus_xing_in_d_bits_sink),
    .auto_bus_xing_in_d_bits_denied(subsystem_cbus_auto_bus_xing_in_d_bits_denied),
    .auto_bus_xing_in_d_bits_data(subsystem_cbus_auto_bus_xing_in_d_bits_data),
    .auto_bus_xing_in_d_bits_corrupt(subsystem_cbus_auto_bus_xing_in_d_bits_corrupt),
    .clock(subsystem_cbus_clock),
    .reset(subsystem_cbus_reset)
  );
  MemoryBus subsystem_mbus ( // @[MemoryBus.scala 25:26]
    .auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_ready(
      subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_ready),
    .auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_valid(
      subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_valid),
    .auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_opcode(
      subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_opcode),
    .auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_param(
      subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_param),
    .auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_size(
      subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_size),
    .auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_source(
      subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_source),
    .auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_address(
      subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_address),
    .auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_mask(
      subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_mask),
    .auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_data(
      subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_data),
    .auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_corrupt(
      subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_corrupt),
    .auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_d_ready(
      subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_d_ready),
    .auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_d_valid(
      subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_d_valid),
    .auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_d_bits_opcode(
      subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_d_bits_opcode),
    .auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_d_bits_size(
      subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_d_bits_size),
    .auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_d_bits_source(
      subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_d_bits_source),
    .auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_d_bits_data(
      subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_d_bits_data),
    .auto_subsystem_mbus_clock_groups_in_member_subsystem_mbus_0_clock(
      subsystem_mbus_auto_subsystem_mbus_clock_groups_in_member_subsystem_mbus_0_clock),
    .auto_subsystem_mbus_clock_groups_in_member_subsystem_mbus_0_reset(
      subsystem_mbus_auto_subsystem_mbus_clock_groups_in_member_subsystem_mbus_0_reset),
    .auto_bus_xing_in_a_ready(subsystem_mbus_auto_bus_xing_in_a_ready),
    .auto_bus_xing_in_a_valid(subsystem_mbus_auto_bus_xing_in_a_valid),
    .auto_bus_xing_in_a_bits_opcode(subsystem_mbus_auto_bus_xing_in_a_bits_opcode),
    .auto_bus_xing_in_a_bits_param(subsystem_mbus_auto_bus_xing_in_a_bits_param),
    .auto_bus_xing_in_a_bits_size(subsystem_mbus_auto_bus_xing_in_a_bits_size),
    .auto_bus_xing_in_a_bits_source(subsystem_mbus_auto_bus_xing_in_a_bits_source),
    .auto_bus_xing_in_a_bits_address(subsystem_mbus_auto_bus_xing_in_a_bits_address),
    .auto_bus_xing_in_a_bits_mask(subsystem_mbus_auto_bus_xing_in_a_bits_mask),
    .auto_bus_xing_in_a_bits_data(subsystem_mbus_auto_bus_xing_in_a_bits_data),
    .auto_bus_xing_in_d_ready(subsystem_mbus_auto_bus_xing_in_d_ready),
    .auto_bus_xing_in_d_valid(subsystem_mbus_auto_bus_xing_in_d_valid),
    .auto_bus_xing_in_d_bits_opcode(subsystem_mbus_auto_bus_xing_in_d_bits_opcode),
    .auto_bus_xing_in_d_bits_size(subsystem_mbus_auto_bus_xing_in_d_bits_size),
    .auto_bus_xing_in_d_bits_source(subsystem_mbus_auto_bus_xing_in_d_bits_source),
    .auto_bus_xing_in_d_bits_data(subsystem_mbus_auto_bus_xing_in_d_bits_data)
  );
  CoherenceManagerWrapper subsystem_l2_wrapper ( // @[BankedL2Params.scala 47:31]
    .auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_ready(
      subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_ready),
    .auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_valid(
      subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_valid),
    .auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_opcode(
      subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_opcode),
    .auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_param(
      subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_param),
    .auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_size(
      subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_size),
    .auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_source(
      subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_source),
    .auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_address(
      subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_address),
    .auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_mask(
      subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_mask),
    .auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_data(
      subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_data),
    .auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_ready(
      subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_ready),
    .auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_valid(
      subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_valid),
    .auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_bits_opcode(
      subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_bits_opcode),
    .auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_bits_size(
      subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_bits_size),
    .auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_bits_source(
      subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_bits_source),
    .auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_bits_data(
      subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_bits_data),
    .auto_coherent_jbar_in_a_ready(subsystem_l2_wrapper_auto_coherent_jbar_in_a_ready),
    .auto_coherent_jbar_in_a_valid(subsystem_l2_wrapper_auto_coherent_jbar_in_a_valid),
    .auto_coherent_jbar_in_a_bits_opcode(subsystem_l2_wrapper_auto_coherent_jbar_in_a_bits_opcode),
    .auto_coherent_jbar_in_a_bits_param(subsystem_l2_wrapper_auto_coherent_jbar_in_a_bits_param),
    .auto_coherent_jbar_in_a_bits_size(subsystem_l2_wrapper_auto_coherent_jbar_in_a_bits_size),
    .auto_coherent_jbar_in_a_bits_source(subsystem_l2_wrapper_auto_coherent_jbar_in_a_bits_source),
    .auto_coherent_jbar_in_a_bits_address(subsystem_l2_wrapper_auto_coherent_jbar_in_a_bits_address),
    .auto_coherent_jbar_in_a_bits_mask(subsystem_l2_wrapper_auto_coherent_jbar_in_a_bits_mask),
    .auto_coherent_jbar_in_a_bits_data(subsystem_l2_wrapper_auto_coherent_jbar_in_a_bits_data),
    .auto_coherent_jbar_in_a_bits_corrupt(subsystem_l2_wrapper_auto_coherent_jbar_in_a_bits_corrupt),
    .auto_coherent_jbar_in_b_ready(subsystem_l2_wrapper_auto_coherent_jbar_in_b_ready),
    .auto_coherent_jbar_in_b_valid(subsystem_l2_wrapper_auto_coherent_jbar_in_b_valid),
    .auto_coherent_jbar_in_b_bits_param(subsystem_l2_wrapper_auto_coherent_jbar_in_b_bits_param),
    .auto_coherent_jbar_in_b_bits_address(subsystem_l2_wrapper_auto_coherent_jbar_in_b_bits_address),
    .auto_coherent_jbar_in_c_ready(subsystem_l2_wrapper_auto_coherent_jbar_in_c_ready),
    .auto_coherent_jbar_in_c_valid(subsystem_l2_wrapper_auto_coherent_jbar_in_c_valid),
    .auto_coherent_jbar_in_c_bits_opcode(subsystem_l2_wrapper_auto_coherent_jbar_in_c_bits_opcode),
    .auto_coherent_jbar_in_c_bits_param(subsystem_l2_wrapper_auto_coherent_jbar_in_c_bits_param),
    .auto_coherent_jbar_in_c_bits_size(subsystem_l2_wrapper_auto_coherent_jbar_in_c_bits_size),
    .auto_coherent_jbar_in_c_bits_source(subsystem_l2_wrapper_auto_coherent_jbar_in_c_bits_source),
    .auto_coherent_jbar_in_c_bits_address(subsystem_l2_wrapper_auto_coherent_jbar_in_c_bits_address),
    .auto_coherent_jbar_in_c_bits_data(subsystem_l2_wrapper_auto_coherent_jbar_in_c_bits_data),
    .auto_coherent_jbar_in_c_bits_corrupt(subsystem_l2_wrapper_auto_coherent_jbar_in_c_bits_corrupt),
    .auto_coherent_jbar_in_d_ready(subsystem_l2_wrapper_auto_coherent_jbar_in_d_ready),
    .auto_coherent_jbar_in_d_valid(subsystem_l2_wrapper_auto_coherent_jbar_in_d_valid),
    .auto_coherent_jbar_in_d_bits_opcode(subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_opcode),
    .auto_coherent_jbar_in_d_bits_param(subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_param),
    .auto_coherent_jbar_in_d_bits_size(subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_size),
    .auto_coherent_jbar_in_d_bits_source(subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_source),
    .auto_coherent_jbar_in_d_bits_sink(subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_sink),
    .auto_coherent_jbar_in_d_bits_data(subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_data),
    .auto_coherent_jbar_in_e_valid(subsystem_l2_wrapper_auto_coherent_jbar_in_e_valid),
    .auto_coherent_jbar_in_e_bits_sink(subsystem_l2_wrapper_auto_coherent_jbar_in_e_bits_sink),
    .auto_subsystem_l2_clock_groups_in_member_subsystem_l2_1_clock(
      subsystem_l2_wrapper_auto_subsystem_l2_clock_groups_in_member_subsystem_l2_1_clock),
    .auto_subsystem_l2_clock_groups_in_member_subsystem_l2_1_reset(
      subsystem_l2_wrapper_auto_subsystem_l2_clock_groups_in_member_subsystem_l2_1_reset),
    .auto_subsystem_l2_clock_groups_in_member_subsystem_l2_0_clock(
      subsystem_l2_wrapper_auto_subsystem_l2_clock_groups_in_member_subsystem_l2_0_clock),
    .auto_subsystem_l2_clock_groups_in_member_subsystem_l2_0_reset(
      subsystem_l2_wrapper_auto_subsystem_l2_clock_groups_in_member_subsystem_l2_0_reset),
    .auto_subsystem_l2_clock_groups_out_member_subsystem_mbus_0_clock(
      subsystem_l2_wrapper_auto_subsystem_l2_clock_groups_out_member_subsystem_mbus_0_clock),
    .auto_subsystem_l2_clock_groups_out_member_subsystem_mbus_0_reset(
      subsystem_l2_wrapper_auto_subsystem_l2_clock_groups_out_member_subsystem_mbus_0_reset)
  );
  TilePRCIDomain tile_prci_domain ( // @[HasTiles.scala 252:38]
    .auto_intsink_in_sync_0(tile_prci_domain_auto_intsink_in_sync_0),
    .auto_tile_reset_domain_tile_hartid_in(tile_prci_domain_auto_tile_reset_domain_tile_hartid_in),
    .auto_int_out_clock_xing_out_2_sync_0(tile_prci_domain_auto_int_out_clock_xing_out_2_sync_0),
    .auto_int_out_clock_xing_out_1_sync_0(tile_prci_domain_auto_int_out_clock_xing_out_1_sync_0),
    .auto_int_out_clock_xing_out_0_sync_0(tile_prci_domain_auto_int_out_clock_xing_out_0_sync_0),
    .auto_int_in_clock_xing_in_2_sync_0(tile_prci_domain_auto_int_in_clock_xing_in_2_sync_0),
    .auto_int_in_clock_xing_in_1_sync_0(tile_prci_domain_auto_int_in_clock_xing_in_1_sync_0),
    .auto_int_in_clock_xing_in_0_sync_0(tile_prci_domain_auto_int_in_clock_xing_in_0_sync_0),
    .auto_int_in_clock_xing_in_0_sync_1(tile_prci_domain_auto_int_in_clock_xing_in_0_sync_1),
    .auto_tl_slave_clock_xing_in_a_ready(tile_prci_domain_auto_tl_slave_clock_xing_in_a_ready),
    .auto_tl_slave_clock_xing_in_a_valid(tile_prci_domain_auto_tl_slave_clock_xing_in_a_valid),
    .auto_tl_slave_clock_xing_in_a_bits_opcode(tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_opcode),
    .auto_tl_slave_clock_xing_in_a_bits_param(tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_param),
    .auto_tl_slave_clock_xing_in_a_bits_size(tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_size),
    .auto_tl_slave_clock_xing_in_a_bits_source(tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_source),
    .auto_tl_slave_clock_xing_in_a_bits_address(tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_address),
    .auto_tl_slave_clock_xing_in_a_bits_mask(tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_mask),
    .auto_tl_slave_clock_xing_in_a_bits_data(tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_data),
    .auto_tl_slave_clock_xing_in_a_bits_corrupt(tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_corrupt),
    .auto_tl_slave_clock_xing_in_d_ready(tile_prci_domain_auto_tl_slave_clock_xing_in_d_ready),
    .auto_tl_slave_clock_xing_in_d_valid(tile_prci_domain_auto_tl_slave_clock_xing_in_d_valid),
    .auto_tl_slave_clock_xing_in_d_bits_opcode(tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_opcode),
    .auto_tl_slave_clock_xing_in_d_bits_param(tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_param),
    .auto_tl_slave_clock_xing_in_d_bits_size(tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_size),
    .auto_tl_slave_clock_xing_in_d_bits_source(tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_source),
    .auto_tl_slave_clock_xing_in_d_bits_sink(tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_sink),
    .auto_tl_slave_clock_xing_in_d_bits_denied(tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_denied),
    .auto_tl_slave_clock_xing_in_d_bits_data(tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_data),
    .auto_tl_slave_clock_xing_in_d_bits_corrupt(tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_corrupt),
    .auto_tl_master_clock_xing_out_a_ready(tile_prci_domain_auto_tl_master_clock_xing_out_a_ready),
    .auto_tl_master_clock_xing_out_a_valid(tile_prci_domain_auto_tl_master_clock_xing_out_a_valid),
    .auto_tl_master_clock_xing_out_a_bits_opcode(tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode),
    .auto_tl_master_clock_xing_out_a_bits_param(tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param),
    .auto_tl_master_clock_xing_out_a_bits_size(tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size),
    .auto_tl_master_clock_xing_out_a_bits_source(tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source),
    .auto_tl_master_clock_xing_out_a_bits_address(tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address),
    .auto_tl_master_clock_xing_out_a_bits_mask(tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask),
    .auto_tl_master_clock_xing_out_a_bits_data(tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data),
    .auto_tl_master_clock_xing_out_a_bits_corrupt(tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt),
    .auto_tl_master_clock_xing_out_b_ready(tile_prci_domain_auto_tl_master_clock_xing_out_b_ready),
    .auto_tl_master_clock_xing_out_b_valid(tile_prci_domain_auto_tl_master_clock_xing_out_b_valid),
    .auto_tl_master_clock_xing_out_b_bits_param(tile_prci_domain_auto_tl_master_clock_xing_out_b_bits_param),
    .auto_tl_master_clock_xing_out_b_bits_address(tile_prci_domain_auto_tl_master_clock_xing_out_b_bits_address),
    .auto_tl_master_clock_xing_out_c_ready(tile_prci_domain_auto_tl_master_clock_xing_out_c_ready),
    .auto_tl_master_clock_xing_out_c_valid(tile_prci_domain_auto_tl_master_clock_xing_out_c_valid),
    .auto_tl_master_clock_xing_out_c_bits_opcode(tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_opcode),
    .auto_tl_master_clock_xing_out_c_bits_param(tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_param),
    .auto_tl_master_clock_xing_out_c_bits_size(tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_size),
    .auto_tl_master_clock_xing_out_c_bits_source(tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_source),
    .auto_tl_master_clock_xing_out_c_bits_address(tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_address),
    .auto_tl_master_clock_xing_out_c_bits_data(tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_data),
    .auto_tl_master_clock_xing_out_c_bits_corrupt(tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_corrupt),
    .auto_tl_master_clock_xing_out_d_ready(tile_prci_domain_auto_tl_master_clock_xing_out_d_ready),
    .auto_tl_master_clock_xing_out_d_valid(tile_prci_domain_auto_tl_master_clock_xing_out_d_valid),
    .auto_tl_master_clock_xing_out_d_bits_opcode(tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_opcode),
    .auto_tl_master_clock_xing_out_d_bits_param(tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_param),
    .auto_tl_master_clock_xing_out_d_bits_size(tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_size),
    .auto_tl_master_clock_xing_out_d_bits_source(tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_source),
    .auto_tl_master_clock_xing_out_d_bits_sink(tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_sink),
    .auto_tl_master_clock_xing_out_d_bits_denied(tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_denied),
    .auto_tl_master_clock_xing_out_d_bits_data(tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_data),
    .auto_tl_master_clock_xing_out_d_bits_corrupt(tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_corrupt),
    .auto_tl_master_clock_xing_out_e_valid(tile_prci_domain_auto_tl_master_clock_xing_out_e_valid),
    .auto_tl_master_clock_xing_out_e_bits_sink(tile_prci_domain_auto_tl_master_clock_xing_out_e_bits_sink),
    .auto_tap_clock_in_clock(tile_prci_domain_auto_tap_clock_in_clock),
    .auto_tap_clock_in_reset(tile_prci_domain_auto_tap_clock_in_reset)
  );
  ClockSinkDomain plicDomainWrapper ( // @[Plic.scala 359:39]
    .auto_plic_int_in_0(plicDomainWrapper_auto_plic_int_in_0),
    .auto_plic_int_in_1(plicDomainWrapper_auto_plic_int_in_1),
    .auto_plic_int_in_2(plicDomainWrapper_auto_plic_int_in_2),
    .auto_plic_int_in_3(plicDomainWrapper_auto_plic_int_in_3),
    .auto_plic_int_in_4(plicDomainWrapper_auto_plic_int_in_4),
    .auto_plic_int_in_5(plicDomainWrapper_auto_plic_int_in_5),
    .auto_plic_int_in_6(plicDomainWrapper_auto_plic_int_in_6),
    .auto_plic_int_in_7(plicDomainWrapper_auto_plic_int_in_7),
    .auto_plic_int_in_8(plicDomainWrapper_auto_plic_int_in_8),
    .auto_plic_int_in_9(plicDomainWrapper_auto_plic_int_in_9),
    .auto_plic_int_in_10(plicDomainWrapper_auto_plic_int_in_10),
    .auto_plic_int_in_11(plicDomainWrapper_auto_plic_int_in_11),
    .auto_plic_int_in_12(plicDomainWrapper_auto_plic_int_in_12),
    .auto_plic_int_in_13(plicDomainWrapper_auto_plic_int_in_13),
    .auto_plic_int_in_14(plicDomainWrapper_auto_plic_int_in_14),
    .auto_plic_int_in_15(plicDomainWrapper_auto_plic_int_in_15),
    .auto_plic_int_in_16(plicDomainWrapper_auto_plic_int_in_16),
    .auto_plic_int_in_17(plicDomainWrapper_auto_plic_int_in_17),
    .auto_plic_int_in_18(plicDomainWrapper_auto_plic_int_in_18),
    .auto_plic_int_in_19(plicDomainWrapper_auto_plic_int_in_19),
    .auto_plic_int_in_20(plicDomainWrapper_auto_plic_int_in_20),
    .auto_plic_int_in_21(plicDomainWrapper_auto_plic_int_in_21),
    .auto_plic_int_in_22(plicDomainWrapper_auto_plic_int_in_22),
    .auto_plic_int_in_23(plicDomainWrapper_auto_plic_int_in_23),
    .auto_plic_int_in_24(plicDomainWrapper_auto_plic_int_in_24),
    .auto_plic_int_in_25(plicDomainWrapper_auto_plic_int_in_25),
    .auto_plic_int_in_26(plicDomainWrapper_auto_plic_int_in_26),
    .auto_plic_int_in_27(plicDomainWrapper_auto_plic_int_in_27),
    .auto_plic_int_in_28(plicDomainWrapper_auto_plic_int_in_28),
    .auto_plic_int_in_29(plicDomainWrapper_auto_plic_int_in_29),
    .auto_plic_int_in_30(plicDomainWrapper_auto_plic_int_in_30),
    .auto_plic_int_in_31(plicDomainWrapper_auto_plic_int_in_31),
    .auto_plic_int_in_32(plicDomainWrapper_auto_plic_int_in_32),
    .auto_plic_int_in_33(plicDomainWrapper_auto_plic_int_in_33),
    .auto_plic_int_in_34(plicDomainWrapper_auto_plic_int_in_34),
    .auto_plic_int_in_35(plicDomainWrapper_auto_plic_int_in_35),
    .auto_plic_int_in_36(plicDomainWrapper_auto_plic_int_in_36),
    .auto_plic_int_in_37(plicDomainWrapper_auto_plic_int_in_37),
    .auto_plic_int_in_38(plicDomainWrapper_auto_plic_int_in_38),
    .auto_plic_int_in_39(plicDomainWrapper_auto_plic_int_in_39),
    .auto_plic_int_in_40(plicDomainWrapper_auto_plic_int_in_40),
    .auto_plic_int_in_41(plicDomainWrapper_auto_plic_int_in_41),
    .auto_plic_int_in_42(plicDomainWrapper_auto_plic_int_in_42),
    .auto_plic_int_in_43(plicDomainWrapper_auto_plic_int_in_43),
    .auto_plic_int_in_44(plicDomainWrapper_auto_plic_int_in_44),
    .auto_plic_int_in_45(plicDomainWrapper_auto_plic_int_in_45),
    .auto_plic_int_in_46(plicDomainWrapper_auto_plic_int_in_46),
    .auto_plic_int_in_47(plicDomainWrapper_auto_plic_int_in_47),
    .auto_plic_int_in_48(plicDomainWrapper_auto_plic_int_in_48),
    .auto_plic_int_in_49(plicDomainWrapper_auto_plic_int_in_49),
    .auto_plic_int_in_50(plicDomainWrapper_auto_plic_int_in_50),
    .auto_plic_int_in_51(plicDomainWrapper_auto_plic_int_in_51),
    .auto_plic_int_in_52(plicDomainWrapper_auto_plic_int_in_52),
    .auto_plic_int_in_53(plicDomainWrapper_auto_plic_int_in_53),
    .auto_plic_int_in_54(plicDomainWrapper_auto_plic_int_in_54),
    .auto_plic_int_in_55(plicDomainWrapper_auto_plic_int_in_55),
    .auto_plic_int_out_1_0(plicDomainWrapper_auto_plic_int_out_1_0),
    .auto_plic_int_out_0_0(plicDomainWrapper_auto_plic_int_out_0_0),
    .auto_plic_in_a_ready(plicDomainWrapper_auto_plic_in_a_ready),
    .auto_plic_in_a_valid(plicDomainWrapper_auto_plic_in_a_valid),
    .auto_plic_in_a_bits_opcode(plicDomainWrapper_auto_plic_in_a_bits_opcode),
    .auto_plic_in_a_bits_param(plicDomainWrapper_auto_plic_in_a_bits_param),
    .auto_plic_in_a_bits_size(plicDomainWrapper_auto_plic_in_a_bits_size),
    .auto_plic_in_a_bits_source(plicDomainWrapper_auto_plic_in_a_bits_source),
    .auto_plic_in_a_bits_address(plicDomainWrapper_auto_plic_in_a_bits_address),
    .auto_plic_in_a_bits_mask(plicDomainWrapper_auto_plic_in_a_bits_mask),
    .auto_plic_in_a_bits_data(plicDomainWrapper_auto_plic_in_a_bits_data),
    .auto_plic_in_a_bits_corrupt(plicDomainWrapper_auto_plic_in_a_bits_corrupt),
    .auto_plic_in_d_ready(plicDomainWrapper_auto_plic_in_d_ready),
    .auto_plic_in_d_valid(plicDomainWrapper_auto_plic_in_d_valid),
    .auto_plic_in_d_bits_opcode(plicDomainWrapper_auto_plic_in_d_bits_opcode),
    .auto_plic_in_d_bits_size(plicDomainWrapper_auto_plic_in_d_bits_size),
    .auto_plic_in_d_bits_source(plicDomainWrapper_auto_plic_in_d_bits_source),
    .auto_plic_in_d_bits_data(plicDomainWrapper_auto_plic_in_d_bits_data),
    .auto_clock_in_clock(plicDomainWrapper_auto_clock_in_clock),
    .auto_clock_in_reset(plicDomainWrapper_auto_clock_in_reset)
  );
  CLINT clint ( // @[CLINT.scala 109:27]
    .clock(clint_clock),
    .reset(clint_reset),
    .auto_int_out_0(clint_auto_int_out_0),
    .auto_int_out_1(clint_auto_int_out_1),
    .auto_in_a_ready(clint_auto_in_a_ready),
    .auto_in_a_valid(clint_auto_in_a_valid),
    .auto_in_a_bits_opcode(clint_auto_in_a_bits_opcode),
    .auto_in_a_bits_param(clint_auto_in_a_bits_param),
    .auto_in_a_bits_size(clint_auto_in_a_bits_size),
    .auto_in_a_bits_source(clint_auto_in_a_bits_source),
    .auto_in_a_bits_address(clint_auto_in_a_bits_address),
    .auto_in_a_bits_mask(clint_auto_in_a_bits_mask),
    .auto_in_a_bits_data(clint_auto_in_a_bits_data),
    .auto_in_a_bits_corrupt(clint_auto_in_a_bits_corrupt),
    .auto_in_d_ready(clint_auto_in_d_ready),
    .auto_in_d_valid(clint_auto_in_d_valid),
    .auto_in_d_bits_opcode(clint_auto_in_d_bits_opcode),
    .auto_in_d_bits_size(clint_auto_in_d_bits_size),
    .auto_in_d_bits_source(clint_auto_in_d_bits_source),
    .auto_in_d_bits_data(clint_auto_in_d_bits_data),
    .io_rtcTick(clint_io_rtcTick)
  );
  TLDebugModule debug_1 ( // @[Periphery.scala 84:27]
    .auto_dmInner_dmInner_tl_in_a_ready(debug_1_auto_dmInner_dmInner_tl_in_a_ready),
    .auto_dmInner_dmInner_tl_in_a_valid(debug_1_auto_dmInner_dmInner_tl_in_a_valid),
    .auto_dmInner_dmInner_tl_in_a_bits_opcode(debug_1_auto_dmInner_dmInner_tl_in_a_bits_opcode),
    .auto_dmInner_dmInner_tl_in_a_bits_param(debug_1_auto_dmInner_dmInner_tl_in_a_bits_param),
    .auto_dmInner_dmInner_tl_in_a_bits_size(debug_1_auto_dmInner_dmInner_tl_in_a_bits_size),
    .auto_dmInner_dmInner_tl_in_a_bits_source(debug_1_auto_dmInner_dmInner_tl_in_a_bits_source),
    .auto_dmInner_dmInner_tl_in_a_bits_address(debug_1_auto_dmInner_dmInner_tl_in_a_bits_address),
    .auto_dmInner_dmInner_tl_in_a_bits_mask(debug_1_auto_dmInner_dmInner_tl_in_a_bits_mask),
    .auto_dmInner_dmInner_tl_in_a_bits_data(debug_1_auto_dmInner_dmInner_tl_in_a_bits_data),
    .auto_dmInner_dmInner_tl_in_a_bits_corrupt(debug_1_auto_dmInner_dmInner_tl_in_a_bits_corrupt),
    .auto_dmInner_dmInner_tl_in_d_ready(debug_1_auto_dmInner_dmInner_tl_in_d_ready),
    .auto_dmInner_dmInner_tl_in_d_valid(debug_1_auto_dmInner_dmInner_tl_in_d_valid),
    .auto_dmInner_dmInner_tl_in_d_bits_opcode(debug_1_auto_dmInner_dmInner_tl_in_d_bits_opcode),
    .auto_dmInner_dmInner_tl_in_d_bits_size(debug_1_auto_dmInner_dmInner_tl_in_d_bits_size),
    .auto_dmInner_dmInner_tl_in_d_bits_source(debug_1_auto_dmInner_dmInner_tl_in_d_bits_source),
    .auto_dmInner_dmInner_tl_in_d_bits_data(debug_1_auto_dmInner_dmInner_tl_in_d_bits_data),
    .auto_dmOuter_intsource_out_sync_0(debug_1_auto_dmOuter_intsource_out_sync_0),
    .io_debug_clock(debug_1_io_debug_clock),
    .io_ctrl_ndreset(debug_1_io_ctrl_ndreset),
    .io_dmi_dmi_req_ready(debug_1_io_dmi_dmi_req_ready),
    .io_dmi_dmi_req_valid(debug_1_io_dmi_dmi_req_valid),
    .io_dmi_dmi_req_bits_addr(debug_1_io_dmi_dmi_req_bits_addr),
    .io_dmi_dmi_req_bits_data(debug_1_io_dmi_dmi_req_bits_data),
    .io_dmi_dmi_req_bits_op(debug_1_io_dmi_dmi_req_bits_op),
    .io_dmi_dmi_resp_ready(debug_1_io_dmi_dmi_resp_ready),
    .io_dmi_dmi_resp_valid(debug_1_io_dmi_dmi_resp_valid),
    .io_dmi_dmi_resp_bits_data(debug_1_io_dmi_dmi_resp_bits_data),
    .io_dmi_dmi_resp_bits_resp(debug_1_io_dmi_dmi_resp_bits_resp),
    .io_dmi_dmiClock(debug_1_io_dmi_dmiClock),
    .io_dmi_dmiReset(debug_1_io_dmi_dmiReset)
  );
  BundleBridgeNexus_15 tileHartIdNexusNode ( // @[HasTiles.scala 159:39]
    .auto_out(tileHartIdNexusNode_auto_out)
  );
  IntSyncCrossingSource_5 intsource ( // @[Crossing.scala 26:31]
    .clock(intsource_clock),
    .reset(intsource_reset),
    .auto_in_0(intsource_auto_in_0),
    .auto_in_1(intsource_auto_in_1),
    .auto_out_sync_0(intsource_auto_out_sync_0),
    .auto_out_sync_1(intsource_auto_out_sync_1)
  );
  IntSyncCrossingSource_1 intsource_1 ( // @[Crossing.scala 26:31]
    .clock(intsource_1_clock),
    .reset(intsource_1_reset),
    .auto_in_0(intsource_1_auto_in_0),
    .auto_out_sync_0(intsource_1_auto_out_sync_0)
  );
  IntSyncCrossingSource_1 intsource_2 ( // @[Crossing.scala 26:31]
    .clock(intsource_2_clock),
    .reset(intsource_2_reset),
    .auto_in_0(intsource_2_auto_in_0),
    .auto_out_sync_0(intsource_2_auto_out_sync_0)
  );
  IntSyncSyncCrossingSink_1 intsink_1 ( // @[Crossing.scala 94:29]
    .auto_in_sync_0(intsink_1_auto_in_sync_0),
    .auto_out_0(intsink_1_auto_out_0)
  );
  IntSyncSyncCrossingSink_1 intsink_2 ( // @[Crossing.scala 94:29]
    .auto_in_sync_0(intsink_2_auto_in_sync_0),
    .auto_out_0(intsink_2_auto_out_0)
  );
  IntSyncSyncCrossingSink_1 intsink_3 ( // @[Crossing.scala 94:29]
    .auto_in_sync_0(intsink_3_auto_in_sync_0),
    .auto_out_0(intsink_3_auto_out_0)
  );
  MockAONWrapper aon_1 ( // @[MockAONPeriphery.scala 21:23]
    .auto_intsource_out_sync_0(aon_1_auto_intsource_out_sync_0),
    .auto_intsource_out_sync_1(aon_1_auto_intsource_out_sync_1),
    .auto_isolation_in_a_mem_0_opcode(aon_1_auto_isolation_in_a_mem_0_opcode),
    .auto_isolation_in_a_mem_0_param(aon_1_auto_isolation_in_a_mem_0_param),
    .auto_isolation_in_a_mem_0_size(aon_1_auto_isolation_in_a_mem_0_size),
    .auto_isolation_in_a_mem_0_source(aon_1_auto_isolation_in_a_mem_0_source),
    .auto_isolation_in_a_mem_0_address(aon_1_auto_isolation_in_a_mem_0_address),
    .auto_isolation_in_a_mem_0_mask(aon_1_auto_isolation_in_a_mem_0_mask),
    .auto_isolation_in_a_mem_0_data(aon_1_auto_isolation_in_a_mem_0_data),
    .auto_isolation_in_a_mem_0_corrupt(aon_1_auto_isolation_in_a_mem_0_corrupt),
    .auto_isolation_in_a_ridx(aon_1_auto_isolation_in_a_ridx),
    .auto_isolation_in_a_widx(aon_1_auto_isolation_in_a_widx),
    .auto_isolation_in_a_safe_ridx_valid(aon_1_auto_isolation_in_a_safe_ridx_valid),
    .auto_isolation_in_a_safe_widx_valid(aon_1_auto_isolation_in_a_safe_widx_valid),
    .auto_isolation_in_a_safe_source_reset_n(aon_1_auto_isolation_in_a_safe_source_reset_n),
    .auto_isolation_in_a_safe_sink_reset_n(aon_1_auto_isolation_in_a_safe_sink_reset_n),
    .auto_isolation_in_d_mem_0_opcode(aon_1_auto_isolation_in_d_mem_0_opcode),
    .auto_isolation_in_d_mem_0_param(aon_1_auto_isolation_in_d_mem_0_param),
    .auto_isolation_in_d_mem_0_size(aon_1_auto_isolation_in_d_mem_0_size),
    .auto_isolation_in_d_mem_0_source(aon_1_auto_isolation_in_d_mem_0_source),
    .auto_isolation_in_d_mem_0_sink(aon_1_auto_isolation_in_d_mem_0_sink),
    .auto_isolation_in_d_mem_0_denied(aon_1_auto_isolation_in_d_mem_0_denied),
    .auto_isolation_in_d_mem_0_data(aon_1_auto_isolation_in_d_mem_0_data),
    .auto_isolation_in_d_mem_0_corrupt(aon_1_auto_isolation_in_d_mem_0_corrupt),
    .auto_isolation_in_d_ridx(aon_1_auto_isolation_in_d_ridx),
    .auto_isolation_in_d_widx(aon_1_auto_isolation_in_d_widx),
    .auto_isolation_in_d_safe_ridx_valid(aon_1_auto_isolation_in_d_safe_ridx_valid),
    .auto_isolation_in_d_safe_widx_valid(aon_1_auto_isolation_in_d_safe_widx_valid),
    .auto_isolation_in_d_safe_source_reset_n(aon_1_auto_isolation_in_d_safe_source_reset_n),
    .auto_isolation_in_d_safe_sink_reset_n(aon_1_auto_isolation_in_d_safe_sink_reset_n),
    .io_pins_erst_n_i_ival(aon_1_io_pins_erst_n_i_ival),
    .io_pins_lfextclk_i_ival(aon_1_io_pins_lfextclk_i_ival),
    .io_rsts_corerst(aon_1_io_rsts_corerst),
    .io_rtc(aon_1_io_rtc),
    .io_ndreset(aon_1_io_ndreset)
  );
  IntSyncAsyncCrossingSink_1 intsink_4 ( // @[Crossing.scala 74:29]
    .clock(intsink_4_clock),
    .auto_in_sync_0(intsink_4_auto_in_sync_0),
    .auto_in_sync_1(intsink_4_auto_in_sync_1),
    .auto_out_0(intsink_4_auto_out_0),
    .auto_out_1(intsink_4_auto_out_1)
  );
  ClockSinkDomain_1 uartClockDomainWrapper ( // @[UART.scala 242:44]
    .auto_uart_0_int_xing_out_sync_0(uartClockDomainWrapper_auto_uart_0_int_xing_out_sync_0),
    .auto_uart_0_control_xing_in_a_ready(uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready),
    .auto_uart_0_control_xing_in_a_valid(uartClockDomainWrapper_auto_uart_0_control_xing_in_a_valid),
    .auto_uart_0_control_xing_in_a_bits_opcode(uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_opcode),
    .auto_uart_0_control_xing_in_a_bits_param(uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_param),
    .auto_uart_0_control_xing_in_a_bits_size(uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_size),
    .auto_uart_0_control_xing_in_a_bits_source(uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_source),
    .auto_uart_0_control_xing_in_a_bits_address(uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_address),
    .auto_uart_0_control_xing_in_a_bits_mask(uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_mask),
    .auto_uart_0_control_xing_in_a_bits_data(uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_data),
    .auto_uart_0_control_xing_in_a_bits_corrupt(uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_corrupt),
    .auto_uart_0_control_xing_in_d_ready(uartClockDomainWrapper_auto_uart_0_control_xing_in_d_ready),
    .auto_uart_0_control_xing_in_d_valid(uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid),
    .auto_uart_0_control_xing_in_d_bits_opcode(uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode),
    .auto_uart_0_control_xing_in_d_bits_size(uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size),
    .auto_uart_0_control_xing_in_d_bits_source(uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source),
    .auto_uart_0_control_xing_in_d_bits_data(uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data),
    .auto_uart_0_io_out_txd(uartClockDomainWrapper_auto_uart_0_io_out_txd),
    .auto_uart_0_io_out_rxd(uartClockDomainWrapper_auto_uart_0_io_out_rxd),
    .auto_clock_in_clock(uartClockDomainWrapper_auto_clock_in_clock),
    .auto_clock_in_reset(uartClockDomainWrapper_auto_clock_in_reset)
  );
  IntSyncSyncCrossingSink_1 intsink_5 ( // @[Crossing.scala 94:29]
    .auto_in_sync_0(intsink_5_auto_in_sync_0),
    .auto_out_0(intsink_5_auto_out_0)
  );
  ClockSinkDomain_2 uartClockDomainWrapper_1 ( // @[UART.scala 242:44]
    .auto_uart_1_int_xing_out_sync_0(uartClockDomainWrapper_1_auto_uart_1_int_xing_out_sync_0),
    .auto_uart_1_control_xing_in_a_ready(uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_ready),
    .auto_uart_1_control_xing_in_a_valid(uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_valid),
    .auto_uart_1_control_xing_in_a_bits_opcode(uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_opcode),
    .auto_uart_1_control_xing_in_a_bits_param(uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_param),
    .auto_uart_1_control_xing_in_a_bits_size(uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_size),
    .auto_uart_1_control_xing_in_a_bits_source(uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_source),
    .auto_uart_1_control_xing_in_a_bits_address(uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_address),
    .auto_uart_1_control_xing_in_a_bits_mask(uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_mask),
    .auto_uart_1_control_xing_in_a_bits_data(uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_data),
    .auto_uart_1_control_xing_in_a_bits_corrupt(uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_corrupt),
    .auto_uart_1_control_xing_in_d_ready(uartClockDomainWrapper_1_auto_uart_1_control_xing_in_d_ready),
    .auto_uart_1_control_xing_in_d_valid(uartClockDomainWrapper_1_auto_uart_1_control_xing_in_d_valid),
    .auto_uart_1_control_xing_in_d_bits_opcode(uartClockDomainWrapper_1_auto_uart_1_control_xing_in_d_bits_opcode),
    .auto_uart_1_control_xing_in_d_bits_size(uartClockDomainWrapper_1_auto_uart_1_control_xing_in_d_bits_size),
    .auto_uart_1_control_xing_in_d_bits_source(uartClockDomainWrapper_1_auto_uart_1_control_xing_in_d_bits_source),
    .auto_uart_1_control_xing_in_d_bits_data(uartClockDomainWrapper_1_auto_uart_1_control_xing_in_d_bits_data),
    .auto_uart_1_io_out_txd(uartClockDomainWrapper_1_auto_uart_1_io_out_txd),
    .auto_uart_1_io_out_rxd(uartClockDomainWrapper_1_auto_uart_1_io_out_rxd),
    .auto_clock_in_clock(uartClockDomainWrapper_1_auto_clock_in_clock),
    .auto_clock_in_reset(uartClockDomainWrapper_1_auto_clock_in_reset)
  );
  IntSyncSyncCrossingSink_1 intsink_6 ( // @[Crossing.scala 94:29]
    .auto_in_sync_0(intsink_6_auto_in_sync_0),
    .auto_out_0(intsink_6_auto_out_0)
  );
  ClockSinkDomain_3 uartClockDomainWrapper_2 ( // @[UART.scala 242:44]
    .auto_uart_2_int_xing_out_sync_0(uartClockDomainWrapper_2_auto_uart_2_int_xing_out_sync_0),
    .auto_uart_2_control_xing_in_a_ready(uartClockDomainWrapper_2_auto_uart_2_control_xing_in_a_ready),
    .auto_uart_2_control_xing_in_a_valid(uartClockDomainWrapper_2_auto_uart_2_control_xing_in_a_valid),
    .auto_uart_2_control_xing_in_a_bits_opcode(uartClockDomainWrapper_2_auto_uart_2_control_xing_in_a_bits_opcode),
    .auto_uart_2_control_xing_in_a_bits_param(uartClockDomainWrapper_2_auto_uart_2_control_xing_in_a_bits_param),
    .auto_uart_2_control_xing_in_a_bits_size(uartClockDomainWrapper_2_auto_uart_2_control_xing_in_a_bits_size),
    .auto_uart_2_control_xing_in_a_bits_source(uartClockDomainWrapper_2_auto_uart_2_control_xing_in_a_bits_source),
    .auto_uart_2_control_xing_in_a_bits_address(uartClockDomainWrapper_2_auto_uart_2_control_xing_in_a_bits_address),
    .auto_uart_2_control_xing_in_a_bits_mask(uartClockDomainWrapper_2_auto_uart_2_control_xing_in_a_bits_mask),
    .auto_uart_2_control_xing_in_a_bits_data(uartClockDomainWrapper_2_auto_uart_2_control_xing_in_a_bits_data),
    .auto_uart_2_control_xing_in_a_bits_corrupt(uartClockDomainWrapper_2_auto_uart_2_control_xing_in_a_bits_corrupt),
    .auto_uart_2_control_xing_in_d_ready(uartClockDomainWrapper_2_auto_uart_2_control_xing_in_d_ready),
    .auto_uart_2_control_xing_in_d_valid(uartClockDomainWrapper_2_auto_uart_2_control_xing_in_d_valid),
    .auto_uart_2_control_xing_in_d_bits_opcode(uartClockDomainWrapper_2_auto_uart_2_control_xing_in_d_bits_opcode),
    .auto_uart_2_control_xing_in_d_bits_size(uartClockDomainWrapper_2_auto_uart_2_control_xing_in_d_bits_size),
    .auto_uart_2_control_xing_in_d_bits_source(uartClockDomainWrapper_2_auto_uart_2_control_xing_in_d_bits_source),
    .auto_uart_2_control_xing_in_d_bits_data(uartClockDomainWrapper_2_auto_uart_2_control_xing_in_d_bits_data),
    .auto_uart_2_io_out_txd(uartClockDomainWrapper_2_auto_uart_2_io_out_txd),
    .auto_uart_2_io_out_rxd(uartClockDomainWrapper_2_auto_uart_2_io_out_rxd),
    .auto_clock_in_clock(uartClockDomainWrapper_2_auto_clock_in_clock),
    .auto_clock_in_reset(uartClockDomainWrapper_2_auto_clock_in_reset)
  );
  IntSyncSyncCrossingSink_1 intsink_7 ( // @[Crossing.scala 94:29]
    .auto_in_sync_0(intsink_7_auto_in_sync_0),
    .auto_out_0(intsink_7_auto_out_0)
  );
  ClockSinkDomain_4 uartClockDomainWrapper_3 ( // @[UART.scala 242:44]
    .auto_uart_3_int_xing_out_sync_0(uartClockDomainWrapper_3_auto_uart_3_int_xing_out_sync_0),
    .auto_uart_3_control_xing_in_a_ready(uartClockDomainWrapper_3_auto_uart_3_control_xing_in_a_ready),
    .auto_uart_3_control_xing_in_a_valid(uartClockDomainWrapper_3_auto_uart_3_control_xing_in_a_valid),
    .auto_uart_3_control_xing_in_a_bits_opcode(uartClockDomainWrapper_3_auto_uart_3_control_xing_in_a_bits_opcode),
    .auto_uart_3_control_xing_in_a_bits_param(uartClockDomainWrapper_3_auto_uart_3_control_xing_in_a_bits_param),
    .auto_uart_3_control_xing_in_a_bits_size(uartClockDomainWrapper_3_auto_uart_3_control_xing_in_a_bits_size),
    .auto_uart_3_control_xing_in_a_bits_source(uartClockDomainWrapper_3_auto_uart_3_control_xing_in_a_bits_source),
    .auto_uart_3_control_xing_in_a_bits_address(uartClockDomainWrapper_3_auto_uart_3_control_xing_in_a_bits_address),
    .auto_uart_3_control_xing_in_a_bits_mask(uartClockDomainWrapper_3_auto_uart_3_control_xing_in_a_bits_mask),
    .auto_uart_3_control_xing_in_a_bits_data(uartClockDomainWrapper_3_auto_uart_3_control_xing_in_a_bits_data),
    .auto_uart_3_control_xing_in_a_bits_corrupt(uartClockDomainWrapper_3_auto_uart_3_control_xing_in_a_bits_corrupt),
    .auto_uart_3_control_xing_in_d_ready(uartClockDomainWrapper_3_auto_uart_3_control_xing_in_d_ready),
    .auto_uart_3_control_xing_in_d_valid(uartClockDomainWrapper_3_auto_uart_3_control_xing_in_d_valid),
    .auto_uart_3_control_xing_in_d_bits_opcode(uartClockDomainWrapper_3_auto_uart_3_control_xing_in_d_bits_opcode),
    .auto_uart_3_control_xing_in_d_bits_size(uartClockDomainWrapper_3_auto_uart_3_control_xing_in_d_bits_size),
    .auto_uart_3_control_xing_in_d_bits_source(uartClockDomainWrapper_3_auto_uart_3_control_xing_in_d_bits_source),
    .auto_uart_3_control_xing_in_d_bits_data(uartClockDomainWrapper_3_auto_uart_3_control_xing_in_d_bits_data),
    .auto_uart_3_io_out_txd(uartClockDomainWrapper_3_auto_uart_3_io_out_txd),
    .auto_uart_3_io_out_rxd(uartClockDomainWrapper_3_auto_uart_3_io_out_rxd),
    .auto_clock_in_clock(uartClockDomainWrapper_3_auto_clock_in_clock),
    .auto_clock_in_reset(uartClockDomainWrapper_3_auto_clock_in_reset)
  );
  IntSyncSyncCrossingSink_1 intsink_8 ( // @[Crossing.scala 94:29]
    .auto_in_sync_0(intsink_8_auto_in_sync_0),
    .auto_out_0(intsink_8_auto_out_0)
  );
  ClockSinkDomain_5 uartClockDomainWrapper_4 ( // @[UART.scala 242:44]
    .auto_uart_4_int_xing_out_sync_0(uartClockDomainWrapper_4_auto_uart_4_int_xing_out_sync_0),
    .auto_uart_4_control_xing_in_a_ready(uartClockDomainWrapper_4_auto_uart_4_control_xing_in_a_ready),
    .auto_uart_4_control_xing_in_a_valid(uartClockDomainWrapper_4_auto_uart_4_control_xing_in_a_valid),
    .auto_uart_4_control_xing_in_a_bits_opcode(uartClockDomainWrapper_4_auto_uart_4_control_xing_in_a_bits_opcode),
    .auto_uart_4_control_xing_in_a_bits_param(uartClockDomainWrapper_4_auto_uart_4_control_xing_in_a_bits_param),
    .auto_uart_4_control_xing_in_a_bits_size(uartClockDomainWrapper_4_auto_uart_4_control_xing_in_a_bits_size),
    .auto_uart_4_control_xing_in_a_bits_source(uartClockDomainWrapper_4_auto_uart_4_control_xing_in_a_bits_source),
    .auto_uart_4_control_xing_in_a_bits_address(uartClockDomainWrapper_4_auto_uart_4_control_xing_in_a_bits_address),
    .auto_uart_4_control_xing_in_a_bits_mask(uartClockDomainWrapper_4_auto_uart_4_control_xing_in_a_bits_mask),
    .auto_uart_4_control_xing_in_a_bits_data(uartClockDomainWrapper_4_auto_uart_4_control_xing_in_a_bits_data),
    .auto_uart_4_control_xing_in_a_bits_corrupt(uartClockDomainWrapper_4_auto_uart_4_control_xing_in_a_bits_corrupt),
    .auto_uart_4_control_xing_in_d_ready(uartClockDomainWrapper_4_auto_uart_4_control_xing_in_d_ready),
    .auto_uart_4_control_xing_in_d_valid(uartClockDomainWrapper_4_auto_uart_4_control_xing_in_d_valid),
    .auto_uart_4_control_xing_in_d_bits_opcode(uartClockDomainWrapper_4_auto_uart_4_control_xing_in_d_bits_opcode),
    .auto_uart_4_control_xing_in_d_bits_size(uartClockDomainWrapper_4_auto_uart_4_control_xing_in_d_bits_size),
    .auto_uart_4_control_xing_in_d_bits_source(uartClockDomainWrapper_4_auto_uart_4_control_xing_in_d_bits_source),
    .auto_uart_4_control_xing_in_d_bits_data(uartClockDomainWrapper_4_auto_uart_4_control_xing_in_d_bits_data),
    .auto_uart_4_io_out_txd(uartClockDomainWrapper_4_auto_uart_4_io_out_txd),
    .auto_uart_4_io_out_rxd(uartClockDomainWrapper_4_auto_uart_4_io_out_rxd),
    .auto_clock_in_clock(uartClockDomainWrapper_4_auto_clock_in_clock),
    .auto_clock_in_reset(uartClockDomainWrapper_4_auto_clock_in_reset)
  );
  IntSyncSyncCrossingSink_1 intsink_9 ( // @[Crossing.scala 94:29]
    .auto_in_sync_0(intsink_9_auto_in_sync_0),
    .auto_out_0(intsink_9_auto_out_0)
  );
  ClockSinkDomain_6 qspiClockDomainWrapper ( // @[SPI.scala 92:44]
    .auto_qspi_0_int_xing_out_sync_0(qspiClockDomainWrapper_auto_qspi_0_int_xing_out_sync_0),
    .auto_qspi_0_mem_xing_in_a_ready(qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_ready),
    .auto_qspi_0_mem_xing_in_a_valid(qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_valid),
    .auto_qspi_0_mem_xing_in_a_bits_opcode(qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_opcode),
    .auto_qspi_0_mem_xing_in_a_bits_param(qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_param),
    .auto_qspi_0_mem_xing_in_a_bits_size(qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_size),
    .auto_qspi_0_mem_xing_in_a_bits_source(qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_source),
    .auto_qspi_0_mem_xing_in_a_bits_address(qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_address),
    .auto_qspi_0_mem_xing_in_a_bits_mask(qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_mask),
    .auto_qspi_0_mem_xing_in_a_bits_corrupt(qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_corrupt),
    .auto_qspi_0_mem_xing_in_d_ready(qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_d_ready),
    .auto_qspi_0_mem_xing_in_d_valid(qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_d_valid),
    .auto_qspi_0_mem_xing_in_d_bits_size(qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_d_bits_size),
    .auto_qspi_0_mem_xing_in_d_bits_source(qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_d_bits_source),
    .auto_qspi_0_mem_xing_in_d_bits_data(qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_d_bits_data),
    .auto_qspi_0_control_xing_in_a_ready(qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_ready),
    .auto_qspi_0_control_xing_in_a_valid(qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_valid),
    .auto_qspi_0_control_xing_in_a_bits_opcode(qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_opcode),
    .auto_qspi_0_control_xing_in_a_bits_param(qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_param),
    .auto_qspi_0_control_xing_in_a_bits_size(qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_size),
    .auto_qspi_0_control_xing_in_a_bits_source(qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_source),
    .auto_qspi_0_control_xing_in_a_bits_address(qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_address),
    .auto_qspi_0_control_xing_in_a_bits_mask(qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_mask),
    .auto_qspi_0_control_xing_in_a_bits_data(qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_data),
    .auto_qspi_0_control_xing_in_a_bits_corrupt(qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_corrupt),
    .auto_qspi_0_control_xing_in_d_ready(qspiClockDomainWrapper_auto_qspi_0_control_xing_in_d_ready),
    .auto_qspi_0_control_xing_in_d_valid(qspiClockDomainWrapper_auto_qspi_0_control_xing_in_d_valid),
    .auto_qspi_0_control_xing_in_d_bits_opcode(qspiClockDomainWrapper_auto_qspi_0_control_xing_in_d_bits_opcode),
    .auto_qspi_0_control_xing_in_d_bits_size(qspiClockDomainWrapper_auto_qspi_0_control_xing_in_d_bits_size),
    .auto_qspi_0_control_xing_in_d_bits_source(qspiClockDomainWrapper_auto_qspi_0_control_xing_in_d_bits_source),
    .auto_qspi_0_control_xing_in_d_bits_data(qspiClockDomainWrapper_auto_qspi_0_control_xing_in_d_bits_data),
    .auto_qspi_0_io_out_sck(qspiClockDomainWrapper_auto_qspi_0_io_out_sck),
    .auto_qspi_0_io_out_dq_0_i(qspiClockDomainWrapper_auto_qspi_0_io_out_dq_0_i),
    .auto_qspi_0_io_out_dq_0_o(qspiClockDomainWrapper_auto_qspi_0_io_out_dq_0_o),
    .auto_qspi_0_io_out_dq_0_oe(qspiClockDomainWrapper_auto_qspi_0_io_out_dq_0_oe),
    .auto_qspi_0_io_out_dq_1_i(qspiClockDomainWrapper_auto_qspi_0_io_out_dq_1_i),
    .auto_qspi_0_io_out_dq_1_o(qspiClockDomainWrapper_auto_qspi_0_io_out_dq_1_o),
    .auto_qspi_0_io_out_dq_1_oe(qspiClockDomainWrapper_auto_qspi_0_io_out_dq_1_oe),
    .auto_qspi_0_io_out_dq_2_i(qspiClockDomainWrapper_auto_qspi_0_io_out_dq_2_i),
    .auto_qspi_0_io_out_dq_2_o(qspiClockDomainWrapper_auto_qspi_0_io_out_dq_2_o),
    .auto_qspi_0_io_out_dq_2_oe(qspiClockDomainWrapper_auto_qspi_0_io_out_dq_2_oe),
    .auto_qspi_0_io_out_dq_3_i(qspiClockDomainWrapper_auto_qspi_0_io_out_dq_3_i),
    .auto_qspi_0_io_out_dq_3_o(qspiClockDomainWrapper_auto_qspi_0_io_out_dq_3_o),
    .auto_qspi_0_io_out_dq_3_oe(qspiClockDomainWrapper_auto_qspi_0_io_out_dq_3_oe),
    .auto_qspi_0_io_out_cs_0(qspiClockDomainWrapper_auto_qspi_0_io_out_cs_0),
    .auto_clock_in_clock(qspiClockDomainWrapper_auto_clock_in_clock),
    .auto_clock_in_reset(qspiClockDomainWrapper_auto_clock_in_reset)
  );
  IntSyncSyncCrossingSink_1 intsink_10 ( // @[Crossing.scala 94:29]
    .auto_in_sync_0(intsink_10_auto_in_sync_0),
    .auto_out_0(intsink_10_auto_out_0)
  );
  ClockSinkDomain_7 qspiClockDomainWrapper_1 ( // @[SPI.scala 39:44]
    .auto_qspi_ram_0_int_xing_out_sync_0(qspiClockDomainWrapper_1_auto_qspi_ram_0_int_xing_out_sync_0),
    .auto_qspi_ram_0_mem_xing_in_a_ready(qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_a_ready),
    .auto_qspi_ram_0_mem_xing_in_a_valid(qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_a_valid),
    .auto_qspi_ram_0_mem_xing_in_a_bits_opcode(qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_a_bits_opcode),
    .auto_qspi_ram_0_mem_xing_in_a_bits_param(qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_a_bits_param),
    .auto_qspi_ram_0_mem_xing_in_a_bits_size(qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_a_bits_size),
    .auto_qspi_ram_0_mem_xing_in_a_bits_source(qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_a_bits_source),
    .auto_qspi_ram_0_mem_xing_in_a_bits_address(qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_a_bits_address),
    .auto_qspi_ram_0_mem_xing_in_a_bits_mask(qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_a_bits_mask),
    .auto_qspi_ram_0_mem_xing_in_a_bits_data(qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_a_bits_data),
    .auto_qspi_ram_0_mem_xing_in_a_bits_corrupt(qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_a_bits_corrupt),
    .auto_qspi_ram_0_mem_xing_in_d_ready(qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_d_ready),
    .auto_qspi_ram_0_mem_xing_in_d_valid(qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_d_valid),
    .auto_qspi_ram_0_mem_xing_in_d_bits_opcode(qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_d_bits_opcode),
    .auto_qspi_ram_0_mem_xing_in_d_bits_size(qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_d_bits_size),
    .auto_qspi_ram_0_mem_xing_in_d_bits_source(qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_d_bits_source),
    .auto_qspi_ram_0_mem_xing_in_d_bits_data(qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_d_bits_data),
    .auto_qspi_ram_0_control_xing_in_a_ready(qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_a_ready),
    .auto_qspi_ram_0_control_xing_in_a_valid(qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_a_valid),
    .auto_qspi_ram_0_control_xing_in_a_bits_opcode(
      qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_a_bits_opcode),
    .auto_qspi_ram_0_control_xing_in_a_bits_param(qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_a_bits_param)
      ,
    .auto_qspi_ram_0_control_xing_in_a_bits_size(qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_a_bits_size),
    .auto_qspi_ram_0_control_xing_in_a_bits_source(
      qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_a_bits_source),
    .auto_qspi_ram_0_control_xing_in_a_bits_address(
      qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_a_bits_address),
    .auto_qspi_ram_0_control_xing_in_a_bits_mask(qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_a_bits_mask),
    .auto_qspi_ram_0_control_xing_in_a_bits_data(qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_a_bits_data),
    .auto_qspi_ram_0_control_xing_in_a_bits_corrupt(
      qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_a_bits_corrupt),
    .auto_qspi_ram_0_control_xing_in_d_ready(qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_d_ready),
    .auto_qspi_ram_0_control_xing_in_d_valid(qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_d_valid),
    .auto_qspi_ram_0_control_xing_in_d_bits_opcode(
      qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_d_bits_opcode),
    .auto_qspi_ram_0_control_xing_in_d_bits_size(qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_d_bits_size),
    .auto_qspi_ram_0_control_xing_in_d_bits_source(
      qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_d_bits_source),
    .auto_qspi_ram_0_control_xing_in_d_bits_data(qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_d_bits_data),
    .auto_qspi_ram_0_io_out_sck(qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_sck),
    .auto_qspi_ram_0_io_out_dq_0_i(qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_dq_0_i),
    .auto_qspi_ram_0_io_out_dq_0_o(qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_dq_0_o),
    .auto_qspi_ram_0_io_out_dq_0_oe(qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_dq_0_oe),
    .auto_qspi_ram_0_io_out_dq_1_i(qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_dq_1_i),
    .auto_qspi_ram_0_io_out_dq_1_o(qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_dq_1_o),
    .auto_qspi_ram_0_io_out_dq_1_oe(qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_dq_1_oe),
    .auto_qspi_ram_0_io_out_dq_2_i(qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_dq_2_i),
    .auto_qspi_ram_0_io_out_dq_2_o(qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_dq_2_o),
    .auto_qspi_ram_0_io_out_dq_2_oe(qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_dq_2_oe),
    .auto_qspi_ram_0_io_out_dq_3_i(qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_dq_3_i),
    .auto_qspi_ram_0_io_out_dq_3_o(qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_dq_3_o),
    .auto_qspi_ram_0_io_out_dq_3_oe(qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_dq_3_oe),
    .auto_qspi_ram_0_io_out_cs_0(qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_cs_0),
    .auto_clock_in_clock(qspiClockDomainWrapper_1_auto_clock_in_clock),
    .auto_clock_in_reset(qspiClockDomainWrapper_1_auto_clock_in_reset)
  );
  IntSyncSyncCrossingSink_1 intsink_11 ( // @[Crossing.scala 94:29]
    .auto_in_sync_0(intsink_11_auto_in_sync_0),
    .auto_out_0(intsink_11_auto_out_0)
  );
  ClockSinkDomain_8 spiClockDomainWrapper ( // @[SPI.scala 35:43]
    .auto_spi_0_int_xing_out_sync_0(spiClockDomainWrapper_auto_spi_0_int_xing_out_sync_0),
    .auto_spi_0_control_xing_in_a_ready(spiClockDomainWrapper_auto_spi_0_control_xing_in_a_ready),
    .auto_spi_0_control_xing_in_a_valid(spiClockDomainWrapper_auto_spi_0_control_xing_in_a_valid),
    .auto_spi_0_control_xing_in_a_bits_opcode(spiClockDomainWrapper_auto_spi_0_control_xing_in_a_bits_opcode),
    .auto_spi_0_control_xing_in_a_bits_param(spiClockDomainWrapper_auto_spi_0_control_xing_in_a_bits_param),
    .auto_spi_0_control_xing_in_a_bits_size(spiClockDomainWrapper_auto_spi_0_control_xing_in_a_bits_size),
    .auto_spi_0_control_xing_in_a_bits_source(spiClockDomainWrapper_auto_spi_0_control_xing_in_a_bits_source),
    .auto_spi_0_control_xing_in_a_bits_address(spiClockDomainWrapper_auto_spi_0_control_xing_in_a_bits_address),
    .auto_spi_0_control_xing_in_a_bits_mask(spiClockDomainWrapper_auto_spi_0_control_xing_in_a_bits_mask),
    .auto_spi_0_control_xing_in_a_bits_data(spiClockDomainWrapper_auto_spi_0_control_xing_in_a_bits_data),
    .auto_spi_0_control_xing_in_a_bits_corrupt(spiClockDomainWrapper_auto_spi_0_control_xing_in_a_bits_corrupt),
    .auto_spi_0_control_xing_in_d_ready(spiClockDomainWrapper_auto_spi_0_control_xing_in_d_ready),
    .auto_spi_0_control_xing_in_d_valid(spiClockDomainWrapper_auto_spi_0_control_xing_in_d_valid),
    .auto_spi_0_control_xing_in_d_bits_opcode(spiClockDomainWrapper_auto_spi_0_control_xing_in_d_bits_opcode),
    .auto_spi_0_control_xing_in_d_bits_size(spiClockDomainWrapper_auto_spi_0_control_xing_in_d_bits_size),
    .auto_spi_0_control_xing_in_d_bits_source(spiClockDomainWrapper_auto_spi_0_control_xing_in_d_bits_source),
    .auto_spi_0_control_xing_in_d_bits_data(spiClockDomainWrapper_auto_spi_0_control_xing_in_d_bits_data),
    .auto_spi_0_io_out_sck(spiClockDomainWrapper_auto_spi_0_io_out_sck),
    .auto_spi_0_io_out_dq_0_i(spiClockDomainWrapper_auto_spi_0_io_out_dq_0_i),
    .auto_spi_0_io_out_dq_0_o(spiClockDomainWrapper_auto_spi_0_io_out_dq_0_o),
    .auto_spi_0_io_out_dq_0_oe(spiClockDomainWrapper_auto_spi_0_io_out_dq_0_oe),
    .auto_spi_0_io_out_dq_1_i(spiClockDomainWrapper_auto_spi_0_io_out_dq_1_i),
    .auto_spi_0_io_out_dq_1_o(spiClockDomainWrapper_auto_spi_0_io_out_dq_1_o),
    .auto_spi_0_io_out_dq_1_oe(spiClockDomainWrapper_auto_spi_0_io_out_dq_1_oe),
    .auto_spi_0_io_out_dq_2_i(spiClockDomainWrapper_auto_spi_0_io_out_dq_2_i),
    .auto_spi_0_io_out_dq_2_o(spiClockDomainWrapper_auto_spi_0_io_out_dq_2_o),
    .auto_spi_0_io_out_dq_2_oe(spiClockDomainWrapper_auto_spi_0_io_out_dq_2_oe),
    .auto_spi_0_io_out_dq_3_i(spiClockDomainWrapper_auto_spi_0_io_out_dq_3_i),
    .auto_spi_0_io_out_dq_3_o(spiClockDomainWrapper_auto_spi_0_io_out_dq_3_o),
    .auto_spi_0_io_out_dq_3_oe(spiClockDomainWrapper_auto_spi_0_io_out_dq_3_oe),
    .auto_spi_0_io_out_cs_0(spiClockDomainWrapper_auto_spi_0_io_out_cs_0),
    .auto_spi_0_io_out_cs_1(spiClockDomainWrapper_auto_spi_0_io_out_cs_1),
    .auto_clock_in_clock(spiClockDomainWrapper_auto_clock_in_clock),
    .auto_clock_in_reset(spiClockDomainWrapper_auto_clock_in_reset)
  );
  IntSyncSyncCrossingSink_1 intsink_12 ( // @[Crossing.scala 94:29]
    .auto_in_sync_0(intsink_12_auto_in_sync_0),
    .auto_out_0(intsink_12_auto_out_0)
  );
  ClockSinkDomain_9 gpioClockDomainWrapper ( // @[GPIO.scala 281:44]
    .auto_gpio_0_int_xing_out_sync_0(gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_0),
    .auto_gpio_0_int_xing_out_sync_1(gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_1),
    .auto_gpio_0_int_xing_out_sync_2(gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_2),
    .auto_gpio_0_int_xing_out_sync_3(gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_3),
    .auto_gpio_0_int_xing_out_sync_4(gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_4),
    .auto_gpio_0_int_xing_out_sync_5(gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_5),
    .auto_gpio_0_int_xing_out_sync_6(gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_6),
    .auto_gpio_0_int_xing_out_sync_7(gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_7),
    .auto_gpio_0_int_xing_out_sync_8(gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_8),
    .auto_gpio_0_int_xing_out_sync_9(gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_9),
    .auto_gpio_0_int_xing_out_sync_10(gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_10),
    .auto_gpio_0_int_xing_out_sync_11(gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_11),
    .auto_gpio_0_int_xing_out_sync_12(gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_12),
    .auto_gpio_0_int_xing_out_sync_13(gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_13),
    .auto_gpio_0_int_xing_out_sync_14(gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_14),
    .auto_gpio_0_int_xing_out_sync_15(gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_15),
    .auto_gpio_0_int_xing_out_sync_16(gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_16),
    .auto_gpio_0_int_xing_out_sync_17(gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_17),
    .auto_gpio_0_int_xing_out_sync_18(gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_18),
    .auto_gpio_0_int_xing_out_sync_19(gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_19),
    .auto_gpio_0_int_xing_out_sync_20(gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_20),
    .auto_gpio_0_int_xing_out_sync_21(gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_21),
    .auto_gpio_0_int_xing_out_sync_22(gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_22),
    .auto_gpio_0_int_xing_out_sync_23(gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_23),
    .auto_gpio_0_int_xing_out_sync_24(gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_24),
    .auto_gpio_0_int_xing_out_sync_25(gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_25),
    .auto_gpio_0_int_xing_out_sync_26(gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_26),
    .auto_gpio_0_int_xing_out_sync_27(gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_27),
    .auto_gpio_0_int_xing_out_sync_28(gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_28),
    .auto_gpio_0_int_xing_out_sync_29(gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_29),
    .auto_gpio_0_int_xing_out_sync_30(gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_30),
    .auto_gpio_0_int_xing_out_sync_31(gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_31),
    .auto_gpio_0_control_xing_in_a_ready(gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_ready),
    .auto_gpio_0_control_xing_in_a_valid(gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_valid),
    .auto_gpio_0_control_xing_in_a_bits_opcode(gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_opcode),
    .auto_gpio_0_control_xing_in_a_bits_param(gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_param),
    .auto_gpio_0_control_xing_in_a_bits_size(gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_size),
    .auto_gpio_0_control_xing_in_a_bits_source(gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_source),
    .auto_gpio_0_control_xing_in_a_bits_address(gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_address),
    .auto_gpio_0_control_xing_in_a_bits_mask(gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_mask),
    .auto_gpio_0_control_xing_in_a_bits_data(gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_data),
    .auto_gpio_0_control_xing_in_a_bits_corrupt(gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_corrupt),
    .auto_gpio_0_control_xing_in_d_ready(gpioClockDomainWrapper_auto_gpio_0_control_xing_in_d_ready),
    .auto_gpio_0_control_xing_in_d_valid(gpioClockDomainWrapper_auto_gpio_0_control_xing_in_d_valid),
    .auto_gpio_0_control_xing_in_d_bits_opcode(gpioClockDomainWrapper_auto_gpio_0_control_xing_in_d_bits_opcode),
    .auto_gpio_0_control_xing_in_d_bits_size(gpioClockDomainWrapper_auto_gpio_0_control_xing_in_d_bits_size),
    .auto_gpio_0_control_xing_in_d_bits_source(gpioClockDomainWrapper_auto_gpio_0_control_xing_in_d_bits_source),
    .auto_gpio_0_control_xing_in_d_bits_data(gpioClockDomainWrapper_auto_gpio_0_control_xing_in_d_bits_data),
    .auto_gpio_0_iof_out_iof_0_0_o_oval(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_0_o_oval),
    .auto_gpio_0_iof_out_iof_0_1_o_oval(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_1_o_oval),
    .auto_gpio_0_iof_out_iof_0_2_i_ival(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_2_i_ival),
    .auto_gpio_0_iof_out_iof_0_2_o_oval(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_2_o_oval),
    .auto_gpio_0_iof_out_iof_0_2_o_oe(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_2_o_oe),
    .auto_gpio_0_iof_out_iof_0_2_o_ie(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_2_o_ie),
    .auto_gpio_0_iof_out_iof_0_3_i_ival(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_3_i_ival),
    .auto_gpio_0_iof_out_iof_0_3_o_oval(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_3_o_oval),
    .auto_gpio_0_iof_out_iof_0_3_o_oe(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_3_o_oe),
    .auto_gpio_0_iof_out_iof_0_3_o_ie(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_3_o_ie),
    .auto_gpio_0_iof_out_iof_0_4_i_ival(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_4_i_ival),
    .auto_gpio_0_iof_out_iof_0_4_o_oval(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_4_o_oval),
    .auto_gpio_0_iof_out_iof_0_4_o_oe(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_4_o_oe),
    .auto_gpio_0_iof_out_iof_0_4_o_ie(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_4_o_ie),
    .auto_gpio_0_iof_out_iof_0_5_i_ival(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_5_i_ival),
    .auto_gpio_0_iof_out_iof_0_5_o_oval(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_5_o_oval),
    .auto_gpio_0_iof_out_iof_0_5_o_oe(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_5_o_oe),
    .auto_gpio_0_iof_out_iof_0_5_o_ie(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_5_o_ie),
    .auto_gpio_0_iof_out_iof_0_12_i_ival(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_12_i_ival),
    .auto_gpio_0_iof_out_iof_0_12_o_oe(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_12_o_oe),
    .auto_gpio_0_iof_out_iof_0_13_i_ival(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_13_i_ival),
    .auto_gpio_0_iof_out_iof_0_13_o_oe(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_13_o_oe),
    .auto_gpio_0_iof_out_iof_0_14_i_ival(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_14_i_ival),
    .auto_gpio_0_iof_out_iof_0_14_o_oe(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_14_o_oe),
    .auto_gpio_0_iof_out_iof_0_15_i_ival(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_15_i_ival),
    .auto_gpio_0_iof_out_iof_0_15_o_oe(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_15_o_oe),
    .auto_gpio_0_iof_out_iof_0_16_i_ival(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_16_i_ival),
    .auto_gpio_0_iof_out_iof_0_17_o_oval(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_17_o_oval),
    .auto_gpio_0_iof_out_iof_0_18_i_ival(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_18_i_ival),
    .auto_gpio_0_iof_out_iof_0_19_o_oval(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_19_o_oval),
    .auto_gpio_0_iof_out_iof_0_20_i_ival(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_20_i_ival),
    .auto_gpio_0_iof_out_iof_0_21_o_oval(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_21_o_oval),
    .auto_gpio_0_iof_out_iof_0_22_i_ival(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_22_i_ival),
    .auto_gpio_0_iof_out_iof_0_23_o_oval(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_23_o_oval),
    .auto_gpio_0_iof_out_iof_0_24_o_oval(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_24_o_oval),
    .auto_gpio_0_iof_out_iof_1_12_o_oval(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_1_12_o_oval),
    .auto_gpio_0_iof_out_iof_1_13_o_oval(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_1_13_o_oval),
    .auto_gpio_0_iof_out_iof_1_14_o_oval(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_1_14_o_oval),
    .auto_gpio_0_iof_out_iof_1_15_o_oval(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_1_15_o_oval),
    .auto_gpio_0_iof_out_iof_1_16_o_oval(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_1_16_o_oval),
    .auto_gpio_0_iof_out_iof_1_17_o_oval(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_1_17_o_oval),
    .auto_gpio_0_iof_out_iof_1_18_o_oval(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_1_18_o_oval),
    .auto_gpio_0_iof_out_iof_1_19_o_oval(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_1_19_o_oval),
    .auto_gpio_0_iof_out_iof_1_20_o_oval(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_1_20_o_oval),
    .auto_gpio_0_iof_out_iof_1_21_o_oval(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_1_21_o_oval),
    .auto_gpio_0_iof_out_iof_1_22_o_oval(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_1_22_o_oval),
    .auto_gpio_0_iof_out_iof_1_23_o_oval(gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_1_23_o_oval),
    .auto_gpio_0_io_out_pins_0_i_ival(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_0_i_ival),
    .auto_gpio_0_io_out_pins_0_o_oval(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_0_o_oval),
    .auto_gpio_0_io_out_pins_0_o_oe(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_0_o_oe),
    .auto_gpio_0_io_out_pins_0_o_ie(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_0_o_ie),
    .auto_gpio_0_io_out_pins_1_i_ival(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_1_i_ival),
    .auto_gpio_0_io_out_pins_1_o_oval(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_1_o_oval),
    .auto_gpio_0_io_out_pins_1_o_oe(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_1_o_oe),
    .auto_gpio_0_io_out_pins_1_o_ie(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_1_o_ie),
    .auto_gpio_0_io_out_pins_2_i_ival(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_2_i_ival),
    .auto_gpio_0_io_out_pins_2_o_oval(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_2_o_oval),
    .auto_gpio_0_io_out_pins_2_o_oe(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_2_o_oe),
    .auto_gpio_0_io_out_pins_2_o_ie(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_2_o_ie),
    .auto_gpio_0_io_out_pins_3_i_ival(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_3_i_ival),
    .auto_gpio_0_io_out_pins_3_o_oval(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_3_o_oval),
    .auto_gpio_0_io_out_pins_3_o_oe(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_3_o_oe),
    .auto_gpio_0_io_out_pins_3_o_ie(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_3_o_ie),
    .auto_gpio_0_io_out_pins_4_i_ival(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_4_i_ival),
    .auto_gpio_0_io_out_pins_4_o_oval(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_4_o_oval),
    .auto_gpio_0_io_out_pins_4_o_oe(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_4_o_oe),
    .auto_gpio_0_io_out_pins_4_o_ie(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_4_o_ie),
    .auto_gpio_0_io_out_pins_5_i_ival(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_5_i_ival),
    .auto_gpio_0_io_out_pins_5_o_oval(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_5_o_oval),
    .auto_gpio_0_io_out_pins_5_o_oe(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_5_o_oe),
    .auto_gpio_0_io_out_pins_5_o_ie(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_5_o_ie),
    .auto_gpio_0_io_out_pins_6_i_ival(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_6_i_ival),
    .auto_gpio_0_io_out_pins_6_o_oval(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_6_o_oval),
    .auto_gpio_0_io_out_pins_6_o_oe(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_6_o_oe),
    .auto_gpio_0_io_out_pins_7_i_ival(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_7_i_ival),
    .auto_gpio_0_io_out_pins_7_o_oval(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_7_o_oval),
    .auto_gpio_0_io_out_pins_7_o_oe(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_7_o_oe),
    .auto_gpio_0_io_out_pins_8_i_ival(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_8_i_ival),
    .auto_gpio_0_io_out_pins_8_o_oval(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_8_o_oval),
    .auto_gpio_0_io_out_pins_8_o_oe(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_8_o_oe),
    .auto_gpio_0_io_out_pins_9_i_ival(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_9_i_ival),
    .auto_gpio_0_io_out_pins_9_o_oval(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_9_o_oval),
    .auto_gpio_0_io_out_pins_9_o_oe(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_9_o_oe),
    .auto_gpio_0_io_out_pins_10_i_ival(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_10_i_ival),
    .auto_gpio_0_io_out_pins_10_o_oval(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_10_o_oval),
    .auto_gpio_0_io_out_pins_10_o_oe(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_10_o_oe),
    .auto_gpio_0_io_out_pins_11_i_ival(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_11_i_ival),
    .auto_gpio_0_io_out_pins_11_o_oval(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_11_o_oval),
    .auto_gpio_0_io_out_pins_11_o_oe(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_11_o_oe),
    .auto_gpio_0_io_out_pins_12_i_ival(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_12_i_ival),
    .auto_gpio_0_io_out_pins_12_o_oval(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_12_o_oval),
    .auto_gpio_0_io_out_pins_12_o_oe(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_12_o_oe),
    .auto_gpio_0_io_out_pins_12_o_ie(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_12_o_ie),
    .auto_gpio_0_io_out_pins_13_i_ival(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_13_i_ival),
    .auto_gpio_0_io_out_pins_13_o_oval(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_13_o_oval),
    .auto_gpio_0_io_out_pins_13_o_oe(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_13_o_oe),
    .auto_gpio_0_io_out_pins_13_o_ie(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_13_o_ie),
    .auto_gpio_0_io_out_pins_14_i_ival(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_14_i_ival),
    .auto_gpio_0_io_out_pins_14_o_oval(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_14_o_oval),
    .auto_gpio_0_io_out_pins_14_o_oe(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_14_o_oe),
    .auto_gpio_0_io_out_pins_14_o_ie(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_14_o_ie),
    .auto_gpio_0_io_out_pins_15_i_ival(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_15_i_ival),
    .auto_gpio_0_io_out_pins_15_o_oval(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_15_o_oval),
    .auto_gpio_0_io_out_pins_15_o_oe(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_15_o_oe),
    .auto_gpio_0_io_out_pins_15_o_ie(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_15_o_ie),
    .auto_gpio_0_io_out_pins_16_i_ival(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_16_i_ival),
    .auto_gpio_0_io_out_pins_16_o_oval(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_16_o_oval),
    .auto_gpio_0_io_out_pins_16_o_oe(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_16_o_oe),
    .auto_gpio_0_io_out_pins_16_o_ie(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_16_o_ie),
    .auto_gpio_0_io_out_pins_17_i_ival(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_17_i_ival),
    .auto_gpio_0_io_out_pins_17_o_oval(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_17_o_oval),
    .auto_gpio_0_io_out_pins_17_o_oe(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_17_o_oe),
    .auto_gpio_0_io_out_pins_17_o_ie(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_17_o_ie),
    .auto_gpio_0_io_out_pins_18_i_ival(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_18_i_ival),
    .auto_gpio_0_io_out_pins_18_o_oval(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_18_o_oval),
    .auto_gpio_0_io_out_pins_18_o_oe(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_18_o_oe),
    .auto_gpio_0_io_out_pins_18_o_ie(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_18_o_ie),
    .auto_gpio_0_io_out_pins_19_i_ival(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_19_i_ival),
    .auto_gpio_0_io_out_pins_19_o_oval(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_19_o_oval),
    .auto_gpio_0_io_out_pins_19_o_oe(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_19_o_oe),
    .auto_gpio_0_io_out_pins_19_o_ie(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_19_o_ie),
    .auto_gpio_0_io_out_pins_20_i_ival(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_20_i_ival),
    .auto_gpio_0_io_out_pins_20_o_oval(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_20_o_oval),
    .auto_gpio_0_io_out_pins_20_o_oe(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_20_o_oe),
    .auto_gpio_0_io_out_pins_20_o_ie(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_20_o_ie),
    .auto_gpio_0_io_out_pins_21_i_ival(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_21_i_ival),
    .auto_gpio_0_io_out_pins_21_o_oval(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_21_o_oval),
    .auto_gpio_0_io_out_pins_21_o_oe(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_21_o_oe),
    .auto_gpio_0_io_out_pins_21_o_ie(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_21_o_ie),
    .auto_gpio_0_io_out_pins_22_i_ival(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_22_i_ival),
    .auto_gpio_0_io_out_pins_22_o_oval(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_22_o_oval),
    .auto_gpio_0_io_out_pins_22_o_oe(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_22_o_oe),
    .auto_gpio_0_io_out_pins_22_o_ie(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_22_o_ie),
    .auto_gpio_0_io_out_pins_23_i_ival(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_23_i_ival),
    .auto_gpio_0_io_out_pins_23_o_oval(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_23_o_oval),
    .auto_gpio_0_io_out_pins_23_o_oe(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_23_o_oe),
    .auto_gpio_0_io_out_pins_23_o_ie(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_23_o_ie),
    .auto_gpio_0_io_out_pins_24_i_ival(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_24_i_ival),
    .auto_gpio_0_io_out_pins_24_o_oval(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_24_o_oval),
    .auto_gpio_0_io_out_pins_24_o_oe(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_24_o_oe),
    .auto_gpio_0_io_out_pins_24_o_ie(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_24_o_ie),
    .auto_gpio_0_io_out_pins_25_i_ival(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_25_i_ival),
    .auto_gpio_0_io_out_pins_25_o_oval(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_25_o_oval),
    .auto_gpio_0_io_out_pins_25_o_oe(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_25_o_oe),
    .auto_gpio_0_io_out_pins_26_i_ival(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_26_i_ival),
    .auto_gpio_0_io_out_pins_26_o_oval(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_26_o_oval),
    .auto_gpio_0_io_out_pins_26_o_oe(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_26_o_oe),
    .auto_gpio_0_io_out_pins_27_i_ival(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_27_i_ival),
    .auto_gpio_0_io_out_pins_27_o_oval(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_27_o_oval),
    .auto_gpio_0_io_out_pins_27_o_oe(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_27_o_oe),
    .auto_gpio_0_io_out_pins_28_i_ival(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_28_i_ival),
    .auto_gpio_0_io_out_pins_28_o_oval(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_28_o_oval),
    .auto_gpio_0_io_out_pins_28_o_oe(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_28_o_oe),
    .auto_gpio_0_io_out_pins_29_i_ival(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_29_i_ival),
    .auto_gpio_0_io_out_pins_29_o_oval(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_29_o_oval),
    .auto_gpio_0_io_out_pins_29_o_oe(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_29_o_oe),
    .auto_gpio_0_io_out_pins_30_i_ival(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_30_i_ival),
    .auto_gpio_0_io_out_pins_30_o_oval(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_30_o_oval),
    .auto_gpio_0_io_out_pins_30_o_oe(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_30_o_oe),
    .auto_gpio_0_io_out_pins_31_i_ival(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_31_i_ival),
    .auto_gpio_0_io_out_pins_31_o_oval(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_31_o_oval),
    .auto_gpio_0_io_out_pins_31_o_oe(gpioClockDomainWrapper_auto_gpio_0_io_out_pins_31_o_oe),
    .auto_clock_in_clock(gpioClockDomainWrapper_auto_clock_in_clock),
    .auto_clock_in_reset(gpioClockDomainWrapper_auto_clock_in_reset)
  );
  IntSyncSyncCrossingSink_15 intsink_13 ( // @[Crossing.scala 94:29]
    .auto_in_sync_0(intsink_13_auto_in_sync_0),
    .auto_in_sync_1(intsink_13_auto_in_sync_1),
    .auto_in_sync_2(intsink_13_auto_in_sync_2),
    .auto_in_sync_3(intsink_13_auto_in_sync_3),
    .auto_in_sync_4(intsink_13_auto_in_sync_4),
    .auto_in_sync_5(intsink_13_auto_in_sync_5),
    .auto_in_sync_6(intsink_13_auto_in_sync_6),
    .auto_in_sync_7(intsink_13_auto_in_sync_7),
    .auto_in_sync_8(intsink_13_auto_in_sync_8),
    .auto_in_sync_9(intsink_13_auto_in_sync_9),
    .auto_in_sync_10(intsink_13_auto_in_sync_10),
    .auto_in_sync_11(intsink_13_auto_in_sync_11),
    .auto_in_sync_12(intsink_13_auto_in_sync_12),
    .auto_in_sync_13(intsink_13_auto_in_sync_13),
    .auto_in_sync_14(intsink_13_auto_in_sync_14),
    .auto_in_sync_15(intsink_13_auto_in_sync_15),
    .auto_in_sync_16(intsink_13_auto_in_sync_16),
    .auto_in_sync_17(intsink_13_auto_in_sync_17),
    .auto_in_sync_18(intsink_13_auto_in_sync_18),
    .auto_in_sync_19(intsink_13_auto_in_sync_19),
    .auto_in_sync_20(intsink_13_auto_in_sync_20),
    .auto_in_sync_21(intsink_13_auto_in_sync_21),
    .auto_in_sync_22(intsink_13_auto_in_sync_22),
    .auto_in_sync_23(intsink_13_auto_in_sync_23),
    .auto_in_sync_24(intsink_13_auto_in_sync_24),
    .auto_in_sync_25(intsink_13_auto_in_sync_25),
    .auto_in_sync_26(intsink_13_auto_in_sync_26),
    .auto_in_sync_27(intsink_13_auto_in_sync_27),
    .auto_in_sync_28(intsink_13_auto_in_sync_28),
    .auto_in_sync_29(intsink_13_auto_in_sync_29),
    .auto_in_sync_30(intsink_13_auto_in_sync_30),
    .auto_in_sync_31(intsink_13_auto_in_sync_31),
    .auto_out_0(intsink_13_auto_out_0),
    .auto_out_1(intsink_13_auto_out_1),
    .auto_out_2(intsink_13_auto_out_2),
    .auto_out_3(intsink_13_auto_out_3),
    .auto_out_4(intsink_13_auto_out_4),
    .auto_out_5(intsink_13_auto_out_5),
    .auto_out_6(intsink_13_auto_out_6),
    .auto_out_7(intsink_13_auto_out_7),
    .auto_out_8(intsink_13_auto_out_8),
    .auto_out_9(intsink_13_auto_out_9),
    .auto_out_10(intsink_13_auto_out_10),
    .auto_out_11(intsink_13_auto_out_11),
    .auto_out_12(intsink_13_auto_out_12),
    .auto_out_13(intsink_13_auto_out_13),
    .auto_out_14(intsink_13_auto_out_14),
    .auto_out_15(intsink_13_auto_out_15),
    .auto_out_16(intsink_13_auto_out_16),
    .auto_out_17(intsink_13_auto_out_17),
    .auto_out_18(intsink_13_auto_out_18),
    .auto_out_19(intsink_13_auto_out_19),
    .auto_out_20(intsink_13_auto_out_20),
    .auto_out_21(intsink_13_auto_out_21),
    .auto_out_22(intsink_13_auto_out_22),
    .auto_out_23(intsink_13_auto_out_23),
    .auto_out_24(intsink_13_auto_out_24),
    .auto_out_25(intsink_13_auto_out_25),
    .auto_out_26(intsink_13_auto_out_26),
    .auto_out_27(intsink_13_auto_out_27),
    .auto_out_28(intsink_13_auto_out_28),
    .auto_out_29(intsink_13_auto_out_29),
    .auto_out_30(intsink_13_auto_out_30),
    .auto_out_31(intsink_13_auto_out_31)
  );
  ClockSinkDomain_10 pwmClockDomainWrapper ( // @[PWM.scala 134:43]
    .auto_pwm_0_int_xing_out_sync_0(pwmClockDomainWrapper_auto_pwm_0_int_xing_out_sync_0),
    .auto_pwm_0_int_xing_out_sync_1(pwmClockDomainWrapper_auto_pwm_0_int_xing_out_sync_1),
    .auto_pwm_0_int_xing_out_sync_2(pwmClockDomainWrapper_auto_pwm_0_int_xing_out_sync_2),
    .auto_pwm_0_int_xing_out_sync_3(pwmClockDomainWrapper_auto_pwm_0_int_xing_out_sync_3),
    .auto_pwm_0_control_xing_in_a_ready(pwmClockDomainWrapper_auto_pwm_0_control_xing_in_a_ready),
    .auto_pwm_0_control_xing_in_a_valid(pwmClockDomainWrapper_auto_pwm_0_control_xing_in_a_valid),
    .auto_pwm_0_control_xing_in_a_bits_opcode(pwmClockDomainWrapper_auto_pwm_0_control_xing_in_a_bits_opcode),
    .auto_pwm_0_control_xing_in_a_bits_param(pwmClockDomainWrapper_auto_pwm_0_control_xing_in_a_bits_param),
    .auto_pwm_0_control_xing_in_a_bits_size(pwmClockDomainWrapper_auto_pwm_0_control_xing_in_a_bits_size),
    .auto_pwm_0_control_xing_in_a_bits_source(pwmClockDomainWrapper_auto_pwm_0_control_xing_in_a_bits_source),
    .auto_pwm_0_control_xing_in_a_bits_address(pwmClockDomainWrapper_auto_pwm_0_control_xing_in_a_bits_address),
    .auto_pwm_0_control_xing_in_a_bits_mask(pwmClockDomainWrapper_auto_pwm_0_control_xing_in_a_bits_mask),
    .auto_pwm_0_control_xing_in_a_bits_data(pwmClockDomainWrapper_auto_pwm_0_control_xing_in_a_bits_data),
    .auto_pwm_0_control_xing_in_a_bits_corrupt(pwmClockDomainWrapper_auto_pwm_0_control_xing_in_a_bits_corrupt),
    .auto_pwm_0_control_xing_in_d_ready(pwmClockDomainWrapper_auto_pwm_0_control_xing_in_d_ready),
    .auto_pwm_0_control_xing_in_d_valid(pwmClockDomainWrapper_auto_pwm_0_control_xing_in_d_valid),
    .auto_pwm_0_control_xing_in_d_bits_opcode(pwmClockDomainWrapper_auto_pwm_0_control_xing_in_d_bits_opcode),
    .auto_pwm_0_control_xing_in_d_bits_size(pwmClockDomainWrapper_auto_pwm_0_control_xing_in_d_bits_size),
    .auto_pwm_0_control_xing_in_d_bits_source(pwmClockDomainWrapper_auto_pwm_0_control_xing_in_d_bits_source),
    .auto_pwm_0_control_xing_in_d_bits_data(pwmClockDomainWrapper_auto_pwm_0_control_xing_in_d_bits_data),
    .auto_pwm_0_io_out_gpio_0(pwmClockDomainWrapper_auto_pwm_0_io_out_gpio_0),
    .auto_pwm_0_io_out_gpio_1(pwmClockDomainWrapper_auto_pwm_0_io_out_gpio_1),
    .auto_pwm_0_io_out_gpio_2(pwmClockDomainWrapper_auto_pwm_0_io_out_gpio_2),
    .auto_pwm_0_io_out_gpio_3(pwmClockDomainWrapper_auto_pwm_0_io_out_gpio_3),
    .auto_clock_in_clock(pwmClockDomainWrapper_auto_clock_in_clock),
    .auto_clock_in_reset(pwmClockDomainWrapper_auto_clock_in_reset)
  );
  IntSyncSyncCrossingSink_16 intsink_14 ( // @[Crossing.scala 94:29]
    .auto_in_sync_0(intsink_14_auto_in_sync_0),
    .auto_in_sync_1(intsink_14_auto_in_sync_1),
    .auto_in_sync_2(intsink_14_auto_in_sync_2),
    .auto_in_sync_3(intsink_14_auto_in_sync_3),
    .auto_out_0(intsink_14_auto_out_0),
    .auto_out_1(intsink_14_auto_out_1),
    .auto_out_2(intsink_14_auto_out_2),
    .auto_out_3(intsink_14_auto_out_3)
  );
  ClockSinkDomain_11 pwmClockDomainWrapper_1 ( // @[PWM.scala 134:43]
    .auto_pwm_1_int_xing_out_sync_0(pwmClockDomainWrapper_1_auto_pwm_1_int_xing_out_sync_0),
    .auto_pwm_1_int_xing_out_sync_1(pwmClockDomainWrapper_1_auto_pwm_1_int_xing_out_sync_1),
    .auto_pwm_1_int_xing_out_sync_2(pwmClockDomainWrapper_1_auto_pwm_1_int_xing_out_sync_2),
    .auto_pwm_1_int_xing_out_sync_3(pwmClockDomainWrapper_1_auto_pwm_1_int_xing_out_sync_3),
    .auto_pwm_1_control_xing_in_a_ready(pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_a_ready),
    .auto_pwm_1_control_xing_in_a_valid(pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_a_valid),
    .auto_pwm_1_control_xing_in_a_bits_opcode(pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_a_bits_opcode),
    .auto_pwm_1_control_xing_in_a_bits_param(pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_a_bits_param),
    .auto_pwm_1_control_xing_in_a_bits_size(pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_a_bits_size),
    .auto_pwm_1_control_xing_in_a_bits_source(pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_a_bits_source),
    .auto_pwm_1_control_xing_in_a_bits_address(pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_a_bits_address),
    .auto_pwm_1_control_xing_in_a_bits_mask(pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_a_bits_mask),
    .auto_pwm_1_control_xing_in_a_bits_data(pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_a_bits_data),
    .auto_pwm_1_control_xing_in_a_bits_corrupt(pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_a_bits_corrupt),
    .auto_pwm_1_control_xing_in_d_ready(pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_d_ready),
    .auto_pwm_1_control_xing_in_d_valid(pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_d_valid),
    .auto_pwm_1_control_xing_in_d_bits_opcode(pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_d_bits_opcode),
    .auto_pwm_1_control_xing_in_d_bits_size(pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_d_bits_size),
    .auto_pwm_1_control_xing_in_d_bits_source(pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_d_bits_source),
    .auto_pwm_1_control_xing_in_d_bits_data(pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_d_bits_data),
    .auto_pwm_1_io_out_gpio_0(pwmClockDomainWrapper_1_auto_pwm_1_io_out_gpio_0),
    .auto_pwm_1_io_out_gpio_1(pwmClockDomainWrapper_1_auto_pwm_1_io_out_gpio_1),
    .auto_pwm_1_io_out_gpio_2(pwmClockDomainWrapper_1_auto_pwm_1_io_out_gpio_2),
    .auto_pwm_1_io_out_gpio_3(pwmClockDomainWrapper_1_auto_pwm_1_io_out_gpio_3),
    .auto_clock_in_clock(pwmClockDomainWrapper_1_auto_clock_in_clock),
    .auto_clock_in_reset(pwmClockDomainWrapper_1_auto_clock_in_reset)
  );
  IntSyncSyncCrossingSink_16 intsink_15 ( // @[Crossing.scala 94:29]
    .auto_in_sync_0(intsink_15_auto_in_sync_0),
    .auto_in_sync_1(intsink_15_auto_in_sync_1),
    .auto_in_sync_2(intsink_15_auto_in_sync_2),
    .auto_in_sync_3(intsink_15_auto_in_sync_3),
    .auto_out_0(intsink_15_auto_out_0),
    .auto_out_1(intsink_15_auto_out_1),
    .auto_out_2(intsink_15_auto_out_2),
    .auto_out_3(intsink_15_auto_out_3)
  );
  ClockSinkDomain_12 pwmClockDomainWrapper_2 ( // @[PWM.scala 134:43]
    .auto_pwm_2_int_xing_out_sync_0(pwmClockDomainWrapper_2_auto_pwm_2_int_xing_out_sync_0),
    .auto_pwm_2_int_xing_out_sync_1(pwmClockDomainWrapper_2_auto_pwm_2_int_xing_out_sync_1),
    .auto_pwm_2_int_xing_out_sync_2(pwmClockDomainWrapper_2_auto_pwm_2_int_xing_out_sync_2),
    .auto_pwm_2_int_xing_out_sync_3(pwmClockDomainWrapper_2_auto_pwm_2_int_xing_out_sync_3),
    .auto_pwm_2_control_xing_in_a_ready(pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_a_ready),
    .auto_pwm_2_control_xing_in_a_valid(pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_a_valid),
    .auto_pwm_2_control_xing_in_a_bits_opcode(pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_a_bits_opcode),
    .auto_pwm_2_control_xing_in_a_bits_param(pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_a_bits_param),
    .auto_pwm_2_control_xing_in_a_bits_size(pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_a_bits_size),
    .auto_pwm_2_control_xing_in_a_bits_source(pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_a_bits_source),
    .auto_pwm_2_control_xing_in_a_bits_address(pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_a_bits_address),
    .auto_pwm_2_control_xing_in_a_bits_mask(pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_a_bits_mask),
    .auto_pwm_2_control_xing_in_a_bits_data(pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_a_bits_data),
    .auto_pwm_2_control_xing_in_a_bits_corrupt(pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_a_bits_corrupt),
    .auto_pwm_2_control_xing_in_d_ready(pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_d_ready),
    .auto_pwm_2_control_xing_in_d_valid(pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_d_valid),
    .auto_pwm_2_control_xing_in_d_bits_opcode(pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_d_bits_opcode),
    .auto_pwm_2_control_xing_in_d_bits_size(pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_d_bits_size),
    .auto_pwm_2_control_xing_in_d_bits_source(pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_d_bits_source),
    .auto_pwm_2_control_xing_in_d_bits_data(pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_d_bits_data),
    .auto_pwm_2_io_out_gpio_0(pwmClockDomainWrapper_2_auto_pwm_2_io_out_gpio_0),
    .auto_pwm_2_io_out_gpio_1(pwmClockDomainWrapper_2_auto_pwm_2_io_out_gpio_1),
    .auto_pwm_2_io_out_gpio_2(pwmClockDomainWrapper_2_auto_pwm_2_io_out_gpio_2),
    .auto_pwm_2_io_out_gpio_3(pwmClockDomainWrapper_2_auto_pwm_2_io_out_gpio_3),
    .auto_clock_in_clock(pwmClockDomainWrapper_2_auto_clock_in_clock),
    .auto_clock_in_reset(pwmClockDomainWrapper_2_auto_clock_in_reset)
  );
  IntSyncSyncCrossingSink_16 intsink_16 ( // @[Crossing.scala 94:29]
    .auto_in_sync_0(intsink_16_auto_in_sync_0),
    .auto_in_sync_1(intsink_16_auto_in_sync_1),
    .auto_in_sync_2(intsink_16_auto_in_sync_2),
    .auto_in_sync_3(intsink_16_auto_in_sync_3),
    .auto_out_0(intsink_16_auto_out_0),
    .auto_out_1(intsink_16_auto_out_1),
    .auto_out_2(intsink_16_auto_out_2),
    .auto_out_3(intsink_16_auto_out_3)
  );
  ClockSinkDomain_13 i2cClockDomainWrapper ( // @[I2C.scala 596:43]
    .auto_i2c_0_int_xing_out_sync_0(i2cClockDomainWrapper_auto_i2c_0_int_xing_out_sync_0),
    .auto_i2c_0_control_xing_in_a_ready(i2cClockDomainWrapper_auto_i2c_0_control_xing_in_a_ready),
    .auto_i2c_0_control_xing_in_a_valid(i2cClockDomainWrapper_auto_i2c_0_control_xing_in_a_valid),
    .auto_i2c_0_control_xing_in_a_bits_opcode(i2cClockDomainWrapper_auto_i2c_0_control_xing_in_a_bits_opcode),
    .auto_i2c_0_control_xing_in_a_bits_param(i2cClockDomainWrapper_auto_i2c_0_control_xing_in_a_bits_param),
    .auto_i2c_0_control_xing_in_a_bits_size(i2cClockDomainWrapper_auto_i2c_0_control_xing_in_a_bits_size),
    .auto_i2c_0_control_xing_in_a_bits_source(i2cClockDomainWrapper_auto_i2c_0_control_xing_in_a_bits_source),
    .auto_i2c_0_control_xing_in_a_bits_address(i2cClockDomainWrapper_auto_i2c_0_control_xing_in_a_bits_address),
    .auto_i2c_0_control_xing_in_a_bits_mask(i2cClockDomainWrapper_auto_i2c_0_control_xing_in_a_bits_mask),
    .auto_i2c_0_control_xing_in_a_bits_data(i2cClockDomainWrapper_auto_i2c_0_control_xing_in_a_bits_data),
    .auto_i2c_0_control_xing_in_a_bits_corrupt(i2cClockDomainWrapper_auto_i2c_0_control_xing_in_a_bits_corrupt),
    .auto_i2c_0_control_xing_in_d_ready(i2cClockDomainWrapper_auto_i2c_0_control_xing_in_d_ready),
    .auto_i2c_0_control_xing_in_d_valid(i2cClockDomainWrapper_auto_i2c_0_control_xing_in_d_valid),
    .auto_i2c_0_control_xing_in_d_bits_opcode(i2cClockDomainWrapper_auto_i2c_0_control_xing_in_d_bits_opcode),
    .auto_i2c_0_control_xing_in_d_bits_size(i2cClockDomainWrapper_auto_i2c_0_control_xing_in_d_bits_size),
    .auto_i2c_0_control_xing_in_d_bits_source(i2cClockDomainWrapper_auto_i2c_0_control_xing_in_d_bits_source),
    .auto_i2c_0_control_xing_in_d_bits_data(i2cClockDomainWrapper_auto_i2c_0_control_xing_in_d_bits_data),
    .auto_i2c_0_io_out_scl_in(i2cClockDomainWrapper_auto_i2c_0_io_out_scl_in),
    .auto_i2c_0_io_out_scl_oe(i2cClockDomainWrapper_auto_i2c_0_io_out_scl_oe),
    .auto_i2c_0_io_out_sda_in(i2cClockDomainWrapper_auto_i2c_0_io_out_sda_in),
    .auto_i2c_0_io_out_sda_oe(i2cClockDomainWrapper_auto_i2c_0_io_out_sda_oe),
    .auto_clock_in_clock(i2cClockDomainWrapper_auto_clock_in_clock),
    .auto_clock_in_reset(i2cClockDomainWrapper_auto_clock_in_reset)
  );
  IntSyncSyncCrossingSink_1 intsink_17 ( // @[Crossing.scala 94:29]
    .auto_in_sync_0(intsink_17_auto_in_sync_0),
    .auto_out_0(intsink_17_auto_out_0)
  );
  ClockSinkDomain_14 i2cClockDomainWrapper_1 ( // @[I2C.scala 596:43]
    .auto_i2c_1_int_xing_out_sync_0(i2cClockDomainWrapper_1_auto_i2c_1_int_xing_out_sync_0),
    .auto_i2c_1_control_xing_in_a_ready(i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_a_ready),
    .auto_i2c_1_control_xing_in_a_valid(i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_a_valid),
    .auto_i2c_1_control_xing_in_a_bits_opcode(i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_a_bits_opcode),
    .auto_i2c_1_control_xing_in_a_bits_param(i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_a_bits_param),
    .auto_i2c_1_control_xing_in_a_bits_size(i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_a_bits_size),
    .auto_i2c_1_control_xing_in_a_bits_source(i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_a_bits_source),
    .auto_i2c_1_control_xing_in_a_bits_address(i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_a_bits_address),
    .auto_i2c_1_control_xing_in_a_bits_mask(i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_a_bits_mask),
    .auto_i2c_1_control_xing_in_a_bits_data(i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_a_bits_data),
    .auto_i2c_1_control_xing_in_a_bits_corrupt(i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_a_bits_corrupt),
    .auto_i2c_1_control_xing_in_d_ready(i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_d_ready),
    .auto_i2c_1_control_xing_in_d_valid(i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_d_valid),
    .auto_i2c_1_control_xing_in_d_bits_opcode(i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_d_bits_opcode),
    .auto_i2c_1_control_xing_in_d_bits_size(i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_d_bits_size),
    .auto_i2c_1_control_xing_in_d_bits_source(i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_d_bits_source),
    .auto_i2c_1_control_xing_in_d_bits_data(i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_d_bits_data),
    .auto_i2c_1_io_out_scl_in(i2cClockDomainWrapper_1_auto_i2c_1_io_out_scl_in),
    .auto_i2c_1_io_out_scl_oe(i2cClockDomainWrapper_1_auto_i2c_1_io_out_scl_oe),
    .auto_i2c_1_io_out_sda_in(i2cClockDomainWrapper_1_auto_i2c_1_io_out_sda_in),
    .auto_i2c_1_io_out_sda_oe(i2cClockDomainWrapper_1_auto_i2c_1_io_out_sda_oe),
    .auto_clock_in_clock(i2cClockDomainWrapper_1_auto_clock_in_clock),
    .auto_clock_in_reset(i2cClockDomainWrapper_1_auto_clock_in_reset)
  );
  IntSyncSyncCrossingSink_1 intsink_18 ( // @[Crossing.scala 94:29]
    .auto_in_sync_0(intsink_18_auto_in_sync_0),
    .auto_out_0(intsink_18_auto_out_0)
  );
  ClockSinkDomain_15 bootROMDomainWrapper ( // @[BootROM.scala 70:42]
    .auto_bootrom_in_a_ready(bootROMDomainWrapper_auto_bootrom_in_a_ready),
    .auto_bootrom_in_a_valid(bootROMDomainWrapper_auto_bootrom_in_a_valid),
    .auto_bootrom_in_a_bits_opcode(bootROMDomainWrapper_auto_bootrom_in_a_bits_opcode),
    .auto_bootrom_in_a_bits_param(bootROMDomainWrapper_auto_bootrom_in_a_bits_param),
    .auto_bootrom_in_a_bits_size(bootROMDomainWrapper_auto_bootrom_in_a_bits_size),
    .auto_bootrom_in_a_bits_source(bootROMDomainWrapper_auto_bootrom_in_a_bits_source),
    .auto_bootrom_in_a_bits_address(bootROMDomainWrapper_auto_bootrom_in_a_bits_address),
    .auto_bootrom_in_a_bits_mask(bootROMDomainWrapper_auto_bootrom_in_a_bits_mask),
    .auto_bootrom_in_a_bits_corrupt(bootROMDomainWrapper_auto_bootrom_in_a_bits_corrupt),
    .auto_bootrom_in_d_ready(bootROMDomainWrapper_auto_bootrom_in_d_ready),
    .auto_bootrom_in_d_valid(bootROMDomainWrapper_auto_bootrom_in_d_valid),
    .auto_bootrom_in_d_bits_size(bootROMDomainWrapper_auto_bootrom_in_d_bits_size),
    .auto_bootrom_in_d_bits_source(bootROMDomainWrapper_auto_bootrom_in_d_bits_source),
    .auto_bootrom_in_d_bits_data(bootROMDomainWrapper_auto_bootrom_in_d_bits_data),
    .auto_clock_in_clock(bootROMDomainWrapper_auto_clock_in_clock),
    .auto_clock_in_reset(bootROMDomainWrapper_auto_clock_in_reset)
  );
  DebugTransportModuleJTAG dtm ( // @[Periphery.scala 161:21]
    .io_jtag_clock(dtm_io_jtag_clock),
    .io_jtag_reset(dtm_io_jtag_reset),
    .io_dmi_req_ready(dtm_io_dmi_req_ready),
    .io_dmi_req_valid(dtm_io_dmi_req_valid),
    .io_dmi_req_bits_addr(dtm_io_dmi_req_bits_addr),
    .io_dmi_req_bits_data(dtm_io_dmi_req_bits_data),
    .io_dmi_req_bits_op(dtm_io_dmi_req_bits_op),
    .io_dmi_resp_ready(dtm_io_dmi_resp_ready),
    .io_dmi_resp_valid(dtm_io_dmi_resp_valid),
    .io_dmi_resp_bits_data(dtm_io_dmi_resp_bits_data),
    .io_dmi_resp_bits_resp(dtm_io_dmi_resp_bits_resp),
    .io_jtag_TMS(dtm_io_jtag_TMS),
    .io_jtag_TDI(dtm_io_jtag_TDI),
    .io_jtag_TDO_data(dtm_io_jtag_TDO_data),
    .io_jtag_TDO_driven(dtm_io_jtag_TDO_driven)
  );
  SynchronizerShiftReg_w1_d3 rtc_sync_rtc ( // @[ShiftReg.scala 45:23]
    .clock(rtc_sync_rtc_clock),
    .io_d(rtc_sync_rtc_io_d),
    .io_q(rtc_sync_rtc_io_q)
  );
  assign debug_systemjtag_jtag_TDO_data = dtm_io_jtag_TDO_data; // @[Periphery.scala 162:17]
  assign debug_systemjtag_jtag_TDO_driven = dtm_io_jtag_TDO_driven; // @[Periphery.scala 162:17]
  assign uart_0_txd = uartClockDomainWrapper_auto_uart_0_io_out_txd; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign uart_1_txd = uartClockDomainWrapper_1_auto_uart_1_io_out_txd; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign uart_2_txd = uartClockDomainWrapper_2_auto_uart_2_io_out_txd; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign uart_3_txd = uartClockDomainWrapper_3_auto_uart_3_io_out_txd; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign uart_4_txd = uartClockDomainWrapper_4_auto_uart_4_io_out_txd; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign spi_0_sck = spiClockDomainWrapper_auto_spi_0_io_out_sck; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign spi_0_dq_0_o = spiClockDomainWrapper_auto_spi_0_io_out_dq_0_o; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign spi_0_dq_0_oe = spiClockDomainWrapper_auto_spi_0_io_out_dq_0_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign spi_0_dq_1_o = spiClockDomainWrapper_auto_spi_0_io_out_dq_1_o; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign spi_0_dq_1_oe = spiClockDomainWrapper_auto_spi_0_io_out_dq_1_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign spi_0_dq_2_o = spiClockDomainWrapper_auto_spi_0_io_out_dq_2_o; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign spi_0_dq_2_oe = spiClockDomainWrapper_auto_spi_0_io_out_dq_2_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign spi_0_dq_3_o = spiClockDomainWrapper_auto_spi_0_io_out_dq_3_o; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign spi_0_dq_3_oe = spiClockDomainWrapper_auto_spi_0_io_out_dq_3_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign spi_0_cs_0 = spiClockDomainWrapper_auto_spi_0_io_out_cs_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign spi_0_cs_1 = spiClockDomainWrapper_auto_spi_0_io_out_cs_1; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_0_o_oval = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_0_o_oval; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_0_o_oe = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_0_o_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_0_o_ie = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_0_o_ie; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_1_o_oval = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_1_o_oval; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_1_o_oe = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_1_o_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_1_o_ie = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_1_o_ie; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_2_o_oval = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_2_o_oval; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_2_o_oe = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_2_o_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_2_o_ie = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_2_o_ie; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_3_o_oval = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_3_o_oval; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_3_o_oe = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_3_o_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_3_o_ie = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_3_o_ie; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_4_o_oval = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_4_o_oval; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_4_o_oe = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_4_o_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_4_o_ie = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_4_o_ie; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_5_o_oval = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_5_o_oval; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_5_o_oe = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_5_o_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_5_o_ie = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_5_o_ie; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_6_o_oval = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_6_o_oval; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_6_o_oe = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_6_o_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_7_o_oval = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_7_o_oval; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_7_o_oe = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_7_o_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_8_o_oval = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_8_o_oval; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_8_o_oe = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_8_o_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_9_o_oval = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_9_o_oval; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_9_o_oe = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_9_o_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_10_o_oval = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_10_o_oval; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_10_o_oe = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_10_o_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_11_o_oval = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_11_o_oval; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_11_o_oe = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_11_o_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_12_o_oval = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_12_o_oval; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_12_o_oe = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_12_o_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_12_o_ie = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_12_o_ie; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_13_o_oval = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_13_o_oval; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_13_o_oe = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_13_o_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_13_o_ie = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_13_o_ie; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_14_o_oval = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_14_o_oval; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_14_o_oe = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_14_o_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_14_o_ie = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_14_o_ie; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_15_o_oval = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_15_o_oval; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_15_o_oe = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_15_o_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_15_o_ie = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_15_o_ie; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_16_o_oval = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_16_o_oval; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_16_o_oe = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_16_o_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_16_o_ie = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_16_o_ie; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_17_o_oval = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_17_o_oval; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_17_o_oe = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_17_o_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_17_o_ie = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_17_o_ie; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_18_o_oval = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_18_o_oval; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_18_o_oe = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_18_o_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_18_o_ie = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_18_o_ie; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_19_o_oval = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_19_o_oval; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_19_o_oe = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_19_o_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_19_o_ie = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_19_o_ie; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_20_o_oval = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_20_o_oval; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_20_o_oe = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_20_o_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_20_o_ie = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_20_o_ie; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_21_o_oval = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_21_o_oval; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_21_o_oe = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_21_o_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_21_o_ie = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_21_o_ie; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_22_o_oval = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_22_o_oval; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_22_o_oe = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_22_o_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_22_o_ie = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_22_o_ie; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_23_o_oval = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_23_o_oval; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_23_o_oe = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_23_o_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_23_o_ie = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_23_o_ie; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_24_o_oval = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_24_o_oval; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_24_o_oe = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_24_o_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_24_o_ie = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_24_o_ie; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_25_o_oval = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_25_o_oval; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_25_o_oe = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_25_o_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_26_o_oval = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_26_o_oval; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_26_o_oe = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_26_o_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_27_o_oval = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_27_o_oval; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_27_o_oe = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_27_o_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_28_o_oval = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_28_o_oval; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_28_o_oe = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_28_o_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_29_o_oval = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_29_o_oval; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_29_o_oe = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_29_o_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_30_o_oval = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_30_o_oval; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_30_o_oe = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_30_o_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_31_o_oval = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_31_o_oval; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpio_0_pins_31_o_oe = gpioClockDomainWrapper_auto_gpio_0_io_out_pins_31_o_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign iof_0_iof_0_2_i_ival = gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_2_i_ival; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign iof_0_iof_0_3_i_ival = gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_3_i_ival; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign iof_0_iof_0_4_i_ival = gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_4_i_ival; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign iof_0_iof_0_5_i_ival = gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_5_i_ival; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign iof_0_iof_0_12_i_ival = gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_12_i_ival; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign iof_0_iof_0_13_i_ival = gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_13_i_ival; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign iof_0_iof_0_14_i_ival = gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_14_i_ival; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign iof_0_iof_0_15_i_ival = gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_15_i_ival; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign iof_0_iof_0_16_i_ival = gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_16_i_ival; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign iof_0_iof_0_18_i_ival = gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_18_i_ival; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign iof_0_iof_0_20_i_ival = gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_20_i_ival; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign iof_0_iof_0_22_i_ival = gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_22_i_ival; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign pwm_0_gpio_0 = pwmClockDomainWrapper_auto_pwm_0_io_out_gpio_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign pwm_0_gpio_1 = pwmClockDomainWrapper_auto_pwm_0_io_out_gpio_1; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign pwm_0_gpio_2 = pwmClockDomainWrapper_auto_pwm_0_io_out_gpio_2; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign pwm_0_gpio_3 = pwmClockDomainWrapper_auto_pwm_0_io_out_gpio_3; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign pwm_1_gpio_0 = pwmClockDomainWrapper_1_auto_pwm_1_io_out_gpio_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign pwm_1_gpio_1 = pwmClockDomainWrapper_1_auto_pwm_1_io_out_gpio_1; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign pwm_1_gpio_2 = pwmClockDomainWrapper_1_auto_pwm_1_io_out_gpio_2; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign pwm_1_gpio_3 = pwmClockDomainWrapper_1_auto_pwm_1_io_out_gpio_3; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign pwm_2_gpio_0 = pwmClockDomainWrapper_2_auto_pwm_2_io_out_gpio_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign pwm_2_gpio_1 = pwmClockDomainWrapper_2_auto_pwm_2_io_out_gpio_1; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign pwm_2_gpio_2 = pwmClockDomainWrapper_2_auto_pwm_2_io_out_gpio_2; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign pwm_2_gpio_3 = pwmClockDomainWrapper_2_auto_pwm_2_io_out_gpio_3; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign qspi_0_sck = qspiClockDomainWrapper_auto_qspi_0_io_out_sck; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign qspi_0_dq_0_o = qspiClockDomainWrapper_auto_qspi_0_io_out_dq_0_o; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign qspi_0_dq_0_oe = qspiClockDomainWrapper_auto_qspi_0_io_out_dq_0_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign qspi_0_dq_1_o = qspiClockDomainWrapper_auto_qspi_0_io_out_dq_1_o; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign qspi_0_dq_1_oe = qspiClockDomainWrapper_auto_qspi_0_io_out_dq_1_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign qspi_0_dq_2_o = qspiClockDomainWrapper_auto_qspi_0_io_out_dq_2_o; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign qspi_0_dq_2_oe = qspiClockDomainWrapper_auto_qspi_0_io_out_dq_2_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign qspi_0_dq_3_o = qspiClockDomainWrapper_auto_qspi_0_io_out_dq_3_o; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign qspi_0_dq_3_oe = qspiClockDomainWrapper_auto_qspi_0_io_out_dq_3_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign qspi_0_cs_0 = qspiClockDomainWrapper_auto_qspi_0_io_out_cs_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign qspi_ram_0_sck = qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_sck; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign qspi_ram_0_dq_0_o = qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_dq_0_o; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign qspi_ram_0_dq_0_oe = qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_dq_0_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign qspi_ram_0_dq_1_o = qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_dq_1_o; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign qspi_ram_0_dq_1_oe = qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_dq_1_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign qspi_ram_0_dq_2_o = qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_dq_2_o; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign qspi_ram_0_dq_2_oe = qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_dq_2_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign qspi_ram_0_dq_3_o = qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_dq_3_o; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign qspi_ram_0_dq_3_oe = qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_dq_3_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign qspi_ram_0_cs_0 = qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_cs_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign aon_rsts_corerst = aon_1_io_rsts_corerst; // @[MockAONPeriphery.scala 37:7]
  assign i2c_0_scl_oe = i2cClockDomainWrapper_auto_i2c_0_io_out_scl_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign i2c_0_sda_oe = i2cClockDomainWrapper_auto_i2c_0_io_out_sda_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign i2c_1_scl_oe = i2cClockDomainWrapper_1_auto_i2c_1_io_out_scl_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign i2c_1_sda_oe = i2cClockDomainWrapper_1_auto_i2c_1_io_out_sda_oe; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_14_0 = intsink_18_auto_out_0; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_13_0 = intsink_17_auto_out_0; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_12_0 = intsink_16_auto_out_0; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_12_1 = intsink_16_auto_out_1; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_12_2 = intsink_16_auto_out_2; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_12_3 = intsink_16_auto_out_3; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_11_0 = intsink_15_auto_out_0; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_11_1 = intsink_15_auto_out_1; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_11_2 = intsink_15_auto_out_2; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_11_3 = intsink_15_auto_out_3; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_10_0 = intsink_14_auto_out_0; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_10_1 = intsink_14_auto_out_1; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_10_2 = intsink_14_auto_out_2; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_10_3 = intsink_14_auto_out_3; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_9_0 = intsink_13_auto_out_0; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_9_1 = intsink_13_auto_out_1; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_9_2 = intsink_13_auto_out_2; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_9_3 = intsink_13_auto_out_3; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_9_4 = intsink_13_auto_out_4; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_9_5 = intsink_13_auto_out_5; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_9_6 = intsink_13_auto_out_6; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_9_7 = intsink_13_auto_out_7; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_9_8 = intsink_13_auto_out_8; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_9_9 = intsink_13_auto_out_9; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_9_10 = intsink_13_auto_out_10; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_9_11 = intsink_13_auto_out_11; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_9_12 = intsink_13_auto_out_12; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_9_13 = intsink_13_auto_out_13; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_9_14 = intsink_13_auto_out_14; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_9_15 = intsink_13_auto_out_15; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_9_16 = intsink_13_auto_out_16; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_9_17 = intsink_13_auto_out_17; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_9_18 = intsink_13_auto_out_18; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_9_19 = intsink_13_auto_out_19; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_9_20 = intsink_13_auto_out_20; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_9_21 = intsink_13_auto_out_21; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_9_22 = intsink_13_auto_out_22; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_9_23 = intsink_13_auto_out_23; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_9_24 = intsink_13_auto_out_24; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_9_25 = intsink_13_auto_out_25; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_9_26 = intsink_13_auto_out_26; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_9_27 = intsink_13_auto_out_27; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_9_28 = intsink_13_auto_out_28; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_9_29 = intsink_13_auto_out_29; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_9_30 = intsink_13_auto_out_30; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_9_31 = intsink_13_auto_out_31; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_8_0 = intsink_12_auto_out_0; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_7_0 = intsink_11_auto_out_0; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_6_0 = intsink_10_auto_out_0; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_5_0 = intsink_9_auto_out_0; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_4_0 = intsink_8_auto_out_0; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_3_0 = intsink_7_auto_out_0; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_2_0 = intsink_6_auto_out_0; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_1_0 = intsink_5_auto_out_0; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_0_0 = intsink_4_auto_out_0; // @[LazyModule.scala 296:16]
  assign ibus_auto_int_bus_int_in_0_1 = intsink_4_auto_out_1; // @[LazyModule.scala 296:16]
  assign dummyClockGroupSourceNode_clock = clock;
  assign dummyClockGroupSourceNode_reset = reset;
  assign subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_valid =
    tile_prci_domain_auto_tl_master_clock_xing_out_a_valid; // @[LazyModule.scala 296:16]
  assign subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_opcode =
    tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_param =
    tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param; // @[LazyModule.scala 296:16]
  assign subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_size =
    tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_source =
    tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_address =
    tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_mask =
    tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_data =
    tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_bits_corrupt =
    tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
  assign subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_b_ready =
    tile_prci_domain_auto_tl_master_clock_xing_out_b_ready; // @[LazyModule.scala 296:16]
  assign subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_c_valid =
    tile_prci_domain_auto_tl_master_clock_xing_out_c_valid; // @[LazyModule.scala 296:16]
  assign subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_opcode =
    tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_opcode; // @[LazyModule.scala 296:16]
  assign subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_param =
    tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_param; // @[LazyModule.scala 296:16]
  assign subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_size =
    tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_size; // @[LazyModule.scala 296:16]
  assign subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_source =
    tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_source; // @[LazyModule.scala 296:16]
  assign subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_address =
    tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_address; // @[LazyModule.scala 296:16]
  assign subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_data =
    tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_data; // @[LazyModule.scala 296:16]
  assign subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_c_bits_corrupt =
    tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[LazyModule.scala 296:16]
  assign subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_ready =
    tile_prci_domain_auto_tl_master_clock_xing_out_d_ready; // @[LazyModule.scala 296:16]
  assign subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_e_valid =
    tile_prci_domain_auto_tl_master_clock_xing_out_e_valid; // @[LazyModule.scala 296:16]
  assign subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_e_bits_sink =
    tile_prci_domain_auto_tl_master_clock_xing_out_e_bits_sink; // @[LazyModule.scala 296:16]
  assign subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_ready =
    subsystem_l2_wrapper_auto_coherent_jbar_in_a_ready; // @[LazyModule.scala 298:16]
  assign subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_b_valid =
    subsystem_l2_wrapper_auto_coherent_jbar_in_b_valid; // @[LazyModule.scala 298:16]
  assign subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_b_bits_param =
    subsystem_l2_wrapper_auto_coherent_jbar_in_b_bits_param; // @[LazyModule.scala 298:16]
  assign subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_b_bits_address =
    subsystem_l2_wrapper_auto_coherent_jbar_in_b_bits_address; // @[LazyModule.scala 298:16]
  assign subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_ready =
    subsystem_l2_wrapper_auto_coherent_jbar_in_c_ready; // @[LazyModule.scala 298:16]
  assign subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_d_valid =
    subsystem_l2_wrapper_auto_coherent_jbar_in_d_valid; // @[LazyModule.scala 298:16]
  assign subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_opcode =
    subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_param =
    subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_param; // @[LazyModule.scala 298:16]
  assign subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_size =
    subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_source =
    subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_sink =
    subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_sink; // @[LazyModule.scala 298:16]
  assign subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_d_bits_data =
    subsystem_l2_wrapper_auto_coherent_jbar_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_ready =
    subsystem_cbus_auto_bus_xing_in_a_ready; // @[LazyModule.scala 298:16]
  assign subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_valid =
    subsystem_cbus_auto_bus_xing_in_d_valid; // @[LazyModule.scala 298:16]
  assign subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_opcode =
    subsystem_cbus_auto_bus_xing_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_param =
    subsystem_cbus_auto_bus_xing_in_d_bits_param; // @[LazyModule.scala 298:16]
  assign subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_size =
    subsystem_cbus_auto_bus_xing_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_source =
    subsystem_cbus_auto_bus_xing_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_sink =
    subsystem_cbus_auto_bus_xing_in_d_bits_sink; // @[LazyModule.scala 298:16]
  assign subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_denied =
    subsystem_cbus_auto_bus_xing_in_d_bits_denied; // @[LazyModule.scala 298:16]
  assign subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_data =
    subsystem_cbus_auto_bus_xing_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_bits_corrupt =
    subsystem_cbus_auto_bus_xing_in_d_bits_corrupt; // @[LazyModule.scala 298:16]
  assign subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_5_clock =
    dummyClockGroupSourceNode_auto_out_member_subsystem_sbus_5_clock; // @[LazyModule.scala 298:16]
  assign subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_5_reset =
    dummyClockGroupSourceNode_auto_out_member_subsystem_sbus_5_reset; // @[LazyModule.scala 298:16]
  assign subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_4_clock =
    dummyClockGroupSourceNode_auto_out_member_subsystem_sbus_4_clock; // @[LazyModule.scala 298:16]
  assign subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_4_reset =
    dummyClockGroupSourceNode_auto_out_member_subsystem_sbus_4_reset; // @[LazyModule.scala 298:16]
  assign subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_3_clock =
    dummyClockGroupSourceNode_auto_out_member_subsystem_sbus_3_clock; // @[LazyModule.scala 298:16]
  assign subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_3_reset =
    dummyClockGroupSourceNode_auto_out_member_subsystem_sbus_3_reset; // @[LazyModule.scala 298:16]
  assign subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_2_clock =
    dummyClockGroupSourceNode_auto_out_member_subsystem_sbus_2_clock; // @[LazyModule.scala 298:16]
  assign subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_2_reset =
    dummyClockGroupSourceNode_auto_out_member_subsystem_sbus_2_reset; // @[LazyModule.scala 298:16]
  assign subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_1_clock =
    dummyClockGroupSourceNode_auto_out_member_subsystem_sbus_1_clock; // @[LazyModule.scala 298:16]
  assign subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_1_reset =
    dummyClockGroupSourceNode_auto_out_member_subsystem_sbus_1_reset; // @[LazyModule.scala 298:16]
  assign subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_0_clock =
    dummyClockGroupSourceNode_auto_out_member_subsystem_sbus_0_clock; // @[LazyModule.scala 298:16]
  assign subsystem_sbus_auto_subsystem_sbus_clock_groups_in_member_subsystem_sbus_0_reset =
    dummyClockGroupSourceNode_auto_out_member_subsystem_sbus_0_reset; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_a_ready =
    i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_a_ready; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_d_valid =
    i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_d_valid; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_d_bits_opcode =
    i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_d_bits_size =
    i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_d_bits_source =
    i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_d_bits_data =
    i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_a_ready =
    i2cClockDomainWrapper_auto_i2c_0_control_xing_in_a_ready; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_d_valid =
    i2cClockDomainWrapper_auto_i2c_0_control_xing_in_d_valid; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_d_bits_opcode =
    i2cClockDomainWrapper_auto_i2c_0_control_xing_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_d_bits_size =
    i2cClockDomainWrapper_auto_i2c_0_control_xing_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_d_bits_source =
    i2cClockDomainWrapper_auto_i2c_0_control_xing_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_d_bits_data =
    i2cClockDomainWrapper_auto_i2c_0_control_xing_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_a_ready =
    pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_a_ready; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_d_valid =
    pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_d_valid; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_d_bits_opcode =
    pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_d_bits_size =
    pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_d_bits_source =
    pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_d_bits_data =
    pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_a_ready =
    pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_a_ready; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_d_valid =
    pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_d_valid; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_d_bits_opcode =
    pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_d_bits_size =
    pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_d_bits_source =
    pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_d_bits_data =
    pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_a_ready =
    pwmClockDomainWrapper_auto_pwm_0_control_xing_in_a_ready; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_d_valid =
    pwmClockDomainWrapper_auto_pwm_0_control_xing_in_d_valid; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_d_bits_opcode =
    pwmClockDomainWrapper_auto_pwm_0_control_xing_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_d_bits_size =
    pwmClockDomainWrapper_auto_pwm_0_control_xing_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_d_bits_source =
    pwmClockDomainWrapper_auto_pwm_0_control_xing_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_d_bits_data =
    pwmClockDomainWrapper_auto_pwm_0_control_xing_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_ready =
    gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_ready; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_d_valid =
    gpioClockDomainWrapper_auto_gpio_0_control_xing_in_d_valid; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_opcode =
    gpioClockDomainWrapper_auto_gpio_0_control_xing_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_size =
    gpioClockDomainWrapper_auto_gpio_0_control_xing_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_source =
    gpioClockDomainWrapper_auto_gpio_0_control_xing_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_d_bits_data =
    gpioClockDomainWrapper_auto_gpio_0_control_xing_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_a_ready =
    spiClockDomainWrapper_auto_spi_0_control_xing_in_a_ready; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_d_valid =
    spiClockDomainWrapper_auto_spi_0_control_xing_in_d_valid; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_d_bits_opcode =
    spiClockDomainWrapper_auto_spi_0_control_xing_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_d_bits_size =
    spiClockDomainWrapper_auto_spi_0_control_xing_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_d_bits_source =
    spiClockDomainWrapper_auto_spi_0_control_xing_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_d_bits_data =
    spiClockDomainWrapper_auto_spi_0_control_xing_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_ready =
    qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_a_ready; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_d_valid =
    qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_d_valid; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_d_bits_opcode =
    qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_d_bits_size =
    qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_d_bits_source =
    qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_d_bits_data =
    qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_ready =
    qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_ready; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_d_valid =
    qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_d_valid; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_d_bits_size =
    qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_d_bits_source =
    qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_d_bits_data =
    qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_ready =
    qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_ready; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_d_valid =
    qspiClockDomainWrapper_auto_qspi_0_control_xing_in_d_valid; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_opcode =
    qspiClockDomainWrapper_auto_qspi_0_control_xing_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_size =
    qspiClockDomainWrapper_auto_qspi_0_control_xing_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_source =
    qspiClockDomainWrapper_auto_qspi_0_control_xing_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_d_bits_data =
    qspiClockDomainWrapper_auto_qspi_0_control_xing_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_a_ready =
    uartClockDomainWrapper_4_auto_uart_4_control_xing_in_a_ready; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_d_valid =
    uartClockDomainWrapper_4_auto_uart_4_control_xing_in_d_valid; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_d_bits_opcode =
    uartClockDomainWrapper_4_auto_uart_4_control_xing_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_d_bits_size =
    uartClockDomainWrapper_4_auto_uart_4_control_xing_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_d_bits_source =
    uartClockDomainWrapper_4_auto_uart_4_control_xing_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_d_bits_data =
    uartClockDomainWrapper_4_auto_uart_4_control_xing_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_a_ready =
    uartClockDomainWrapper_3_auto_uart_3_control_xing_in_a_ready; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_d_valid =
    uartClockDomainWrapper_3_auto_uart_3_control_xing_in_d_valid; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_d_bits_opcode =
    uartClockDomainWrapper_3_auto_uart_3_control_xing_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_d_bits_size =
    uartClockDomainWrapper_3_auto_uart_3_control_xing_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_d_bits_source =
    uartClockDomainWrapper_3_auto_uart_3_control_xing_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_d_bits_data =
    uartClockDomainWrapper_3_auto_uart_3_control_xing_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_a_ready =
    uartClockDomainWrapper_2_auto_uart_2_control_xing_in_a_ready; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_d_valid =
    uartClockDomainWrapper_2_auto_uart_2_control_xing_in_d_valid; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_d_bits_opcode =
    uartClockDomainWrapper_2_auto_uart_2_control_xing_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_d_bits_size =
    uartClockDomainWrapper_2_auto_uart_2_control_xing_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_d_bits_source =
    uartClockDomainWrapper_2_auto_uart_2_control_xing_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_d_bits_data =
    uartClockDomainWrapper_2_auto_uart_2_control_xing_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_ready =
    uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_ready; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_d_valid =
    uartClockDomainWrapper_1_auto_uart_1_control_xing_in_d_valid; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_opcode =
    uartClockDomainWrapper_1_auto_uart_1_control_xing_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_size =
    uartClockDomainWrapper_1_auto_uart_1_control_xing_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_source =
    uartClockDomainWrapper_1_auto_uart_1_control_xing_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_d_bits_data =
    uartClockDomainWrapper_1_auto_uart_1_control_xing_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_ready =
    uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_valid =
    uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode =
    uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size =
    uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source =
    uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data =
    uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign subsystem_pbus_auto_subsystem_pbus_clock_groups_in_member_subsystem_pbus_0_clock =
    subsystem_cbus_auto_subsystem_cbus_clock_groups_out_member_subsystem_pbus_0_clock; // @[LazyModule.scala 296:16]
  assign subsystem_pbus_auto_subsystem_pbus_clock_groups_in_member_subsystem_pbus_0_reset =
    subsystem_cbus_auto_subsystem_cbus_clock_groups_out_member_subsystem_pbus_0_reset; // @[LazyModule.scala 296:16]
  assign subsystem_pbus_auto_bus_xing_in_a_valid =
    subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_valid; // @[LazyModule.scala 296:16]
  assign subsystem_pbus_auto_bus_xing_in_a_bits_opcode =
    subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign subsystem_pbus_auto_bus_xing_in_a_bits_param =
    subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_param; // @[LazyModule.scala 296:16]
  assign subsystem_pbus_auto_bus_xing_in_a_bits_size =
    subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign subsystem_pbus_auto_bus_xing_in_a_bits_source =
    subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign subsystem_pbus_auto_bus_xing_in_a_bits_address =
    subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign subsystem_pbus_auto_bus_xing_in_a_bits_mask =
    subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign subsystem_pbus_auto_bus_xing_in_a_bits_data =
    subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign subsystem_pbus_auto_bus_xing_in_a_bits_corrupt =
    subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_bits_corrupt; // @[LazyModule.scala 296:16]
  assign subsystem_pbus_auto_bus_xing_in_d_ready =
    subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_ready; // @[LazyModule.scala 296:16]
  assign subsystem_fbus_auto_subsystem_fbus_clock_groups_in_member_subsystem_fbus_0_clock =
    subsystem_sbus_auto_subsystem_sbus_clock_groups_out_1_member_subsystem_fbus_0_clock; // @[LazyModule.scala 298:16]
  assign subsystem_fbus_auto_subsystem_fbus_clock_groups_in_member_subsystem_fbus_0_reset =
    subsystem_sbus_auto_subsystem_sbus_clock_groups_out_1_member_subsystem_fbus_0_reset; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_ready = bootROMDomainWrapper_auto_bootrom_in_a_ready; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_d_valid = bootROMDomainWrapper_auto_bootrom_in_d_valid; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_d_bits_size =
    bootROMDomainWrapper_auto_bootrom_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_d_bits_source =
    bootROMDomainWrapper_auto_bootrom_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_d_bits_data =
    bootROMDomainWrapper_auto_bootrom_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_aon_asource_out_a_ridx = aon_1_auto_isolation_in_a_ridx; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_aon_asource_out_a_safe_ridx_valid = aon_1_auto_isolation_in_a_safe_ridx_valid; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_aon_asource_out_a_safe_sink_reset_n =
    aon_1_auto_isolation_in_a_safe_sink_reset_n; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_aon_asource_out_d_mem_0_opcode = aon_1_auto_isolation_in_d_mem_0_opcode; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_aon_asource_out_d_mem_0_param = aon_1_auto_isolation_in_d_mem_0_param; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_aon_asource_out_d_mem_0_size = aon_1_auto_isolation_in_d_mem_0_size; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_aon_asource_out_d_mem_0_source = aon_1_auto_isolation_in_d_mem_0_source; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_aon_asource_out_d_mem_0_sink = aon_1_auto_isolation_in_d_mem_0_sink; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_aon_asource_out_d_mem_0_denied = aon_1_auto_isolation_in_d_mem_0_denied; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_aon_asource_out_d_mem_0_data = aon_1_auto_isolation_in_d_mem_0_data; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_aon_asource_out_d_mem_0_corrupt = aon_1_auto_isolation_in_d_mem_0_corrupt; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_aon_asource_out_d_widx = aon_1_auto_isolation_in_d_widx; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_aon_asource_out_d_safe_widx_valid = aon_1_auto_isolation_in_d_safe_widx_valid; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_aon_asource_out_d_safe_source_reset_n =
    aon_1_auto_isolation_in_d_safe_source_reset_n; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_ready =
    tile_prci_domain_auto_tl_slave_clock_xing_in_a_ready; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_valid =
    tile_prci_domain_auto_tl_slave_clock_xing_in_d_valid; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_opcode =
    tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_param =
    tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_param; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_size =
    tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_source =
    tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_sink =
    tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_sink; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_denied =
    tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_denied; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_data =
    tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_bits_corrupt =
    tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_corrupt; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_ready = debug_1_auto_dmInner_dmInner_tl_in_a_ready; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_valid = debug_1_auto_dmInner_dmInner_tl_in_d_valid; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_bits_opcode =
    debug_1_auto_dmInner_dmInner_tl_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_bits_size =
    debug_1_auto_dmInner_dmInner_tl_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_bits_source =
    debug_1_auto_dmInner_dmInner_tl_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_bits_data =
    debug_1_auto_dmInner_dmInner_tl_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_ready = clint_auto_in_a_ready; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_valid = clint_auto_in_d_valid; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_bits_opcode = clint_auto_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_bits_size = clint_auto_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_bits_source = clint_auto_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_bits_data = clint_auto_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_ready = plicDomainWrapper_auto_plic_in_a_ready; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_valid = plicDomainWrapper_auto_plic_in_d_valid; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_bits_opcode = plicDomainWrapper_auto_plic_in_d_bits_opcode
    ; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_bits_size = plicDomainWrapper_auto_plic_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_bits_source = plicDomainWrapper_auto_plic_in_d_bits_source
    ; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_bits_data = plicDomainWrapper_auto_plic_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_a_ready =
    subsystem_pbus_auto_bus_xing_in_a_ready; // @[LazyModule.scala 296:16]
  assign subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_valid =
    subsystem_pbus_auto_bus_xing_in_d_valid; // @[LazyModule.scala 296:16]
  assign subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_opcode =
    subsystem_pbus_auto_bus_xing_in_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_param =
    subsystem_pbus_auto_bus_xing_in_d_bits_param; // @[LazyModule.scala 296:16]
  assign subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_size =
    subsystem_pbus_auto_bus_xing_in_d_bits_size; // @[LazyModule.scala 296:16]
  assign subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_source =
    subsystem_pbus_auto_bus_xing_in_d_bits_source; // @[LazyModule.scala 296:16]
  assign subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_sink =
    subsystem_pbus_auto_bus_xing_in_d_bits_sink; // @[LazyModule.scala 296:16]
  assign subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_denied =
    subsystem_pbus_auto_bus_xing_in_d_bits_denied; // @[LazyModule.scala 296:16]
  assign subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_data =
    subsystem_pbus_auto_bus_xing_in_d_bits_data; // @[LazyModule.scala 296:16]
  assign subsystem_cbus_auto_coupler_to_bus_named_subsystem_pbus_bus_xing_out_d_bits_corrupt =
    subsystem_pbus_auto_bus_xing_in_d_bits_corrupt; // @[LazyModule.scala 296:16]
  assign subsystem_cbus_auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_1_clock =
    subsystem_sbus_auto_subsystem_sbus_clock_groups_out_0_member_subsystem_cbus_1_clock; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_1_reset =
    subsystem_sbus_auto_subsystem_sbus_clock_groups_out_0_member_subsystem_cbus_1_reset; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_0_clock =
    subsystem_sbus_auto_subsystem_sbus_clock_groups_out_0_member_subsystem_cbus_0_clock; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_subsystem_cbus_clock_groups_in_member_subsystem_cbus_0_reset =
    subsystem_sbus_auto_subsystem_sbus_clock_groups_out_0_member_subsystem_cbus_0_reset; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_bus_xing_in_a_valid =
    subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_valid; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_bus_xing_in_a_bits_opcode =
    subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_bus_xing_in_a_bits_param =
    subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_bus_xing_in_a_bits_size =
    subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_bus_xing_in_a_bits_source =
    subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_bus_xing_in_a_bits_address =
    subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_bus_xing_in_a_bits_mask =
    subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_bus_xing_in_a_bits_data =
    subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_bus_xing_in_a_bits_corrupt =
    subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign subsystem_cbus_auto_bus_xing_in_d_ready =
    subsystem_sbus_auto_coupler_to_bus_named_subsystem_cbus_bus_xing_out_d_ready; // @[LazyModule.scala 298:16]
  assign subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_ready =
    qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_a_ready; // @[LazyModule.scala 298:16]
  assign subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_d_valid =
    qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_d_valid; // @[LazyModule.scala 298:16]
  assign subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_d_bits_opcode =
    qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_d_bits_opcode; // @[LazyModule.scala 298:16]
  assign subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_d_bits_size =
    qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_d_bits_size; // @[LazyModule.scala 298:16]
  assign subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_d_bits_source =
    qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_d_bits_source; // @[LazyModule.scala 298:16]
  assign subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_d_bits_data =
    qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_d_bits_data; // @[LazyModule.scala 298:16]
  assign subsystem_mbus_auto_subsystem_mbus_clock_groups_in_member_subsystem_mbus_0_clock =
    subsystem_l2_wrapper_auto_subsystem_l2_clock_groups_out_member_subsystem_mbus_0_clock; // @[LazyModule.scala 296:16]
  assign subsystem_mbus_auto_subsystem_mbus_clock_groups_in_member_subsystem_mbus_0_reset =
    subsystem_l2_wrapper_auto_subsystem_l2_clock_groups_out_member_subsystem_mbus_0_reset; // @[LazyModule.scala 296:16]
  assign subsystem_mbus_auto_bus_xing_in_a_valid =
    subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_valid; // @[LazyModule.scala 296:16]
  assign subsystem_mbus_auto_bus_xing_in_a_bits_opcode =
    subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_opcode; // @[LazyModule.scala 296:16]
  assign subsystem_mbus_auto_bus_xing_in_a_bits_param =
    subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_param; // @[LazyModule.scala 296:16]
  assign subsystem_mbus_auto_bus_xing_in_a_bits_size =
    subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_size; // @[LazyModule.scala 296:16]
  assign subsystem_mbus_auto_bus_xing_in_a_bits_source =
    subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_source; // @[LazyModule.scala 296:16]
  assign subsystem_mbus_auto_bus_xing_in_a_bits_address =
    subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_address; // @[LazyModule.scala 296:16]
  assign subsystem_mbus_auto_bus_xing_in_a_bits_mask =
    subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_mask; // @[LazyModule.scala 296:16]
  assign subsystem_mbus_auto_bus_xing_in_a_bits_data =
    subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_bits_data; // @[LazyModule.scala 296:16]
  assign subsystem_mbus_auto_bus_xing_in_d_ready =
    subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_ready; // @[LazyModule.scala 296:16]
  assign subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_a_ready =
    subsystem_mbus_auto_bus_xing_in_a_ready; // @[LazyModule.scala 296:16]
  assign subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_valid =
    subsystem_mbus_auto_bus_xing_in_d_valid; // @[LazyModule.scala 296:16]
  assign subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_bits_opcode =
    subsystem_mbus_auto_bus_xing_in_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_bits_size =
    subsystem_mbus_auto_bus_xing_in_d_bits_size; // @[LazyModule.scala 296:16]
  assign subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_bits_source =
    subsystem_mbus_auto_bus_xing_in_d_bits_source; // @[LazyModule.scala 296:16]
  assign subsystem_l2_wrapper_auto_coupler_to_bus_named_subsystem_mbus_bus_xing_out_d_bits_data =
    subsystem_mbus_auto_bus_xing_in_d_bits_data; // @[LazyModule.scala 296:16]
  assign subsystem_l2_wrapper_auto_coherent_jbar_in_a_valid =
    subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_valid; // @[LazyModule.scala 298:16]
  assign subsystem_l2_wrapper_auto_coherent_jbar_in_a_bits_opcode =
    subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign subsystem_l2_wrapper_auto_coherent_jbar_in_a_bits_param =
    subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign subsystem_l2_wrapper_auto_coherent_jbar_in_a_bits_size =
    subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign subsystem_l2_wrapper_auto_coherent_jbar_in_a_bits_source =
    subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign subsystem_l2_wrapper_auto_coherent_jbar_in_a_bits_address =
    subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign subsystem_l2_wrapper_auto_coherent_jbar_in_a_bits_mask =
    subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign subsystem_l2_wrapper_auto_coherent_jbar_in_a_bits_data =
    subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign subsystem_l2_wrapper_auto_coherent_jbar_in_a_bits_corrupt =
    subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign subsystem_l2_wrapper_auto_coherent_jbar_in_b_ready =
    subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_b_ready; // @[LazyModule.scala 298:16]
  assign subsystem_l2_wrapper_auto_coherent_jbar_in_c_valid =
    subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_valid; // @[LazyModule.scala 298:16]
  assign subsystem_l2_wrapper_auto_coherent_jbar_in_c_bits_opcode =
    subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_opcode; // @[LazyModule.scala 298:16]
  assign subsystem_l2_wrapper_auto_coherent_jbar_in_c_bits_param =
    subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_param; // @[LazyModule.scala 298:16]
  assign subsystem_l2_wrapper_auto_coherent_jbar_in_c_bits_size =
    subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_size; // @[LazyModule.scala 298:16]
  assign subsystem_l2_wrapper_auto_coherent_jbar_in_c_bits_source =
    subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_source; // @[LazyModule.scala 298:16]
  assign subsystem_l2_wrapper_auto_coherent_jbar_in_c_bits_address =
    subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_address; // @[LazyModule.scala 298:16]
  assign subsystem_l2_wrapper_auto_coherent_jbar_in_c_bits_data =
    subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_data; // @[LazyModule.scala 298:16]
  assign subsystem_l2_wrapper_auto_coherent_jbar_in_c_bits_corrupt =
    subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_c_bits_corrupt; // @[LazyModule.scala 298:16]
  assign subsystem_l2_wrapper_auto_coherent_jbar_in_d_ready =
    subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_d_ready; // @[LazyModule.scala 298:16]
  assign subsystem_l2_wrapper_auto_coherent_jbar_in_e_valid =
    subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_e_valid; // @[LazyModule.scala 298:16]
  assign subsystem_l2_wrapper_auto_coherent_jbar_in_e_bits_sink =
    subsystem_sbus_auto_coupler_to_bus_named_subsystem_l2_widget_out_e_bits_sink; // @[LazyModule.scala 298:16]
  assign subsystem_l2_wrapper_auto_subsystem_l2_clock_groups_in_member_subsystem_l2_1_clock =
    subsystem_sbus_auto_subsystem_sbus_clock_groups_out_2_member_subsystem_l2_1_clock; // @[LazyModule.scala 298:16]
  assign subsystem_l2_wrapper_auto_subsystem_l2_clock_groups_in_member_subsystem_l2_1_reset =
    subsystem_sbus_auto_subsystem_sbus_clock_groups_out_2_member_subsystem_l2_1_reset; // @[LazyModule.scala 298:16]
  assign subsystem_l2_wrapper_auto_subsystem_l2_clock_groups_in_member_subsystem_l2_0_clock =
    subsystem_sbus_auto_subsystem_sbus_clock_groups_out_2_member_subsystem_l2_0_clock; // @[LazyModule.scala 298:16]
  assign subsystem_l2_wrapper_auto_subsystem_l2_clock_groups_in_member_subsystem_l2_0_reset =
    subsystem_sbus_auto_subsystem_sbus_clock_groups_out_2_member_subsystem_l2_0_reset; // @[LazyModule.scala 298:16]
  assign tile_prci_domain_auto_intsink_in_sync_0 = debug_1_auto_dmOuter_intsource_out_sync_0; // @[LazyModule.scala 296:16]
  assign tile_prci_domain_auto_tile_reset_domain_tile_hartid_in = tileHartIdNexusNode_auto_out; // @[LazyModule.scala 296:16]
  assign tile_prci_domain_auto_int_in_clock_xing_in_2_sync_0 = intsource_2_auto_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign tile_prci_domain_auto_int_in_clock_xing_in_1_sync_0 = intsource_1_auto_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign tile_prci_domain_auto_int_in_clock_xing_in_0_sync_0 = intsource_auto_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign tile_prci_domain_auto_int_in_clock_xing_in_0_sync_1 = intsource_auto_out_sync_1; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign tile_prci_domain_auto_tl_slave_clock_xing_in_a_valid =
    subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_valid; // @[LazyModule.scala 298:16]
  assign tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_opcode =
    subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_param =
    subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_size =
    subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_source =
    subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_address =
    subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_mask =
    subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_data =
    subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign tile_prci_domain_auto_tl_slave_clock_xing_in_a_bits_corrupt =
    subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign tile_prci_domain_auto_tl_slave_clock_xing_in_d_ready =
    subsystem_cbus_auto_coupler_to_tile_tl_slave_clock_xing_out_d_ready; // @[LazyModule.scala 298:16]
  assign tile_prci_domain_auto_tl_master_clock_xing_out_a_ready =
    subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_a_ready; // @[LazyModule.scala 296:16]
  assign tile_prci_domain_auto_tl_master_clock_xing_out_b_valid =
    subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_b_valid; // @[LazyModule.scala 296:16]
  assign tile_prci_domain_auto_tl_master_clock_xing_out_b_bits_param =
    subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_b_bits_param; // @[LazyModule.scala 296:16]
  assign tile_prci_domain_auto_tl_master_clock_xing_out_b_bits_address =
    subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_b_bits_address; // @[LazyModule.scala 296:16]
  assign tile_prci_domain_auto_tl_master_clock_xing_out_c_ready =
    subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_c_ready; // @[LazyModule.scala 296:16]
  assign tile_prci_domain_auto_tl_master_clock_xing_out_d_valid =
    subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_valid; // @[LazyModule.scala 296:16]
  assign tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_opcode =
    subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_opcode; // @[LazyModule.scala 296:16]
  assign tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_param =
    subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_param; // @[LazyModule.scala 296:16]
  assign tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_size =
    subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_size; // @[LazyModule.scala 296:16]
  assign tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_source =
    subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_source; // @[LazyModule.scala 296:16]
  assign tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_sink =
    subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_sink; // @[LazyModule.scala 296:16]
  assign tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_denied =
    subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_denied; // @[LazyModule.scala 296:16]
  assign tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_data =
    subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_data; // @[LazyModule.scala 296:16]
  assign tile_prci_domain_auto_tl_master_clock_xing_out_d_bits_corrupt =
    subsystem_sbus_auto_coupler_from_tile_tl_master_clock_xing_in_d_bits_corrupt; // @[LazyModule.scala 296:16]
  assign tile_prci_domain_auto_tap_clock_in_clock = subsystem_sbus_auto_fixedClockNode_out_1_clock; // @[LazyModule.scala 298:16]
  assign tile_prci_domain_auto_tap_clock_in_reset = subsystem_sbus_auto_fixedClockNode_out_1_reset; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_0 = ibus_auto_int_bus_int_out_0; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_1 = ibus_auto_int_bus_int_out_1; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_2 = ibus_auto_int_bus_int_out_2; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_3 = ibus_auto_int_bus_int_out_3; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_4 = ibus_auto_int_bus_int_out_4; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_5 = ibus_auto_int_bus_int_out_5; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_6 = ibus_auto_int_bus_int_out_6; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_7 = ibus_auto_int_bus_int_out_7; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_8 = ibus_auto_int_bus_int_out_8; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_9 = ibus_auto_int_bus_int_out_9; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_10 = ibus_auto_int_bus_int_out_10; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_11 = ibus_auto_int_bus_int_out_11; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_12 = ibus_auto_int_bus_int_out_12; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_13 = ibus_auto_int_bus_int_out_13; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_14 = ibus_auto_int_bus_int_out_14; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_15 = ibus_auto_int_bus_int_out_15; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_16 = ibus_auto_int_bus_int_out_16; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_17 = ibus_auto_int_bus_int_out_17; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_18 = ibus_auto_int_bus_int_out_18; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_19 = ibus_auto_int_bus_int_out_19; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_20 = ibus_auto_int_bus_int_out_20; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_21 = ibus_auto_int_bus_int_out_21; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_22 = ibus_auto_int_bus_int_out_22; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_23 = ibus_auto_int_bus_int_out_23; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_24 = ibus_auto_int_bus_int_out_24; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_25 = ibus_auto_int_bus_int_out_25; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_26 = ibus_auto_int_bus_int_out_26; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_27 = ibus_auto_int_bus_int_out_27; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_28 = ibus_auto_int_bus_int_out_28; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_29 = ibus_auto_int_bus_int_out_29; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_30 = ibus_auto_int_bus_int_out_30; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_31 = ibus_auto_int_bus_int_out_31; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_32 = ibus_auto_int_bus_int_out_32; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_33 = ibus_auto_int_bus_int_out_33; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_34 = ibus_auto_int_bus_int_out_34; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_35 = ibus_auto_int_bus_int_out_35; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_36 = ibus_auto_int_bus_int_out_36; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_37 = ibus_auto_int_bus_int_out_37; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_38 = ibus_auto_int_bus_int_out_38; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_39 = ibus_auto_int_bus_int_out_39; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_40 = ibus_auto_int_bus_int_out_40; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_41 = ibus_auto_int_bus_int_out_41; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_42 = ibus_auto_int_bus_int_out_42; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_43 = ibus_auto_int_bus_int_out_43; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_44 = ibus_auto_int_bus_int_out_44; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_45 = ibus_auto_int_bus_int_out_45; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_46 = ibus_auto_int_bus_int_out_46; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_47 = ibus_auto_int_bus_int_out_47; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_48 = ibus_auto_int_bus_int_out_48; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_49 = ibus_auto_int_bus_int_out_49; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_50 = ibus_auto_int_bus_int_out_50; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_51 = ibus_auto_int_bus_int_out_51; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_52 = ibus_auto_int_bus_int_out_52; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_53 = ibus_auto_int_bus_int_out_53; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_54 = ibus_auto_int_bus_int_out_54; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_int_in_55 = ibus_auto_int_bus_int_out_55; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_in_a_valid = subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_valid; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_in_a_bits_opcode = subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_opcode
    ; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_in_a_bits_param = subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_in_a_bits_size = subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_in_a_bits_source = subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_source
    ; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_in_a_bits_address =
    subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_in_a_bits_mask = subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_in_a_bits_data = subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_in_a_bits_corrupt =
    subsystem_cbus_auto_coupler_to_plic_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_plic_in_d_ready = subsystem_cbus_auto_coupler_to_plic_fragmenter_out_d_ready; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_clock_in_clock = subsystem_cbus_auto_fixedClockNode_out_0_clock; // @[LazyModule.scala 298:16]
  assign plicDomainWrapper_auto_clock_in_reset = subsystem_cbus_auto_fixedClockNode_out_0_reset; // @[LazyModule.scala 298:16]
  assign clint_clock = subsystem_cbus_clock; // @[CLINT.scala 115:26]
  assign clint_reset = subsystem_cbus_reset; // @[CLINT.scala 116:26]
  assign clint_auto_in_a_valid = subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_valid; // @[LazyModule.scala 298:16]
  assign clint_auto_in_a_bits_opcode = subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign clint_auto_in_a_bits_param = subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign clint_auto_in_a_bits_size = subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign clint_auto_in_a_bits_source = subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign clint_auto_in_a_bits_address = subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign clint_auto_in_a_bits_mask = subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign clint_auto_in_a_bits_data = subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign clint_auto_in_a_bits_corrupt = subsystem_cbus_auto_coupler_to_clint_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign clint_auto_in_d_ready = subsystem_cbus_auto_coupler_to_clint_fragmenter_out_d_ready; // @[LazyModule.scala 298:16]
  assign clint_io_rtcTick = rtc_tick; // @[MockAONPeriphery.scala 50:29]
  assign debug_1_auto_dmInner_dmInner_tl_in_a_valid = subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_valid; // @[LazyModule.scala 298:16]
  assign debug_1_auto_dmInner_dmInner_tl_in_a_bits_opcode =
    subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign debug_1_auto_dmInner_dmInner_tl_in_a_bits_param =
    subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign debug_1_auto_dmInner_dmInner_tl_in_a_bits_size =
    subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign debug_1_auto_dmInner_dmInner_tl_in_a_bits_source =
    subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign debug_1_auto_dmInner_dmInner_tl_in_a_bits_address =
    subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign debug_1_auto_dmInner_dmInner_tl_in_a_bits_mask =
    subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign debug_1_auto_dmInner_dmInner_tl_in_a_bits_data =
    subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign debug_1_auto_dmInner_dmInner_tl_in_a_bits_corrupt =
    subsystem_cbus_auto_coupler_to_debug_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign debug_1_auto_dmInner_dmInner_tl_in_d_ready = subsystem_cbus_auto_coupler_to_debug_fragmenter_out_d_ready; // @[LazyModule.scala 298:16]
  assign debug_1_io_debug_clock = debug_clock; // @[Periphery.scala 144:38]
  assign debug_1_io_dmi_dmi_req_valid = dtm_io_dmi_req_valid; // @[Periphery.scala 174:40]
  assign debug_1_io_dmi_dmi_req_bits_addr = dtm_io_dmi_req_bits_addr; // @[Periphery.scala 174:40]
  assign debug_1_io_dmi_dmi_req_bits_data = dtm_io_dmi_req_bits_data; // @[Periphery.scala 174:40]
  assign debug_1_io_dmi_dmi_req_bits_op = dtm_io_dmi_req_bits_op; // @[Periphery.scala 174:40]
  assign debug_1_io_dmi_dmi_resp_ready = dtm_io_dmi_resp_ready; // @[Periphery.scala 174:40]
  assign debug_1_io_dmi_dmiClock = debug_systemjtag_jtag_TCK; // @[Periphery.scala 175:45]
  assign debug_1_io_dmi_dmiReset = debug_systemjtag_reset; // @[Periphery.scala 176:45]
  assign intsource_clock = clock;
  assign intsource_reset = reset;
  assign intsource_auto_in_0 = clint_auto_int_out_0; // @[LazyModule.scala 298:16]
  assign intsource_auto_in_1 = clint_auto_int_out_1; // @[LazyModule.scala 298:16]
  assign intsource_1_clock = clock;
  assign intsource_1_reset = reset;
  assign intsource_1_auto_in_0 = plicDomainWrapper_auto_plic_int_out_0_0; // @[LazyModule.scala 298:16]
  assign intsource_2_clock = clock;
  assign intsource_2_reset = reset;
  assign intsource_2_auto_in_0 = plicDomainWrapper_auto_plic_int_out_1_0; // @[LazyModule.scala 298:16]
  assign intsink_1_auto_in_sync_0 = tile_prci_domain_auto_int_out_clock_xing_out_0_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_2_auto_in_sync_0 = tile_prci_domain_auto_int_out_clock_xing_out_1_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_3_auto_in_sync_0 = tile_prci_domain_auto_int_out_clock_xing_out_2_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign aon_1_auto_isolation_in_a_mem_0_opcode = subsystem_cbus_auto_coupler_to_aon_asource_out_a_mem_0_opcode; // @[LazyModule.scala 298:16]
  assign aon_1_auto_isolation_in_a_mem_0_param = subsystem_cbus_auto_coupler_to_aon_asource_out_a_mem_0_param; // @[LazyModule.scala 298:16]
  assign aon_1_auto_isolation_in_a_mem_0_size = subsystem_cbus_auto_coupler_to_aon_asource_out_a_mem_0_size; // @[LazyModule.scala 298:16]
  assign aon_1_auto_isolation_in_a_mem_0_source = subsystem_cbus_auto_coupler_to_aon_asource_out_a_mem_0_source; // @[LazyModule.scala 298:16]
  assign aon_1_auto_isolation_in_a_mem_0_address = subsystem_cbus_auto_coupler_to_aon_asource_out_a_mem_0_address; // @[LazyModule.scala 298:16]
  assign aon_1_auto_isolation_in_a_mem_0_mask = subsystem_cbus_auto_coupler_to_aon_asource_out_a_mem_0_mask; // @[LazyModule.scala 298:16]
  assign aon_1_auto_isolation_in_a_mem_0_data = subsystem_cbus_auto_coupler_to_aon_asource_out_a_mem_0_data; // @[LazyModule.scala 298:16]
  assign aon_1_auto_isolation_in_a_mem_0_corrupt = subsystem_cbus_auto_coupler_to_aon_asource_out_a_mem_0_corrupt; // @[LazyModule.scala 298:16]
  assign aon_1_auto_isolation_in_a_widx = subsystem_cbus_auto_coupler_to_aon_asource_out_a_widx; // @[LazyModule.scala 298:16]
  assign aon_1_auto_isolation_in_a_safe_widx_valid = subsystem_cbus_auto_coupler_to_aon_asource_out_a_safe_widx_valid; // @[LazyModule.scala 298:16]
  assign aon_1_auto_isolation_in_a_safe_source_reset_n =
    subsystem_cbus_auto_coupler_to_aon_asource_out_a_safe_source_reset_n; // @[LazyModule.scala 298:16]
  assign aon_1_auto_isolation_in_d_ridx = subsystem_cbus_auto_coupler_to_aon_asource_out_d_ridx; // @[LazyModule.scala 298:16]
  assign aon_1_auto_isolation_in_d_safe_ridx_valid = subsystem_cbus_auto_coupler_to_aon_asource_out_d_safe_ridx_valid; // @[LazyModule.scala 298:16]
  assign aon_1_auto_isolation_in_d_safe_sink_reset_n =
    subsystem_cbus_auto_coupler_to_aon_asource_out_d_safe_sink_reset_n; // @[LazyModule.scala 298:16]
  assign aon_1_io_pins_erst_n_i_ival = aon_pins_erst_n_i_ival; // @[MockAONPeriphery.scala 37:7]
  assign aon_1_io_pins_lfextclk_i_ival = aon_pins_lfextclk_i_ival; // @[MockAONPeriphery.scala 37:7]
  assign aon_1_io_ndreset = debug_1_io_ctrl_ndreset; // @[MockAONPeriphery.scala 53:31]
  assign intsink_4_clock = clock;
  assign intsink_4_auto_in_sync_0 = aon_1_auto_intsource_out_sync_0; // @[LazyModule.scala 298:16]
  assign intsink_4_auto_in_sync_1 = aon_1_auto_intsource_out_sync_1; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_auto_uart_0_control_xing_in_a_valid =
    subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_opcode =
    subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_param =
    subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_size =
    subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_source =
    subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_address =
    subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_mask =
    subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_data =
    subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_auto_uart_0_control_xing_in_a_bits_corrupt =
    subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_auto_uart_0_control_xing_in_d_ready =
    subsystem_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_auto_uart_0_io_out_rxd = uart_0_rxd; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign uartClockDomainWrapper_auto_clock_in_clock = subsystem_pbus_auto_fixedClockNode_out_0_clock; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_auto_clock_in_reset = subsystem_pbus_auto_fixedClockNode_out_0_reset; // @[LazyModule.scala 298:16]
  assign intsink_5_auto_in_sync_0 = uartClockDomainWrapper_auto_uart_0_int_xing_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_valid =
    subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_valid; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_opcode =
    subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_param =
    subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_size =
    subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_source =
    subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_address =
    subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_mask =
    subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_data =
    subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_1_auto_uart_1_control_xing_in_a_bits_corrupt =
    subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_1_auto_uart_1_control_xing_in_d_ready =
    subsystem_pbus_auto_coupler_to_device_named_uart_1_control_xing_out_d_ready; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_1_auto_uart_1_io_out_rxd = uart_1_rxd; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign uartClockDomainWrapper_1_auto_clock_in_clock = subsystem_pbus_auto_fixedClockNode_out_1_clock; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_1_auto_clock_in_reset = subsystem_pbus_auto_fixedClockNode_out_1_reset; // @[LazyModule.scala 298:16]
  assign intsink_6_auto_in_sync_0 = uartClockDomainWrapper_1_auto_uart_1_int_xing_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign uartClockDomainWrapper_2_auto_uart_2_control_xing_in_a_valid =
    subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_a_valid; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_2_auto_uart_2_control_xing_in_a_bits_opcode =
    subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_2_auto_uart_2_control_xing_in_a_bits_param =
    subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_2_auto_uart_2_control_xing_in_a_bits_size =
    subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_2_auto_uart_2_control_xing_in_a_bits_source =
    subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_2_auto_uart_2_control_xing_in_a_bits_address =
    subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_2_auto_uart_2_control_xing_in_a_bits_mask =
    subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_2_auto_uart_2_control_xing_in_a_bits_data =
    subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_2_auto_uart_2_control_xing_in_a_bits_corrupt =
    subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_2_auto_uart_2_control_xing_in_d_ready =
    subsystem_pbus_auto_coupler_to_device_named_uart_2_control_xing_out_d_ready; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_2_auto_uart_2_io_out_rxd = uart_2_rxd; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign uartClockDomainWrapper_2_auto_clock_in_clock = subsystem_pbus_auto_fixedClockNode_out_2_clock; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_2_auto_clock_in_reset = subsystem_pbus_auto_fixedClockNode_out_2_reset; // @[LazyModule.scala 298:16]
  assign intsink_7_auto_in_sync_0 = uartClockDomainWrapper_2_auto_uart_2_int_xing_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign uartClockDomainWrapper_3_auto_uart_3_control_xing_in_a_valid =
    subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_a_valid; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_3_auto_uart_3_control_xing_in_a_bits_opcode =
    subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_3_auto_uart_3_control_xing_in_a_bits_param =
    subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_3_auto_uart_3_control_xing_in_a_bits_size =
    subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_3_auto_uart_3_control_xing_in_a_bits_source =
    subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_3_auto_uart_3_control_xing_in_a_bits_address =
    subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_3_auto_uart_3_control_xing_in_a_bits_mask =
    subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_3_auto_uart_3_control_xing_in_a_bits_data =
    subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_3_auto_uart_3_control_xing_in_a_bits_corrupt =
    subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_3_auto_uart_3_control_xing_in_d_ready =
    subsystem_pbus_auto_coupler_to_device_named_uart_3_control_xing_out_d_ready; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_3_auto_uart_3_io_out_rxd = uart_3_rxd; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign uartClockDomainWrapper_3_auto_clock_in_clock = subsystem_pbus_auto_fixedClockNode_out_3_clock; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_3_auto_clock_in_reset = subsystem_pbus_auto_fixedClockNode_out_3_reset; // @[LazyModule.scala 298:16]
  assign intsink_8_auto_in_sync_0 = uartClockDomainWrapper_3_auto_uart_3_int_xing_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign uartClockDomainWrapper_4_auto_uart_4_control_xing_in_a_valid =
    subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_a_valid; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_4_auto_uart_4_control_xing_in_a_bits_opcode =
    subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_4_auto_uart_4_control_xing_in_a_bits_param =
    subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_4_auto_uart_4_control_xing_in_a_bits_size =
    subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_4_auto_uart_4_control_xing_in_a_bits_source =
    subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_4_auto_uart_4_control_xing_in_a_bits_address =
    subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_4_auto_uart_4_control_xing_in_a_bits_mask =
    subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_4_auto_uart_4_control_xing_in_a_bits_data =
    subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_4_auto_uart_4_control_xing_in_a_bits_corrupt =
    subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_4_auto_uart_4_control_xing_in_d_ready =
    subsystem_pbus_auto_coupler_to_device_named_uart_4_control_xing_out_d_ready; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_4_auto_uart_4_io_out_rxd = uart_4_rxd; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign uartClockDomainWrapper_4_auto_clock_in_clock = subsystem_pbus_auto_fixedClockNode_out_4_clock; // @[LazyModule.scala 298:16]
  assign uartClockDomainWrapper_4_auto_clock_in_reset = subsystem_pbus_auto_fixedClockNode_out_4_reset; // @[LazyModule.scala 298:16]
  assign intsink_9_auto_in_sync_0 = uartClockDomainWrapper_4_auto_uart_4_int_xing_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_valid =
    subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_valid; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_opcode =
    subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_param =
    subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_size =
    subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_source =
    subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_address =
    subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_mask =
    subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_a_bits_corrupt =
    subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_auto_qspi_0_mem_xing_in_d_ready =
    subsystem_pbus_auto_coupler_to_device_named_qspi_0_mem_xing_out_d_ready; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_valid =
    subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_valid; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_opcode =
    subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_param =
    subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_size =
    subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_source =
    subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_address =
    subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_mask =
    subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_data =
    subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_auto_qspi_0_control_xing_in_a_bits_corrupt =
    subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_auto_qspi_0_control_xing_in_d_ready =
    subsystem_pbus_auto_coupler_to_device_named_qspi_0_control_xing_out_d_ready; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_auto_qspi_0_io_out_dq_0_i = qspi_0_dq_0_i; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign qspiClockDomainWrapper_auto_qspi_0_io_out_dq_1_i = qspi_0_dq_1_i; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign qspiClockDomainWrapper_auto_qspi_0_io_out_dq_2_i = qspi_0_dq_2_i; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign qspiClockDomainWrapper_auto_qspi_0_io_out_dq_3_i = qspi_0_dq_3_i; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign qspiClockDomainWrapper_auto_clock_in_clock = subsystem_pbus_auto_fixedClockNode_out_5_clock; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_auto_clock_in_reset = subsystem_pbus_auto_fixedClockNode_out_5_reset; // @[LazyModule.scala 298:16]
  assign intsink_10_auto_in_sync_0 = qspiClockDomainWrapper_auto_qspi_0_int_xing_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_a_valid =
    subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_valid; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_a_bits_opcode =
    subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_a_bits_param =
    subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_a_bits_size =
    subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_a_bits_source =
    subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_a_bits_address =
    subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_a_bits_mask =
    subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_a_bits_data =
    subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_a_bits_corrupt =
    subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_1_auto_qspi_ram_0_mem_xing_in_d_ready =
    subsystem_mbus_auto_coupler_to_device_named_qspi_ram_0_mem_xing_out_d_ready; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_a_valid =
    subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_valid; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_a_bits_opcode =
    subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_a_bits_param =
    subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_a_bits_size =
    subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_a_bits_source =
    subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_a_bits_address =
    subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_a_bits_mask =
    subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_a_bits_data =
    subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_a_bits_corrupt =
    subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_1_auto_qspi_ram_0_control_xing_in_d_ready =
    subsystem_pbus_auto_coupler_to_device_named_qspi_ram_0_control_xing_out_d_ready; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_dq_0_i = qspi_ram_0_dq_0_i; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_dq_1_i = qspi_ram_0_dq_1_i; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_dq_2_i = qspi_ram_0_dq_2_i; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign qspiClockDomainWrapper_1_auto_qspi_ram_0_io_out_dq_3_i = qspi_ram_0_dq_3_i; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign qspiClockDomainWrapper_1_auto_clock_in_clock = subsystem_pbus_auto_fixedClockNode_out_6_clock; // @[LazyModule.scala 298:16]
  assign qspiClockDomainWrapper_1_auto_clock_in_reset = subsystem_pbus_auto_fixedClockNode_out_6_reset; // @[LazyModule.scala 298:16]
  assign intsink_11_auto_in_sync_0 = qspiClockDomainWrapper_1_auto_qspi_ram_0_int_xing_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign spiClockDomainWrapper_auto_spi_0_control_xing_in_a_valid =
    subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_a_valid; // @[LazyModule.scala 298:16]
  assign spiClockDomainWrapper_auto_spi_0_control_xing_in_a_bits_opcode =
    subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign spiClockDomainWrapper_auto_spi_0_control_xing_in_a_bits_param =
    subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign spiClockDomainWrapper_auto_spi_0_control_xing_in_a_bits_size =
    subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign spiClockDomainWrapper_auto_spi_0_control_xing_in_a_bits_source =
    subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign spiClockDomainWrapper_auto_spi_0_control_xing_in_a_bits_address =
    subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign spiClockDomainWrapper_auto_spi_0_control_xing_in_a_bits_mask =
    subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign spiClockDomainWrapper_auto_spi_0_control_xing_in_a_bits_data =
    subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign spiClockDomainWrapper_auto_spi_0_control_xing_in_a_bits_corrupt =
    subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign spiClockDomainWrapper_auto_spi_0_control_xing_in_d_ready =
    subsystem_pbus_auto_coupler_to_device_named_spi_0_control_xing_out_d_ready; // @[LazyModule.scala 298:16]
  assign spiClockDomainWrapper_auto_spi_0_io_out_dq_0_i = spi_0_dq_0_i; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign spiClockDomainWrapper_auto_spi_0_io_out_dq_1_i = spi_0_dq_1_i; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign spiClockDomainWrapper_auto_spi_0_io_out_dq_2_i = spi_0_dq_2_i; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign spiClockDomainWrapper_auto_spi_0_io_out_dq_3_i = spi_0_dq_3_i; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign spiClockDomainWrapper_auto_clock_in_clock = subsystem_pbus_auto_fixedClockNode_out_7_clock; // @[LazyModule.scala 298:16]
  assign spiClockDomainWrapper_auto_clock_in_reset = subsystem_pbus_auto_fixedClockNode_out_7_reset; // @[LazyModule.scala 298:16]
  assign intsink_12_auto_in_sync_0 = spiClockDomainWrapper_auto_spi_0_int_xing_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_valid =
    subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_valid; // @[LazyModule.scala 298:16]
  assign gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_opcode =
    subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_param =
    subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_size =
    subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_source =
    subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_address =
    subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_mask =
    subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_data =
    subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign gpioClockDomainWrapper_auto_gpio_0_control_xing_in_a_bits_corrupt =
    subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign gpioClockDomainWrapper_auto_gpio_0_control_xing_in_d_ready =
    subsystem_pbus_auto_coupler_to_device_named_gpio_0_control_xing_out_d_ready; // @[LazyModule.scala 298:16]
  assign gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_0_o_oval = iof_0_iof_0_0_o_oval; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_1_o_oval = iof_0_iof_0_1_o_oval; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_2_o_oval = iof_0_iof_0_2_o_oval; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_2_o_oe = iof_0_iof_0_2_o_oe; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_2_o_ie = iof_0_iof_0_2_o_ie; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_3_o_oval = iof_0_iof_0_3_o_oval; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_3_o_oe = iof_0_iof_0_3_o_oe; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_3_o_ie = iof_0_iof_0_3_o_ie; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_4_o_oval = iof_0_iof_0_4_o_oval; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_4_o_oe = iof_0_iof_0_4_o_oe; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_4_o_ie = iof_0_iof_0_4_o_ie; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_5_o_oval = iof_0_iof_0_5_o_oval; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_5_o_oe = iof_0_iof_0_5_o_oe; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_5_o_ie = iof_0_iof_0_5_o_ie; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_12_o_oe = iof_0_iof_0_12_o_oe; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_13_o_oe = iof_0_iof_0_13_o_oe; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_14_o_oe = iof_0_iof_0_14_o_oe; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_15_o_oe = iof_0_iof_0_15_o_oe; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_17_o_oval = iof_0_iof_0_17_o_oval; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_19_o_oval = iof_0_iof_0_19_o_oval; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_21_o_oval = iof_0_iof_0_21_o_oval; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_23_o_oval = iof_0_iof_0_23_o_oval; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_0_24_o_oval = iof_0_iof_0_24_o_oval; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_1_12_o_oval = iof_0_iof_1_12_o_oval; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_1_13_o_oval = iof_0_iof_1_13_o_oval; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_1_14_o_oval = iof_0_iof_1_14_o_oval; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_1_15_o_oval = iof_0_iof_1_15_o_oval; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_1_16_o_oval = iof_0_iof_1_16_o_oval; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_1_17_o_oval = iof_0_iof_1_17_o_oval; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_1_18_o_oval = iof_0_iof_1_18_o_oval; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_1_19_o_oval = iof_0_iof_1_19_o_oval; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_1_20_o_oval = iof_0_iof_1_20_o_oval; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_1_21_o_oval = iof_0_iof_1_21_o_oval; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_1_22_o_oval = iof_0_iof_1_22_o_oval; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_iof_out_iof_1_23_o_oval = iof_0_iof_1_23_o_oval; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_io_out_pins_0_i_ival = gpio_0_pins_0_i_ival; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_io_out_pins_1_i_ival = gpio_0_pins_1_i_ival; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_io_out_pins_2_i_ival = gpio_0_pins_2_i_ival; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_io_out_pins_3_i_ival = gpio_0_pins_3_i_ival; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_io_out_pins_4_i_ival = gpio_0_pins_4_i_ival; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_io_out_pins_5_i_ival = gpio_0_pins_5_i_ival; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_io_out_pins_6_i_ival = gpio_0_pins_6_i_ival; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_io_out_pins_7_i_ival = gpio_0_pins_7_i_ival; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_io_out_pins_8_i_ival = gpio_0_pins_8_i_ival; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_io_out_pins_9_i_ival = gpio_0_pins_9_i_ival; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_io_out_pins_10_i_ival = gpio_0_pins_10_i_ival; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_io_out_pins_11_i_ival = gpio_0_pins_11_i_ival; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_io_out_pins_12_i_ival = gpio_0_pins_12_i_ival; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_io_out_pins_13_i_ival = gpio_0_pins_13_i_ival; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_io_out_pins_14_i_ival = gpio_0_pins_14_i_ival; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_io_out_pins_15_i_ival = gpio_0_pins_15_i_ival; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_io_out_pins_16_i_ival = gpio_0_pins_16_i_ival; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_io_out_pins_17_i_ival = gpio_0_pins_17_i_ival; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_io_out_pins_18_i_ival = gpio_0_pins_18_i_ival; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_io_out_pins_19_i_ival = gpio_0_pins_19_i_ival; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_io_out_pins_20_i_ival = gpio_0_pins_20_i_ival; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_io_out_pins_21_i_ival = gpio_0_pins_21_i_ival; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_io_out_pins_22_i_ival = gpio_0_pins_22_i_ival; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_io_out_pins_23_i_ival = gpio_0_pins_23_i_ival; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_io_out_pins_24_i_ival = gpio_0_pins_24_i_ival; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_io_out_pins_25_i_ival = gpio_0_pins_25_i_ival; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_io_out_pins_26_i_ival = gpio_0_pins_26_i_ival; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_io_out_pins_27_i_ival = gpio_0_pins_27_i_ival; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_io_out_pins_28_i_ival = gpio_0_pins_28_i_ival; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_io_out_pins_29_i_ival = gpio_0_pins_29_i_ival; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_io_out_pins_30_i_ival = gpio_0_pins_30_i_ival; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_gpio_0_io_out_pins_31_i_ival = gpio_0_pins_31_i_ival; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign gpioClockDomainWrapper_auto_clock_in_clock = subsystem_pbus_auto_fixedClockNode_out_8_clock; // @[LazyModule.scala 298:16]
  assign gpioClockDomainWrapper_auto_clock_in_reset = subsystem_pbus_auto_fixedClockNode_out_8_reset; // @[LazyModule.scala 298:16]
  assign intsink_13_auto_in_sync_0 = gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_13_auto_in_sync_1 = gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_1; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_13_auto_in_sync_2 = gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_2; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_13_auto_in_sync_3 = gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_3; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_13_auto_in_sync_4 = gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_4; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_13_auto_in_sync_5 = gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_5; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_13_auto_in_sync_6 = gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_6; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_13_auto_in_sync_7 = gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_7; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_13_auto_in_sync_8 = gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_8; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_13_auto_in_sync_9 = gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_9; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_13_auto_in_sync_10 = gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_10; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_13_auto_in_sync_11 = gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_11; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_13_auto_in_sync_12 = gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_12; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_13_auto_in_sync_13 = gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_13; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_13_auto_in_sync_14 = gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_14; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_13_auto_in_sync_15 = gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_15; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_13_auto_in_sync_16 = gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_16; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_13_auto_in_sync_17 = gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_17; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_13_auto_in_sync_18 = gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_18; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_13_auto_in_sync_19 = gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_19; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_13_auto_in_sync_20 = gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_20; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_13_auto_in_sync_21 = gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_21; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_13_auto_in_sync_22 = gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_22; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_13_auto_in_sync_23 = gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_23; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_13_auto_in_sync_24 = gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_24; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_13_auto_in_sync_25 = gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_25; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_13_auto_in_sync_26 = gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_26; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_13_auto_in_sync_27 = gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_27; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_13_auto_in_sync_28 = gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_28; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_13_auto_in_sync_29 = gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_29; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_13_auto_in_sync_30 = gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_30; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_13_auto_in_sync_31 = gpioClockDomainWrapper_auto_gpio_0_int_xing_out_sync_31; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign pwmClockDomainWrapper_auto_pwm_0_control_xing_in_a_valid =
    subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_a_valid; // @[LazyModule.scala 298:16]
  assign pwmClockDomainWrapper_auto_pwm_0_control_xing_in_a_bits_opcode =
    subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign pwmClockDomainWrapper_auto_pwm_0_control_xing_in_a_bits_param =
    subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign pwmClockDomainWrapper_auto_pwm_0_control_xing_in_a_bits_size =
    subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign pwmClockDomainWrapper_auto_pwm_0_control_xing_in_a_bits_source =
    subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign pwmClockDomainWrapper_auto_pwm_0_control_xing_in_a_bits_address =
    subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign pwmClockDomainWrapper_auto_pwm_0_control_xing_in_a_bits_mask =
    subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign pwmClockDomainWrapper_auto_pwm_0_control_xing_in_a_bits_data =
    subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign pwmClockDomainWrapper_auto_pwm_0_control_xing_in_a_bits_corrupt =
    subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign pwmClockDomainWrapper_auto_pwm_0_control_xing_in_d_ready =
    subsystem_pbus_auto_coupler_to_device_named_pwm_0_control_xing_out_d_ready; // @[LazyModule.scala 298:16]
  assign pwmClockDomainWrapper_auto_clock_in_clock = subsystem_pbus_auto_fixedClockNode_out_9_clock; // @[LazyModule.scala 298:16]
  assign pwmClockDomainWrapper_auto_clock_in_reset = subsystem_pbus_auto_fixedClockNode_out_9_reset; // @[LazyModule.scala 298:16]
  assign intsink_14_auto_in_sync_0 = pwmClockDomainWrapper_auto_pwm_0_int_xing_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_14_auto_in_sync_1 = pwmClockDomainWrapper_auto_pwm_0_int_xing_out_sync_1; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_14_auto_in_sync_2 = pwmClockDomainWrapper_auto_pwm_0_int_xing_out_sync_2; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_14_auto_in_sync_3 = pwmClockDomainWrapper_auto_pwm_0_int_xing_out_sync_3; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_a_valid =
    subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_a_valid; // @[LazyModule.scala 298:16]
  assign pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_a_bits_opcode =
    subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_a_bits_param =
    subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_a_bits_size =
    subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_a_bits_source =
    subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_a_bits_address =
    subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_a_bits_mask =
    subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_a_bits_data =
    subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_a_bits_corrupt =
    subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign pwmClockDomainWrapper_1_auto_pwm_1_control_xing_in_d_ready =
    subsystem_pbus_auto_coupler_to_device_named_pwm_1_control_xing_out_d_ready; // @[LazyModule.scala 298:16]
  assign pwmClockDomainWrapper_1_auto_clock_in_clock = subsystem_pbus_auto_fixedClockNode_out_10_clock; // @[LazyModule.scala 298:16]
  assign pwmClockDomainWrapper_1_auto_clock_in_reset = subsystem_pbus_auto_fixedClockNode_out_10_reset; // @[LazyModule.scala 298:16]
  assign intsink_15_auto_in_sync_0 = pwmClockDomainWrapper_1_auto_pwm_1_int_xing_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_15_auto_in_sync_1 = pwmClockDomainWrapper_1_auto_pwm_1_int_xing_out_sync_1; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_15_auto_in_sync_2 = pwmClockDomainWrapper_1_auto_pwm_1_int_xing_out_sync_2; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_15_auto_in_sync_3 = pwmClockDomainWrapper_1_auto_pwm_1_int_xing_out_sync_3; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_a_valid =
    subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_a_valid; // @[LazyModule.scala 298:16]
  assign pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_a_bits_opcode =
    subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_a_bits_param =
    subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_a_bits_size =
    subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_a_bits_source =
    subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_a_bits_address =
    subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_a_bits_mask =
    subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_a_bits_data =
    subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_a_bits_corrupt =
    subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign pwmClockDomainWrapper_2_auto_pwm_2_control_xing_in_d_ready =
    subsystem_pbus_auto_coupler_to_device_named_pwm_2_control_xing_out_d_ready; // @[LazyModule.scala 298:16]
  assign pwmClockDomainWrapper_2_auto_clock_in_clock = subsystem_pbus_auto_fixedClockNode_out_11_clock; // @[LazyModule.scala 298:16]
  assign pwmClockDomainWrapper_2_auto_clock_in_reset = subsystem_pbus_auto_fixedClockNode_out_11_reset; // @[LazyModule.scala 298:16]
  assign intsink_16_auto_in_sync_0 = pwmClockDomainWrapper_2_auto_pwm_2_int_xing_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_16_auto_in_sync_1 = pwmClockDomainWrapper_2_auto_pwm_2_int_xing_out_sync_1; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_16_auto_in_sync_2 = pwmClockDomainWrapper_2_auto_pwm_2_int_xing_out_sync_2; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign intsink_16_auto_in_sync_3 = pwmClockDomainWrapper_2_auto_pwm_2_int_xing_out_sync_3; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign i2cClockDomainWrapper_auto_i2c_0_control_xing_in_a_valid =
    subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_a_valid; // @[LazyModule.scala 298:16]
  assign i2cClockDomainWrapper_auto_i2c_0_control_xing_in_a_bits_opcode =
    subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign i2cClockDomainWrapper_auto_i2c_0_control_xing_in_a_bits_param =
    subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign i2cClockDomainWrapper_auto_i2c_0_control_xing_in_a_bits_size =
    subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign i2cClockDomainWrapper_auto_i2c_0_control_xing_in_a_bits_source =
    subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign i2cClockDomainWrapper_auto_i2c_0_control_xing_in_a_bits_address =
    subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign i2cClockDomainWrapper_auto_i2c_0_control_xing_in_a_bits_mask =
    subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign i2cClockDomainWrapper_auto_i2c_0_control_xing_in_a_bits_data =
    subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign i2cClockDomainWrapper_auto_i2c_0_control_xing_in_a_bits_corrupt =
    subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign i2cClockDomainWrapper_auto_i2c_0_control_xing_in_d_ready =
    subsystem_pbus_auto_coupler_to_device_named_i2c_0_control_xing_out_d_ready; // @[LazyModule.scala 298:16]
  assign i2cClockDomainWrapper_auto_i2c_0_io_out_scl_in = i2c_0_scl_in; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign i2cClockDomainWrapper_auto_i2c_0_io_out_sda_in = i2c_0_sda_in; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign i2cClockDomainWrapper_auto_clock_in_clock = subsystem_pbus_auto_fixedClockNode_out_12_clock; // @[LazyModule.scala 298:16]
  assign i2cClockDomainWrapper_auto_clock_in_reset = subsystem_pbus_auto_fixedClockNode_out_12_reset; // @[LazyModule.scala 298:16]
  assign intsink_17_auto_in_sync_0 = i2cClockDomainWrapper_auto_i2c_0_int_xing_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_a_valid =
    subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_a_valid; // @[LazyModule.scala 298:16]
  assign i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_a_bits_opcode =
    subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_a_bits_param =
    subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_a_bits_size =
    subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_a_bits_source =
    subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_a_bits_address =
    subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_a_bits_mask =
    subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_a_bits_data =
    subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_data; // @[LazyModule.scala 298:16]
  assign i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_a_bits_corrupt =
    subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign i2cClockDomainWrapper_1_auto_i2c_1_control_xing_in_d_ready =
    subsystem_pbus_auto_coupler_to_device_named_i2c_1_control_xing_out_d_ready; // @[LazyModule.scala 298:16]
  assign i2cClockDomainWrapper_1_auto_i2c_1_io_out_scl_in = i2c_1_scl_in; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign i2cClockDomainWrapper_1_auto_i2c_1_io_out_sda_in = i2c_1_sda_in; // @[Nodes.scala 1210:84 BundleBridge.scala 54:8]
  assign i2cClockDomainWrapper_1_auto_clock_in_clock = subsystem_pbus_auto_fixedClockNode_out_13_clock; // @[LazyModule.scala 298:16]
  assign i2cClockDomainWrapper_1_auto_clock_in_reset = subsystem_pbus_auto_fixedClockNode_out_13_reset; // @[LazyModule.scala 298:16]
  assign intsink_18_auto_in_sync_0 = i2cClockDomainWrapper_1_auto_i2c_1_int_xing_out_sync_0; // @[Nodes.scala 1210:84 LazyModule.scala 296:16]
  assign bootROMDomainWrapper_auto_bootrom_in_a_valid = subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_valid; // @[LazyModule.scala 298:16]
  assign bootROMDomainWrapper_auto_bootrom_in_a_bits_opcode =
    subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 298:16]
  assign bootROMDomainWrapper_auto_bootrom_in_a_bits_param =
    subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_param; // @[LazyModule.scala 298:16]
  assign bootROMDomainWrapper_auto_bootrom_in_a_bits_size =
    subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_size; // @[LazyModule.scala 298:16]
  assign bootROMDomainWrapper_auto_bootrom_in_a_bits_source =
    subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_source; // @[LazyModule.scala 298:16]
  assign bootROMDomainWrapper_auto_bootrom_in_a_bits_address =
    subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_address; // @[LazyModule.scala 298:16]
  assign bootROMDomainWrapper_auto_bootrom_in_a_bits_mask =
    subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_mask; // @[LazyModule.scala 298:16]
  assign bootROMDomainWrapper_auto_bootrom_in_a_bits_corrupt =
    subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 298:16]
  assign bootROMDomainWrapper_auto_bootrom_in_d_ready = subsystem_cbus_auto_coupler_to_bootrom_fragmenter_out_d_ready; // @[LazyModule.scala 298:16]
  assign bootROMDomainWrapper_auto_clock_in_clock = subsystem_cbus_auto_fixedClockNode_out_2_clock; // @[LazyModule.scala 298:16]
  assign bootROMDomainWrapper_auto_clock_in_reset = subsystem_cbus_auto_fixedClockNode_out_2_reset; // @[LazyModule.scala 298:16]
  assign dtm_io_jtag_clock = debug_systemjtag_jtag_TCK; // @[Periphery.scala 166:24]
  assign dtm_io_jtag_reset = debug_systemjtag_reset; // @[Periphery.scala 167:24]
  assign dtm_io_dmi_req_ready = debug_1_io_dmi_dmi_req_ready; // @[Periphery.scala 174:40]
  assign dtm_io_dmi_resp_valid = debug_1_io_dmi_dmi_resp_valid; // @[Periphery.scala 174:40]
  assign dtm_io_dmi_resp_bits_data = debug_1_io_dmi_dmi_resp_bits_data; // @[Periphery.scala 174:40]
  assign dtm_io_dmi_resp_bits_resp = debug_1_io_dmi_dmi_resp_bits_resp; // @[Periphery.scala 174:40]
  assign dtm_io_jtag_TMS = debug_systemjtag_jtag_TMS; // @[Periphery.scala 162:17]
  assign dtm_io_jtag_TDI = debug_systemjtag_jtag_TDI; // @[Periphery.scala 162:17]
  assign rtc_sync_rtc_clock = clock;
  assign rtc_sync_rtc_io_d = aon_1_io_rtc; // @[MockAONPeriphery.scala 45:63]
  always @(posedge clock) begin
    if (reset) begin // @[MockAONPeriphery.scala 46:21]
      rtc_last <= 1'h0; // @[MockAONPeriphery.scala 46:21]
    end else begin
      rtc_last <= rtc_sync; // @[MockAONPeriphery.scala 46:21]
    end
    if (reset) begin // @[MockAONPeriphery.scala 47:21]
      rtc_tick <= 1'h0; // @[MockAONPeriphery.scala 47:21]
    end else begin
      rtc_tick <= rtc_tick_x2; // @[MockAONPeriphery.scala 47:21]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  rtc_last = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  rtc_tick = _RAND_1[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module AsyncResetSynchronizerPrimitiveShiftReg_d20_i0(
  input   clock,
  input   reset,
  output  io_q
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
`endif // RANDOMIZE_REG_INIT
  reg  sync_0; // @[SynchronizerReg.scala 51:87]
  reg  sync_1; // @[SynchronizerReg.scala 51:87]
  reg  sync_2; // @[SynchronizerReg.scala 51:87]
  reg  sync_3; // @[SynchronizerReg.scala 51:87]
  reg  sync_4; // @[SynchronizerReg.scala 51:87]
  reg  sync_5; // @[SynchronizerReg.scala 51:87]
  reg  sync_6; // @[SynchronizerReg.scala 51:87]
  reg  sync_7; // @[SynchronizerReg.scala 51:87]
  reg  sync_8; // @[SynchronizerReg.scala 51:87]
  reg  sync_9; // @[SynchronizerReg.scala 51:87]
  reg  sync_10; // @[SynchronizerReg.scala 51:87]
  reg  sync_11; // @[SynchronizerReg.scala 51:87]
  reg  sync_12; // @[SynchronizerReg.scala 51:87]
  reg  sync_13; // @[SynchronizerReg.scala 51:87]
  reg  sync_14; // @[SynchronizerReg.scala 51:87]
  reg  sync_15; // @[SynchronizerReg.scala 51:87]
  reg  sync_16; // @[SynchronizerReg.scala 51:87]
  reg  sync_17; // @[SynchronizerReg.scala 51:87]
  reg  sync_18; // @[SynchronizerReg.scala 51:87]
  reg  sync_19; // @[SynchronizerReg.scala 51:87]
  assign io_q = sync_0; // @[SynchronizerReg.scala 59:8]
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[SynchronizerReg.scala 51:87]
      sync_0 <= 1'h0; // @[SynchronizerReg.scala 51:87]
    end else begin
      sync_0 <= sync_1; // @[SynchronizerReg.scala 57:10]
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[SynchronizerReg.scala 51:87]
      sync_1 <= 1'h0; // @[SynchronizerReg.scala 51:87]
    end else begin
      sync_1 <= sync_2; // @[SynchronizerReg.scala 57:10]
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[SynchronizerReg.scala 51:87]
      sync_2 <= 1'h0; // @[SynchronizerReg.scala 51:87]
    end else begin
      sync_2 <= sync_3; // @[SynchronizerReg.scala 57:10]
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[SynchronizerReg.scala 51:87]
      sync_3 <= 1'h0; // @[SynchronizerReg.scala 51:87]
    end else begin
      sync_3 <= sync_4; // @[SynchronizerReg.scala 57:10]
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[SynchronizerReg.scala 51:87]
      sync_4 <= 1'h0; // @[SynchronizerReg.scala 51:87]
    end else begin
      sync_4 <= sync_5; // @[SynchronizerReg.scala 57:10]
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[SynchronizerReg.scala 51:87]
      sync_5 <= 1'h0; // @[SynchronizerReg.scala 51:87]
    end else begin
      sync_5 <= sync_6; // @[SynchronizerReg.scala 57:10]
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[SynchronizerReg.scala 51:87]
      sync_6 <= 1'h0; // @[SynchronizerReg.scala 51:87]
    end else begin
      sync_6 <= sync_7; // @[SynchronizerReg.scala 57:10]
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[SynchronizerReg.scala 51:87]
      sync_7 <= 1'h0; // @[SynchronizerReg.scala 51:87]
    end else begin
      sync_7 <= sync_8; // @[SynchronizerReg.scala 57:10]
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[SynchronizerReg.scala 51:87]
      sync_8 <= 1'h0; // @[SynchronizerReg.scala 51:87]
    end else begin
      sync_8 <= sync_9; // @[SynchronizerReg.scala 57:10]
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[SynchronizerReg.scala 51:87]
      sync_9 <= 1'h0; // @[SynchronizerReg.scala 51:87]
    end else begin
      sync_9 <= sync_10; // @[SynchronizerReg.scala 57:10]
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[SynchronizerReg.scala 51:87]
      sync_10 <= 1'h0; // @[SynchronizerReg.scala 51:87]
    end else begin
      sync_10 <= sync_11; // @[SynchronizerReg.scala 57:10]
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[SynchronizerReg.scala 51:87]
      sync_11 <= 1'h0; // @[SynchronizerReg.scala 51:87]
    end else begin
      sync_11 <= sync_12; // @[SynchronizerReg.scala 57:10]
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[SynchronizerReg.scala 51:87]
      sync_12 <= 1'h0; // @[SynchronizerReg.scala 51:87]
    end else begin
      sync_12 <= sync_13; // @[SynchronizerReg.scala 57:10]
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[SynchronizerReg.scala 51:87]
      sync_13 <= 1'h0; // @[SynchronizerReg.scala 51:87]
    end else begin
      sync_13 <= sync_14; // @[SynchronizerReg.scala 57:10]
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[SynchronizerReg.scala 51:87]
      sync_14 <= 1'h0; // @[SynchronizerReg.scala 51:87]
    end else begin
      sync_14 <= sync_15; // @[SynchronizerReg.scala 57:10]
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[SynchronizerReg.scala 51:87]
      sync_15 <= 1'h0; // @[SynchronizerReg.scala 51:87]
    end else begin
      sync_15 <= sync_16; // @[SynchronizerReg.scala 57:10]
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[SynchronizerReg.scala 51:87]
      sync_16 <= 1'h0; // @[SynchronizerReg.scala 51:87]
    end else begin
      sync_16 <= sync_17; // @[SynchronizerReg.scala 57:10]
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[SynchronizerReg.scala 51:87]
      sync_17 <= 1'h0; // @[SynchronizerReg.scala 51:87]
    end else begin
      sync_17 <= sync_18; // @[SynchronizerReg.scala 57:10]
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[SynchronizerReg.scala 51:87]
      sync_18 <= 1'h0; // @[SynchronizerReg.scala 51:87]
    end else begin
      sync_18 <= sync_19; // @[SynchronizerReg.scala 57:10]
    end
  end
  always @(posedge clock or posedge reset) begin
    if (reset) begin // @[SynchronizerReg.scala 54:22]
      sync_19 <= 1'h0;
    end else begin
      sync_19 <= 1'h1;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  sync_0 = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  sync_1 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  sync_2 = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  sync_3 = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  sync_4 = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  sync_5 = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  sync_6 = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  sync_7 = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  sync_8 = _RAND_8[0:0];
  _RAND_9 = {1{`RANDOM}};
  sync_9 = _RAND_9[0:0];
  _RAND_10 = {1{`RANDOM}};
  sync_10 = _RAND_10[0:0];
  _RAND_11 = {1{`RANDOM}};
  sync_11 = _RAND_11[0:0];
  _RAND_12 = {1{`RANDOM}};
  sync_12 = _RAND_12[0:0];
  _RAND_13 = {1{`RANDOM}};
  sync_13 = _RAND_13[0:0];
  _RAND_14 = {1{`RANDOM}};
  sync_14 = _RAND_14[0:0];
  _RAND_15 = {1{`RANDOM}};
  sync_15 = _RAND_15[0:0];
  _RAND_16 = {1{`RANDOM}};
  sync_16 = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  sync_17 = _RAND_17[0:0];
  _RAND_18 = {1{`RANDOM}};
  sync_18 = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  sync_19 = _RAND_19[0:0];
`endif // RANDOMIZE_REG_INIT
  if (reset) begin
    sync_0 = 1'h0;
  end
  if (reset) begin
    sync_1 = 1'h0;
  end
  if (reset) begin
    sync_2 = 1'h0;
  end
  if (reset) begin
    sync_3 = 1'h0;
  end
  if (reset) begin
    sync_4 = 1'h0;
  end
  if (reset) begin
    sync_5 = 1'h0;
  end
  if (reset) begin
    sync_6 = 1'h0;
  end
  if (reset) begin
    sync_7 = 1'h0;
  end
  if (reset) begin
    sync_8 = 1'h0;
  end
  if (reset) begin
    sync_9 = 1'h0;
  end
  if (reset) begin
    sync_10 = 1'h0;
  end
  if (reset) begin
    sync_11 = 1'h0;
  end
  if (reset) begin
    sync_12 = 1'h0;
  end
  if (reset) begin
    sync_13 = 1'h0;
  end
  if (reset) begin
    sync_14 = 1'h0;
  end
  if (reset) begin
    sync_15 = 1'h0;
  end
  if (reset) begin
    sync_16 = 1'h0;
  end
  if (reset) begin
    sync_17 = 1'h0;
  end
  if (reset) begin
    sync_18 = 1'h0;
  end
  if (reset) begin
    sync_19 = 1'h0;
  end
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module AsyncResetSynchronizerShiftReg_w1_d20_i0(
  input   clock,
  input   reset,
  output  io_q
);
  wire  output_chain_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_reset; // @[ShiftReg.scala 45:23]
  wire  output_chain_io_q; // @[ShiftReg.scala 45:23]
  AsyncResetSynchronizerPrimitiveShiftReg_d20_i0 output_chain ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_clock),
    .reset(output_chain_reset),
    .io_q(output_chain_io_q)
  );
  assign io_q = output_chain_io_q; // @[ShiftReg.scala 48:{24,24}]
  assign output_chain_clock = clock;
  assign output_chain_reset = reset; // @[SynchronizerReg.scala 86:21]
endmodule
module ResetCatchAndSync_d20(
  input   clock,
  input   reset,
  output  io_sync_reset
);
  wire  io_sync_reset_chain_clock; // @[ShiftReg.scala 45:23]
  wire  io_sync_reset_chain_reset; // @[ShiftReg.scala 45:23]
  wire  io_sync_reset_chain_io_q; // @[ShiftReg.scala 45:23]
  wire  _io_sync_reset_WIRE = io_sync_reset_chain_io_q; // @[ShiftReg.scala 48:{24,24}]
  AsyncResetSynchronizerShiftReg_w1_d20_i0 io_sync_reset_chain ( // @[ShiftReg.scala 45:23]
    .clock(io_sync_reset_chain_clock),
    .reset(io_sync_reset_chain_reset),
    .io_q(io_sync_reset_chain_io_q)
  );
  assign io_sync_reset = ~_io_sync_reset_WIRE; // @[ResetCatchAndSync.scala 29:7]
  assign io_sync_reset_chain_clock = clock;
  assign io_sync_reset_chain_reset = reset; // @[ResetCatchAndSync.scala 26:27]
endmodule
module SyncResetSynchronizerPrimitiveShiftReg_d3_i1(
  input   clock,
  input   reset,
  input   io_d,
  output  io_q
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
  reg  sync_0; // @[SynchronizerReg.scala 51:87]
  reg  sync_1; // @[SynchronizerReg.scala 51:87]
  reg  sync_2; // @[SynchronizerReg.scala 51:87]
  assign io_q = sync_0; // @[SynchronizerReg.scala 59:8]
  always @(posedge clock) begin
    sync_0 <= reset | sync_1; // @[SynchronizerReg.scala 51:{87,87} 57:10]
    sync_1 <= reset | sync_2; // @[SynchronizerReg.scala 51:{87,87} 57:10]
    sync_2 <= reset | io_d; // @[SynchronizerReg.scala 51:{87,87} 54:14]
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  sync_0 = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  sync_1 = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  sync_2 = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module SyncResetSynchronizerShiftReg_w1_d3_i1(
  input   clock,
  input   reset,
  input   io_d,
  output  io_q
);
  wire  output_chain_clock; // @[ShiftReg.scala 45:23]
  wire  output_chain_reset; // @[ShiftReg.scala 45:23]
  wire  output_chain_io_d; // @[ShiftReg.scala 45:23]
  wire  output_chain_io_q; // @[ShiftReg.scala 45:23]
  SyncResetSynchronizerPrimitiveShiftReg_d3_i1 output_chain ( // @[ShiftReg.scala 45:23]
    .clock(output_chain_clock),
    .reset(output_chain_reset),
    .io_d(output_chain_io_d),
    .io_q(output_chain_io_q)
  );
  assign io_q = output_chain_io_q; // @[ShiftReg.scala 48:{24,24}]
  assign output_chain_clock = clock;
  assign output_chain_reset = reset; // @[SynchronizerReg.scala 118:21]
  assign output_chain_io_d = io_d; // @[SynchronizerReg.scala 119:41]
endmodule
module MarmotCaravelPlatform(
  input   clock,
  input   io_pins_jtag_TCK_i_ival,
  input   io_pins_jtag_TMS_i_ival,
  input   io_pins_jtag_TDI_i_ival,
  output  io_pins_jtag_TDO_o_oval,
  output  io_pins_jtag_TDO_o_oe,
  input   io_pins_gpio_pins_0_i_ival,
  output  io_pins_gpio_pins_0_o_oval,
  output  io_pins_gpio_pins_0_o_oe,
  output  io_pins_gpio_pins_0_o_ie,
  input   io_pins_gpio_pins_1_i_ival,
  output  io_pins_gpio_pins_1_o_oval,
  output  io_pins_gpio_pins_1_o_oe,
  output  io_pins_gpio_pins_1_o_ie,
  input   io_pins_gpio_pins_2_i_ival,
  output  io_pins_gpio_pins_2_o_oval,
  output  io_pins_gpio_pins_2_o_oe,
  output  io_pins_gpio_pins_2_o_ie,
  input   io_pins_gpio_pins_3_i_ival,
  output  io_pins_gpio_pins_3_o_oval,
  output  io_pins_gpio_pins_3_o_oe,
  output  io_pins_gpio_pins_3_o_ie,
  input   io_pins_gpio_pins_4_i_ival,
  output  io_pins_gpio_pins_4_o_oval,
  output  io_pins_gpio_pins_4_o_oe,
  output  io_pins_gpio_pins_4_o_ie,
  input   io_pins_gpio_pins_5_i_ival,
  output  io_pins_gpio_pins_5_o_oval,
  output  io_pins_gpio_pins_5_o_oe,
  output  io_pins_gpio_pins_5_o_ie,
  input   io_pins_gpio_pins_6_i_ival,
  output  io_pins_gpio_pins_6_o_oval,
  output  io_pins_gpio_pins_6_o_oe,
  input   io_pins_gpio_pins_7_i_ival,
  output  io_pins_gpio_pins_7_o_oval,
  output  io_pins_gpio_pins_7_o_oe,
  input   io_pins_gpio_pins_8_i_ival,
  output  io_pins_gpio_pins_8_o_oval,
  output  io_pins_gpio_pins_8_o_oe,
  input   io_pins_gpio_pins_9_i_ival,
  output  io_pins_gpio_pins_9_o_oval,
  output  io_pins_gpio_pins_9_o_oe,
  input   io_pins_gpio_pins_10_i_ival,
  output  io_pins_gpio_pins_10_o_oval,
  output  io_pins_gpio_pins_10_o_oe,
  input   io_pins_gpio_pins_11_i_ival,
  output  io_pins_gpio_pins_11_o_oval,
  output  io_pins_gpio_pins_11_o_oe,
  input   io_pins_gpio_pins_12_i_ival,
  output  io_pins_gpio_pins_12_o_oval,
  output  io_pins_gpio_pins_12_o_oe,
  output  io_pins_gpio_pins_12_o_ie,
  input   io_pins_gpio_pins_13_i_ival,
  output  io_pins_gpio_pins_13_o_oval,
  output  io_pins_gpio_pins_13_o_oe,
  output  io_pins_gpio_pins_13_o_ie,
  input   io_pins_gpio_pins_14_i_ival,
  output  io_pins_gpio_pins_14_o_oval,
  output  io_pins_gpio_pins_14_o_oe,
  output  io_pins_gpio_pins_14_o_ie,
  input   io_pins_gpio_pins_15_i_ival,
  output  io_pins_gpio_pins_15_o_oval,
  output  io_pins_gpio_pins_15_o_oe,
  output  io_pins_gpio_pins_15_o_ie,
  input   io_pins_gpio_pins_16_i_ival,
  output  io_pins_gpio_pins_16_o_oval,
  output  io_pins_gpio_pins_16_o_oe,
  output  io_pins_gpio_pins_16_o_ie,
  input   io_pins_gpio_pins_17_i_ival,
  output  io_pins_gpio_pins_17_o_oval,
  output  io_pins_gpio_pins_17_o_oe,
  output  io_pins_gpio_pins_17_o_ie,
  input   io_pins_gpio_pins_18_i_ival,
  output  io_pins_gpio_pins_18_o_oval,
  output  io_pins_gpio_pins_18_o_oe,
  output  io_pins_gpio_pins_18_o_ie,
  input   io_pins_gpio_pins_19_i_ival,
  output  io_pins_gpio_pins_19_o_oval,
  output  io_pins_gpio_pins_19_o_oe,
  output  io_pins_gpio_pins_19_o_ie,
  input   io_pins_gpio_pins_20_i_ival,
  output  io_pins_gpio_pins_20_o_oval,
  output  io_pins_gpio_pins_20_o_oe,
  output  io_pins_gpio_pins_20_o_ie,
  input   io_pins_gpio_pins_21_i_ival,
  output  io_pins_gpio_pins_21_o_oval,
  output  io_pins_gpio_pins_21_o_oe,
  output  io_pins_gpio_pins_21_o_ie,
  input   io_pins_gpio_pins_22_i_ival,
  output  io_pins_gpio_pins_22_o_oval,
  output  io_pins_gpio_pins_22_o_oe,
  output  io_pins_gpio_pins_22_o_ie,
  input   io_pins_gpio_pins_23_i_ival,
  output  io_pins_gpio_pins_23_o_oval,
  output  io_pins_gpio_pins_23_o_oe,
  output  io_pins_gpio_pins_23_o_ie,
  input   io_pins_gpio_pins_24_i_ival,
  output  io_pins_gpio_pins_24_o_oval,
  output  io_pins_gpio_pins_24_o_oe,
  output  io_pins_gpio_pins_24_o_ie,
  input   io_pins_gpio_pins_25_i_ival,
  output  io_pins_gpio_pins_25_o_oval,
  output  io_pins_gpio_pins_25_o_oe,
  input   io_pins_gpio_pins_26_i_ival,
  output  io_pins_gpio_pins_26_o_oval,
  output  io_pins_gpio_pins_26_o_oe,
  input   io_pins_gpio_pins_27_i_ival,
  output  io_pins_gpio_pins_27_o_oval,
  output  io_pins_gpio_pins_27_o_oe,
  input   io_pins_gpio_pins_28_i_ival,
  output  io_pins_gpio_pins_28_o_oval,
  output  io_pins_gpio_pins_28_o_oe,
  input   io_pins_gpio_pins_29_i_ival,
  output  io_pins_gpio_pins_29_o_oval,
  output  io_pins_gpio_pins_29_o_oe,
  input   io_pins_gpio_pins_30_i_ival,
  output  io_pins_gpio_pins_30_o_oval,
  output  io_pins_gpio_pins_30_o_oe,
  input   io_pins_gpio_pins_31_i_ival,
  output  io_pins_gpio_pins_31_o_oval,
  output  io_pins_gpio_pins_31_o_oe,
  output  io_pins_qspi_sck_o_oval,
  input   io_pins_qspi_dq_0_i_ival,
  output  io_pins_qspi_dq_0_o_oval,
  output  io_pins_qspi_dq_0_o_oe,
  output  io_pins_qspi_dq_0_o_ie,
  input   io_pins_qspi_dq_1_i_ival,
  output  io_pins_qspi_dq_1_o_oval,
  output  io_pins_qspi_dq_1_o_oe,
  output  io_pins_qspi_dq_1_o_ie,
  input   io_pins_qspi_dq_2_i_ival,
  output  io_pins_qspi_dq_2_o_oval,
  output  io_pins_qspi_dq_2_o_oe,
  output  io_pins_qspi_dq_2_o_ie,
  input   io_pins_qspi_dq_3_i_ival,
  output  io_pins_qspi_dq_3_o_oval,
  output  io_pins_qspi_dq_3_o_oe,
  output  io_pins_qspi_dq_3_o_ie,
  output  io_pins_qspi_cs_0_o_oval,
  output  io_pins_qspi_ram_sck_o_oval,
  input   io_pins_qspi_ram_dq_0_i_ival,
  output  io_pins_qspi_ram_dq_0_o_oval,
  output  io_pins_qspi_ram_dq_0_o_oe,
  output  io_pins_qspi_ram_dq_0_o_ie,
  input   io_pins_qspi_ram_dq_1_i_ival,
  output  io_pins_qspi_ram_dq_1_o_oval,
  output  io_pins_qspi_ram_dq_1_o_oe,
  output  io_pins_qspi_ram_dq_1_o_ie,
  input   io_pins_qspi_ram_dq_2_i_ival,
  output  io_pins_qspi_ram_dq_2_o_oval,
  output  io_pins_qspi_ram_dq_2_o_oe,
  output  io_pins_qspi_ram_dq_2_o_ie,
  input   io_pins_qspi_ram_dq_3_i_ival,
  output  io_pins_qspi_ram_dq_3_o_oval,
  output  io_pins_qspi_ram_dq_3_o_oe,
  output  io_pins_qspi_ram_dq_3_o_ie,
  output  io_pins_qspi_ram_cs_0_o_oval,
  input   io_pins_uart_rxd_i_ival,
  output  io_pins_uart_txd_o_oval,
  input   io_pins_aon_erst_n_i_ival,
  input   io_pins_aon_lfextclk_i_ival,
  input   io_jtag_reset
);
  wire  sys_clock; // @[Platform.scala 58:19]
  wire  sys_reset; // @[Platform.scala 58:19]
  wire  sys_debug_clock; // @[Platform.scala 58:19]
  wire  sys_debug_systemjtag_jtag_TCK; // @[Platform.scala 58:19]
  wire  sys_debug_systemjtag_jtag_TMS; // @[Platform.scala 58:19]
  wire  sys_debug_systemjtag_jtag_TDI; // @[Platform.scala 58:19]
  wire  sys_debug_systemjtag_jtag_TDO_data; // @[Platform.scala 58:19]
  wire  sys_debug_systemjtag_jtag_TDO_driven; // @[Platform.scala 58:19]
  wire  sys_debug_systemjtag_reset; // @[Platform.scala 58:19]
  wire  sys_uart_0_txd; // @[Platform.scala 58:19]
  wire  sys_uart_0_rxd; // @[Platform.scala 58:19]
  wire  sys_uart_1_txd; // @[Platform.scala 58:19]
  wire  sys_uart_1_rxd; // @[Platform.scala 58:19]
  wire  sys_uart_2_txd; // @[Platform.scala 58:19]
  wire  sys_uart_2_rxd; // @[Platform.scala 58:19]
  wire  sys_uart_3_txd; // @[Platform.scala 58:19]
  wire  sys_uart_3_rxd; // @[Platform.scala 58:19]
  wire  sys_uart_4_txd; // @[Platform.scala 58:19]
  wire  sys_uart_4_rxd; // @[Platform.scala 58:19]
  wire  sys_spi_0_sck; // @[Platform.scala 58:19]
  wire  sys_spi_0_dq_0_i; // @[Platform.scala 58:19]
  wire  sys_spi_0_dq_0_o; // @[Platform.scala 58:19]
  wire  sys_spi_0_dq_0_oe; // @[Platform.scala 58:19]
  wire  sys_spi_0_dq_1_i; // @[Platform.scala 58:19]
  wire  sys_spi_0_dq_1_o; // @[Platform.scala 58:19]
  wire  sys_spi_0_dq_1_oe; // @[Platform.scala 58:19]
  wire  sys_spi_0_dq_2_i; // @[Platform.scala 58:19]
  wire  sys_spi_0_dq_2_o; // @[Platform.scala 58:19]
  wire  sys_spi_0_dq_2_oe; // @[Platform.scala 58:19]
  wire  sys_spi_0_dq_3_i; // @[Platform.scala 58:19]
  wire  sys_spi_0_dq_3_o; // @[Platform.scala 58:19]
  wire  sys_spi_0_dq_3_oe; // @[Platform.scala 58:19]
  wire  sys_spi_0_cs_0; // @[Platform.scala 58:19]
  wire  sys_spi_0_cs_1; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_0_i_ival; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_0_o_oval; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_0_o_oe; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_0_o_ie; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_1_i_ival; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_1_o_oval; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_1_o_oe; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_1_o_ie; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_2_i_ival; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_2_o_oval; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_2_o_oe; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_2_o_ie; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_3_i_ival; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_3_o_oval; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_3_o_oe; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_3_o_ie; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_4_i_ival; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_4_o_oval; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_4_o_oe; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_4_o_ie; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_5_i_ival; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_5_o_oval; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_5_o_oe; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_5_o_ie; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_6_i_ival; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_6_o_oval; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_6_o_oe; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_7_i_ival; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_7_o_oval; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_7_o_oe; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_8_i_ival; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_8_o_oval; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_8_o_oe; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_9_i_ival; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_9_o_oval; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_9_o_oe; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_10_i_ival; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_10_o_oval; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_10_o_oe; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_11_i_ival; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_11_o_oval; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_11_o_oe; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_12_i_ival; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_12_o_oval; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_12_o_oe; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_12_o_ie; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_13_i_ival; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_13_o_oval; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_13_o_oe; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_13_o_ie; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_14_i_ival; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_14_o_oval; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_14_o_oe; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_14_o_ie; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_15_i_ival; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_15_o_oval; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_15_o_oe; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_15_o_ie; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_16_i_ival; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_16_o_oval; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_16_o_oe; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_16_o_ie; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_17_i_ival; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_17_o_oval; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_17_o_oe; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_17_o_ie; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_18_i_ival; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_18_o_oval; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_18_o_oe; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_18_o_ie; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_19_i_ival; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_19_o_oval; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_19_o_oe; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_19_o_ie; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_20_i_ival; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_20_o_oval; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_20_o_oe; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_20_o_ie; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_21_i_ival; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_21_o_oval; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_21_o_oe; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_21_o_ie; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_22_i_ival; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_22_o_oval; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_22_o_oe; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_22_o_ie; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_23_i_ival; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_23_o_oval; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_23_o_oe; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_23_o_ie; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_24_i_ival; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_24_o_oval; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_24_o_oe; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_24_o_ie; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_25_i_ival; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_25_o_oval; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_25_o_oe; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_26_i_ival; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_26_o_oval; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_26_o_oe; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_27_i_ival; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_27_o_oval; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_27_o_oe; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_28_i_ival; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_28_o_oval; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_28_o_oe; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_29_i_ival; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_29_o_oval; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_29_o_oe; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_30_i_ival; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_30_o_oval; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_30_o_oe; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_31_i_ival; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_31_o_oval; // @[Platform.scala 58:19]
  wire  sys_gpio_0_pins_31_o_oe; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_0_0_o_oval; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_0_1_o_oval; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_0_2_i_ival; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_0_2_o_oval; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_0_2_o_oe; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_0_2_o_ie; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_0_3_i_ival; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_0_3_o_oval; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_0_3_o_oe; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_0_3_o_ie; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_0_4_i_ival; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_0_4_o_oval; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_0_4_o_oe; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_0_4_o_ie; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_0_5_i_ival; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_0_5_o_oval; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_0_5_o_oe; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_0_5_o_ie; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_0_12_i_ival; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_0_12_o_oe; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_0_13_i_ival; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_0_13_o_oe; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_0_14_i_ival; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_0_14_o_oe; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_0_15_i_ival; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_0_15_o_oe; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_0_16_i_ival; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_0_17_o_oval; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_0_18_i_ival; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_0_19_o_oval; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_0_20_i_ival; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_0_21_o_oval; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_0_22_i_ival; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_0_23_o_oval; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_0_24_o_oval; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_1_12_o_oval; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_1_13_o_oval; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_1_14_o_oval; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_1_15_o_oval; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_1_16_o_oval; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_1_17_o_oval; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_1_18_o_oval; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_1_19_o_oval; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_1_20_o_oval; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_1_21_o_oval; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_1_22_o_oval; // @[Platform.scala 58:19]
  wire  sys_iof_0_iof_1_23_o_oval; // @[Platform.scala 58:19]
  wire  sys_pwm_0_gpio_0; // @[Platform.scala 58:19]
  wire  sys_pwm_0_gpio_1; // @[Platform.scala 58:19]
  wire  sys_pwm_0_gpio_2; // @[Platform.scala 58:19]
  wire  sys_pwm_0_gpio_3; // @[Platform.scala 58:19]
  wire  sys_pwm_1_gpio_0; // @[Platform.scala 58:19]
  wire  sys_pwm_1_gpio_1; // @[Platform.scala 58:19]
  wire  sys_pwm_1_gpio_2; // @[Platform.scala 58:19]
  wire  sys_pwm_1_gpio_3; // @[Platform.scala 58:19]
  wire  sys_pwm_2_gpio_0; // @[Platform.scala 58:19]
  wire  sys_pwm_2_gpio_1; // @[Platform.scala 58:19]
  wire  sys_pwm_2_gpio_2; // @[Platform.scala 58:19]
  wire  sys_pwm_2_gpio_3; // @[Platform.scala 58:19]
  wire  sys_qspi_0_sck; // @[Platform.scala 58:19]
  wire  sys_qspi_0_dq_0_i; // @[Platform.scala 58:19]
  wire  sys_qspi_0_dq_0_o; // @[Platform.scala 58:19]
  wire  sys_qspi_0_dq_0_oe; // @[Platform.scala 58:19]
  wire  sys_qspi_0_dq_1_i; // @[Platform.scala 58:19]
  wire  sys_qspi_0_dq_1_o; // @[Platform.scala 58:19]
  wire  sys_qspi_0_dq_1_oe; // @[Platform.scala 58:19]
  wire  sys_qspi_0_dq_2_i; // @[Platform.scala 58:19]
  wire  sys_qspi_0_dq_2_o; // @[Platform.scala 58:19]
  wire  sys_qspi_0_dq_2_oe; // @[Platform.scala 58:19]
  wire  sys_qspi_0_dq_3_i; // @[Platform.scala 58:19]
  wire  sys_qspi_0_dq_3_o; // @[Platform.scala 58:19]
  wire  sys_qspi_0_dq_3_oe; // @[Platform.scala 58:19]
  wire  sys_qspi_0_cs_0; // @[Platform.scala 58:19]
  wire  sys_qspi_ram_0_sck; // @[Platform.scala 58:19]
  wire  sys_qspi_ram_0_dq_0_i; // @[Platform.scala 58:19]
  wire  sys_qspi_ram_0_dq_0_o; // @[Platform.scala 58:19]
  wire  sys_qspi_ram_0_dq_0_oe; // @[Platform.scala 58:19]
  wire  sys_qspi_ram_0_dq_1_i; // @[Platform.scala 58:19]
  wire  sys_qspi_ram_0_dq_1_o; // @[Platform.scala 58:19]
  wire  sys_qspi_ram_0_dq_1_oe; // @[Platform.scala 58:19]
  wire  sys_qspi_ram_0_dq_2_i; // @[Platform.scala 58:19]
  wire  sys_qspi_ram_0_dq_2_o; // @[Platform.scala 58:19]
  wire  sys_qspi_ram_0_dq_2_oe; // @[Platform.scala 58:19]
  wire  sys_qspi_ram_0_dq_3_i; // @[Platform.scala 58:19]
  wire  sys_qspi_ram_0_dq_3_o; // @[Platform.scala 58:19]
  wire  sys_qspi_ram_0_dq_3_oe; // @[Platform.scala 58:19]
  wire  sys_qspi_ram_0_cs_0; // @[Platform.scala 58:19]
  wire  sys_aon_pins_erst_n_i_ival; // @[Platform.scala 58:19]
  wire  sys_aon_pins_lfextclk_i_ival; // @[Platform.scala 58:19]
  wire  sys_aon_rsts_corerst; // @[Platform.scala 58:19]
  wire  sys_i2c_0_scl_in; // @[Platform.scala 58:19]
  wire  sys_i2c_0_scl_oe; // @[Platform.scala 58:19]
  wire  sys_i2c_0_sda_in; // @[Platform.scala 58:19]
  wire  sys_i2c_0_sda_oe; // @[Platform.scala 58:19]
  wire  sys_i2c_1_scl_in; // @[Platform.scala 58:19]
  wire  sys_i2c_1_scl_oe; // @[Platform.scala 58:19]
  wire  sys_i2c_1_sda_in; // @[Platform.scala 58:19]
  wire  sys_i2c_1_sda_oe; // @[Platform.scala 58:19]
  wire  sys_reset_catcher_clock; // @[ResetCatchAndSync.scala 39:28]
  wire  sys_reset_catcher_reset; // @[ResetCatchAndSync.scala 39:28]
  wire  sys_reset_catcher_io_sync_reset; // @[ResetCatchAndSync.scala 39:28]
  wire  sys_qspi_0_dq_0_i_spi_dq_0_sync_clock; // @[ShiftReg.scala 45:23]
  wire  sys_qspi_0_dq_0_i_spi_dq_0_sync_io_d; // @[ShiftReg.scala 45:23]
  wire  sys_qspi_0_dq_0_i_spi_dq_0_sync_io_q; // @[ShiftReg.scala 45:23]
  wire  sys_qspi_0_dq_1_i_spi_dq_1_sync_clock; // @[ShiftReg.scala 45:23]
  wire  sys_qspi_0_dq_1_i_spi_dq_1_sync_io_d; // @[ShiftReg.scala 45:23]
  wire  sys_qspi_0_dq_1_i_spi_dq_1_sync_io_q; // @[ShiftReg.scala 45:23]
  wire  sys_qspi_0_dq_2_i_spi_dq_2_sync_clock; // @[ShiftReg.scala 45:23]
  wire  sys_qspi_0_dq_2_i_spi_dq_2_sync_io_d; // @[ShiftReg.scala 45:23]
  wire  sys_qspi_0_dq_2_i_spi_dq_2_sync_io_q; // @[ShiftReg.scala 45:23]
  wire  sys_qspi_0_dq_3_i_spi_dq_3_sync_clock; // @[ShiftReg.scala 45:23]
  wire  sys_qspi_0_dq_3_i_spi_dq_3_sync_io_d; // @[ShiftReg.scala 45:23]
  wire  sys_qspi_0_dq_3_i_spi_dq_3_sync_io_q; // @[ShiftReg.scala 45:23]
  wire  sys_qspi_ram_0_dq_0_i_spi_dq_0_sync_clock; // @[ShiftReg.scala 45:23]
  wire  sys_qspi_ram_0_dq_0_i_spi_dq_0_sync_io_d; // @[ShiftReg.scala 45:23]
  wire  sys_qspi_ram_0_dq_0_i_spi_dq_0_sync_io_q; // @[ShiftReg.scala 45:23]
  wire  sys_qspi_ram_0_dq_1_i_spi_dq_1_sync_clock; // @[ShiftReg.scala 45:23]
  wire  sys_qspi_ram_0_dq_1_i_spi_dq_1_sync_io_d; // @[ShiftReg.scala 45:23]
  wire  sys_qspi_ram_0_dq_1_i_spi_dq_1_sync_io_q; // @[ShiftReg.scala 45:23]
  wire  sys_qspi_ram_0_dq_2_i_spi_dq_2_sync_clock; // @[ShiftReg.scala 45:23]
  wire  sys_qspi_ram_0_dq_2_i_spi_dq_2_sync_io_d; // @[ShiftReg.scala 45:23]
  wire  sys_qspi_ram_0_dq_2_i_spi_dq_2_sync_io_q; // @[ShiftReg.scala 45:23]
  wire  sys_qspi_ram_0_dq_3_i_spi_dq_3_sync_clock; // @[ShiftReg.scala 45:23]
  wire  sys_qspi_ram_0_dq_3_i_spi_dq_3_sync_io_d; // @[ShiftReg.scala 45:23]
  wire  sys_qspi_ram_0_dq_3_i_spi_dq_3_sync_io_q; // @[ShiftReg.scala 45:23]
  wire  sys_uart_0_rxd_uart_rxd_sync_clock; // @[ShiftReg.scala 45:23]
  wire  sys_uart_0_rxd_uart_rxd_sync_reset; // @[ShiftReg.scala 45:23]
  wire  sys_uart_0_rxd_uart_rxd_sync_io_d; // @[ShiftReg.scala 45:23]
  wire  sys_uart_0_rxd_uart_rxd_sync_io_q; // @[ShiftReg.scala 45:23]
  MarmotCaravelSystem sys ( // @[Platform.scala 58:19]
    .clock(sys_clock),
    .reset(sys_reset),
    .debug_clock(sys_debug_clock),
    .debug_systemjtag_jtag_TCK(sys_debug_systemjtag_jtag_TCK),
    .debug_systemjtag_jtag_TMS(sys_debug_systemjtag_jtag_TMS),
    .debug_systemjtag_jtag_TDI(sys_debug_systemjtag_jtag_TDI),
    .debug_systemjtag_jtag_TDO_data(sys_debug_systemjtag_jtag_TDO_data),
    .debug_systemjtag_jtag_TDO_driven(sys_debug_systemjtag_jtag_TDO_driven),
    .debug_systemjtag_reset(sys_debug_systemjtag_reset),
    .uart_0_txd(sys_uart_0_txd),
    .uart_0_rxd(sys_uart_0_rxd),
    .uart_1_txd(sys_uart_1_txd),
    .uart_1_rxd(sys_uart_1_rxd),
    .uart_2_txd(sys_uart_2_txd),
    .uart_2_rxd(sys_uart_2_rxd),
    .uart_3_txd(sys_uart_3_txd),
    .uart_3_rxd(sys_uart_3_rxd),
    .uart_4_txd(sys_uart_4_txd),
    .uart_4_rxd(sys_uart_4_rxd),
    .spi_0_sck(sys_spi_0_sck),
    .spi_0_dq_0_i(sys_spi_0_dq_0_i),
    .spi_0_dq_0_o(sys_spi_0_dq_0_o),
    .spi_0_dq_0_oe(sys_spi_0_dq_0_oe),
    .spi_0_dq_1_i(sys_spi_0_dq_1_i),
    .spi_0_dq_1_o(sys_spi_0_dq_1_o),
    .spi_0_dq_1_oe(sys_spi_0_dq_1_oe),
    .spi_0_dq_2_i(sys_spi_0_dq_2_i),
    .spi_0_dq_2_o(sys_spi_0_dq_2_o),
    .spi_0_dq_2_oe(sys_spi_0_dq_2_oe),
    .spi_0_dq_3_i(sys_spi_0_dq_3_i),
    .spi_0_dq_3_o(sys_spi_0_dq_3_o),
    .spi_0_dq_3_oe(sys_spi_0_dq_3_oe),
    .spi_0_cs_0(sys_spi_0_cs_0),
    .spi_0_cs_1(sys_spi_0_cs_1),
    .gpio_0_pins_0_i_ival(sys_gpio_0_pins_0_i_ival),
    .gpio_0_pins_0_o_oval(sys_gpio_0_pins_0_o_oval),
    .gpio_0_pins_0_o_oe(sys_gpio_0_pins_0_o_oe),
    .gpio_0_pins_0_o_ie(sys_gpio_0_pins_0_o_ie),
    .gpio_0_pins_1_i_ival(sys_gpio_0_pins_1_i_ival),
    .gpio_0_pins_1_o_oval(sys_gpio_0_pins_1_o_oval),
    .gpio_0_pins_1_o_oe(sys_gpio_0_pins_1_o_oe),
    .gpio_0_pins_1_o_ie(sys_gpio_0_pins_1_o_ie),
    .gpio_0_pins_2_i_ival(sys_gpio_0_pins_2_i_ival),
    .gpio_0_pins_2_o_oval(sys_gpio_0_pins_2_o_oval),
    .gpio_0_pins_2_o_oe(sys_gpio_0_pins_2_o_oe),
    .gpio_0_pins_2_o_ie(sys_gpio_0_pins_2_o_ie),
    .gpio_0_pins_3_i_ival(sys_gpio_0_pins_3_i_ival),
    .gpio_0_pins_3_o_oval(sys_gpio_0_pins_3_o_oval),
    .gpio_0_pins_3_o_oe(sys_gpio_0_pins_3_o_oe),
    .gpio_0_pins_3_o_ie(sys_gpio_0_pins_3_o_ie),
    .gpio_0_pins_4_i_ival(sys_gpio_0_pins_4_i_ival),
    .gpio_0_pins_4_o_oval(sys_gpio_0_pins_4_o_oval),
    .gpio_0_pins_4_o_oe(sys_gpio_0_pins_4_o_oe),
    .gpio_0_pins_4_o_ie(sys_gpio_0_pins_4_o_ie),
    .gpio_0_pins_5_i_ival(sys_gpio_0_pins_5_i_ival),
    .gpio_0_pins_5_o_oval(sys_gpio_0_pins_5_o_oval),
    .gpio_0_pins_5_o_oe(sys_gpio_0_pins_5_o_oe),
    .gpio_0_pins_5_o_ie(sys_gpio_0_pins_5_o_ie),
    .gpio_0_pins_6_i_ival(sys_gpio_0_pins_6_i_ival),
    .gpio_0_pins_6_o_oval(sys_gpio_0_pins_6_o_oval),
    .gpio_0_pins_6_o_oe(sys_gpio_0_pins_6_o_oe),
    .gpio_0_pins_7_i_ival(sys_gpio_0_pins_7_i_ival),
    .gpio_0_pins_7_o_oval(sys_gpio_0_pins_7_o_oval),
    .gpio_0_pins_7_o_oe(sys_gpio_0_pins_7_o_oe),
    .gpio_0_pins_8_i_ival(sys_gpio_0_pins_8_i_ival),
    .gpio_0_pins_8_o_oval(sys_gpio_0_pins_8_o_oval),
    .gpio_0_pins_8_o_oe(sys_gpio_0_pins_8_o_oe),
    .gpio_0_pins_9_i_ival(sys_gpio_0_pins_9_i_ival),
    .gpio_0_pins_9_o_oval(sys_gpio_0_pins_9_o_oval),
    .gpio_0_pins_9_o_oe(sys_gpio_0_pins_9_o_oe),
    .gpio_0_pins_10_i_ival(sys_gpio_0_pins_10_i_ival),
    .gpio_0_pins_10_o_oval(sys_gpio_0_pins_10_o_oval),
    .gpio_0_pins_10_o_oe(sys_gpio_0_pins_10_o_oe),
    .gpio_0_pins_11_i_ival(sys_gpio_0_pins_11_i_ival),
    .gpio_0_pins_11_o_oval(sys_gpio_0_pins_11_o_oval),
    .gpio_0_pins_11_o_oe(sys_gpio_0_pins_11_o_oe),
    .gpio_0_pins_12_i_ival(sys_gpio_0_pins_12_i_ival),
    .gpio_0_pins_12_o_oval(sys_gpio_0_pins_12_o_oval),
    .gpio_0_pins_12_o_oe(sys_gpio_0_pins_12_o_oe),
    .gpio_0_pins_12_o_ie(sys_gpio_0_pins_12_o_ie),
    .gpio_0_pins_13_i_ival(sys_gpio_0_pins_13_i_ival),
    .gpio_0_pins_13_o_oval(sys_gpio_0_pins_13_o_oval),
    .gpio_0_pins_13_o_oe(sys_gpio_0_pins_13_o_oe),
    .gpio_0_pins_13_o_ie(sys_gpio_0_pins_13_o_ie),
    .gpio_0_pins_14_i_ival(sys_gpio_0_pins_14_i_ival),
    .gpio_0_pins_14_o_oval(sys_gpio_0_pins_14_o_oval),
    .gpio_0_pins_14_o_oe(sys_gpio_0_pins_14_o_oe),
    .gpio_0_pins_14_o_ie(sys_gpio_0_pins_14_o_ie),
    .gpio_0_pins_15_i_ival(sys_gpio_0_pins_15_i_ival),
    .gpio_0_pins_15_o_oval(sys_gpio_0_pins_15_o_oval),
    .gpio_0_pins_15_o_oe(sys_gpio_0_pins_15_o_oe),
    .gpio_0_pins_15_o_ie(sys_gpio_0_pins_15_o_ie),
    .gpio_0_pins_16_i_ival(sys_gpio_0_pins_16_i_ival),
    .gpio_0_pins_16_o_oval(sys_gpio_0_pins_16_o_oval),
    .gpio_0_pins_16_o_oe(sys_gpio_0_pins_16_o_oe),
    .gpio_0_pins_16_o_ie(sys_gpio_0_pins_16_o_ie),
    .gpio_0_pins_17_i_ival(sys_gpio_0_pins_17_i_ival),
    .gpio_0_pins_17_o_oval(sys_gpio_0_pins_17_o_oval),
    .gpio_0_pins_17_o_oe(sys_gpio_0_pins_17_o_oe),
    .gpio_0_pins_17_o_ie(sys_gpio_0_pins_17_o_ie),
    .gpio_0_pins_18_i_ival(sys_gpio_0_pins_18_i_ival),
    .gpio_0_pins_18_o_oval(sys_gpio_0_pins_18_o_oval),
    .gpio_0_pins_18_o_oe(sys_gpio_0_pins_18_o_oe),
    .gpio_0_pins_18_o_ie(sys_gpio_0_pins_18_o_ie),
    .gpio_0_pins_19_i_ival(sys_gpio_0_pins_19_i_ival),
    .gpio_0_pins_19_o_oval(sys_gpio_0_pins_19_o_oval),
    .gpio_0_pins_19_o_oe(sys_gpio_0_pins_19_o_oe),
    .gpio_0_pins_19_o_ie(sys_gpio_0_pins_19_o_ie),
    .gpio_0_pins_20_i_ival(sys_gpio_0_pins_20_i_ival),
    .gpio_0_pins_20_o_oval(sys_gpio_0_pins_20_o_oval),
    .gpio_0_pins_20_o_oe(sys_gpio_0_pins_20_o_oe),
    .gpio_0_pins_20_o_ie(sys_gpio_0_pins_20_o_ie),
    .gpio_0_pins_21_i_ival(sys_gpio_0_pins_21_i_ival),
    .gpio_0_pins_21_o_oval(sys_gpio_0_pins_21_o_oval),
    .gpio_0_pins_21_o_oe(sys_gpio_0_pins_21_o_oe),
    .gpio_0_pins_21_o_ie(sys_gpio_0_pins_21_o_ie),
    .gpio_0_pins_22_i_ival(sys_gpio_0_pins_22_i_ival),
    .gpio_0_pins_22_o_oval(sys_gpio_0_pins_22_o_oval),
    .gpio_0_pins_22_o_oe(sys_gpio_0_pins_22_o_oe),
    .gpio_0_pins_22_o_ie(sys_gpio_0_pins_22_o_ie),
    .gpio_0_pins_23_i_ival(sys_gpio_0_pins_23_i_ival),
    .gpio_0_pins_23_o_oval(sys_gpio_0_pins_23_o_oval),
    .gpio_0_pins_23_o_oe(sys_gpio_0_pins_23_o_oe),
    .gpio_0_pins_23_o_ie(sys_gpio_0_pins_23_o_ie),
    .gpio_0_pins_24_i_ival(sys_gpio_0_pins_24_i_ival),
    .gpio_0_pins_24_o_oval(sys_gpio_0_pins_24_o_oval),
    .gpio_0_pins_24_o_oe(sys_gpio_0_pins_24_o_oe),
    .gpio_0_pins_24_o_ie(sys_gpio_0_pins_24_o_ie),
    .gpio_0_pins_25_i_ival(sys_gpio_0_pins_25_i_ival),
    .gpio_0_pins_25_o_oval(sys_gpio_0_pins_25_o_oval),
    .gpio_0_pins_25_o_oe(sys_gpio_0_pins_25_o_oe),
    .gpio_0_pins_26_i_ival(sys_gpio_0_pins_26_i_ival),
    .gpio_0_pins_26_o_oval(sys_gpio_0_pins_26_o_oval),
    .gpio_0_pins_26_o_oe(sys_gpio_0_pins_26_o_oe),
    .gpio_0_pins_27_i_ival(sys_gpio_0_pins_27_i_ival),
    .gpio_0_pins_27_o_oval(sys_gpio_0_pins_27_o_oval),
    .gpio_0_pins_27_o_oe(sys_gpio_0_pins_27_o_oe),
    .gpio_0_pins_28_i_ival(sys_gpio_0_pins_28_i_ival),
    .gpio_0_pins_28_o_oval(sys_gpio_0_pins_28_o_oval),
    .gpio_0_pins_28_o_oe(sys_gpio_0_pins_28_o_oe),
    .gpio_0_pins_29_i_ival(sys_gpio_0_pins_29_i_ival),
    .gpio_0_pins_29_o_oval(sys_gpio_0_pins_29_o_oval),
    .gpio_0_pins_29_o_oe(sys_gpio_0_pins_29_o_oe),
    .gpio_0_pins_30_i_ival(sys_gpio_0_pins_30_i_ival),
    .gpio_0_pins_30_o_oval(sys_gpio_0_pins_30_o_oval),
    .gpio_0_pins_30_o_oe(sys_gpio_0_pins_30_o_oe),
    .gpio_0_pins_31_i_ival(sys_gpio_0_pins_31_i_ival),
    .gpio_0_pins_31_o_oval(sys_gpio_0_pins_31_o_oval),
    .gpio_0_pins_31_o_oe(sys_gpio_0_pins_31_o_oe),
    .iof_0_iof_0_0_o_oval(sys_iof_0_iof_0_0_o_oval),
    .iof_0_iof_0_1_o_oval(sys_iof_0_iof_0_1_o_oval),
    .iof_0_iof_0_2_i_ival(sys_iof_0_iof_0_2_i_ival),
    .iof_0_iof_0_2_o_oval(sys_iof_0_iof_0_2_o_oval),
    .iof_0_iof_0_2_o_oe(sys_iof_0_iof_0_2_o_oe),
    .iof_0_iof_0_2_o_ie(sys_iof_0_iof_0_2_o_ie),
    .iof_0_iof_0_3_i_ival(sys_iof_0_iof_0_3_i_ival),
    .iof_0_iof_0_3_o_oval(sys_iof_0_iof_0_3_o_oval),
    .iof_0_iof_0_3_o_oe(sys_iof_0_iof_0_3_o_oe),
    .iof_0_iof_0_3_o_ie(sys_iof_0_iof_0_3_o_ie),
    .iof_0_iof_0_4_i_ival(sys_iof_0_iof_0_4_i_ival),
    .iof_0_iof_0_4_o_oval(sys_iof_0_iof_0_4_o_oval),
    .iof_0_iof_0_4_o_oe(sys_iof_0_iof_0_4_o_oe),
    .iof_0_iof_0_4_o_ie(sys_iof_0_iof_0_4_o_ie),
    .iof_0_iof_0_5_i_ival(sys_iof_0_iof_0_5_i_ival),
    .iof_0_iof_0_5_o_oval(sys_iof_0_iof_0_5_o_oval),
    .iof_0_iof_0_5_o_oe(sys_iof_0_iof_0_5_o_oe),
    .iof_0_iof_0_5_o_ie(sys_iof_0_iof_0_5_o_ie),
    .iof_0_iof_0_12_i_ival(sys_iof_0_iof_0_12_i_ival),
    .iof_0_iof_0_12_o_oe(sys_iof_0_iof_0_12_o_oe),
    .iof_0_iof_0_13_i_ival(sys_iof_0_iof_0_13_i_ival),
    .iof_0_iof_0_13_o_oe(sys_iof_0_iof_0_13_o_oe),
    .iof_0_iof_0_14_i_ival(sys_iof_0_iof_0_14_i_ival),
    .iof_0_iof_0_14_o_oe(sys_iof_0_iof_0_14_o_oe),
    .iof_0_iof_0_15_i_ival(sys_iof_0_iof_0_15_i_ival),
    .iof_0_iof_0_15_o_oe(sys_iof_0_iof_0_15_o_oe),
    .iof_0_iof_0_16_i_ival(sys_iof_0_iof_0_16_i_ival),
    .iof_0_iof_0_17_o_oval(sys_iof_0_iof_0_17_o_oval),
    .iof_0_iof_0_18_i_ival(sys_iof_0_iof_0_18_i_ival),
    .iof_0_iof_0_19_o_oval(sys_iof_0_iof_0_19_o_oval),
    .iof_0_iof_0_20_i_ival(sys_iof_0_iof_0_20_i_ival),
    .iof_0_iof_0_21_o_oval(sys_iof_0_iof_0_21_o_oval),
    .iof_0_iof_0_22_i_ival(sys_iof_0_iof_0_22_i_ival),
    .iof_0_iof_0_23_o_oval(sys_iof_0_iof_0_23_o_oval),
    .iof_0_iof_0_24_o_oval(sys_iof_0_iof_0_24_o_oval),
    .iof_0_iof_1_12_o_oval(sys_iof_0_iof_1_12_o_oval),
    .iof_0_iof_1_13_o_oval(sys_iof_0_iof_1_13_o_oval),
    .iof_0_iof_1_14_o_oval(sys_iof_0_iof_1_14_o_oval),
    .iof_0_iof_1_15_o_oval(sys_iof_0_iof_1_15_o_oval),
    .iof_0_iof_1_16_o_oval(sys_iof_0_iof_1_16_o_oval),
    .iof_0_iof_1_17_o_oval(sys_iof_0_iof_1_17_o_oval),
    .iof_0_iof_1_18_o_oval(sys_iof_0_iof_1_18_o_oval),
    .iof_0_iof_1_19_o_oval(sys_iof_0_iof_1_19_o_oval),
    .iof_0_iof_1_20_o_oval(sys_iof_0_iof_1_20_o_oval),
    .iof_0_iof_1_21_o_oval(sys_iof_0_iof_1_21_o_oval),
    .iof_0_iof_1_22_o_oval(sys_iof_0_iof_1_22_o_oval),
    .iof_0_iof_1_23_o_oval(sys_iof_0_iof_1_23_o_oval),
    .pwm_0_gpio_0(sys_pwm_0_gpio_0),
    .pwm_0_gpio_1(sys_pwm_0_gpio_1),
    .pwm_0_gpio_2(sys_pwm_0_gpio_2),
    .pwm_0_gpio_3(sys_pwm_0_gpio_3),
    .pwm_1_gpio_0(sys_pwm_1_gpio_0),
    .pwm_1_gpio_1(sys_pwm_1_gpio_1),
    .pwm_1_gpio_2(sys_pwm_1_gpio_2),
    .pwm_1_gpio_3(sys_pwm_1_gpio_3),
    .pwm_2_gpio_0(sys_pwm_2_gpio_0),
    .pwm_2_gpio_1(sys_pwm_2_gpio_1),
    .pwm_2_gpio_2(sys_pwm_2_gpio_2),
    .pwm_2_gpio_3(sys_pwm_2_gpio_3),
    .qspi_0_sck(sys_qspi_0_sck),
    .qspi_0_dq_0_i(sys_qspi_0_dq_0_i),
    .qspi_0_dq_0_o(sys_qspi_0_dq_0_o),
    .qspi_0_dq_0_oe(sys_qspi_0_dq_0_oe),
    .qspi_0_dq_1_i(sys_qspi_0_dq_1_i),
    .qspi_0_dq_1_o(sys_qspi_0_dq_1_o),
    .qspi_0_dq_1_oe(sys_qspi_0_dq_1_oe),
    .qspi_0_dq_2_i(sys_qspi_0_dq_2_i),
    .qspi_0_dq_2_o(sys_qspi_0_dq_2_o),
    .qspi_0_dq_2_oe(sys_qspi_0_dq_2_oe),
    .qspi_0_dq_3_i(sys_qspi_0_dq_3_i),
    .qspi_0_dq_3_o(sys_qspi_0_dq_3_o),
    .qspi_0_dq_3_oe(sys_qspi_0_dq_3_oe),
    .qspi_0_cs_0(sys_qspi_0_cs_0),
    .qspi_ram_0_sck(sys_qspi_ram_0_sck),
    .qspi_ram_0_dq_0_i(sys_qspi_ram_0_dq_0_i),
    .qspi_ram_0_dq_0_o(sys_qspi_ram_0_dq_0_o),
    .qspi_ram_0_dq_0_oe(sys_qspi_ram_0_dq_0_oe),
    .qspi_ram_0_dq_1_i(sys_qspi_ram_0_dq_1_i),
    .qspi_ram_0_dq_1_o(sys_qspi_ram_0_dq_1_o),
    .qspi_ram_0_dq_1_oe(sys_qspi_ram_0_dq_1_oe),
    .qspi_ram_0_dq_2_i(sys_qspi_ram_0_dq_2_i),
    .qspi_ram_0_dq_2_o(sys_qspi_ram_0_dq_2_o),
    .qspi_ram_0_dq_2_oe(sys_qspi_ram_0_dq_2_oe),
    .qspi_ram_0_dq_3_i(sys_qspi_ram_0_dq_3_i),
    .qspi_ram_0_dq_3_o(sys_qspi_ram_0_dq_3_o),
    .qspi_ram_0_dq_3_oe(sys_qspi_ram_0_dq_3_oe),
    .qspi_ram_0_cs_0(sys_qspi_ram_0_cs_0),
    .aon_pins_erst_n_i_ival(sys_aon_pins_erst_n_i_ival),
    .aon_pins_lfextclk_i_ival(sys_aon_pins_lfextclk_i_ival),
    .aon_rsts_corerst(sys_aon_rsts_corerst),
    .i2c_0_scl_in(sys_i2c_0_scl_in),
    .i2c_0_scl_oe(sys_i2c_0_scl_oe),
    .i2c_0_sda_in(sys_i2c_0_sda_in),
    .i2c_0_sda_oe(sys_i2c_0_sda_oe),
    .i2c_1_scl_in(sys_i2c_1_scl_in),
    .i2c_1_scl_oe(sys_i2c_1_scl_oe),
    .i2c_1_sda_in(sys_i2c_1_sda_in),
    .i2c_1_sda_oe(sys_i2c_1_sda_oe)
  );
  ResetCatchAndSync_d20 sys_reset_catcher ( // @[ResetCatchAndSync.scala 39:28]
    .clock(sys_reset_catcher_clock),
    .reset(sys_reset_catcher_reset),
    .io_sync_reset(sys_reset_catcher_io_sync_reset)
  );
  SynchronizerShiftReg_w1_d3 sys_qspi_0_dq_0_i_spi_dq_0_sync ( // @[ShiftReg.scala 45:23]
    .clock(sys_qspi_0_dq_0_i_spi_dq_0_sync_clock),
    .io_d(sys_qspi_0_dq_0_i_spi_dq_0_sync_io_d),
    .io_q(sys_qspi_0_dq_0_i_spi_dq_0_sync_io_q)
  );
  SynchronizerShiftReg_w1_d3 sys_qspi_0_dq_1_i_spi_dq_1_sync ( // @[ShiftReg.scala 45:23]
    .clock(sys_qspi_0_dq_1_i_spi_dq_1_sync_clock),
    .io_d(sys_qspi_0_dq_1_i_spi_dq_1_sync_io_d),
    .io_q(sys_qspi_0_dq_1_i_spi_dq_1_sync_io_q)
  );
  SynchronizerShiftReg_w1_d3 sys_qspi_0_dq_2_i_spi_dq_2_sync ( // @[ShiftReg.scala 45:23]
    .clock(sys_qspi_0_dq_2_i_spi_dq_2_sync_clock),
    .io_d(sys_qspi_0_dq_2_i_spi_dq_2_sync_io_d),
    .io_q(sys_qspi_0_dq_2_i_spi_dq_2_sync_io_q)
  );
  SynchronizerShiftReg_w1_d3 sys_qspi_0_dq_3_i_spi_dq_3_sync ( // @[ShiftReg.scala 45:23]
    .clock(sys_qspi_0_dq_3_i_spi_dq_3_sync_clock),
    .io_d(sys_qspi_0_dq_3_i_spi_dq_3_sync_io_d),
    .io_q(sys_qspi_0_dq_3_i_spi_dq_3_sync_io_q)
  );
  SynchronizerShiftReg_w1_d3 sys_qspi_ram_0_dq_0_i_spi_dq_0_sync ( // @[ShiftReg.scala 45:23]
    .clock(sys_qspi_ram_0_dq_0_i_spi_dq_0_sync_clock),
    .io_d(sys_qspi_ram_0_dq_0_i_spi_dq_0_sync_io_d),
    .io_q(sys_qspi_ram_0_dq_0_i_spi_dq_0_sync_io_q)
  );
  SynchronizerShiftReg_w1_d3 sys_qspi_ram_0_dq_1_i_spi_dq_1_sync ( // @[ShiftReg.scala 45:23]
    .clock(sys_qspi_ram_0_dq_1_i_spi_dq_1_sync_clock),
    .io_d(sys_qspi_ram_0_dq_1_i_spi_dq_1_sync_io_d),
    .io_q(sys_qspi_ram_0_dq_1_i_spi_dq_1_sync_io_q)
  );
  SynchronizerShiftReg_w1_d3 sys_qspi_ram_0_dq_2_i_spi_dq_2_sync ( // @[ShiftReg.scala 45:23]
    .clock(sys_qspi_ram_0_dq_2_i_spi_dq_2_sync_clock),
    .io_d(sys_qspi_ram_0_dq_2_i_spi_dq_2_sync_io_d),
    .io_q(sys_qspi_ram_0_dq_2_i_spi_dq_2_sync_io_q)
  );
  SynchronizerShiftReg_w1_d3 sys_qspi_ram_0_dq_3_i_spi_dq_3_sync ( // @[ShiftReg.scala 45:23]
    .clock(sys_qspi_ram_0_dq_3_i_spi_dq_3_sync_clock),
    .io_d(sys_qspi_ram_0_dq_3_i_spi_dq_3_sync_io_d),
    .io_q(sys_qspi_ram_0_dq_3_i_spi_dq_3_sync_io_q)
  );
  SyncResetSynchronizerShiftReg_w1_d3_i1 sys_uart_0_rxd_uart_rxd_sync ( // @[ShiftReg.scala 45:23]
    .clock(sys_uart_0_rxd_uart_rxd_sync_clock),
    .reset(sys_uart_0_rxd_uart_rxd_sync_reset),
    .io_d(sys_uart_0_rxd_uart_rxd_sync_io_d),
    .io_q(sys_uart_0_rxd_uart_rxd_sync_io_q)
  );
  assign io_pins_jtag_TDO_o_oval = sys_debug_systemjtag_jtag_TDO_data; // @[PinCtrl.scala 60:17]
  assign io_pins_jtag_TDO_o_oe = sys_debug_systemjtag_jtag_TDO_driven; // @[JTAGPins.scala 35:19]
  assign io_pins_gpio_pins_0_o_oval = sys_gpio_0_pins_0_o_oval; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_0_o_oe = sys_gpio_0_pins_0_o_oe; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_0_o_ie = sys_gpio_0_pins_0_o_ie; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_1_o_oval = sys_gpio_0_pins_1_o_oval; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_1_o_oe = sys_gpio_0_pins_1_o_oe; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_1_o_ie = sys_gpio_0_pins_1_o_ie; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_2_o_oval = sys_gpio_0_pins_2_o_oval; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_2_o_oe = sys_gpio_0_pins_2_o_oe; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_2_o_ie = sys_gpio_0_pins_2_o_ie; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_3_o_oval = sys_gpio_0_pins_3_o_oval; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_3_o_oe = sys_gpio_0_pins_3_o_oe; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_3_o_ie = sys_gpio_0_pins_3_o_ie; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_4_o_oval = sys_gpio_0_pins_4_o_oval; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_4_o_oe = sys_gpio_0_pins_4_o_oe; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_4_o_ie = sys_gpio_0_pins_4_o_ie; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_5_o_oval = sys_gpio_0_pins_5_o_oval; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_5_o_oe = sys_gpio_0_pins_5_o_oe; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_5_o_ie = sys_gpio_0_pins_5_o_ie; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_6_o_oval = sys_gpio_0_pins_6_o_oval; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_6_o_oe = sys_gpio_0_pins_6_o_oe; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_7_o_oval = sys_gpio_0_pins_7_o_oval; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_7_o_oe = sys_gpio_0_pins_7_o_oe; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_8_o_oval = sys_gpio_0_pins_8_o_oval; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_8_o_oe = sys_gpio_0_pins_8_o_oe; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_9_o_oval = sys_gpio_0_pins_9_o_oval; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_9_o_oe = sys_gpio_0_pins_9_o_oe; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_10_o_oval = sys_gpio_0_pins_10_o_oval; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_10_o_oe = sys_gpio_0_pins_10_o_oe; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_11_o_oval = sys_gpio_0_pins_11_o_oval; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_11_o_oe = sys_gpio_0_pins_11_o_oe; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_12_o_oval = sys_gpio_0_pins_12_o_oval; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_12_o_oe = sys_gpio_0_pins_12_o_oe; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_12_o_ie = sys_gpio_0_pins_12_o_ie; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_13_o_oval = sys_gpio_0_pins_13_o_oval; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_13_o_oe = sys_gpio_0_pins_13_o_oe; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_13_o_ie = sys_gpio_0_pins_13_o_ie; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_14_o_oval = sys_gpio_0_pins_14_o_oval; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_14_o_oe = sys_gpio_0_pins_14_o_oe; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_14_o_ie = sys_gpio_0_pins_14_o_ie; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_15_o_oval = sys_gpio_0_pins_15_o_oval; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_15_o_oe = sys_gpio_0_pins_15_o_oe; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_15_o_ie = sys_gpio_0_pins_15_o_ie; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_16_o_oval = sys_gpio_0_pins_16_o_oval; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_16_o_oe = sys_gpio_0_pins_16_o_oe; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_16_o_ie = sys_gpio_0_pins_16_o_ie; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_17_o_oval = sys_gpio_0_pins_17_o_oval; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_17_o_oe = sys_gpio_0_pins_17_o_oe; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_17_o_ie = sys_gpio_0_pins_17_o_ie; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_18_o_oval = sys_gpio_0_pins_18_o_oval; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_18_o_oe = sys_gpio_0_pins_18_o_oe; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_18_o_ie = sys_gpio_0_pins_18_o_ie; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_19_o_oval = sys_gpio_0_pins_19_o_oval; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_19_o_oe = sys_gpio_0_pins_19_o_oe; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_19_o_ie = sys_gpio_0_pins_19_o_ie; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_20_o_oval = sys_gpio_0_pins_20_o_oval; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_20_o_oe = sys_gpio_0_pins_20_o_oe; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_20_o_ie = sys_gpio_0_pins_20_o_ie; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_21_o_oval = sys_gpio_0_pins_21_o_oval; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_21_o_oe = sys_gpio_0_pins_21_o_oe; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_21_o_ie = sys_gpio_0_pins_21_o_ie; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_22_o_oval = sys_gpio_0_pins_22_o_oval; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_22_o_oe = sys_gpio_0_pins_22_o_oe; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_22_o_ie = sys_gpio_0_pins_22_o_ie; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_23_o_oval = sys_gpio_0_pins_23_o_oval; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_23_o_oe = sys_gpio_0_pins_23_o_oe; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_23_o_ie = sys_gpio_0_pins_23_o_ie; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_24_o_oval = sys_gpio_0_pins_24_o_oval; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_24_o_oe = sys_gpio_0_pins_24_o_oe; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_24_o_ie = sys_gpio_0_pins_24_o_ie; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_25_o_oval = sys_gpio_0_pins_25_o_oval; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_25_o_oe = sys_gpio_0_pins_25_o_oe; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_26_o_oval = sys_gpio_0_pins_26_o_oval; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_26_o_oe = sys_gpio_0_pins_26_o_oe; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_27_o_oval = sys_gpio_0_pins_27_o_oval; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_27_o_oe = sys_gpio_0_pins_27_o_oe; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_28_o_oval = sys_gpio_0_pins_28_o_oval; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_28_o_oe = sys_gpio_0_pins_28_o_oe; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_29_o_oval = sys_gpio_0_pins_29_o_oval; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_29_o_oe = sys_gpio_0_pins_29_o_oe; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_30_o_oval = sys_gpio_0_pins_30_o_oval; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_30_o_oe = sys_gpio_0_pins_30_o_oe; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_31_o_oval = sys_gpio_0_pins_31_o_oval; // @[GPIOPins.scala 38:11]
  assign io_pins_gpio_pins_31_o_oe = sys_gpio_0_pins_31_o_oe; // @[GPIOPins.scala 38:11]
  assign io_pins_qspi_sck_o_oval = sys_qspi_0_sck; // @[PinCtrl.scala 60:17]
  assign io_pins_qspi_dq_0_o_oval = sys_qspi_0_dq_0_o; // @[PinCtrl.scala 60:17]
  assign io_pins_qspi_dq_0_o_oe = sys_qspi_0_dq_0_oe; // @[SPIPins.scala 29:16]
  assign io_pins_qspi_dq_0_o_ie = ~sys_qspi_0_dq_0_oe; // @[SPIPins.scala 30:19]
  assign io_pins_qspi_dq_1_o_oval = sys_qspi_0_dq_1_o; // @[PinCtrl.scala 60:17]
  assign io_pins_qspi_dq_1_o_oe = sys_qspi_0_dq_1_oe; // @[SPIPins.scala 29:16]
  assign io_pins_qspi_dq_1_o_ie = ~sys_qspi_0_dq_1_oe; // @[SPIPins.scala 30:19]
  assign io_pins_qspi_dq_2_o_oval = sys_qspi_0_dq_2_o; // @[PinCtrl.scala 60:17]
  assign io_pins_qspi_dq_2_o_oe = sys_qspi_0_dq_2_oe; // @[SPIPins.scala 29:16]
  assign io_pins_qspi_dq_2_o_ie = ~sys_qspi_0_dq_2_oe; // @[SPIPins.scala 30:19]
  assign io_pins_qspi_dq_3_o_oval = sys_qspi_0_dq_3_o; // @[PinCtrl.scala 60:17]
  assign io_pins_qspi_dq_3_o_oe = sys_qspi_0_dq_3_oe; // @[SPIPins.scala 29:16]
  assign io_pins_qspi_dq_3_o_ie = ~sys_qspi_0_dq_3_oe; // @[SPIPins.scala 30:19]
  assign io_pins_qspi_cs_0_o_oval = sys_qspi_0_cs_0; // @[PinCtrl.scala 60:17]
  assign io_pins_qspi_ram_sck_o_oval = sys_qspi_ram_0_sck; // @[PinCtrl.scala 60:17]
  assign io_pins_qspi_ram_dq_0_o_oval = sys_qspi_ram_0_dq_0_o; // @[PinCtrl.scala 60:17]
  assign io_pins_qspi_ram_dq_0_o_oe = sys_qspi_ram_0_dq_0_oe; // @[SPIPins.scala 29:16]
  assign io_pins_qspi_ram_dq_0_o_ie = ~sys_qspi_ram_0_dq_0_oe; // @[SPIPins.scala 30:19]
  assign io_pins_qspi_ram_dq_1_o_oval = sys_qspi_ram_0_dq_1_o; // @[PinCtrl.scala 60:17]
  assign io_pins_qspi_ram_dq_1_o_oe = sys_qspi_ram_0_dq_1_oe; // @[SPIPins.scala 29:16]
  assign io_pins_qspi_ram_dq_1_o_ie = ~sys_qspi_ram_0_dq_1_oe; // @[SPIPins.scala 30:19]
  assign io_pins_qspi_ram_dq_2_o_oval = sys_qspi_ram_0_dq_2_o; // @[PinCtrl.scala 60:17]
  assign io_pins_qspi_ram_dq_2_o_oe = sys_qspi_ram_0_dq_2_oe; // @[SPIPins.scala 29:16]
  assign io_pins_qspi_ram_dq_2_o_ie = ~sys_qspi_ram_0_dq_2_oe; // @[SPIPins.scala 30:19]
  assign io_pins_qspi_ram_dq_3_o_oval = sys_qspi_ram_0_dq_3_o; // @[PinCtrl.scala 60:17]
  assign io_pins_qspi_ram_dq_3_o_oe = sys_qspi_ram_0_dq_3_oe; // @[SPIPins.scala 29:16]
  assign io_pins_qspi_ram_dq_3_o_ie = ~sys_qspi_ram_0_dq_3_oe; // @[SPIPins.scala 30:19]
  assign io_pins_qspi_ram_cs_0_o_oval = sys_qspi_ram_0_cs_0; // @[PinCtrl.scala 60:17]
  assign io_pins_uart_txd_o_oval = sys_uart_0_txd; // @[PinCtrl.scala 60:17]
  assign sys_clock = clock;
  assign sys_reset = sys_reset_catcher_io_sync_reset; // @[Platform.scala 64:13]
  assign sys_debug_clock = sys_clock; // @[Platform.scala 189:23]
  assign sys_debug_systemjtag_jtag_TCK = io_pins_jtag_TCK_i_ival; // @[JTAGPins.scala 29:55]
  assign sys_debug_systemjtag_jtag_TMS = io_pins_jtag_TMS_i_ival; // @[JTAGPins.scala 30:15]
  assign sys_debug_systemjtag_jtag_TDI = io_pins_jtag_TDI_i_ival; // @[JTAGPins.scala 31:15]
  assign sys_debug_systemjtag_reset = io_jtag_reset; // @[Platform.scala 184:15]
  assign sys_uart_0_rxd = sys_uart_0_rxd_uart_rxd_sync_io_q; // @[ShiftReg.scala 48:{24,24}]
  assign sys_uart_1_rxd = sys_iof_0_iof_0_16_i_ival; // @[Platform.scala 84:54 IOF.scala 61:9]
  assign sys_uart_2_rxd = sys_iof_0_iof_0_18_i_ival; // @[Platform.scala 84:54 IOF.scala 61:9]
  assign sys_uart_3_rxd = sys_iof_0_iof_0_20_i_ival; // @[Platform.scala 84:54 IOF.scala 61:9]
  assign sys_uart_4_rxd = sys_iof_0_iof_0_22_i_ival; // @[Platform.scala 84:54 IOF.scala 61:9]
  assign sys_spi_0_dq_0_i = sys_iof_0_iof_0_2_i_ival; // @[Platform.scala 86:54 IOF.scala 61:9]
  assign sys_spi_0_dq_1_i = sys_iof_0_iof_0_3_i_ival; // @[Platform.scala 86:54 IOF.scala 61:9]
  assign sys_spi_0_dq_2_i = sys_iof_0_iof_0_4_i_ival; // @[Platform.scala 86:54 IOF.scala 61:9]
  assign sys_spi_0_dq_3_i = sys_iof_0_iof_0_5_i_ival; // @[Platform.scala 86:54 IOF.scala 61:9]
  assign sys_gpio_0_pins_0_i_ival = io_pins_gpio_pins_0_i_ival; // @[GPIOPins.scala 38:11]
  assign sys_gpio_0_pins_1_i_ival = io_pins_gpio_pins_1_i_ival; // @[GPIOPins.scala 38:11]
  assign sys_gpio_0_pins_2_i_ival = io_pins_gpio_pins_2_i_ival; // @[GPIOPins.scala 38:11]
  assign sys_gpio_0_pins_3_i_ival = io_pins_gpio_pins_3_i_ival; // @[GPIOPins.scala 38:11]
  assign sys_gpio_0_pins_4_i_ival = io_pins_gpio_pins_4_i_ival; // @[GPIOPins.scala 38:11]
  assign sys_gpio_0_pins_5_i_ival = io_pins_gpio_pins_5_i_ival; // @[GPIOPins.scala 38:11]
  assign sys_gpio_0_pins_6_i_ival = io_pins_gpio_pins_6_i_ival; // @[GPIOPins.scala 38:11]
  assign sys_gpio_0_pins_7_i_ival = io_pins_gpio_pins_7_i_ival; // @[GPIOPins.scala 38:11]
  assign sys_gpio_0_pins_8_i_ival = io_pins_gpio_pins_8_i_ival; // @[GPIOPins.scala 38:11]
  assign sys_gpio_0_pins_9_i_ival = io_pins_gpio_pins_9_i_ival; // @[GPIOPins.scala 38:11]
  assign sys_gpio_0_pins_10_i_ival = io_pins_gpio_pins_10_i_ival; // @[GPIOPins.scala 38:11]
  assign sys_gpio_0_pins_11_i_ival = io_pins_gpio_pins_11_i_ival; // @[GPIOPins.scala 38:11]
  assign sys_gpio_0_pins_12_i_ival = io_pins_gpio_pins_12_i_ival; // @[GPIOPins.scala 38:11]
  assign sys_gpio_0_pins_13_i_ival = io_pins_gpio_pins_13_i_ival; // @[GPIOPins.scala 38:11]
  assign sys_gpio_0_pins_14_i_ival = io_pins_gpio_pins_14_i_ival; // @[GPIOPins.scala 38:11]
  assign sys_gpio_0_pins_15_i_ival = io_pins_gpio_pins_15_i_ival; // @[GPIOPins.scala 38:11]
  assign sys_gpio_0_pins_16_i_ival = io_pins_gpio_pins_16_i_ival; // @[GPIOPins.scala 38:11]
  assign sys_gpio_0_pins_17_i_ival = io_pins_gpio_pins_17_i_ival; // @[GPIOPins.scala 38:11]
  assign sys_gpio_0_pins_18_i_ival = io_pins_gpio_pins_18_i_ival; // @[GPIOPins.scala 38:11]
  assign sys_gpio_0_pins_19_i_ival = io_pins_gpio_pins_19_i_ival; // @[GPIOPins.scala 38:11]
  assign sys_gpio_0_pins_20_i_ival = io_pins_gpio_pins_20_i_ival; // @[GPIOPins.scala 38:11]
  assign sys_gpio_0_pins_21_i_ival = io_pins_gpio_pins_21_i_ival; // @[GPIOPins.scala 38:11]
  assign sys_gpio_0_pins_22_i_ival = io_pins_gpio_pins_22_i_ival; // @[GPIOPins.scala 38:11]
  assign sys_gpio_0_pins_23_i_ival = io_pins_gpio_pins_23_i_ival; // @[GPIOPins.scala 38:11]
  assign sys_gpio_0_pins_24_i_ival = io_pins_gpio_pins_24_i_ival; // @[GPIOPins.scala 38:11]
  assign sys_gpio_0_pins_25_i_ival = io_pins_gpio_pins_25_i_ival; // @[GPIOPins.scala 38:11]
  assign sys_gpio_0_pins_26_i_ival = io_pins_gpio_pins_26_i_ival; // @[GPIOPins.scala 38:11]
  assign sys_gpio_0_pins_27_i_ival = io_pins_gpio_pins_27_i_ival; // @[GPIOPins.scala 38:11]
  assign sys_gpio_0_pins_28_i_ival = io_pins_gpio_pins_28_i_ival; // @[GPIOPins.scala 38:11]
  assign sys_gpio_0_pins_29_i_ival = io_pins_gpio_pins_29_i_ival; // @[GPIOPins.scala 38:11]
  assign sys_gpio_0_pins_30_i_ival = io_pins_gpio_pins_30_i_ival; // @[GPIOPins.scala 38:11]
  assign sys_gpio_0_pins_31_i_ival = io_pins_gpio_pins_31_i_ival; // @[GPIOPins.scala 38:11]
  assign sys_iof_0_iof_0_0_o_oval = sys_spi_0_cs_0; // @[PinCtrl.scala 60:17 Platform.scala 86:54]
  assign sys_iof_0_iof_0_1_o_oval = sys_spi_0_sck; // @[PinCtrl.scala 60:17 Platform.scala 86:54]
  assign sys_iof_0_iof_0_2_o_oval = sys_spi_0_dq_0_o; // @[PinCtrl.scala 60:17 Platform.scala 86:54]
  assign sys_iof_0_iof_0_2_o_oe = sys_spi_0_dq_0_oe; // @[Platform.scala 86:54 SPIPins.scala 29:16]
  assign sys_iof_0_iof_0_2_o_ie = ~sys_spi_0_dq_0_oe; // @[SPIPins.scala 30:19]
  assign sys_iof_0_iof_0_3_o_oval = sys_spi_0_dq_1_o; // @[PinCtrl.scala 60:17 Platform.scala 86:54]
  assign sys_iof_0_iof_0_3_o_oe = sys_spi_0_dq_1_oe; // @[Platform.scala 86:54 SPIPins.scala 29:16]
  assign sys_iof_0_iof_0_3_o_ie = ~sys_spi_0_dq_1_oe; // @[SPIPins.scala 30:19]
  assign sys_iof_0_iof_0_4_o_oval = sys_spi_0_dq_2_o; // @[PinCtrl.scala 60:17 Platform.scala 86:54]
  assign sys_iof_0_iof_0_4_o_oe = sys_spi_0_dq_2_oe; // @[Platform.scala 86:54 SPIPins.scala 29:16]
  assign sys_iof_0_iof_0_4_o_ie = ~sys_spi_0_dq_2_oe; // @[SPIPins.scala 30:19]
  assign sys_iof_0_iof_0_5_o_oval = sys_spi_0_dq_3_o; // @[PinCtrl.scala 60:17 Platform.scala 86:54]
  assign sys_iof_0_iof_0_5_o_oe = sys_spi_0_dq_3_oe; // @[Platform.scala 86:54 SPIPins.scala 29:16]
  assign sys_iof_0_iof_0_5_o_ie = ~sys_spi_0_dq_3_oe; // @[SPIPins.scala 30:19]
  assign sys_iof_0_iof_0_12_o_oe = sys_i2c_0_sda_oe; // @[I2CPins.scala 27:21 Platform.scala 87:54]
  assign sys_iof_0_iof_0_13_o_oe = sys_i2c_0_scl_oe; // @[I2CPins.scala 22:21 Platform.scala 87:54]
  assign sys_iof_0_iof_0_14_o_oe = sys_i2c_1_sda_oe; // @[I2CPins.scala 27:21 Platform.scala 87:54]
  assign sys_iof_0_iof_0_15_o_oe = sys_i2c_1_scl_oe; // @[I2CPins.scala 22:21 Platform.scala 87:54]
  assign sys_iof_0_iof_0_17_o_oval = sys_uart_1_txd; // @[PinCtrl.scala 60:17 Platform.scala 84:54]
  assign sys_iof_0_iof_0_19_o_oval = sys_uart_2_txd; // @[PinCtrl.scala 60:17 Platform.scala 84:54]
  assign sys_iof_0_iof_0_21_o_oval = sys_uart_3_txd; // @[PinCtrl.scala 60:17 Platform.scala 84:54]
  assign sys_iof_0_iof_0_23_o_oval = sys_uart_4_txd; // @[PinCtrl.scala 60:17 Platform.scala 84:54]
  assign sys_iof_0_iof_0_24_o_oval = sys_spi_0_cs_1; // @[PinCtrl.scala 60:17 Platform.scala 86:54]
  assign sys_iof_0_iof_1_12_o_oval = sys_pwm_0_gpio_0; // @[PinCtrl.scala 60:17 Platform.scala 85:54]
  assign sys_iof_0_iof_1_13_o_oval = sys_pwm_0_gpio_1; // @[PinCtrl.scala 60:17 Platform.scala 85:54]
  assign sys_iof_0_iof_1_14_o_oval = sys_pwm_0_gpio_2; // @[PinCtrl.scala 60:17 Platform.scala 85:54]
  assign sys_iof_0_iof_1_15_o_oval = sys_pwm_0_gpio_3; // @[PinCtrl.scala 60:17 Platform.scala 85:54]
  assign sys_iof_0_iof_1_16_o_oval = sys_pwm_1_gpio_0; // @[PinCtrl.scala 60:17 Platform.scala 85:54]
  assign sys_iof_0_iof_1_17_o_oval = sys_pwm_1_gpio_1; // @[PinCtrl.scala 60:17 Platform.scala 85:54]
  assign sys_iof_0_iof_1_18_o_oval = sys_pwm_1_gpio_2; // @[PinCtrl.scala 60:17 Platform.scala 85:54]
  assign sys_iof_0_iof_1_19_o_oval = sys_pwm_1_gpio_3; // @[PinCtrl.scala 60:17 Platform.scala 85:54]
  assign sys_iof_0_iof_1_20_o_oval = sys_pwm_2_gpio_0; // @[PinCtrl.scala 60:17 Platform.scala 85:54]
  assign sys_iof_0_iof_1_21_o_oval = sys_pwm_2_gpio_1; // @[PinCtrl.scala 60:17 Platform.scala 85:54]
  assign sys_iof_0_iof_1_22_o_oval = sys_pwm_2_gpio_2; // @[PinCtrl.scala 60:17 Platform.scala 85:54]
  assign sys_iof_0_iof_1_23_o_oval = sys_pwm_2_gpio_3; // @[PinCtrl.scala 60:17 Platform.scala 85:54]
  assign sys_qspi_0_dq_0_i = sys_qspi_0_dq_0_i_spi_dq_0_sync_io_q; // @[ShiftReg.scala 48:{24,24}]
  assign sys_qspi_0_dq_1_i = sys_qspi_0_dq_1_i_spi_dq_1_sync_io_q; // @[ShiftReg.scala 48:{24,24}]
  assign sys_qspi_0_dq_2_i = sys_qspi_0_dq_2_i_spi_dq_2_sync_io_q; // @[ShiftReg.scala 48:{24,24}]
  assign sys_qspi_0_dq_3_i = sys_qspi_0_dq_3_i_spi_dq_3_sync_io_q; // @[ShiftReg.scala 48:{24,24}]
  assign sys_qspi_ram_0_dq_0_i = sys_qspi_ram_0_dq_0_i_spi_dq_0_sync_io_q; // @[ShiftReg.scala 48:{24,24}]
  assign sys_qspi_ram_0_dq_1_i = sys_qspi_ram_0_dq_1_i_spi_dq_1_sync_io_q; // @[ShiftReg.scala 48:{24,24}]
  assign sys_qspi_ram_0_dq_2_i = sys_qspi_ram_0_dq_2_i_spi_dq_2_sync_io_q; // @[ShiftReg.scala 48:{24,24}]
  assign sys_qspi_ram_0_dq_3_i = sys_qspi_ram_0_dq_3_i_spi_dq_3_sync_io_q; // @[ShiftReg.scala 48:{24,24}]
  assign sys_aon_pins_erst_n_i_ival = io_pins_aon_erst_n_i_ival; // @[Platform.scala 194:15]
  assign sys_aon_pins_lfextclk_i_ival = io_pins_aon_lfextclk_i_ival; // @[Platform.scala 194:15]
  assign sys_i2c_0_scl_in = sys_iof_0_iof_0_13_i_ival; // @[Platform.scala 87:54 IOF.scala 61:9]
  assign sys_i2c_0_sda_in = sys_iof_0_iof_0_12_i_ival; // @[Platform.scala 87:54 IOF.scala 61:9]
  assign sys_i2c_1_scl_in = sys_iof_0_iof_0_15_i_ival; // @[Platform.scala 87:54 IOF.scala 61:9]
  assign sys_i2c_1_sda_in = sys_iof_0_iof_0_14_i_ival; // @[Platform.scala 87:54 IOF.scala 61:9]
  assign sys_reset_catcher_clock = clock;
  assign sys_reset_catcher_reset = sys_aon_rsts_corerst;
  assign sys_qspi_0_dq_0_i_spi_dq_0_sync_clock = sys_clock;
  assign sys_qspi_0_dq_0_i_spi_dq_0_sync_io_d = io_pins_qspi_dq_0_i_ival; // @[ShiftReg.scala 47:16]
  assign sys_qspi_0_dq_1_i_spi_dq_1_sync_clock = sys_clock;
  assign sys_qspi_0_dq_1_i_spi_dq_1_sync_io_d = io_pins_qspi_dq_1_i_ival; // @[ShiftReg.scala 47:16]
  assign sys_qspi_0_dq_2_i_spi_dq_2_sync_clock = sys_clock;
  assign sys_qspi_0_dq_2_i_spi_dq_2_sync_io_d = io_pins_qspi_dq_2_i_ival; // @[ShiftReg.scala 47:16]
  assign sys_qspi_0_dq_3_i_spi_dq_3_sync_clock = sys_clock;
  assign sys_qspi_0_dq_3_i_spi_dq_3_sync_io_d = io_pins_qspi_dq_3_i_ival; // @[ShiftReg.scala 47:16]
  assign sys_qspi_ram_0_dq_0_i_spi_dq_0_sync_clock = sys_clock;
  assign sys_qspi_ram_0_dq_0_i_spi_dq_0_sync_io_d = io_pins_qspi_ram_dq_0_i_ival; // @[ShiftReg.scala 47:16]
  assign sys_qspi_ram_0_dq_1_i_spi_dq_1_sync_clock = sys_clock;
  assign sys_qspi_ram_0_dq_1_i_spi_dq_1_sync_io_d = io_pins_qspi_ram_dq_1_i_ival; // @[ShiftReg.scala 47:16]
  assign sys_qspi_ram_0_dq_2_i_spi_dq_2_sync_clock = sys_clock;
  assign sys_qspi_ram_0_dq_2_i_spi_dq_2_sync_io_d = io_pins_qspi_ram_dq_2_i_ival; // @[ShiftReg.scala 47:16]
  assign sys_qspi_ram_0_dq_3_i_spi_dq_3_sync_clock = sys_clock;
  assign sys_qspi_ram_0_dq_3_i_spi_dq_3_sync_io_d = io_pins_qspi_ram_dq_3_i_ival; // @[ShiftReg.scala 47:16]
  assign sys_uart_0_rxd_uart_rxd_sync_clock = sys_clock;
  assign sys_uart_0_rxd_uart_rxd_sync_reset = sys_reset; // @[compatibility.scala 290:56]
  assign sys_uart_0_rxd_uart_rxd_sync_io_d = io_pins_uart_rxd_i_ival; // @[ShiftReg.scala 47:16]
endmodule
module MarmotCaravelChip(
  input   clk,
  input   rst_n,
  input   io_in_0,
  input   io_in_1,
  input   io_in_2,
  input   io_in_3,
  input   io_in_4,
  input   io_in_5,
  input   io_in_6,
  input   io_in_7,
  input   io_in_8,
  input   io_in_9,
  input   io_in_10,
  input   io_in_11,
  input   io_in_12,
  input   io_in_13,
  input   io_in_14,
  input   io_in_15,
  input   io_in_16,
  input   io_in_17,
  input   io_in_18,
  input   io_in_19,
  input   io_in_20,
  input   io_in_21,
  input   io_in_22,
  input   io_in_23,
  input   io_in_24,
  input   io_in_25,
  input   io_in_26,
  input   io_in_27,
  input   io_in_28,
  input   io_in_29,
  input   io_in_30,
  input   io_in_31,
  input   io_in_32,
  input   io_in_33,
  input   io_in_34,
  input   io_in_35,
  input   io_in_36,
  input   io_in_37,
  output  io_out_0,
  output  io_out_1,
  output  io_out_2,
  output  io_out_3,
  output  io_out_4,
  output  io_out_5,
  output  io_out_6,
  output  io_out_7,
  output  io_out_8,
  output  io_out_9,
  output  io_out_10,
  output  io_out_11,
  output  io_out_12,
  output  io_out_13,
  output  io_out_14,
  output  io_out_15,
  output  io_out_16,
  output  io_out_17,
  output  io_out_18,
  output  io_out_19,
  output  io_out_20,
  output  io_out_21,
  output  io_out_22,
  output  io_out_23,
  output  io_out_24,
  output  io_out_25,
  output  io_out_26,
  output  io_out_27,
  output  io_out_28,
  output  io_out_29,
  output  io_out_30,
  output  io_out_31,
  output  io_out_32,
  output  io_out_33,
  output  io_out_34,
  output  io_out_35,
  output  io_out_36,
  output  io_out_37,
  output  io_oeb_0,
  output  io_oeb_1,
  output  io_oeb_2,
  output  io_oeb_3,
  output  io_oeb_4,
  output  io_oeb_5,
  output  io_oeb_6,
  output  io_oeb_7,
  output  io_oeb_8,
  output  io_oeb_9,
  output  io_oeb_10,
  output  io_oeb_11,
  output  io_oeb_12,
  output  io_oeb_13,
  output  io_oeb_14,
  output  io_oeb_15,
  output  io_oeb_16,
  output  io_oeb_17,
  output  io_oeb_18,
  output  io_oeb_19,
  output  io_oeb_20,
  output  io_oeb_21,
  output  io_oeb_22,
  output  io_oeb_23,
  output  io_oeb_24,
  output  io_oeb_25,
  output  io_oeb_26,
  output  io_oeb_27,
  output  io_oeb_28,
  output  io_oeb_29,
  output  io_oeb_30,
  output  io_oeb_31,
  output  io_oeb_32,
  output  io_oeb_33,
  output  io_oeb_34,
  output  io_oeb_35,
  output  io_oeb_36,
  output  io_oeb_37,
  output  gpio_out_0,
  output  gpio_out_1,
  output  gpio_out_2,
  output  gpio_out_3,
  output  gpio_out_4,
  output  gpio_out_5,
  output  gpio_out_6,
  output  gpio_out_7,
  output  gpio_out_8,
  output  gpio_out_9,
  output  gpio_out_10,
  output  gpio_out_11,
  output  gpio_out_12,
  output  gpio_out_13,
  output  gpio_out_14,
  output  gpio_out_15,
  output  gpio_out_16,
  output  gpio_out_17,
  output  gpio_out_18,
  output  gpio_out_19,
  output  gpio_out_20,
  output  gpio_out_21,
  output  gpio_out_22,
  output  gpio_out_23,
  output  gpio_out_24,
  output  gpio_out_25,
  output  gpio_out_26,
  output  gpio_out_27,
  output  gpio_out_28,
  output  gpio_out_29,
  output  gpio_out_30,
  output  gpio_out_31,
  input   gpio_in_0,
  input   gpio_in_1,
  input   gpio_in_2,
  input   gpio_in_3,
  input   gpio_in_4,
  input   gpio_in_5,
  input   gpio_in_6,
  input   gpio_in_7,
  input   gpio_in_8,
  input   gpio_in_9,
  input   gpio_in_10,
  input   gpio_in_11,
  input   gpio_in_12,
  input   gpio_in_13,
  input   gpio_in_14,
  input   gpio_in_15,
  input   gpio_in_16,
  input   gpio_in_17,
  input   gpio_in_18,
  input   gpio_in_19,
  input   gpio_in_20,
  input   gpio_in_21,
  input   gpio_in_22,
  input   gpio_in_23,
  input   gpio_in_24,
  input   gpio_in_25,
  input   gpio_in_26,
  input   gpio_in_27,
  input   gpio_in_28,
  input   gpio_in_29,
  input   gpio_in_30,
  input   gpio_in_31
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
  wire  dut_clock; // @[Chip.scala 41:21]
  wire  dut_io_pins_jtag_TCK_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_jtag_TMS_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_jtag_TDI_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_jtag_TDO_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_jtag_TDO_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_0_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_0_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_0_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_0_o_ie; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_1_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_1_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_1_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_1_o_ie; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_2_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_2_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_2_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_2_o_ie; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_3_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_3_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_3_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_3_o_ie; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_4_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_4_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_4_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_4_o_ie; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_5_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_5_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_5_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_5_o_ie; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_6_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_6_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_6_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_7_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_7_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_7_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_8_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_8_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_8_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_9_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_9_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_9_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_10_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_10_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_10_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_11_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_11_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_11_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_12_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_12_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_12_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_12_o_ie; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_13_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_13_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_13_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_13_o_ie; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_14_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_14_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_14_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_14_o_ie; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_15_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_15_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_15_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_15_o_ie; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_16_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_16_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_16_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_16_o_ie; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_17_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_17_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_17_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_17_o_ie; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_18_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_18_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_18_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_18_o_ie; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_19_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_19_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_19_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_19_o_ie; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_20_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_20_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_20_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_20_o_ie; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_21_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_21_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_21_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_21_o_ie; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_22_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_22_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_22_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_22_o_ie; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_23_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_23_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_23_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_23_o_ie; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_24_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_24_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_24_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_24_o_ie; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_25_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_25_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_25_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_26_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_26_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_26_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_27_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_27_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_27_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_28_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_28_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_28_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_29_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_29_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_29_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_30_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_30_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_30_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_31_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_31_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_gpio_pins_31_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_qspi_sck_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_qspi_dq_0_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_qspi_dq_0_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_qspi_dq_0_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_qspi_dq_0_o_ie; // @[Chip.scala 41:21]
  wire  dut_io_pins_qspi_dq_1_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_qspi_dq_1_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_qspi_dq_1_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_qspi_dq_1_o_ie; // @[Chip.scala 41:21]
  wire  dut_io_pins_qspi_dq_2_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_qspi_dq_2_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_qspi_dq_2_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_qspi_dq_2_o_ie; // @[Chip.scala 41:21]
  wire  dut_io_pins_qspi_dq_3_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_qspi_dq_3_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_qspi_dq_3_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_qspi_dq_3_o_ie; // @[Chip.scala 41:21]
  wire  dut_io_pins_qspi_cs_0_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_qspi_ram_sck_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_qspi_ram_dq_0_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_qspi_ram_dq_0_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_qspi_ram_dq_0_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_qspi_ram_dq_0_o_ie; // @[Chip.scala 41:21]
  wire  dut_io_pins_qspi_ram_dq_1_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_qspi_ram_dq_1_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_qspi_ram_dq_1_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_qspi_ram_dq_1_o_ie; // @[Chip.scala 41:21]
  wire  dut_io_pins_qspi_ram_dq_2_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_qspi_ram_dq_2_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_qspi_ram_dq_2_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_qspi_ram_dq_2_o_ie; // @[Chip.scala 41:21]
  wire  dut_io_pins_qspi_ram_dq_3_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_qspi_ram_dq_3_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_qspi_ram_dq_3_o_oe; // @[Chip.scala 41:21]
  wire  dut_io_pins_qspi_ram_dq_3_o_ie; // @[Chip.scala 41:21]
  wire  dut_io_pins_qspi_ram_cs_0_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_uart_rxd_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_uart_txd_o_oval; // @[Chip.scala 41:21]
  wire  dut_io_pins_aon_erst_n_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_pins_aon_lfextclk_i_ival; // @[Chip.scala 41:21]
  wire  dut_io_jtag_reset; // @[Chip.scala 41:21]
  wire  _T = ~rst_n; // @[Chip.scala 28:26]
  reg  clockToggleReg; // @[Chip.scala 29:33]
  reg [1:0] slowTick_value; // @[Counter.scala 62:40]
  wire  slowTick_wrap_wrap = slowTick_value == 2'h3; // @[Counter.scala 74:24]
  wire [1:0] _slowTick_wrap_value_T_1 = slowTick_value + 2'h1; // @[Counter.scala 78:24]
  MarmotCaravelPlatform dut ( // @[Chip.scala 41:21]
    .clock(dut_clock),
    .io_pins_jtag_TCK_i_ival(dut_io_pins_jtag_TCK_i_ival),
    .io_pins_jtag_TMS_i_ival(dut_io_pins_jtag_TMS_i_ival),
    .io_pins_jtag_TDI_i_ival(dut_io_pins_jtag_TDI_i_ival),
    .io_pins_jtag_TDO_o_oval(dut_io_pins_jtag_TDO_o_oval),
    .io_pins_jtag_TDO_o_oe(dut_io_pins_jtag_TDO_o_oe),
    .io_pins_gpio_pins_0_i_ival(dut_io_pins_gpio_pins_0_i_ival),
    .io_pins_gpio_pins_0_o_oval(dut_io_pins_gpio_pins_0_o_oval),
    .io_pins_gpio_pins_0_o_oe(dut_io_pins_gpio_pins_0_o_oe),
    .io_pins_gpio_pins_0_o_ie(dut_io_pins_gpio_pins_0_o_ie),
    .io_pins_gpio_pins_1_i_ival(dut_io_pins_gpio_pins_1_i_ival),
    .io_pins_gpio_pins_1_o_oval(dut_io_pins_gpio_pins_1_o_oval),
    .io_pins_gpio_pins_1_o_oe(dut_io_pins_gpio_pins_1_o_oe),
    .io_pins_gpio_pins_1_o_ie(dut_io_pins_gpio_pins_1_o_ie),
    .io_pins_gpio_pins_2_i_ival(dut_io_pins_gpio_pins_2_i_ival),
    .io_pins_gpio_pins_2_o_oval(dut_io_pins_gpio_pins_2_o_oval),
    .io_pins_gpio_pins_2_o_oe(dut_io_pins_gpio_pins_2_o_oe),
    .io_pins_gpio_pins_2_o_ie(dut_io_pins_gpio_pins_2_o_ie),
    .io_pins_gpio_pins_3_i_ival(dut_io_pins_gpio_pins_3_i_ival),
    .io_pins_gpio_pins_3_o_oval(dut_io_pins_gpio_pins_3_o_oval),
    .io_pins_gpio_pins_3_o_oe(dut_io_pins_gpio_pins_3_o_oe),
    .io_pins_gpio_pins_3_o_ie(dut_io_pins_gpio_pins_3_o_ie),
    .io_pins_gpio_pins_4_i_ival(dut_io_pins_gpio_pins_4_i_ival),
    .io_pins_gpio_pins_4_o_oval(dut_io_pins_gpio_pins_4_o_oval),
    .io_pins_gpio_pins_4_o_oe(dut_io_pins_gpio_pins_4_o_oe),
    .io_pins_gpio_pins_4_o_ie(dut_io_pins_gpio_pins_4_o_ie),
    .io_pins_gpio_pins_5_i_ival(dut_io_pins_gpio_pins_5_i_ival),
    .io_pins_gpio_pins_5_o_oval(dut_io_pins_gpio_pins_5_o_oval),
    .io_pins_gpio_pins_5_o_oe(dut_io_pins_gpio_pins_5_o_oe),
    .io_pins_gpio_pins_5_o_ie(dut_io_pins_gpio_pins_5_o_ie),
    .io_pins_gpio_pins_6_i_ival(dut_io_pins_gpio_pins_6_i_ival),
    .io_pins_gpio_pins_6_o_oval(dut_io_pins_gpio_pins_6_o_oval),
    .io_pins_gpio_pins_6_o_oe(dut_io_pins_gpio_pins_6_o_oe),
    .io_pins_gpio_pins_7_i_ival(dut_io_pins_gpio_pins_7_i_ival),
    .io_pins_gpio_pins_7_o_oval(dut_io_pins_gpio_pins_7_o_oval),
    .io_pins_gpio_pins_7_o_oe(dut_io_pins_gpio_pins_7_o_oe),
    .io_pins_gpio_pins_8_i_ival(dut_io_pins_gpio_pins_8_i_ival),
    .io_pins_gpio_pins_8_o_oval(dut_io_pins_gpio_pins_8_o_oval),
    .io_pins_gpio_pins_8_o_oe(dut_io_pins_gpio_pins_8_o_oe),
    .io_pins_gpio_pins_9_i_ival(dut_io_pins_gpio_pins_9_i_ival),
    .io_pins_gpio_pins_9_o_oval(dut_io_pins_gpio_pins_9_o_oval),
    .io_pins_gpio_pins_9_o_oe(dut_io_pins_gpio_pins_9_o_oe),
    .io_pins_gpio_pins_10_i_ival(dut_io_pins_gpio_pins_10_i_ival),
    .io_pins_gpio_pins_10_o_oval(dut_io_pins_gpio_pins_10_o_oval),
    .io_pins_gpio_pins_10_o_oe(dut_io_pins_gpio_pins_10_o_oe),
    .io_pins_gpio_pins_11_i_ival(dut_io_pins_gpio_pins_11_i_ival),
    .io_pins_gpio_pins_11_o_oval(dut_io_pins_gpio_pins_11_o_oval),
    .io_pins_gpio_pins_11_o_oe(dut_io_pins_gpio_pins_11_o_oe),
    .io_pins_gpio_pins_12_i_ival(dut_io_pins_gpio_pins_12_i_ival),
    .io_pins_gpio_pins_12_o_oval(dut_io_pins_gpio_pins_12_o_oval),
    .io_pins_gpio_pins_12_o_oe(dut_io_pins_gpio_pins_12_o_oe),
    .io_pins_gpio_pins_12_o_ie(dut_io_pins_gpio_pins_12_o_ie),
    .io_pins_gpio_pins_13_i_ival(dut_io_pins_gpio_pins_13_i_ival),
    .io_pins_gpio_pins_13_o_oval(dut_io_pins_gpio_pins_13_o_oval),
    .io_pins_gpio_pins_13_o_oe(dut_io_pins_gpio_pins_13_o_oe),
    .io_pins_gpio_pins_13_o_ie(dut_io_pins_gpio_pins_13_o_ie),
    .io_pins_gpio_pins_14_i_ival(dut_io_pins_gpio_pins_14_i_ival),
    .io_pins_gpio_pins_14_o_oval(dut_io_pins_gpio_pins_14_o_oval),
    .io_pins_gpio_pins_14_o_oe(dut_io_pins_gpio_pins_14_o_oe),
    .io_pins_gpio_pins_14_o_ie(dut_io_pins_gpio_pins_14_o_ie),
    .io_pins_gpio_pins_15_i_ival(dut_io_pins_gpio_pins_15_i_ival),
    .io_pins_gpio_pins_15_o_oval(dut_io_pins_gpio_pins_15_o_oval),
    .io_pins_gpio_pins_15_o_oe(dut_io_pins_gpio_pins_15_o_oe),
    .io_pins_gpio_pins_15_o_ie(dut_io_pins_gpio_pins_15_o_ie),
    .io_pins_gpio_pins_16_i_ival(dut_io_pins_gpio_pins_16_i_ival),
    .io_pins_gpio_pins_16_o_oval(dut_io_pins_gpio_pins_16_o_oval),
    .io_pins_gpio_pins_16_o_oe(dut_io_pins_gpio_pins_16_o_oe),
    .io_pins_gpio_pins_16_o_ie(dut_io_pins_gpio_pins_16_o_ie),
    .io_pins_gpio_pins_17_i_ival(dut_io_pins_gpio_pins_17_i_ival),
    .io_pins_gpio_pins_17_o_oval(dut_io_pins_gpio_pins_17_o_oval),
    .io_pins_gpio_pins_17_o_oe(dut_io_pins_gpio_pins_17_o_oe),
    .io_pins_gpio_pins_17_o_ie(dut_io_pins_gpio_pins_17_o_ie),
    .io_pins_gpio_pins_18_i_ival(dut_io_pins_gpio_pins_18_i_ival),
    .io_pins_gpio_pins_18_o_oval(dut_io_pins_gpio_pins_18_o_oval),
    .io_pins_gpio_pins_18_o_oe(dut_io_pins_gpio_pins_18_o_oe),
    .io_pins_gpio_pins_18_o_ie(dut_io_pins_gpio_pins_18_o_ie),
    .io_pins_gpio_pins_19_i_ival(dut_io_pins_gpio_pins_19_i_ival),
    .io_pins_gpio_pins_19_o_oval(dut_io_pins_gpio_pins_19_o_oval),
    .io_pins_gpio_pins_19_o_oe(dut_io_pins_gpio_pins_19_o_oe),
    .io_pins_gpio_pins_19_o_ie(dut_io_pins_gpio_pins_19_o_ie),
    .io_pins_gpio_pins_20_i_ival(dut_io_pins_gpio_pins_20_i_ival),
    .io_pins_gpio_pins_20_o_oval(dut_io_pins_gpio_pins_20_o_oval),
    .io_pins_gpio_pins_20_o_oe(dut_io_pins_gpio_pins_20_o_oe),
    .io_pins_gpio_pins_20_o_ie(dut_io_pins_gpio_pins_20_o_ie),
    .io_pins_gpio_pins_21_i_ival(dut_io_pins_gpio_pins_21_i_ival),
    .io_pins_gpio_pins_21_o_oval(dut_io_pins_gpio_pins_21_o_oval),
    .io_pins_gpio_pins_21_o_oe(dut_io_pins_gpio_pins_21_o_oe),
    .io_pins_gpio_pins_21_o_ie(dut_io_pins_gpio_pins_21_o_ie),
    .io_pins_gpio_pins_22_i_ival(dut_io_pins_gpio_pins_22_i_ival),
    .io_pins_gpio_pins_22_o_oval(dut_io_pins_gpio_pins_22_o_oval),
    .io_pins_gpio_pins_22_o_oe(dut_io_pins_gpio_pins_22_o_oe),
    .io_pins_gpio_pins_22_o_ie(dut_io_pins_gpio_pins_22_o_ie),
    .io_pins_gpio_pins_23_i_ival(dut_io_pins_gpio_pins_23_i_ival),
    .io_pins_gpio_pins_23_o_oval(dut_io_pins_gpio_pins_23_o_oval),
    .io_pins_gpio_pins_23_o_oe(dut_io_pins_gpio_pins_23_o_oe),
    .io_pins_gpio_pins_23_o_ie(dut_io_pins_gpio_pins_23_o_ie),
    .io_pins_gpio_pins_24_i_ival(dut_io_pins_gpio_pins_24_i_ival),
    .io_pins_gpio_pins_24_o_oval(dut_io_pins_gpio_pins_24_o_oval),
    .io_pins_gpio_pins_24_o_oe(dut_io_pins_gpio_pins_24_o_oe),
    .io_pins_gpio_pins_24_o_ie(dut_io_pins_gpio_pins_24_o_ie),
    .io_pins_gpio_pins_25_i_ival(dut_io_pins_gpio_pins_25_i_ival),
    .io_pins_gpio_pins_25_o_oval(dut_io_pins_gpio_pins_25_o_oval),
    .io_pins_gpio_pins_25_o_oe(dut_io_pins_gpio_pins_25_o_oe),
    .io_pins_gpio_pins_26_i_ival(dut_io_pins_gpio_pins_26_i_ival),
    .io_pins_gpio_pins_26_o_oval(dut_io_pins_gpio_pins_26_o_oval),
    .io_pins_gpio_pins_26_o_oe(dut_io_pins_gpio_pins_26_o_oe),
    .io_pins_gpio_pins_27_i_ival(dut_io_pins_gpio_pins_27_i_ival),
    .io_pins_gpio_pins_27_o_oval(dut_io_pins_gpio_pins_27_o_oval),
    .io_pins_gpio_pins_27_o_oe(dut_io_pins_gpio_pins_27_o_oe),
    .io_pins_gpio_pins_28_i_ival(dut_io_pins_gpio_pins_28_i_ival),
    .io_pins_gpio_pins_28_o_oval(dut_io_pins_gpio_pins_28_o_oval),
    .io_pins_gpio_pins_28_o_oe(dut_io_pins_gpio_pins_28_o_oe),
    .io_pins_gpio_pins_29_i_ival(dut_io_pins_gpio_pins_29_i_ival),
    .io_pins_gpio_pins_29_o_oval(dut_io_pins_gpio_pins_29_o_oval),
    .io_pins_gpio_pins_29_o_oe(dut_io_pins_gpio_pins_29_o_oe),
    .io_pins_gpio_pins_30_i_ival(dut_io_pins_gpio_pins_30_i_ival),
    .io_pins_gpio_pins_30_o_oval(dut_io_pins_gpio_pins_30_o_oval),
    .io_pins_gpio_pins_30_o_oe(dut_io_pins_gpio_pins_30_o_oe),
    .io_pins_gpio_pins_31_i_ival(dut_io_pins_gpio_pins_31_i_ival),
    .io_pins_gpio_pins_31_o_oval(dut_io_pins_gpio_pins_31_o_oval),
    .io_pins_gpio_pins_31_o_oe(dut_io_pins_gpio_pins_31_o_oe),
    .io_pins_qspi_sck_o_oval(dut_io_pins_qspi_sck_o_oval),
    .io_pins_qspi_dq_0_i_ival(dut_io_pins_qspi_dq_0_i_ival),
    .io_pins_qspi_dq_0_o_oval(dut_io_pins_qspi_dq_0_o_oval),
    .io_pins_qspi_dq_0_o_oe(dut_io_pins_qspi_dq_0_o_oe),
    .io_pins_qspi_dq_0_o_ie(dut_io_pins_qspi_dq_0_o_ie),
    .io_pins_qspi_dq_1_i_ival(dut_io_pins_qspi_dq_1_i_ival),
    .io_pins_qspi_dq_1_o_oval(dut_io_pins_qspi_dq_1_o_oval),
    .io_pins_qspi_dq_1_o_oe(dut_io_pins_qspi_dq_1_o_oe),
    .io_pins_qspi_dq_1_o_ie(dut_io_pins_qspi_dq_1_o_ie),
    .io_pins_qspi_dq_2_i_ival(dut_io_pins_qspi_dq_2_i_ival),
    .io_pins_qspi_dq_2_o_oval(dut_io_pins_qspi_dq_2_o_oval),
    .io_pins_qspi_dq_2_o_oe(dut_io_pins_qspi_dq_2_o_oe),
    .io_pins_qspi_dq_2_o_ie(dut_io_pins_qspi_dq_2_o_ie),
    .io_pins_qspi_dq_3_i_ival(dut_io_pins_qspi_dq_3_i_ival),
    .io_pins_qspi_dq_3_o_oval(dut_io_pins_qspi_dq_3_o_oval),
    .io_pins_qspi_dq_3_o_oe(dut_io_pins_qspi_dq_3_o_oe),
    .io_pins_qspi_dq_3_o_ie(dut_io_pins_qspi_dq_3_o_ie),
    .io_pins_qspi_cs_0_o_oval(dut_io_pins_qspi_cs_0_o_oval),
    .io_pins_qspi_ram_sck_o_oval(dut_io_pins_qspi_ram_sck_o_oval),
    .io_pins_qspi_ram_dq_0_i_ival(dut_io_pins_qspi_ram_dq_0_i_ival),
    .io_pins_qspi_ram_dq_0_o_oval(dut_io_pins_qspi_ram_dq_0_o_oval),
    .io_pins_qspi_ram_dq_0_o_oe(dut_io_pins_qspi_ram_dq_0_o_oe),
    .io_pins_qspi_ram_dq_0_o_ie(dut_io_pins_qspi_ram_dq_0_o_ie),
    .io_pins_qspi_ram_dq_1_i_ival(dut_io_pins_qspi_ram_dq_1_i_ival),
    .io_pins_qspi_ram_dq_1_o_oval(dut_io_pins_qspi_ram_dq_1_o_oval),
    .io_pins_qspi_ram_dq_1_o_oe(dut_io_pins_qspi_ram_dq_1_o_oe),
    .io_pins_qspi_ram_dq_1_o_ie(dut_io_pins_qspi_ram_dq_1_o_ie),
    .io_pins_qspi_ram_dq_2_i_ival(dut_io_pins_qspi_ram_dq_2_i_ival),
    .io_pins_qspi_ram_dq_2_o_oval(dut_io_pins_qspi_ram_dq_2_o_oval),
    .io_pins_qspi_ram_dq_2_o_oe(dut_io_pins_qspi_ram_dq_2_o_oe),
    .io_pins_qspi_ram_dq_2_o_ie(dut_io_pins_qspi_ram_dq_2_o_ie),
    .io_pins_qspi_ram_dq_3_i_ival(dut_io_pins_qspi_ram_dq_3_i_ival),
    .io_pins_qspi_ram_dq_3_o_oval(dut_io_pins_qspi_ram_dq_3_o_oval),
    .io_pins_qspi_ram_dq_3_o_oe(dut_io_pins_qspi_ram_dq_3_o_oe),
    .io_pins_qspi_ram_dq_3_o_ie(dut_io_pins_qspi_ram_dq_3_o_ie),
    .io_pins_qspi_ram_cs_0_o_oval(dut_io_pins_qspi_ram_cs_0_o_oval),
    .io_pins_uart_rxd_i_ival(dut_io_pins_uart_rxd_i_ival),
    .io_pins_uart_txd_o_oval(dut_io_pins_uart_txd_o_oval),
    .io_pins_aon_erst_n_i_ival(dut_io_pins_aon_erst_n_i_ival),
    .io_pins_aon_lfextclk_i_ival(dut_io_pins_aon_lfextclk_i_ival),
    .io_jtag_reset(dut_io_jtag_reset)
  );
  assign io_out_0 = 1'h0; // @[Chip.scala 48:15]
  assign io_out_1 = dut_io_pins_jtag_TDO_o_oval; // @[Chip.scala 52:15]
  assign io_out_2 = 1'h0; // @[Chip.scala 56:15]
  assign io_out_3 = 1'h0; // @[Chip.scala 61:15]
  assign io_out_4 = 1'h0; // @[Chip.scala 66:15]
  assign io_out_5 = 1'h0; // @[Chip.scala 82:15]
  assign io_out_6 = dut_io_pins_uart_txd_o_oval; // @[Chip.scala 87:15]
  assign io_out_7 = dut_io_pins_gpio_pins_24_o_oval; // @[Chip.scala 183:16]
  assign io_out_8 = dut_io_pins_qspi_cs_0_o_oval; // @[Chip.scala 95:16]
  assign io_out_9 = dut_io_pins_qspi_sck_o_oval; // @[Chip.scala 99:16]
  assign io_out_10 = dut_io_pins_qspi_dq_0_o_oval; // @[Chip.scala 103:16]
  assign io_out_11 = dut_io_pins_qspi_dq_1_o_oval; // @[Chip.scala 108:16]
  assign io_out_12 = dut_io_pins_qspi_dq_2_o_oval; // @[Chip.scala 113:16]
  assign io_out_13 = dut_io_pins_qspi_dq_3_o_oval; // @[Chip.scala 118:16]
  assign io_out_14 = dut_io_pins_gpio_pins_0_o_oval; // @[Chip.scala 165:23]
  assign io_out_15 = dut_io_pins_gpio_pins_1_o_oval; // @[Chip.scala 165:23]
  assign io_out_16 = dut_io_pins_gpio_pins_2_o_oval; // @[Chip.scala 165:23]
  assign io_out_17 = dut_io_pins_gpio_pins_3_o_oval; // @[Chip.scala 165:23]
  assign io_out_18 = dut_io_pins_gpio_pins_4_o_oval; // @[Chip.scala 165:23]
  assign io_out_19 = dut_io_pins_gpio_pins_5_o_oval; // @[Chip.scala 165:23]
  assign io_out_20 = dut_io_pins_qspi_ram_cs_0_o_oval; // @[Chip.scala 127:17]
  assign io_out_21 = dut_io_pins_qspi_ram_sck_o_oval; // @[Chip.scala 131:17]
  assign io_out_22 = dut_io_pins_qspi_ram_dq_0_o_oval; // @[Chip.scala 135:16]
  assign io_out_23 = dut_io_pins_qspi_ram_dq_1_o_oval; // @[Chip.scala 140:16]
  assign io_out_24 = dut_io_pins_qspi_ram_dq_2_o_oval; // @[Chip.scala 145:16]
  assign io_out_25 = dut_io_pins_qspi_ram_dq_3_o_oval; // @[Chip.scala 150:16]
  assign io_out_26 = dut_io_pins_gpio_pins_12_o_oval; // @[Chip.scala 177:23]
  assign io_out_27 = dut_io_pins_gpio_pins_13_o_oval; // @[Chip.scala 177:23]
  assign io_out_28 = dut_io_pins_gpio_pins_14_o_oval; // @[Chip.scala 177:23]
  assign io_out_29 = dut_io_pins_gpio_pins_15_o_oval; // @[Chip.scala 177:23]
  assign io_out_30 = dut_io_pins_gpio_pins_16_o_oval; // @[Chip.scala 177:23]
  assign io_out_31 = dut_io_pins_gpio_pins_17_o_oval; // @[Chip.scala 177:23]
  assign io_out_32 = dut_io_pins_gpio_pins_18_o_oval; // @[Chip.scala 177:23]
  assign io_out_33 = dut_io_pins_gpio_pins_19_o_oval; // @[Chip.scala 177:23]
  assign io_out_34 = dut_io_pins_gpio_pins_20_o_oval; // @[Chip.scala 177:23]
  assign io_out_35 = dut_io_pins_gpio_pins_21_o_oval; // @[Chip.scala 177:23]
  assign io_out_36 = dut_io_pins_gpio_pins_22_o_oval; // @[Chip.scala 177:23]
  assign io_out_37 = dut_io_pins_gpio_pins_23_o_oval; // @[Chip.scala 177:23]
  assign io_oeb_0 = 1'h1; // @[Chip.scala 49:15]
  assign io_oeb_1 = ~dut_io_pins_jtag_TDO_o_oe; // @[Chip.scala 53:18]
  assign io_oeb_2 = 1'h1; // @[Chip.scala 57:15]
  assign io_oeb_3 = 1'h1; // @[Chip.scala 62:15]
  assign io_oeb_4 = 1'h1; // @[Chip.scala 67:15]
  assign io_oeb_5 = 1'h1; // @[Chip.scala 83:15]
  assign io_oeb_6 = 1'h0; // @[Chip.scala 88:18]
  assign io_oeb_7 = ~dut_io_pins_gpio_pins_24_o_oe; // @[Chip.scala 184:19]
  assign io_oeb_8 = 1'h0; // @[Chip.scala 96:19]
  assign io_oeb_9 = 1'h0; // @[Chip.scala 100:19]
  assign io_oeb_10 = ~dut_io_pins_qspi_dq_0_o_oe; // @[Chip.scala 104:19]
  assign io_oeb_11 = ~dut_io_pins_qspi_dq_1_o_oe; // @[Chip.scala 109:19]
  assign io_oeb_12 = ~dut_io_pins_qspi_dq_2_o_oe; // @[Chip.scala 114:19]
  assign io_oeb_13 = ~dut_io_pins_qspi_dq_3_o_oe; // @[Chip.scala 119:19]
  assign io_oeb_14 = ~dut_io_pins_gpio_pins_0_o_oe; // @[Chip.scala 166:26]
  assign io_oeb_15 = ~dut_io_pins_gpio_pins_1_o_oe; // @[Chip.scala 166:26]
  assign io_oeb_16 = ~dut_io_pins_gpio_pins_2_o_oe; // @[Chip.scala 166:26]
  assign io_oeb_17 = ~dut_io_pins_gpio_pins_3_o_oe; // @[Chip.scala 166:26]
  assign io_oeb_18 = ~dut_io_pins_gpio_pins_4_o_oe; // @[Chip.scala 166:26]
  assign io_oeb_19 = ~dut_io_pins_gpio_pins_5_o_oe; // @[Chip.scala 166:26]
  assign io_oeb_20 = 1'h0; // @[Chip.scala 128:20]
  assign io_oeb_21 = 1'h0; // @[Chip.scala 132:20]
  assign io_oeb_22 = ~dut_io_pins_qspi_ram_dq_0_o_oe; // @[Chip.scala 136:19]
  assign io_oeb_23 = ~dut_io_pins_qspi_ram_dq_1_o_oe; // @[Chip.scala 141:19]
  assign io_oeb_24 = ~dut_io_pins_qspi_ram_dq_2_o_oe; // @[Chip.scala 146:19]
  assign io_oeb_25 = ~dut_io_pins_qspi_ram_dq_3_o_oe; // @[Chip.scala 151:19]
  assign io_oeb_26 = ~dut_io_pins_gpio_pins_12_o_oe; // @[Chip.scala 178:26]
  assign io_oeb_27 = ~dut_io_pins_gpio_pins_13_o_oe; // @[Chip.scala 178:26]
  assign io_oeb_28 = ~dut_io_pins_gpio_pins_14_o_oe; // @[Chip.scala 178:26]
  assign io_oeb_29 = ~dut_io_pins_gpio_pins_15_o_oe; // @[Chip.scala 178:26]
  assign io_oeb_30 = ~dut_io_pins_gpio_pins_16_o_oe; // @[Chip.scala 178:26]
  assign io_oeb_31 = ~dut_io_pins_gpio_pins_17_o_oe; // @[Chip.scala 178:26]
  assign io_oeb_32 = ~dut_io_pins_gpio_pins_18_o_oe; // @[Chip.scala 178:26]
  assign io_oeb_33 = ~dut_io_pins_gpio_pins_19_o_oe; // @[Chip.scala 178:26]
  assign io_oeb_34 = ~dut_io_pins_gpio_pins_20_o_oe; // @[Chip.scala 178:26]
  assign io_oeb_35 = ~dut_io_pins_gpio_pins_21_o_oe; // @[Chip.scala 178:26]
  assign io_oeb_36 = ~dut_io_pins_gpio_pins_22_o_oe; // @[Chip.scala 178:26]
  assign io_oeb_37 = ~dut_io_pins_gpio_pins_23_o_oe; // @[Chip.scala 178:26]
  assign gpio_out_0 = dut_io_pins_gpio_pins_0_o_oe & dut_io_pins_gpio_pins_0_o_oval; // @[Chip.scala 160:56]
  assign gpio_out_1 = dut_io_pins_gpio_pins_1_o_oe & dut_io_pins_gpio_pins_1_o_oval; // @[Chip.scala 160:56]
  assign gpio_out_2 = dut_io_pins_gpio_pins_2_o_oe & dut_io_pins_gpio_pins_2_o_oval; // @[Chip.scala 160:56]
  assign gpio_out_3 = dut_io_pins_gpio_pins_3_o_oe & dut_io_pins_gpio_pins_3_o_oval; // @[Chip.scala 160:56]
  assign gpio_out_4 = dut_io_pins_gpio_pins_4_o_oe & dut_io_pins_gpio_pins_4_o_oval; // @[Chip.scala 160:56]
  assign gpio_out_5 = dut_io_pins_gpio_pins_5_o_oe & dut_io_pins_gpio_pins_5_o_oval; // @[Chip.scala 160:56]
  assign gpio_out_6 = dut_io_pins_gpio_pins_6_o_oe & dut_io_pins_gpio_pins_6_o_oval; // @[Chip.scala 160:56]
  assign gpio_out_7 = dut_io_pins_gpio_pins_7_o_oe & dut_io_pins_gpio_pins_7_o_oval; // @[Chip.scala 160:56]
  assign gpio_out_8 = dut_io_pins_gpio_pins_8_o_oe & dut_io_pins_gpio_pins_8_o_oval; // @[Chip.scala 160:56]
  assign gpio_out_9 = dut_io_pins_gpio_pins_9_o_oe & dut_io_pins_gpio_pins_9_o_oval; // @[Chip.scala 160:56]
  assign gpio_out_10 = dut_io_pins_gpio_pins_10_o_oe & dut_io_pins_gpio_pins_10_o_oval; // @[Chip.scala 160:56]
  assign gpio_out_11 = dut_io_pins_gpio_pins_11_o_oe & dut_io_pins_gpio_pins_11_o_oval; // @[Chip.scala 160:56]
  assign gpio_out_12 = dut_io_pins_gpio_pins_12_o_oe & dut_io_pins_gpio_pins_12_o_oval; // @[Chip.scala 160:56]
  assign gpio_out_13 = dut_io_pins_gpio_pins_13_o_oe & dut_io_pins_gpio_pins_13_o_oval; // @[Chip.scala 160:56]
  assign gpio_out_14 = dut_io_pins_gpio_pins_14_o_oe & dut_io_pins_gpio_pins_14_o_oval; // @[Chip.scala 160:56]
  assign gpio_out_15 = dut_io_pins_gpio_pins_15_o_oe & dut_io_pins_gpio_pins_15_o_oval; // @[Chip.scala 160:56]
  assign gpio_out_16 = dut_io_pins_gpio_pins_16_o_oe & dut_io_pins_gpio_pins_16_o_oval; // @[Chip.scala 160:56]
  assign gpio_out_17 = dut_io_pins_gpio_pins_17_o_oe & dut_io_pins_gpio_pins_17_o_oval; // @[Chip.scala 160:56]
  assign gpio_out_18 = dut_io_pins_gpio_pins_18_o_oe & dut_io_pins_gpio_pins_18_o_oval; // @[Chip.scala 160:56]
  assign gpio_out_19 = dut_io_pins_gpio_pins_19_o_oe & dut_io_pins_gpio_pins_19_o_oval; // @[Chip.scala 160:56]
  assign gpio_out_20 = dut_io_pins_gpio_pins_20_o_oe & dut_io_pins_gpio_pins_20_o_oval; // @[Chip.scala 160:56]
  assign gpio_out_21 = dut_io_pins_gpio_pins_21_o_oe & dut_io_pins_gpio_pins_21_o_oval; // @[Chip.scala 160:56]
  assign gpio_out_22 = dut_io_pins_gpio_pins_22_o_oe & dut_io_pins_gpio_pins_22_o_oval; // @[Chip.scala 160:56]
  assign gpio_out_23 = dut_io_pins_gpio_pins_23_o_oe & dut_io_pins_gpio_pins_23_o_oval; // @[Chip.scala 160:56]
  assign gpio_out_24 = dut_io_pins_gpio_pins_24_o_oe & dut_io_pins_gpio_pins_24_o_oval; // @[Chip.scala 160:56]
  assign gpio_out_25 = dut_io_pins_gpio_pins_25_o_oe & dut_io_pins_gpio_pins_25_o_oval; // @[Chip.scala 160:56]
  assign gpio_out_26 = dut_io_pins_gpio_pins_26_o_oe & dut_io_pins_gpio_pins_26_o_oval; // @[Chip.scala 160:56]
  assign gpio_out_27 = dut_io_pins_gpio_pins_27_o_oe & dut_io_pins_gpio_pins_27_o_oval; // @[Chip.scala 160:56]
  assign gpio_out_28 = dut_io_pins_gpio_pins_28_o_oe & dut_io_pins_gpio_pins_28_o_oval; // @[Chip.scala 160:56]
  assign gpio_out_29 = dut_io_pins_gpio_pins_29_o_oe & dut_io_pins_gpio_pins_29_o_oval; // @[Chip.scala 160:56]
  assign gpio_out_30 = dut_io_pins_gpio_pins_30_o_oe & dut_io_pins_gpio_pins_30_o_oval; // @[Chip.scala 160:56]
  assign gpio_out_31 = dut_io_pins_gpio_pins_31_o_oe & dut_io_pins_gpio_pins_31_o_oval; // @[Chip.scala 160:56]
  assign dut_clock = clk;
  assign dut_io_pins_jtag_TCK_i_ival = io_in_4; // @[Chip.scala 68:45]
  assign dut_io_pins_jtag_TMS_i_ival = io_in_3; // @[Chip.scala 63:45]
  assign dut_io_pins_jtag_TDI_i_ival = io_in_2; // @[Chip.scala 58:45]
  assign dut_io_pins_gpio_pins_0_i_ival = io_in_14 & dut_io_pins_gpio_pins_0_o_ie; // @[Chip.scala 167:58]
  assign dut_io_pins_gpio_pins_1_i_ival = io_in_15 & dut_io_pins_gpio_pins_1_o_ie; // @[Chip.scala 167:58]
  assign dut_io_pins_gpio_pins_2_i_ival = io_in_16 & dut_io_pins_gpio_pins_2_o_ie; // @[Chip.scala 167:58]
  assign dut_io_pins_gpio_pins_3_i_ival = io_in_17 & dut_io_pins_gpio_pins_3_o_ie; // @[Chip.scala 167:58]
  assign dut_io_pins_gpio_pins_4_i_ival = io_in_18 & dut_io_pins_gpio_pins_4_o_ie; // @[Chip.scala 167:58]
  assign dut_io_pins_gpio_pins_5_i_ival = io_in_19 & dut_io_pins_gpio_pins_5_o_ie; // @[Chip.scala 167:58]
  assign dut_io_pins_gpio_pins_6_i_ival = gpio_in_6; // @[Chip.scala 172:41]
  assign dut_io_pins_gpio_pins_7_i_ival = gpio_in_7; // @[Chip.scala 172:41]
  assign dut_io_pins_gpio_pins_8_i_ival = gpio_in_8; // @[Chip.scala 172:41]
  assign dut_io_pins_gpio_pins_9_i_ival = gpio_in_9; // @[Chip.scala 172:41]
  assign dut_io_pins_gpio_pins_10_i_ival = gpio_in_10; // @[Chip.scala 172:41]
  assign dut_io_pins_gpio_pins_11_i_ival = gpio_in_11; // @[Chip.scala 172:41]
  assign dut_io_pins_gpio_pins_12_i_ival = io_in_26 & dut_io_pins_gpio_pins_12_o_ie; // @[Chip.scala 179:58]
  assign dut_io_pins_gpio_pins_13_i_ival = io_in_27 & dut_io_pins_gpio_pins_13_o_ie; // @[Chip.scala 179:58]
  assign dut_io_pins_gpio_pins_14_i_ival = io_in_28 & dut_io_pins_gpio_pins_14_o_ie; // @[Chip.scala 179:58]
  assign dut_io_pins_gpio_pins_15_i_ival = io_in_29 & dut_io_pins_gpio_pins_15_o_ie; // @[Chip.scala 179:58]
  assign dut_io_pins_gpio_pins_16_i_ival = io_in_30 & dut_io_pins_gpio_pins_16_o_ie; // @[Chip.scala 179:58]
  assign dut_io_pins_gpio_pins_17_i_ival = io_in_31 & dut_io_pins_gpio_pins_17_o_ie; // @[Chip.scala 179:58]
  assign dut_io_pins_gpio_pins_18_i_ival = io_in_32 & dut_io_pins_gpio_pins_18_o_ie; // @[Chip.scala 179:58]
  assign dut_io_pins_gpio_pins_19_i_ival = io_in_33 & dut_io_pins_gpio_pins_19_o_ie; // @[Chip.scala 179:58]
  assign dut_io_pins_gpio_pins_20_i_ival = io_in_34 & dut_io_pins_gpio_pins_20_o_ie; // @[Chip.scala 179:58]
  assign dut_io_pins_gpio_pins_21_i_ival = io_in_35 & dut_io_pins_gpio_pins_21_o_ie; // @[Chip.scala 179:58]
  assign dut_io_pins_gpio_pins_22_i_ival = io_in_36 & dut_io_pins_gpio_pins_22_o_ie; // @[Chip.scala 179:58]
  assign dut_io_pins_gpio_pins_23_i_ival = io_in_37 & dut_io_pins_gpio_pins_23_o_ie; // @[Chip.scala 179:58]
  assign dut_io_pins_gpio_pins_24_i_ival = io_in_7 & dut_io_pins_gpio_pins_24_o_ie; // @[Chip.scala 185:50]
  assign dut_io_pins_gpio_pins_25_i_ival = gpio_in_25; // @[Chip.scala 189:41]
  assign dut_io_pins_gpio_pins_26_i_ival = gpio_in_26; // @[Chip.scala 189:41]
  assign dut_io_pins_gpio_pins_27_i_ival = gpio_in_27; // @[Chip.scala 189:41]
  assign dut_io_pins_gpio_pins_28_i_ival = gpio_in_28; // @[Chip.scala 189:41]
  assign dut_io_pins_gpio_pins_29_i_ival = gpio_in_29; // @[Chip.scala 189:41]
  assign dut_io_pins_gpio_pins_30_i_ival = gpio_in_30; // @[Chip.scala 189:41]
  assign dut_io_pins_gpio_pins_31_i_ival = gpio_in_31; // @[Chip.scala 189:41]
  assign dut_io_pins_qspi_dq_0_i_ival = io_in_10 & dut_io_pins_qspi_dq_0_o_ie; // @[Chip.scala 105:48]
  assign dut_io_pins_qspi_dq_1_i_ival = io_in_11 & dut_io_pins_qspi_dq_1_o_ie; // @[Chip.scala 110:48]
  assign dut_io_pins_qspi_dq_2_i_ival = io_in_12 & dut_io_pins_qspi_dq_2_o_ie; // @[Chip.scala 115:48]
  assign dut_io_pins_qspi_dq_3_i_ival = io_in_13 & dut_io_pins_qspi_dq_3_o_ie; // @[Chip.scala 120:48]
  assign dut_io_pins_qspi_ram_dq_0_i_ival = io_in_22 & dut_io_pins_qspi_ram_dq_0_o_ie; // @[Chip.scala 137:52]
  assign dut_io_pins_qspi_ram_dq_1_i_ival = io_in_23 & dut_io_pins_qspi_ram_dq_1_o_ie; // @[Chip.scala 142:52]
  assign dut_io_pins_qspi_ram_dq_2_i_ival = io_in_24 & dut_io_pins_qspi_ram_dq_2_o_ie; // @[Chip.scala 147:52]
  assign dut_io_pins_qspi_ram_dq_3_i_ival = io_in_25 & dut_io_pins_qspi_ram_dq_3_o_ie; // @[Chip.scala 152:52]
  assign dut_io_pins_uart_rxd_i_ival = io_in_5; // @[Chip.scala 84:45]
  assign dut_io_pins_aon_erst_n_i_ival = rst_n; // @[Chip.scala 196:41]
  assign dut_io_pins_aon_lfextclk_i_ival = clockToggleReg; // @[Chip.scala 25:24 33:16]
  assign dut_io_jtag_reset = ~rst_n; // @[Chip.scala 71:26]
  always @(posedge clk) begin
    if (_T) begin // @[Chip.scala 29:33]
      clockToggleReg <= 1'h0; // @[Chip.scala 29:33]
    end else if (slowTick_wrap_wrap) begin // @[Chip.scala 32:21]
      clockToggleReg <= ~clockToggleReg; // @[Chip.scala 32:37]
    end
    if (_T) begin // @[Counter.scala 62:40]
      slowTick_value <= 2'h0; // @[Counter.scala 62:40]
    end else begin
      slowTick_value <= _slowTick_wrap_value_T_1;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  clockToggleReg = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  slowTick_value = _RAND_1[1:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module data_arrays_0(
  input  [9:0] RW0_addr,
  input        RW0_en,
  input        RW0_clk,
  input        RW0_wmode,
  input  [7:0] RW0_wdata_0,
  input  [7:0] RW0_wdata_1,
  input  [7:0] RW0_wdata_2,
  input  [7:0] RW0_wdata_3,
  input  [7:0] RW0_wdata_4,
  input  [7:0] RW0_wdata_5,
  input  [7:0] RW0_wdata_6,
  input  [7:0] RW0_wdata_7,
  output [7:0] RW0_rdata_0,
  output [7:0] RW0_rdata_1,
  output [7:0] RW0_rdata_2,
  output [7:0] RW0_rdata_3,
  output [7:0] RW0_rdata_4,
  output [7:0] RW0_rdata_5,
  output [7:0] RW0_rdata_6,
  output [7:0] RW0_rdata_7,
  input        RW0_wmask_0,
  input        RW0_wmask_1,
  input        RW0_wmask_2,
  input        RW0_wmask_3,
  input        RW0_wmask_4,
  input        RW0_wmask_5,
  input        RW0_wmask_6,
  input        RW0_wmask_7
);
  wire [9:0] data_arrays_0_ext_RW0_addr;
  wire  data_arrays_0_ext_RW0_en;
  wire  data_arrays_0_ext_RW0_clk;
  wire  data_arrays_0_ext_RW0_wmode;
  wire [63:0] data_arrays_0_ext_RW0_wdata;
  wire [63:0] data_arrays_0_ext_RW0_rdata;
  wire [7:0] data_arrays_0_ext_RW0_wmask;
  wire [31:0] _GEN_4 = {RW0_wdata_7,RW0_wdata_6,RW0_wdata_5,RW0_wdata_4};
  wire [31:0] _GEN_5 = {RW0_wdata_3,RW0_wdata_2,RW0_wdata_1,RW0_wdata_0};
  wire [3:0] _GEN_10 = {RW0_wmask_7,RW0_wmask_6,RW0_wmask_5,RW0_wmask_4};
  wire [3:0] _GEN_11 = {RW0_wmask_3,RW0_wmask_2,RW0_wmask_1,RW0_wmask_0};
  data_arrays_0_ext data_arrays_0_ext (
    .RW0_addr(data_arrays_0_ext_RW0_addr),
    .RW0_en(data_arrays_0_ext_RW0_en),
    .RW0_clk(data_arrays_0_ext_RW0_clk),
    .RW0_wmode(data_arrays_0_ext_RW0_wmode),
    .RW0_wdata(data_arrays_0_ext_RW0_wdata),
    .RW0_rdata(data_arrays_0_ext_RW0_rdata),
    .RW0_wmask(data_arrays_0_ext_RW0_wmask)
  );
  assign data_arrays_0_ext_RW0_clk = RW0_clk;
  assign data_arrays_0_ext_RW0_en = RW0_en;
  assign data_arrays_0_ext_RW0_addr = RW0_addr;
  assign RW0_rdata_0 = data_arrays_0_ext_RW0_rdata[7:0];
  assign RW0_rdata_1 = data_arrays_0_ext_RW0_rdata[15:8];
  assign RW0_rdata_2 = data_arrays_0_ext_RW0_rdata[23:16];
  assign RW0_rdata_3 = data_arrays_0_ext_RW0_rdata[31:24];
  assign RW0_rdata_4 = data_arrays_0_ext_RW0_rdata[39:32];
  assign RW0_rdata_5 = data_arrays_0_ext_RW0_rdata[47:40];
  assign RW0_rdata_6 = data_arrays_0_ext_RW0_rdata[55:48];
  assign RW0_rdata_7 = data_arrays_0_ext_RW0_rdata[63:56];
  assign data_arrays_0_ext_RW0_wmode = RW0_wmode;
  assign data_arrays_0_ext_RW0_wdata = {_GEN_4,_GEN_5};
  assign data_arrays_0_ext_RW0_wmask = {_GEN_10,_GEN_11};
endmodule
module tag_array(
  input  [5:0]  RW0_addr,
  input         RW0_en,
  input         RW0_clk,
  input         RW0_wmode,
  input  [20:0] RW0_wdata_0,
  input  [20:0] RW0_wdata_1,
  output [20:0] RW0_rdata_0,
  output [20:0] RW0_rdata_1,
  input         RW0_wmask_0,
  input         RW0_wmask_1
);
  wire [5:0] tag_array_ext_RW0_addr;
  wire  tag_array_ext_RW0_en;
  wire  tag_array_ext_RW0_clk;
  wire  tag_array_ext_RW0_wmode;
  wire [41:0] tag_array_ext_RW0_wdata;
  wire [41:0] tag_array_ext_RW0_rdata;
  wire [1:0] tag_array_ext_RW0_wmask;
  tag_array_ext tag_array_ext (
    .RW0_addr(tag_array_ext_RW0_addr),
    .RW0_en(tag_array_ext_RW0_en),
    .RW0_clk(tag_array_ext_RW0_clk),
    .RW0_wmode(tag_array_ext_RW0_wmode),
    .RW0_wdata(tag_array_ext_RW0_wdata),
    .RW0_rdata(tag_array_ext_RW0_rdata),
    .RW0_wmask(tag_array_ext_RW0_wmask)
  );
  assign tag_array_ext_RW0_clk = RW0_clk;
  assign tag_array_ext_RW0_en = RW0_en;
  assign tag_array_ext_RW0_addr = RW0_addr;
  assign RW0_rdata_0 = tag_array_ext_RW0_rdata[20:0];
  assign RW0_rdata_1 = tag_array_ext_RW0_rdata[41:21];
  assign tag_array_ext_RW0_wmode = RW0_wmode;
  assign tag_array_ext_RW0_wdata = {RW0_wdata_1,RW0_wdata_0};
  assign tag_array_ext_RW0_wmask = {RW0_wmask_1,RW0_wmask_0};
endmodule
module tag_array_0(
  input  [6:0]  RW0_addr,
  input         RW0_en,
  input         RW0_clk,
  input         RW0_wmode,
  input  [18:0] RW0_wdata_0,
  input  [18:0] RW0_wdata_1,
  output [18:0] RW0_rdata_0,
  output [18:0] RW0_rdata_1,
  input         RW0_wmask_0,
  input         RW0_wmask_1
);
  wire [6:0] tag_array_0_ext_RW0_addr;
  wire  tag_array_0_ext_RW0_en;
  wire  tag_array_0_ext_RW0_clk;
  wire  tag_array_0_ext_RW0_wmode;
  wire [37:0] tag_array_0_ext_RW0_wdata;
  wire [37:0] tag_array_0_ext_RW0_rdata;
  wire [1:0] tag_array_0_ext_RW0_wmask;
  tag_array_0_ext tag_array_0_ext (
    .RW0_addr(tag_array_0_ext_RW0_addr),
    .RW0_en(tag_array_0_ext_RW0_en),
    .RW0_clk(tag_array_0_ext_RW0_clk),
    .RW0_wmode(tag_array_0_ext_RW0_wmode),
    .RW0_wdata(tag_array_0_ext_RW0_wdata),
    .RW0_rdata(tag_array_0_ext_RW0_rdata),
    .RW0_wmask(tag_array_0_ext_RW0_wmask)
  );
  assign tag_array_0_ext_RW0_clk = RW0_clk;
  assign tag_array_0_ext_RW0_en = RW0_en;
  assign tag_array_0_ext_RW0_addr = RW0_addr;
  assign RW0_rdata_0 = tag_array_0_ext_RW0_rdata[18:0];
  assign RW0_rdata_1 = tag_array_0_ext_RW0_rdata[37:19];
  assign tag_array_0_ext_RW0_wmode = RW0_wmode;
  assign tag_array_0_ext_RW0_wdata = {RW0_wdata_1,RW0_wdata_0};
  assign tag_array_0_ext_RW0_wmask = {RW0_wmask_1,RW0_wmask_0};
endmodule
module data_arrays_0_0(
  input  [10:0] RW0_addr,
  input         RW0_en,
  input         RW0_clk,
  input         RW0_wmode,
  input  [31:0] RW0_wdata_0,
  input  [31:0] RW0_wdata_1,
  output [31:0] RW0_rdata_0,
  output [31:0] RW0_rdata_1,
  input         RW0_wmask_0,
  input         RW0_wmask_1
);
  wire [10:0] data_arrays_0_0_ext_RW0_addr;
  wire  data_arrays_0_0_ext_RW0_en;
  wire  data_arrays_0_0_ext_RW0_clk;
  wire  data_arrays_0_0_ext_RW0_wmode;
  wire [63:0] data_arrays_0_0_ext_RW0_wdata;
  wire [63:0] data_arrays_0_0_ext_RW0_rdata;
  wire [1:0] data_arrays_0_0_ext_RW0_wmask;
  data_arrays_0_0_ext data_arrays_0_0_ext (
    .RW0_addr(data_arrays_0_0_ext_RW0_addr),
    .RW0_en(data_arrays_0_0_ext_RW0_en),
    .RW0_clk(data_arrays_0_0_ext_RW0_clk),
    .RW0_wmode(data_arrays_0_0_ext_RW0_wmode),
    .RW0_wdata(data_arrays_0_0_ext_RW0_wdata),
    .RW0_rdata(data_arrays_0_0_ext_RW0_rdata),
    .RW0_wmask(data_arrays_0_0_ext_RW0_wmask)
  );
  assign data_arrays_0_0_ext_RW0_clk = RW0_clk;
  assign data_arrays_0_0_ext_RW0_en = RW0_en;
  assign data_arrays_0_0_ext_RW0_addr = RW0_addr;
  assign RW0_rdata_0 = data_arrays_0_0_ext_RW0_rdata[31:0];
  assign RW0_rdata_1 = data_arrays_0_0_ext_RW0_rdata[63:32];
  assign data_arrays_0_0_ext_RW0_wmode = RW0_wmode;
  assign data_arrays_0_0_ext_RW0_wdata = {RW0_wdata_1,RW0_wdata_0};
  assign data_arrays_0_0_ext_RW0_wmask = {RW0_wmask_1,RW0_wmask_0};
endmodule